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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
cd84d340 | 44 | static inline struct pci_dev *ctrl_dev(struct controller *ctrl) |
a0f018da | 45 | { |
cd84d340 | 46 | return ctrl->pcie->port; |
a0f018da | 47 | } |
1da177e4 | 48 | |
48fe3915 KK |
49 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
50 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
51 | |
52 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 53 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 54 | { |
48fe3915 | 55 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 56 | |
1da177e4 | 57 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 58 | pcie_isr(0, ctrl); |
1da177e4 | 59 | |
48fe3915 | 60 | init_timer(&ctrl->poll_timer); |
1da177e4 | 61 | if (!pciehp_poll_time) |
40730d10 | 62 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 63 | |
48fe3915 | 64 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
65 | } |
66 | ||
67 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 68 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 69 | { |
48fe3915 KK |
70 | /* Clamp to sane value */ |
71 | if ((sec <= 0) || (sec > 60)) | |
f7625980 | 72 | sec = 2; |
48fe3915 KK |
73 | |
74 | ctrl->poll_timer.function = &int_poll_timeout; | |
75 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
76 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
77 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
78 | } |
79 | ||
2aeeef11 KK |
80 | static inline int pciehp_request_irq(struct controller *ctrl) |
81 | { | |
f7a10e32 | 82 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
83 | |
84 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
85 | if (pciehp_poll_mode) { | |
86 | init_timer(&ctrl->poll_timer); | |
87 | start_int_poll_timer(ctrl, 10); | |
88 | return 0; | |
89 | } | |
90 | ||
91 | /* Installs the interrupt handler */ | |
92 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
93 | if (retval) | |
7f2feec1 TI |
94 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
95 | irq); | |
2aeeef11 KK |
96 | return retval; |
97 | } | |
98 | ||
99 | static inline void pciehp_free_irq(struct controller *ctrl) | |
100 | { | |
101 | if (pciehp_poll_mode) | |
102 | del_timer_sync(&ctrl->poll_timer); | |
103 | else | |
f7a10e32 | 104 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
105 | } |
106 | ||
563f1190 | 107 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a | 108 | { |
cd84d340 | 109 | struct pci_dev *pdev = ctrl_dev(ctrl); |
6592e02a | 110 | u16 slot_status; |
1a84b99c | 111 | int timeout = 1000; |
6592e02a | 112 | |
1a84b99c BH |
113 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
114 | if (slot_status & PCI_EXP_SLTSTA_CC) { | |
cd84d340 BH |
115 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
116 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 117 | return 1; |
820943b6 | 118 | } |
a5827f40 | 119 | while (timeout > 0) { |
66618bad KK |
120 | msleep(10); |
121 | timeout -= 10; | |
1a84b99c BH |
122 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
123 | if (slot_status & PCI_EXP_SLTSTA_CC) { | |
cd84d340 BH |
124 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
125 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 126 | return 1; |
820943b6 | 127 | } |
6592e02a KK |
128 | } |
129 | return 0; /* timeout */ | |
6592e02a KK |
130 | } |
131 | ||
563f1190 | 132 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 133 | { |
262303fe KK |
134 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
135 | unsigned long timeout = msecs_to_jiffies(msecs); | |
136 | int rc; | |
137 | ||
6592e02a KK |
138 | if (poll) |
139 | rc = pcie_poll_cmd(ctrl); | |
140 | else | |
d737bdc1 | 141 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 142 | if (!rc) |
7f2feec1 | 143 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
144 | } |
145 | ||
f4778364 KK |
146 | /** |
147 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 148 | * @ctrl: controller to which the command is issued |
f4778364 KK |
149 | * @cmd: command value written to slot control register |
150 | * @mask: bitmask of slot control register to be modified | |
151 | */ | |
6dae6202 | 152 | static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 153 | { |
cd84d340 | 154 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 155 | u16 slot_status; |
f4778364 | 156 | u16 slot_ctrl; |
1da177e4 | 157 | |
44ef4cef KK |
158 | mutex_lock(&ctrl->ctrl_lock); |
159 | ||
1a84b99c | 160 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 161 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
162 | if (!ctrl->no_cmd_complete) { |
163 | /* | |
164 | * After 1 sec and CMD_COMPLETED still not set, just | |
165 | * proceed forward to issue the next command according | |
166 | * to spec. Just print out the error message. | |
167 | */ | |
18b341b7 | 168 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
169 | } else if (!NO_CMD_CMPL(ctrl)) { |
170 | /* | |
f7625980 | 171 | * This controller seems to notify of command completed |
5808639b KK |
172 | * event even though it supports none of power |
173 | * controller, attention led, power led and EMI. | |
174 | */ | |
18b341b7 TI |
175 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
176 | "wait for command completed event.\n"); | |
5808639b KK |
177 | ctrl->no_cmd_complete = 0; |
178 | } else { | |
18b341b7 TI |
179 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
180 | "the controller is broken.\n"); | |
5808639b | 181 | } |
1da177e4 LT |
182 | } |
183 | ||
1a84b99c | 184 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
f4778364 | 185 | slot_ctrl &= ~mask; |
b7aa1f16 | 186 | slot_ctrl |= (cmd & mask); |
f4778364 | 187 | ctrl->cmd_busy = 1; |
2d32a9ae | 188 | smp_mb(); |
1a84b99c | 189 | pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 190 | |
44ef4cef KK |
191 | /* |
192 | * Wait for command completion. | |
193 | */ | |
1a84b99c | 194 | if (!ctrl->no_cmd_complete) { |
6592e02a KK |
195 | int poll = 0; |
196 | /* | |
197 | * if hotplug interrupt is not enabled or command | |
198 | * completed interrupt is not enabled, we need to poll | |
199 | * command completed event. | |
200 | */ | |
322162a7 KK |
201 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
202 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 203 | poll = 1; |
d737bdc1 | 204 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 205 | } |
44ef4cef | 206 | mutex_unlock(&ctrl->ctrl_lock); |
1da177e4 LT |
207 | } |
208 | ||
4e2ce405 | 209 | static bool check_link_active(struct controller *ctrl) |
f18e9625 | 210 | { |
cd84d340 | 211 | struct pci_dev *pdev = ctrl_dev(ctrl); |
4e2ce405 | 212 | u16 lnk_status; |
1a84b99c | 213 | bool ret; |
f18e9625 | 214 | |
1a84b99c | 215 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
4e2ce405 YL |
216 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
217 | ||
218 | if (ret) | |
219 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | |
220 | ||
221 | return ret; | |
f18e9625 KK |
222 | } |
223 | ||
bffe4f72 | 224 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
f18e9625 KK |
225 | { |
226 | int timeout = 1000; | |
227 | ||
bffe4f72 | 228 | if (check_link_active(ctrl) == active) |
f18e9625 KK |
229 | return; |
230 | while (timeout > 0) { | |
231 | msleep(10); | |
232 | timeout -= 10; | |
bffe4f72 | 233 | if (check_link_active(ctrl) == active) |
f18e9625 KK |
234 | return; |
235 | } | |
bffe4f72 YL |
236 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
237 | active ? "set" : "cleared"); | |
238 | } | |
239 | ||
240 | static void pcie_wait_link_active(struct controller *ctrl) | |
241 | { | |
242 | __pcie_wait_link_active(ctrl, true); | |
243 | } | |
244 | ||
245 | static void pcie_wait_link_not_active(struct controller *ctrl) | |
246 | { | |
247 | __pcie_wait_link_active(ctrl, false); | |
f18e9625 KK |
248 | } |
249 | ||
2f5d8e4f YL |
250 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
251 | { | |
252 | u32 l; | |
253 | int count = 0; | |
254 | int delay = 1000, step = 20; | |
255 | bool found = false; | |
256 | ||
257 | do { | |
258 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
259 | count++; | |
260 | ||
261 | if (found) | |
262 | break; | |
263 | ||
264 | msleep(step); | |
265 | delay -= step; | |
266 | } while (delay > 0); | |
267 | ||
268 | if (count > 1 && pciehp_debug) | |
269 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
270 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
271 | PCI_FUNC(devfn), count, step, l); | |
272 | ||
273 | return found; | |
274 | } | |
275 | ||
82a9e79e | 276 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 277 | { |
cd84d340 | 278 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1a84b99c | 279 | bool found; |
1da177e4 | 280 | u16 lnk_status; |
1da177e4 | 281 | |
f18e9625 KK |
282 | /* |
283 | * Data Link Layer Link Active Reporting must be capable for | |
284 | * hot-plug capable downstream port. But old controller might | |
285 | * not implement it. In this case, we wait for 1000 ms. | |
286 | */ | |
0cab0841 | 287 | if (ctrl->link_active_reporting) |
f18e9625 | 288 | pcie_wait_link_active(ctrl); |
0cab0841 | 289 | else |
f18e9625 KK |
290 | msleep(1000); |
291 | ||
2f5d8e4f YL |
292 | /* wait 100ms before read pci conf, and try in 1s */ |
293 | msleep(100); | |
294 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
295 | PCI_DEVFN(0, 0)); | |
0027cb3e | 296 | |
1a84b99c | 297 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
7f2feec1 | 298 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
299 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
300 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 301 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1a84b99c | 302 | return -1; |
1da177e4 LT |
303 | } |
304 | ||
fdbd3ce9 YL |
305 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
306 | ||
1a84b99c BH |
307 | if (!found) |
308 | return -1; | |
2f5d8e4f | 309 | |
1a84b99c | 310 | return 0; |
1da177e4 LT |
311 | } |
312 | ||
7f822999 YL |
313 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
314 | { | |
cd84d340 | 315 | struct pci_dev *pdev = ctrl_dev(ctrl); |
7f822999 | 316 | u16 lnk_ctrl; |
7f822999 | 317 | |
1a84b99c | 318 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); |
7f822999 YL |
319 | |
320 | if (enable) | |
321 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; | |
322 | else | |
323 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; | |
324 | ||
1a84b99c | 325 | pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); |
7f822999 | 326 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); |
1a84b99c | 327 | return 0; |
7f822999 YL |
328 | } |
329 | ||
330 | static int pciehp_link_enable(struct controller *ctrl) | |
331 | { | |
332 | return __pciehp_link_set(ctrl, true); | |
333 | } | |
334 | ||
335 | static int pciehp_link_disable(struct controller *ctrl) | |
336 | { | |
337 | return __pciehp_link_set(ctrl, false); | |
338 | } | |
339 | ||
6dae6202 | 340 | void pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 341 | { |
48fe3915 | 342 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 343 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 344 | u16 slot_ctrl; |
1da177e4 | 345 | |
1a84b99c | 346 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
347 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
348 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 349 | |
e7b4f0d7 BH |
350 | switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { |
351 | case PCI_EXP_SLTCTL_ATTN_IND_ON: | |
1da177e4 LT |
352 | *status = 1; /* On */ |
353 | break; | |
e7b4f0d7 | 354 | case PCI_EXP_SLTCTL_ATTN_IND_BLINK: |
1da177e4 LT |
355 | *status = 2; /* Blink */ |
356 | break; | |
e7b4f0d7 | 357 | case PCI_EXP_SLTCTL_ATTN_IND_OFF: |
1da177e4 LT |
358 | *status = 0; /* Off */ |
359 | break; | |
360 | default: | |
361 | *status = 0xFF; | |
362 | break; | |
363 | } | |
1da177e4 LT |
364 | } |
365 | ||
6dae6202 | 366 | void pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 367 | { |
48fe3915 | 368 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 369 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 370 | u16 slot_ctrl; |
1da177e4 | 371 | |
1a84b99c | 372 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
373 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
374 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 375 | |
e7b4f0d7 BH |
376 | switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { |
377 | case PCI_EXP_SLTCTL_PWR_ON: | |
378 | *status = 1; /* On */ | |
1da177e4 | 379 | break; |
e7b4f0d7 BH |
380 | case PCI_EXP_SLTCTL_PWR_OFF: |
381 | *status = 0; /* Off */ | |
1da177e4 LT |
382 | break; |
383 | default: | |
384 | *status = 0xFF; | |
385 | break; | |
386 | } | |
1da177e4 LT |
387 | } |
388 | ||
6dae6202 | 389 | void pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 390 | { |
1a84b99c | 391 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 392 | u16 slot_status; |
1da177e4 | 393 | |
1a84b99c | 394 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 395 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
396 | } |
397 | ||
6dae6202 | 398 | void pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 399 | { |
1a84b99c | 400 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 401 | u16 slot_status; |
1da177e4 | 402 | |
1a84b99c | 403 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 404 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
405 | } |
406 | ||
82a9e79e | 407 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 408 | { |
1a84b99c | 409 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 410 | u16 slot_status; |
1da177e4 | 411 | |
1a84b99c | 412 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 413 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
414 | } |
415 | ||
6dae6202 | 416 | void pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 417 | { |
48fe3915 | 418 | struct controller *ctrl = slot->ctrl; |
f4778364 | 419 | u16 slot_cmd; |
1da177e4 | 420 | |
af9ab791 BH |
421 | if (!ATTN_LED(ctrl)) |
422 | return; | |
423 | ||
1da177e4 | 424 | switch (value) { |
445f7985 | 425 | case 0 : /* turn off */ |
e7b4f0d7 | 426 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; |
445f7985 KK |
427 | break; |
428 | case 1: /* turn on */ | |
e7b4f0d7 | 429 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; |
445f7985 KK |
430 | break; |
431 | case 2: /* turn blink */ | |
e7b4f0d7 | 432 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; |
445f7985 KK |
433 | break; |
434 | default: | |
6dae6202 | 435 | return; |
1da177e4 | 436 | } |
1518c17a KK |
437 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
438 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
e7b4f0d7 | 439 | pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); |
1da177e4 LT |
440 | } |
441 | ||
82a9e79e | 442 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 443 | { |
48fe3915 | 444 | struct controller *ctrl = slot->ctrl; |
71ad556d | 445 | |
af9ab791 BH |
446 | if (!PWR_LED(ctrl)) |
447 | return; | |
448 | ||
e7b4f0d7 | 449 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC); |
1518c17a | 450 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
451 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
452 | PCI_EXP_SLTCTL_PWR_IND_ON); | |
1da177e4 LT |
453 | } |
454 | ||
82a9e79e | 455 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 456 | { |
48fe3915 | 457 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 458 | |
af9ab791 BH |
459 | if (!PWR_LED(ctrl)) |
460 | return; | |
461 | ||
e7b4f0d7 | 462 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC); |
1518c17a | 463 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
464 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
465 | PCI_EXP_SLTCTL_PWR_IND_OFF); | |
1da177e4 LT |
466 | } |
467 | ||
82a9e79e | 468 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 469 | { |
48fe3915 | 470 | struct controller *ctrl = slot->ctrl; |
71ad556d | 471 | |
af9ab791 BH |
472 | if (!PWR_LED(ctrl)) |
473 | return; | |
474 | ||
e7b4f0d7 | 475 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC); |
1518c17a | 476 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
477 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
478 | PCI_EXP_SLTCTL_PWR_IND_BLINK); | |
1da177e4 LT |
479 | } |
480 | ||
82a9e79e | 481 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 482 | { |
48fe3915 | 483 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 484 | struct pci_dev *pdev = ctrl_dev(ctrl); |
f4778364 | 485 | u16 slot_status; |
1a84b99c | 486 | int retval; |
1da177e4 | 487 | |
5a49f203 | 488 | /* Clear sticky power-fault bit from previous power failures */ |
1a84b99c | 489 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
2f2ed41c BH |
490 | if (slot_status & PCI_EXP_SLTSTA_PFD) |
491 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
492 | PCI_EXP_SLTSTA_PFD); | |
5651c48c | 493 | ctrl->power_fault_detected = 0; |
1da177e4 | 494 | |
e7b4f0d7 | 495 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); |
1518c17a | 496 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
497 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
498 | PCI_EXP_SLTCTL_PWR_ON); | |
1da177e4 | 499 | |
2debd928 YL |
500 | retval = pciehp_link_enable(ctrl); |
501 | if (retval) | |
502 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); | |
503 | ||
1da177e4 LT |
504 | return retval; |
505 | } | |
506 | ||
6dae6202 | 507 | void pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 508 | { |
48fe3915 | 509 | struct controller *ctrl = slot->ctrl; |
f1050a35 | 510 | |
2debd928 YL |
511 | /* Disable the link at first */ |
512 | pciehp_link_disable(ctrl); | |
513 | /* wait the link is down */ | |
514 | if (ctrl->link_active_reporting) | |
515 | pcie_wait_link_not_active(ctrl); | |
516 | else | |
517 | msleep(1000); | |
518 | ||
e7b4f0d7 | 519 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); |
1518c17a | 520 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
521 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
522 | PCI_EXP_SLTCTL_PWR_OFF); | |
1da177e4 LT |
523 | } |
524 | ||
48fe3915 | 525 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 526 | { |
48fe3915 | 527 | struct controller *ctrl = (struct controller *)dev_id; |
cd84d340 | 528 | struct pci_dev *pdev = ctrl_dev(ctrl); |
8720d27d | 529 | struct slot *slot = ctrl->slot; |
c6b069e9 | 530 | u16 detected, intr_loc; |
1da177e4 | 531 | |
c6b069e9 KK |
532 | /* |
533 | * In order to guarantee that all interrupt events are | |
534 | * serviced, we need to re-inspect Slot Status register after | |
535 | * clearing what is presumed to be the last pending interrupt. | |
536 | */ | |
537 | intr_loc = 0; | |
538 | do { | |
1a84b99c | 539 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected); |
1da177e4 | 540 | |
322162a7 KK |
541 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
542 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
543 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 544 | detected &= ~intr_loc; |
c6b069e9 KK |
545 | intr_loc |= detected; |
546 | if (!intr_loc) | |
1da177e4 | 547 | return IRQ_NONE; |
1a84b99c BH |
548 | if (detected) |
549 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
550 | intr_loc); | |
c6b069e9 | 551 | } while (detected); |
71ad556d | 552 | |
7f2feec1 | 553 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 554 | |
c6b069e9 | 555 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 556 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 557 | ctrl->cmd_busy = 0; |
2d32a9ae | 558 | smp_mb(); |
d737bdc1 | 559 | wake_up(&ctrl->queue); |
1da177e4 LT |
560 | } |
561 | ||
322162a7 | 562 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
563 | return IRQ_HANDLED; |
564 | ||
c6b069e9 | 565 | /* Check MRL Sensor Changed */ |
322162a7 | 566 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 567 | pciehp_handle_switch_change(slot); |
48fe3915 | 568 | |
c6b069e9 | 569 | /* Check Attention Button Pressed */ |
322162a7 | 570 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 571 | pciehp_handle_attention_button(slot); |
48fe3915 | 572 | |
c6b069e9 | 573 | /* Check Presence Detect Changed */ |
322162a7 | 574 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 575 | pciehp_handle_presence_change(slot); |
48fe3915 | 576 | |
c6b069e9 | 577 | /* Check Power Fault Detected */ |
99f0169c KK |
578 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
579 | ctrl->power_fault_detected = 1; | |
8720d27d | 580 | pciehp_handle_power_fault(slot); |
99f0169c | 581 | } |
1da177e4 LT |
582 | return IRQ_HANDLED; |
583 | } | |
584 | ||
6dae6202 | 585 | void pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 586 | { |
c27fb883 | 587 | u16 cmd, mask; |
1da177e4 | 588 | |
5651c48c KK |
589 | /* |
590 | * TBD: Power fault detected software notification support. | |
591 | * | |
592 | * Power fault detected software notification is not enabled | |
593 | * now, because it caused power fault detected interrupt storm | |
594 | * on some machines. On those machines, power fault detected | |
595 | * bit in the slot status register was set again immediately | |
596 | * when it is cleared in the interrupt service routine, and | |
597 | * next power fault detected interrupt was notified again. | |
598 | */ | |
322162a7 | 599 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 600 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 601 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 602 | if (MRL_SENS(ctrl)) |
322162a7 | 603 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 604 | if (!pciehp_poll_mode) |
322162a7 | 605 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 606 | |
322162a7 KK |
607 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
608 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
609 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 | 610 | |
6dae6202 | 611 | pcie_write_cmd(ctrl, cmd, mask); |
c4635eb0 KK |
612 | } |
613 | ||
614 | static void pcie_disable_notification(struct controller *ctrl) | |
615 | { | |
616 | u16 mask; | |
6dae6202 | 617 | |
322162a7 KK |
618 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
619 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
620 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
621 | PCI_EXP_SLTCTL_DLLSCE); | |
6dae6202 | 622 | pcie_write_cmd(ctrl, 0, mask); |
c4635eb0 KK |
623 | } |
624 | ||
2e35afae AW |
625 | /* |
626 | * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary | |
627 | * bus reset of the bridge, but if the slot supports surprise removal we need | |
628 | * to disable presence detection around the bus reset and clear any spurious | |
629 | * events after. | |
630 | */ | |
631 | int pciehp_reset_slot(struct slot *slot, int probe) | |
632 | { | |
633 | struct controller *ctrl = slot->ctrl; | |
cd84d340 | 634 | struct pci_dev *pdev = ctrl_dev(ctrl); |
2e35afae AW |
635 | |
636 | if (probe) | |
637 | return 0; | |
638 | ||
639 | if (HP_SUPR_RM(ctrl)) { | |
640 | pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE); | |
641 | if (pciehp_poll_mode) | |
642 | del_timer_sync(&ctrl->poll_timer); | |
643 | } | |
644 | ||
645 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); | |
646 | ||
647 | if (HP_SUPR_RM(ctrl)) { | |
cd84d340 BH |
648 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
649 | PCI_EXP_SLTSTA_PDC); | |
2e35afae AW |
650 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE); |
651 | if (pciehp_poll_mode) | |
652 | int_poll_timeout(ctrl->poll_timer.data); | |
653 | } | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
dbc7e1e5 | 658 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
659 | { |
660 | if (pciehp_request_irq(ctrl)) | |
661 | return -1; | |
6dae6202 | 662 | pcie_enable_notification(ctrl); |
dbc7e1e5 | 663 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
664 | return 0; |
665 | } | |
666 | ||
667 | static void pcie_shutdown_notification(struct controller *ctrl) | |
668 | { | |
dbc7e1e5 EB |
669 | if (ctrl->notification_enabled) { |
670 | pcie_disable_notification(ctrl); | |
671 | pciehp_free_irq(ctrl); | |
672 | ctrl->notification_enabled = 0; | |
673 | } | |
c4635eb0 KK |
674 | } |
675 | ||
c4635eb0 KK |
676 | static int pcie_init_slot(struct controller *ctrl) |
677 | { | |
678 | struct slot *slot; | |
679 | ||
680 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
681 | if (!slot) | |
682 | return -ENOMEM; | |
683 | ||
d8537548 | 684 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
c2be6f93 YW |
685 | if (!slot->wq) |
686 | goto abort; | |
687 | ||
c4635eb0 | 688 | slot->ctrl = ctrl; |
c4635eb0 KK |
689 | mutex_init(&slot->lock); |
690 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
8720d27d | 691 | ctrl->slot = slot; |
1da177e4 | 692 | return 0; |
c2be6f93 YW |
693 | abort: |
694 | kfree(slot); | |
695 | return -ENOMEM; | |
1da177e4 | 696 | } |
08e7a7d2 | 697 | |
c4635eb0 KK |
698 | static void pcie_cleanup_slot(struct controller *ctrl) |
699 | { | |
8720d27d | 700 | struct slot *slot = ctrl->slot; |
c4635eb0 | 701 | cancel_delayed_work(&slot->work); |
c2be6f93 | 702 | destroy_workqueue(slot->wq); |
c4635eb0 KK |
703 | kfree(slot); |
704 | } | |
705 | ||
2aeeef11 | 706 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 707 | { |
2aeeef11 KK |
708 | int i; |
709 | u16 reg16; | |
385e2491 | 710 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 711 | |
2aeeef11 KK |
712 | if (!pciehp_debug) |
713 | return; | |
08e7a7d2 | 714 | |
7f2feec1 TI |
715 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
716 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
717 | pci_name(pdev), pdev->irq); | |
718 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
719 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
720 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
721 | pdev->subsystem_device); | |
722 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
723 | pdev->subsystem_vendor); | |
1518c17a KK |
724 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
725 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
726 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
727 | if (!pci_resource_len(pdev, i)) | |
728 | continue; | |
e1944c6b BH |
729 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
730 | i, &pdev->resource[i]); | |
08e7a7d2 | 731 | } |
7f2feec1 | 732 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 733 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
734 | ctrl_info(ctrl, " Attention Button : %3s\n", |
735 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
736 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
737 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
738 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
739 | MRL_SENS(ctrl) ? "yes" : "no"); | |
740 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
741 | ATTN_LED(ctrl) ? "yes" : "no"); | |
742 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
743 | PWR_LED(ctrl) ? "yes" : "no"); | |
744 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
745 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
746 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
747 | EMI(ctrl) ? "yes" : "no"); | |
748 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
749 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
cd84d340 | 750 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 751 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
cd84d340 | 752 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 753 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 754 | } |
08e7a7d2 | 755 | |
afe2478f BH |
756 | #define FLAG(x,y) (((x) & (y)) ? '+' : '-') |
757 | ||
c4635eb0 | 758 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 759 | { |
c4635eb0 | 760 | struct controller *ctrl; |
f18e9625 | 761 | u32 slot_cap, link_cap; |
2aeeef11 | 762 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 763 | |
c4635eb0 KK |
764 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
765 | if (!ctrl) { | |
18b341b7 | 766 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
767 | goto abort; |
768 | } | |
f7a10e32 | 769 | ctrl->pcie = dev; |
1a84b99c | 770 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); |
2aeeef11 | 771 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 772 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 773 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 774 | dbg_ctrl(ctrl); |
5808639b KK |
775 | /* |
776 | * Controller doesn't notify of command completion if the "No | |
777 | * Command Completed Support" bit is set in Slot Capability | |
778 | * register or the controller supports none of power | |
779 | * controller, attention led, power led and EMI. | |
780 | */ | |
781 | if (NO_CMD_CMPL(ctrl) || | |
782 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
783 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 784 | |
f18e9625 | 785 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
1a84b99c | 786 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); |
322162a7 | 787 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
788 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
789 | ctrl->link_active_reporting = 1; | |
790 | } | |
791 | ||
c4635eb0 | 792 | /* Clear all remaining event bits in Slot Status register */ |
df72648c BH |
793 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
794 | PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | | |
795 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
796 | PCI_EXP_SLTSTA_CC); | |
08e7a7d2 | 797 | |
f7625980 | 798 | /* Disable software notification */ |
c4635eb0 | 799 | pcie_disable_notification(ctrl); |
ecdde939 | 800 | |
afe2478f BH |
801 | ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n", |
802 | (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, | |
803 | FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), | |
804 | FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), | |
805 | FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), | |
806 | FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), | |
807 | FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), | |
808 | FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), | |
809 | FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), | |
810 | FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); | |
c4635eb0 KK |
811 | |
812 | if (pcie_init_slot(ctrl)) | |
813 | goto abort_ctrl; | |
2aeeef11 | 814 | |
c4635eb0 KK |
815 | return ctrl; |
816 | ||
c4635eb0 KK |
817 | abort_ctrl: |
818 | kfree(ctrl); | |
08e7a7d2 | 819 | abort: |
c4635eb0 KK |
820 | return NULL; |
821 | } | |
822 | ||
82a9e79e | 823 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
824 | { |
825 | pcie_shutdown_notification(ctrl); | |
826 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 827 | kfree(ctrl); |
08e7a7d2 | 828 | } |