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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
1da177e4 LT |
34 | #include "../pci.h" |
35 | #include "pciehp.h" | |
36 | ||
37 | #ifdef DEBUG | |
38 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ | |
39 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ | |
40 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ | |
41 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ | |
42 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) | |
43 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) | |
44 | /* Redefine this flagword to set debug level */ | |
45 | #define DEBUG_LEVEL DBG_K_STANDARD | |
46 | ||
47 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; | |
48 | ||
49 | #define DBG_PRINT( dbg_flags, args... ) \ | |
50 | do { \ | |
51 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ | |
52 | { \ | |
53 | int len; \ | |
54 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ | |
55 | __FILE__, __LINE__, __FUNCTION__ ); \ | |
56 | sprintf( __dbg_str_buf + len, args ); \ | |
57 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ | |
58 | } \ | |
59 | } while (0) | |
60 | ||
61 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); | |
62 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); | |
63 | #else | |
64 | #define DEFINE_DBG_BUFFER | |
65 | #define DBG_ENTER_ROUTINE | |
66 | #define DBG_LEAVE_ROUTINE | |
67 | #endif /* DEBUG */ | |
68 | ||
69 | struct ctrl_reg { | |
70 | u8 cap_id; | |
71 | u8 nxt_ptr; | |
72 | u16 cap_reg; | |
73 | u32 dev_cap; | |
74 | u16 dev_ctrl; | |
75 | u16 dev_status; | |
76 | u32 lnk_cap; | |
77 | u16 lnk_ctrl; | |
78 | u16 lnk_status; | |
79 | u32 slot_cap; | |
80 | u16 slot_ctrl; | |
81 | u16 slot_status; | |
82 | u16 root_ctrl; | |
83 | u16 rsvp; | |
84 | u32 root_status; | |
85 | } __attribute__ ((packed)); | |
86 | ||
87 | /* offsets to the controller registers based on the above structure layout */ | |
88 | enum ctrl_offsets { | |
89 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
90 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
91 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
92 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
93 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
94 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
95 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
96 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
97 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
98 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
99 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
100 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
101 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
102 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
103 | }; | |
104 | static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */ | |
105 | ||
8b245e45 DS |
106 | #define PCIE_CAP_ID(cb) ( cb + PCIECAPID ) |
107 | #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR ) | |
108 | #define CAP_REG(cb) ( cb + CAPREG ) | |
109 | #define DEV_CAP(cb) ( cb + DEVCAP ) | |
110 | #define DEV_CTRL(cb) ( cb + DEVCTRL ) | |
111 | #define DEV_STATUS(cb) ( cb + DEVSTATUS ) | |
112 | #define LNK_CAP(cb) ( cb + LNKCAP ) | |
113 | #define LNK_CTRL(cb) ( cb + LNKCTRL ) | |
114 | #define LNK_STATUS(cb) ( cb + LNKSTATUS ) | |
115 | #define SLOT_CAP(cb) ( cb + SLOTCAP ) | |
116 | #define SLOT_CTRL(cb) ( cb + SLOTCTRL ) | |
117 | #define SLOT_STATUS(cb) ( cb + SLOTSTATUS ) | |
118 | #define ROOT_CTRL(cb) ( cb + ROOTCTRL ) | |
119 | #define ROOT_STATUS(cb) ( cb + ROOTSTATUS ) | |
1da177e4 LT |
120 | |
121 | #define hp_register_read_word(pdev, reg , value) \ | |
122 | pci_read_config_word(pdev, reg, &value) | |
123 | ||
124 | #define hp_register_read_dword(pdev, reg , value) \ | |
125 | pci_read_config_dword(pdev, reg, &value) | |
126 | ||
127 | #define hp_register_write_word(pdev, reg , value) \ | |
128 | pci_write_config_word(pdev, reg, value) | |
129 | ||
130 | #define hp_register_dwrite_word(pdev, reg , value) \ | |
131 | pci_write_config_dword(pdev, reg, value) | |
132 | ||
133 | /* Field definitions in PCI Express Capabilities Register */ | |
134 | #define CAP_VER 0x000F | |
135 | #define DEV_PORT_TYPE 0x00F0 | |
136 | #define SLOT_IMPL 0x0100 | |
137 | #define MSG_NUM 0x3E00 | |
138 | ||
139 | /* Device or Port Type */ | |
140 | #define NAT_ENDPT 0x00 | |
141 | #define LEG_ENDPT 0x01 | |
142 | #define ROOT_PORT 0x04 | |
143 | #define UP_STREAM 0x05 | |
144 | #define DN_STREAM 0x06 | |
145 | #define PCIE_PCI_BRDG 0x07 | |
146 | #define PCI_PCIE_BRDG 0x10 | |
147 | ||
148 | /* Field definitions in Device Capabilities Register */ | |
149 | #define DATTN_BUTTN_PRSN 0x1000 | |
150 | #define DATTN_LED_PRSN 0x2000 | |
151 | #define DPWR_LED_PRSN 0x4000 | |
152 | ||
153 | /* Field definitions in Link Capabilities Register */ | |
154 | #define MAX_LNK_SPEED 0x000F | |
155 | #define MAX_LNK_WIDTH 0x03F0 | |
156 | ||
157 | /* Link Width Encoding */ | |
158 | #define LNK_X1 0x01 | |
159 | #define LNK_X2 0x02 | |
160 | #define LNK_X4 0x04 | |
161 | #define LNK_X8 0x08 | |
162 | #define LNK_X12 0x0C | |
163 | #define LNK_X16 0x10 | |
164 | #define LNK_X32 0x20 | |
165 | ||
166 | /*Field definitions of Link Status Register */ | |
167 | #define LNK_SPEED 0x000F | |
168 | #define NEG_LINK_WD 0x03F0 | |
169 | #define LNK_TRN_ERR 0x0400 | |
170 | #define LNK_TRN 0x0800 | |
171 | #define SLOT_CLK_CONF 0x1000 | |
172 | ||
173 | /* Field definitions in Slot Capabilities Register */ | |
174 | #define ATTN_BUTTN_PRSN 0x00000001 | |
175 | #define PWR_CTRL_PRSN 0x00000002 | |
176 | #define MRL_SENS_PRSN 0x00000004 | |
177 | #define ATTN_LED_PRSN 0x00000008 | |
178 | #define PWR_LED_PRSN 0x00000010 | |
179 | #define HP_SUPR_RM_SUP 0x00000020 | |
180 | #define HP_CAP 0x00000040 | |
181 | #define SLOT_PWR_VALUE 0x000003F8 | |
182 | #define SLOT_PWR_LIMIT 0x00000C00 | |
183 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
184 | ||
185 | /* Field definitions in Slot Control Register */ | |
186 | #define ATTN_BUTTN_ENABLE 0x0001 | |
187 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
188 | #define MRL_DETECT_ENABLE 0x0004 | |
189 | #define PRSN_DETECT_ENABLE 0x0008 | |
190 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
191 | #define HP_INTR_ENABLE 0x0020 | |
192 | #define ATTN_LED_CTRL 0x00C0 | |
193 | #define PWR_LED_CTRL 0x0300 | |
194 | #define PWR_CTRL 0x0400 | |
195 | ||
196 | /* Attention indicator and Power indicator states */ | |
197 | #define LED_ON 0x01 | |
198 | #define LED_BLINK 0x10 | |
199 | #define LED_OFF 0x11 | |
200 | ||
201 | /* Power Control Command */ | |
202 | #define POWER_ON 0 | |
203 | #define POWER_OFF 0x0400 | |
204 | ||
205 | /* Field definitions in Slot Status Register */ | |
206 | #define ATTN_BUTTN_PRESSED 0x0001 | |
207 | #define PWR_FAULT_DETECTED 0x0002 | |
208 | #define MRL_SENS_CHANGED 0x0004 | |
209 | #define PRSN_DETECT_CHANGED 0x0008 | |
210 | #define CMD_COMPLETED 0x0010 | |
211 | #define MRL_STATE 0x0020 | |
212 | #define PRSN_STATE 0x0040 | |
213 | ||
1da177e4 LT |
214 | static spinlock_t hpc_event_lock; |
215 | ||
216 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ | |
217 | static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ | |
218 | static int ctlr_seq_num = 0; /* Controller sequence # */ | |
219 | static spinlock_t list_lock; | |
220 | ||
221 | static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs); | |
222 | ||
223 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds); | |
224 | ||
225 | /* This is the interrupt polling timeout function. */ | |
226 | static void int_poll_timeout(unsigned long lphp_ctlr) | |
227 | { | |
228 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr; | |
229 | ||
230 | DBG_ENTER_ROUTINE | |
231 | ||
232 | if ( !php_ctlr ) { | |
233 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
234 | return; | |
235 | } | |
236 | ||
237 | /* Poll for interrupt events. regs == NULL => polling */ | |
238 | pcie_isr( 0, (void *)php_ctlr, NULL ); | |
239 | ||
240 | init_timer(&php_ctlr->int_poll_timer); | |
241 | ||
242 | if (!pciehp_poll_time) | |
243 | pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ | |
244 | ||
245 | start_int_poll_timer(php_ctlr, pciehp_poll_time); | |
246 | ||
247 | return; | |
248 | } | |
249 | ||
250 | /* This function starts the interrupt polling timer. */ | |
251 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds) | |
252 | { | |
253 | if (!php_ctlr) { | |
254 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
255 | return; | |
256 | } | |
257 | ||
258 | if ( ( seconds <= 0 ) || ( seconds > 60 ) ) | |
259 | seconds = 2; /* Clamp to sane value */ | |
260 | ||
261 | php_ctlr->int_poll_timer.function = &int_poll_timeout; | |
262 | php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */ | |
263 | php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ; | |
264 | add_timer(&php_ctlr->int_poll_timer); | |
265 | ||
266 | return; | |
267 | } | |
268 | ||
269 | static int pcie_write_cmd(struct slot *slot, u16 cmd) | |
270 | { | |
271 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
272 | int retval = 0; | |
273 | u16 slot_status; | |
274 | ||
275 | DBG_ENTER_ROUTINE | |
276 | ||
1da177e4 LT |
277 | if (!php_ctlr) { |
278 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
279 | return -1; | |
280 | } | |
281 | ||
8b245e45 | 282 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); |
1da177e4 LT |
283 | if (retval) { |
284 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
285 | return retval; | |
286 | } | |
1da177e4 LT |
287 | |
288 | if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { | |
289 | /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue | |
290 | the next command according to spec. Just print out the error message */ | |
291 | dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__); | |
292 | } | |
293 | ||
8b245e45 | 294 | retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE); |
1da177e4 LT |
295 | if (retval) { |
296 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
297 | return retval; | |
298 | } | |
1da177e4 LT |
299 | |
300 | DBG_LEAVE_ROUTINE | |
301 | return retval; | |
302 | } | |
303 | ||
304 | static int hpc_check_lnk_status(struct controller *ctrl) | |
305 | { | |
306 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | |
307 | u16 lnk_status; | |
308 | int retval = 0; | |
309 | ||
310 | DBG_ENTER_ROUTINE | |
311 | ||
312 | if (!php_ctlr) { | |
313 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
314 | return -1; | |
315 | } | |
316 | ||
8b245e45 | 317 | retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status); |
1da177e4 LT |
318 | |
319 | if (retval) { | |
320 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
321 | return retval; | |
322 | } | |
323 | ||
324 | dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status); | |
325 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || | |
326 | !(lnk_status & NEG_LINK_WD)) { | |
327 | err("%s : Link Training Error occurs \n", __FUNCTION__); | |
328 | retval = -1; | |
329 | return retval; | |
330 | } | |
331 | ||
332 | DBG_LEAVE_ROUTINE | |
333 | return retval; | |
334 | } | |
335 | ||
336 | ||
337 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
338 | { | |
339 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
340 | u16 slot_ctrl; | |
341 | u8 atten_led_state; | |
342 | int retval = 0; | |
343 | ||
344 | DBG_ENTER_ROUTINE | |
345 | ||
346 | if (!php_ctlr) { | |
347 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
348 | return -1; | |
349 | } | |
350 | ||
8b245e45 | 351 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
352 | |
353 | if (retval) { | |
354 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
355 | return retval; | |
356 | } | |
357 | ||
8b245e45 | 358 | dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
359 | |
360 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
361 | ||
362 | switch (atten_led_state) { | |
363 | case 0: | |
364 | *status = 0xFF; /* Reserved */ | |
365 | break; | |
366 | case 1: | |
367 | *status = 1; /* On */ | |
368 | break; | |
369 | case 2: | |
370 | *status = 2; /* Blink */ | |
371 | break; | |
372 | case 3: | |
373 | *status = 0; /* Off */ | |
374 | break; | |
375 | default: | |
376 | *status = 0xFF; | |
377 | break; | |
378 | } | |
379 | ||
380 | DBG_LEAVE_ROUTINE | |
381 | return 0; | |
382 | } | |
383 | ||
384 | static int hpc_get_power_status(struct slot * slot, u8 *status) | |
385 | { | |
386 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
387 | u16 slot_ctrl; | |
388 | u8 pwr_state; | |
389 | int retval = 0; | |
390 | ||
391 | DBG_ENTER_ROUTINE | |
392 | ||
393 | if (!php_ctlr) { | |
394 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
395 | return -1; | |
396 | } | |
397 | ||
8b245e45 | 398 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
399 | |
400 | if (retval) { | |
401 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
402 | return retval; | |
403 | } | |
8b245e45 | 404 | dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
405 | |
406 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
407 | ||
408 | switch (pwr_state) { | |
409 | case 0: | |
410 | *status = 1; | |
411 | break; | |
412 | case 1: | |
413 | *status = 0; | |
414 | break; | |
415 | default: | |
416 | *status = 0xFF; | |
417 | break; | |
418 | } | |
419 | ||
420 | DBG_LEAVE_ROUTINE | |
421 | return retval; | |
422 | } | |
423 | ||
424 | ||
425 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
426 | { | |
427 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
428 | u16 slot_status; | |
429 | int retval = 0; | |
430 | ||
431 | DBG_ENTER_ROUTINE | |
432 | ||
433 | if (!php_ctlr) { | |
434 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
435 | return -1; | |
436 | } | |
437 | ||
8b245e45 | 438 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); |
1da177e4 LT |
439 | |
440 | if (retval) { | |
441 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
442 | return retval; | |
443 | } | |
444 | ||
445 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; | |
446 | ||
447 | DBG_LEAVE_ROUTINE | |
448 | return 0; | |
449 | } | |
450 | ||
451 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
452 | { | |
453 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
454 | u16 slot_status; | |
455 | u8 card_state; | |
456 | int retval = 0; | |
457 | ||
458 | DBG_ENTER_ROUTINE | |
459 | ||
460 | if (!php_ctlr) { | |
461 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
462 | return -1; | |
463 | } | |
464 | ||
8b245e45 | 465 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); |
1da177e4 LT |
466 | |
467 | if (retval) { | |
468 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
469 | return retval; | |
470 | } | |
471 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
472 | *status = (card_state == 1) ? 1 : 0; | |
473 | ||
474 | DBG_LEAVE_ROUTINE | |
475 | return 0; | |
476 | } | |
477 | ||
478 | static int hpc_query_power_fault(struct slot * slot) | |
479 | { | |
480 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
481 | u16 slot_status; | |
482 | u8 pwr_fault; | |
483 | int retval = 0; | |
484 | u8 status; | |
485 | ||
486 | DBG_ENTER_ROUTINE | |
487 | ||
488 | if (!php_ctlr) { | |
489 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
490 | return -1; | |
491 | } | |
492 | ||
8b245e45 | 493 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status); |
1da177e4 LT |
494 | |
495 | if (retval) { | |
496 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
497 | return retval; | |
498 | } | |
499 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
500 | status = (pwr_fault != 1) ? 1 : 0; | |
501 | ||
502 | DBG_LEAVE_ROUTINE | |
503 | /* Note: Logic 0 => fault */ | |
504 | return status; | |
505 | } | |
506 | ||
507 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
508 | { | |
509 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
510 | u16 slot_cmd = 0; | |
511 | u16 slot_ctrl; | |
512 | int rc = 0; | |
513 | ||
1a9ed1bf RS |
514 | DBG_ENTER_ROUTINE |
515 | ||
1da177e4 LT |
516 | if (!php_ctlr) { |
517 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
518 | return -1; | |
519 | } | |
520 | ||
521 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
522 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
523 | return -1; | |
524 | } | |
8b245e45 | 525 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
526 | |
527 | if (rc) { | |
528 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
529 | return rc; | |
530 | } | |
1da177e4 LT |
531 | |
532 | switch (value) { | |
533 | case 0 : /* turn off */ | |
534 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0; | |
535 | break; | |
536 | case 1: /* turn on */ | |
537 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040; | |
538 | break; | |
539 | case 2: /* turn blink */ | |
540 | slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080; | |
541 | break; | |
542 | default: | |
543 | return -1; | |
544 | } | |
545 | if (!pciehp_poll_mode) | |
546 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
547 | ||
548 | pcie_write_cmd(slot, slot_cmd); | |
8b245e45 | 549 | dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 | 550 | |
1a9ed1bf | 551 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
552 | return rc; |
553 | } | |
554 | ||
555 | ||
556 | static void hpc_set_green_led_on(struct slot *slot) | |
557 | { | |
558 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
559 | u16 slot_cmd; | |
560 | u16 slot_ctrl; | |
561 | int rc = 0; | |
562 | ||
1a9ed1bf RS |
563 | DBG_ENTER_ROUTINE |
564 | ||
1da177e4 LT |
565 | if (!php_ctlr) { |
566 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
567 | return ; | |
568 | } | |
569 | ||
570 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
571 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
572 | return ; | |
573 | } | |
574 | ||
8b245e45 | 575 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
576 | |
577 | if (rc) { | |
578 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
579 | return; | |
580 | } | |
1da177e4 LT |
581 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100; |
582 | if (!pciehp_poll_mode) | |
583 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
584 | ||
585 | pcie_write_cmd(slot, slot_cmd); | |
586 | ||
8b245e45 | 587 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1a9ed1bf | 588 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
589 | return; |
590 | } | |
591 | ||
592 | static void hpc_set_green_led_off(struct slot *slot) | |
593 | { | |
594 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
595 | u16 slot_cmd; | |
596 | u16 slot_ctrl; | |
597 | int rc = 0; | |
598 | ||
1a9ed1bf RS |
599 | DBG_ENTER_ROUTINE |
600 | ||
1da177e4 LT |
601 | if (!php_ctlr) { |
602 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
603 | return ; | |
604 | } | |
605 | ||
606 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
607 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
608 | return ; | |
609 | } | |
610 | ||
8b245e45 | 611 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
612 | |
613 | if (rc) { | |
614 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
615 | return; | |
616 | } | |
1da177e4 LT |
617 | |
618 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300; | |
619 | ||
620 | if (!pciehp_poll_mode) | |
621 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
622 | pcie_write_cmd(slot, slot_cmd); | |
8b245e45 | 623 | dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 | 624 | |
1a9ed1bf | 625 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
626 | return; |
627 | } | |
628 | ||
629 | static void hpc_set_green_led_blink(struct slot *slot) | |
630 | { | |
631 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
632 | u16 slot_cmd; | |
633 | u16 slot_ctrl; | |
634 | int rc = 0; | |
635 | ||
1a9ed1bf RS |
636 | DBG_ENTER_ROUTINE |
637 | ||
1da177e4 LT |
638 | if (!php_ctlr) { |
639 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
640 | return ; | |
641 | } | |
642 | ||
643 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
644 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
645 | return ; | |
646 | } | |
647 | ||
8b245e45 | 648 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
649 | |
650 | if (rc) { | |
651 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
652 | return; | |
653 | } | |
1da177e4 LT |
654 | |
655 | slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200; | |
656 | ||
657 | if (!pciehp_poll_mode) | |
658 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
659 | pcie_write_cmd(slot, slot_cmd); | |
660 | ||
8b245e45 | 661 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1a9ed1bf | 662 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
663 | return; |
664 | } | |
665 | ||
666 | int pcie_get_ctlr_slot_config(struct controller *ctrl, | |
667 | int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */ | |
668 | int *first_device_num, /* PCI dev num of the first slot in this PCIE */ | |
669 | int *physical_slot_num, /* phy slot num of the first slot in this PCIE */ | |
670 | u8 *ctrlcap) | |
671 | { | |
672 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | |
673 | u32 slot_cap; | |
674 | int rc = 0; | |
675 | ||
676 | DBG_ENTER_ROUTINE | |
677 | ||
678 | if (!php_ctlr) { | |
679 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
680 | return -1; | |
681 | } | |
682 | ||
683 | *first_device_num = 0; | |
684 | *num_ctlr_slots = 1; | |
685 | ||
8b245e45 | 686 | rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap); |
1da177e4 LT |
687 | |
688 | if (rc) { | |
689 | err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__); | |
690 | return -1; | |
691 | } | |
692 | ||
693 | *physical_slot_num = slot_cap >> 19; | |
694 | dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num); | |
695 | ||
696 | *ctrlcap = slot_cap & 0x0000007f; | |
697 | ||
698 | DBG_LEAVE_ROUTINE | |
699 | return 0; | |
700 | } | |
701 | ||
702 | static void hpc_release_ctlr(struct controller *ctrl) | |
703 | { | |
704 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | |
705 | struct php_ctlr_state_s *p, *p_prev; | |
706 | ||
707 | DBG_ENTER_ROUTINE | |
708 | ||
709 | if (!php_ctlr) { | |
710 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
711 | return ; | |
712 | } | |
713 | ||
714 | if (pciehp_poll_mode) { | |
715 | del_timer(&php_ctlr->int_poll_timer); | |
716 | } else { | |
717 | if (php_ctlr->irq) { | |
718 | free_irq(php_ctlr->irq, ctrl); | |
719 | php_ctlr->irq = 0; | |
720 | if (!pcie_mch_quirk) | |
721 | pci_disable_msi(php_ctlr->pci_dev); | |
722 | } | |
723 | } | |
724 | if (php_ctlr->pci_dev) | |
725 | php_ctlr->pci_dev = NULL; | |
726 | ||
727 | spin_lock(&list_lock); | |
728 | p = php_ctlr_list_head; | |
729 | p_prev = NULL; | |
730 | while (p) { | |
731 | if (p == php_ctlr) { | |
732 | if (p_prev) | |
733 | p_prev->pnext = p->pnext; | |
734 | else | |
735 | php_ctlr_list_head = p->pnext; | |
736 | break; | |
737 | } else { | |
738 | p_prev = p; | |
739 | p = p->pnext; | |
740 | } | |
741 | } | |
742 | spin_unlock(&list_lock); | |
743 | ||
744 | kfree(php_ctlr); | |
745 | ||
746 | DBG_LEAVE_ROUTINE | |
747 | ||
748 | } | |
749 | ||
750 | static int hpc_power_on_slot(struct slot * slot) | |
751 | { | |
752 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
753 | u16 slot_cmd; | |
754 | u16 slot_ctrl; | |
755 | ||
756 | int retval = 0; | |
757 | ||
758 | DBG_ENTER_ROUTINE | |
1da177e4 LT |
759 | |
760 | if (!php_ctlr) { | |
761 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
762 | return -1; | |
763 | } | |
764 | ||
765 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); | |
766 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
767 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
768 | return -1; | |
769 | } | |
770 | ||
8b245e45 | 771 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
772 | |
773 | if (retval) { | |
774 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
775 | return retval; | |
776 | } | |
1da177e4 LT |
777 | |
778 | slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON; | |
779 | ||
780 | if (!pciehp_poll_mode) | |
781 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
782 | ||
783 | retval = pcie_write_cmd(slot, slot_cmd); | |
784 | ||
785 | if (retval) { | |
786 | err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd); | |
787 | return -1; | |
788 | } | |
8b245e45 | 789 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 LT |
790 | |
791 | DBG_LEAVE_ROUTINE | |
792 | ||
793 | return retval; | |
794 | } | |
795 | ||
796 | static int hpc_power_off_slot(struct slot * slot) | |
797 | { | |
798 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
799 | u16 slot_cmd; | |
800 | u16 slot_ctrl; | |
801 | ||
802 | int retval = 0; | |
803 | ||
804 | DBG_ENTER_ROUTINE | |
1da177e4 LT |
805 | |
806 | if (!php_ctlr) { | |
807 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
808 | return -1; | |
809 | } | |
810 | ||
811 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); | |
812 | slot->hp_slot = 0; | |
813 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
814 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
815 | return -1; | |
816 | } | |
8b245e45 | 817 | retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
818 | |
819 | if (retval) { | |
820 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
821 | return retval; | |
822 | } | |
1da177e4 LT |
823 | |
824 | slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF; | |
825 | ||
826 | if (!pciehp_poll_mode) | |
827 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
828 | ||
829 | retval = pcie_write_cmd(slot, slot_cmd); | |
830 | ||
831 | if (retval) { | |
832 | err("%s: Write command failed!\n", __FUNCTION__); | |
833 | return -1; | |
834 | } | |
8b245e45 | 835 | dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd); |
1da177e4 LT |
836 | |
837 | DBG_LEAVE_ROUTINE | |
838 | ||
839 | return retval; | |
840 | } | |
841 | ||
842 | static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |
843 | { | |
844 | struct controller *ctrl = NULL; | |
845 | struct php_ctlr_state_s *php_ctlr; | |
846 | u8 schedule_flag = 0; | |
847 | u16 slot_status, intr_detect, intr_loc; | |
848 | u16 temp_word; | |
849 | int hp_slot = 0; /* only 1 slot per PCI Express port */ | |
850 | int rc = 0; | |
851 | ||
852 | if (!dev_id) | |
853 | return IRQ_NONE; | |
854 | ||
855 | if (!pciehp_poll_mode) { | |
856 | ctrl = dev_id; | |
857 | php_ctlr = ctrl->hpc_ctlr_handle; | |
858 | } else { | |
859 | php_ctlr = dev_id; | |
860 | ctrl = (struct controller *)php_ctlr->callback_instance_id; | |
861 | } | |
862 | ||
863 | if (!ctrl) { | |
864 | dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id); | |
865 | return IRQ_NONE; | |
866 | } | |
867 | ||
868 | if (!php_ctlr) { | |
869 | dbg("%s: php_ctlr == NULL\n", __FUNCTION__); | |
870 | return IRQ_NONE; | |
871 | } | |
872 | ||
8b245e45 | 873 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
874 | if (rc) { |
875 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
876 | return IRQ_NONE; | |
877 | } | |
878 | ||
879 | intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED | | |
880 | PRSN_DETECT_CHANGED | CMD_COMPLETED ); | |
881 | ||
882 | intr_loc = slot_status & intr_detect; | |
883 | ||
884 | /* Check to see if it was our interrupt */ | |
885 | if ( !intr_loc ) | |
886 | return IRQ_NONE; | |
887 | ||
888 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); | |
889 | /* Mask Hot-plug Interrupt Enable */ | |
890 | if (!pciehp_poll_mode) { | |
8b245e45 | 891 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
892 | if (rc) { |
893 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
894 | return IRQ_NONE; | |
895 | } | |
896 | ||
1da177e4 LT |
897 | dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word); |
898 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; | |
899 | ||
8b245e45 | 900 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
901 | if (rc) { |
902 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
903 | return IRQ_NONE; | |
904 | } | |
1da177e4 | 905 | |
8b245e45 | 906 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
907 | if (rc) { |
908 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
909 | return IRQ_NONE; | |
910 | } | |
911 | dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status); | |
912 | ||
913 | /* Clear command complete interrupt caused by this write */ | |
914 | temp_word = 0x1f; | |
8b245e45 | 915 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
916 | if (rc) { |
917 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
918 | return IRQ_NONE; | |
919 | } | |
1da177e4 LT |
920 | } |
921 | ||
922 | if (intr_loc & CMD_COMPLETED) { | |
923 | /* | |
924 | * Command Complete Interrupt Pending | |
925 | */ | |
1da177e4 LT |
926 | wake_up_interruptible(&ctrl->queue); |
927 | } | |
928 | ||
929 | if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED)) | |
930 | schedule_flag += php_ctlr->switch_change_callback( | |
931 | hp_slot, php_ctlr->callback_instance_id); | |
932 | if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED)) | |
933 | schedule_flag += php_ctlr->attention_button_callback( | |
934 | hp_slot, php_ctlr->callback_instance_id); | |
935 | if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED)) | |
936 | schedule_flag += php_ctlr->presence_change_callback( | |
937 | hp_slot , php_ctlr->callback_instance_id); | |
938 | if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED)) | |
939 | schedule_flag += php_ctlr->power_fault_callback( | |
940 | hp_slot, php_ctlr->callback_instance_id); | |
941 | ||
942 | /* Clear all events after serving them */ | |
943 | temp_word = 0x1F; | |
8b245e45 | 944 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
945 | if (rc) { |
946 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
947 | return IRQ_NONE; | |
948 | } | |
949 | /* Unmask Hot-plug Interrupt Enable */ | |
950 | if (!pciehp_poll_mode) { | |
8b245e45 | 951 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
952 | if (rc) { |
953 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
954 | return IRQ_NONE; | |
955 | } | |
956 | ||
957 | dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); | |
1da177e4 LT |
958 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; |
959 | ||
8b245e45 | 960 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
961 | if (rc) { |
962 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
963 | return IRQ_NONE; | |
964 | } | |
1da177e4 | 965 | |
8b245e45 | 966 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
967 | if (rc) { |
968 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
969 | return IRQ_NONE; | |
970 | } | |
1da177e4 LT |
971 | |
972 | /* Clear command complete interrupt caused by this write */ | |
973 | temp_word = 0x1F; | |
8b245e45 | 974 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
975 | if (rc) { |
976 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
977 | return IRQ_NONE; | |
978 | } | |
979 | dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word); | |
980 | } | |
981 | ||
982 | return IRQ_HANDLED; | |
983 | } | |
984 | ||
985 | static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |
986 | { | |
987 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
988 | enum pcie_link_speed lnk_speed; | |
989 | u32 lnk_cap; | |
990 | int retval = 0; | |
991 | ||
992 | DBG_ENTER_ROUTINE | |
993 | ||
994 | if (!php_ctlr) { | |
995 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
996 | return -1; | |
997 | } | |
998 | ||
999 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
1000 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
1001 | return -1; | |
1002 | } | |
1003 | ||
8b245e45 | 1004 | retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap); |
1da177e4 LT |
1005 | |
1006 | if (retval) { | |
1007 | err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__); | |
1008 | return retval; | |
1009 | } | |
1010 | ||
1011 | switch (lnk_cap & 0x000F) { | |
1012 | case 1: | |
1013 | lnk_speed = PCIE_2PT5GB; | |
1014 | break; | |
1015 | default: | |
1016 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
1017 | break; | |
1018 | } | |
1019 | ||
1020 | *value = lnk_speed; | |
1021 | dbg("Max link speed = %d\n", lnk_speed); | |
1022 | DBG_LEAVE_ROUTINE | |
1023 | return retval; | |
1024 | } | |
1025 | ||
1026 | static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value) | |
1027 | { | |
1028 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
1029 | enum pcie_link_width lnk_wdth; | |
1030 | u32 lnk_cap; | |
1031 | int retval = 0; | |
1032 | ||
1033 | DBG_ENTER_ROUTINE | |
1034 | ||
1035 | if (!php_ctlr) { | |
1036 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
1037 | return -1; | |
1038 | } | |
1039 | ||
1040 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
1041 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
1042 | return -1; | |
1043 | } | |
1044 | ||
8b245e45 | 1045 | retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap); |
1da177e4 LT |
1046 | |
1047 | if (retval) { | |
1048 | err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__); | |
1049 | return retval; | |
1050 | } | |
1051 | ||
1052 | switch ((lnk_cap & 0x03F0) >> 4){ | |
1053 | case 0: | |
1054 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
1055 | break; | |
1056 | case 1: | |
1057 | lnk_wdth = PCIE_LNK_X1; | |
1058 | break; | |
1059 | case 2: | |
1060 | lnk_wdth = PCIE_LNK_X2; | |
1061 | break; | |
1062 | case 4: | |
1063 | lnk_wdth = PCIE_LNK_X4; | |
1064 | break; | |
1065 | case 8: | |
1066 | lnk_wdth = PCIE_LNK_X8; | |
1067 | break; | |
1068 | case 12: | |
1069 | lnk_wdth = PCIE_LNK_X12; | |
1070 | break; | |
1071 | case 16: | |
1072 | lnk_wdth = PCIE_LNK_X16; | |
1073 | break; | |
1074 | case 32: | |
1075 | lnk_wdth = PCIE_LNK_X32; | |
1076 | break; | |
1077 | default: | |
1078 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
1079 | break; | |
1080 | } | |
1081 | ||
1082 | *value = lnk_wdth; | |
1083 | dbg("Max link width = %d\n", lnk_wdth); | |
1084 | DBG_LEAVE_ROUTINE | |
1085 | return retval; | |
1086 | } | |
1087 | ||
1088 | static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |
1089 | { | |
1090 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
1091 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; | |
1092 | int retval = 0; | |
1093 | u16 lnk_status; | |
1094 | ||
1095 | DBG_ENTER_ROUTINE | |
1096 | ||
1097 | if (!php_ctlr) { | |
1098 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
1099 | return -1; | |
1100 | } | |
1101 | ||
1102 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
1103 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
1104 | return -1; | |
1105 | } | |
1106 | ||
8b245e45 | 1107 | retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status); |
1da177e4 LT |
1108 | |
1109 | if (retval) { | |
1110 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
1111 | return retval; | |
1112 | } | |
1113 | ||
1114 | switch (lnk_status & 0x0F) { | |
1115 | case 1: | |
1116 | lnk_speed = PCIE_2PT5GB; | |
1117 | break; | |
1118 | default: | |
1119 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
1120 | break; | |
1121 | } | |
1122 | ||
1123 | *value = lnk_speed; | |
1124 | dbg("Current link speed = %d\n", lnk_speed); | |
1125 | DBG_LEAVE_ROUTINE | |
1126 | return retval; | |
1127 | } | |
1128 | ||
1129 | static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value) | |
1130 | { | |
1131 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; | |
1132 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
1133 | int retval = 0; | |
1134 | u16 lnk_status; | |
1135 | ||
1136 | DBG_ENTER_ROUTINE | |
1137 | ||
1138 | if (!php_ctlr) { | |
1139 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
1140 | return -1; | |
1141 | } | |
1142 | ||
1143 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
1144 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
1145 | return -1; | |
1146 | } | |
1147 | ||
8b245e45 | 1148 | retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status); |
1da177e4 LT |
1149 | |
1150 | if (retval) { | |
1151 | err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__); | |
1152 | return retval; | |
1153 | } | |
1154 | ||
1155 | switch ((lnk_status & 0x03F0) >> 4){ | |
1156 | case 0: | |
1157 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
1158 | break; | |
1159 | case 1: | |
1160 | lnk_wdth = PCIE_LNK_X1; | |
1161 | break; | |
1162 | case 2: | |
1163 | lnk_wdth = PCIE_LNK_X2; | |
1164 | break; | |
1165 | case 4: | |
1166 | lnk_wdth = PCIE_LNK_X4; | |
1167 | break; | |
1168 | case 8: | |
1169 | lnk_wdth = PCIE_LNK_X8; | |
1170 | break; | |
1171 | case 12: | |
1172 | lnk_wdth = PCIE_LNK_X12; | |
1173 | break; | |
1174 | case 16: | |
1175 | lnk_wdth = PCIE_LNK_X16; | |
1176 | break; | |
1177 | case 32: | |
1178 | lnk_wdth = PCIE_LNK_X32; | |
1179 | break; | |
1180 | default: | |
1181 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
1182 | break; | |
1183 | } | |
1184 | ||
1185 | *value = lnk_wdth; | |
1186 | dbg("Current link width = %d\n", lnk_wdth); | |
1187 | DBG_LEAVE_ROUTINE | |
1188 | return retval; | |
1189 | } | |
1190 | ||
1191 | static struct hpc_ops pciehp_hpc_ops = { | |
1192 | .power_on_slot = hpc_power_on_slot, | |
1193 | .power_off_slot = hpc_power_off_slot, | |
1194 | .set_attention_status = hpc_set_attention_status, | |
1195 | .get_power_status = hpc_get_power_status, | |
1196 | .get_attention_status = hpc_get_attention_status, | |
1197 | .get_latch_status = hpc_get_latch_status, | |
1198 | .get_adapter_status = hpc_get_adapter_status, | |
1199 | ||
1200 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
1201 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
1202 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
1203 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
1204 | ||
1205 | .query_power_fault = hpc_query_power_fault, | |
1206 | .green_led_on = hpc_set_green_led_on, | |
1207 | .green_led_off = hpc_set_green_led_off, | |
1208 | .green_led_blink = hpc_set_green_led_blink, | |
1209 | ||
1210 | .release_ctlr = hpc_release_ctlr, | |
1211 | .check_lnk_status = hpc_check_lnk_status, | |
1212 | }; | |
1213 | ||
ed6cbcf2 | 1214 | int pcie_init(struct controller * ctrl, struct pcie_device *dev) |
1da177e4 LT |
1215 | { |
1216 | struct php_ctlr_state_s *php_ctlr, *p; | |
1217 | void *instance_id = ctrl; | |
1218 | int rc; | |
1219 | static int first = 1; | |
1220 | u16 temp_word; | |
1221 | u16 cap_reg; | |
1222 | u16 intr_enable = 0; | |
1223 | u32 slot_cap; | |
1224 | int cap_base, saved_cap_base; | |
1225 | u16 slot_status, slot_ctrl; | |
1226 | struct pci_dev *pdev; | |
1227 | ||
1228 | DBG_ENTER_ROUTINE | |
1229 | ||
1230 | spin_lock_init(&list_lock); | |
1231 | php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL); | |
1232 | ||
1233 | if (!php_ctlr) { /* allocate controller state data */ | |
1234 | err("%s: HPC controller memory allocation error!\n", __FUNCTION__); | |
1235 | goto abort; | |
1236 | } | |
1237 | ||
1238 | memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s)); | |
1239 | ||
1240 | pdev = dev->port; | |
1241 | php_ctlr->pci_dev = pdev; /* save pci_dev in context */ | |
1242 | ||
1a9ed1bf RS |
1243 | dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", |
1244 | __FUNCTION__, pdev->vendor, pdev->device); | |
1da177e4 LT |
1245 | |
1246 | saved_cap_base = pcie_cap_base; | |
1247 | ||
1248 | if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { | |
1249 | dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); | |
1250 | goto abort_free_ctlr; | |
1251 | } | |
1252 | ||
8b245e45 | 1253 | ctrl->cap_base = cap_base; |
1da177e4 LT |
1254 | |
1255 | dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base); | |
1256 | ||
8b245e45 | 1257 | rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg); |
1da177e4 LT |
1258 | if (rc) { |
1259 | err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__); | |
1260 | goto abort_free_ctlr; | |
1261 | } | |
8b245e45 | 1262 | dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg); |
1da177e4 | 1263 | |
8b245e45 DS |
1264 | if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040) |
1265 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { | |
1da177e4 LT |
1266 | dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__); |
1267 | goto abort_free_ctlr; | |
1268 | } | |
1269 | ||
8b245e45 | 1270 | rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap); |
1da177e4 LT |
1271 | if (rc) { |
1272 | err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__); | |
1273 | goto abort_free_ctlr; | |
1274 | } | |
8b245e45 | 1275 | dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap); |
1da177e4 LT |
1276 | |
1277 | if (!(slot_cap & HP_CAP)) { | |
1278 | dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); | |
1279 | goto abort_free_ctlr; | |
1280 | } | |
1281 | /* For debugging purpose */ | |
8b245e45 | 1282 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1283 | if (rc) { |
1284 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
1285 | goto abort_free_ctlr; | |
1286 | } | |
8b245e45 | 1287 | dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 | 1288 | |
8b245e45 | 1289 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
1290 | if (rc) { |
1291 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
1292 | goto abort_free_ctlr; | |
1293 | } | |
8b245e45 | 1294 | dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl); |
1da177e4 LT |
1295 | |
1296 | if (first) { | |
1297 | spin_lock_init(&hpc_event_lock); | |
1298 | first = 0; | |
1299 | } | |
1300 | ||
1da177e4 LT |
1301 | for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) |
1302 | if (pci_resource_len(pdev, rc) > 0) | |
1303 | dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc, | |
1304 | pci_resource_start(pdev, rc), pci_resource_len(pdev, rc)); | |
1305 | ||
1306 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, | |
1307 | pdev->subsystem_vendor, pdev->subsystem_device); | |
1308 | ||
1309 | if (pci_enable_device(pdev)) | |
1310 | goto abort_free_ctlr; | |
1311 | ||
1312 | init_MUTEX(&ctrl->crit_sect); | |
1313 | /* setup wait queue */ | |
1314 | init_waitqueue_head(&ctrl->queue); | |
1315 | ||
1316 | /* find the IRQ */ | |
1317 | php_ctlr->irq = dev->irq; | |
1da177e4 LT |
1318 | |
1319 | /* Save interrupt callback info */ | |
ed6cbcf2 RS |
1320 | php_ctlr->attention_button_callback = pciehp_handle_attention_button; |
1321 | php_ctlr->switch_change_callback = pciehp_handle_switch_change; | |
1322 | php_ctlr->presence_change_callback = pciehp_handle_presence_change; | |
1323 | php_ctlr->power_fault_callback = pciehp_handle_power_fault; | |
1da177e4 LT |
1324 | php_ctlr->callback_instance_id = instance_id; |
1325 | ||
1326 | /* return PCI Controller Info */ | |
1327 | php_ctlr->slot_device_offset = 0; | |
1328 | php_ctlr->num_slots = 1; | |
1329 | ||
1330 | /* Mask Hot-plug Interrupt Enable */ | |
8b245e45 | 1331 | rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1332 | if (rc) { |
1333 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
1334 | goto abort_free_ctlr; | |
1335 | } | |
1336 | ||
8b245e45 | 1337 | dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1338 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; |
1339 | ||
8b245e45 | 1340 | rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1341 | if (rc) { |
1342 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
1343 | goto abort_free_ctlr; | |
1344 | } | |
1da177e4 | 1345 | |
8b245e45 | 1346 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1347 | if (rc) { |
1348 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
1349 | goto abort_free_ctlr; | |
1350 | } | |
1da177e4 LT |
1351 | |
1352 | temp_word = 0x1F; /* Clear all events */ | |
8b245e45 | 1353 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
1354 | if (rc) { |
1355 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
1356 | goto abort_free_ctlr; | |
1357 | } | |
1da177e4 LT |
1358 | |
1359 | if (pciehp_poll_mode) {/* Install interrupt polling code */ | |
1360 | /* Install and start the interrupt polling timer */ | |
1361 | init_timer(&php_ctlr->int_poll_timer); | |
1362 | start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ | |
1363 | } else { | |
1364 | /* Installs the interrupt handler */ | |
1365 | rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl); | |
1366 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); | |
1367 | if (rc) { | |
1368 | err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); | |
1369 | goto abort_free_ctlr; | |
1370 | } | |
1371 | } | |
1372 | ||
1a9ed1bf RS |
1373 | dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, |
1374 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); | |
1375 | ||
8b245e45 | 1376 | rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1377 | if (rc) { |
1378 | err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__); | |
1379 | goto abort_free_ctlr; | |
1380 | } | |
1da177e4 LT |
1381 | |
1382 | intr_enable = intr_enable | PRSN_DETECT_ENABLE; | |
1383 | ||
1384 | if (ATTN_BUTTN(slot_cap)) | |
1385 | intr_enable = intr_enable | ATTN_BUTTN_ENABLE; | |
1386 | ||
1387 | if (POWER_CTRL(slot_cap)) | |
1388 | intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; | |
1389 | ||
1390 | if (MRL_SENS(slot_cap)) | |
1391 | intr_enable = intr_enable | MRL_DETECT_ENABLE; | |
1392 | ||
1393 | temp_word = (temp_word & ~intr_enable) | intr_enable; | |
1394 | ||
1395 | if (pciehp_poll_mode) { | |
1396 | temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; | |
1397 | } else { | |
1398 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; | |
1399 | } | |
1da177e4 LT |
1400 | |
1401 | /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ | |
8b245e45 | 1402 | rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word); |
1da177e4 LT |
1403 | if (rc) { |
1404 | err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__); | |
1405 | goto abort_free_ctlr; | |
1406 | } | |
8b245e45 | 1407 | rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status); |
1da177e4 LT |
1408 | if (rc) { |
1409 | err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__); | |
1410 | goto abort_free_ctlr; | |
1411 | } | |
1da177e4 LT |
1412 | |
1413 | temp_word = 0x1F; /* Clear all events */ | |
8b245e45 | 1414 | rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word); |
1da177e4 LT |
1415 | if (rc) { |
1416 | err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__); | |
1417 | goto abort_free_ctlr; | |
1418 | } | |
1da177e4 | 1419 | |
a8a2be94 RS |
1420 | rc = get_hp_hw_control_from_firmware(ctrl->pci_dev); |
1421 | if (rc) | |
1422 | goto abort_free_ctlr; | |
1423 | ||
1da177e4 LT |
1424 | /* Add this HPC instance into the HPC list */ |
1425 | spin_lock(&list_lock); | |
1426 | if (php_ctlr_list_head == 0) { | |
1427 | php_ctlr_list_head = php_ctlr; | |
1428 | p = php_ctlr_list_head; | |
1429 | p->pnext = NULL; | |
1430 | } else { | |
1431 | p = php_ctlr_list_head; | |
1432 | ||
1433 | while (p->pnext) | |
1434 | p = p->pnext; | |
1435 | ||
1436 | p->pnext = php_ctlr; | |
1437 | } | |
1438 | spin_unlock(&list_lock); | |
1439 | ||
1440 | ctlr_seq_num++; | |
1441 | ctrl->hpc_ctlr_handle = php_ctlr; | |
1442 | ctrl->hpc_ops = &pciehp_hpc_ops; | |
1443 | ||
1444 | DBG_LEAVE_ROUTINE | |
1445 | return 0; | |
1446 | ||
1447 | /* We end up here for the many possible ways to fail this API. */ | |
1448 | abort_free_ctlr: | |
1449 | pcie_cap_base = saved_cap_base; | |
1450 | kfree(php_ctlr); | |
1451 | abort: | |
1452 | DBG_LEAVE_ROUTINE | |
1453 | return -1; | |
1454 | } |