]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
5d1b8c9e | 40 | |
1da177e4 LT |
41 | #include "../pci.h" |
42 | #include "pciehp.h" | |
1da177e4 | 43 | |
cd84d340 | 44 | static inline struct pci_dev *ctrl_dev(struct controller *ctrl) |
a0f018da | 45 | { |
cd84d340 | 46 | return ctrl->pcie->port; |
a0f018da | 47 | } |
1da177e4 | 48 | |
48fe3915 KK |
49 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
50 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
51 | |
52 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 53 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 54 | { |
48fe3915 | 55 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 56 | |
1da177e4 | 57 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 58 | pcie_isr(0, ctrl); |
1da177e4 | 59 | |
48fe3915 | 60 | init_timer(&ctrl->poll_timer); |
1da177e4 | 61 | if (!pciehp_poll_time) |
40730d10 | 62 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 63 | |
48fe3915 | 64 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
65 | } |
66 | ||
67 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 68 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 69 | { |
48fe3915 KK |
70 | /* Clamp to sane value */ |
71 | if ((sec <= 0) || (sec > 60)) | |
f7625980 | 72 | sec = 2; |
48fe3915 KK |
73 | |
74 | ctrl->poll_timer.function = &int_poll_timeout; | |
75 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
76 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
77 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
78 | } |
79 | ||
2aeeef11 KK |
80 | static inline int pciehp_request_irq(struct controller *ctrl) |
81 | { | |
f7a10e32 | 82 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
83 | |
84 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
85 | if (pciehp_poll_mode) { | |
86 | init_timer(&ctrl->poll_timer); | |
87 | start_int_poll_timer(ctrl, 10); | |
88 | return 0; | |
89 | } | |
90 | ||
91 | /* Installs the interrupt handler */ | |
92 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
93 | if (retval) | |
7f2feec1 TI |
94 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
95 | irq); | |
2aeeef11 KK |
96 | return retval; |
97 | } | |
98 | ||
99 | static inline void pciehp_free_irq(struct controller *ctrl) | |
100 | { | |
101 | if (pciehp_poll_mode) | |
102 | del_timer_sync(&ctrl->poll_timer); | |
103 | else | |
f7a10e32 | 104 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
105 | } |
106 | ||
563f1190 | 107 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a | 108 | { |
cd84d340 | 109 | struct pci_dev *pdev = ctrl_dev(ctrl); |
6592e02a | 110 | u16 slot_status; |
1a84b99c | 111 | int timeout = 1000; |
6592e02a | 112 | |
1a84b99c BH |
113 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
114 | if (slot_status & PCI_EXP_SLTSTA_CC) { | |
cd84d340 BH |
115 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
116 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 117 | return 1; |
820943b6 | 118 | } |
a5827f40 | 119 | while (timeout > 0) { |
66618bad KK |
120 | msleep(10); |
121 | timeout -= 10; | |
1a84b99c BH |
122 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
123 | if (slot_status & PCI_EXP_SLTSTA_CC) { | |
cd84d340 BH |
124 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
125 | PCI_EXP_SLTSTA_CC); | |
322162a7 | 126 | return 1; |
820943b6 | 127 | } |
6592e02a KK |
128 | } |
129 | return 0; /* timeout */ | |
6592e02a KK |
130 | } |
131 | ||
563f1190 | 132 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 133 | { |
262303fe KK |
134 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
135 | unsigned long timeout = msecs_to_jiffies(msecs); | |
136 | int rc; | |
137 | ||
6592e02a KK |
138 | if (poll) |
139 | rc = pcie_poll_cmd(ctrl); | |
140 | else | |
d737bdc1 | 141 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 142 | if (!rc) |
7f2feec1 | 143 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
144 | } |
145 | ||
f4778364 KK |
146 | /** |
147 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 148 | * @ctrl: controller to which the command is issued |
f4778364 KK |
149 | * @cmd: command value written to slot control register |
150 | * @mask: bitmask of slot control register to be modified | |
151 | */ | |
6dae6202 | 152 | static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 153 | { |
cd84d340 | 154 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 155 | u16 slot_status; |
f4778364 | 156 | u16 slot_ctrl; |
1da177e4 | 157 | |
44ef4cef KK |
158 | mutex_lock(&ctrl->ctrl_lock); |
159 | ||
1a84b99c | 160 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 161 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
162 | if (!ctrl->no_cmd_complete) { |
163 | /* | |
164 | * After 1 sec and CMD_COMPLETED still not set, just | |
165 | * proceed forward to issue the next command according | |
166 | * to spec. Just print out the error message. | |
167 | */ | |
18b341b7 | 168 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
169 | } else if (!NO_CMD_CMPL(ctrl)) { |
170 | /* | |
f7625980 | 171 | * This controller seems to notify of command completed |
5808639b KK |
172 | * event even though it supports none of power |
173 | * controller, attention led, power led and EMI. | |
174 | */ | |
18b341b7 TI |
175 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
176 | "wait for command completed event.\n"); | |
5808639b KK |
177 | ctrl->no_cmd_complete = 0; |
178 | } else { | |
18b341b7 TI |
179 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
180 | "the controller is broken.\n"); | |
5808639b | 181 | } |
1da177e4 LT |
182 | } |
183 | ||
1a84b99c | 184 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
f4778364 | 185 | slot_ctrl &= ~mask; |
b7aa1f16 | 186 | slot_ctrl |= (cmd & mask); |
f4778364 | 187 | ctrl->cmd_busy = 1; |
2d32a9ae | 188 | smp_mb(); |
1a84b99c | 189 | pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 190 | |
44ef4cef KK |
191 | /* |
192 | * Wait for command completion. | |
193 | */ | |
1a84b99c | 194 | if (!ctrl->no_cmd_complete) { |
6592e02a KK |
195 | int poll = 0; |
196 | /* | |
197 | * if hotplug interrupt is not enabled or command | |
198 | * completed interrupt is not enabled, we need to poll | |
199 | * command completed event. | |
200 | */ | |
322162a7 KK |
201 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
202 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 203 | poll = 1; |
d737bdc1 | 204 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 205 | } |
44ef4cef | 206 | mutex_unlock(&ctrl->ctrl_lock); |
1da177e4 LT |
207 | } |
208 | ||
4703389f | 209 | bool pciehp_check_link_active(struct controller *ctrl) |
f18e9625 | 210 | { |
cd84d340 | 211 | struct pci_dev *pdev = ctrl_dev(ctrl); |
4e2ce405 | 212 | u16 lnk_status; |
1a84b99c | 213 | bool ret; |
f18e9625 | 214 | |
1a84b99c | 215 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
4e2ce405 YL |
216 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
217 | ||
218 | if (ret) | |
219 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); | |
220 | ||
221 | return ret; | |
f18e9625 KK |
222 | } |
223 | ||
bffe4f72 | 224 | static void __pcie_wait_link_active(struct controller *ctrl, bool active) |
f18e9625 KK |
225 | { |
226 | int timeout = 1000; | |
227 | ||
4703389f | 228 | if (pciehp_check_link_active(ctrl) == active) |
f18e9625 KK |
229 | return; |
230 | while (timeout > 0) { | |
231 | msleep(10); | |
232 | timeout -= 10; | |
4703389f | 233 | if (pciehp_check_link_active(ctrl) == active) |
f18e9625 KK |
234 | return; |
235 | } | |
bffe4f72 YL |
236 | ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", |
237 | active ? "set" : "cleared"); | |
238 | } | |
239 | ||
240 | static void pcie_wait_link_active(struct controller *ctrl) | |
241 | { | |
242 | __pcie_wait_link_active(ctrl, true); | |
243 | } | |
244 | ||
2f5d8e4f YL |
245 | static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) |
246 | { | |
247 | u32 l; | |
248 | int count = 0; | |
249 | int delay = 1000, step = 20; | |
250 | bool found = false; | |
251 | ||
252 | do { | |
253 | found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0); | |
254 | count++; | |
255 | ||
256 | if (found) | |
257 | break; | |
258 | ||
259 | msleep(step); | |
260 | delay -= step; | |
261 | } while (delay > 0); | |
262 | ||
263 | if (count > 1 && pciehp_debug) | |
264 | printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n", | |
265 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
266 | PCI_FUNC(devfn), count, step, l); | |
267 | ||
268 | return found; | |
269 | } | |
270 | ||
82a9e79e | 271 | int pciehp_check_link_status(struct controller *ctrl) |
1da177e4 | 272 | { |
cd84d340 | 273 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1a84b99c | 274 | bool found; |
1da177e4 | 275 | u16 lnk_status; |
1da177e4 | 276 | |
f18e9625 KK |
277 | /* |
278 | * Data Link Layer Link Active Reporting must be capable for | |
279 | * hot-plug capable downstream port. But old controller might | |
280 | * not implement it. In this case, we wait for 1000 ms. | |
281 | */ | |
0cab0841 | 282 | if (ctrl->link_active_reporting) |
f18e9625 | 283 | pcie_wait_link_active(ctrl); |
0cab0841 | 284 | else |
f18e9625 KK |
285 | msleep(1000); |
286 | ||
2f5d8e4f YL |
287 | /* wait 100ms before read pci conf, and try in 1s */ |
288 | msleep(100); | |
289 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | |
290 | PCI_DEVFN(0, 0)); | |
0027cb3e | 291 | |
1a84b99c | 292 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
7f2feec1 | 293 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
294 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
295 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 296 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1a84b99c | 297 | return -1; |
1da177e4 LT |
298 | } |
299 | ||
fdbd3ce9 YL |
300 | pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); |
301 | ||
1a84b99c BH |
302 | if (!found) |
303 | return -1; | |
2f5d8e4f | 304 | |
1a84b99c | 305 | return 0; |
1da177e4 LT |
306 | } |
307 | ||
7f822999 YL |
308 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
309 | { | |
cd84d340 | 310 | struct pci_dev *pdev = ctrl_dev(ctrl); |
7f822999 | 311 | u16 lnk_ctrl; |
7f822999 | 312 | |
1a84b99c | 313 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); |
7f822999 YL |
314 | |
315 | if (enable) | |
316 | lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; | |
317 | else | |
318 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; | |
319 | ||
1a84b99c | 320 | pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); |
7f822999 | 321 | ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); |
1a84b99c | 322 | return 0; |
7f822999 YL |
323 | } |
324 | ||
325 | static int pciehp_link_enable(struct controller *ctrl) | |
326 | { | |
327 | return __pciehp_link_set(ctrl, true); | |
328 | } | |
329 | ||
6dae6202 | 330 | void pciehp_get_attention_status(struct slot *slot, u8 *status) |
1da177e4 | 331 | { |
48fe3915 | 332 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 333 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 334 | u16 slot_ctrl; |
1da177e4 | 335 | |
1a84b99c | 336 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
337 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, |
338 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 339 | |
e7b4f0d7 BH |
340 | switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) { |
341 | case PCI_EXP_SLTCTL_ATTN_IND_ON: | |
1da177e4 LT |
342 | *status = 1; /* On */ |
343 | break; | |
e7b4f0d7 | 344 | case PCI_EXP_SLTCTL_ATTN_IND_BLINK: |
1da177e4 LT |
345 | *status = 2; /* Blink */ |
346 | break; | |
e7b4f0d7 | 347 | case PCI_EXP_SLTCTL_ATTN_IND_OFF: |
1da177e4 LT |
348 | *status = 0; /* Off */ |
349 | break; | |
350 | default: | |
351 | *status = 0xFF; | |
352 | break; | |
353 | } | |
1da177e4 LT |
354 | } |
355 | ||
6dae6202 | 356 | void pciehp_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 357 | { |
48fe3915 | 358 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 359 | struct pci_dev *pdev = ctrl_dev(ctrl); |
1da177e4 | 360 | u16 slot_ctrl; |
1da177e4 | 361 | |
1a84b99c | 362 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
1518c17a KK |
363 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, |
364 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); | |
1da177e4 | 365 | |
e7b4f0d7 BH |
366 | switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) { |
367 | case PCI_EXP_SLTCTL_PWR_ON: | |
368 | *status = 1; /* On */ | |
1da177e4 | 369 | break; |
e7b4f0d7 BH |
370 | case PCI_EXP_SLTCTL_PWR_OFF: |
371 | *status = 0; /* Off */ | |
1da177e4 LT |
372 | break; |
373 | default: | |
374 | *status = 0xFF; | |
375 | break; | |
376 | } | |
1da177e4 LT |
377 | } |
378 | ||
6dae6202 | 379 | void pciehp_get_latch_status(struct slot *slot, u8 *status) |
1da177e4 | 380 | { |
1a84b99c | 381 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 382 | u16 slot_status; |
1da177e4 | 383 | |
1a84b99c | 384 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 385 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
386 | } |
387 | ||
6dae6202 | 388 | void pciehp_get_adapter_status(struct slot *slot, u8 *status) |
1da177e4 | 389 | { |
1a84b99c | 390 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 391 | u16 slot_status; |
1da177e4 | 392 | |
1a84b99c | 393 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 394 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
395 | } |
396 | ||
82a9e79e | 397 | int pciehp_query_power_fault(struct slot *slot) |
1da177e4 | 398 | { |
1a84b99c | 399 | struct pci_dev *pdev = ctrl_dev(slot->ctrl); |
1da177e4 | 400 | u16 slot_status; |
1da177e4 | 401 | |
1a84b99c | 402 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
322162a7 | 403 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
404 | } |
405 | ||
6dae6202 | 406 | void pciehp_set_attention_status(struct slot *slot, u8 value) |
1da177e4 | 407 | { |
48fe3915 | 408 | struct controller *ctrl = slot->ctrl; |
f4778364 | 409 | u16 slot_cmd; |
1da177e4 | 410 | |
af9ab791 BH |
411 | if (!ATTN_LED(ctrl)) |
412 | return; | |
413 | ||
1da177e4 | 414 | switch (value) { |
445f7985 | 415 | case 0 : /* turn off */ |
e7b4f0d7 | 416 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF; |
445f7985 KK |
417 | break; |
418 | case 1: /* turn on */ | |
e7b4f0d7 | 419 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON; |
445f7985 KK |
420 | break; |
421 | case 2: /* turn blink */ | |
e7b4f0d7 | 422 | slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK; |
445f7985 KK |
423 | break; |
424 | default: | |
6dae6202 | 425 | return; |
1da177e4 | 426 | } |
1518c17a KK |
427 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
428 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); | |
e7b4f0d7 | 429 | pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); |
1da177e4 LT |
430 | } |
431 | ||
82a9e79e | 432 | void pciehp_green_led_on(struct slot *slot) |
1da177e4 | 433 | { |
48fe3915 | 434 | struct controller *ctrl = slot->ctrl; |
71ad556d | 435 | |
af9ab791 BH |
436 | if (!PWR_LED(ctrl)) |
437 | return; | |
438 | ||
e7b4f0d7 | 439 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC); |
1518c17a | 440 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
441 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
442 | PCI_EXP_SLTCTL_PWR_IND_ON); | |
1da177e4 LT |
443 | } |
444 | ||
82a9e79e | 445 | void pciehp_green_led_off(struct slot *slot) |
1da177e4 | 446 | { |
48fe3915 | 447 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 448 | |
af9ab791 BH |
449 | if (!PWR_LED(ctrl)) |
450 | return; | |
451 | ||
e7b4f0d7 | 452 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC); |
1518c17a | 453 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
454 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
455 | PCI_EXP_SLTCTL_PWR_IND_OFF); | |
1da177e4 LT |
456 | } |
457 | ||
82a9e79e | 458 | void pciehp_green_led_blink(struct slot *slot) |
1da177e4 | 459 | { |
48fe3915 | 460 | struct controller *ctrl = slot->ctrl; |
71ad556d | 461 | |
af9ab791 BH |
462 | if (!PWR_LED(ctrl)) |
463 | return; | |
464 | ||
e7b4f0d7 | 465 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC); |
1518c17a | 466 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
467 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
468 | PCI_EXP_SLTCTL_PWR_IND_BLINK); | |
1da177e4 LT |
469 | } |
470 | ||
82a9e79e | 471 | int pciehp_power_on_slot(struct slot * slot) |
1da177e4 | 472 | { |
48fe3915 | 473 | struct controller *ctrl = slot->ctrl; |
cd84d340 | 474 | struct pci_dev *pdev = ctrl_dev(ctrl); |
f4778364 | 475 | u16 slot_status; |
1a84b99c | 476 | int retval; |
1da177e4 | 477 | |
5a49f203 | 478 | /* Clear sticky power-fault bit from previous power failures */ |
1a84b99c | 479 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
2f2ed41c BH |
480 | if (slot_status & PCI_EXP_SLTSTA_PFD) |
481 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
482 | PCI_EXP_SLTSTA_PFD); | |
5651c48c | 483 | ctrl->power_fault_detected = 0; |
1da177e4 | 484 | |
e7b4f0d7 | 485 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); |
1518c17a | 486 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
487 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
488 | PCI_EXP_SLTCTL_PWR_ON); | |
1da177e4 | 489 | |
2debd928 YL |
490 | retval = pciehp_link_enable(ctrl); |
491 | if (retval) | |
492 | ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); | |
493 | ||
1da177e4 LT |
494 | return retval; |
495 | } | |
496 | ||
6dae6202 | 497 | void pciehp_power_off_slot(struct slot * slot) |
1da177e4 | 498 | { |
48fe3915 | 499 | struct controller *ctrl = slot->ctrl; |
f1050a35 | 500 | |
e7b4f0d7 | 501 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); |
1518c17a | 502 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, |
e7b4f0d7 BH |
503 | pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, |
504 | PCI_EXP_SLTCTL_PWR_OFF); | |
1da177e4 LT |
505 | } |
506 | ||
48fe3915 | 507 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 508 | { |
48fe3915 | 509 | struct controller *ctrl = (struct controller *)dev_id; |
cd84d340 | 510 | struct pci_dev *pdev = ctrl_dev(ctrl); |
8720d27d | 511 | struct slot *slot = ctrl->slot; |
c6b069e9 | 512 | u16 detected, intr_loc; |
1da177e4 | 513 | |
c6b069e9 KK |
514 | /* |
515 | * In order to guarantee that all interrupt events are | |
516 | * serviced, we need to re-inspect Slot Status register after | |
517 | * clearing what is presumed to be the last pending interrupt. | |
518 | */ | |
519 | intr_loc = 0; | |
520 | do { | |
1a84b99c | 521 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected); |
1da177e4 | 522 | |
322162a7 KK |
523 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
524 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
e48f1b67 | 525 | PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC); |
81b840cd | 526 | detected &= ~intr_loc; |
c6b069e9 KK |
527 | intr_loc |= detected; |
528 | if (!intr_loc) | |
1da177e4 | 529 | return IRQ_NONE; |
1a84b99c BH |
530 | if (detected) |
531 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | |
532 | intr_loc); | |
c6b069e9 | 533 | } while (detected); |
71ad556d | 534 | |
7f2feec1 | 535 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 536 | |
c6b069e9 | 537 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 538 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 539 | ctrl->cmd_busy = 0; |
2d32a9ae | 540 | smp_mb(); |
d737bdc1 | 541 | wake_up(&ctrl->queue); |
1da177e4 LT |
542 | } |
543 | ||
322162a7 | 544 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
545 | return IRQ_HANDLED; |
546 | ||
c6b069e9 | 547 | /* Check MRL Sensor Changed */ |
322162a7 | 548 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
8720d27d | 549 | pciehp_handle_switch_change(slot); |
48fe3915 | 550 | |
c6b069e9 | 551 | /* Check Attention Button Pressed */ |
322162a7 | 552 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
8720d27d | 553 | pciehp_handle_attention_button(slot); |
48fe3915 | 554 | |
c6b069e9 | 555 | /* Check Presence Detect Changed */ |
322162a7 | 556 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
8720d27d | 557 | pciehp_handle_presence_change(slot); |
48fe3915 | 558 | |
c6b069e9 | 559 | /* Check Power Fault Detected */ |
99f0169c KK |
560 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
561 | ctrl->power_fault_detected = 1; | |
8720d27d | 562 | pciehp_handle_power_fault(slot); |
99f0169c | 563 | } |
e48f1b67 RJ |
564 | |
565 | if (intr_loc & PCI_EXP_SLTSTA_DLLSC) | |
566 | pciehp_handle_linkstate_change(slot); | |
567 | ||
1da177e4 LT |
568 | return IRQ_HANDLED; |
569 | } | |
570 | ||
6dae6202 | 571 | void pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 572 | { |
c27fb883 | 573 | u16 cmd, mask; |
1da177e4 | 574 | |
5651c48c KK |
575 | /* |
576 | * TBD: Power fault detected software notification support. | |
577 | * | |
578 | * Power fault detected software notification is not enabled | |
579 | * now, because it caused power fault detected interrupt storm | |
580 | * on some machines. On those machines, power fault detected | |
581 | * bit in the slot status register was set again immediately | |
582 | * when it is cleared in the interrupt service routine, and | |
583 | * next power fault detected interrupt was notified again. | |
584 | */ | |
4f854f2a RJ |
585 | |
586 | /* | |
587 | * Always enable link events: thus link-up and link-down shall | |
588 | * always be treated as hotplug and unplug respectively. Enable | |
589 | * presence detect only if Attention Button is not present. | |
590 | */ | |
591 | cmd = PCI_EXP_SLTCTL_DLLSCE; | |
ae416e6b | 592 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 593 | cmd |= PCI_EXP_SLTCTL_ABPE; |
4f854f2a RJ |
594 | else |
595 | cmd |= PCI_EXP_SLTCTL_PDCE; | |
ae416e6b | 596 | if (MRL_SENS(ctrl)) |
322162a7 | 597 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 598 | if (!pciehp_poll_mode) |
322162a7 | 599 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 600 | |
322162a7 KK |
601 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
602 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
4f854f2a RJ |
603 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
604 | PCI_EXP_SLTCTL_DLLSCE); | |
c27fb883 | 605 | |
6dae6202 | 606 | pcie_write_cmd(ctrl, cmd, mask); |
c4635eb0 KK |
607 | } |
608 | ||
609 | static void pcie_disable_notification(struct controller *ctrl) | |
610 | { | |
611 | u16 mask; | |
6dae6202 | 612 | |
322162a7 KK |
613 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
614 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
f22daf1f KK |
615 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE | |
616 | PCI_EXP_SLTCTL_DLLSCE); | |
6dae6202 | 617 | pcie_write_cmd(ctrl, 0, mask); |
c4635eb0 KK |
618 | } |
619 | ||
2e35afae AW |
620 | /* |
621 | * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary | |
06a8d89a RJ |
622 | * bus reset of the bridge, but if the slot supports surprise removal (or |
623 | * link state change based hotplug), we need to disable presence detection | |
624 | * (or link state notifications) around the bus reset and clear any spurious | |
2e35afae AW |
625 | * events after. |
626 | */ | |
627 | int pciehp_reset_slot(struct slot *slot, int probe) | |
628 | { | |
629 | struct controller *ctrl = slot->ctrl; | |
cd84d340 | 630 | struct pci_dev *pdev = ctrl_dev(ctrl); |
06a8d89a | 631 | u16 stat_mask = 0, ctrl_mask = 0; |
2e35afae AW |
632 | |
633 | if (probe) | |
634 | return 0; | |
635 | ||
06a8d89a RJ |
636 | if (HP_SUPR_RM(ctrl) && !ATTN_BUTTN(ctrl)) { |
637 | ctrl_mask |= PCI_EXP_SLTCTL_PDCE; | |
638 | stat_mask |= PCI_EXP_SLTSTA_PDC; | |
2e35afae | 639 | } |
06a8d89a RJ |
640 | ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE; |
641 | stat_mask |= PCI_EXP_SLTSTA_DLLSC; | |
642 | ||
643 | pcie_write_cmd(ctrl, 0, ctrl_mask); | |
644 | if (pciehp_poll_mode) | |
645 | del_timer_sync(&ctrl->poll_timer); | |
2e35afae AW |
646 | |
647 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); | |
648 | ||
06a8d89a RJ |
649 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); |
650 | pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask); | |
651 | if (pciehp_poll_mode) | |
652 | int_poll_timeout(ctrl->poll_timer.data); | |
2e35afae AW |
653 | |
654 | return 0; | |
655 | } | |
656 | ||
dbc7e1e5 | 657 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
658 | { |
659 | if (pciehp_request_irq(ctrl)) | |
660 | return -1; | |
6dae6202 | 661 | pcie_enable_notification(ctrl); |
dbc7e1e5 | 662 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
663 | return 0; |
664 | } | |
665 | ||
666 | static void pcie_shutdown_notification(struct controller *ctrl) | |
667 | { | |
dbc7e1e5 EB |
668 | if (ctrl->notification_enabled) { |
669 | pcie_disable_notification(ctrl); | |
670 | pciehp_free_irq(ctrl); | |
671 | ctrl->notification_enabled = 0; | |
672 | } | |
c4635eb0 KK |
673 | } |
674 | ||
c4635eb0 KK |
675 | static int pcie_init_slot(struct controller *ctrl) |
676 | { | |
677 | struct slot *slot; | |
678 | ||
679 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
680 | if (!slot) | |
681 | return -ENOMEM; | |
682 | ||
d8537548 | 683 | slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); |
c2be6f93 YW |
684 | if (!slot->wq) |
685 | goto abort; | |
686 | ||
c4635eb0 | 687 | slot->ctrl = ctrl; |
c4635eb0 | 688 | mutex_init(&slot->lock); |
50b52fde | 689 | mutex_init(&slot->hotplug_lock); |
c4635eb0 | 690 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); |
8720d27d | 691 | ctrl->slot = slot; |
1da177e4 | 692 | return 0; |
c2be6f93 YW |
693 | abort: |
694 | kfree(slot); | |
695 | return -ENOMEM; | |
1da177e4 | 696 | } |
08e7a7d2 | 697 | |
c4635eb0 KK |
698 | static void pcie_cleanup_slot(struct controller *ctrl) |
699 | { | |
8720d27d | 700 | struct slot *slot = ctrl->slot; |
c4635eb0 | 701 | cancel_delayed_work(&slot->work); |
c2be6f93 | 702 | destroy_workqueue(slot->wq); |
c4635eb0 KK |
703 | kfree(slot); |
704 | } | |
705 | ||
2aeeef11 | 706 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 707 | { |
2aeeef11 KK |
708 | int i; |
709 | u16 reg16; | |
385e2491 | 710 | struct pci_dev *pdev = ctrl->pcie->port; |
08e7a7d2 | 711 | |
2aeeef11 KK |
712 | if (!pciehp_debug) |
713 | return; | |
08e7a7d2 | 714 | |
7f2feec1 TI |
715 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
716 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
717 | pci_name(pdev), pdev->irq); | |
718 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
719 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
720 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
721 | pdev->subsystem_device); | |
722 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
723 | pdev->subsystem_vendor); | |
1518c17a KK |
724 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", |
725 | pci_pcie_cap(pdev)); | |
2aeeef11 KK |
726 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
727 | if (!pci_resource_len(pdev, i)) | |
728 | continue; | |
e1944c6b BH |
729 | ctrl_info(ctrl, " PCI resource [%d] : %pR\n", |
730 | i, &pdev->resource[i]); | |
08e7a7d2 | 731 | } |
7f2feec1 | 732 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
d54798f0 | 733 | ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); |
7f2feec1 TI |
734 | ctrl_info(ctrl, " Attention Button : %3s\n", |
735 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
736 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
737 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
738 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
739 | MRL_SENS(ctrl) ? "yes" : "no"); | |
740 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
741 | ATTN_LED(ctrl) ? "yes" : "no"); | |
742 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
743 | PWR_LED(ctrl) ? "yes" : "no"); | |
744 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
745 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
746 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
747 | EMI(ctrl) ? "yes" : "no"); | |
748 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
749 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
cd84d340 | 750 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 751 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
cd84d340 | 752 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 753 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 754 | } |
08e7a7d2 | 755 | |
afe2478f BH |
756 | #define FLAG(x,y) (((x) & (y)) ? '+' : '-') |
757 | ||
c4635eb0 | 758 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 759 | { |
c4635eb0 | 760 | struct controller *ctrl; |
f18e9625 | 761 | u32 slot_cap, link_cap; |
2aeeef11 | 762 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 763 | |
c4635eb0 KK |
764 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
765 | if (!ctrl) { | |
18b341b7 | 766 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
767 | goto abort; |
768 | } | |
f7a10e32 | 769 | ctrl->pcie = dev; |
1a84b99c | 770 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); |
2aeeef11 | 771 | ctrl->slot_cap = slot_cap; |
08e7a7d2 | 772 | mutex_init(&ctrl->ctrl_lock); |
08e7a7d2 | 773 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 774 | dbg_ctrl(ctrl); |
5808639b KK |
775 | /* |
776 | * Controller doesn't notify of command completion if the "No | |
777 | * Command Completed Support" bit is set in Slot Capability | |
778 | * register or the controller supports none of power | |
779 | * controller, attention led, power led and EMI. | |
780 | */ | |
781 | if (NO_CMD_CMPL(ctrl) || | |
782 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
783 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 784 | |
f18e9625 | 785 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
1a84b99c | 786 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap); |
322162a7 | 787 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
788 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
789 | ctrl->link_active_reporting = 1; | |
790 | } | |
791 | ||
c4635eb0 | 792 | /* Clear all remaining event bits in Slot Status register */ |
df72648c BH |
793 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
794 | PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | | |
795 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
796 | PCI_EXP_SLTSTA_CC); | |
08e7a7d2 | 797 | |
f7625980 | 798 | /* Disable software notification */ |
c4635eb0 | 799 | pcie_disable_notification(ctrl); |
ecdde939 | 800 | |
afe2478f BH |
801 | ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n", |
802 | (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19, | |
803 | FLAG(slot_cap, PCI_EXP_SLTCAP_ABP), | |
804 | FLAG(slot_cap, PCI_EXP_SLTCAP_AIP), | |
805 | FLAG(slot_cap, PCI_EXP_SLTCAP_PIP), | |
806 | FLAG(slot_cap, PCI_EXP_SLTCAP_PCP), | |
807 | FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP), | |
808 | FLAG(slot_cap, PCI_EXP_SLTCAP_EIP), | |
809 | FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS), | |
810 | FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC)); | |
c4635eb0 KK |
811 | |
812 | if (pcie_init_slot(ctrl)) | |
813 | goto abort_ctrl; | |
2aeeef11 | 814 | |
c4635eb0 KK |
815 | return ctrl; |
816 | ||
c4635eb0 KK |
817 | abort_ctrl: |
818 | kfree(ctrl); | |
08e7a7d2 | 819 | abort: |
c4635eb0 KK |
820 | return NULL; |
821 | } | |
822 | ||
82a9e79e | 823 | void pciehp_release_ctrl(struct controller *ctrl) |
c4635eb0 KK |
824 | { |
825 | pcie_shutdown_notification(ctrl); | |
826 | pcie_cleanup_slot(ctrl); | |
c4635eb0 | 827 | kfree(ctrl); |
08e7a7d2 | 828 | } |