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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
1da177e4 LT |
45 | struct ctrl_reg { |
46 | u8 cap_id; | |
47 | u8 nxt_ptr; | |
48 | u16 cap_reg; | |
49 | u32 dev_cap; | |
50 | u16 dev_ctrl; | |
51 | u16 dev_status; | |
52 | u32 lnk_cap; | |
53 | u16 lnk_ctrl; | |
54 | u16 lnk_status; | |
55 | u32 slot_cap; | |
56 | u16 slot_ctrl; | |
57 | u16 slot_status; | |
58 | u16 root_ctrl; | |
59 | u16 rsvp; | |
60 | u32 root_status; | |
61 | } __attribute__ ((packed)); | |
62 | ||
63 | /* offsets to the controller registers based on the above structure layout */ | |
64 | enum ctrl_offsets { | |
65 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
66 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
67 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
68 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
69 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
70 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
71 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
72 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
73 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
74 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
75 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
76 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
77 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
78 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
79 | }; | |
1da177e4 | 80 | |
a0f018da KK |
81 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
82 | { | |
83 | struct pci_dev *dev = ctrl->pci_dev; | |
84 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); | |
85 | } | |
86 | ||
87 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
88 | { | |
89 | struct pci_dev *dev = ctrl->pci_dev; | |
90 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); | |
91 | } | |
92 | ||
93 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
94 | { | |
95 | struct pci_dev *dev = ctrl->pci_dev; | |
96 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); | |
97 | } | |
98 | ||
99 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
100 | { | |
101 | struct pci_dev *dev = ctrl->pci_dev; | |
102 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); | |
103 | } | |
1da177e4 LT |
104 | |
105 | /* Field definitions in PCI Express Capabilities Register */ | |
106 | #define CAP_VER 0x000F | |
107 | #define DEV_PORT_TYPE 0x00F0 | |
108 | #define SLOT_IMPL 0x0100 | |
109 | #define MSG_NUM 0x3E00 | |
110 | ||
111 | /* Device or Port Type */ | |
112 | #define NAT_ENDPT 0x00 | |
113 | #define LEG_ENDPT 0x01 | |
114 | #define ROOT_PORT 0x04 | |
115 | #define UP_STREAM 0x05 | |
116 | #define DN_STREAM 0x06 | |
117 | #define PCIE_PCI_BRDG 0x07 | |
118 | #define PCI_PCIE_BRDG 0x10 | |
119 | ||
120 | /* Field definitions in Device Capabilities Register */ | |
121 | #define DATTN_BUTTN_PRSN 0x1000 | |
122 | #define DATTN_LED_PRSN 0x2000 | |
123 | #define DPWR_LED_PRSN 0x4000 | |
124 | ||
125 | /* Field definitions in Link Capabilities Register */ | |
126 | #define MAX_LNK_SPEED 0x000F | |
127 | #define MAX_LNK_WIDTH 0x03F0 | |
128 | ||
129 | /* Link Width Encoding */ | |
130 | #define LNK_X1 0x01 | |
131 | #define LNK_X2 0x02 | |
71ad556d | 132 | #define LNK_X4 0x04 |
1da177e4 LT |
133 | #define LNK_X8 0x08 |
134 | #define LNK_X12 0x0C | |
71ad556d | 135 | #define LNK_X16 0x10 |
1da177e4 LT |
136 | #define LNK_X32 0x20 |
137 | ||
138 | /*Field definitions of Link Status Register */ | |
139 | #define LNK_SPEED 0x000F | |
140 | #define NEG_LINK_WD 0x03F0 | |
141 | #define LNK_TRN_ERR 0x0400 | |
142 | #define LNK_TRN 0x0800 | |
143 | #define SLOT_CLK_CONF 0x1000 | |
144 | ||
145 | /* Field definitions in Slot Capabilities Register */ | |
146 | #define ATTN_BUTTN_PRSN 0x00000001 | |
147 | #define PWR_CTRL_PRSN 0x00000002 | |
148 | #define MRL_SENS_PRSN 0x00000004 | |
149 | #define ATTN_LED_PRSN 0x00000008 | |
150 | #define PWR_LED_PRSN 0x00000010 | |
151 | #define HP_SUPR_RM_SUP 0x00000020 | |
152 | #define HP_CAP 0x00000040 | |
153 | #define SLOT_PWR_VALUE 0x000003F8 | |
154 | #define SLOT_PWR_LIMIT 0x00000C00 | |
155 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
156 | ||
157 | /* Field definitions in Slot Control Register */ | |
158 | #define ATTN_BUTTN_ENABLE 0x0001 | |
159 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
160 | #define MRL_DETECT_ENABLE 0x0004 | |
161 | #define PRSN_DETECT_ENABLE 0x0008 | |
162 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
163 | #define HP_INTR_ENABLE 0x0020 | |
164 | #define ATTN_LED_CTRL 0x00C0 | |
165 | #define PWR_LED_CTRL 0x0300 | |
166 | #define PWR_CTRL 0x0400 | |
34d03419 | 167 | #define EMI_CTRL 0x0800 |
1da177e4 LT |
168 | |
169 | /* Attention indicator and Power indicator states */ | |
170 | #define LED_ON 0x01 | |
171 | #define LED_BLINK 0x10 | |
172 | #define LED_OFF 0x11 | |
173 | ||
174 | /* Power Control Command */ | |
175 | #define POWER_ON 0 | |
176 | #define POWER_OFF 0x0400 | |
177 | ||
34d03419 KCA |
178 | /* EMI Status defines */ |
179 | #define EMI_DISENGAGED 0 | |
180 | #define EMI_ENGAGED 1 | |
181 | ||
1da177e4 LT |
182 | /* Field definitions in Slot Status Register */ |
183 | #define ATTN_BUTTN_PRESSED 0x0001 | |
184 | #define PWR_FAULT_DETECTED 0x0002 | |
185 | #define MRL_SENS_CHANGED 0x0004 | |
186 | #define PRSN_DETECT_CHANGED 0x0008 | |
187 | #define CMD_COMPLETED 0x0010 | |
188 | #define MRL_STATE 0x0020 | |
189 | #define PRSN_STATE 0x0040 | |
34d03419 KCA |
190 | #define EMI_STATE 0x0080 |
191 | #define EMI_STATUS_BIT 7 | |
1da177e4 | 192 | |
48fe3915 KK |
193 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
194 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
195 | |
196 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 197 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 198 | { |
48fe3915 | 199 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 200 | |
1da177e4 | 201 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 202 | pcie_isr(0, ctrl); |
1da177e4 | 203 | |
48fe3915 | 204 | init_timer(&ctrl->poll_timer); |
1da177e4 LT |
205 | if (!pciehp_poll_time) |
206 | pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ | |
207 | ||
48fe3915 | 208 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 212 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 213 | { |
48fe3915 KK |
214 | /* Clamp to sane value */ |
215 | if ((sec <= 0) || (sec > 60)) | |
216 | sec = 2; | |
217 | ||
218 | ctrl->poll_timer.function = &int_poll_timeout; | |
219 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
220 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
221 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
222 | } |
223 | ||
44ef4cef KK |
224 | static inline int pcie_wait_cmd(struct controller *ctrl) |
225 | { | |
262303fe KK |
226 | int retval = 0; |
227 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; | |
228 | unsigned long timeout = msecs_to_jiffies(msecs); | |
229 | int rc; | |
230 | ||
231 | rc = wait_event_interruptible_timeout(ctrl->queue, | |
232 | !ctrl->cmd_busy, timeout); | |
233 | if (!rc) | |
234 | dbg("Command not completed in 1000 msec\n"); | |
235 | else if (rc < 0) { | |
236 | retval = -EINTR; | |
237 | info("Command was interrupted by a signal\n"); | |
238 | } | |
44ef4cef | 239 | |
262303fe | 240 | return retval; |
44ef4cef KK |
241 | } |
242 | ||
f4778364 KK |
243 | /** |
244 | * pcie_write_cmd - Issue controller command | |
245 | * @slot: slot to which the command is issued | |
246 | * @cmd: command value written to slot control register | |
247 | * @mask: bitmask of slot control register to be modified | |
248 | */ | |
249 | static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask) | |
1da177e4 | 250 | { |
48fe3915 | 251 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
252 | int retval = 0; |
253 | u16 slot_status; | |
f4778364 KK |
254 | u16 slot_ctrl; |
255 | unsigned long flags; | |
1da177e4 | 256 | |
44ef4cef KK |
257 | mutex_lock(&ctrl->ctrl_lock); |
258 | ||
a0f018da | 259 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 260 | if (retval) { |
a0f018da | 261 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
44ef4cef | 262 | goto out; |
a0f018da KK |
263 | } |
264 | ||
71ad556d | 265 | if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { |
44ef4cef KK |
266 | /* After 1 sec and CMD_COMPLETED still not set, just |
267 | proceed forward to issue the next command according | |
268 | to spec. Just print out the error message */ | |
269 | dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", | |
270 | __FUNCTION__); | |
1da177e4 LT |
271 | } |
272 | ||
f4778364 KK |
273 | spin_lock_irqsave(&ctrl->lock, flags); |
274 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); | |
1da177e4 | 275 | if (retval) { |
f4778364 KK |
276 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
277 | goto out_spin_unlock; | |
1da177e4 | 278 | } |
1da177e4 | 279 | |
f4778364 KK |
280 | slot_ctrl &= ~mask; |
281 | slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE); | |
282 | ||
283 | ctrl->cmd_busy = 1; | |
284 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); | |
285 | if (retval) | |
286 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); | |
287 | ||
288 | out_spin_unlock: | |
289 | spin_unlock_irqrestore(&ctrl->lock, flags); | |
290 | ||
44ef4cef KK |
291 | /* |
292 | * Wait for command completion. | |
293 | */ | |
f4778364 KK |
294 | if (!retval) |
295 | retval = pcie_wait_cmd(ctrl); | |
44ef4cef KK |
296 | out: |
297 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
298 | return retval; |
299 | } | |
300 | ||
301 | static int hpc_check_lnk_status(struct controller *ctrl) | |
302 | { | |
1da177e4 LT |
303 | u16 lnk_status; |
304 | int retval = 0; | |
305 | ||
a0f018da | 306 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 307 | if (retval) { |
a0f018da | 308 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
309 | return retval; |
310 | } | |
311 | ||
312 | dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status); | |
71ad556d | 313 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
1da177e4 LT |
314 | !(lnk_status & NEG_LINK_WD)) { |
315 | err("%s : Link Training Error occurs \n", __FUNCTION__); | |
316 | retval = -1; | |
317 | return retval; | |
318 | } | |
319 | ||
1da177e4 LT |
320 | return retval; |
321 | } | |
322 | ||
323 | ||
324 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
325 | { | |
48fe3915 | 326 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
327 | u16 slot_ctrl; |
328 | u8 atten_led_state; | |
329 | int retval = 0; | |
1da177e4 | 330 | |
a0f018da | 331 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 332 | if (retval) { |
a0f018da | 333 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
334 | return retval; |
335 | } | |
336 | ||
a0f018da KK |
337 | dbg("%s: SLOTCTRL %x, value read %x\n", |
338 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | |
1da177e4 LT |
339 | |
340 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
341 | ||
342 | switch (atten_led_state) { | |
343 | case 0: | |
344 | *status = 0xFF; /* Reserved */ | |
345 | break; | |
346 | case 1: | |
347 | *status = 1; /* On */ | |
348 | break; | |
349 | case 2: | |
350 | *status = 2; /* Blink */ | |
351 | break; | |
352 | case 3: | |
353 | *status = 0; /* Off */ | |
354 | break; | |
355 | default: | |
356 | *status = 0xFF; | |
357 | break; | |
358 | } | |
359 | ||
1da177e4 LT |
360 | return 0; |
361 | } | |
362 | ||
48fe3915 | 363 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 364 | { |
48fe3915 | 365 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
366 | u16 slot_ctrl; |
367 | u8 pwr_state; | |
368 | int retval = 0; | |
1da177e4 | 369 | |
a0f018da | 370 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 371 | if (retval) { |
a0f018da | 372 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
373 | return retval; |
374 | } | |
a0f018da KK |
375 | dbg("%s: SLOTCTRL %x value read %x\n", |
376 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | |
1da177e4 LT |
377 | |
378 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
379 | ||
380 | switch (pwr_state) { | |
381 | case 0: | |
382 | *status = 1; | |
383 | break; | |
384 | case 1: | |
71ad556d | 385 | *status = 0; |
1da177e4 LT |
386 | break; |
387 | default: | |
388 | *status = 0xFF; | |
389 | break; | |
390 | } | |
391 | ||
1da177e4 LT |
392 | return retval; |
393 | } | |
394 | ||
395 | ||
396 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
397 | { | |
48fe3915 | 398 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
399 | u16 slot_status; |
400 | int retval = 0; | |
401 | ||
a0f018da | 402 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 403 | if (retval) { |
a0f018da | 404 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
405 | return retval; |
406 | } | |
407 | ||
71ad556d | 408 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
1da177e4 | 409 | |
1da177e4 LT |
410 | return 0; |
411 | } | |
412 | ||
413 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
414 | { | |
48fe3915 | 415 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
416 | u16 slot_status; |
417 | u8 card_state; | |
418 | int retval = 0; | |
419 | ||
a0f018da | 420 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 421 | if (retval) { |
a0f018da | 422 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
423 | return retval; |
424 | } | |
425 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
426 | *status = (card_state == 1) ? 1 : 0; | |
427 | ||
1da177e4 LT |
428 | return 0; |
429 | } | |
430 | ||
48fe3915 | 431 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 432 | { |
48fe3915 | 433 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
434 | u16 slot_status; |
435 | u8 pwr_fault; | |
436 | int retval = 0; | |
1da177e4 | 437 | |
a0f018da | 438 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 439 | if (retval) { |
a0f018da | 440 | err("%s: Cannot check for power fault\n", __FUNCTION__); |
1da177e4 LT |
441 | return retval; |
442 | } | |
443 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
71ad556d | 444 | |
8239def1 | 445 | return pwr_fault; |
1da177e4 LT |
446 | } |
447 | ||
34d03419 KCA |
448 | static int hpc_get_emi_status(struct slot *slot, u8 *status) |
449 | { | |
450 | struct controller *ctrl = slot->ctrl; | |
451 | u16 slot_status; | |
452 | int retval = 0; | |
453 | ||
34d03419 KCA |
454 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
455 | if (retval) { | |
456 | err("%s : Cannot check EMI status\n", __FUNCTION__); | |
457 | return retval; | |
458 | } | |
459 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | |
460 | ||
34d03419 KCA |
461 | return retval; |
462 | } | |
463 | ||
464 | static int hpc_toggle_emi(struct slot *slot) | |
465 | { | |
f4778364 KK |
466 | u16 slot_cmd; |
467 | u16 cmd_mask; | |
468 | int rc; | |
34d03419 | 469 | |
f4778364 KK |
470 | slot_cmd = EMI_CTRL; |
471 | cmd_mask = EMI_CTRL; | |
472 | if (!pciehp_poll_mode) { | |
34d03419 | 473 | slot_cmd = slot_cmd | HP_INTR_ENABLE; |
f4778364 KK |
474 | cmd_mask = cmd_mask | HP_INTR_ENABLE; |
475 | } | |
34d03419 | 476 | |
f4778364 | 477 | rc = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
34d03419 | 478 | slot->last_emi_toggle = get_seconds(); |
c8426483 | 479 | |
34d03419 KCA |
480 | return rc; |
481 | } | |
482 | ||
1da177e4 LT |
483 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
484 | { | |
48fe3915 | 485 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
486 | u16 slot_cmd; |
487 | u16 cmd_mask; | |
488 | int rc; | |
1da177e4 | 489 | |
f4778364 | 490 | cmd_mask = ATTN_LED_CTRL; |
1da177e4 LT |
491 | switch (value) { |
492 | case 0 : /* turn off */ | |
f4778364 | 493 | slot_cmd = 0x00C0; |
1da177e4 LT |
494 | break; |
495 | case 1: /* turn on */ | |
f4778364 | 496 | slot_cmd = 0x0040; |
1da177e4 LT |
497 | break; |
498 | case 2: /* turn blink */ | |
f4778364 | 499 | slot_cmd = 0x0080; |
1da177e4 LT |
500 | break; |
501 | default: | |
502 | return -1; | |
503 | } | |
f4778364 KK |
504 | if (!pciehp_poll_mode) { |
505 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
506 | cmd_mask = cmd_mask | HP_INTR_ENABLE; | |
507 | } | |
1da177e4 | 508 | |
f4778364 | 509 | rc = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
a0f018da KK |
510 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
511 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
71ad556d | 512 | |
1da177e4 LT |
513 | return rc; |
514 | } | |
515 | ||
516 | ||
517 | static void hpc_set_green_led_on(struct slot *slot) | |
518 | { | |
48fe3915 | 519 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 520 | u16 slot_cmd; |
f4778364 | 521 | u16 cmd_mask; |
71ad556d | 522 | |
f4778364 KK |
523 | slot_cmd = 0x0100; |
524 | cmd_mask = PWR_LED_CTRL; | |
525 | if (!pciehp_poll_mode) { | |
526 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
527 | cmd_mask = cmd_mask | HP_INTR_ENABLE; | |
1da177e4 | 528 | } |
1da177e4 | 529 | |
f4778364 | 530 | pcie_write_cmd(slot, slot_cmd, cmd_mask); |
1da177e4 | 531 | |
a0f018da KK |
532 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
533 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
534 | } |
535 | ||
536 | static void hpc_set_green_led_off(struct slot *slot) | |
537 | { | |
48fe3915 | 538 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 539 | u16 slot_cmd; |
f4778364 | 540 | u16 cmd_mask; |
1da177e4 | 541 | |
f4778364 KK |
542 | slot_cmd = 0x0300; |
543 | cmd_mask = PWR_LED_CTRL; | |
544 | if (!pciehp_poll_mode) { | |
545 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
546 | cmd_mask = cmd_mask | HP_INTR_ENABLE; | |
1da177e4 | 547 | } |
1da177e4 | 548 | |
f4778364 | 549 | pcie_write_cmd(slot, slot_cmd, cmd_mask); |
a0f018da KK |
550 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
551 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
552 | } |
553 | ||
554 | static void hpc_set_green_led_blink(struct slot *slot) | |
555 | { | |
48fe3915 | 556 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 557 | u16 slot_cmd; |
f4778364 | 558 | u16 cmd_mask; |
71ad556d | 559 | |
f4778364 KK |
560 | slot_cmd = 0x0200; |
561 | cmd_mask = PWR_LED_CTRL; | |
562 | if (!pciehp_poll_mode) { | |
563 | slot_cmd = slot_cmd | HP_INTR_ENABLE; | |
564 | cmd_mask = cmd_mask | HP_INTR_ENABLE; | |
1da177e4 | 565 | } |
1da177e4 | 566 | |
f4778364 | 567 | pcie_write_cmd(slot, slot_cmd, cmd_mask); |
1da177e4 | 568 | |
a0f018da KK |
569 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
570 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 LT |
571 | } |
572 | ||
1da177e4 LT |
573 | static void hpc_release_ctlr(struct controller *ctrl) |
574 | { | |
48fe3915 KK |
575 | if (pciehp_poll_mode) |
576 | del_timer(&ctrl->poll_timer); | |
577 | else | |
578 | free_irq(ctrl->pci_dev->irq, ctrl); | |
1da177e4 | 579 | |
5d386e1a KK |
580 | /* |
581 | * If this is the last controller to be released, destroy the | |
582 | * pciehp work queue | |
583 | */ | |
584 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
585 | destroy_workqueue(pciehp_wq); | |
1da177e4 LT |
586 | } |
587 | ||
588 | static int hpc_power_on_slot(struct slot * slot) | |
589 | { | |
48fe3915 | 590 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 591 | u16 slot_cmd; |
f4778364 KK |
592 | u16 cmd_mask; |
593 | u16 slot_status; | |
1da177e4 LT |
594 | int retval = 0; |
595 | ||
1da177e4 | 596 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
1da177e4 | 597 | |
5a49f203 | 598 | /* Clear sticky power-fault bit from previous power failures */ |
a0f018da KK |
599 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
600 | if (retval) { | |
601 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); | |
602 | return retval; | |
603 | } | |
5a49f203 | 604 | slot_status &= PWR_FAULT_DETECTED; |
a0f018da KK |
605 | if (slot_status) { |
606 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); | |
607 | if (retval) { | |
608 | err("%s: Cannot write to SLOTSTATUS register\n", | |
609 | __FUNCTION__); | |
610 | return retval; | |
611 | } | |
612 | } | |
1da177e4 | 613 | |
f4778364 KK |
614 | slot_cmd = POWER_ON; |
615 | cmd_mask = PWR_CTRL; | |
c7ab337f | 616 | /* Enable detection that we turned off at slot power-off time */ |
f4778364 | 617 | if (!pciehp_poll_mode) { |
c7ab337f TS |
618 | slot_cmd = slot_cmd | |
619 | PWR_FAULT_DETECT_ENABLE | | |
620 | MRL_DETECT_ENABLE | | |
621 | PRSN_DETECT_ENABLE | | |
622 | HP_INTR_ENABLE; | |
f4778364 KK |
623 | cmd_mask = cmd_mask | |
624 | PWR_FAULT_DETECT_ENABLE | | |
625 | MRL_DETECT_ENABLE | | |
626 | PRSN_DETECT_ENABLE | | |
627 | HP_INTR_ENABLE; | |
628 | } | |
1da177e4 | 629 | |
f4778364 | 630 | retval = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
1da177e4 LT |
631 | |
632 | if (retval) { | |
633 | err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd); | |
634 | return -1; | |
635 | } | |
a0f018da KK |
636 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
637 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 | 638 | |
1da177e4 LT |
639 | return retval; |
640 | } | |
641 | ||
642 | static int hpc_power_off_slot(struct slot * slot) | |
643 | { | |
48fe3915 | 644 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 645 | u16 slot_cmd; |
f4778364 | 646 | u16 cmd_mask; |
1da177e4 LT |
647 | int retval = 0; |
648 | ||
1da177e4 | 649 | dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); |
1da177e4 | 650 | |
f4778364 KK |
651 | slot_cmd = POWER_OFF; |
652 | cmd_mask = PWR_CTRL; | |
c7ab337f TS |
653 | /* |
654 | * If we get MRL or presence detect interrupts now, the isr | |
655 | * will notice the sticky power-fault bit too and issue power | |
656 | * indicator change commands. This will lead to an endless loop | |
657 | * of command completions, since the power-fault bit remains on | |
658 | * till the slot is powered on again. | |
659 | */ | |
f4778364 | 660 | if (!pciehp_poll_mode) { |
c7ab337f TS |
661 | slot_cmd = (slot_cmd & |
662 | ~PWR_FAULT_DETECT_ENABLE & | |
663 | ~MRL_DETECT_ENABLE & | |
664 | ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE; | |
f4778364 KK |
665 | cmd_mask = cmd_mask | |
666 | PWR_FAULT_DETECT_ENABLE | | |
667 | MRL_DETECT_ENABLE | | |
668 | PRSN_DETECT_ENABLE | | |
669 | HP_INTR_ENABLE; | |
670 | } | |
1da177e4 | 671 | |
f4778364 | 672 | retval = pcie_write_cmd(slot, slot_cmd, cmd_mask); |
1da177e4 LT |
673 | if (retval) { |
674 | err("%s: Write command failed!\n", __FUNCTION__); | |
675 | return -1; | |
676 | } | |
a0f018da KK |
677 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
678 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); | |
1da177e4 | 679 | |
1da177e4 LT |
680 | return retval; |
681 | } | |
682 | ||
48fe3915 | 683 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 684 | { |
48fe3915 | 685 | struct controller *ctrl = (struct controller *)dev_id; |
1da177e4 LT |
686 | u16 slot_status, intr_detect, intr_loc; |
687 | u16 temp_word; | |
688 | int hp_slot = 0; /* only 1 slot per PCI Express port */ | |
689 | int rc = 0; | |
f4778364 | 690 | unsigned long flags; |
1da177e4 | 691 | |
a0f018da | 692 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 693 | if (rc) { |
a0f018da | 694 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
695 | return IRQ_NONE; |
696 | } | |
697 | ||
698 | intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED | | |
699 | PRSN_DETECT_CHANGED | CMD_COMPLETED ); | |
700 | ||
701 | intr_loc = slot_status & intr_detect; | |
702 | ||
703 | /* Check to see if it was our interrupt */ | |
704 | if ( !intr_loc ) | |
705 | return IRQ_NONE; | |
706 | ||
707 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); | |
708 | /* Mask Hot-plug Interrupt Enable */ | |
709 | if (!pciehp_poll_mode) { | |
f4778364 | 710 | spin_lock_irqsave(&ctrl->lock, flags); |
a0f018da | 711 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1da177e4 | 712 | if (rc) { |
a0f018da KK |
713 | err("%s: Cannot read SLOT_CTRL register\n", |
714 | __FUNCTION__); | |
f4778364 | 715 | spin_unlock_irqrestore(&ctrl->lock, flags); |
1da177e4 LT |
716 | return IRQ_NONE; |
717 | } | |
718 | ||
a0f018da KK |
719 | dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n", |
720 | __FUNCTION__, temp_word); | |
1da177e4 | 721 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; |
a0f018da | 722 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1da177e4 | 723 | if (rc) { |
a0f018da KK |
724 | err("%s: Cannot write to SLOTCTRL register\n", |
725 | __FUNCTION__); | |
f4778364 | 726 | spin_unlock_irqrestore(&ctrl->lock, flags); |
1da177e4 LT |
727 | return IRQ_NONE; |
728 | } | |
f4778364 | 729 | spin_unlock_irqrestore(&ctrl->lock, flags); |
a0f018da KK |
730 | |
731 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | |
1da177e4 | 732 | if (rc) { |
a0f018da KK |
733 | err("%s: Cannot read SLOT_STATUS register\n", |
734 | __FUNCTION__); | |
1da177e4 LT |
735 | return IRQ_NONE; |
736 | } | |
a0f018da KK |
737 | dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n", |
738 | __FUNCTION__, slot_status); | |
71ad556d | 739 | |
1da177e4 LT |
740 | /* Clear command complete interrupt caused by this write */ |
741 | temp_word = 0x1f; | |
a0f018da | 742 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 743 | if (rc) { |
a0f018da KK |
744 | err("%s: Cannot write to SLOTSTATUS register\n", |
745 | __FUNCTION__); | |
1da177e4 LT |
746 | return IRQ_NONE; |
747 | } | |
1da177e4 | 748 | } |
71ad556d | 749 | |
1da177e4 | 750 | if (intr_loc & CMD_COMPLETED) { |
71ad556d KK |
751 | /* |
752 | * Command Complete Interrupt Pending | |
1da177e4 | 753 | */ |
262303fe | 754 | ctrl->cmd_busy = 0; |
1da177e4 LT |
755 | wake_up_interruptible(&ctrl->queue); |
756 | } | |
757 | ||
48fe3915 KK |
758 | if (intr_loc & MRL_SENS_CHANGED) |
759 | pciehp_handle_switch_change(hp_slot, ctrl); | |
760 | ||
761 | if (intr_loc & ATTN_BUTTN_PRESSED) | |
762 | pciehp_handle_attention_button(hp_slot, ctrl); | |
763 | ||
764 | if (intr_loc & PRSN_DETECT_CHANGED) | |
765 | pciehp_handle_presence_change(hp_slot, ctrl); | |
766 | ||
767 | if (intr_loc & PWR_FAULT_DETECTED) | |
768 | pciehp_handle_power_fault(hp_slot, ctrl); | |
1da177e4 LT |
769 | |
770 | /* Clear all events after serving them */ | |
771 | temp_word = 0x1F; | |
a0f018da | 772 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 773 | if (rc) { |
a0f018da | 774 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
775 | return IRQ_NONE; |
776 | } | |
777 | /* Unmask Hot-plug Interrupt Enable */ | |
778 | if (!pciehp_poll_mode) { | |
f4778364 | 779 | spin_lock_irqsave(&ctrl->lock, flags); |
a0f018da | 780 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1da177e4 | 781 | if (rc) { |
a0f018da KK |
782 | err("%s: Cannot read SLOTCTRL register\n", |
783 | __FUNCTION__); | |
f4778364 | 784 | spin_unlock_irqrestore(&ctrl->lock, flags); |
1da177e4 LT |
785 | return IRQ_NONE; |
786 | } | |
787 | ||
788 | dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__); | |
1da177e4 LT |
789 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; |
790 | ||
a0f018da | 791 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1da177e4 | 792 | if (rc) { |
a0f018da KK |
793 | err("%s: Cannot write to SLOTCTRL register\n", |
794 | __FUNCTION__); | |
f4778364 | 795 | spin_unlock_irqrestore(&ctrl->lock, flags); |
1da177e4 LT |
796 | return IRQ_NONE; |
797 | } | |
f4778364 | 798 | spin_unlock_irqrestore(&ctrl->lock, flags); |
a0f018da KK |
799 | |
800 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); | |
1da177e4 | 801 | if (rc) { |
a0f018da KK |
802 | err("%s: Cannot read SLOT_STATUS register\n", |
803 | __FUNCTION__); | |
1da177e4 LT |
804 | return IRQ_NONE; |
805 | } | |
71ad556d | 806 | |
1da177e4 LT |
807 | /* Clear command complete interrupt caused by this write */ |
808 | temp_word = 0x1F; | |
a0f018da | 809 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 810 | if (rc) { |
a0f018da KK |
811 | err("%s: Cannot write to SLOTSTATUS failed\n", |
812 | __FUNCTION__); | |
1da177e4 LT |
813 | return IRQ_NONE; |
814 | } | |
a0f018da KK |
815 | dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n", |
816 | __FUNCTION__, temp_word); | |
1da177e4 | 817 | } |
71ad556d | 818 | |
1da177e4 LT |
819 | return IRQ_HANDLED; |
820 | } | |
821 | ||
822 | static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |
823 | { | |
48fe3915 | 824 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
825 | enum pcie_link_speed lnk_speed; |
826 | u32 lnk_cap; | |
827 | int retval = 0; | |
828 | ||
a0f018da | 829 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 830 | if (retval) { |
a0f018da | 831 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); |
1da177e4 LT |
832 | return retval; |
833 | } | |
834 | ||
835 | switch (lnk_cap & 0x000F) { | |
836 | case 1: | |
837 | lnk_speed = PCIE_2PT5GB; | |
838 | break; | |
839 | default: | |
840 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
841 | break; | |
842 | } | |
843 | ||
844 | *value = lnk_speed; | |
845 | dbg("Max link speed = %d\n", lnk_speed); | |
c8426483 | 846 | |
1da177e4 LT |
847 | return retval; |
848 | } | |
849 | ||
850 | static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value) | |
851 | { | |
48fe3915 | 852 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
853 | enum pcie_link_width lnk_wdth; |
854 | u32 lnk_cap; | |
855 | int retval = 0; | |
856 | ||
a0f018da | 857 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 858 | if (retval) { |
a0f018da | 859 | err("%s: Cannot read LNKCAP register\n", __FUNCTION__); |
1da177e4 LT |
860 | return retval; |
861 | } | |
862 | ||
863 | switch ((lnk_cap & 0x03F0) >> 4){ | |
864 | case 0: | |
865 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
866 | break; | |
867 | case 1: | |
868 | lnk_wdth = PCIE_LNK_X1; | |
869 | break; | |
870 | case 2: | |
871 | lnk_wdth = PCIE_LNK_X2; | |
872 | break; | |
873 | case 4: | |
874 | lnk_wdth = PCIE_LNK_X4; | |
875 | break; | |
876 | case 8: | |
877 | lnk_wdth = PCIE_LNK_X8; | |
878 | break; | |
879 | case 12: | |
880 | lnk_wdth = PCIE_LNK_X12; | |
881 | break; | |
882 | case 16: | |
883 | lnk_wdth = PCIE_LNK_X16; | |
884 | break; | |
885 | case 32: | |
886 | lnk_wdth = PCIE_LNK_X32; | |
887 | break; | |
888 | default: | |
889 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
890 | break; | |
891 | } | |
892 | ||
893 | *value = lnk_wdth; | |
894 | dbg("Max link width = %d\n", lnk_wdth); | |
c8426483 | 895 | |
1da177e4 LT |
896 | return retval; |
897 | } | |
898 | ||
899 | static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value) | |
900 | { | |
48fe3915 | 901 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
902 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
903 | int retval = 0; | |
904 | u16 lnk_status; | |
905 | ||
a0f018da | 906 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 907 | if (retval) { |
a0f018da | 908 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
909 | return retval; |
910 | } | |
911 | ||
912 | switch (lnk_status & 0x0F) { | |
913 | case 1: | |
914 | lnk_speed = PCIE_2PT5GB; | |
915 | break; | |
916 | default: | |
917 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
918 | break; | |
919 | } | |
920 | ||
921 | *value = lnk_speed; | |
922 | dbg("Current link speed = %d\n", lnk_speed); | |
c8426483 | 923 | |
1da177e4 LT |
924 | return retval; |
925 | } | |
926 | ||
927 | static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value) | |
928 | { | |
48fe3915 | 929 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
930 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
931 | int retval = 0; | |
932 | u16 lnk_status; | |
933 | ||
a0f018da | 934 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 935 | if (retval) { |
a0f018da | 936 | err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
937 | return retval; |
938 | } | |
71ad556d | 939 | |
1da177e4 LT |
940 | switch ((lnk_status & 0x03F0) >> 4){ |
941 | case 0: | |
942 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
943 | break; | |
944 | case 1: | |
945 | lnk_wdth = PCIE_LNK_X1; | |
946 | break; | |
947 | case 2: | |
948 | lnk_wdth = PCIE_LNK_X2; | |
949 | break; | |
950 | case 4: | |
951 | lnk_wdth = PCIE_LNK_X4; | |
952 | break; | |
953 | case 8: | |
954 | lnk_wdth = PCIE_LNK_X8; | |
955 | break; | |
956 | case 12: | |
957 | lnk_wdth = PCIE_LNK_X12; | |
958 | break; | |
959 | case 16: | |
960 | lnk_wdth = PCIE_LNK_X16; | |
961 | break; | |
962 | case 32: | |
963 | lnk_wdth = PCIE_LNK_X32; | |
964 | break; | |
965 | default: | |
966 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
967 | break; | |
968 | } | |
969 | ||
970 | *value = lnk_wdth; | |
971 | dbg("Current link width = %d\n", lnk_wdth); | |
c8426483 | 972 | |
1da177e4 LT |
973 | return retval; |
974 | } | |
975 | ||
976 | static struct hpc_ops pciehp_hpc_ops = { | |
977 | .power_on_slot = hpc_power_on_slot, | |
978 | .power_off_slot = hpc_power_off_slot, | |
979 | .set_attention_status = hpc_set_attention_status, | |
980 | .get_power_status = hpc_get_power_status, | |
981 | .get_attention_status = hpc_get_attention_status, | |
982 | .get_latch_status = hpc_get_latch_status, | |
983 | .get_adapter_status = hpc_get_adapter_status, | |
34d03419 KCA |
984 | .get_emi_status = hpc_get_emi_status, |
985 | .toggle_emi = hpc_toggle_emi, | |
1da177e4 LT |
986 | |
987 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
988 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
989 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
990 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
71ad556d | 991 | |
1da177e4 LT |
992 | .query_power_fault = hpc_query_power_fault, |
993 | .green_led_on = hpc_set_green_led_on, | |
994 | .green_led_off = hpc_set_green_led_off, | |
995 | .green_led_blink = hpc_set_green_led_blink, | |
71ad556d | 996 | |
1da177e4 LT |
997 | .release_ctlr = hpc_release_ctlr, |
998 | .check_lnk_status = hpc_check_lnk_status, | |
999 | }; | |
1000 | ||
783c49fc KA |
1001 | #ifdef CONFIG_ACPI |
1002 | int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) | |
1003 | { | |
1004 | acpi_status status; | |
1005 | acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); | |
1006 | struct pci_dev *pdev = dev; | |
1007 | struct pci_bus *parent; | |
b2e6e3ba | 1008 | struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; |
783c49fc KA |
1009 | |
1010 | /* | |
1011 | * Per PCI firmware specification, we should run the ACPI _OSC | |
1012 | * method to get control of hotplug hardware before using it. | |
1013 | * If an _OSC is missing, we look for an OSHP to do the same thing. | |
1014 | * To handle different BIOS behavior, we look for _OSC and OSHP | |
1015 | * within the scope of the hotplug controller and its parents, upto | |
1016 | * the host bridge under which this controller exists. | |
1017 | */ | |
1018 | while (!handle) { | |
1019 | /* | |
1020 | * This hotplug controller was not listed in the ACPI name | |
1021 | * space at all. Try to get acpi handle of parent pci bus. | |
1022 | */ | |
1023 | if (!pdev || !pdev->bus->parent) | |
1024 | break; | |
1025 | parent = pdev->bus->parent; | |
1026 | dbg("Could not find %s in acpi namespace, trying parent\n", | |
1027 | pci_name(pdev)); | |
1028 | if (!parent->self) | |
1029 | /* Parent must be a host bridge */ | |
1030 | handle = acpi_get_pci_rootbridge_handle( | |
1031 | pci_domain_nr(parent), | |
1032 | parent->number); | |
1033 | else | |
1034 | handle = DEVICE_ACPI_HANDLE( | |
1035 | &(parent->self->dev)); | |
1036 | pdev = parent->self; | |
1037 | } | |
1038 | ||
1039 | while (handle) { | |
b2e6e3ba MT |
1040 | acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); |
1041 | dbg("Trying to get hotplug control for %s \n", | |
1042 | (char *)string.pointer); | |
783c49fc | 1043 | status = pci_osc_control_set(handle, |
57d90c02 | 1044 | OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL | |
783c49fc KA |
1045 | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL); |
1046 | if (status == AE_NOT_FOUND) | |
1047 | status = acpi_run_oshp(handle); | |
1048 | if (ACPI_SUCCESS(status)) { | |
1049 | dbg("Gained control for hotplug HW for pci %s (%s)\n", | |
b2e6e3ba | 1050 | pci_name(dev), (char *)string.pointer); |
81b26bca | 1051 | kfree(string.pointer); |
783c49fc KA |
1052 | return 0; |
1053 | } | |
1054 | if (acpi_root_bridge(handle)) | |
1055 | break; | |
1056 | chandle = handle; | |
1057 | status = acpi_get_parent(chandle, &handle); | |
1058 | if (ACPI_FAILURE(status)) | |
1059 | break; | |
1060 | } | |
1061 | ||
1062 | err("Cannot get control of hotplug hardware for pci %s\n", | |
1063 | pci_name(dev)); | |
b2e6e3ba | 1064 | |
81b26bca | 1065 | kfree(string.pointer); |
783c49fc KA |
1066 | return -1; |
1067 | } | |
1068 | #endif | |
1069 | ||
1070 | ||
1071 | ||
ed6cbcf2 | 1072 | int pcie_init(struct controller * ctrl, struct pcie_device *dev) |
1da177e4 | 1073 | { |
1da177e4 | 1074 | int rc; |
1da177e4 LT |
1075 | u16 temp_word; |
1076 | u16 cap_reg; | |
1077 | u16 intr_enable = 0; | |
1078 | u32 slot_cap; | |
75e13178 | 1079 | int cap_base; |
1da177e4 LT |
1080 | u16 slot_status, slot_ctrl; |
1081 | struct pci_dev *pdev; | |
1082 | ||
1da177e4 | 1083 | pdev = dev->port; |
48fe3915 | 1084 | ctrl->pci_dev = pdev; /* save pci_dev in context */ |
1da177e4 | 1085 | |
1a9ed1bf RS |
1086 | dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", |
1087 | __FUNCTION__, pdev->vendor, pdev->device); | |
1da177e4 | 1088 | |
1da177e4 LT |
1089 | if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { |
1090 | dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); | |
1091 | goto abort_free_ctlr; | |
1092 | } | |
1093 | ||
8b245e45 | 1094 | ctrl->cap_base = cap_base; |
1da177e4 | 1095 | |
75e13178 | 1096 | dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base); |
1da177e4 | 1097 | |
a0f018da | 1098 | rc = pciehp_readw(ctrl, CAPREG, &cap_reg); |
1da177e4 | 1099 | if (rc) { |
a0f018da | 1100 | err("%s: Cannot read CAPREG register\n", __FUNCTION__); |
1da177e4 LT |
1101 | goto abort_free_ctlr; |
1102 | } | |
a0f018da KK |
1103 | dbg("%s: CAPREG offset %x cap_reg %x\n", |
1104 | __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg); | |
1da177e4 | 1105 | |
8b245e45 DS |
1106 | if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040) |
1107 | && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { | |
1da177e4 LT |
1108 | dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__); |
1109 | goto abort_free_ctlr; | |
1110 | } | |
1111 | ||
a0f018da | 1112 | rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap); |
1da177e4 | 1113 | if (rc) { |
a0f018da | 1114 | err("%s: Cannot read SLOTCAP register\n", __FUNCTION__); |
1da177e4 LT |
1115 | goto abort_free_ctlr; |
1116 | } | |
a0f018da KK |
1117 | dbg("%s: SLOTCAP offset %x slot_cap %x\n", |
1118 | __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap); | |
1da177e4 LT |
1119 | |
1120 | if (!(slot_cap & HP_CAP)) { | |
1121 | dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); | |
1122 | goto abort_free_ctlr; | |
1123 | } | |
1124 | /* For debugging purpose */ | |
a0f018da | 1125 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 1126 | if (rc) { |
a0f018da | 1127 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
1128 | goto abort_free_ctlr; |
1129 | } | |
a0f018da KK |
1130 | dbg("%s: SLOTSTATUS offset %x slot_status %x\n", |
1131 | __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status); | |
1da177e4 | 1132 | |
a0f018da | 1133 | rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 1134 | if (rc) { |
a0f018da | 1135 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
1136 | goto abort_free_ctlr; |
1137 | } | |
a0f018da KK |
1138 | dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n", |
1139 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); | |
1da177e4 | 1140 | |
1da177e4 LT |
1141 | for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++) |
1142 | if (pci_resource_len(pdev, rc) > 0) | |
1396a8c3 GKH |
1143 | dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc, |
1144 | (unsigned long long)pci_resource_start(pdev, rc), | |
1145 | (unsigned long long)pci_resource_len(pdev, rc)); | |
1da177e4 | 1146 | |
71ad556d | 1147 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, |
1da177e4 LT |
1148 | pdev->subsystem_vendor, pdev->subsystem_device); |
1149 | ||
6aa4cdd0 | 1150 | mutex_init(&ctrl->crit_sect); |
dd5619cb | 1151 | mutex_init(&ctrl->ctrl_lock); |
f4778364 | 1152 | spin_lock_init(&ctrl->lock); |
dd5619cb | 1153 | |
1da177e4 LT |
1154 | /* setup wait queue */ |
1155 | init_waitqueue_head(&ctrl->queue); | |
1156 | ||
1da177e4 | 1157 | /* return PCI Controller Info */ |
48fe3915 KK |
1158 | ctrl->slot_device_offset = 0; |
1159 | ctrl->num_slots = 1; | |
1160 | ctrl->first_slot = slot_cap >> 19; | |
1161 | ctrl->ctrlcap = slot_cap & 0x0000007f; | |
1da177e4 LT |
1162 | |
1163 | /* Mask Hot-plug Interrupt Enable */ | |
a0f018da | 1164 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1da177e4 | 1165 | if (rc) { |
a0f018da | 1166 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
1167 | goto abort_free_ctlr; |
1168 | } | |
1169 | ||
a0f018da KK |
1170 | dbg("%s: SLOTCTRL %x value read %x\n", |
1171 | __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word); | |
1da177e4 LT |
1172 | temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00; |
1173 | ||
a0f018da | 1174 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1da177e4 | 1175 | if (rc) { |
a0f018da | 1176 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); |
1da177e4 LT |
1177 | goto abort_free_ctlr; |
1178 | } | |
1da177e4 | 1179 | |
a0f018da | 1180 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 1181 | if (rc) { |
a0f018da | 1182 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
1183 | goto abort_free_ctlr; |
1184 | } | |
1da177e4 LT |
1185 | |
1186 | temp_word = 0x1F; /* Clear all events */ | |
a0f018da | 1187 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 1188 | if (rc) { |
a0f018da | 1189 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
1da177e4 LT |
1190 | goto abort_free_ctlr; |
1191 | } | |
1da177e4 | 1192 | |
48fe3915 KK |
1193 | if (pciehp_poll_mode) { |
1194 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
1195 | init_timer(&ctrl->poll_timer); | |
1196 | start_int_poll_timer(ctrl, 10); | |
1da177e4 LT |
1197 | } else { |
1198 | /* Installs the interrupt handler */ | |
48fe3915 KK |
1199 | rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED, |
1200 | MY_NAME, (void *)ctrl); | |
1201 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", | |
5d386e1a KK |
1202 | __FUNCTION__, ctrl->pci_dev->irq, |
1203 | atomic_read(&pciehp_num_controllers), rc); | |
1da177e4 | 1204 | if (rc) { |
48fe3915 KK |
1205 | err("Can't get irq %d for the hotplug controller\n", |
1206 | ctrl->pci_dev->irq); | |
1da177e4 LT |
1207 | goto abort_free_ctlr; |
1208 | } | |
1209 | } | |
1a9ed1bf RS |
1210 | dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, |
1211 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq); | |
1212 | ||
5d386e1a KK |
1213 | /* |
1214 | * If this is the first controller to be initialized, | |
1215 | * initialize the pciehp work queue | |
1216 | */ | |
1217 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
1218 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
1219 | if (!pciehp_wq) { | |
1220 | rc = -ENOMEM; | |
1221 | goto abort_free_irq; | |
1222 | } | |
1223 | } | |
1224 | ||
a0f018da | 1225 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
1da177e4 | 1226 | if (rc) { |
a0f018da | 1227 | err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); |
9c64f977 | 1228 | goto abort_free_irq; |
1da177e4 | 1229 | } |
1da177e4 LT |
1230 | |
1231 | intr_enable = intr_enable | PRSN_DETECT_ENABLE; | |
1232 | ||
1233 | if (ATTN_BUTTN(slot_cap)) | |
1234 | intr_enable = intr_enable | ATTN_BUTTN_ENABLE; | |
71ad556d | 1235 | |
1da177e4 LT |
1236 | if (POWER_CTRL(slot_cap)) |
1237 | intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE; | |
71ad556d | 1238 | |
1da177e4 LT |
1239 | if (MRL_SENS(slot_cap)) |
1240 | intr_enable = intr_enable | MRL_DETECT_ENABLE; | |
1241 | ||
71ad556d | 1242 | temp_word = (temp_word & ~intr_enable) | intr_enable; |
1da177e4 LT |
1243 | |
1244 | if (pciehp_poll_mode) { | |
1245 | temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0; | |
1246 | } else { | |
1247 | temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE; | |
1248 | } | |
1da177e4 LT |
1249 | |
1250 | /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */ | |
a0f018da | 1251 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
1da177e4 | 1252 | if (rc) { |
a0f018da | 1253 | err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__); |
9c64f977 | 1254 | goto abort_free_irq; |
1da177e4 | 1255 | } |
a0f018da | 1256 | rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 1257 | if (rc) { |
a0f018da | 1258 | err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); |
9c64f977 | 1259 | goto abort_disable_intr; |
1da177e4 | 1260 | } |
71ad556d | 1261 | |
1da177e4 | 1262 | temp_word = 0x1F; /* Clear all events */ |
a0f018da | 1263 | rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word); |
1da177e4 | 1264 | if (rc) { |
a0f018da | 1265 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); |
9c64f977 | 1266 | goto abort_disable_intr; |
1da177e4 | 1267 | } |
71ad556d | 1268 | |
a3a45ec8 RS |
1269 | if (pciehp_force) { |
1270 | dbg("Bypassing BIOS check for pciehp use on %s\n", | |
1271 | pci_name(ctrl->pci_dev)); | |
1272 | } else { | |
6560aa5c | 1273 | rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev); |
a3a45ec8 | 1274 | if (rc) |
9c64f977 | 1275 | goto abort_disable_intr; |
a3a45ec8 | 1276 | } |
a8a2be94 | 1277 | |
1da177e4 LT |
1278 | ctrl->hpc_ops = &pciehp_hpc_ops; |
1279 | ||
1da177e4 LT |
1280 | return 0; |
1281 | ||
1282 | /* We end up here for the many possible ways to fail this API. */ | |
9c64f977 | 1283 | abort_disable_intr: |
a0f018da | 1284 | rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); |
9c64f977 JB |
1285 | if (!rc) { |
1286 | temp_word &= ~(intr_enable | HP_INTR_ENABLE); | |
a0f018da | 1287 | rc = pciehp_writew(ctrl, SLOTCTRL, temp_word); |
9c64f977 JB |
1288 | } |
1289 | if (rc) | |
1290 | err("%s : disabling interrupts failed\n", __FUNCTION__); | |
1291 | ||
1292 | abort_free_irq: | |
1293 | if (pciehp_poll_mode) | |
48fe3915 | 1294 | del_timer_sync(&ctrl->poll_timer); |
9c64f977 | 1295 | else |
48fe3915 | 1296 | free_irq(ctrl->pci_dev->irq, ctrl); |
9c64f977 | 1297 | |
1da177e4 | 1298 | abort_free_ctlr: |
1da177e4 LT |
1299 | return -1; |
1300 | } |