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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
a0f018da KK |
45 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
46 | { | |
47 | struct pci_dev *dev = ctrl->pci_dev; | |
48 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); | |
49 | } | |
50 | ||
51 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
52 | { | |
53 | struct pci_dev *dev = ctrl->pci_dev; | |
54 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); | |
55 | } | |
56 | ||
57 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
58 | { | |
59 | struct pci_dev *dev = ctrl->pci_dev; | |
60 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); | |
61 | } | |
62 | ||
63 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
64 | { | |
65 | struct pci_dev *dev = ctrl->pci_dev; | |
66 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); | |
67 | } | |
1da177e4 | 68 | |
1da177e4 LT |
69 | /* Power Control Command */ |
70 | #define POWER_ON 0 | |
322162a7 | 71 | #define POWER_OFF PCI_EXP_SLTCTL_PCC |
1da177e4 | 72 | |
48fe3915 KK |
73 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
74 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
75 | |
76 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 77 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 78 | { |
48fe3915 | 79 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 80 | |
1da177e4 | 81 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 82 | pcie_isr(0, ctrl); |
1da177e4 | 83 | |
48fe3915 | 84 | init_timer(&ctrl->poll_timer); |
1da177e4 | 85 | if (!pciehp_poll_time) |
40730d10 | 86 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 87 | |
48fe3915 | 88 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
89 | } |
90 | ||
91 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 92 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 93 | { |
48fe3915 KK |
94 | /* Clamp to sane value */ |
95 | if ((sec <= 0) || (sec > 60)) | |
96 | sec = 2; | |
97 | ||
98 | ctrl->poll_timer.function = &int_poll_timeout; | |
99 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
100 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
101 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
102 | } |
103 | ||
2aeeef11 KK |
104 | static inline int pciehp_request_irq(struct controller *ctrl) |
105 | { | |
f7a10e32 | 106 | int retval, irq = ctrl->pcie->irq; |
2aeeef11 KK |
107 | |
108 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
109 | if (pciehp_poll_mode) { | |
110 | init_timer(&ctrl->poll_timer); | |
111 | start_int_poll_timer(ctrl, 10); | |
112 | return 0; | |
113 | } | |
114 | ||
115 | /* Installs the interrupt handler */ | |
116 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
117 | if (retval) | |
7f2feec1 TI |
118 | ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", |
119 | irq); | |
2aeeef11 KK |
120 | return retval; |
121 | } | |
122 | ||
123 | static inline void pciehp_free_irq(struct controller *ctrl) | |
124 | { | |
125 | if (pciehp_poll_mode) | |
126 | del_timer_sync(&ctrl->poll_timer); | |
127 | else | |
f7a10e32 | 128 | free_irq(ctrl->pcie->irq, ctrl); |
2aeeef11 KK |
129 | } |
130 | ||
563f1190 | 131 | static int pcie_poll_cmd(struct controller *ctrl) |
6592e02a KK |
132 | { |
133 | u16 slot_status; | |
322162a7 | 134 | int err, timeout = 1000; |
6592e02a | 135 | |
322162a7 KK |
136 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
137 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
138 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
139 | return 1; | |
820943b6 | 140 | } |
a5827f40 | 141 | while (timeout > 0) { |
66618bad KK |
142 | msleep(10); |
143 | timeout -= 10; | |
322162a7 KK |
144 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
145 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | |
146 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | |
147 | return 1; | |
820943b6 | 148 | } |
6592e02a KK |
149 | } |
150 | return 0; /* timeout */ | |
6592e02a KK |
151 | } |
152 | ||
563f1190 | 153 | static void pcie_wait_cmd(struct controller *ctrl, int poll) |
44ef4cef | 154 | { |
262303fe KK |
155 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; |
156 | unsigned long timeout = msecs_to_jiffies(msecs); | |
157 | int rc; | |
158 | ||
6592e02a KK |
159 | if (poll) |
160 | rc = pcie_poll_cmd(ctrl); | |
161 | else | |
d737bdc1 | 162 | rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); |
262303fe | 163 | if (!rc) |
7f2feec1 | 164 | ctrl_dbg(ctrl, "Command not completed in 1000 msec\n"); |
44ef4cef KK |
165 | } |
166 | ||
f4778364 KK |
167 | /** |
168 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 169 | * @ctrl: controller to which the command is issued |
f4778364 KK |
170 | * @cmd: command value written to slot control register |
171 | * @mask: bitmask of slot control register to be modified | |
172 | */ | |
c27fb883 | 173 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 174 | { |
1da177e4 LT |
175 | int retval = 0; |
176 | u16 slot_status; | |
f4778364 | 177 | u16 slot_ctrl; |
1da177e4 | 178 | |
44ef4cef KK |
179 | mutex_lock(&ctrl->ctrl_lock); |
180 | ||
322162a7 | 181 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 182 | if (retval) { |
7f2feec1 TI |
183 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
184 | __func__); | |
44ef4cef | 185 | goto out; |
a0f018da KK |
186 | } |
187 | ||
322162a7 | 188 | if (slot_status & PCI_EXP_SLTSTA_CC) { |
5808639b KK |
189 | if (!ctrl->no_cmd_complete) { |
190 | /* | |
191 | * After 1 sec and CMD_COMPLETED still not set, just | |
192 | * proceed forward to issue the next command according | |
193 | * to spec. Just print out the error message. | |
194 | */ | |
18b341b7 | 195 | ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n"); |
5808639b KK |
196 | } else if (!NO_CMD_CMPL(ctrl)) { |
197 | /* | |
198 | * This controller semms to notify of command completed | |
199 | * event even though it supports none of power | |
200 | * controller, attention led, power led and EMI. | |
201 | */ | |
18b341b7 TI |
202 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to " |
203 | "wait for command completed event.\n"); | |
5808639b KK |
204 | ctrl->no_cmd_complete = 0; |
205 | } else { | |
18b341b7 TI |
206 | ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe " |
207 | "the controller is broken.\n"); | |
5808639b | 208 | } |
1da177e4 LT |
209 | } |
210 | ||
322162a7 | 211 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 212 | if (retval) { |
7f2feec1 | 213 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 214 | goto out; |
1da177e4 | 215 | } |
1da177e4 | 216 | |
f4778364 | 217 | slot_ctrl &= ~mask; |
b7aa1f16 | 218 | slot_ctrl |= (cmd & mask); |
f4778364 | 219 | ctrl->cmd_busy = 1; |
2d32a9ae | 220 | smp_mb(); |
322162a7 | 221 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); |
f4778364 | 222 | if (retval) |
18b341b7 | 223 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
f4778364 | 224 | |
44ef4cef KK |
225 | /* |
226 | * Wait for command completion. | |
227 | */ | |
6592e02a KK |
228 | if (!retval && !ctrl->no_cmd_complete) { |
229 | int poll = 0; | |
230 | /* | |
231 | * if hotplug interrupt is not enabled or command | |
232 | * completed interrupt is not enabled, we need to poll | |
233 | * command completed event. | |
234 | */ | |
322162a7 KK |
235 | if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) || |
236 | !(slot_ctrl & PCI_EXP_SLTCTL_CCIE)) | |
6592e02a | 237 | poll = 1; |
d737bdc1 | 238 | pcie_wait_cmd(ctrl, poll); |
6592e02a | 239 | } |
44ef4cef KK |
240 | out: |
241 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
242 | return retval; |
243 | } | |
244 | ||
f18e9625 KK |
245 | static inline int check_link_active(struct controller *ctrl) |
246 | { | |
247 | u16 link_status; | |
248 | ||
322162a7 | 249 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status)) |
f18e9625 | 250 | return 0; |
322162a7 | 251 | return !!(link_status & PCI_EXP_LNKSTA_DLLLA); |
f18e9625 KK |
252 | } |
253 | ||
254 | static void pcie_wait_link_active(struct controller *ctrl) | |
255 | { | |
256 | int timeout = 1000; | |
257 | ||
258 | if (check_link_active(ctrl)) | |
259 | return; | |
260 | while (timeout > 0) { | |
261 | msleep(10); | |
262 | timeout -= 10; | |
263 | if (check_link_active(ctrl)) | |
264 | return; | |
265 | } | |
266 | ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n"); | |
267 | } | |
268 | ||
1da177e4 LT |
269 | static int hpc_check_lnk_status(struct controller *ctrl) |
270 | { | |
1da177e4 LT |
271 | u16 lnk_status; |
272 | int retval = 0; | |
273 | ||
f18e9625 KK |
274 | /* |
275 | * Data Link Layer Link Active Reporting must be capable for | |
276 | * hot-plug capable downstream port. But old controller might | |
277 | * not implement it. In this case, we wait for 1000 ms. | |
278 | */ | |
279 | if (ctrl->link_active_reporting){ | |
280 | /* Wait for Data Link Layer Link Active bit to be set */ | |
281 | pcie_wait_link_active(ctrl); | |
282 | /* | |
283 | * We must wait for 100 ms after the Data Link Layer | |
284 | * Link Active bit reads 1b before initiating a | |
285 | * configuration access to the hot added device. | |
286 | */ | |
287 | msleep(100); | |
288 | } else | |
289 | msleep(1000); | |
290 | ||
322162a7 | 291 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 292 | if (retval) { |
18b341b7 | 293 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
1da177e4 LT |
294 | return retval; |
295 | } | |
296 | ||
7f2feec1 | 297 | ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); |
322162a7 KK |
298 | if ((lnk_status & PCI_EXP_LNKSTA_LT) || |
299 | !(lnk_status & PCI_EXP_LNKSTA_NLW)) { | |
18b341b7 | 300 | ctrl_err(ctrl, "Link Training Error occurs \n"); |
1da177e4 LT |
301 | retval = -1; |
302 | return retval; | |
303 | } | |
304 | ||
1da177e4 LT |
305 | return retval; |
306 | } | |
307 | ||
1da177e4 LT |
308 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
309 | { | |
48fe3915 | 310 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
311 | u16 slot_ctrl; |
312 | u8 atten_led_state; | |
313 | int retval = 0; | |
1da177e4 | 314 | |
322162a7 | 315 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 316 | if (retval) { |
7f2feec1 | 317 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
318 | return retval; |
319 | } | |
320 | ||
7f2feec1 | 321 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", |
322162a7 | 322 | __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl); |
1da177e4 | 323 | |
322162a7 | 324 | atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6; |
1da177e4 LT |
325 | |
326 | switch (atten_led_state) { | |
327 | case 0: | |
328 | *status = 0xFF; /* Reserved */ | |
329 | break; | |
330 | case 1: | |
331 | *status = 1; /* On */ | |
332 | break; | |
333 | case 2: | |
334 | *status = 2; /* Blink */ | |
335 | break; | |
336 | case 3: | |
337 | *status = 0; /* Off */ | |
338 | break; | |
339 | default: | |
340 | *status = 0xFF; | |
341 | break; | |
342 | } | |
343 | ||
1da177e4 LT |
344 | return 0; |
345 | } | |
346 | ||
48fe3915 | 347 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 348 | { |
48fe3915 | 349 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
350 | u16 slot_ctrl; |
351 | u8 pwr_state; | |
352 | int retval = 0; | |
1da177e4 | 353 | |
322162a7 | 354 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); |
1da177e4 | 355 | if (retval) { |
7f2feec1 | 356 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
357 | return retval; |
358 | } | |
7f2feec1 | 359 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", |
322162a7 | 360 | __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl); |
1da177e4 | 361 | |
322162a7 | 362 | pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10; |
1da177e4 LT |
363 | |
364 | switch (pwr_state) { | |
365 | case 0: | |
366 | *status = 1; | |
367 | break; | |
368 | case 1: | |
71ad556d | 369 | *status = 0; |
1da177e4 LT |
370 | break; |
371 | default: | |
372 | *status = 0xFF; | |
373 | break; | |
374 | } | |
375 | ||
1da177e4 LT |
376 | return retval; |
377 | } | |
378 | ||
1da177e4 LT |
379 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
380 | { | |
48fe3915 | 381 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 382 | u16 slot_status; |
322162a7 | 383 | int retval; |
1da177e4 | 384 | |
322162a7 | 385 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 386 | if (retval) { |
7f2feec1 TI |
387 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
388 | __func__); | |
1da177e4 LT |
389 | return retval; |
390 | } | |
322162a7 | 391 | *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS); |
1da177e4 LT |
392 | return 0; |
393 | } | |
394 | ||
395 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
396 | { | |
48fe3915 | 397 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 398 | u16 slot_status; |
322162a7 | 399 | int retval; |
1da177e4 | 400 | |
322162a7 | 401 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 402 | if (retval) { |
7f2feec1 TI |
403 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
404 | __func__); | |
1da177e4 LT |
405 | return retval; |
406 | } | |
322162a7 | 407 | *status = !!(slot_status & PCI_EXP_SLTSTA_PDS); |
1da177e4 LT |
408 | return 0; |
409 | } | |
410 | ||
48fe3915 | 411 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 412 | { |
48fe3915 | 413 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 414 | u16 slot_status; |
322162a7 | 415 | int retval; |
1da177e4 | 416 | |
322162a7 | 417 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
1da177e4 | 418 | if (retval) { |
18b341b7 | 419 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
1da177e4 LT |
420 | return retval; |
421 | } | |
322162a7 | 422 | return !!(slot_status & PCI_EXP_SLTSTA_PFD); |
1da177e4 LT |
423 | } |
424 | ||
425 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
426 | { | |
48fe3915 | 427 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
428 | u16 slot_cmd; |
429 | u16 cmd_mask; | |
430 | int rc; | |
1da177e4 | 431 | |
322162a7 | 432 | cmd_mask = PCI_EXP_SLTCTL_AIC; |
1da177e4 LT |
433 | switch (value) { |
434 | case 0 : /* turn off */ | |
f4778364 | 435 | slot_cmd = 0x00C0; |
1da177e4 LT |
436 | break; |
437 | case 1: /* turn on */ | |
f4778364 | 438 | slot_cmd = 0x0040; |
1da177e4 LT |
439 | break; |
440 | case 2: /* turn blink */ | |
f4778364 | 441 | slot_cmd = 0x0080; |
1da177e4 LT |
442 | break; |
443 | default: | |
444 | return -1; | |
445 | } | |
c27fb883 | 446 | rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
7f2feec1 | 447 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
322162a7 | 448 | __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); |
71ad556d | 449 | |
1da177e4 LT |
450 | return rc; |
451 | } | |
452 | ||
1da177e4 LT |
453 | static void hpc_set_green_led_on(struct slot *slot) |
454 | { | |
48fe3915 | 455 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 456 | u16 slot_cmd; |
f4778364 | 457 | u16 cmd_mask; |
71ad556d | 458 | |
f4778364 | 459 | slot_cmd = 0x0100; |
322162a7 | 460 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 461 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
7f2feec1 | 462 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
322162a7 | 463 | __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); |
1da177e4 LT |
464 | } |
465 | ||
466 | static void hpc_set_green_led_off(struct slot *slot) | |
467 | { | |
48fe3915 | 468 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 469 | u16 slot_cmd; |
f4778364 | 470 | u16 cmd_mask; |
1da177e4 | 471 | |
f4778364 | 472 | slot_cmd = 0x0300; |
322162a7 | 473 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 474 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
7f2feec1 | 475 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
322162a7 | 476 | __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); |
1da177e4 LT |
477 | } |
478 | ||
479 | static void hpc_set_green_led_blink(struct slot *slot) | |
480 | { | |
48fe3915 | 481 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 482 | u16 slot_cmd; |
f4778364 | 483 | u16 cmd_mask; |
71ad556d | 484 | |
f4778364 | 485 | slot_cmd = 0x0200; |
322162a7 | 486 | cmd_mask = PCI_EXP_SLTCTL_PIC; |
c27fb883 | 487 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
7f2feec1 | 488 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
322162a7 | 489 | __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); |
1da177e4 LT |
490 | } |
491 | ||
1da177e4 LT |
492 | static int hpc_power_on_slot(struct slot * slot) |
493 | { | |
48fe3915 | 494 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 495 | u16 slot_cmd; |
f4778364 KK |
496 | u16 cmd_mask; |
497 | u16 slot_status; | |
1da177e4 LT |
498 | int retval = 0; |
499 | ||
7f2feec1 | 500 | ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 501 | |
5a49f203 | 502 | /* Clear sticky power-fault bit from previous power failures */ |
322162a7 | 503 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); |
a0f018da | 504 | if (retval) { |
7f2feec1 TI |
505 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
506 | __func__); | |
a0f018da KK |
507 | return retval; |
508 | } | |
322162a7 | 509 | slot_status &= PCI_EXP_SLTSTA_PFD; |
a0f018da | 510 | if (slot_status) { |
322162a7 | 511 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); |
a0f018da | 512 | if (retval) { |
7f2feec1 TI |
513 | ctrl_err(ctrl, |
514 | "%s: Cannot write to SLOTSTATUS register\n", | |
515 | __func__); | |
a0f018da KK |
516 | return retval; |
517 | } | |
518 | } | |
1da177e4 | 519 | |
f4778364 | 520 | slot_cmd = POWER_ON; |
322162a7 | 521 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
f4778364 | 522 | if (!pciehp_poll_mode) { |
99f0169c KK |
523 | /* Enable power fault detection turned off at power off time */ |
524 | slot_cmd |= PCI_EXP_SLTCTL_PFDE; | |
525 | cmd_mask |= PCI_EXP_SLTCTL_PFDE; | |
f4778364 | 526 | } |
1da177e4 | 527 | |
c27fb883 | 528 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 529 | if (retval) { |
18b341b7 | 530 | ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd); |
99f0169c | 531 | return retval; |
1da177e4 | 532 | } |
7f2feec1 | 533 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
322162a7 | 534 | __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); |
1da177e4 | 535 | |
99f0169c | 536 | ctrl->power_fault_detected = 0; |
1da177e4 LT |
537 | return retval; |
538 | } | |
539 | ||
f1050a35 KK |
540 | static inline int pcie_mask_bad_dllp(struct controller *ctrl) |
541 | { | |
542 | struct pci_dev *dev = ctrl->pci_dev; | |
543 | int pos; | |
544 | u32 reg; | |
545 | ||
546 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
547 | if (!pos) | |
548 | return 0; | |
549 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
550 | if (reg & PCI_ERR_COR_BAD_DLLP) | |
551 | return 0; | |
552 | reg |= PCI_ERR_COR_BAD_DLLP; | |
553 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
554 | return 1; | |
555 | } | |
556 | ||
557 | static inline void pcie_unmask_bad_dllp(struct controller *ctrl) | |
558 | { | |
559 | struct pci_dev *dev = ctrl->pci_dev; | |
560 | u32 reg; | |
561 | int pos; | |
562 | ||
563 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
564 | if (!pos) | |
565 | return; | |
566 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
567 | if (!(reg & PCI_ERR_COR_BAD_DLLP)) | |
568 | return; | |
569 | reg &= ~PCI_ERR_COR_BAD_DLLP; | |
570 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
571 | } | |
572 | ||
1da177e4 LT |
573 | static int hpc_power_off_slot(struct slot * slot) |
574 | { | |
48fe3915 | 575 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 576 | u16 slot_cmd; |
f4778364 | 577 | u16 cmd_mask; |
1da177e4 | 578 | int retval = 0; |
f1050a35 | 579 | int changed; |
1da177e4 | 580 | |
7f2feec1 | 581 | ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 582 | |
f1050a35 KK |
583 | /* |
584 | * Set Bad DLLP Mask bit in Correctable Error Mask | |
585 | * Register. This is the workaround against Bad DLLP error | |
586 | * that sometimes happens during turning power off the slot | |
587 | * which conforms to PCI Express 1.0a spec. | |
588 | */ | |
589 | changed = pcie_mask_bad_dllp(ctrl); | |
590 | ||
f4778364 | 591 | slot_cmd = POWER_OFF; |
322162a7 | 592 | cmd_mask = PCI_EXP_SLTCTL_PCC; |
f4778364 | 593 | if (!pciehp_poll_mode) { |
99f0169c KK |
594 | /* Disable power fault detection */ |
595 | slot_cmd &= ~PCI_EXP_SLTCTL_PFDE; | |
596 | cmd_mask |= PCI_EXP_SLTCTL_PFDE; | |
f4778364 | 597 | } |
1da177e4 | 598 | |
c27fb883 | 599 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 600 | if (retval) { |
18b341b7 | 601 | ctrl_err(ctrl, "Write command failed!\n"); |
c1ef5cbd KK |
602 | retval = -1; |
603 | goto out; | |
1da177e4 | 604 | } |
7f2feec1 | 605 | ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", |
322162a7 | 606 | __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd); |
c1ef5cbd | 607 | out: |
f1050a35 KK |
608 | if (changed) |
609 | pcie_unmask_bad_dllp(ctrl); | |
610 | ||
1da177e4 LT |
611 | return retval; |
612 | } | |
613 | ||
48fe3915 | 614 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 615 | { |
48fe3915 | 616 | struct controller *ctrl = (struct controller *)dev_id; |
c6b069e9 | 617 | u16 detected, intr_loc; |
dbd79aed | 618 | struct slot *p_slot; |
1da177e4 | 619 | |
c6b069e9 KK |
620 | /* |
621 | * In order to guarantee that all interrupt events are | |
622 | * serviced, we need to re-inspect Slot Status register after | |
623 | * clearing what is presumed to be the last pending interrupt. | |
624 | */ | |
625 | intr_loc = 0; | |
626 | do { | |
322162a7 | 627 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { |
7f2feec1 TI |
628 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
629 | __func__); | |
1da177e4 LT |
630 | return IRQ_NONE; |
631 | } | |
632 | ||
322162a7 KK |
633 | detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD | |
634 | PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC | | |
635 | PCI_EXP_SLTSTA_CC); | |
81b840cd | 636 | detected &= ~intr_loc; |
c6b069e9 KK |
637 | intr_loc |= detected; |
638 | if (!intr_loc) | |
1da177e4 | 639 | return IRQ_NONE; |
81b840cd | 640 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { |
7f2feec1 TI |
641 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
642 | __func__); | |
1da177e4 LT |
643 | return IRQ_NONE; |
644 | } | |
c6b069e9 | 645 | } while (detected); |
71ad556d | 646 | |
7f2feec1 | 647 | ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); |
71ad556d | 648 | |
c6b069e9 | 649 | /* Check Command Complete Interrupt Pending */ |
322162a7 | 650 | if (intr_loc & PCI_EXP_SLTSTA_CC) { |
262303fe | 651 | ctrl->cmd_busy = 0; |
2d32a9ae | 652 | smp_mb(); |
d737bdc1 | 653 | wake_up(&ctrl->queue); |
1da177e4 LT |
654 | } |
655 | ||
322162a7 | 656 | if (!(intr_loc & ~PCI_EXP_SLTSTA_CC)) |
dbd79aed KK |
657 | return IRQ_HANDLED; |
658 | ||
dbd79aed | 659 | p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); |
dbd79aed | 660 | |
c6b069e9 | 661 | /* Check MRL Sensor Changed */ |
322162a7 | 662 | if (intr_loc & PCI_EXP_SLTSTA_MRLSC) |
dbd79aed | 663 | pciehp_handle_switch_change(p_slot); |
48fe3915 | 664 | |
c6b069e9 | 665 | /* Check Attention Button Pressed */ |
322162a7 | 666 | if (intr_loc & PCI_EXP_SLTSTA_ABP) |
dbd79aed | 667 | pciehp_handle_attention_button(p_slot); |
48fe3915 | 668 | |
c6b069e9 | 669 | /* Check Presence Detect Changed */ |
322162a7 | 670 | if (intr_loc & PCI_EXP_SLTSTA_PDC) |
dbd79aed | 671 | pciehp_handle_presence_change(p_slot); |
48fe3915 | 672 | |
c6b069e9 | 673 | /* Check Power Fault Detected */ |
99f0169c KK |
674 | if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { |
675 | ctrl->power_fault_detected = 1; | |
dbd79aed | 676 | pciehp_handle_power_fault(p_slot); |
99f0169c | 677 | } |
1da177e4 LT |
678 | return IRQ_HANDLED; |
679 | } | |
680 | ||
40730d10 | 681 | static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 682 | { |
48fe3915 | 683 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
684 | enum pcie_link_speed lnk_speed; |
685 | u32 lnk_cap; | |
686 | int retval = 0; | |
687 | ||
322162a7 | 688 | retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); |
1da177e4 | 689 | if (retval) { |
7f2feec1 | 690 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
691 | return retval; |
692 | } | |
693 | ||
694 | switch (lnk_cap & 0x000F) { | |
695 | case 1: | |
825c423a KK |
696 | lnk_speed = PCIE_2_5GB; |
697 | break; | |
698 | case 2: | |
699 | lnk_speed = PCIE_5_0GB; | |
1da177e4 LT |
700 | break; |
701 | default: | |
702 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
703 | break; | |
704 | } | |
705 | ||
706 | *value = lnk_speed; | |
7f2feec1 | 707 | ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed); |
c8426483 | 708 | |
1da177e4 LT |
709 | return retval; |
710 | } | |
711 | ||
40730d10 KK |
712 | static int hpc_get_max_lnk_width(struct slot *slot, |
713 | enum pcie_link_width *value) | |
1da177e4 | 714 | { |
48fe3915 | 715 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
716 | enum pcie_link_width lnk_wdth; |
717 | u32 lnk_cap; | |
718 | int retval = 0; | |
719 | ||
322162a7 | 720 | retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap); |
1da177e4 | 721 | if (retval) { |
7f2feec1 | 722 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
723 | return retval; |
724 | } | |
725 | ||
322162a7 | 726 | switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
727 | case 0: |
728 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
729 | break; | |
730 | case 1: | |
731 | lnk_wdth = PCIE_LNK_X1; | |
732 | break; | |
733 | case 2: | |
734 | lnk_wdth = PCIE_LNK_X2; | |
735 | break; | |
736 | case 4: | |
737 | lnk_wdth = PCIE_LNK_X4; | |
738 | break; | |
739 | case 8: | |
740 | lnk_wdth = PCIE_LNK_X8; | |
741 | break; | |
742 | case 12: | |
743 | lnk_wdth = PCIE_LNK_X12; | |
744 | break; | |
745 | case 16: | |
746 | lnk_wdth = PCIE_LNK_X16; | |
747 | break; | |
748 | case 32: | |
749 | lnk_wdth = PCIE_LNK_X32; | |
750 | break; | |
751 | default: | |
752 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
753 | break; | |
754 | } | |
755 | ||
756 | *value = lnk_wdth; | |
7f2feec1 | 757 | ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth); |
c8426483 | 758 | |
1da177e4 LT |
759 | return retval; |
760 | } | |
761 | ||
40730d10 | 762 | static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 763 | { |
48fe3915 | 764 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
765 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
766 | int retval = 0; | |
767 | u16 lnk_status; | |
768 | ||
322162a7 | 769 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 770 | if (retval) { |
7f2feec1 TI |
771 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
772 | __func__); | |
1da177e4 LT |
773 | return retval; |
774 | } | |
775 | ||
322162a7 | 776 | switch (lnk_status & PCI_EXP_LNKSTA_CLS) { |
1da177e4 | 777 | case 1: |
825c423a KK |
778 | lnk_speed = PCIE_2_5GB; |
779 | break; | |
780 | case 2: | |
781 | lnk_speed = PCIE_5_0GB; | |
1da177e4 LT |
782 | break; |
783 | default: | |
784 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
785 | break; | |
786 | } | |
787 | ||
788 | *value = lnk_speed; | |
7f2feec1 | 789 | ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed); |
c8426483 | 790 | |
1da177e4 LT |
791 | return retval; |
792 | } | |
793 | ||
40730d10 KK |
794 | static int hpc_get_cur_lnk_width(struct slot *slot, |
795 | enum pcie_link_width *value) | |
1da177e4 | 796 | { |
48fe3915 | 797 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
798 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
799 | int retval = 0; | |
800 | u16 lnk_status; | |
801 | ||
322162a7 | 802 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |
1da177e4 | 803 | if (retval) { |
7f2feec1 TI |
804 | ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n", |
805 | __func__); | |
1da177e4 LT |
806 | return retval; |
807 | } | |
71ad556d | 808 | |
322162a7 | 809 | switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){ |
1da177e4 LT |
810 | case 0: |
811 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
812 | break; | |
813 | case 1: | |
814 | lnk_wdth = PCIE_LNK_X1; | |
815 | break; | |
816 | case 2: | |
817 | lnk_wdth = PCIE_LNK_X2; | |
818 | break; | |
819 | case 4: | |
820 | lnk_wdth = PCIE_LNK_X4; | |
821 | break; | |
822 | case 8: | |
823 | lnk_wdth = PCIE_LNK_X8; | |
824 | break; | |
825 | case 12: | |
826 | lnk_wdth = PCIE_LNK_X12; | |
827 | break; | |
828 | case 16: | |
829 | lnk_wdth = PCIE_LNK_X16; | |
830 | break; | |
831 | case 32: | |
832 | lnk_wdth = PCIE_LNK_X32; | |
833 | break; | |
834 | default: | |
835 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
836 | break; | |
837 | } | |
838 | ||
839 | *value = lnk_wdth; | |
7f2feec1 | 840 | ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth); |
c8426483 | 841 | |
1da177e4 LT |
842 | return retval; |
843 | } | |
844 | ||
c4635eb0 | 845 | static void pcie_release_ctrl(struct controller *ctrl); |
1da177e4 LT |
846 | static struct hpc_ops pciehp_hpc_ops = { |
847 | .power_on_slot = hpc_power_on_slot, | |
848 | .power_off_slot = hpc_power_off_slot, | |
849 | .set_attention_status = hpc_set_attention_status, | |
850 | .get_power_status = hpc_get_power_status, | |
851 | .get_attention_status = hpc_get_attention_status, | |
852 | .get_latch_status = hpc_get_latch_status, | |
853 | .get_adapter_status = hpc_get_adapter_status, | |
854 | ||
855 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
856 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
857 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
858 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
71ad556d | 859 | |
1da177e4 LT |
860 | .query_power_fault = hpc_query_power_fault, |
861 | .green_led_on = hpc_set_green_led_on, | |
862 | .green_led_off = hpc_set_green_led_off, | |
863 | .green_led_blink = hpc_set_green_led_blink, | |
71ad556d | 864 | |
c4635eb0 | 865 | .release_ctlr = pcie_release_ctrl, |
1da177e4 LT |
866 | .check_lnk_status = hpc_check_lnk_status, |
867 | }; | |
868 | ||
c4635eb0 | 869 | int pcie_enable_notification(struct controller *ctrl) |
ecdde939 | 870 | { |
c27fb883 | 871 | u16 cmd, mask; |
1da177e4 | 872 | |
322162a7 | 873 | cmd = PCI_EXP_SLTCTL_PDCE; |
ae416e6b | 874 | if (ATTN_BUTTN(ctrl)) |
322162a7 | 875 | cmd |= PCI_EXP_SLTCTL_ABPE; |
ae416e6b | 876 | if (POWER_CTRL(ctrl)) |
322162a7 | 877 | cmd |= PCI_EXP_SLTCTL_PFDE; |
ae416e6b | 878 | if (MRL_SENS(ctrl)) |
322162a7 | 879 | cmd |= PCI_EXP_SLTCTL_MRLSCE; |
c27fb883 | 880 | if (!pciehp_poll_mode) |
322162a7 | 881 | cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE; |
c27fb883 | 882 | |
322162a7 KK |
883 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
884 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
885 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c27fb883 KK |
886 | |
887 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
18b341b7 | 888 | ctrl_err(ctrl, "Cannot enable software notification\n"); |
125c39f7 | 889 | return -1; |
1da177e4 | 890 | } |
c4635eb0 KK |
891 | return 0; |
892 | } | |
893 | ||
894 | static void pcie_disable_notification(struct controller *ctrl) | |
895 | { | |
896 | u16 mask; | |
322162a7 KK |
897 | mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE | |
898 | PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE | | |
899 | PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE); | |
c4635eb0 | 900 | if (pcie_write_cmd(ctrl, 0, mask)) |
18b341b7 | 901 | ctrl_warn(ctrl, "Cannot disable software notification\n"); |
c4635eb0 KK |
902 | } |
903 | ||
dbc7e1e5 | 904 | int pcie_init_notification(struct controller *ctrl) |
c4635eb0 KK |
905 | { |
906 | if (pciehp_request_irq(ctrl)) | |
907 | return -1; | |
908 | if (pcie_enable_notification(ctrl)) { | |
909 | pciehp_free_irq(ctrl); | |
910 | return -1; | |
911 | } | |
dbc7e1e5 | 912 | ctrl->notification_enabled = 1; |
c4635eb0 KK |
913 | return 0; |
914 | } | |
915 | ||
916 | static void pcie_shutdown_notification(struct controller *ctrl) | |
917 | { | |
dbc7e1e5 EB |
918 | if (ctrl->notification_enabled) { |
919 | pcie_disable_notification(ctrl); | |
920 | pciehp_free_irq(ctrl); | |
921 | ctrl->notification_enabled = 0; | |
922 | } | |
c4635eb0 KK |
923 | } |
924 | ||
c4635eb0 KK |
925 | static int pcie_init_slot(struct controller *ctrl) |
926 | { | |
927 | struct slot *slot; | |
928 | ||
929 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
930 | if (!slot) | |
931 | return -ENOMEM; | |
932 | ||
933 | slot->hp_slot = 0; | |
934 | slot->ctrl = ctrl; | |
935 | slot->bus = ctrl->pci_dev->subordinate->number; | |
936 | slot->device = ctrl->slot_device_offset + slot->hp_slot; | |
937 | slot->hpc_ops = ctrl->hpc_ops; | |
938 | slot->number = ctrl->first_slot; | |
c4635eb0 KK |
939 | mutex_init(&slot->lock); |
940 | INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work); | |
941 | list_add(&slot->slot_list, &ctrl->slot_list); | |
1da177e4 | 942 | return 0; |
1da177e4 | 943 | } |
08e7a7d2 | 944 | |
c4635eb0 KK |
945 | static void pcie_cleanup_slot(struct controller *ctrl) |
946 | { | |
947 | struct slot *slot; | |
948 | slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list); | |
949 | list_del(&slot->slot_list); | |
950 | cancel_delayed_work(&slot->work); | |
951 | flush_scheduled_work(); | |
952 | flush_workqueue(pciehp_wq); | |
953 | kfree(slot); | |
954 | } | |
955 | ||
2aeeef11 | 956 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 957 | { |
2aeeef11 KK |
958 | int i; |
959 | u16 reg16; | |
960 | struct pci_dev *pdev = ctrl->pci_dev; | |
08e7a7d2 | 961 | |
2aeeef11 KK |
962 | if (!pciehp_debug) |
963 | return; | |
08e7a7d2 | 964 | |
7f2feec1 TI |
965 | ctrl_info(ctrl, "Hotplug Controller:\n"); |
966 | ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", | |
967 | pci_name(pdev), pdev->irq); | |
968 | ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); | |
969 | ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); | |
970 | ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", | |
971 | pdev->subsystem_device); | |
972 | ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", | |
973 | pdev->subsystem_vendor); | |
974 | ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | |
2aeeef11 KK |
975 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
976 | if (!pci_resource_len(pdev, i)) | |
977 | continue; | |
7f2feec1 TI |
978 | ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n", |
979 | i, (unsigned long long)pci_resource_len(pdev, i), | |
980 | (unsigned long long)pci_resource_start(pdev, i)); | |
08e7a7d2 | 981 | } |
7f2feec1 TI |
982 | ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
983 | ctrl_info(ctrl, " Physical Slot Number : %d\n", ctrl->first_slot); | |
984 | ctrl_info(ctrl, " Attention Button : %3s\n", | |
985 | ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
986 | ctrl_info(ctrl, " Power Controller : %3s\n", | |
987 | POWER_CTRL(ctrl) ? "yes" : "no"); | |
988 | ctrl_info(ctrl, " MRL Sensor : %3s\n", | |
989 | MRL_SENS(ctrl) ? "yes" : "no"); | |
990 | ctrl_info(ctrl, " Attention Indicator : %3s\n", | |
991 | ATTN_LED(ctrl) ? "yes" : "no"); | |
992 | ctrl_info(ctrl, " Power Indicator : %3s\n", | |
993 | PWR_LED(ctrl) ? "yes" : "no"); | |
994 | ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", | |
995 | HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
996 | ctrl_info(ctrl, " EMI Present : %3s\n", | |
997 | EMI(ctrl) ? "yes" : "no"); | |
998 | ctrl_info(ctrl, " Command Completed : %3s\n", | |
999 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | |
322162a7 | 1000 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); |
7f2feec1 | 1001 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
322162a7 | 1002 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); |
7f2feec1 | 1003 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
2aeeef11 | 1004 | } |
08e7a7d2 | 1005 | |
c4635eb0 | 1006 | struct controller *pcie_init(struct pcie_device *dev) |
2aeeef11 | 1007 | { |
c4635eb0 | 1008 | struct controller *ctrl; |
f18e9625 | 1009 | u32 slot_cap, link_cap; |
2aeeef11 | 1010 | struct pci_dev *pdev = dev->port; |
08e7a7d2 | 1011 | |
c4635eb0 KK |
1012 | ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
1013 | if (!ctrl) { | |
18b341b7 | 1014 | dev_err(&dev->device, "%s: Out of memory\n", __func__); |
c4635eb0 KK |
1015 | goto abort; |
1016 | } | |
1017 | INIT_LIST_HEAD(&ctrl->slot_list); | |
1018 | ||
f7a10e32 | 1019 | ctrl->pcie = dev; |
2aeeef11 KK |
1020 | ctrl->pci_dev = pdev; |
1021 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1022 | if (!ctrl->cap_base) { | |
18b341b7 | 1023 | ctrl_err(ctrl, "Cannot find PCI Express capability\n"); |
b84346ef | 1024 | goto abort_ctrl; |
08e7a7d2 | 1025 | } |
322162a7 | 1026 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { |
18b341b7 | 1027 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
b84346ef | 1028 | goto abort_ctrl; |
08e7a7d2 | 1029 | } |
08e7a7d2 | 1030 | |
2aeeef11 KK |
1031 | ctrl->slot_cap = slot_cap; |
1032 | ctrl->first_slot = slot_cap >> 19; | |
1033 | ctrl->slot_device_offset = 0; | |
1034 | ctrl->num_slots = 1; | |
1035 | ctrl->hpc_ops = &pciehp_hpc_ops; | |
08e7a7d2 ML |
1036 | mutex_init(&ctrl->crit_sect); |
1037 | mutex_init(&ctrl->ctrl_lock); | |
08e7a7d2 | 1038 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 1039 | dbg_ctrl(ctrl); |
5808639b KK |
1040 | /* |
1041 | * Controller doesn't notify of command completion if the "No | |
1042 | * Command Completed Support" bit is set in Slot Capability | |
1043 | * register or the controller supports none of power | |
1044 | * controller, attention led, power led and EMI. | |
1045 | */ | |
1046 | if (NO_CMD_CMPL(ctrl) || | |
1047 | !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl))) | |
1048 | ctrl->no_cmd_complete = 1; | |
08e7a7d2 | 1049 | |
f18e9625 | 1050 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
322162a7 | 1051 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { |
f18e9625 KK |
1052 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
1053 | goto abort_ctrl; | |
1054 | } | |
322162a7 | 1055 | if (link_cap & PCI_EXP_LNKCAP_DLLLARC) { |
f18e9625 KK |
1056 | ctrl_dbg(ctrl, "Link Active Reporting supported\n"); |
1057 | ctrl->link_active_reporting = 1; | |
1058 | } | |
1059 | ||
c4635eb0 | 1060 | /* Clear all remaining event bits in Slot Status register */ |
322162a7 | 1061 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) |
c4635eb0 | 1062 | goto abort_ctrl; |
08e7a7d2 | 1063 | |
c4635eb0 KK |
1064 | /* Disable sotfware notification */ |
1065 | pcie_disable_notification(ctrl); | |
ecdde939 ML |
1066 | |
1067 | /* | |
1068 | * If this is the first controller to be initialized, | |
1069 | * initialize the pciehp work queue | |
1070 | */ | |
1071 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
1072 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
c4635eb0 KK |
1073 | if (!pciehp_wq) |
1074 | goto abort_ctrl; | |
ecdde939 ML |
1075 | } |
1076 | ||
7f2feec1 TI |
1077 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1078 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
1079 | pdev->subsystem_device); | |
c4635eb0 KK |
1080 | |
1081 | if (pcie_init_slot(ctrl)) | |
1082 | goto abort_ctrl; | |
2aeeef11 | 1083 | |
c4635eb0 KK |
1084 | return ctrl; |
1085 | ||
c4635eb0 KK |
1086 | abort_ctrl: |
1087 | kfree(ctrl); | |
08e7a7d2 | 1088 | abort: |
c4635eb0 KK |
1089 | return NULL; |
1090 | } | |
1091 | ||
1092 | void pcie_release_ctrl(struct controller *ctrl) | |
1093 | { | |
1094 | pcie_shutdown_notification(ctrl); | |
1095 | pcie_cleanup_slot(ctrl); | |
1096 | /* | |
1097 | * If this is the last controller to be released, destroy the | |
1098 | * pciehp work queue | |
1099 | */ | |
1100 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
1101 | destroy_workqueue(pciehp_wq); | |
1102 | kfree(ctrl); | |
08e7a7d2 | 1103 | } |