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1da177e4 LT |
1 | /* |
2 | * PCI Express PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
de25968c TS |
33 | #include <linux/signal.h> |
34 | #include <linux/jiffies.h> | |
35 | #include <linux/timer.h> | |
1da177e4 | 36 | #include <linux/pci.h> |
5d1b8c9e | 37 | #include <linux/interrupt.h> |
34d03419 | 38 | #include <linux/time.h> |
5d1b8c9e | 39 | |
1da177e4 LT |
40 | #include "../pci.h" |
41 | #include "pciehp.h" | |
1da177e4 | 42 | |
5d386e1a KK |
43 | static atomic_t pciehp_num_controllers = ATOMIC_INIT(0); |
44 | ||
1da177e4 LT |
45 | struct ctrl_reg { |
46 | u8 cap_id; | |
47 | u8 nxt_ptr; | |
48 | u16 cap_reg; | |
49 | u32 dev_cap; | |
50 | u16 dev_ctrl; | |
51 | u16 dev_status; | |
52 | u32 lnk_cap; | |
53 | u16 lnk_ctrl; | |
54 | u16 lnk_status; | |
55 | u32 slot_cap; | |
56 | u16 slot_ctrl; | |
57 | u16 slot_status; | |
58 | u16 root_ctrl; | |
59 | u16 rsvp; | |
60 | u32 root_status; | |
61 | } __attribute__ ((packed)); | |
62 | ||
63 | /* offsets to the controller registers based on the above structure layout */ | |
64 | enum ctrl_offsets { | |
65 | PCIECAPID = offsetof(struct ctrl_reg, cap_id), | |
66 | NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr), | |
67 | CAPREG = offsetof(struct ctrl_reg, cap_reg), | |
68 | DEVCAP = offsetof(struct ctrl_reg, dev_cap), | |
69 | DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl), | |
70 | DEVSTATUS = offsetof(struct ctrl_reg, dev_status), | |
71 | LNKCAP = offsetof(struct ctrl_reg, lnk_cap), | |
72 | LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl), | |
73 | LNKSTATUS = offsetof(struct ctrl_reg, lnk_status), | |
74 | SLOTCAP = offsetof(struct ctrl_reg, slot_cap), | |
75 | SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl), | |
76 | SLOTSTATUS = offsetof(struct ctrl_reg, slot_status), | |
77 | ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl), | |
78 | ROOTSTATUS = offsetof(struct ctrl_reg, root_status), | |
79 | }; | |
1da177e4 | 80 | |
a0f018da KK |
81 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) |
82 | { | |
83 | struct pci_dev *dev = ctrl->pci_dev; | |
84 | return pci_read_config_word(dev, ctrl->cap_base + reg, value); | |
85 | } | |
86 | ||
87 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | |
88 | { | |
89 | struct pci_dev *dev = ctrl->pci_dev; | |
90 | return pci_read_config_dword(dev, ctrl->cap_base + reg, value); | |
91 | } | |
92 | ||
93 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | |
94 | { | |
95 | struct pci_dev *dev = ctrl->pci_dev; | |
96 | return pci_write_config_word(dev, ctrl->cap_base + reg, value); | |
97 | } | |
98 | ||
99 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | |
100 | { | |
101 | struct pci_dev *dev = ctrl->pci_dev; | |
102 | return pci_write_config_dword(dev, ctrl->cap_base + reg, value); | |
103 | } | |
1da177e4 LT |
104 | |
105 | /* Field definitions in PCI Express Capabilities Register */ | |
106 | #define CAP_VER 0x000F | |
107 | #define DEV_PORT_TYPE 0x00F0 | |
108 | #define SLOT_IMPL 0x0100 | |
109 | #define MSG_NUM 0x3E00 | |
110 | ||
111 | /* Device or Port Type */ | |
112 | #define NAT_ENDPT 0x00 | |
113 | #define LEG_ENDPT 0x01 | |
114 | #define ROOT_PORT 0x04 | |
115 | #define UP_STREAM 0x05 | |
116 | #define DN_STREAM 0x06 | |
117 | #define PCIE_PCI_BRDG 0x07 | |
118 | #define PCI_PCIE_BRDG 0x10 | |
119 | ||
120 | /* Field definitions in Device Capabilities Register */ | |
121 | #define DATTN_BUTTN_PRSN 0x1000 | |
122 | #define DATTN_LED_PRSN 0x2000 | |
123 | #define DPWR_LED_PRSN 0x4000 | |
124 | ||
125 | /* Field definitions in Link Capabilities Register */ | |
126 | #define MAX_LNK_SPEED 0x000F | |
127 | #define MAX_LNK_WIDTH 0x03F0 | |
128 | ||
129 | /* Link Width Encoding */ | |
130 | #define LNK_X1 0x01 | |
131 | #define LNK_X2 0x02 | |
71ad556d | 132 | #define LNK_X4 0x04 |
1da177e4 LT |
133 | #define LNK_X8 0x08 |
134 | #define LNK_X12 0x0C | |
71ad556d | 135 | #define LNK_X16 0x10 |
1da177e4 LT |
136 | #define LNK_X32 0x20 |
137 | ||
138 | /*Field definitions of Link Status Register */ | |
139 | #define LNK_SPEED 0x000F | |
140 | #define NEG_LINK_WD 0x03F0 | |
141 | #define LNK_TRN_ERR 0x0400 | |
142 | #define LNK_TRN 0x0800 | |
143 | #define SLOT_CLK_CONF 0x1000 | |
144 | ||
145 | /* Field definitions in Slot Capabilities Register */ | |
146 | #define ATTN_BUTTN_PRSN 0x00000001 | |
147 | #define PWR_CTRL_PRSN 0x00000002 | |
148 | #define MRL_SENS_PRSN 0x00000004 | |
149 | #define ATTN_LED_PRSN 0x00000008 | |
150 | #define PWR_LED_PRSN 0x00000010 | |
151 | #define HP_SUPR_RM_SUP 0x00000020 | |
152 | #define HP_CAP 0x00000040 | |
153 | #define SLOT_PWR_VALUE 0x000003F8 | |
154 | #define SLOT_PWR_LIMIT 0x00000C00 | |
155 | #define PSN 0xFFF80000 /* PSN: Physical Slot Number */ | |
156 | ||
157 | /* Field definitions in Slot Control Register */ | |
158 | #define ATTN_BUTTN_ENABLE 0x0001 | |
159 | #define PWR_FAULT_DETECT_ENABLE 0x0002 | |
160 | #define MRL_DETECT_ENABLE 0x0004 | |
161 | #define PRSN_DETECT_ENABLE 0x0008 | |
162 | #define CMD_CMPL_INTR_ENABLE 0x0010 | |
163 | #define HP_INTR_ENABLE 0x0020 | |
164 | #define ATTN_LED_CTRL 0x00C0 | |
165 | #define PWR_LED_CTRL 0x0300 | |
166 | #define PWR_CTRL 0x0400 | |
34d03419 | 167 | #define EMI_CTRL 0x0800 |
1da177e4 LT |
168 | |
169 | /* Attention indicator and Power indicator states */ | |
170 | #define LED_ON 0x01 | |
171 | #define LED_BLINK 0x10 | |
172 | #define LED_OFF 0x11 | |
173 | ||
174 | /* Power Control Command */ | |
175 | #define POWER_ON 0 | |
176 | #define POWER_OFF 0x0400 | |
177 | ||
34d03419 KCA |
178 | /* EMI Status defines */ |
179 | #define EMI_DISENGAGED 0 | |
180 | #define EMI_ENGAGED 1 | |
181 | ||
1da177e4 LT |
182 | /* Field definitions in Slot Status Register */ |
183 | #define ATTN_BUTTN_PRESSED 0x0001 | |
184 | #define PWR_FAULT_DETECTED 0x0002 | |
185 | #define MRL_SENS_CHANGED 0x0004 | |
186 | #define PRSN_DETECT_CHANGED 0x0008 | |
187 | #define CMD_COMPLETED 0x0010 | |
188 | #define MRL_STATE 0x0020 | |
189 | #define PRSN_STATE 0x0040 | |
34d03419 KCA |
190 | #define EMI_STATE 0x0080 |
191 | #define EMI_STATUS_BIT 7 | |
1da177e4 | 192 | |
48fe3915 KK |
193 | static irqreturn_t pcie_isr(int irq, void *dev_id); |
194 | static void start_int_poll_timer(struct controller *ctrl, int sec); | |
1da177e4 LT |
195 | |
196 | /* This is the interrupt polling timeout function. */ | |
48fe3915 | 197 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 198 | { |
48fe3915 | 199 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 200 | |
1da177e4 | 201 | /* Poll for interrupt events. regs == NULL => polling */ |
48fe3915 | 202 | pcie_isr(0, ctrl); |
1da177e4 | 203 | |
48fe3915 | 204 | init_timer(&ctrl->poll_timer); |
1da177e4 | 205 | if (!pciehp_poll_time) |
40730d10 | 206 | pciehp_poll_time = 2; /* default polling interval is 2 sec */ |
1da177e4 | 207 | |
48fe3915 | 208 | start_int_poll_timer(ctrl, pciehp_poll_time); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* This function starts the interrupt polling timer. */ | |
48fe3915 | 212 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 213 | { |
48fe3915 KK |
214 | /* Clamp to sane value */ |
215 | if ((sec <= 0) || (sec > 60)) | |
216 | sec = 2; | |
217 | ||
218 | ctrl->poll_timer.function = &int_poll_timeout; | |
219 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
220 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
221 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
222 | } |
223 | ||
2aeeef11 KK |
224 | static inline int pciehp_request_irq(struct controller *ctrl) |
225 | { | |
226 | int retval, irq = ctrl->pci_dev->irq; | |
227 | ||
228 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
229 | if (pciehp_poll_mode) { | |
230 | init_timer(&ctrl->poll_timer); | |
231 | start_int_poll_timer(ctrl, 10); | |
232 | return 0; | |
233 | } | |
234 | ||
235 | /* Installs the interrupt handler */ | |
236 | retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); | |
237 | if (retval) | |
238 | err("Cannot get irq %d for the hotplug controller\n", irq); | |
239 | return retval; | |
240 | } | |
241 | ||
242 | static inline void pciehp_free_irq(struct controller *ctrl) | |
243 | { | |
244 | if (pciehp_poll_mode) | |
245 | del_timer_sync(&ctrl->poll_timer); | |
246 | else | |
247 | free_irq(ctrl->pci_dev->irq, ctrl); | |
248 | } | |
249 | ||
44ef4cef KK |
250 | static inline int pcie_wait_cmd(struct controller *ctrl) |
251 | { | |
262303fe KK |
252 | int retval = 0; |
253 | unsigned int msecs = pciehp_poll_mode ? 2500 : 1000; | |
254 | unsigned long timeout = msecs_to_jiffies(msecs); | |
255 | int rc; | |
256 | ||
257 | rc = wait_event_interruptible_timeout(ctrl->queue, | |
258 | !ctrl->cmd_busy, timeout); | |
259 | if (!rc) | |
260 | dbg("Command not completed in 1000 msec\n"); | |
261 | else if (rc < 0) { | |
262 | retval = -EINTR; | |
263 | info("Command was interrupted by a signal\n"); | |
264 | } | |
44ef4cef | 265 | |
262303fe | 266 | return retval; |
44ef4cef KK |
267 | } |
268 | ||
f4778364 KK |
269 | /** |
270 | * pcie_write_cmd - Issue controller command | |
c27fb883 | 271 | * @ctrl: controller to which the command is issued |
f4778364 KK |
272 | * @cmd: command value written to slot control register |
273 | * @mask: bitmask of slot control register to be modified | |
274 | */ | |
c27fb883 | 275 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
1da177e4 | 276 | { |
1da177e4 LT |
277 | int retval = 0; |
278 | u16 slot_status; | |
f4778364 | 279 | u16 slot_ctrl; |
1da177e4 | 280 | |
44ef4cef KK |
281 | mutex_lock(&ctrl->ctrl_lock); |
282 | ||
a0f018da | 283 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 284 | if (retval) { |
66bef8c0 | 285 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
44ef4cef | 286 | goto out; |
a0f018da KK |
287 | } |
288 | ||
71ad556d | 289 | if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { |
44ef4cef KK |
290 | /* After 1 sec and CMD_COMPLETED still not set, just |
291 | proceed forward to issue the next command according | |
292 | to spec. Just print out the error message */ | |
293 | dbg("%s: CMD_COMPLETED not clear after 1 sec.\n", | |
66bef8c0 | 294 | __func__); |
1da177e4 LT |
295 | } |
296 | ||
f4778364 | 297 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 298 | if (retval) { |
66bef8c0 | 299 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
c6b069e9 | 300 | goto out; |
1da177e4 | 301 | } |
1da177e4 | 302 | |
f4778364 KK |
303 | slot_ctrl &= ~mask; |
304 | slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE); | |
305 | ||
306 | ctrl->cmd_busy = 1; | |
2d32a9ae | 307 | smp_mb(); |
f4778364 KK |
308 | retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl); |
309 | if (retval) | |
66bef8c0 | 310 | err("%s: Cannot write to SLOTCTRL register\n", __func__); |
f4778364 | 311 | |
44ef4cef KK |
312 | /* |
313 | * Wait for command completion. | |
314 | */ | |
f4778364 KK |
315 | if (!retval) |
316 | retval = pcie_wait_cmd(ctrl); | |
44ef4cef KK |
317 | out: |
318 | mutex_unlock(&ctrl->ctrl_lock); | |
1da177e4 LT |
319 | return retval; |
320 | } | |
321 | ||
322 | static int hpc_check_lnk_status(struct controller *ctrl) | |
323 | { | |
1da177e4 LT |
324 | u16 lnk_status; |
325 | int retval = 0; | |
326 | ||
a0f018da | 327 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 328 | if (retval) { |
66bef8c0 | 329 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
330 | return retval; |
331 | } | |
332 | ||
66bef8c0 | 333 | dbg("%s: lnk_status = %x\n", __func__, lnk_status); |
71ad556d | 334 | if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || |
1da177e4 | 335 | !(lnk_status & NEG_LINK_WD)) { |
66bef8c0 | 336 | err("%s : Link Training Error occurs \n", __func__); |
1da177e4 LT |
337 | retval = -1; |
338 | return retval; | |
339 | } | |
340 | ||
1da177e4 LT |
341 | return retval; |
342 | } | |
343 | ||
1da177e4 LT |
344 | static int hpc_get_attention_status(struct slot *slot, u8 *status) |
345 | { | |
48fe3915 | 346 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
347 | u16 slot_ctrl; |
348 | u8 atten_led_state; | |
349 | int retval = 0; | |
1da177e4 | 350 | |
a0f018da | 351 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 352 | if (retval) { |
66bef8c0 | 353 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
354 | return retval; |
355 | } | |
356 | ||
a0f018da | 357 | dbg("%s: SLOTCTRL %x, value read %x\n", |
66bef8c0 | 358 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1da177e4 LT |
359 | |
360 | atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6; | |
361 | ||
362 | switch (atten_led_state) { | |
363 | case 0: | |
364 | *status = 0xFF; /* Reserved */ | |
365 | break; | |
366 | case 1: | |
367 | *status = 1; /* On */ | |
368 | break; | |
369 | case 2: | |
370 | *status = 2; /* Blink */ | |
371 | break; | |
372 | case 3: | |
373 | *status = 0; /* Off */ | |
374 | break; | |
375 | default: | |
376 | *status = 0xFF; | |
377 | break; | |
378 | } | |
379 | ||
1da177e4 LT |
380 | return 0; |
381 | } | |
382 | ||
48fe3915 | 383 | static int hpc_get_power_status(struct slot *slot, u8 *status) |
1da177e4 | 384 | { |
48fe3915 | 385 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
386 | u16 slot_ctrl; |
387 | u8 pwr_state; | |
388 | int retval = 0; | |
1da177e4 | 389 | |
a0f018da | 390 | retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); |
1da177e4 | 391 | if (retval) { |
66bef8c0 | 392 | err("%s: Cannot read SLOTCTRL register\n", __func__); |
1da177e4 LT |
393 | return retval; |
394 | } | |
a0f018da | 395 | dbg("%s: SLOTCTRL %x value read %x\n", |
66bef8c0 | 396 | __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl); |
1da177e4 LT |
397 | |
398 | pwr_state = (slot_ctrl & PWR_CTRL) >> 10; | |
399 | ||
400 | switch (pwr_state) { | |
401 | case 0: | |
402 | *status = 1; | |
403 | break; | |
404 | case 1: | |
71ad556d | 405 | *status = 0; |
1da177e4 LT |
406 | break; |
407 | default: | |
408 | *status = 0xFF; | |
409 | break; | |
410 | } | |
411 | ||
1da177e4 LT |
412 | return retval; |
413 | } | |
414 | ||
1da177e4 LT |
415 | static int hpc_get_latch_status(struct slot *slot, u8 *status) |
416 | { | |
48fe3915 | 417 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
418 | u16 slot_status; |
419 | int retval = 0; | |
420 | ||
a0f018da | 421 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 422 | if (retval) { |
66bef8c0 | 423 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
1da177e4 LT |
424 | return retval; |
425 | } | |
426 | ||
71ad556d | 427 | *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1; |
1da177e4 | 428 | |
1da177e4 LT |
429 | return 0; |
430 | } | |
431 | ||
432 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
433 | { | |
48fe3915 | 434 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
435 | u16 slot_status; |
436 | u8 card_state; | |
437 | int retval = 0; | |
438 | ||
a0f018da | 439 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 440 | if (retval) { |
66bef8c0 | 441 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
1da177e4 LT |
442 | return retval; |
443 | } | |
444 | card_state = (u8)((slot_status & PRSN_STATE) >> 6); | |
445 | *status = (card_state == 1) ? 1 : 0; | |
446 | ||
1da177e4 LT |
447 | return 0; |
448 | } | |
449 | ||
48fe3915 | 450 | static int hpc_query_power_fault(struct slot *slot) |
1da177e4 | 451 | { |
48fe3915 | 452 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
453 | u16 slot_status; |
454 | u8 pwr_fault; | |
455 | int retval = 0; | |
1da177e4 | 456 | |
a0f018da | 457 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
1da177e4 | 458 | if (retval) { |
66bef8c0 | 459 | err("%s: Cannot check for power fault\n", __func__); |
1da177e4 LT |
460 | return retval; |
461 | } | |
462 | pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1); | |
71ad556d | 463 | |
8239def1 | 464 | return pwr_fault; |
1da177e4 LT |
465 | } |
466 | ||
34d03419 KCA |
467 | static int hpc_get_emi_status(struct slot *slot, u8 *status) |
468 | { | |
469 | struct controller *ctrl = slot->ctrl; | |
470 | u16 slot_status; | |
471 | int retval = 0; | |
472 | ||
34d03419 KCA |
473 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
474 | if (retval) { | |
66bef8c0 | 475 | err("%s : Cannot check EMI status\n", __func__); |
34d03419 KCA |
476 | return retval; |
477 | } | |
478 | *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT; | |
479 | ||
34d03419 KCA |
480 | return retval; |
481 | } | |
482 | ||
483 | static int hpc_toggle_emi(struct slot *slot) | |
484 | { | |
f4778364 KK |
485 | u16 slot_cmd; |
486 | u16 cmd_mask; | |
487 | int rc; | |
34d03419 | 488 | |
f4778364 KK |
489 | slot_cmd = EMI_CTRL; |
490 | cmd_mask = EMI_CTRL; | |
c27fb883 | 491 | rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask); |
34d03419 | 492 | slot->last_emi_toggle = get_seconds(); |
c8426483 | 493 | |
34d03419 KCA |
494 | return rc; |
495 | } | |
496 | ||
1da177e4 LT |
497 | static int hpc_set_attention_status(struct slot *slot, u8 value) |
498 | { | |
48fe3915 | 499 | struct controller *ctrl = slot->ctrl; |
f4778364 KK |
500 | u16 slot_cmd; |
501 | u16 cmd_mask; | |
502 | int rc; | |
1da177e4 | 503 | |
f4778364 | 504 | cmd_mask = ATTN_LED_CTRL; |
1da177e4 LT |
505 | switch (value) { |
506 | case 0 : /* turn off */ | |
f4778364 | 507 | slot_cmd = 0x00C0; |
1da177e4 LT |
508 | break; |
509 | case 1: /* turn on */ | |
f4778364 | 510 | slot_cmd = 0x0040; |
1da177e4 LT |
511 | break; |
512 | case 2: /* turn blink */ | |
f4778364 | 513 | slot_cmd = 0x0080; |
1da177e4 LT |
514 | break; |
515 | default: | |
516 | return -1; | |
517 | } | |
c27fb883 | 518 | rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 519 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 520 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
71ad556d | 521 | |
1da177e4 LT |
522 | return rc; |
523 | } | |
524 | ||
1da177e4 LT |
525 | static void hpc_set_green_led_on(struct slot *slot) |
526 | { | |
48fe3915 | 527 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 528 | u16 slot_cmd; |
f4778364 | 529 | u16 cmd_mask; |
71ad556d | 530 | |
f4778364 KK |
531 | slot_cmd = 0x0100; |
532 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 533 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 534 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 535 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
536 | } |
537 | ||
538 | static void hpc_set_green_led_off(struct slot *slot) | |
539 | { | |
48fe3915 | 540 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 541 | u16 slot_cmd; |
f4778364 | 542 | u16 cmd_mask; |
1da177e4 | 543 | |
f4778364 KK |
544 | slot_cmd = 0x0300; |
545 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 546 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 547 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 548 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
549 | } |
550 | ||
551 | static void hpc_set_green_led_blink(struct slot *slot) | |
552 | { | |
48fe3915 | 553 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 554 | u16 slot_cmd; |
f4778364 | 555 | u16 cmd_mask; |
71ad556d | 556 | |
f4778364 KK |
557 | slot_cmd = 0x0200; |
558 | cmd_mask = PWR_LED_CTRL; | |
c27fb883 | 559 | pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
a0f018da | 560 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 561 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 LT |
562 | } |
563 | ||
1da177e4 LT |
564 | static void hpc_release_ctlr(struct controller *ctrl) |
565 | { | |
d84be093 KK |
566 | /* Mask Hot-plug Interrupt Enable */ |
567 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) | |
568 | err("%s: Cannot mask hotplut interrupt enable\n", __func__); | |
569 | ||
2aeeef11 KK |
570 | /* Free interrupt handler or interrupt polling timer */ |
571 | pciehp_free_irq(ctrl); | |
1da177e4 | 572 | |
5d386e1a KK |
573 | /* |
574 | * If this is the last controller to be released, destroy the | |
575 | * pciehp work queue | |
576 | */ | |
577 | if (atomic_dec_and_test(&pciehp_num_controllers)) | |
578 | destroy_workqueue(pciehp_wq); | |
1da177e4 LT |
579 | } |
580 | ||
581 | static int hpc_power_on_slot(struct slot * slot) | |
582 | { | |
48fe3915 | 583 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 584 | u16 slot_cmd; |
f4778364 KK |
585 | u16 cmd_mask; |
586 | u16 slot_status; | |
1da177e4 LT |
587 | int retval = 0; |
588 | ||
66bef8c0 | 589 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 590 | |
5a49f203 | 591 | /* Clear sticky power-fault bit from previous power failures */ |
a0f018da KK |
592 | retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); |
593 | if (retval) { | |
66bef8c0 | 594 | err("%s: Cannot read SLOTSTATUS register\n", __func__); |
a0f018da KK |
595 | return retval; |
596 | } | |
5a49f203 | 597 | slot_status &= PWR_FAULT_DETECTED; |
a0f018da KK |
598 | if (slot_status) { |
599 | retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status); | |
600 | if (retval) { | |
601 | err("%s: Cannot write to SLOTSTATUS register\n", | |
66bef8c0 | 602 | __func__); |
a0f018da KK |
603 | return retval; |
604 | } | |
605 | } | |
1da177e4 | 606 | |
f4778364 KK |
607 | slot_cmd = POWER_ON; |
608 | cmd_mask = PWR_CTRL; | |
c7ab337f | 609 | /* Enable detection that we turned off at slot power-off time */ |
f4778364 | 610 | if (!pciehp_poll_mode) { |
cff00654 KK |
611 | slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
612 | PRSN_DETECT_ENABLE); | |
613 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
614 | PRSN_DETECT_ENABLE); | |
f4778364 | 615 | } |
1da177e4 | 616 | |
c27fb883 | 617 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 LT |
618 | |
619 | if (retval) { | |
66bef8c0 | 620 | err("%s: Write %x command failed!\n", __func__, slot_cmd); |
1da177e4 LT |
621 | return -1; |
622 | } | |
a0f018da | 623 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 624 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 | 625 | |
1da177e4 LT |
626 | return retval; |
627 | } | |
628 | ||
f1050a35 KK |
629 | static inline int pcie_mask_bad_dllp(struct controller *ctrl) |
630 | { | |
631 | struct pci_dev *dev = ctrl->pci_dev; | |
632 | int pos; | |
633 | u32 reg; | |
634 | ||
635 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
636 | if (!pos) | |
637 | return 0; | |
638 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
639 | if (reg & PCI_ERR_COR_BAD_DLLP) | |
640 | return 0; | |
641 | reg |= PCI_ERR_COR_BAD_DLLP; | |
642 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
643 | return 1; | |
644 | } | |
645 | ||
646 | static inline void pcie_unmask_bad_dllp(struct controller *ctrl) | |
647 | { | |
648 | struct pci_dev *dev = ctrl->pci_dev; | |
649 | u32 reg; | |
650 | int pos; | |
651 | ||
652 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
653 | if (!pos) | |
654 | return; | |
655 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®); | |
656 | if (!(reg & PCI_ERR_COR_BAD_DLLP)) | |
657 | return; | |
658 | reg &= ~PCI_ERR_COR_BAD_DLLP; | |
659 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg); | |
660 | } | |
661 | ||
1da177e4 LT |
662 | static int hpc_power_off_slot(struct slot * slot) |
663 | { | |
48fe3915 | 664 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 665 | u16 slot_cmd; |
f4778364 | 666 | u16 cmd_mask; |
1da177e4 | 667 | int retval = 0; |
f1050a35 | 668 | int changed; |
1da177e4 | 669 | |
66bef8c0 | 670 | dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot); |
1da177e4 | 671 | |
f1050a35 KK |
672 | /* |
673 | * Set Bad DLLP Mask bit in Correctable Error Mask | |
674 | * Register. This is the workaround against Bad DLLP error | |
675 | * that sometimes happens during turning power off the slot | |
676 | * which conforms to PCI Express 1.0a spec. | |
677 | */ | |
678 | changed = pcie_mask_bad_dllp(ctrl); | |
679 | ||
f4778364 KK |
680 | slot_cmd = POWER_OFF; |
681 | cmd_mask = PWR_CTRL; | |
c7ab337f TS |
682 | /* |
683 | * If we get MRL or presence detect interrupts now, the isr | |
684 | * will notice the sticky power-fault bit too and issue power | |
685 | * indicator change commands. This will lead to an endless loop | |
686 | * of command completions, since the power-fault bit remains on | |
687 | * till the slot is powered on again. | |
688 | */ | |
f4778364 | 689 | if (!pciehp_poll_mode) { |
cff00654 KK |
690 | slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | |
691 | PRSN_DETECT_ENABLE); | |
692 | cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | | |
693 | PRSN_DETECT_ENABLE); | |
f4778364 | 694 | } |
1da177e4 | 695 | |
c27fb883 | 696 | retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask); |
1da177e4 | 697 | if (retval) { |
66bef8c0 | 698 | err("%s: Write command failed!\n", __func__); |
c1ef5cbd KK |
699 | retval = -1; |
700 | goto out; | |
1da177e4 | 701 | } |
a0f018da | 702 | dbg("%s: SLOTCTRL %x write cmd %x\n", |
66bef8c0 | 703 | __func__, ctrl->cap_base + SLOTCTRL, slot_cmd); |
1da177e4 | 704 | |
8bb7c7af KK |
705 | /* |
706 | * After turning power off, we must wait for at least 1 second | |
707 | * before taking any action that relies on power having been | |
708 | * removed from the slot/adapter. | |
709 | */ | |
710 | msleep(1000); | |
c1ef5cbd | 711 | out: |
f1050a35 KK |
712 | if (changed) |
713 | pcie_unmask_bad_dllp(ctrl); | |
714 | ||
1da177e4 LT |
715 | return retval; |
716 | } | |
717 | ||
48fe3915 | 718 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
1da177e4 | 719 | { |
48fe3915 | 720 | struct controller *ctrl = (struct controller *)dev_id; |
c6b069e9 | 721 | u16 detected, intr_loc; |
1da177e4 | 722 | |
c6b069e9 KK |
723 | /* |
724 | * In order to guarantee that all interrupt events are | |
725 | * serviced, we need to re-inspect Slot Status register after | |
726 | * clearing what is presumed to be the last pending interrupt. | |
727 | */ | |
728 | intr_loc = 0; | |
729 | do { | |
730 | if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) { | |
731 | err("%s: Cannot read SLOTSTATUS\n", __func__); | |
1da177e4 LT |
732 | return IRQ_NONE; |
733 | } | |
734 | ||
c6b069e9 KK |
735 | detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | |
736 | MRL_SENS_CHANGED | PRSN_DETECT_CHANGED | | |
737 | CMD_COMPLETED); | |
738 | intr_loc |= detected; | |
739 | if (!intr_loc) | |
1da177e4 | 740 | return IRQ_NONE; |
c6b069e9 KK |
741 | if (pciehp_writew(ctrl, SLOTSTATUS, detected)) { |
742 | err("%s: Cannot write to SLOTSTATUS\n", __func__); | |
1da177e4 LT |
743 | return IRQ_NONE; |
744 | } | |
c6b069e9 | 745 | } while (detected); |
71ad556d | 746 | |
c6b069e9 | 747 | dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc); |
71ad556d | 748 | |
c6b069e9 | 749 | /* Check Command Complete Interrupt Pending */ |
1da177e4 | 750 | if (intr_loc & CMD_COMPLETED) { |
262303fe | 751 | ctrl->cmd_busy = 0; |
2d32a9ae | 752 | smp_mb(); |
1da177e4 LT |
753 | wake_up_interruptible(&ctrl->queue); |
754 | } | |
755 | ||
c6b069e9 | 756 | /* Check MRL Sensor Changed */ |
48fe3915 | 757 | if (intr_loc & MRL_SENS_CHANGED) |
c6b069e9 | 758 | pciehp_handle_switch_change(0, ctrl); |
48fe3915 | 759 | |
c6b069e9 | 760 | /* Check Attention Button Pressed */ |
48fe3915 | 761 | if (intr_loc & ATTN_BUTTN_PRESSED) |
c6b069e9 | 762 | pciehp_handle_attention_button(0, ctrl); |
48fe3915 | 763 | |
c6b069e9 | 764 | /* Check Presence Detect Changed */ |
48fe3915 | 765 | if (intr_loc & PRSN_DETECT_CHANGED) |
c6b069e9 | 766 | pciehp_handle_presence_change(0, ctrl); |
48fe3915 | 767 | |
c6b069e9 | 768 | /* Check Power Fault Detected */ |
48fe3915 | 769 | if (intr_loc & PWR_FAULT_DETECTED) |
c6b069e9 | 770 | pciehp_handle_power_fault(0, ctrl); |
71ad556d | 771 | |
1da177e4 LT |
772 | return IRQ_HANDLED; |
773 | } | |
774 | ||
40730d10 | 775 | static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 776 | { |
48fe3915 | 777 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
778 | enum pcie_link_speed lnk_speed; |
779 | u32 lnk_cap; | |
780 | int retval = 0; | |
781 | ||
a0f018da | 782 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 783 | if (retval) { |
66bef8c0 | 784 | err("%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
785 | return retval; |
786 | } | |
787 | ||
788 | switch (lnk_cap & 0x000F) { | |
789 | case 1: | |
790 | lnk_speed = PCIE_2PT5GB; | |
791 | break; | |
792 | default: | |
793 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
794 | break; | |
795 | } | |
796 | ||
797 | *value = lnk_speed; | |
798 | dbg("Max link speed = %d\n", lnk_speed); | |
c8426483 | 799 | |
1da177e4 LT |
800 | return retval; |
801 | } | |
802 | ||
40730d10 KK |
803 | static int hpc_get_max_lnk_width(struct slot *slot, |
804 | enum pcie_link_width *value) | |
1da177e4 | 805 | { |
48fe3915 | 806 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
807 | enum pcie_link_width lnk_wdth; |
808 | u32 lnk_cap; | |
809 | int retval = 0; | |
810 | ||
a0f018da | 811 | retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap); |
1da177e4 | 812 | if (retval) { |
66bef8c0 | 813 | err("%s: Cannot read LNKCAP register\n", __func__); |
1da177e4 LT |
814 | return retval; |
815 | } | |
816 | ||
817 | switch ((lnk_cap & 0x03F0) >> 4){ | |
818 | case 0: | |
819 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
820 | break; | |
821 | case 1: | |
822 | lnk_wdth = PCIE_LNK_X1; | |
823 | break; | |
824 | case 2: | |
825 | lnk_wdth = PCIE_LNK_X2; | |
826 | break; | |
827 | case 4: | |
828 | lnk_wdth = PCIE_LNK_X4; | |
829 | break; | |
830 | case 8: | |
831 | lnk_wdth = PCIE_LNK_X8; | |
832 | break; | |
833 | case 12: | |
834 | lnk_wdth = PCIE_LNK_X12; | |
835 | break; | |
836 | case 16: | |
837 | lnk_wdth = PCIE_LNK_X16; | |
838 | break; | |
839 | case 32: | |
840 | lnk_wdth = PCIE_LNK_X32; | |
841 | break; | |
842 | default: | |
843 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
844 | break; | |
845 | } | |
846 | ||
847 | *value = lnk_wdth; | |
848 | dbg("Max link width = %d\n", lnk_wdth); | |
c8426483 | 849 | |
1da177e4 LT |
850 | return retval; |
851 | } | |
852 | ||
40730d10 | 853 | static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value) |
1da177e4 | 854 | { |
48fe3915 | 855 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
856 | enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN; |
857 | int retval = 0; | |
858 | u16 lnk_status; | |
859 | ||
a0f018da | 860 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 861 | if (retval) { |
66bef8c0 | 862 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
863 | return retval; |
864 | } | |
865 | ||
866 | switch (lnk_status & 0x0F) { | |
867 | case 1: | |
868 | lnk_speed = PCIE_2PT5GB; | |
869 | break; | |
870 | default: | |
871 | lnk_speed = PCIE_LNK_SPEED_UNKNOWN; | |
872 | break; | |
873 | } | |
874 | ||
875 | *value = lnk_speed; | |
876 | dbg("Current link speed = %d\n", lnk_speed); | |
c8426483 | 877 | |
1da177e4 LT |
878 | return retval; |
879 | } | |
880 | ||
40730d10 KK |
881 | static int hpc_get_cur_lnk_width(struct slot *slot, |
882 | enum pcie_link_width *value) | |
1da177e4 | 883 | { |
48fe3915 | 884 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
885 | enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; |
886 | int retval = 0; | |
887 | u16 lnk_status; | |
888 | ||
a0f018da | 889 | retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status); |
1da177e4 | 890 | if (retval) { |
66bef8c0 | 891 | err("%s: Cannot read LNKSTATUS register\n", __func__); |
1da177e4 LT |
892 | return retval; |
893 | } | |
71ad556d | 894 | |
1da177e4 LT |
895 | switch ((lnk_status & 0x03F0) >> 4){ |
896 | case 0: | |
897 | lnk_wdth = PCIE_LNK_WIDTH_RESRV; | |
898 | break; | |
899 | case 1: | |
900 | lnk_wdth = PCIE_LNK_X1; | |
901 | break; | |
902 | case 2: | |
903 | lnk_wdth = PCIE_LNK_X2; | |
904 | break; | |
905 | case 4: | |
906 | lnk_wdth = PCIE_LNK_X4; | |
907 | break; | |
908 | case 8: | |
909 | lnk_wdth = PCIE_LNK_X8; | |
910 | break; | |
911 | case 12: | |
912 | lnk_wdth = PCIE_LNK_X12; | |
913 | break; | |
914 | case 16: | |
915 | lnk_wdth = PCIE_LNK_X16; | |
916 | break; | |
917 | case 32: | |
918 | lnk_wdth = PCIE_LNK_X32; | |
919 | break; | |
920 | default: | |
921 | lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN; | |
922 | break; | |
923 | } | |
924 | ||
925 | *value = lnk_wdth; | |
926 | dbg("Current link width = %d\n", lnk_wdth); | |
c8426483 | 927 | |
1da177e4 LT |
928 | return retval; |
929 | } | |
930 | ||
931 | static struct hpc_ops pciehp_hpc_ops = { | |
932 | .power_on_slot = hpc_power_on_slot, | |
933 | .power_off_slot = hpc_power_off_slot, | |
934 | .set_attention_status = hpc_set_attention_status, | |
935 | .get_power_status = hpc_get_power_status, | |
936 | .get_attention_status = hpc_get_attention_status, | |
937 | .get_latch_status = hpc_get_latch_status, | |
938 | .get_adapter_status = hpc_get_adapter_status, | |
34d03419 KCA |
939 | .get_emi_status = hpc_get_emi_status, |
940 | .toggle_emi = hpc_toggle_emi, | |
1da177e4 LT |
941 | |
942 | .get_max_bus_speed = hpc_get_max_lnk_speed, | |
943 | .get_cur_bus_speed = hpc_get_cur_lnk_speed, | |
944 | .get_max_lnk_width = hpc_get_max_lnk_width, | |
945 | .get_cur_lnk_width = hpc_get_cur_lnk_width, | |
71ad556d | 946 | |
1da177e4 LT |
947 | .query_power_fault = hpc_query_power_fault, |
948 | .green_led_on = hpc_set_green_led_on, | |
949 | .green_led_off = hpc_set_green_led_off, | |
950 | .green_led_blink = hpc_set_green_led_blink, | |
71ad556d | 951 | |
1da177e4 LT |
952 | .release_ctlr = hpc_release_ctlr, |
953 | .check_lnk_status = hpc_check_lnk_status, | |
954 | }; | |
955 | ||
783c49fc | 956 | #ifdef CONFIG_ACPI |
4ea3e58b | 957 | static int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev) |
783c49fc KA |
958 | { |
959 | acpi_status status; | |
960 | acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev)); | |
961 | struct pci_dev *pdev = dev; | |
962 | struct pci_bus *parent; | |
b2e6e3ba | 963 | struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL }; |
783c49fc KA |
964 | |
965 | /* | |
966 | * Per PCI firmware specification, we should run the ACPI _OSC | |
967 | * method to get control of hotplug hardware before using it. | |
968 | * If an _OSC is missing, we look for an OSHP to do the same thing. | |
969 | * To handle different BIOS behavior, we look for _OSC and OSHP | |
970 | * within the scope of the hotplug controller and its parents, upto | |
971 | * the host bridge under which this controller exists. | |
972 | */ | |
973 | while (!handle) { | |
974 | /* | |
975 | * This hotplug controller was not listed in the ACPI name | |
976 | * space at all. Try to get acpi handle of parent pci bus. | |
977 | */ | |
978 | if (!pdev || !pdev->bus->parent) | |
979 | break; | |
980 | parent = pdev->bus->parent; | |
981 | dbg("Could not find %s in acpi namespace, trying parent\n", | |
982 | pci_name(pdev)); | |
983 | if (!parent->self) | |
984 | /* Parent must be a host bridge */ | |
985 | handle = acpi_get_pci_rootbridge_handle( | |
986 | pci_domain_nr(parent), | |
987 | parent->number); | |
988 | else | |
989 | handle = DEVICE_ACPI_HANDLE( | |
990 | &(parent->self->dev)); | |
991 | pdev = parent->self; | |
992 | } | |
993 | ||
994 | while (handle) { | |
b2e6e3ba MT |
995 | acpi_get_name(handle, ACPI_FULL_PATHNAME, &string); |
996 | dbg("Trying to get hotplug control for %s \n", | |
997 | (char *)string.pointer); | |
783c49fc | 998 | status = pci_osc_control_set(handle, |
57d90c02 | 999 | OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL | |
783c49fc KA |
1000 | OSC_PCI_EXPRESS_NATIVE_HP_CONTROL); |
1001 | if (status == AE_NOT_FOUND) | |
1002 | status = acpi_run_oshp(handle); | |
1003 | if (ACPI_SUCCESS(status)) { | |
1004 | dbg("Gained control for hotplug HW for pci %s (%s)\n", | |
b2e6e3ba | 1005 | pci_name(dev), (char *)string.pointer); |
81b26bca | 1006 | kfree(string.pointer); |
783c49fc KA |
1007 | return 0; |
1008 | } | |
1009 | if (acpi_root_bridge(handle)) | |
1010 | break; | |
1011 | chandle = handle; | |
1012 | status = acpi_get_parent(chandle, &handle); | |
1013 | if (ACPI_FAILURE(status)) | |
1014 | break; | |
1015 | } | |
1016 | ||
1017 | err("Cannot get control of hotplug hardware for pci %s\n", | |
1018 | pci_name(dev)); | |
b2e6e3ba | 1019 | |
81b26bca | 1020 | kfree(string.pointer); |
783c49fc KA |
1021 | return -1; |
1022 | } | |
1023 | #endif | |
1024 | ||
ecdde939 ML |
1025 | static int pcie_init_hardware_part1(struct controller *ctrl, |
1026 | struct pcie_device *dev) | |
1da177e4 | 1027 | { |
1da177e4 | 1028 | /* Mask Hot-plug Interrupt Enable */ |
c27fb883 KK |
1029 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) { |
1030 | err("%s: Cannot mask hotplug interrupt enable\n", __func__); | |
ecdde939 | 1031 | return -1; |
1da177e4 | 1032 | } |
ecdde939 ML |
1033 | return 0; |
1034 | } | |
1a9ed1bf | 1035 | |
ecdde939 ML |
1036 | int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev) |
1037 | { | |
c27fb883 | 1038 | u16 cmd, mask; |
1da177e4 | 1039 | |
40730d10 | 1040 | /* |
c27fb883 KK |
1041 | * We need to clear all events before enabling hotplug interrupt |
1042 | * notification mechanism in order for hotplug controler to | |
1043 | * generate interrupts. | |
40730d10 | 1044 | */ |
c27fb883 KK |
1045 | if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) { |
1046 | err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__); | |
1047 | return -1; | |
1da177e4 | 1048 | } |
71ad556d | 1049 | |
c27fb883 | 1050 | cmd = PRSN_DETECT_ENABLE; |
ae416e6b | 1051 | if (ATTN_BUTTN(ctrl)) |
c27fb883 | 1052 | cmd |= ATTN_BUTTN_ENABLE; |
ae416e6b | 1053 | if (POWER_CTRL(ctrl)) |
c27fb883 | 1054 | cmd |= PWR_FAULT_DETECT_ENABLE; |
ae416e6b | 1055 | if (MRL_SENS(ctrl)) |
c27fb883 KK |
1056 | cmd |= MRL_DETECT_ENABLE; |
1057 | if (!pciehp_poll_mode) | |
1058 | cmd |= HP_INTR_ENABLE; | |
1059 | ||
1060 | mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE | | |
1061 | PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE; | |
1062 | ||
1063 | if (pcie_write_cmd(ctrl, cmd, mask)) { | |
1064 | err("%s: Cannot enable software notification\n", __func__); | |
1065 | goto abort; | |
1da177e4 | 1066 | } |
71ad556d | 1067 | |
c27fb883 | 1068 | if (pciehp_force) |
a3a45ec8 RS |
1069 | dbg("Bypassing BIOS check for pciehp use on %s\n", |
1070 | pci_name(ctrl->pci_dev)); | |
c27fb883 KK |
1071 | else if (pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev)) |
1072 | goto abort_disable_intr; | |
a8a2be94 | 1073 | |
1da177e4 LT |
1074 | return 0; |
1075 | ||
40730d10 | 1076 | /* We end up here for the many possible ways to fail this API. */ |
9c64f977 | 1077 | abort_disable_intr: |
c27fb883 | 1078 | if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE)) |
66bef8c0 | 1079 | err("%s : disabling interrupts failed\n", __func__); |
ecdde939 | 1080 | abort: |
1da177e4 LT |
1081 | return -1; |
1082 | } | |
08e7a7d2 | 1083 | |
2aeeef11 | 1084 | static inline void dbg_ctrl(struct controller *ctrl) |
08e7a7d2 | 1085 | { |
2aeeef11 KK |
1086 | int i; |
1087 | u16 reg16; | |
1088 | struct pci_dev *pdev = ctrl->pci_dev; | |
08e7a7d2 | 1089 | |
2aeeef11 KK |
1090 | if (!pciehp_debug) |
1091 | return; | |
08e7a7d2 | 1092 | |
2aeeef11 KK |
1093 | dbg("Hotplug Controller:\n"); |
1094 | dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq); | |
1095 | dbg(" Vendor ID : 0x%04x\n", pdev->vendor); | |
1096 | dbg(" Device ID : 0x%04x\n", pdev->device); | |
1097 | dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device); | |
1098 | dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor); | |
1099 | dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base); | |
1100 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1101 | if (!pci_resource_len(pdev, i)) | |
1102 | continue; | |
1103 | dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i, | |
1104 | (unsigned long long)pci_resource_len(pdev, i), | |
1105 | (unsigned long long)pci_resource_start(pdev, i)); | |
08e7a7d2 | 1106 | } |
2aeeef11 KK |
1107 | dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap); |
1108 | dbg(" Physical Slot Number : %d\n", ctrl->first_slot); | |
1109 | dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no"); | |
1110 | dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no"); | |
1111 | dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no"); | |
1112 | dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no"); | |
1113 | dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no"); | |
1114 | dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no"); | |
1115 | dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no"); | |
1116 | pciehp_readw(ctrl, SLOTSTATUS, ®16); | |
1117 | dbg("Slot Status : 0x%04x\n", reg16); | |
1118 | pciehp_readw(ctrl, SLOTSTATUS, ®16); | |
1119 | dbg("Slot Control : 0x%04x\n", reg16); | |
1120 | } | |
08e7a7d2 | 1121 | |
2aeeef11 KK |
1122 | int pcie_init(struct controller *ctrl, struct pcie_device *dev) |
1123 | { | |
1124 | u32 slot_cap; | |
1125 | struct pci_dev *pdev = dev->port; | |
08e7a7d2 | 1126 | |
2aeeef11 KK |
1127 | ctrl->pci_dev = pdev; |
1128 | ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1129 | if (!ctrl->cap_base) { | |
1130 | err("%s: Cannot find PCI Express capability\n", __func__); | |
08e7a7d2 ML |
1131 | goto abort; |
1132 | } | |
2aeeef11 | 1133 | if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) { |
66bef8c0 | 1134 | err("%s: Cannot read SLOTCAP register\n", __func__); |
08e7a7d2 ML |
1135 | goto abort; |
1136 | } | |
08e7a7d2 | 1137 | |
2aeeef11 KK |
1138 | ctrl->slot_cap = slot_cap; |
1139 | ctrl->first_slot = slot_cap >> 19; | |
1140 | ctrl->slot_device_offset = 0; | |
1141 | ctrl->num_slots = 1; | |
1142 | ctrl->hpc_ops = &pciehp_hpc_ops; | |
08e7a7d2 ML |
1143 | mutex_init(&ctrl->crit_sect); |
1144 | mutex_init(&ctrl->ctrl_lock); | |
08e7a7d2 | 1145 | init_waitqueue_head(&ctrl->queue); |
2aeeef11 | 1146 | dbg_ctrl(ctrl); |
08e7a7d2 | 1147 | |
2aeeef11 KK |
1148 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
1149 | pdev->vendor, pdev->device, | |
1150 | pdev->subsystem_vendor, pdev->subsystem_device); | |
08e7a7d2 | 1151 | |
2aeeef11 | 1152 | if (pcie_init_hardware_part1(ctrl, dev)) |
ecdde939 ML |
1153 | goto abort; |
1154 | ||
2aeeef11 KK |
1155 | if (pciehp_request_irq(ctrl)) |
1156 | goto abort; | |
ecdde939 ML |
1157 | |
1158 | /* | |
1159 | * If this is the first controller to be initialized, | |
1160 | * initialize the pciehp work queue | |
1161 | */ | |
1162 | if (atomic_add_return(1, &pciehp_num_controllers) == 1) { | |
1163 | pciehp_wq = create_singlethread_workqueue("pciehpd"); | |
1164 | if (!pciehp_wq) { | |
ecdde939 ML |
1165 | goto abort_free_irq; |
1166 | } | |
1167 | } | |
1168 | ||
2aeeef11 KK |
1169 | if (pcie_init_hardware_part2(ctrl, dev)) |
1170 | goto abort_free_irq; | |
1171 | ||
1172 | return 0; | |
1173 | ||
ecdde939 | 1174 | abort_free_irq: |
2aeeef11 | 1175 | pciehp_free_irq(ctrl); |
08e7a7d2 ML |
1176 | abort: |
1177 | return -1; | |
1178 | } |