[mirror_ubuntu-zesty-kernel.git] / drivers / pci / hotplug / shpchp.h

/*
 * Standard Hot Plug Controller Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
 *
 */
#ifndef _SHPCHP_H
#define _SHPCHP_H

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/pci_hotplug.h>
#include <linux/delay.h>
#include <linux/sched.h>	/* signal_pending(), struct timer_list */
#include <linux/mutex.h>
#include <linux/workqueue.h>

#if !defined(MODULE)
	#define MY_NAME	"shpchp"
#else
	#define MY_NAME	THIS_MODULE->name
#endif

extern bool shpchp_poll_mode;
extern int shpchp_poll_time;
extern bool shpchp_debug;

#define dbg(format, arg...)						\
do {									\
	if (shpchp_debug)						\
		printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg);	\
} while (0)
#define err(format, arg...)						\
	printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
#define info(format, arg...)						\
	printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
#define warn(format, arg...)						\
	printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)

#define ctrl_dbg(ctrl, format, arg...)					\
	do {								\
		if (shpchp_debug)					\
			dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev,	\
					format, ## arg);		\
	} while (0)
#define ctrl_err(ctrl, format, arg...)					\
	dev_err(&ctrl->pci_dev->dev, format, ## arg)
#define ctrl_info(ctrl, format, arg...)					\
	dev_info(&ctrl->pci_dev->dev, format, ## arg)
#define ctrl_warn(ctrl, format, arg...)					\
	dev_warn(&ctrl->pci_dev->dev, format, ## arg)


#define SLOT_NAME_SIZE 10
struct slot {
	u8 bus;
	u8 device;
	u16 status;
	u32 number;
	u8 is_a_board;
	u8 state;
	u8 presence_save;
	u8 pwr_save;
	struct controller *ctrl;
	const struct hpc_ops *hpc_ops;
	struct hotplug_slot *hotplug_slot;
	struct list_head	slot_list;
	struct delayed_work work;	/* work for button event */
	struct mutex lock;
	struct workqueue_struct *wq;
	u8 hp_slot;
};

struct event_info {
	u32 event_type;
	struct slot *p_slot;
	struct work_struct work;
};

struct controller {
	struct mutex crit_sect;		/* critical section mutex */
	struct mutex cmd_lock;		/* command lock */
	int num_slots;			/* Number of slots on ctlr */
	int slot_num_inc;		/* 1 or -1 */
	struct pci_dev *pci_dev;
	struct list_head slot_list;
	const struct hpc_ops *hpc_ops;
	wait_queue_head_t queue;	/* sleep & wake process */
	u8 slot_device_offset;
	u32 pcix_misc2_reg;	/* for amd pogo errata */
	u32 first_slot;		/* First physical slot number */
	u32 cap_offset;
	unsigned long mmio_base;
	unsigned long mmio_size;
	void __iomem *creg;
	struct timer_list poll_timer;
};

/* Define AMD SHPC ID  */
#define PCI_DEVICE_ID_AMD_GOLAM_7450	0x7450
#define PCI_DEVICE_ID_AMD_POGO_7458	0x7458

/* AMD PCI-X bridge registers */
#define PCIX_MEM_BASE_LIMIT_OFFSET	0x1C
#define PCIX_MISCII_OFFSET		0x48
#define PCIX_MISC_BRIDGE_ERRORS_OFFSET	0x80

/* AMD PCIX_MISCII masks and offsets */
#define PERRNONFATALENABLE_MASK		0x00040000
#define PERRFATALENABLE_MASK		0x00080000
#define PERRFLOODENABLE_MASK		0x00100000
#define SERRNONFATALENABLE_MASK		0x00200000
#define SERRFATALENABLE_MASK		0x00400000

/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
#define PERR_OBSERVED_MASK		0x00000001

/* AMD PCIX_MEM_BASE_LIMIT masks */
#define RSE_MASK			0x40000000

#define INT_BUTTON_IGNORE		0
#define INT_PRESENCE_ON			1
#define INT_PRESENCE_OFF		2
#define INT_SWITCH_CLOSE		3
#define INT_SWITCH_OPEN			4
#define INT_POWER_FAULT			5
#define INT_POWER_FAULT_CLEAR		6
#define INT_BUTTON_PRESS		7
#define INT_BUTTON_RELEASE		8
#define INT_BUTTON_CANCEL		9

#define STATIC_STATE			0
#define BLINKINGON_STATE		1
#define BLINKINGOFF_STATE		2
#define POWERON_STATE			3
#define POWEROFF_STATE			4

/* Error messages */
#define INTERLOCK_OPEN			0x00000002
#define ADD_NOT_SUPPORTED		0x00000003
#define CARD_FUNCTIONING		0x00000005
#define ADAPTER_NOT_SAME		0x00000006
#define NO_ADAPTER_PRESENT		0x00000009
#define NOT_ENOUGH_RESOURCES		0x0000000B
#define DEVICE_TYPE_NOT_SUPPORTED	0x0000000C
#define WRONG_BUS_FREQUENCY		0x0000000D
#define POWER_FAILURE			0x0000000E

int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
void shpchp_remove_ctrl_files(struct controller *ctrl);
int shpchp_sysfs_enable_slot(struct slot *slot);
int shpchp_sysfs_disable_slot(struct slot *slot);
u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
int shpchp_configure_device(struct slot *p_slot);
int shpchp_unconfigure_device(struct slot *p_slot);
void cleanup_slots(struct controller *ctrl);
void shpchp_queue_pushbutton_work(struct work_struct *work);
int shpc_init(struct controller *ctrl, struct pci_dev *pdev);

static inline const char *slot_name(struct slot *slot)
{
	return hotplug_slot_name(slot->hotplug_slot);
}

#ifdef CONFIG_ACPI
#include <linux/pci-acpi.h>
static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
{
	u32 flags = OSC_PCI_SHPC_NATIVE_HP_CONTROL;
	return acpi_get_hp_hw_control_from_firmware(dev, flags);
}
#else
#define get_hp_hw_control_from_firmware(dev) (0)
#endif

struct ctrl_reg {
	volatile u32 base_offset;
	volatile u32 slot_avail1;
	volatile u32 slot_avail2;
	volatile u32 slot_config;
	volatile u16 sec_bus_config;
	volatile u8  msi_ctrl;
	volatile u8  prog_interface;
	volatile u16 cmd;
	volatile u16 cmd_status;
	volatile u32 intr_loc;
	volatile u32 serr_loc;
	volatile u32 serr_intr_enable;
	volatile u32 slot1;
} __attribute__ ((packed));

/* offsets to the controller registers based on the above structure layout */
enum ctrl_offsets {
	BASE_OFFSET	 = offsetof(struct ctrl_reg, base_offset),
	SLOT_AVAIL1	 = offsetof(struct ctrl_reg, slot_avail1),
	SLOT_AVAIL2	 = offsetof(struct ctrl_reg, slot_avail2),
	SLOT_CONFIG	 = offsetof(struct ctrl_reg, slot_config),
	SEC_BUS_CONFIG	 = offsetof(struct ctrl_reg, sec_bus_config),
	MSI_CTRL	 = offsetof(struct ctrl_reg, msi_ctrl),
	PROG_INTERFACE	 = offsetof(struct ctrl_reg, prog_interface),
	CMD		 = offsetof(struct ctrl_reg, cmd),
	CMD_STATUS	 = offsetof(struct ctrl_reg, cmd_status),
	INTR_LOC	 = offsetof(struct ctrl_reg, intr_loc),
	SERR_LOC	 = offsetof(struct ctrl_reg, serr_loc),
	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
	SLOT1		 = offsetof(struct ctrl_reg, slot1),
};

static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
{
	return hotplug_slot->private;
}

static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
{
	struct slot *slot;

	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
		if (slot->device == device)
			return slot;
	}

	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
	return NULL;
}

static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
{
	u32 pcix_misc2_temp;

	/* save MiscII register */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);

	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;

	/* clear SERR/PERR enable bits */
	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
}

static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
{
	u32 pcix_misc2_temp;
	u32 pcix_bridge_errors_reg;
	u32 pcix_mem_base_reg;
	u8  perr_set;
	u8  rse_set;

	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
	if (perr_set) {
		ctrl_dbg(p_slot->ctrl,
			 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
			 perr_set);

		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
	}

	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
	rse_set = pcix_mem_base_reg & RSE_MASK;
	if (rse_set) {
		ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");

		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
	}
	/* restore MiscII register */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);

	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
		pcix_misc2_temp |= SERRFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~SERRFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
		pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
		pcix_misc2_temp |= PERRFLOODENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
		pcix_misc2_temp |= PERRFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
		pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
}

struct hpc_ops {
	int (*power_on_slot)(struct slot *slot);
	int (*slot_enable)(struct slot *slot);
	int (*slot_disable)(struct slot *slot);
	int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
	int (*get_power_status)(struct slot *slot, u8 *status);
	int (*get_attention_status)(struct slot *slot, u8 *status);
	int (*set_attention_status)(struct slot *slot, u8 status);
	int (*get_latch_status)(struct slot *slot, u8 *status);
	int (*get_adapter_status)(struct slot *slot, u8 *status);
	int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
	int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
	int (*get_prog_int)(struct slot *slot, u8 *prog_int);
	int (*query_power_fault)(struct slot *slot);
	void (*green_led_on)(struct slot *slot);
	void (*green_led_off)(struct slot *slot);
	void (*green_led_blink)(struct slot *slot);
	void (*release_ctlr)(struct controller *ctrl);
	int (*check_cmd_status)(struct controller *ctrl);
};

#endif				/* _SHPCHP_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Standard Hot Plug Controller Driver
	3	*
	4	* Copyright (C) 1995,2001 Compaq Computer Corporation
	5	* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
	6	* Copyright (C) 2001 IBM
	7	* Copyright (C) 2003-2004 Intel Corporation
	8	*
	9	* All rights reserved.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or (at
	14	* your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but
	17	* WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	19	* NON INFRINGEMENT. See the GNU General Public License for more
	20	* details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
8cf4c195	26	* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4 LT	27	*
	28	*/
	29	#ifndef _SHPCHP_H
	30	#define _SHPCHP_H
	31
	32	#include <linux/types.h>
	33	#include <linux/pci.h>
7a54f25c	34	#include <linux/pci_hotplug.h>
1da177e4	35	#include <linux/delay.h>
4e57b681	36	#include <linux/sched.h> /* signal_pending(), struct timer_list */
6aa4cdd0	37	#include <linux/mutex.h>
e24dcbef	38	#include <linux/workqueue.h>
4e57b681	39
1da177e4 LT	40	#if !defined(MODULE)
	41	#define MY_NAME "shpchp"
	42	#else
	43	#define MY_NAME THIS_MODULE->name
	44	#endif
	45
90ab5ee9	46	extern bool shpchp_poll_mode;
1da177e4	47	extern int shpchp_poll_time;
90ab5ee9	48	extern bool shpchp_debug;
1da177e4	49
8352e04e	50	#define dbg(format, arg...) \
1c35b8e5 FS	51	do { \
1c35b8e5 FS	52	if (shpchp_debug) \
ff3ce480	53	printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
1c35b8e5	54	} while (0)
8352e04e	55	#define err(format, arg...) \
ff3ce480	56	printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
8352e04e	57	#define info(format, arg...) \
ff3ce480	58	printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
8352e04e	59	#define warn(format, arg...) \
ff3ce480	60	printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
1da177e4	61
f98ca311 TI	62	#define ctrl_dbg(ctrl, format, arg...) \
	63	do { \
	64	if (shpchp_debug) \
1c35b8e5	65	dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev, \
f98ca311 TI	66	format, ## arg); \
	67	} while (0)
	68	#define ctrl_err(ctrl, format, arg...) \
	69	dev_err(&ctrl->pci_dev->dev, format, ## arg)
	70	#define ctrl_info(ctrl, format, arg...) \
	71	dev_info(&ctrl->pci_dev->dev, format, ## arg)
	72	#define ctrl_warn(ctrl, format, arg...) \
	73	dev_warn(&ctrl->pci_dev->dev, format, ## arg)
	74
	75
bbe779db	76	#define SLOT_NAME_SIZE 10
1da177e4	77	struct slot {
1da177e4 LT	78	u8 bus;
1da177e4 LT	79	u8 device;
2178bfad	80	u16 status;
1da177e4 LT	81	u32 number;
1da177e4 LT	82	u8 is_a_board;
1da177e4	83	u8 state;
1da177e4	84	u8 presence_save;
2178bfad	85	u8 pwr_save;
1da177e4	86	struct controller *ctrl;
bd790082	87	const struct hpc_ops *hpc_ops;
1da177e4 LT	88	struct hotplug_slot *hotplug_slot;
1da177e4 LT	89	struct list_head slot_list;
c4028958	90	struct delayed_work work; /* work for button event */
a246fa4e	91	struct mutex lock;
f652e7d2	92	struct workqueue_struct *wq;
66f17055	93	u8 hp_slot;
1da177e4 LT	94	};
1da177e4 LT	95
1da177e4 LT	96	struct event_info {
1da177e4 LT	97	u32 event_type;
f7391f53 KK	98	struct slot *p_slot;
f7391f53 KK	99	struct work_struct work;
1da177e4 LT	100	};
	101
	102	struct controller {
6aa4cdd0	103	struct mutex crit_sect; /* critical section mutex */
d29aadda	104	struct mutex cmd_lock; /* command lock */
1da177e4 LT	105	int num_slots; /* Number of slots on ctlr */
1da177e4 LT	106	int slot_num_inc; /* 1 or -1 */
1da177e4	107	struct pci_dev *pci_dev;
5b1a960d	108	struct list_head slot_list;
bd790082	109	const struct hpc_ops *hpc_ops;
1da177e4	110	wait_queue_head_t queue; /* sleep & wake process */
1da177e4	111	u8 slot_device_offset;
53044f35	112	u32 pcix_misc2_reg; /* for amd pogo errata */
1da177e4	113	u32 first_slot; /* First physical slot number */
0455986c KK	114	u32 cap_offset;
	115	unsigned long mmio_base;
	116	unsigned long mmio_size;
0abe68ce KK	117	void __iomem *creg;
0abe68ce KK	118	struct timer_list poll_timer;
1da177e4 LT	119	};
1da177e4 LT	120
1da177e4	121	/* Define AMD SHPC ID */
9f593e30	122	#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
53044f35 KD	123	#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
53044f35 KD	124
45e829ea	125	/* AMD PCI-X bridge registers */
53044f35 KD	126	#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
	127	#define PCIX_MISCII_OFFSET 0x48
	128	#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
	129
	130	/* AMD PCIX_MISCII masks and offsets */
	131	#define PERRNONFATALENABLE_MASK 0x00040000
	132	#define PERRFATALENABLE_MASK 0x00080000
	133	#define PERRFLOODENABLE_MASK 0x00100000
	134	#define SERRNONFATALENABLE_MASK 0x00200000
	135	#define SERRFATALENABLE_MASK 0x00400000
	136
	137	/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
	138	#define PERR_OBSERVED_MASK 0x00000001
	139
	140	/* AMD PCIX_MEM_BASE_LIMIT masks */
	141	#define RSE_MASK 0x40000000
1da177e4 LT	142
	143	#define INT_BUTTON_IGNORE 0
	144	#define INT_PRESENCE_ON 1
	145	#define INT_PRESENCE_OFF 2
	146	#define INT_SWITCH_CLOSE 3
	147	#define INT_SWITCH_OPEN 4
	148	#define INT_POWER_FAULT 5
	149	#define INT_POWER_FAULT_CLEAR 6
	150	#define INT_BUTTON_PRESS 7
	151	#define INT_BUTTON_RELEASE 8
	152	#define INT_BUTTON_CANCEL 9
	153
	154	#define STATIC_STATE 0
	155	#define BLINKINGON_STATE 1
	156	#define BLINKINGOFF_STATE 2
	157	#define POWERON_STATE 3
	158	#define POWEROFF_STATE 4
	159
1da177e4 LT	160	/* Error messages */
	161	#define INTERLOCK_OPEN 0x00000002
	162	#define ADD_NOT_SUPPORTED 0x00000003
	163	#define CARD_FUNCTIONING 0x00000005
	164	#define ADAPTER_NOT_SAME 0x00000006
	165	#define NO_ADAPTER_PRESENT 0x00000009
	166	#define NOT_ENOUGH_RESOURCES 0x0000000B
	167	#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
	168	#define WRONG_BUS_FREQUENCY 0x0000000D
	169	#define POWER_FAILURE 0x0000000E
	170
f39d5b72 BH	171	int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
	172	void shpchp_remove_ctrl_files(struct controller *ctrl);
	173	int shpchp_sysfs_enable_slot(struct slot *slot);
	174	int shpchp_sysfs_disable_slot(struct slot *slot);
	175	u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
	176	u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
	177	u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
	178	u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
	179	int shpchp_configure_device(struct slot *p_slot);
	180	int shpchp_unconfigure_device(struct slot *p_slot);
	181	void cleanup_slots(struct controller *ctrl);
	182	void shpchp_queue_pushbutton_work(struct work_struct *work);
3c78bc61	183	int shpc_init(struct controller ctrl, struct pci_dev pdev);
783c49fc	184
66f17055 AC	185	static inline const char slot_name(struct slot slot)
	186	{
	187	return hotplug_slot_name(slot->hotplug_slot);
	188	}
	189
783c49fc	190	#ifdef CONFIG_ACPI
ac9c052d	191	#include <linux/pci-acpi.h>
ac9c052d KK	192	static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
ac9c052d KK	193	{
7dab9ef4	194	u32 flags = OSC_PCI_SHPC_NATIVE_HP_CONTROL;
ac9c052d KK	195	return acpi_get_hp_hw_control_from_firmware(dev, flags);
ac9c052d KK	196	}
783c49fc	197	#else
ac9c052d	198	#define get_hp_hw_control_from_firmware(dev) (0)
783c49fc KA	199	#endif
783c49fc KA	200
1da177e4 LT	201	struct ctrl_reg {
	202	volatile u32 base_offset;
	203	volatile u32 slot_avail1;
	204	volatile u32 slot_avail2;
	205	volatile u32 slot_config;
	206	volatile u16 sec_bus_config;
	207	volatile u8 msi_ctrl;
	208	volatile u8 prog_interface;
	209	volatile u16 cmd;
	210	volatile u16 cmd_status;
	211	volatile u32 intr_loc;
	212	volatile u32 serr_loc;
	213	volatile u32 serr_intr_enable;
	214	volatile u32 slot1;
1da177e4 LT	215	} __attribute__ ((packed));
	216
	217	/* offsets to the controller registers based on the above structure layout */
	218	enum ctrl_offsets {
f7625980 BH	219	BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
f7625980 BH	220	SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
8352e04e	221	SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
f7625980	222	SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
8352e04e KK	223	SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
8352e04e KK	224	MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
f7625980	225	PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
8352e04e KK	226	CMD = offsetof(struct ctrl_reg, cmd),
	227	CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
	228	INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
	229	SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
	230	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
	231	SLOT1 = offsetof(struct ctrl_reg, slot1),
1da177e4	232	};
1da177e4	233
8352e04e	234	static inline struct slot get_slot(struct hotplug_slot hotplug_slot)
9f593e30	235	{
8352e04e	236	return hotplug_slot->private;
1da177e4 LT	237	}
1da177e4 LT	238
8352e04e	239	static inline struct slot shpchp_find_slot(struct controller ctrl, u8 device)
1da177e4	240	{
5b1a960d	241	struct slot *slot;
1da177e4	242
5b1a960d KK	243	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
	244	if (slot->device == device)
	245	return slot;
1da177e4 LT	246	}
1da177e4 LT	247
be7bce25	248	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
5b1a960d	249	return NULL;
1da177e4 LT	250	}
1da177e4 LT	251
53044f35 KD	252	static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
	253	{
	254	u32 pcix_misc2_temp;
	255
	256	/* save MiscII register */
	257	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
	258
	259	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
	260
	261	/* clear SERR/PERR enable bits */
	262	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	263	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	264	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	265	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	266	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	267	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
	268	}
	269
	270	static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
	271	{
	272	u32 pcix_misc2_temp;
	273	u32 pcix_bridge_errors_reg;
	274	u32 pcix_mem_base_reg;
	275	u8 perr_set;
	276	u8 rse_set;
	277
	278	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
	279	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
	280	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
	281	if (perr_set) {
f98ca311	282	ctrl_dbg(p_slot->ctrl,
be7bce25 TI	283	"Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
be7bce25 TI	284	perr_set);
53044f35 KD	285
	286	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
	287	}
	288
	289	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
	290	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
	291	rse_set = pcix_mem_base_reg & RSE_MASK;
	292	if (rse_set) {
be7bce25	293	ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
53044f35 KD	294
	295	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
	296	}
	297	/* restore MiscII register */
ff3ce480	298	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
53044f35 KD	299
	300	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
	301	pcix_misc2_temp \|= SERRFATALENABLE_MASK;
	302	else
	303	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	304
	305	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
	306	pcix_misc2_temp \|= SERRNONFATALENABLE_MASK;
	307	else
	308	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	309
	310	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
	311	pcix_misc2_temp \|= PERRFLOODENABLE_MASK;
	312	else
	313	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	314
	315	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
	316	pcix_misc2_temp \|= PERRFATALENABLE_MASK;
	317	else
	318	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	319
	320	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
	321	pcix_misc2_temp \|= PERRNONFATALENABLE_MASK;
	322	else
	323	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	324	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
	325	}
	326
1da177e4	327	struct hpc_ops {
8352e04e KK	328	int (power_on_slot)(struct slot slot);
	329	int (slot_enable)(struct slot slot);
	330	int (slot_disable)(struct slot slot);
	331	int (set_bus_speed_mode)(struct slot slot, enum pci_bus_speed speed);
	332	int (get_power_status)(struct slot slot, u8 *status);
	333	int (get_attention_status)(struct slot slot, u8 *status);
	334	int (set_attention_status)(struct slot slot, u8 status);
	335	int (get_latch_status)(struct slot slot, u8 *status);
	336	int (get_adapter_status)(struct slot slot, u8 *status);
8352e04e KK	337	int (get_adapter_speed)(struct slot slot, enum pci_bus_speed *speed);
	338	int (get_mode1_ECC_cap)(struct slot slot, u8 *mode);
	339	int (get_prog_int)(struct slot slot, u8 *prog_int);
	340	int (query_power_fault)(struct slot slot);
	341	void (green_led_on)(struct slot slot);
	342	void (green_led_off)(struct slot slot);
	343	void (green_led_blink)(struct slot slot);
	344	void (release_ctlr)(struct controller ctrl);
	345	int (check_cmd_status)(struct controller ctrl);
1da177e4 LT	346	};
	347
	348	#endif /* _SHPCHP_H */