[mirror_ubuntu-zesty-kernel.git] / drivers / pci / hotplug / shpchp.h

/*
 * Standard Hot Plug Controller Driver
 *
 * Copyright (C) 1995,2001 Compaq Computer Corporation
 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
 * Copyright (C) 2001 IBM
 * Copyright (C) 2003-2004 Intel Corporation
 *
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
 *
 */
#ifndef _SHPCHP_H
#define _SHPCHP_H

#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/sched.h>	/* signal_pending(), struct timer_list */
#include <linux/mutex.h>

#include "pci_hotplug.h"

#if !defined(MODULE)
	#define MY_NAME	"shpchp"
#else
	#define MY_NAME	THIS_MODULE->name
#endif

extern int shpchp_poll_mode;
extern int shpchp_poll_time;
extern int shpchp_debug;
extern struct workqueue_struct *shpchp_wq;

/*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
#define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)

#define SLOT_NAME_SIZE 10
struct slot {
	u8 bus;
	u8 device;
	u16 status;
	u32 number;
	u8 is_a_board;
	u8 state;
	u8 presence_save;
	u8 pwr_save;
	struct timer_list task_event;
	u8 hp_slot;
	struct controller *ctrl;
	struct hpc_ops *hpc_ops;
	struct hotplug_slot *hotplug_slot;
	struct list_head	slot_list;
	char name[SLOT_NAME_SIZE];
	struct work_struct work;	/* work for button event */
	struct mutex lock;
};

struct event_info {
	u32 event_type;
	struct slot *p_slot;
	struct work_struct work;
};

struct controller {
	struct mutex crit_sect;		/* critical section mutex */
	struct mutex cmd_lock;		/* command lock */
	struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
	int num_slots;			/* Number of slots on ctlr */
	int slot_num_inc;		/* 1 or -1 */
	struct pci_dev *pci_dev;
	struct list_head slot_list;
	struct hpc_ops *hpc_ops;
	wait_queue_head_t queue;	/* sleep & wake process */
	u8 bus;
	u8 device;
	u8 function;
	u8 slot_device_offset;
	u8 add_support;
	u32 pcix_misc2_reg;	/* for amd pogo errata */
	enum pci_bus_speed speed;
	u32 first_slot;		/* First physical slot number */
	u8 slot_bus;		/* Bus where the slots handled by this controller sit */
	u32 cap_offset;
	unsigned long mmio_base;
	unsigned long mmio_size;
};


/* Define AMD SHPC ID  */
#define PCI_DEVICE_ID_AMD_GOLAM_7450	0x7450 
#define PCI_DEVICE_ID_AMD_POGO_7458	0x7458

/* AMD PCIX bridge registers */

#define PCIX_MEM_BASE_LIMIT_OFFSET	0x1C
#define PCIX_MISCII_OFFSET		0x48
#define PCIX_MISC_BRIDGE_ERRORS_OFFSET	0x80

/* AMD PCIX_MISCII masks and offsets */
#define PERRNONFATALENABLE_MASK		0x00040000
#define PERRFATALENABLE_MASK		0x00080000
#define PERRFLOODENABLE_MASK		0x00100000
#define SERRNONFATALENABLE_MASK		0x00200000
#define SERRFATALENABLE_MASK		0x00400000

/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
#define PERR_OBSERVED_MASK		0x00000001

/* AMD PCIX_MEM_BASE_LIMIT masks */
#define RSE_MASK			0x40000000

#define INT_BUTTON_IGNORE		0
#define INT_PRESENCE_ON			1
#define INT_PRESENCE_OFF		2
#define INT_SWITCH_CLOSE		3
#define INT_SWITCH_OPEN			4
#define INT_POWER_FAULT			5
#define INT_POWER_FAULT_CLEAR		6
#define INT_BUTTON_PRESS		7
#define INT_BUTTON_RELEASE		8
#define INT_BUTTON_CANCEL		9

#define STATIC_STATE			0
#define BLINKINGON_STATE		1
#define BLINKINGOFF_STATE		2
#define POWERON_STATE			3
#define POWEROFF_STATE			4

#define PCI_TO_PCI_BRIDGE_CLASS		0x00060400

/* Error messages */
#define INTERLOCK_OPEN			0x00000002
#define ADD_NOT_SUPPORTED		0x00000003
#define CARD_FUNCTIONING		0x00000005
#define ADAPTER_NOT_SAME		0x00000006
#define NO_ADAPTER_PRESENT		0x00000009
#define NOT_ENOUGH_RESOURCES		0x0000000B
#define DEVICE_TYPE_NOT_SUPPORTED	0x0000000C
#define WRONG_BUS_FREQUENCY		0x0000000D
#define POWER_FAILURE			0x0000000E

#define REMOVE_NOT_SUPPORTED		0x00000003

#define DISABLE_CARD			1

/*
 * error Messages
 */
#define msg_initialization_err	"Initialization failure, error=%d\n"
#define msg_button_on		"PCI slot #%s - powering on due to button press.\n"
#define msg_button_off		"PCI slot #%s - powering off due to button press.\n"
#define msg_button_cancel	"PCI slot #%s - action canceled due to button press.\n"

/* sysfs functions for the hotplug controller info */
extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);

extern int	shpchp_sysfs_enable_slot(struct slot *slot);
extern int	shpchp_sysfs_disable_slot(struct slot *slot);

extern u8	shpchp_handle_attention_button(u8 hp_slot, void *inst_id);
extern u8	shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
extern u8	shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
extern u8	shpchp_handle_power_fault(u8 hp_slot, void *inst_id);

/* pci functions */
extern int	shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
extern int	shpchp_configure_device(struct slot *p_slot);
extern int	shpchp_unconfigure_device(struct slot *p_slot);
extern void	shpchp_remove_ctrl_files(struct controller *ctrl);
extern void	cleanup_slots(struct controller *ctrl);
extern void	queue_pushbutton_work(void *data);


#ifdef CONFIG_ACPI
static inline int get_hp_params_from_firmware(struct pci_dev *dev,
			struct hotplug_params *hpp)
{
	if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp)))
			return -ENODEV;
	return 0;
}
#define get_hp_hw_control_from_firmware(pdev) \
	do { \
		if (DEVICE_ACPI_HANDLE(&(pdev->dev))) \
			acpi_run_oshp(DEVICE_ACPI_HANDLE(&(pdev->dev))); \
	} while (0)
#else
#define get_hp_params_from_firmware(dev, hpp) (-ENODEV)
#define get_hp_hw_control_from_firmware(dev) do { } while (0)
#endif

struct ctrl_reg {
	volatile u32 base_offset;
	volatile u32 slot_avail1;
	volatile u32 slot_avail2;
	volatile u32 slot_config;
	volatile u16 sec_bus_config;
	volatile u8  msi_ctrl;
	volatile u8  prog_interface;
	volatile u16 cmd;
	volatile u16 cmd_status;
	volatile u32 intr_loc;
	volatile u32 serr_loc;
	volatile u32 serr_intr_enable;
	volatile u32 slot1;
	volatile u32 slot2;
	volatile u32 slot3;
	volatile u32 slot4;
	volatile u32 slot5;
	volatile u32 slot6;
	volatile u32 slot7;
	volatile u32 slot8;
	volatile u32 slot9;
	volatile u32 slot10;
	volatile u32 slot11;
	volatile u32 slot12;
} __attribute__ ((packed));

/* offsets to the controller registers based on the above structure layout */
enum ctrl_offsets {
	BASE_OFFSET =	offsetof(struct ctrl_reg, base_offset),
	SLOT_AVAIL1 =	offsetof(struct ctrl_reg, slot_avail1),
	SLOT_AVAIL2	=	offsetof(struct ctrl_reg, slot_avail2),
	SLOT_CONFIG =	offsetof(struct ctrl_reg, slot_config),
	SEC_BUS_CONFIG =	offsetof(struct ctrl_reg, sec_bus_config),
	MSI_CTRL	=	offsetof(struct ctrl_reg, msi_ctrl),
	PROG_INTERFACE =	offsetof(struct ctrl_reg, prog_interface),
	CMD		=	offsetof(struct ctrl_reg, cmd),
	CMD_STATUS	=	offsetof(struct ctrl_reg, cmd_status),
	INTR_LOC	= 	offsetof(struct ctrl_reg, intr_loc),
	SERR_LOC	= 	offsetof(struct ctrl_reg, serr_loc),
	SERR_INTR_ENABLE =	offsetof(struct ctrl_reg, serr_intr_enable),
	SLOT1 =		offsetof(struct ctrl_reg, slot1),
	SLOT2 =		offsetof(struct ctrl_reg, slot2),
	SLOT3 =		offsetof(struct ctrl_reg, slot3),
	SLOT4 =		offsetof(struct ctrl_reg, slot4),
	SLOT5 =		offsetof(struct ctrl_reg, slot5),
	SLOT6 =		offsetof(struct ctrl_reg, slot6),		
	SLOT7 =		offsetof(struct ctrl_reg, slot7),
	SLOT8 =		offsetof(struct ctrl_reg, slot8),
	SLOT9 =		offsetof(struct ctrl_reg, slot9),
	SLOT10 =	offsetof(struct ctrl_reg, slot10),
	SLOT11 =	offsetof(struct ctrl_reg, slot11),
	SLOT12 =	offsetof(struct ctrl_reg, slot12),
};
typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
struct php_ctlr_state_s {
	struct php_ctlr_state_s *pnext;
	struct pci_dev *pci_dev;
	unsigned int irq;
	unsigned long flags;	/* spinlock's */
	u32 slot_device_offset;
	u32 num_slots;
    	struct timer_list	int_poll_timer;	/* Added for poll event */
	php_intr_callback_t attention_button_callback;
	php_intr_callback_t switch_change_callback;
	php_intr_callback_t presence_change_callback;
	php_intr_callback_t power_fault_callback;
	void *callback_instance_id;
	void __iomem *creg;			/* Ptr to controller register space */
};
/* Inline functions */


/* Inline functions to check the sanity of a pointer that is passed to us */
static inline int slot_paranoia_check (struct slot *slot, const char *function)
{
	if (!slot) {
		dbg("%s - slot == NULL", function);
		return -1;
	}
	if (!slot->hotplug_slot) {
		dbg("%s - slot->hotplug_slot == NULL!", function);
		return -1;
	}
	return 0;
}

static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function)
{ 
	struct slot *slot;

	if (!hotplug_slot) {
		dbg("%s - hotplug_slot == NULL\n", function);
		return NULL;
	}

	slot = (struct slot *)hotplug_slot->private;
	if (slot_paranoia_check (slot, function))
                return NULL;
	return slot;
}

static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
{
	struct slot *slot;

	if (!ctrl)
		return NULL;

	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
		if (slot->device == device)
			return slot;
	}

	err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);

	return NULL;
}

static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
{
	u32 pcix_misc2_temp;

	/* save MiscII register */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);

	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;

	/* clear SERR/PERR enable bits */
	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
}

static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
{
	u32 pcix_misc2_temp;
	u32 pcix_bridge_errors_reg;
	u32 pcix_mem_base_reg;
	u8  perr_set;
	u8  rse_set;

	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
	if (perr_set) {
		dbg ("%s  W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);

		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
	}

	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
	rse_set = pcix_mem_base_reg & RSE_MASK;
	if (rse_set) {
		dbg ("%s  W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );

		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
	}
	/* restore MiscII register */
	pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );

	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
		pcix_misc2_temp |= SERRFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~SERRFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
		pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
		pcix_misc2_temp |= PERRFLOODENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
		pcix_misc2_temp |= PERRFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRFATALENABLE_MASK;

	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
		pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
	else
		pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
}

enum php_ctlr_type {
	PCI,
	ISA,
	ACPI
};

int shpc_init( struct controller *ctrl, struct pci_dev *pdev);

int shpc_get_ctlr_slot_config( struct controller *ctrl,
		int *num_ctlr_slots,
		int *first_device_num,
		int *physical_slot_num,
		int *updown,
		int *flags);

struct hpc_ops {
	int	(*power_on_slot )		(struct slot *slot);
	int	(*slot_enable )			(struct slot *slot);
	int	(*slot_disable )		(struct slot *slot);
	int	(*set_bus_speed_mode)	(struct slot *slot, enum pci_bus_speed speed);
	int	(*get_power_status)		(struct slot *slot, u8 *status);
	int	(*get_attention_status)	(struct slot *slot, u8 *status);
	int	(*set_attention_status)	(struct slot *slot, u8 status);
	int	(*get_latch_status)		(struct slot *slot, u8 *status);
	int	(*get_adapter_status)	(struct slot *slot, u8 *status);

	int	(*get_max_bus_speed)	(struct slot *slot, enum pci_bus_speed *speed);
	int	(*get_cur_bus_speed)	(struct slot *slot, enum pci_bus_speed *speed);
	int	(*get_adapter_speed)	(struct slot *slot, enum pci_bus_speed *speed);
	int	(*get_mode1_ECC_cap)	(struct slot *slot, u8 *mode);
	int	(*get_prog_int)			(struct slot *slot, u8 *prog_int);

	int	(*query_power_fault)	(struct slot *slot);
	void	(*green_led_on)		(struct slot *slot);
	void	(*green_led_off)	(struct slot *slot);
	void	(*green_led_blink)	(struct slot *slot);
	void	(*release_ctlr)		(struct controller *ctrl);
	int (*check_cmd_status)		(struct controller *ctrl);
};

#endif				/* _SHPCHP_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Standard Hot Plug Controller Driver
	3	*
	4	* Copyright (C) 1995,2001 Compaq Computer Corporation
	5	* Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
	6	* Copyright (C) 2001 IBM
	7	* Copyright (C) 2003-2004 Intel Corporation
	8	*
	9	* All rights reserved.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or (at
	14	* your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful, but
	17	* WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	19	* NON INFRINGEMENT. See the GNU General Public License for more
	20	* details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
8cf4c195	26	* Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4 LT	27	*
	28	*/
	29	#ifndef _SHPCHP_H
	30	#define _SHPCHP_H
	31
	32	#include <linux/types.h>
	33	#include <linux/pci.h>
	34	#include <linux/delay.h>
4e57b681	35	#include <linux/sched.h> /* signal_pending(), struct timer_list */
6aa4cdd0	36	#include <linux/mutex.h>
4e57b681	37
1da177e4 LT	38	#include "pci_hotplug.h"
	39
	40	#if !defined(MODULE)
	41	#define MY_NAME "shpchp"
	42	#else
	43	#define MY_NAME THIS_MODULE->name
	44	#endif
	45
	46	extern int shpchp_poll_mode;
	47	extern int shpchp_poll_time;
	48	extern int shpchp_debug;
f7391f53	49	extern struct workqueue_struct *shpchp_wq;
1da177e4 LT	50
	51	/#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)/
	52	#define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
	53	#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
	54	#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
	55	#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
	56
bbe779db	57	#define SLOT_NAME_SIZE 10
1da177e4	58	struct slot {
1da177e4 LT	59	u8 bus;
1da177e4 LT	60	u8 device;
2178bfad	61	u16 status;
1da177e4 LT	62	u32 number;
1da177e4 LT	63	u8 is_a_board;
1da177e4	64	u8 state;
1da177e4	65	u8 presence_save;
2178bfad	66	u8 pwr_save;
1da177e4 LT	67	struct timer_list task_event;
	68	u8 hp_slot;
	69	struct controller *ctrl;
	70	struct hpc_ops *hpc_ops;
	71	struct hotplug_slot *hotplug_slot;
	72	struct list_head slot_list;
bbe779db	73	char name[SLOT_NAME_SIZE];
f7391f53	74	struct work_struct work; /* work for button event */
a246fa4e	75	struct mutex lock;
1da177e4 LT	76	};
1da177e4 LT	77
1da177e4 LT	78	struct event_info {
1da177e4 LT	79	u32 event_type;
f7391f53 KK	80	struct slot *p_slot;
f7391f53 KK	81	struct work_struct work;
1da177e4 LT	82	};
	83
	84	struct controller {
6aa4cdd0	85	struct mutex crit_sect; /* critical section mutex */
d29aadda	86	struct mutex cmd_lock; /* command lock */
ee138334	87	struct php_ctlr_state_s hpc_ctlr_handle; / HPC controller handle */
1da177e4 LT	88	int num_slots; /* Number of slots on ctlr */
1da177e4 LT	89	int slot_num_inc; /* 1 or -1 */
1da177e4	90	struct pci_dev *pci_dev;
5b1a960d	91	struct list_head slot_list;
1da177e4 LT	92	struct hpc_ops *hpc_ops;
1da177e4 LT	93	wait_queue_head_t queue; /* sleep & wake process */
1da177e4 LT	94	u8 bus;
	95	u8 device;
	96	u8 function;
1da177e4 LT	97	u8 slot_device_offset;
1da177e4 LT	98	u8 add_support;
53044f35	99	u32 pcix_misc2_reg; /* for amd pogo errata */
1da177e4 LT	100	enum pci_bus_speed speed;
	101	u32 first_slot; /* First physical slot number */
	102	u8 slot_bus; /* Bus where the slots handled by this controller sit */
0455986c KK	103	u32 cap_offset;
	104	unsigned long mmio_base;
	105	unsigned long mmio_size;
1da177e4 LT	106	};
1da177e4 LT	107
424600f9	108
1da177e4 LT	109	/* Define AMD SHPC ID */
1da177e4 LT	110	#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
53044f35 KD	111	#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
	112
	113	/* AMD PCIX bridge registers */
	114
	115	#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
	116	#define PCIX_MISCII_OFFSET 0x48
	117	#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
	118
	119	/* AMD PCIX_MISCII masks and offsets */
	120	#define PERRNONFATALENABLE_MASK 0x00040000
	121	#define PERRFATALENABLE_MASK 0x00080000
	122	#define PERRFLOODENABLE_MASK 0x00100000
	123	#define SERRNONFATALENABLE_MASK 0x00200000
	124	#define SERRFATALENABLE_MASK 0x00400000
	125
	126	/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
	127	#define PERR_OBSERVED_MASK 0x00000001
	128
	129	/* AMD PCIX_MEM_BASE_LIMIT masks */
	130	#define RSE_MASK 0x40000000
1da177e4 LT	131
	132	#define INT_BUTTON_IGNORE 0
	133	#define INT_PRESENCE_ON 1
	134	#define INT_PRESENCE_OFF 2
	135	#define INT_SWITCH_CLOSE 3
	136	#define INT_SWITCH_OPEN 4
	137	#define INT_POWER_FAULT 5
	138	#define INT_POWER_FAULT_CLEAR 6
	139	#define INT_BUTTON_PRESS 7
	140	#define INT_BUTTON_RELEASE 8
	141	#define INT_BUTTON_CANCEL 9
	142
	143	#define STATIC_STATE 0
	144	#define BLINKINGON_STATE 1
	145	#define BLINKINGOFF_STATE 2
	146	#define POWERON_STATE 3
	147	#define POWEROFF_STATE 4
	148
	149	#define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
	150
	151	/* Error messages */
	152	#define INTERLOCK_OPEN 0x00000002
	153	#define ADD_NOT_SUPPORTED 0x00000003
	154	#define CARD_FUNCTIONING 0x00000005
	155	#define ADAPTER_NOT_SAME 0x00000006
	156	#define NO_ADAPTER_PRESENT 0x00000009
	157	#define NOT_ENOUGH_RESOURCES 0x0000000B
	158	#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
	159	#define WRONG_BUS_FREQUENCY 0x0000000D
	160	#define POWER_FAILURE 0x0000000E
	161
	162	#define REMOVE_NOT_SUPPORTED 0x00000003
	163
	164	#define DISABLE_CARD 1
	165
	166	/*
	167	* error Messages
	168	*/
	169	#define msg_initialization_err "Initialization failure, error=%d\n"
99ff124d KK	170	#define msg_button_on "PCI slot #%s - powering on due to button press.\n"
	171	#define msg_button_off "PCI slot #%s - powering off due to button press.\n"
	172	#define msg_button_cancel "PCI slot #%s - action canceled due to button press.\n"
1da177e4 LT	173
1da177e4 LT	174	/* sysfs functions for the hotplug controller info */
e1b95dc6	175	extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
1da177e4	176
a246fa4e KK	177	extern int shpchp_sysfs_enable_slot(struct slot *slot);
a246fa4e KK	178	extern int shpchp_sysfs_disable_slot(struct slot *slot);
1da177e4 LT	179
	180	extern u8 shpchp_handle_attention_button(u8 hp_slot, void *inst_id);
	181	extern u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
	182	extern u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
	183	extern u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id);
	184
1da177e4	185	/* pci functions */
1da177e4	186	extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
dbd7a788	187	extern int shpchp_configure_device(struct slot *p_slot);
2178bfad	188	extern int shpchp_unconfigure_device(struct slot *p_slot);
c2608a11	189	extern void shpchp_remove_ctrl_files(struct controller *ctrl);
f7391f53	190	extern void cleanup_slots(struct controller *ctrl);
a246fa4e	191	extern void queue_pushbutton_work(void *data);
1da177e4	192
783c49fc KA	193
	194	#ifdef CONFIG_ACPI
	195	static inline int get_hp_params_from_firmware(struct pci_dev *dev,
	196	struct hotplug_params *hpp)
	197	{
7430e34c	198	if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp)))
783c49fc KA	199	return -ENODEV;
	200	return 0;
	201	}
	202	#define get_hp_hw_control_from_firmware(pdev) \
	203	do { \
	204	if (DEVICE_ACPI_HANDLE(&(pdev->dev))) \
	205	acpi_run_oshp(DEVICE_ACPI_HANDLE(&(pdev->dev))); \
	206	} while (0)
	207	#else
	208	#define get_hp_params_from_firmware(dev, hpp) (-ENODEV)
	209	#define get_hp_hw_control_from_firmware(dev) do { } while (0)
	210	#endif
	211
1da177e4 LT	212	struct ctrl_reg {
	213	volatile u32 base_offset;
	214	volatile u32 slot_avail1;
	215	volatile u32 slot_avail2;
	216	volatile u32 slot_config;
	217	volatile u16 sec_bus_config;
	218	volatile u8 msi_ctrl;
	219	volatile u8 prog_interface;
	220	volatile u16 cmd;
	221	volatile u16 cmd_status;
	222	volatile u32 intr_loc;
	223	volatile u32 serr_loc;
	224	volatile u32 serr_intr_enable;
	225	volatile u32 slot1;
	226	volatile u32 slot2;
	227	volatile u32 slot3;
	228	volatile u32 slot4;
	229	volatile u32 slot5;
	230	volatile u32 slot6;
	231	volatile u32 slot7;
	232	volatile u32 slot8;
	233	volatile u32 slot9;
	234	volatile u32 slot10;
	235	volatile u32 slot11;
	236	volatile u32 slot12;
	237	} __attribute__ ((packed));
	238
	239	/* offsets to the controller registers based on the above structure layout */
	240	enum ctrl_offsets {
	241	BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
	242	SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
	243	SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
	244	SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
	245	SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
	246	MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
	247	PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
	248	CMD = offsetof(struct ctrl_reg, cmd),
	249	CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
	250	INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
	251	SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
	252	SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
	253	SLOT1 = offsetof(struct ctrl_reg, slot1),
	254	SLOT2 = offsetof(struct ctrl_reg, slot2),
	255	SLOT3 = offsetof(struct ctrl_reg, slot3),
	256	SLOT4 = offsetof(struct ctrl_reg, slot4),
	257	SLOT5 = offsetof(struct ctrl_reg, slot5),
	258	SLOT6 = offsetof(struct ctrl_reg, slot6),
	259	SLOT7 = offsetof(struct ctrl_reg, slot7),
	260	SLOT8 = offsetof(struct ctrl_reg, slot8),
	261	SLOT9 = offsetof(struct ctrl_reg, slot9),
	262	SLOT10 = offsetof(struct ctrl_reg, slot10),
	263	SLOT11 = offsetof(struct ctrl_reg, slot11),
	264	SLOT12 = offsetof(struct ctrl_reg, slot12),
	265	};
ee138334	266	typedef u8(php_intr_callback_t) (u8 hp_slot, void instance_id);
1da177e4 LT	267	struct php_ctlr_state_s {
	268	struct php_ctlr_state_s *pnext;
	269	struct pci_dev *pci_dev;
	270	unsigned int irq;
	271	unsigned long flags; /* spinlock's */
	272	u32 slot_device_offset;
	273	u32 num_slots;
	274	struct timer_list int_poll_timer; /* Added for poll event */
	275	php_intr_callback_t attention_button_callback;
	276	php_intr_callback_t switch_change_callback;
	277	php_intr_callback_t presence_change_callback;
	278	php_intr_callback_t power_fault_callback;
	279	void *callback_instance_id;
	280	void __iomem creg; / Ptr to controller register space */
	281	};
	282	/* Inline functions */
	283
	284
	285	/* Inline functions to check the sanity of a pointer that is passed to us */
	286	static inline int slot_paranoia_check (struct slot slot, const char function)
	287	{
	288	if (!slot) {
	289	dbg("%s - slot == NULL", function);
	290	return -1;
	291	}
1da177e4 LT	292	if (!slot->hotplug_slot) {
	293	dbg("%s - slot->hotplug_slot == NULL!", function);
	294	return -1;
	295	}
	296	return 0;
	297	}
	298
	299	static inline struct slot get_slot (struct hotplug_slot hotplug_slot, const char *function)
	300	{
	301	struct slot *slot;
	302
	303	if (!hotplug_slot) {
	304	dbg("%s - hotplug_slot == NULL\n", function);
	305	return NULL;
	306	}
	307
	308	slot = (struct slot *)hotplug_slot->private;
	309	if (slot_paranoia_check (slot, function))
	310	return NULL;
	311	return slot;
	312	}
	313
	314	static inline struct slot shpchp_find_slot (struct controller ctrl, u8 device)
	315	{
5b1a960d	316	struct slot *slot;
1da177e4 LT	317
	318	if (!ctrl)
	319	return NULL;
	320
5b1a960d KK	321	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
	322	if (slot->device == device)
	323	return slot;
1da177e4 LT	324	}
1da177e4 LT	325
5b1a960d KK	326	err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
	327
	328	return NULL;
1da177e4 LT	329	}
1da177e4 LT	330
53044f35 KD	331	static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
	332	{
	333	u32 pcix_misc2_temp;
	334
	335	/* save MiscII register */
	336	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
	337
	338	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
	339
	340	/* clear SERR/PERR enable bits */
	341	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	342	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	343	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	344	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
	345	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
	346	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
	347	}
	348
	349	static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
	350	{
	351	u32 pcix_misc2_temp;
	352	u32 pcix_bridge_errors_reg;
	353	u32 pcix_mem_base_reg;
	354	u8 perr_set;
	355	u8 rse_set;
	356
	357	/* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
	358	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
	359	perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
	360	if (perr_set) {
	361	dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
	362
	363	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
	364	}
	365
	366	/* write-one-to-clear Memory_Base_Limit[ RSE ] */
	367	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
	368	rse_set = pcix_mem_base_reg & RSE_MASK;
	369	if (rse_set) {
	370	dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
	371
	372	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
	373	}
	374	/* restore MiscII register */
	375	pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
	376
	377	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
	378	pcix_misc2_temp \|= SERRFATALENABLE_MASK;
	379	else
	380	pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
	381
	382	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
	383	pcix_misc2_temp \|= SERRNONFATALENABLE_MASK;
	384	else
	385	pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
	386
	387	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
	388	pcix_misc2_temp \|= PERRFLOODENABLE_MASK;
	389	else
	390	pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
	391
	392	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
	393	pcix_misc2_temp \|= PERRFATALENABLE_MASK;
	394	else
395	pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
396
397	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
398	pcix_misc2_temp \|= PERRNONFATALENABLE_MASK;
399	else
400	pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
401	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
402	}
403
1da177e4 LT	404	enum php_ctlr_type {
	405	PCI,
	406	ISA,
	407	ACPI
	408	};
	409
ee138334	410	int shpc_init( struct controller ctrl, struct pci_dev pdev);
1da177e4 LT	411
	412	int shpc_get_ctlr_slot_config( struct controller *ctrl,
	413	int *num_ctlr_slots,
	414	int *first_device_num,
	415	int *physical_slot_num,
	416	int *updown,
	417	int *flags);
	418
	419	struct hpc_ops {
	420	int (power_on_slot ) (struct slot slot);
	421	int (slot_enable ) (struct slot slot);
	422	int (slot_disable ) (struct slot slot);
1da177e4 LT	423	int (set_bus_speed_mode) (struct slot slot, enum pci_bus_speed speed);
	424	int (get_power_status) (struct slot slot, u8 *status);
	425	int (get_attention_status) (struct slot slot, u8 *status);
	426	int (set_attention_status) (struct slot slot, u8 status);
	427	int (get_latch_status) (struct slot slot, u8 *status);
	428	int (get_adapter_status) (struct slot slot, u8 *status);
	429
	430	int (get_max_bus_speed) (struct slot slot, enum pci_bus_speed *speed);
	431	int (get_cur_bus_speed) (struct slot slot, enum pci_bus_speed *speed);
	432	int (get_adapter_speed) (struct slot slot, enum pci_bus_speed *speed);
	433	int (get_mode1_ECC_cap) (struct slot slot, u8 *mode);
	434	int (get_prog_int) (struct slot slot, u8 *prog_int);
	435
	436	int (query_power_fault) (struct slot slot);
	437	void (green_led_on) (struct slot slot);
	438	void (green_led_off) (struct slot slot);
	439	void (green_led_blink) (struct slot slot);
	440	void (release_ctlr) (struct controller ctrl);
	441	int (check_cmd_status) (struct controller ctrl);
	442	};
	443
	444	#endif /* _SHPCHP_H */