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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Standard PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
d4d28dd4 AM |
34 | #include <linux/interrupt.h> |
35 | ||
1da177e4 LT |
36 | #include "shpchp.h" |
37 | ||
1da177e4 LT |
38 | /* Slot Available Register I field definition */ |
39 | #define SLOT_33MHZ 0x0000001f | |
40 | #define SLOT_66MHZ_PCIX 0x00001f00 | |
41 | #define SLOT_100MHZ_PCIX 0x001f0000 | |
42 | #define SLOT_133MHZ_PCIX 0x1f000000 | |
43 | ||
44 | /* Slot Available Register II field definition */ | |
45 | #define SLOT_66MHZ 0x0000001f | |
46 | #define SLOT_66MHZ_PCIX_266 0x00000f00 | |
47 | #define SLOT_100MHZ_PCIX_266 0x0000f000 | |
48 | #define SLOT_133MHZ_PCIX_266 0x000f0000 | |
49 | #define SLOT_66MHZ_PCIX_533 0x00f00000 | |
50 | #define SLOT_100MHZ_PCIX_533 0x0f000000 | |
51 | #define SLOT_133MHZ_PCIX_533 0xf0000000 | |
52 | ||
1da177e4 LT |
53 | /* Slot Configuration */ |
54 | #define SLOT_NUM 0x0000001F | |
55 | #define FIRST_DEV_NUM 0x00001F00 | |
56 | #define PSN 0x07FF0000 | |
57 | #define UPDOWN 0x20000000 | |
58 | #define MRLSENSOR 0x40000000 | |
59 | #define ATTN_BUTTON 0x80000000 | |
60 | ||
c4cecc19 KK |
61 | /* |
62 | * Interrupt Locator Register definitions | |
63 | */ | |
64 | #define CMD_INTR_PENDING (1 << 0) | |
65 | #define SLOT_INTR_PENDING(i) (1 << (i + 1)) | |
66 | ||
e7138723 KK |
67 | /* |
68 | * Controller SERR-INT Register | |
69 | */ | |
70 | #define GLOBAL_INTR_MASK (1 << 0) | |
71 | #define GLOBAL_SERR_MASK (1 << 1) | |
72 | #define COMMAND_INTR_MASK (1 << 2) | |
73 | #define ARBITER_SERR_MASK (1 << 3) | |
74 | #define COMMAND_DETECTED (1 << 16) | |
75 | #define ARBITER_DETECTED (1 << 17) | |
76 | #define SERR_INTR_RSVDZ_MASK 0xfffc0000 | |
77 | ||
2b34da7e KK |
78 | /* |
79 | * Logical Slot Register definitions | |
80 | */ | |
81 | #define SLOT_REG(i) (SLOT1 + (4 * i)) | |
82 | ||
5858759c KK |
83 | #define SLOT_STATE_SHIFT (0) |
84 | #define SLOT_STATE_MASK (3 << 0) | |
85 | #define SLOT_STATE_PWRONLY (1) | |
86 | #define SLOT_STATE_ENABLED (2) | |
87 | #define SLOT_STATE_DISABLED (3) | |
88 | #define PWR_LED_STATE_SHIFT (2) | |
89 | #define PWR_LED_STATE_MASK (3 << 2) | |
90 | #define ATN_LED_STATE_SHIFT (4) | |
91 | #define ATN_LED_STATE_MASK (3 << 4) | |
92 | #define ATN_LED_STATE_ON (1) | |
93 | #define ATN_LED_STATE_BLINK (2) | |
94 | #define ATN_LED_STATE_OFF (3) | |
95 | #define POWER_FAULT (1 << 6) | |
96 | #define ATN_BUTTON (1 << 7) | |
97 | #define MRL_SENSOR (1 << 8) | |
98 | #define MHZ66_CAP (1 << 9) | |
99 | #define PRSNT_SHIFT (10) | |
100 | #define PRSNT_MASK (3 << 10) | |
101 | #define PCIX_CAP_SHIFT (12) | |
102 | #define PCIX_CAP_MASK_PI1 (3 << 12) | |
103 | #define PCIX_CAP_MASK_PI2 (7 << 12) | |
104 | #define PRSNT_CHANGE_DETECTED (1 << 16) | |
105 | #define ISO_PFAULT_DETECTED (1 << 17) | |
106 | #define BUTTON_PRESS_DETECTED (1 << 18) | |
107 | #define MRL_CHANGE_DETECTED (1 << 19) | |
108 | #define CON_PFAULT_DETECTED (1 << 20) | |
109 | #define PRSNT_CHANGE_INTR_MASK (1 << 24) | |
110 | #define ISO_PFAULT_INTR_MASK (1 << 25) | |
111 | #define BUTTON_PRESS_INTR_MASK (1 << 26) | |
112 | #define MRL_CHANGE_INTR_MASK (1 << 27) | |
113 | #define CON_PFAULT_INTR_MASK (1 << 28) | |
114 | #define MRL_CHANGE_SERR_MASK (1 << 29) | |
115 | #define CON_PFAULT_SERR_MASK (1 << 30) | |
116 | #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) | |
1da177e4 | 117 | |
4085399d KK |
118 | /* |
119 | * SHPC Command Code definitnions | |
120 | * | |
121 | * Slot Operation 00h - 3Fh | |
122 | * Set Bus Segment Speed/Mode A 40h - 47h | |
123 | * Power-Only All Slots 48h | |
124 | * Enable All Slots 49h | |
125 | * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh | |
126 | * Reserved Command Codes 60h - BFh | |
127 | * Vendor Specific Commands C0h - FFh | |
128 | */ | |
129 | #define SET_SLOT_PWR 0x01 /* Slot Operation */ | |
130 | #define SET_SLOT_ENABLE 0x02 | |
131 | #define SET_SLOT_DISABLE 0x03 | |
132 | #define SET_PWR_ON 0x04 | |
133 | #define SET_PWR_BLINK 0x08 | |
134 | #define SET_PWR_OFF 0x0c | |
135 | #define SET_ATTN_ON 0x10 | |
136 | #define SET_ATTN_BLINK 0x20 | |
137 | #define SET_ATTN_OFF 0x30 | |
138 | #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ | |
1da177e4 LT |
139 | #define SETA_PCI_66MHZ 0x41 |
140 | #define SETA_PCIX_66MHZ 0x42 | |
141 | #define SETA_PCIX_100MHZ 0x43 | |
142 | #define SETA_PCIX_133MHZ 0x44 | |
4085399d KK |
143 | #define SETA_RESERVED1 0x45 |
144 | #define SETA_RESERVED2 0x46 | |
145 | #define SETA_RESERVED3 0x47 | |
146 | #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ | |
147 | #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ | |
148 | #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ | |
1da177e4 LT |
149 | #define SETB_PCI_66MHZ 0x51 |
150 | #define SETB_PCIX_66MHZ_PM 0x52 | |
151 | #define SETB_PCIX_100MHZ_PM 0x53 | |
152 | #define SETB_PCIX_133MHZ_PM 0x54 | |
153 | #define SETB_PCIX_66MHZ_EM 0x55 | |
154 | #define SETB_PCIX_100MHZ_EM 0x56 | |
155 | #define SETB_PCIX_133MHZ_EM 0x57 | |
156 | #define SETB_PCIX_66MHZ_266 0x58 | |
157 | #define SETB_PCIX_100MHZ_266 0x59 | |
158 | #define SETB_PCIX_133MHZ_266 0x5a | |
159 | #define SETB_PCIX_66MHZ_533 0x5b | |
160 | #define SETB_PCIX_100MHZ_533 0x5c | |
161 | #define SETB_PCIX_133MHZ_533 0x5d | |
4085399d KK |
162 | #define SETB_RESERVED1 0x5e |
163 | #define SETB_RESERVED2 0x5f | |
1da177e4 | 164 | |
4085399d KK |
165 | /* |
166 | * SHPC controller command error code | |
167 | */ | |
1da177e4 LT |
168 | #define SWITCH_OPEN 0x1 |
169 | #define INVALID_CMD 0x2 | |
170 | #define INVALID_SPEED_MODE 0x4 | |
171 | ||
4085399d KK |
172 | /* |
173 | * For accessing SHPC Working Register Set via PCI Configuration Space | |
174 | */ | |
1da177e4 LT |
175 | #define DWORD_SELECT 0x2 |
176 | #define DWORD_DATA 0x4 | |
1da177e4 LT |
177 | |
178 | /* Field Offset in Logical Slot Register - byte boundary */ | |
179 | #define SLOT_EVENT_LATCH 0x2 | |
180 | #define SLOT_SERR_INT_MASK 0x3 | |
181 | ||
82d5f4aa KK |
182 | static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); |
183 | ||
7d12e780 | 184 | static irqreturn_t shpc_isr(int irq, void *dev_id); |
0abe68ce | 185 | static void start_int_poll_timer(struct controller *ctrl, int sec); |
d29aadda | 186 | static int hpc_check_cmd_status(struct controller *ctrl); |
1da177e4 | 187 | |
75d97c59 KK |
188 | static inline u8 shpc_readb(struct controller *ctrl, int reg) |
189 | { | |
0abe68ce | 190 | return readb(ctrl->creg + reg); |
75d97c59 KK |
191 | } |
192 | ||
193 | static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) | |
194 | { | |
0abe68ce | 195 | writeb(val, ctrl->creg + reg); |
75d97c59 KK |
196 | } |
197 | ||
198 | static inline u16 shpc_readw(struct controller *ctrl, int reg) | |
199 | { | |
0abe68ce | 200 | return readw(ctrl->creg + reg); |
75d97c59 KK |
201 | } |
202 | ||
203 | static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) | |
204 | { | |
0abe68ce | 205 | writew(val, ctrl->creg + reg); |
75d97c59 KK |
206 | } |
207 | ||
208 | static inline u32 shpc_readl(struct controller *ctrl, int reg) | |
209 | { | |
0abe68ce | 210 | return readl(ctrl->creg + reg); |
75d97c59 KK |
211 | } |
212 | ||
213 | static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) | |
214 | { | |
0abe68ce | 215 | writel(val, ctrl->creg + reg); |
75d97c59 KK |
216 | } |
217 | ||
218 | static inline int shpc_indirect_read(struct controller *ctrl, int index, | |
219 | u32 *value) | |
220 | { | |
221 | int rc; | |
222 | u32 cap_offset = ctrl->cap_offset; | |
223 | struct pci_dev *pdev = ctrl->pci_dev; | |
224 | ||
225 | rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); | |
226 | if (rc) | |
227 | return rc; | |
228 | return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); | |
229 | } | |
230 | ||
f4263957 KK |
231 | /* |
232 | * This is the interrupt polling timeout function. | |
233 | */ | |
0abe68ce | 234 | static void int_poll_timeout(unsigned long data) |
1da177e4 | 235 | { |
0abe68ce | 236 | struct controller *ctrl = (struct controller *)data; |
1da177e4 | 237 | |
f4263957 | 238 | /* Poll for interrupt events. regs == NULL => polling */ |
0abe68ce | 239 | shpc_isr(0, ctrl); |
1da177e4 | 240 | |
0abe68ce | 241 | init_timer(&ctrl->poll_timer); |
1da177e4 | 242 | if (!shpchp_poll_time) |
f4263957 KK |
243 | shpchp_poll_time = 2; /* default polling interval is 2 sec */ |
244 | ||
0abe68ce | 245 | start_int_poll_timer(ctrl, shpchp_poll_time); |
1da177e4 LT |
246 | } |
247 | ||
f4263957 KK |
248 | /* |
249 | * This function starts the interrupt polling timer. | |
250 | */ | |
0abe68ce | 251 | static void start_int_poll_timer(struct controller *ctrl, int sec) |
1da177e4 | 252 | { |
f4263957 KK |
253 | /* Clamp to sane value */ |
254 | if ((sec <= 0) || (sec > 60)) | |
255 | sec = 2; | |
256 | ||
0abe68ce KK |
257 | ctrl->poll_timer.function = &int_poll_timeout; |
258 | ctrl->poll_timer.data = (unsigned long)ctrl; | |
259 | ctrl->poll_timer.expires = jiffies + sec * HZ; | |
260 | add_timer(&ctrl->poll_timer); | |
1da177e4 LT |
261 | } |
262 | ||
d1729cce KK |
263 | static inline int is_ctrl_busy(struct controller *ctrl) |
264 | { | |
265 | u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); | |
266 | return cmd_status & 0x1; | |
267 | } | |
268 | ||
b4a1efff KK |
269 | /* |
270 | * Returns 1 if SHPC finishes executing a command within 1 sec, | |
271 | * otherwise returns 0. | |
272 | */ | |
273 | static inline int shpc_poll_ctrl_busy(struct controller *ctrl) | |
274 | { | |
275 | int i; | |
b4a1efff | 276 | |
d1729cce | 277 | if (!is_ctrl_busy(ctrl)) |
b4a1efff KK |
278 | return 1; |
279 | ||
280 | /* Check every 0.1 sec for a total of 1 sec */ | |
281 | for (i = 0; i < 10; i++) { | |
282 | msleep(100); | |
d1729cce | 283 | if (!is_ctrl_busy(ctrl)) |
b4a1efff KK |
284 | return 1; |
285 | } | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
bd62e271 KK |
290 | static inline int shpc_wait_cmd(struct controller *ctrl) |
291 | { | |
292 | int retval = 0; | |
b4a1efff KK |
293 | unsigned long timeout = msecs_to_jiffies(1000); |
294 | int rc; | |
295 | ||
296 | if (shpchp_poll_mode) | |
297 | rc = shpc_poll_ctrl_busy(ctrl); | |
298 | else | |
299 | rc = wait_event_interruptible_timeout(ctrl->queue, | |
6aa562c2 | 300 | !is_ctrl_busy(ctrl), timeout); |
d1729cce | 301 | if (!rc && is_ctrl_busy(ctrl)) { |
bd62e271 | 302 | retval = -EIO; |
f98ca311 | 303 | ctrl_err(ctrl, "Command not completed in 1000 msec\n"); |
bd62e271 KK |
304 | } else if (rc < 0) { |
305 | retval = -EINTR; | |
f98ca311 | 306 | ctrl_info(ctrl, "Command was interrupted by a signal\n"); |
bd62e271 | 307 | } |
bd62e271 KK |
308 | |
309 | return retval; | |
310 | } | |
311 | ||
1da177e4 LT |
312 | static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) |
313 | { | |
75d97c59 | 314 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
315 | u16 cmd_status; |
316 | int retval = 0; | |
317 | u16 temp_word; | |
1da177e4 | 318 | |
d29aadda KK |
319 | mutex_lock(&slot->ctrl->cmd_lock); |
320 | ||
b4a1efff | 321 | if (!shpc_poll_ctrl_busy(ctrl)) { |
1da177e4 | 322 | /* After 1 sec and and the controller is still busy */ |
be7bce25 | 323 | ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); |
d29aadda KK |
324 | retval = -EBUSY; |
325 | goto out; | |
1da177e4 LT |
326 | } |
327 | ||
328 | ++t_slot; | |
329 | temp_word = (t_slot << 8) | (cmd & 0xFF); | |
f98ca311 | 330 | ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); |
9f593e30 | 331 | |
1da177e4 | 332 | /* To make sure the Controller Busy bit is 0 before we send out the |
9f593e30 | 333 | * command. |
1da177e4 | 334 | */ |
75d97c59 | 335 | shpc_writew(ctrl, CMD, temp_word); |
1da177e4 | 336 | |
bd62e271 KK |
337 | /* |
338 | * Wait for command completion. | |
339 | */ | |
340 | retval = shpc_wait_cmd(slot->ctrl); | |
d29aadda KK |
341 | if (retval) |
342 | goto out; | |
343 | ||
344 | cmd_status = hpc_check_cmd_status(slot->ctrl); | |
345 | if (cmd_status) { | |
be7bce25 TI |
346 | ctrl_err(ctrl, |
347 | "Failed to issued command 0x%x (error code = %d)\n", | |
348 | cmd, cmd_status); | |
d29aadda KK |
349 | retval = -EIO; |
350 | } | |
351 | out: | |
352 | mutex_unlock(&slot->ctrl->cmd_lock); | |
1da177e4 LT |
353 | return retval; |
354 | } | |
355 | ||
356 | static int hpc_check_cmd_status(struct controller *ctrl) | |
357 | { | |
1da177e4 | 358 | int retval = 0; |
1555b33d | 359 | u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; |
9f593e30 | 360 | |
1da177e4 LT |
361 | switch (cmd_status >> 1) { |
362 | case 0: | |
363 | retval = 0; | |
364 | break; | |
365 | case 1: | |
366 | retval = SWITCH_OPEN; | |
be7bce25 | 367 | ctrl_err(ctrl, "Switch opened!\n"); |
1da177e4 LT |
368 | break; |
369 | case 2: | |
370 | retval = INVALID_CMD; | |
be7bce25 | 371 | ctrl_err(ctrl, "Invalid HPC command!\n"); |
1da177e4 LT |
372 | break; |
373 | case 4: | |
374 | retval = INVALID_SPEED_MODE; | |
be7bce25 | 375 | ctrl_err(ctrl, "Invalid bus speed/mode!\n"); |
1da177e4 LT |
376 | break; |
377 | default: | |
378 | retval = cmd_status; | |
379 | } | |
380 | ||
1da177e4 LT |
381 | return retval; |
382 | } | |
383 | ||
384 | ||
385 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
386 | { | |
75d97c59 | 387 | struct controller *ctrl = slot->ctrl; |
1555b33d KK |
388 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
389 | u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; | |
1da177e4 | 390 | |
5858759c KK |
391 | switch (state) { |
392 | case ATN_LED_STATE_ON: | |
1da177e4 LT |
393 | *status = 1; /* On */ |
394 | break; | |
5858759c | 395 | case ATN_LED_STATE_BLINK: |
1da177e4 LT |
396 | *status = 2; /* Blink */ |
397 | break; | |
5858759c | 398 | case ATN_LED_STATE_OFF: |
1da177e4 LT |
399 | *status = 0; /* Off */ |
400 | break; | |
401 | default: | |
5858759c | 402 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
403 | break; |
404 | } | |
405 | ||
1da177e4 LT |
406 | return 0; |
407 | } | |
408 | ||
409 | static int hpc_get_power_status(struct slot * slot, u8 *status) | |
410 | { | |
75d97c59 | 411 | struct controller *ctrl = slot->ctrl; |
1555b33d KK |
412 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
413 | u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; | |
1da177e4 | 414 | |
5858759c KK |
415 | switch (state) { |
416 | case SLOT_STATE_PWRONLY: | |
1da177e4 LT |
417 | *status = 2; /* Powered only */ |
418 | break; | |
5858759c | 419 | case SLOT_STATE_ENABLED: |
1da177e4 LT |
420 | *status = 1; /* Enabled */ |
421 | break; | |
5858759c | 422 | case SLOT_STATE_DISABLED: |
1da177e4 LT |
423 | *status = 0; /* Disabled */ |
424 | break; | |
425 | default: | |
5858759c | 426 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
427 | break; |
428 | } | |
429 | ||
5858759c | 430 | return 0; |
1da177e4 LT |
431 | } |
432 | ||
433 | ||
434 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
435 | { | |
75d97c59 | 436 | struct controller *ctrl = slot->ctrl; |
1555b33d | 437 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
1da177e4 | 438 | |
5858759c | 439 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
1da177e4 | 440 | |
1da177e4 LT |
441 | return 0; |
442 | } | |
443 | ||
444 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
445 | { | |
75d97c59 | 446 | struct controller *ctrl = slot->ctrl; |
1555b33d KK |
447 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
448 | u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; | |
1da177e4 | 449 | |
5858759c | 450 | *status = (state != 0x3) ? 1 : 0; |
1da177e4 | 451 | |
1da177e4 LT |
452 | return 0; |
453 | } | |
454 | ||
455 | static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) | |
456 | { | |
75d97c59 | 457 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 458 | |
75d97c59 | 459 | *prog_int = shpc_readb(ctrl, PROG_INTERFACE); |
1da177e4 | 460 | |
1da177e4 LT |
461 | return 0; |
462 | } | |
463 | ||
464 | static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |
465 | { | |
1da177e4 | 466 | int retval = 0; |
75d97c59 | 467 | struct controller *ctrl = slot->ctrl; |
2b34da7e | 468 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 469 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); |
795eb5c4 | 470 | u8 pi, pcix_cap; |
1da177e4 | 471 | |
795eb5c4 KK |
472 | if ((retval = hpc_get_prog_int(slot, &pi))) |
473 | return retval; | |
474 | ||
475 | switch (pi) { | |
476 | case 1: | |
477 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; | |
478 | break; | |
479 | case 2: | |
480 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; | |
481 | break; | |
482 | default: | |
483 | return -ENODEV; | |
484 | } | |
485 | ||
f98ca311 TI |
486 | ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", |
487 | __func__, slot_reg, pcix_cap, m66_cap); | |
1da177e4 | 488 | |
0afabe90 KK |
489 | switch (pcix_cap) { |
490 | case 0x0: | |
491 | *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; | |
492 | break; | |
493 | case 0x1: | |
494 | *value = PCI_SPEED_66MHz_PCIX; | |
495 | break; | |
496 | case 0x3: | |
497 | *value = PCI_SPEED_133MHz_PCIX; | |
498 | break; | |
499 | case 0x4: | |
500 | *value = PCI_SPEED_133MHz_PCIX_266; | |
501 | break; | |
502 | case 0x5: | |
503 | *value = PCI_SPEED_133MHz_PCIX_533; | |
504 | break; | |
505 | case 0x2: | |
506 | default: | |
507 | *value = PCI_SPEED_UNKNOWN; | |
508 | retval = -ENODEV; | |
509 | break; | |
1da177e4 LT |
510 | } |
511 | ||
f98ca311 | 512 | ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); |
1da177e4 LT |
513 | return retval; |
514 | } | |
515 | ||
516 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | |
517 | { | |
1da177e4 | 518 | int retval = 0; |
1555b33d KK |
519 | struct controller *ctrl = slot->ctrl; |
520 | u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); | |
521 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | |
1da177e4 LT |
522 | |
523 | if (pi == 2) { | |
87d6c559 | 524 | *mode = (sec_bus_status & 0x0100) >> 8; |
1da177e4 LT |
525 | } else { |
526 | retval = -1; | |
527 | } | |
528 | ||
f98ca311 | 529 | ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); |
1da177e4 LT |
530 | return retval; |
531 | } | |
532 | ||
533 | static int hpc_query_power_fault(struct slot * slot) | |
534 | { | |
75d97c59 | 535 | struct controller *ctrl = slot->ctrl; |
1555b33d | 536 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
1da177e4 | 537 | |
1da177e4 | 538 | /* Note: Logic 0 => fault */ |
5858759c | 539 | return !(slot_reg & POWER_FAULT); |
1da177e4 LT |
540 | } |
541 | ||
542 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
543 | { | |
1da177e4 | 544 | u8 slot_cmd = 0; |
1da177e4 LT |
545 | |
546 | switch (value) { | |
9f593e30 | 547 | case 0 : |
4085399d | 548 | slot_cmd = SET_ATTN_OFF; /* OFF */ |
1da177e4 LT |
549 | break; |
550 | case 1: | |
4085399d | 551 | slot_cmd = SET_ATTN_ON; /* ON */ |
1da177e4 LT |
552 | break; |
553 | case 2: | |
4085399d | 554 | slot_cmd = SET_ATTN_BLINK; /* BLINK */ |
1da177e4 LT |
555 | break; |
556 | default: | |
557 | return -1; | |
558 | } | |
559 | ||
d4fbf600 | 560 | return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); |
1da177e4 LT |
561 | } |
562 | ||
563 | ||
564 | static void hpc_set_green_led_on(struct slot *slot) | |
565 | { | |
4085399d | 566 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); |
1da177e4 LT |
567 | } |
568 | ||
569 | static void hpc_set_green_led_off(struct slot *slot) | |
570 | { | |
4085399d | 571 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); |
1da177e4 LT |
572 | } |
573 | ||
574 | static void hpc_set_green_led_blink(struct slot *slot) | |
575 | { | |
4085399d | 576 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); |
1da177e4 LT |
577 | } |
578 | ||
1da177e4 LT |
579 | static void hpc_release_ctlr(struct controller *ctrl) |
580 | { | |
f7391f53 | 581 | int i; |
d49f2c49 | 582 | u32 slot_reg, serr_int; |
1da177e4 | 583 | |
f7391f53 | 584 | /* |
795eb5c4 | 585 | * Mask event interrupts and SERRs of all slots |
f7391f53 | 586 | */ |
795eb5c4 KK |
587 | for (i = 0; i < ctrl->num_slots; i++) { |
588 | slot_reg = shpc_readl(ctrl, SLOT_REG(i)); | |
589 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | | |
590 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
591 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | |
592 | CON_PFAULT_SERR_MASK); | |
593 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
594 | shpc_writel(ctrl, SLOT_REG(i), slot_reg); | |
595 | } | |
f7391f53 KK |
596 | |
597 | cleanup_slots(ctrl); | |
598 | ||
d49f2c49 | 599 | /* |
3609801e | 600 | * Mask SERR and System Interrupt generation |
d49f2c49 KK |
601 | */ |
602 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
603 | serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | | |
604 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); | |
605 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
606 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
607 | ||
0abe68ce KK |
608 | if (shpchp_poll_mode) |
609 | del_timer(&ctrl->poll_timer); | |
610 | else { | |
611 | free_irq(ctrl->pci_dev->irq, ctrl); | |
612 | pci_disable_msi(ctrl->pci_dev); | |
1da177e4 | 613 | } |
1da177e4 | 614 | |
0abe68ce KK |
615 | iounmap(ctrl->creg); |
616 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | |
1da177e4 | 617 | |
82d5f4aa KK |
618 | /* |
619 | * If this is the last controller to be released, destroy the | |
620 | * shpchpd work queue | |
621 | */ | |
622 | if (atomic_dec_and_test(&shpchp_num_controllers)) | |
623 | destroy_workqueue(shpchp_wq); | |
1da177e4 LT |
624 | } |
625 | ||
626 | static int hpc_power_on_slot(struct slot * slot) | |
627 | { | |
d4fbf600 | 628 | int retval; |
1da177e4 | 629 | |
4085399d | 630 | retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); |
1555b33d | 631 | if (retval) |
f98ca311 | 632 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
1da177e4 | 633 | |
1555b33d | 634 | return retval; |
1da177e4 LT |
635 | } |
636 | ||
637 | static int hpc_slot_enable(struct slot * slot) | |
638 | { | |
d4fbf600 | 639 | int retval; |
1da177e4 | 640 | |
4085399d KK |
641 | /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ |
642 | retval = shpc_write_cmd(slot, slot->hp_slot, | |
643 | SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); | |
1555b33d | 644 | if (retval) |
f98ca311 | 645 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
1da177e4 | 646 | |
1555b33d | 647 | return retval; |
1da177e4 LT |
648 | } |
649 | ||
650 | static int hpc_slot_disable(struct slot * slot) | |
651 | { | |
d4fbf600 | 652 | int retval; |
1da177e4 | 653 | |
4085399d KK |
654 | /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ |
655 | retval = shpc_write_cmd(slot, slot->hp_slot, | |
656 | SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); | |
1555b33d | 657 | if (retval) |
f98ca311 | 658 | ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); |
1da177e4 | 659 | |
1555b33d | 660 | return retval; |
1da177e4 LT |
661 | } |
662 | ||
1da177e4 LT |
663 | static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) |
664 | { | |
0afabe90 | 665 | int retval; |
75d97c59 | 666 | struct controller *ctrl = slot->ctrl; |
0afabe90 | 667 | u8 pi, cmd; |
1da177e4 | 668 | |
75d97c59 | 669 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
0afabe90 KK |
670 | if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) |
671 | return -EINVAL; | |
1da177e4 | 672 | |
0afabe90 KK |
673 | switch (value) { |
674 | case PCI_SPEED_33MHz: | |
675 | cmd = SETA_PCI_33MHZ; | |
676 | break; | |
677 | case PCI_SPEED_66MHz: | |
678 | cmd = SETA_PCI_66MHZ; | |
679 | break; | |
680 | case PCI_SPEED_66MHz_PCIX: | |
681 | cmd = SETA_PCIX_66MHZ; | |
682 | break; | |
683 | case PCI_SPEED_100MHz_PCIX: | |
684 | cmd = SETA_PCIX_100MHZ; | |
685 | break; | |
686 | case PCI_SPEED_133MHz_PCIX: | |
687 | cmd = SETA_PCIX_133MHZ; | |
688 | break; | |
689 | case PCI_SPEED_66MHz_PCIX_ECC: | |
690 | cmd = SETB_PCIX_66MHZ_EM; | |
691 | break; | |
692 | case PCI_SPEED_100MHz_PCIX_ECC: | |
693 | cmd = SETB_PCIX_100MHZ_EM; | |
694 | break; | |
695 | case PCI_SPEED_133MHz_PCIX_ECC: | |
696 | cmd = SETB_PCIX_133MHZ_EM; | |
697 | break; | |
698 | case PCI_SPEED_66MHz_PCIX_266: | |
699 | cmd = SETB_PCIX_66MHZ_266; | |
700 | break; | |
701 | case PCI_SPEED_100MHz_PCIX_266: | |
702 | cmd = SETB_PCIX_100MHZ_266; | |
703 | break; | |
704 | case PCI_SPEED_133MHz_PCIX_266: | |
705 | cmd = SETB_PCIX_133MHZ_266; | |
706 | break; | |
707 | case PCI_SPEED_66MHz_PCIX_533: | |
708 | cmd = SETB_PCIX_66MHZ_533; | |
709 | break; | |
710 | case PCI_SPEED_100MHz_PCIX_533: | |
711 | cmd = SETB_PCIX_100MHZ_533; | |
712 | break; | |
713 | case PCI_SPEED_133MHz_PCIX_533: | |
714 | cmd = SETB_PCIX_133MHZ_533; | |
715 | break; | |
716 | default: | |
717 | return -EINVAL; | |
1da177e4 | 718 | } |
0afabe90 KK |
719 | |
720 | retval = shpc_write_cmd(slot, 0, cmd); | |
721 | if (retval) | |
f98ca311 | 722 | ctrl_err(ctrl, "%s: Write command failed!\n", __func__); |
1da177e4 | 723 | |
1da177e4 LT |
724 | return retval; |
725 | } | |
726 | ||
7d12e780 | 727 | static irqreturn_t shpc_isr(int irq, void *dev_id) |
1da177e4 | 728 | { |
c4cecc19 | 729 | struct controller *ctrl = (struct controller *)dev_id; |
c4cecc19 | 730 | u32 serr_int, slot_reg, intr_loc, intr_loc2; |
1da177e4 LT |
731 | int hp_slot; |
732 | ||
1da177e4 | 733 | /* Check to see if it was our interrupt */ |
75d97c59 | 734 | intr_loc = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
735 | if (!intr_loc) |
736 | return IRQ_NONE; | |
c4cecc19 | 737 | |
f98ca311 | 738 | ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); |
1da177e4 LT |
739 | |
740 | if(!shpchp_poll_mode) { | |
c4cecc19 KK |
741 | /* |
742 | * Mask Global Interrupt Mask - see implementation | |
743 | * note on p. 139 of SHPC spec rev 1.0 | |
744 | */ | |
745 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
746 | serr_int |= GLOBAL_INTR_MASK; | |
747 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
748 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
1da177e4 | 749 | |
75d97c59 | 750 | intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
f98ca311 | 751 | ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); |
1da177e4 LT |
752 | } |
753 | ||
c4cecc19 | 754 | if (intr_loc & CMD_INTR_PENDING) { |
9f593e30 KK |
755 | /* |
756 | * Command Complete Interrupt Pending | |
f467f618 | 757 | * RO only - clear by writing 1 to the Command Completion |
1da177e4 LT |
758 | * Detect bit in Controller SERR-INT register |
759 | */ | |
c4cecc19 KK |
760 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
761 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
762 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
763 | ||
1da177e4 LT |
764 | wake_up_interruptible(&ctrl->queue); |
765 | } | |
766 | ||
c4cecc19 | 767 | if (!(intr_loc & ~CMD_INTR_PENDING)) |
e4e73041 | 768 | goto out; |
1da177e4 | 769 | |
9f593e30 | 770 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
c4cecc19 KK |
771 | /* To find out which slot has interrupt pending */ |
772 | if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) | |
773 | continue; | |
774 | ||
775 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); | |
be7bce25 TI |
776 | ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", |
777 | hp_slot, slot_reg); | |
c4cecc19 KK |
778 | |
779 | if (slot_reg & MRL_CHANGE_DETECTED) | |
0abe68ce | 780 | shpchp_handle_switch_change(hp_slot, ctrl); |
c4cecc19 KK |
781 | |
782 | if (slot_reg & BUTTON_PRESS_DETECTED) | |
0abe68ce | 783 | shpchp_handle_attention_button(hp_slot, ctrl); |
c4cecc19 KK |
784 | |
785 | if (slot_reg & PRSNT_CHANGE_DETECTED) | |
0abe68ce | 786 | shpchp_handle_presence_change(hp_slot, ctrl); |
c4cecc19 KK |
787 | |
788 | if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) | |
0abe68ce | 789 | shpchp_handle_power_fault(hp_slot, ctrl); |
c4cecc19 KK |
790 | |
791 | /* Clear all slot events */ | |
792 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
793 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 | 794 | } |
e4e73041 | 795 | out: |
1da177e4 LT |
796 | if (!shpchp_poll_mode) { |
797 | /* Unmask Global Interrupt Mask */ | |
c4cecc19 KK |
798 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
799 | serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); | |
800 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
1da177e4 | 801 | } |
9f593e30 | 802 | |
1da177e4 LT |
803 | return IRQ_HANDLED; |
804 | } | |
805 | ||
806 | static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |
807 | { | |
0afabe90 | 808 | int retval = 0; |
75d97c59 | 809 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 810 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
811 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
812 | u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); | |
813 | u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); | |
1da177e4 | 814 | |
1da177e4 | 815 | if (pi == 2) { |
6558b6ab | 816 | if (slot_avail2 & SLOT_133MHZ_PCIX_533) |
0afabe90 | 817 | bus_speed = PCI_SPEED_133MHz_PCIX_533; |
6558b6ab | 818 | else if (slot_avail2 & SLOT_100MHZ_PCIX_533) |
0afabe90 | 819 | bus_speed = PCI_SPEED_100MHz_PCIX_533; |
6558b6ab | 820 | else if (slot_avail2 & SLOT_66MHZ_PCIX_533) |
0afabe90 | 821 | bus_speed = PCI_SPEED_66MHz_PCIX_533; |
6558b6ab | 822 | else if (slot_avail2 & SLOT_133MHZ_PCIX_266) |
0afabe90 | 823 | bus_speed = PCI_SPEED_133MHz_PCIX_266; |
6558b6ab | 824 | else if (slot_avail2 & SLOT_100MHZ_PCIX_266) |
0afabe90 | 825 | bus_speed = PCI_SPEED_100MHz_PCIX_266; |
6558b6ab | 826 | else if (slot_avail2 & SLOT_66MHZ_PCIX_266) |
0afabe90 KK |
827 | bus_speed = PCI_SPEED_66MHz_PCIX_266; |
828 | } | |
829 | ||
830 | if (bus_speed == PCI_SPEED_UNKNOWN) { | |
6558b6ab | 831 | if (slot_avail1 & SLOT_133MHZ_PCIX) |
0afabe90 | 832 | bus_speed = PCI_SPEED_133MHz_PCIX; |
6558b6ab | 833 | else if (slot_avail1 & SLOT_100MHZ_PCIX) |
0afabe90 | 834 | bus_speed = PCI_SPEED_100MHz_PCIX; |
6558b6ab | 835 | else if (slot_avail1 & SLOT_66MHZ_PCIX) |
0afabe90 | 836 | bus_speed = PCI_SPEED_66MHz_PCIX; |
6558b6ab | 837 | else if (slot_avail2 & SLOT_66MHZ) |
0afabe90 | 838 | bus_speed = PCI_SPEED_66MHz; |
6558b6ab | 839 | else if (slot_avail1 & SLOT_33MHZ) |
0afabe90 KK |
840 | bus_speed = PCI_SPEED_33MHz; |
841 | else | |
842 | retval = -ENODEV; | |
1da177e4 LT |
843 | } |
844 | ||
845 | *value = bus_speed; | |
f98ca311 | 846 | ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); |
1555b33d | 847 | |
1da177e4 LT |
848 | return retval; |
849 | } | |
850 | ||
851 | static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |
852 | { | |
0afabe90 | 853 | int retval = 0; |
75d97c59 | 854 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 855 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
856 | u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); |
857 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | |
0afabe90 | 858 | u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); |
1da177e4 | 859 | |
0afabe90 KK |
860 | if ((pi == 1) && (speed_mode > 4)) { |
861 | *value = PCI_SPEED_UNKNOWN; | |
862 | return -ENODEV; | |
1da177e4 LT |
863 | } |
864 | ||
0afabe90 KK |
865 | switch (speed_mode) { |
866 | case 0x0: | |
867 | *value = PCI_SPEED_33MHz; | |
868 | break; | |
869 | case 0x1: | |
870 | *value = PCI_SPEED_66MHz; | |
871 | break; | |
872 | case 0x2: | |
873 | *value = PCI_SPEED_66MHz_PCIX; | |
874 | break; | |
875 | case 0x3: | |
876 | *value = PCI_SPEED_100MHz_PCIX; | |
877 | break; | |
878 | case 0x4: | |
879 | *value = PCI_SPEED_133MHz_PCIX; | |
880 | break; | |
881 | case 0x5: | |
882 | *value = PCI_SPEED_66MHz_PCIX_ECC; | |
883 | break; | |
884 | case 0x6: | |
885 | *value = PCI_SPEED_100MHz_PCIX_ECC; | |
886 | break; | |
887 | case 0x7: | |
888 | *value = PCI_SPEED_133MHz_PCIX_ECC; | |
889 | break; | |
890 | case 0x8: | |
891 | *value = PCI_SPEED_66MHz_PCIX_266; | |
892 | break; | |
893 | case 0x9: | |
894 | *value = PCI_SPEED_100MHz_PCIX_266; | |
895 | break; | |
896 | case 0xa: | |
897 | *value = PCI_SPEED_133MHz_PCIX_266; | |
898 | break; | |
899 | case 0xb: | |
900 | *value = PCI_SPEED_66MHz_PCIX_533; | |
901 | break; | |
902 | case 0xc: | |
903 | *value = PCI_SPEED_100MHz_PCIX_533; | |
904 | break; | |
905 | case 0xd: | |
906 | *value = PCI_SPEED_133MHz_PCIX_533; | |
907 | break; | |
908 | default: | |
909 | *value = PCI_SPEED_UNKNOWN; | |
910 | retval = -ENODEV; | |
911 | break; | |
1da177e4 LT |
912 | } |
913 | ||
f98ca311 | 914 | ctrl_dbg(ctrl, "Current bus speed = %d\n", bus_speed); |
1da177e4 LT |
915 | return retval; |
916 | } | |
917 | ||
918 | static struct hpc_ops shpchp_hpc_ops = { | |
919 | .power_on_slot = hpc_power_on_slot, | |
920 | .slot_enable = hpc_slot_enable, | |
921 | .slot_disable = hpc_slot_disable, | |
9f593e30 | 922 | .set_bus_speed_mode = hpc_set_bus_speed_mode, |
1da177e4 LT |
923 | .set_attention_status = hpc_set_attention_status, |
924 | .get_power_status = hpc_get_power_status, | |
925 | .get_attention_status = hpc_get_attention_status, | |
926 | .get_latch_status = hpc_get_latch_status, | |
927 | .get_adapter_status = hpc_get_adapter_status, | |
928 | ||
929 | .get_max_bus_speed = hpc_get_max_bus_speed, | |
930 | .get_cur_bus_speed = hpc_get_cur_bus_speed, | |
931 | .get_adapter_speed = hpc_get_adapter_speed, | |
932 | .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, | |
933 | .get_prog_int = hpc_get_prog_int, | |
934 | ||
935 | .query_power_fault = hpc_query_power_fault, | |
936 | .green_led_on = hpc_set_green_led_on, | |
937 | .green_led_off = hpc_set_green_led_off, | |
938 | .green_led_blink = hpc_set_green_led_blink, | |
9f593e30 | 939 | |
1da177e4 | 940 | .release_ctlr = hpc_release_ctlr, |
1da177e4 LT |
941 | }; |
942 | ||
0abe68ce | 943 | int shpc_init(struct controller *ctrl, struct pci_dev *pdev) |
1da177e4 | 944 | { |
662a98fb | 945 | int rc = -1, num_slots = 0; |
1da177e4 | 946 | u8 hp_slot; |
0455986c | 947 | u32 shpc_base_offset; |
75d97c59 | 948 | u32 tempdword, slot_reg, slot_config; |
1da177e4 LT |
949 | u8 i; |
950 | ||
0455986c | 951 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
be7bce25 | 952 | ctrl_dbg(ctrl, "Hotplug Controller:\n"); |
0455986c | 953 | |
ee138334 RS |
954 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == |
955 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { | |
0455986c KK |
956 | /* amd shpc driver doesn't use Base Offset; assume 0 */ |
957 | ctrl->mmio_base = pci_resource_start(pdev, 0); | |
958 | ctrl->mmio_size = pci_resource_len(pdev, 0); | |
1da177e4 | 959 | } else { |
0455986c KK |
960 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
961 | if (!ctrl->cap_offset) { | |
be7bce25 | 962 | ctrl_err(ctrl, "Cannot find PCI capability\n"); |
0abe68ce | 963 | goto abort; |
1da177e4 | 964 | } |
be7bce25 | 965 | ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); |
0455986c | 966 | |
75d97c59 | 967 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
1da177e4 | 968 | if (rc) { |
be7bce25 | 969 | ctrl_err(ctrl, "Cannot read base_offset\n"); |
0abe68ce | 970 | goto abort; |
1da177e4 | 971 | } |
0455986c | 972 | |
75d97c59 | 973 | rc = shpc_indirect_read(ctrl, 3, &tempdword); |
1da177e4 | 974 | if (rc) { |
be7bce25 | 975 | ctrl_err(ctrl, "Cannot read slot config\n"); |
0abe68ce | 976 | goto abort; |
1da177e4 | 977 | } |
0455986c | 978 | num_slots = tempdword & SLOT_NUM; |
be7bce25 | 979 | ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); |
1da177e4 | 980 | |
0455986c | 981 | for (i = 0; i < 9 + num_slots; i++) { |
75d97c59 | 982 | rc = shpc_indirect_read(ctrl, i, &tempdword); |
1da177e4 | 983 | if (rc) { |
be7bce25 TI |
984 | ctrl_err(ctrl, |
985 | "Cannot read creg (index = %d)\n", i); | |
0abe68ce | 986 | goto abort; |
1da177e4 | 987 | } |
be7bce25 | 988 | ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); |
1da177e4 | 989 | } |
0455986c KK |
990 | |
991 | ctrl->mmio_base = | |
992 | pci_resource_start(pdev, 0) + shpc_base_offset; | |
993 | ctrl->mmio_size = 0x24 + 0x4 * num_slots; | |
1da177e4 LT |
994 | } |
995 | ||
f98ca311 TI |
996 | ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", |
997 | pdev->vendor, pdev->device, pdev->subsystem_vendor, | |
998 | pdev->subsystem_device); | |
9f593e30 | 999 | |
662a98fb AL |
1000 | rc = pci_enable_device(pdev); |
1001 | if (rc) { | |
be7bce25 | 1002 | ctrl_err(ctrl, "pci_enable_device failed\n"); |
0abe68ce | 1003 | goto abort; |
662a98fb | 1004 | } |
1da177e4 | 1005 | |
0455986c | 1006 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
be7bce25 | 1007 | ctrl_err(ctrl, "Cannot reserve MMIO region\n"); |
662a98fb | 1008 | rc = -1; |
0abe68ce | 1009 | goto abort; |
1da177e4 LT |
1010 | } |
1011 | ||
0abe68ce KK |
1012 | ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
1013 | if (!ctrl->creg) { | |
be7bce25 TI |
1014 | ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", |
1015 | ctrl->mmio_size, ctrl->mmio_base); | |
0455986c | 1016 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
662a98fb | 1017 | rc = -1; |
0abe68ce | 1018 | goto abort; |
1da177e4 | 1019 | } |
be7bce25 | 1020 | ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); |
1da177e4 | 1021 | |
6aa4cdd0 | 1022 | mutex_init(&ctrl->crit_sect); |
d29aadda KK |
1023 | mutex_init(&ctrl->cmd_lock); |
1024 | ||
1da177e4 LT |
1025 | /* Setup wait queue */ |
1026 | init_waitqueue_head(&ctrl->queue); | |
1027 | ||
75d97c59 KK |
1028 | ctrl->hpc_ops = &shpchp_hpc_ops; |
1029 | ||
1da177e4 | 1030 | /* Return PCI Controller Info */ |
75d97c59 | 1031 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
0abe68ce KK |
1032 | ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; |
1033 | ctrl->num_slots = slot_config & SLOT_NUM; | |
1034 | ctrl->first_slot = (slot_config & PSN) >> 16; | |
1035 | ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; | |
1da177e4 LT |
1036 | |
1037 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ | |
75d97c59 | 1038 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
be7bce25 | 1039 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
e7138723 KK |
1040 | tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
1041 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); | |
1042 | tempdword &= ~SERR_INTR_RSVDZ_MASK; | |
75d97c59 KK |
1043 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1044 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
be7bce25 | 1045 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
1da177e4 LT |
1046 | |
1047 | /* Mask the MRL sensor SERR Mask of individual slot in | |
1048 | * Slot SERR-INT Mask & clear all the existing event if any | |
1049 | */ | |
0abe68ce | 1050 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
2b34da7e | 1051 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
be7bce25 TI |
1052 | ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
1053 | hp_slot, slot_reg); | |
795eb5c4 KK |
1054 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1055 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
1056 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | |
1057 | CON_PFAULT_SERR_MASK); | |
1058 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
1059 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 | 1060 | } |
9f593e30 | 1061 | |
0abe68ce KK |
1062 | if (shpchp_poll_mode) { |
1063 | /* Install interrupt polling timer. Start with 10 sec delay */ | |
1064 | init_timer(&ctrl->poll_timer); | |
1065 | start_int_poll_timer(ctrl, 10); | |
1da177e4 LT |
1066 | } else { |
1067 | /* Installs the interrupt handler */ | |
1068 | rc = pci_enable_msi(pdev); | |
1069 | if (rc) { | |
f98ca311 TI |
1070 | ctrl_info(ctrl, |
1071 | "Can't get msi for the hotplug controller\n"); | |
1072 | ctrl_info(ctrl, | |
1073 | "Use INTx for the hotplug controller\n"); | |
0abe68ce | 1074 | } |
9f593e30 | 1075 | |
0abe68ce KK |
1076 | rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, |
1077 | MY_NAME, (void *)ctrl); | |
be7bce25 TI |
1078 | ctrl_dbg(ctrl, "request_irq %d for hpc%d (returns %d)\n", |
1079 | ctrl->pci_dev->irq, | |
0abe68ce | 1080 | atomic_read(&shpchp_num_controllers), rc); |
1da177e4 | 1081 | if (rc) { |
f98ca311 TI |
1082 | ctrl_err(ctrl, "Can't get irq %d for the hotplug " |
1083 | "controller\n", ctrl->pci_dev->irq); | |
0abe68ce | 1084 | goto abort_iounmap; |
1da177e4 | 1085 | } |
1da177e4 | 1086 | } |
be7bce25 | 1087 | ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); |
1da177e4 | 1088 | |
82d5f4aa KK |
1089 | /* |
1090 | * If this is the first controller to be initialized, | |
1091 | * initialize the shpchpd work queue | |
1092 | */ | |
1093 | if (atomic_add_return(1, &shpchp_num_controllers) == 1) { | |
1094 | shpchp_wq = create_singlethread_workqueue("shpchpd"); | |
662a98fb AL |
1095 | if (!shpchp_wq) { |
1096 | rc = -ENOMEM; | |
0abe68ce | 1097 | goto abort_iounmap; |
662a98fb | 1098 | } |
82d5f4aa KK |
1099 | } |
1100 | ||
795eb5c4 KK |
1101 | /* |
1102 | * Unmask all event interrupts of all slots | |
1103 | */ | |
0abe68ce | 1104 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { |
2b34da7e | 1105 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
be7bce25 TI |
1106 | ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", |
1107 | hp_slot, slot_reg); | |
795eb5c4 KK |
1108 | slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1109 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
1110 | CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); | |
1111 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 LT |
1112 | } |
1113 | if (!shpchp_poll_mode) { | |
1114 | /* Unmask all general input interrupts and SERR */ | |
75d97c59 | 1115 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
e7138723 KK |
1116 | tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | |
1117 | SERR_INTR_RSVDZ_MASK); | |
75d97c59 KK |
1118 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1119 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
be7bce25 | 1120 | ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); |
1da177e4 LT |
1121 | } |
1122 | ||
1da177e4 LT |
1123 | return 0; |
1124 | ||
1125 | /* We end up here for the many possible ways to fail this API. */ | |
0abe68ce KK |
1126 | abort_iounmap: |
1127 | iounmap(ctrl->creg); | |
1da177e4 | 1128 | abort: |
662a98fb | 1129 | return rc; |
1da177e4 | 1130 | } |