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1da177e4 LT |
1 | /* |
2 | * Standard PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
d4d28dd4 AM |
34 | #include <linux/interrupt.h> |
35 | ||
1da177e4 LT |
36 | #include "shpchp.h" |
37 | ||
38 | #ifdef DEBUG | |
39 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ | |
40 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ | |
41 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ | |
42 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ | |
43 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) | |
44 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) | |
45 | /* Redefine this flagword to set debug level */ | |
46 | #define DEBUG_LEVEL DBG_K_STANDARD | |
47 | ||
48 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; | |
49 | ||
50 | #define DBG_PRINT( dbg_flags, args... ) \ | |
51 | do { \ | |
52 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ | |
53 | { \ | |
54 | int len; \ | |
55 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ | |
56 | __FILE__, __LINE__, __FUNCTION__ ); \ | |
57 | sprintf( __dbg_str_buf + len, args ); \ | |
58 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ | |
59 | } \ | |
60 | } while (0) | |
61 | ||
62 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); | |
63 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); | |
64 | #else | |
65 | #define DEFINE_DBG_BUFFER | |
66 | #define DBG_ENTER_ROUTINE | |
67 | #define DBG_LEAVE_ROUTINE | |
68 | #endif /* DEBUG */ | |
69 | ||
70 | /* Slot Available Register I field definition */ | |
71 | #define SLOT_33MHZ 0x0000001f | |
72 | #define SLOT_66MHZ_PCIX 0x00001f00 | |
73 | #define SLOT_100MHZ_PCIX 0x001f0000 | |
74 | #define SLOT_133MHZ_PCIX 0x1f000000 | |
75 | ||
76 | /* Slot Available Register II field definition */ | |
77 | #define SLOT_66MHZ 0x0000001f | |
78 | #define SLOT_66MHZ_PCIX_266 0x00000f00 | |
79 | #define SLOT_100MHZ_PCIX_266 0x0000f000 | |
80 | #define SLOT_133MHZ_PCIX_266 0x000f0000 | |
81 | #define SLOT_66MHZ_PCIX_533 0x00f00000 | |
82 | #define SLOT_100MHZ_PCIX_533 0x0f000000 | |
83 | #define SLOT_133MHZ_PCIX_533 0xf0000000 | |
84 | ||
1da177e4 LT |
85 | /* Slot Configuration */ |
86 | #define SLOT_NUM 0x0000001F | |
87 | #define FIRST_DEV_NUM 0x00001F00 | |
88 | #define PSN 0x07FF0000 | |
89 | #define UPDOWN 0x20000000 | |
90 | #define MRLSENSOR 0x40000000 | |
91 | #define ATTN_BUTTON 0x80000000 | |
92 | ||
c4cecc19 KK |
93 | /* |
94 | * Interrupt Locator Register definitions | |
95 | */ | |
96 | #define CMD_INTR_PENDING (1 << 0) | |
97 | #define SLOT_INTR_PENDING(i) (1 << (i + 1)) | |
98 | ||
e7138723 KK |
99 | /* |
100 | * Controller SERR-INT Register | |
101 | */ | |
102 | #define GLOBAL_INTR_MASK (1 << 0) | |
103 | #define GLOBAL_SERR_MASK (1 << 1) | |
104 | #define COMMAND_INTR_MASK (1 << 2) | |
105 | #define ARBITER_SERR_MASK (1 << 3) | |
106 | #define COMMAND_DETECTED (1 << 16) | |
107 | #define ARBITER_DETECTED (1 << 17) | |
108 | #define SERR_INTR_RSVDZ_MASK 0xfffc0000 | |
109 | ||
2b34da7e KK |
110 | /* |
111 | * Logical Slot Register definitions | |
112 | */ | |
113 | #define SLOT_REG(i) (SLOT1 + (4 * i)) | |
114 | ||
5858759c KK |
115 | #define SLOT_STATE_SHIFT (0) |
116 | #define SLOT_STATE_MASK (3 << 0) | |
117 | #define SLOT_STATE_PWRONLY (1) | |
118 | #define SLOT_STATE_ENABLED (2) | |
119 | #define SLOT_STATE_DISABLED (3) | |
120 | #define PWR_LED_STATE_SHIFT (2) | |
121 | #define PWR_LED_STATE_MASK (3 << 2) | |
122 | #define ATN_LED_STATE_SHIFT (4) | |
123 | #define ATN_LED_STATE_MASK (3 << 4) | |
124 | #define ATN_LED_STATE_ON (1) | |
125 | #define ATN_LED_STATE_BLINK (2) | |
126 | #define ATN_LED_STATE_OFF (3) | |
127 | #define POWER_FAULT (1 << 6) | |
128 | #define ATN_BUTTON (1 << 7) | |
129 | #define MRL_SENSOR (1 << 8) | |
130 | #define MHZ66_CAP (1 << 9) | |
131 | #define PRSNT_SHIFT (10) | |
132 | #define PRSNT_MASK (3 << 10) | |
133 | #define PCIX_CAP_SHIFT (12) | |
134 | #define PCIX_CAP_MASK_PI1 (3 << 12) | |
135 | #define PCIX_CAP_MASK_PI2 (7 << 12) | |
136 | #define PRSNT_CHANGE_DETECTED (1 << 16) | |
137 | #define ISO_PFAULT_DETECTED (1 << 17) | |
138 | #define BUTTON_PRESS_DETECTED (1 << 18) | |
139 | #define MRL_CHANGE_DETECTED (1 << 19) | |
140 | #define CON_PFAULT_DETECTED (1 << 20) | |
141 | #define PRSNT_CHANGE_INTR_MASK (1 << 24) | |
142 | #define ISO_PFAULT_INTR_MASK (1 << 25) | |
143 | #define BUTTON_PRESS_INTR_MASK (1 << 26) | |
144 | #define MRL_CHANGE_INTR_MASK (1 << 27) | |
145 | #define CON_PFAULT_INTR_MASK (1 << 28) | |
146 | #define MRL_CHANGE_SERR_MASK (1 << 29) | |
147 | #define CON_PFAULT_SERR_MASK (1 << 30) | |
148 | #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) | |
1da177e4 | 149 | |
4085399d KK |
150 | /* |
151 | * SHPC Command Code definitnions | |
152 | * | |
153 | * Slot Operation 00h - 3Fh | |
154 | * Set Bus Segment Speed/Mode A 40h - 47h | |
155 | * Power-Only All Slots 48h | |
156 | * Enable All Slots 49h | |
157 | * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh | |
158 | * Reserved Command Codes 60h - BFh | |
159 | * Vendor Specific Commands C0h - FFh | |
160 | */ | |
161 | #define SET_SLOT_PWR 0x01 /* Slot Operation */ | |
162 | #define SET_SLOT_ENABLE 0x02 | |
163 | #define SET_SLOT_DISABLE 0x03 | |
164 | #define SET_PWR_ON 0x04 | |
165 | #define SET_PWR_BLINK 0x08 | |
166 | #define SET_PWR_OFF 0x0c | |
167 | #define SET_ATTN_ON 0x10 | |
168 | #define SET_ATTN_BLINK 0x20 | |
169 | #define SET_ATTN_OFF 0x30 | |
170 | #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */ | |
1da177e4 LT |
171 | #define SETA_PCI_66MHZ 0x41 |
172 | #define SETA_PCIX_66MHZ 0x42 | |
173 | #define SETA_PCIX_100MHZ 0x43 | |
174 | #define SETA_PCIX_133MHZ 0x44 | |
4085399d KK |
175 | #define SETA_RESERVED1 0x45 |
176 | #define SETA_RESERVED2 0x46 | |
177 | #define SETA_RESERVED3 0x47 | |
178 | #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */ | |
179 | #define SET_ENABLE_ALL 0x49 /* Enable All Slots */ | |
180 | #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */ | |
1da177e4 LT |
181 | #define SETB_PCI_66MHZ 0x51 |
182 | #define SETB_PCIX_66MHZ_PM 0x52 | |
183 | #define SETB_PCIX_100MHZ_PM 0x53 | |
184 | #define SETB_PCIX_133MHZ_PM 0x54 | |
185 | #define SETB_PCIX_66MHZ_EM 0x55 | |
186 | #define SETB_PCIX_100MHZ_EM 0x56 | |
187 | #define SETB_PCIX_133MHZ_EM 0x57 | |
188 | #define SETB_PCIX_66MHZ_266 0x58 | |
189 | #define SETB_PCIX_100MHZ_266 0x59 | |
190 | #define SETB_PCIX_133MHZ_266 0x5a | |
191 | #define SETB_PCIX_66MHZ_533 0x5b | |
192 | #define SETB_PCIX_100MHZ_533 0x5c | |
193 | #define SETB_PCIX_133MHZ_533 0x5d | |
4085399d KK |
194 | #define SETB_RESERVED1 0x5e |
195 | #define SETB_RESERVED2 0x5f | |
1da177e4 | 196 | |
4085399d KK |
197 | /* |
198 | * SHPC controller command error code | |
199 | */ | |
1da177e4 LT |
200 | #define SWITCH_OPEN 0x1 |
201 | #define INVALID_CMD 0x2 | |
202 | #define INVALID_SPEED_MODE 0x4 | |
203 | ||
4085399d KK |
204 | /* |
205 | * For accessing SHPC Working Register Set via PCI Configuration Space | |
206 | */ | |
1da177e4 LT |
207 | #define DWORD_SELECT 0x2 |
208 | #define DWORD_DATA 0x4 | |
1da177e4 LT |
209 | |
210 | /* Field Offset in Logical Slot Register - byte boundary */ | |
211 | #define SLOT_EVENT_LATCH 0x2 | |
212 | #define SLOT_SERR_INT_MASK 0x3 | |
213 | ||
1da177e4 LT |
214 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ |
215 | static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ | |
216 | static int ctlr_seq_num = 0; /* Controller sequenc # */ | |
217 | static spinlock_t list_lock; | |
218 | ||
82d5f4aa KK |
219 | static atomic_t shpchp_num_controllers = ATOMIC_INIT(0); |
220 | ||
7d12e780 | 221 | static irqreturn_t shpc_isr(int irq, void *dev_id); |
f4263957 | 222 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec); |
d29aadda | 223 | static int hpc_check_cmd_status(struct controller *ctrl); |
1da177e4 | 224 | |
75d97c59 KK |
225 | static inline u8 shpc_readb(struct controller *ctrl, int reg) |
226 | { | |
227 | return readb(ctrl->hpc_ctlr_handle->creg + reg); | |
228 | } | |
229 | ||
230 | static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) | |
231 | { | |
232 | writeb(val, ctrl->hpc_ctlr_handle->creg + reg); | |
233 | } | |
234 | ||
235 | static inline u16 shpc_readw(struct controller *ctrl, int reg) | |
236 | { | |
237 | return readw(ctrl->hpc_ctlr_handle->creg + reg); | |
238 | } | |
239 | ||
240 | static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) | |
241 | { | |
242 | writew(val, ctrl->hpc_ctlr_handle->creg + reg); | |
243 | } | |
244 | ||
245 | static inline u32 shpc_readl(struct controller *ctrl, int reg) | |
246 | { | |
247 | return readl(ctrl->hpc_ctlr_handle->creg + reg); | |
248 | } | |
249 | ||
250 | static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) | |
251 | { | |
252 | writel(val, ctrl->hpc_ctlr_handle->creg + reg); | |
253 | } | |
254 | ||
255 | static inline int shpc_indirect_read(struct controller *ctrl, int index, | |
256 | u32 *value) | |
257 | { | |
258 | int rc; | |
259 | u32 cap_offset = ctrl->cap_offset; | |
260 | struct pci_dev *pdev = ctrl->pci_dev; | |
261 | ||
262 | rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); | |
263 | if (rc) | |
264 | return rc; | |
265 | return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); | |
266 | } | |
267 | ||
f4263957 KK |
268 | /* |
269 | * This is the interrupt polling timeout function. | |
270 | */ | |
1da177e4 LT |
271 | static void int_poll_timeout(unsigned long lphp_ctlr) |
272 | { | |
f4263957 KK |
273 | struct php_ctlr_state_s *php_ctlr = |
274 | (struct php_ctlr_state_s *)lphp_ctlr; | |
1da177e4 | 275 | |
f4263957 | 276 | DBG_ENTER_ROUTINE |
1da177e4 | 277 | |
f4263957 | 278 | /* Poll for interrupt events. regs == NULL => polling */ |
7d12e780 | 279 | shpc_isr(0, php_ctlr->callback_instance_id); |
1da177e4 | 280 | |
f4263957 | 281 | init_timer(&php_ctlr->int_poll_timer); |
1da177e4 | 282 | if (!shpchp_poll_time) |
f4263957 KK |
283 | shpchp_poll_time = 2; /* default polling interval is 2 sec */ |
284 | ||
285 | start_int_poll_timer(php_ctlr, shpchp_poll_time); | |
1da177e4 | 286 | |
f4263957 | 287 | DBG_LEAVE_ROUTINE |
1da177e4 LT |
288 | } |
289 | ||
f4263957 KK |
290 | /* |
291 | * This function starts the interrupt polling timer. | |
292 | */ | |
293 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec) | |
1da177e4 | 294 | { |
f4263957 KK |
295 | /* Clamp to sane value */ |
296 | if ((sec <= 0) || (sec > 60)) | |
297 | sec = 2; | |
298 | ||
299 | php_ctlr->int_poll_timer.function = &int_poll_timeout; | |
300 | php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; | |
301 | php_ctlr->int_poll_timer.expires = jiffies + sec * HZ; | |
302 | add_timer(&php_ctlr->int_poll_timer); | |
1da177e4 LT |
303 | } |
304 | ||
b4a1efff KK |
305 | /* |
306 | * Returns 1 if SHPC finishes executing a command within 1 sec, | |
307 | * otherwise returns 0. | |
308 | */ | |
309 | static inline int shpc_poll_ctrl_busy(struct controller *ctrl) | |
310 | { | |
311 | int i; | |
312 | u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); | |
313 | ||
314 | if (!(cmd_status & 0x1)) | |
315 | return 1; | |
316 | ||
317 | /* Check every 0.1 sec for a total of 1 sec */ | |
318 | for (i = 0; i < 10; i++) { | |
319 | msleep(100); | |
320 | cmd_status = shpc_readw(ctrl, CMD_STATUS); | |
321 | if (!(cmd_status & 0x1)) | |
322 | return 1; | |
323 | } | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
bd62e271 KK |
328 | static inline int shpc_wait_cmd(struct controller *ctrl) |
329 | { | |
330 | int retval = 0; | |
b4a1efff KK |
331 | unsigned long timeout = msecs_to_jiffies(1000); |
332 | int rc; | |
333 | ||
334 | if (shpchp_poll_mode) | |
335 | rc = shpc_poll_ctrl_busy(ctrl); | |
336 | else | |
337 | rc = wait_event_interruptible_timeout(ctrl->queue, | |
338 | !ctrl->cmd_busy, timeout); | |
bd62e271 KK |
339 | if (!rc) { |
340 | retval = -EIO; | |
b4a1efff | 341 | err("Command not completed in 1000 msec\n"); |
bd62e271 KK |
342 | } else if (rc < 0) { |
343 | retval = -EINTR; | |
344 | info("Command was interrupted by a signal\n"); | |
345 | } | |
346 | ctrl->cmd_busy = 0; | |
347 | ||
348 | return retval; | |
349 | } | |
350 | ||
1da177e4 LT |
351 | static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) |
352 | { | |
75d97c59 | 353 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
354 | u16 cmd_status; |
355 | int retval = 0; | |
356 | u16 temp_word; | |
1da177e4 LT |
357 | |
358 | DBG_ENTER_ROUTINE | |
d29aadda KK |
359 | |
360 | mutex_lock(&slot->ctrl->cmd_lock); | |
361 | ||
b4a1efff | 362 | if (!shpc_poll_ctrl_busy(ctrl)) { |
1da177e4 | 363 | /* After 1 sec and and the controller is still busy */ |
b4a1efff KK |
364 | err("%s : Controller is still busy after 1 sec.\n", |
365 | __FUNCTION__); | |
d29aadda KK |
366 | retval = -EBUSY; |
367 | goto out; | |
1da177e4 LT |
368 | } |
369 | ||
370 | ++t_slot; | |
371 | temp_word = (t_slot << 8) | (cmd & 0xFF); | |
372 | dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd); | |
373 | ||
374 | /* To make sure the Controller Busy bit is 0 before we send out the | |
375 | * command. | |
376 | */ | |
bd62e271 | 377 | slot->ctrl->cmd_busy = 1; |
75d97c59 | 378 | shpc_writew(ctrl, CMD, temp_word); |
1da177e4 | 379 | |
bd62e271 KK |
380 | /* |
381 | * Wait for command completion. | |
382 | */ | |
383 | retval = shpc_wait_cmd(slot->ctrl); | |
d29aadda KK |
384 | if (retval) |
385 | goto out; | |
386 | ||
387 | cmd_status = hpc_check_cmd_status(slot->ctrl); | |
388 | if (cmd_status) { | |
389 | err("%s: Failed to issued command 0x%x (error code = %d)\n", | |
390 | __FUNCTION__, cmd, cmd_status); | |
391 | retval = -EIO; | |
392 | } | |
393 | out: | |
394 | mutex_unlock(&slot->ctrl->cmd_lock); | |
bd62e271 | 395 | |
1da177e4 LT |
396 | DBG_LEAVE_ROUTINE |
397 | return retval; | |
398 | } | |
399 | ||
400 | static int hpc_check_cmd_status(struct controller *ctrl) | |
401 | { | |
1da177e4 LT |
402 | u16 cmd_status; |
403 | int retval = 0; | |
404 | ||
405 | DBG_ENTER_ROUTINE | |
1da177e4 | 406 | |
75d97c59 | 407 | cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; |
1da177e4 LT |
408 | |
409 | switch (cmd_status >> 1) { | |
410 | case 0: | |
411 | retval = 0; | |
412 | break; | |
413 | case 1: | |
414 | retval = SWITCH_OPEN; | |
415 | err("%s: Switch opened!\n", __FUNCTION__); | |
416 | break; | |
417 | case 2: | |
418 | retval = INVALID_CMD; | |
419 | err("%s: Invalid HPC command!\n", __FUNCTION__); | |
420 | break; | |
421 | case 4: | |
422 | retval = INVALID_SPEED_MODE; | |
423 | err("%s: Invalid bus speed/mode!\n", __FUNCTION__); | |
424 | break; | |
425 | default: | |
426 | retval = cmd_status; | |
427 | } | |
428 | ||
429 | DBG_LEAVE_ROUTINE | |
430 | return retval; | |
431 | } | |
432 | ||
433 | ||
434 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
435 | { | |
75d97c59 | 436 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 437 | u32 slot_reg; |
5858759c | 438 | u8 state; |
1da177e4 LT |
439 | |
440 | DBG_ENTER_ROUTINE | |
441 | ||
2b34da7e | 442 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 443 | state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; |
1da177e4 | 444 | |
5858759c KK |
445 | switch (state) { |
446 | case ATN_LED_STATE_ON: | |
1da177e4 LT |
447 | *status = 1; /* On */ |
448 | break; | |
5858759c | 449 | case ATN_LED_STATE_BLINK: |
1da177e4 LT |
450 | *status = 2; /* Blink */ |
451 | break; | |
5858759c | 452 | case ATN_LED_STATE_OFF: |
1da177e4 LT |
453 | *status = 0; /* Off */ |
454 | break; | |
455 | default: | |
5858759c | 456 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
457 | break; |
458 | } | |
459 | ||
460 | DBG_LEAVE_ROUTINE | |
461 | return 0; | |
462 | } | |
463 | ||
464 | static int hpc_get_power_status(struct slot * slot, u8 *status) | |
465 | { | |
75d97c59 | 466 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 467 | u32 slot_reg; |
5858759c | 468 | u8 state; |
1da177e4 LT |
469 | |
470 | DBG_ENTER_ROUTINE | |
471 | ||
2b34da7e | 472 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 473 | state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; |
1da177e4 | 474 | |
5858759c KK |
475 | switch (state) { |
476 | case SLOT_STATE_PWRONLY: | |
1da177e4 LT |
477 | *status = 2; /* Powered only */ |
478 | break; | |
5858759c | 479 | case SLOT_STATE_ENABLED: |
1da177e4 LT |
480 | *status = 1; /* Enabled */ |
481 | break; | |
5858759c | 482 | case SLOT_STATE_DISABLED: |
1da177e4 LT |
483 | *status = 0; /* Disabled */ |
484 | break; | |
485 | default: | |
5858759c | 486 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
487 | break; |
488 | } | |
489 | ||
490 | DBG_LEAVE_ROUTINE | |
5858759c | 491 | return 0; |
1da177e4 LT |
492 | } |
493 | ||
494 | ||
495 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
496 | { | |
75d97c59 | 497 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 498 | u32 slot_reg; |
1da177e4 LT |
499 | |
500 | DBG_ENTER_ROUTINE | |
501 | ||
2b34da7e | 502 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 503 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
1da177e4 LT |
504 | |
505 | DBG_LEAVE_ROUTINE | |
506 | return 0; | |
507 | } | |
508 | ||
509 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
510 | { | |
75d97c59 | 511 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 512 | u32 slot_reg; |
5858759c | 513 | u8 state; |
1da177e4 LT |
514 | |
515 | DBG_ENTER_ROUTINE | |
516 | ||
2b34da7e | 517 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c KK |
518 | state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; |
519 | *status = (state != 0x3) ? 1 : 0; | |
1da177e4 LT |
520 | |
521 | DBG_LEAVE_ROUTINE | |
522 | return 0; | |
523 | } | |
524 | ||
525 | static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) | |
526 | { | |
75d97c59 | 527 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
528 | |
529 | DBG_ENTER_ROUTINE | |
1da177e4 | 530 | |
75d97c59 | 531 | *prog_int = shpc_readb(ctrl, PROG_INTERFACE); |
1da177e4 LT |
532 | |
533 | DBG_LEAVE_ROUTINE | |
534 | return 0; | |
535 | } | |
536 | ||
537 | static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |
538 | { | |
1da177e4 | 539 | int retval = 0; |
75d97c59 | 540 | struct controller *ctrl = slot->ctrl; |
2b34da7e | 541 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 542 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); |
795eb5c4 | 543 | u8 pi, pcix_cap; |
1da177e4 LT |
544 | |
545 | DBG_ENTER_ROUTINE | |
546 | ||
795eb5c4 KK |
547 | if ((retval = hpc_get_prog_int(slot, &pi))) |
548 | return retval; | |
549 | ||
550 | switch (pi) { | |
551 | case 1: | |
552 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; | |
553 | break; | |
554 | case 2: | |
555 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; | |
556 | break; | |
557 | default: | |
558 | return -ENODEV; | |
559 | } | |
560 | ||
0afabe90 KK |
561 | dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", |
562 | __FUNCTION__, slot_reg, pcix_cap, m66_cap); | |
1da177e4 | 563 | |
0afabe90 KK |
564 | switch (pcix_cap) { |
565 | case 0x0: | |
566 | *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; | |
567 | break; | |
568 | case 0x1: | |
569 | *value = PCI_SPEED_66MHz_PCIX; | |
570 | break; | |
571 | case 0x3: | |
572 | *value = PCI_SPEED_133MHz_PCIX; | |
573 | break; | |
574 | case 0x4: | |
575 | *value = PCI_SPEED_133MHz_PCIX_266; | |
576 | break; | |
577 | case 0x5: | |
578 | *value = PCI_SPEED_133MHz_PCIX_533; | |
579 | break; | |
580 | case 0x2: | |
581 | default: | |
582 | *value = PCI_SPEED_UNKNOWN; | |
583 | retval = -ENODEV; | |
584 | break; | |
1da177e4 LT |
585 | } |
586 | ||
587 | dbg("Adapter speed = %d\n", *value); | |
1da177e4 LT |
588 | DBG_LEAVE_ROUTINE |
589 | return retval; | |
590 | } | |
591 | ||
592 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | |
593 | { | |
75d97c59 | 594 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
595 | u16 sec_bus_status; |
596 | u8 pi; | |
597 | int retval = 0; | |
598 | ||
599 | DBG_ENTER_ROUTINE | |
600 | ||
75d97c59 KK |
601 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
602 | sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); | |
1da177e4 LT |
603 | |
604 | if (pi == 2) { | |
87d6c559 | 605 | *mode = (sec_bus_status & 0x0100) >> 8; |
1da177e4 LT |
606 | } else { |
607 | retval = -1; | |
608 | } | |
609 | ||
610 | dbg("Mode 1 ECC cap = %d\n", *mode); | |
611 | ||
612 | DBG_LEAVE_ROUTINE | |
613 | return retval; | |
614 | } | |
615 | ||
616 | static int hpc_query_power_fault(struct slot * slot) | |
617 | { | |
75d97c59 | 618 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 619 | u32 slot_reg; |
1da177e4 LT |
620 | |
621 | DBG_ENTER_ROUTINE | |
622 | ||
2b34da7e | 623 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
1da177e4 LT |
624 | |
625 | DBG_LEAVE_ROUTINE | |
626 | /* Note: Logic 0 => fault */ | |
5858759c | 627 | return !(slot_reg & POWER_FAULT); |
1da177e4 LT |
628 | } |
629 | ||
630 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
631 | { | |
1da177e4 | 632 | u8 slot_cmd = 0; |
1da177e4 LT |
633 | |
634 | switch (value) { | |
635 | case 0 : | |
4085399d | 636 | slot_cmd = SET_ATTN_OFF; /* OFF */ |
1da177e4 LT |
637 | break; |
638 | case 1: | |
4085399d | 639 | slot_cmd = SET_ATTN_ON; /* ON */ |
1da177e4 LT |
640 | break; |
641 | case 2: | |
4085399d | 642 | slot_cmd = SET_ATTN_BLINK; /* BLINK */ |
1da177e4 LT |
643 | break; |
644 | default: | |
645 | return -1; | |
646 | } | |
647 | ||
d4fbf600 | 648 | return shpc_write_cmd(slot, slot->hp_slot, slot_cmd); |
1da177e4 LT |
649 | } |
650 | ||
651 | ||
652 | static void hpc_set_green_led_on(struct slot *slot) | |
653 | { | |
4085399d | 654 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON); |
1da177e4 LT |
655 | } |
656 | ||
657 | static void hpc_set_green_led_off(struct slot *slot) | |
658 | { | |
4085399d | 659 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF); |
1da177e4 LT |
660 | } |
661 | ||
662 | static void hpc_set_green_led_blink(struct slot *slot) | |
663 | { | |
4085399d | 664 | shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK); |
1da177e4 LT |
665 | } |
666 | ||
667 | int shpc_get_ctlr_slot_config(struct controller *ctrl, | |
668 | int *num_ctlr_slots, /* number of slots in this HPC */ | |
669 | int *first_device_num, /* PCI dev num of the first slot in this SHPC */ | |
670 | int *physical_slot_num, /* phy slot num of the first slot in this SHPC */ | |
671 | int *updown, /* physical_slot_num increament: 1 or -1 */ | |
672 | int *flags) | |
673 | { | |
75d97c59 | 674 | u32 slot_config; |
1da177e4 LT |
675 | |
676 | DBG_ENTER_ROUTINE | |
677 | ||
75d97c59 KK |
678 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
679 | *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8; | |
680 | *num_ctlr_slots = slot_config & SLOT_NUM; | |
681 | *physical_slot_num = (slot_config & PSN) >> 16; | |
682 | *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1; | |
1da177e4 | 683 | |
1da177e4 | 684 | dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num); |
1da177e4 LT |
685 | |
686 | DBG_LEAVE_ROUTINE | |
687 | return 0; | |
688 | } | |
689 | ||
690 | static void hpc_release_ctlr(struct controller *ctrl) | |
691 | { | |
ee138334 | 692 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; |
1da177e4 | 693 | struct php_ctlr_state_s *p, *p_prev; |
f7391f53 | 694 | int i; |
d49f2c49 | 695 | u32 slot_reg, serr_int; |
1da177e4 LT |
696 | |
697 | DBG_ENTER_ROUTINE | |
698 | ||
f7391f53 | 699 | /* |
795eb5c4 | 700 | * Mask event interrupts and SERRs of all slots |
f7391f53 | 701 | */ |
795eb5c4 KK |
702 | for (i = 0; i < ctrl->num_slots; i++) { |
703 | slot_reg = shpc_readl(ctrl, SLOT_REG(i)); | |
704 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | | |
705 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
706 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | |
707 | CON_PFAULT_SERR_MASK); | |
708 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
709 | shpc_writel(ctrl, SLOT_REG(i), slot_reg); | |
710 | } | |
f7391f53 KK |
711 | |
712 | cleanup_slots(ctrl); | |
713 | ||
d49f2c49 KK |
714 | /* |
715 | * Mask SERR and System Interrut generation | |
716 | */ | |
717 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
718 | serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | | |
719 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); | |
720 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
721 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
722 | ||
1da177e4 LT |
723 | if (shpchp_poll_mode) { |
724 | del_timer(&php_ctlr->int_poll_timer); | |
725 | } else { | |
726 | if (php_ctlr->irq) { | |
727 | free_irq(php_ctlr->irq, ctrl); | |
728 | php_ctlr->irq = 0; | |
729 | pci_disable_msi(php_ctlr->pci_dev); | |
730 | } | |
731 | } | |
f7391f53 | 732 | |
1da177e4 | 733 | if (php_ctlr->pci_dev) { |
1da177e4 | 734 | iounmap(php_ctlr->creg); |
0455986c | 735 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
1da177e4 LT |
736 | php_ctlr->pci_dev = NULL; |
737 | } | |
738 | ||
739 | spin_lock(&list_lock); | |
740 | p = php_ctlr_list_head; | |
741 | p_prev = NULL; | |
742 | while (p) { | |
743 | if (p == php_ctlr) { | |
744 | if (p_prev) | |
745 | p_prev->pnext = p->pnext; | |
746 | else | |
747 | php_ctlr_list_head = p->pnext; | |
748 | break; | |
749 | } else { | |
750 | p_prev = p; | |
751 | p = p->pnext; | |
752 | } | |
753 | } | |
754 | spin_unlock(&list_lock); | |
755 | ||
756 | kfree(php_ctlr); | |
757 | ||
82d5f4aa KK |
758 | /* |
759 | * If this is the last controller to be released, destroy the | |
760 | * shpchpd work queue | |
761 | */ | |
762 | if (atomic_dec_and_test(&shpchp_num_controllers)) | |
763 | destroy_workqueue(shpchp_wq); | |
764 | ||
1da177e4 LT |
765 | DBG_LEAVE_ROUTINE |
766 | ||
767 | } | |
768 | ||
769 | static int hpc_power_on_slot(struct slot * slot) | |
770 | { | |
d4fbf600 | 771 | int retval; |
1da177e4 LT |
772 | |
773 | DBG_ENTER_ROUTINE | |
774 | ||
4085399d | 775 | retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR); |
1da177e4 LT |
776 | if (retval) { |
777 | err("%s: Write command failed!\n", __FUNCTION__); | |
d4fbf600 | 778 | return retval; |
1da177e4 LT |
779 | } |
780 | ||
781 | DBG_LEAVE_ROUTINE | |
782 | ||
d4fbf600 | 783 | return 0; |
1da177e4 LT |
784 | } |
785 | ||
786 | static int hpc_slot_enable(struct slot * slot) | |
787 | { | |
d4fbf600 | 788 | int retval; |
1da177e4 LT |
789 | |
790 | DBG_ENTER_ROUTINE | |
791 | ||
4085399d KK |
792 | /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ |
793 | retval = shpc_write_cmd(slot, slot->hp_slot, | |
794 | SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF); | |
1da177e4 LT |
795 | if (retval) { |
796 | err("%s: Write command failed!\n", __FUNCTION__); | |
d4fbf600 | 797 | return retval; |
1da177e4 LT |
798 | } |
799 | ||
800 | DBG_LEAVE_ROUTINE | |
d4fbf600 | 801 | return 0; |
1da177e4 LT |
802 | } |
803 | ||
804 | static int hpc_slot_disable(struct slot * slot) | |
805 | { | |
d4fbf600 | 806 | int retval; |
1da177e4 LT |
807 | |
808 | DBG_ENTER_ROUTINE | |
809 | ||
4085399d KK |
810 | /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */ |
811 | retval = shpc_write_cmd(slot, slot->hp_slot, | |
812 | SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON); | |
1da177e4 LT |
813 | if (retval) { |
814 | err("%s: Write command failed!\n", __FUNCTION__); | |
d4fbf600 | 815 | return retval; |
1da177e4 LT |
816 | } |
817 | ||
818 | DBG_LEAVE_ROUTINE | |
d4fbf600 | 819 | return 0; |
1da177e4 LT |
820 | } |
821 | ||
1da177e4 LT |
822 | static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) |
823 | { | |
0afabe90 | 824 | int retval; |
75d97c59 | 825 | struct controller *ctrl = slot->ctrl; |
0afabe90 | 826 | u8 pi, cmd; |
1da177e4 LT |
827 | |
828 | DBG_ENTER_ROUTINE | |
1da177e4 | 829 | |
75d97c59 | 830 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
0afabe90 KK |
831 | if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) |
832 | return -EINVAL; | |
1da177e4 | 833 | |
0afabe90 KK |
834 | switch (value) { |
835 | case PCI_SPEED_33MHz: | |
836 | cmd = SETA_PCI_33MHZ; | |
837 | break; | |
838 | case PCI_SPEED_66MHz: | |
839 | cmd = SETA_PCI_66MHZ; | |
840 | break; | |
841 | case PCI_SPEED_66MHz_PCIX: | |
842 | cmd = SETA_PCIX_66MHZ; | |
843 | break; | |
844 | case PCI_SPEED_100MHz_PCIX: | |
845 | cmd = SETA_PCIX_100MHZ; | |
846 | break; | |
847 | case PCI_SPEED_133MHz_PCIX: | |
848 | cmd = SETA_PCIX_133MHZ; | |
849 | break; | |
850 | case PCI_SPEED_66MHz_PCIX_ECC: | |
851 | cmd = SETB_PCIX_66MHZ_EM; | |
852 | break; | |
853 | case PCI_SPEED_100MHz_PCIX_ECC: | |
854 | cmd = SETB_PCIX_100MHZ_EM; | |
855 | break; | |
856 | case PCI_SPEED_133MHz_PCIX_ECC: | |
857 | cmd = SETB_PCIX_133MHZ_EM; | |
858 | break; | |
859 | case PCI_SPEED_66MHz_PCIX_266: | |
860 | cmd = SETB_PCIX_66MHZ_266; | |
861 | break; | |
862 | case PCI_SPEED_100MHz_PCIX_266: | |
863 | cmd = SETB_PCIX_100MHZ_266; | |
864 | break; | |
865 | case PCI_SPEED_133MHz_PCIX_266: | |
866 | cmd = SETB_PCIX_133MHZ_266; | |
867 | break; | |
868 | case PCI_SPEED_66MHz_PCIX_533: | |
869 | cmd = SETB_PCIX_66MHZ_533; | |
870 | break; | |
871 | case PCI_SPEED_100MHz_PCIX_533: | |
872 | cmd = SETB_PCIX_100MHZ_533; | |
873 | break; | |
874 | case PCI_SPEED_133MHz_PCIX_533: | |
875 | cmd = SETB_PCIX_133MHZ_533; | |
876 | break; | |
877 | default: | |
878 | return -EINVAL; | |
1da177e4 | 879 | } |
0afabe90 KK |
880 | |
881 | retval = shpc_write_cmd(slot, 0, cmd); | |
882 | if (retval) | |
1da177e4 | 883 | err("%s: Write command failed!\n", __FUNCTION__); |
1da177e4 LT |
884 | |
885 | DBG_LEAVE_ROUTINE | |
886 | return retval; | |
887 | } | |
888 | ||
7d12e780 | 889 | static irqreturn_t shpc_isr(int irq, void *dev_id) |
1da177e4 | 890 | { |
c4cecc19 KK |
891 | struct controller *ctrl = (struct controller *)dev_id; |
892 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; | |
893 | u32 serr_int, slot_reg, intr_loc, intr_loc2; | |
1da177e4 LT |
894 | int hp_slot; |
895 | ||
1da177e4 | 896 | /* Check to see if it was our interrupt */ |
75d97c59 | 897 | intr_loc = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
898 | if (!intr_loc) |
899 | return IRQ_NONE; | |
c4cecc19 | 900 | |
1da177e4 LT |
901 | dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); |
902 | ||
903 | if(!shpchp_poll_mode) { | |
c4cecc19 KK |
904 | /* |
905 | * Mask Global Interrupt Mask - see implementation | |
906 | * note on p. 139 of SHPC spec rev 1.0 | |
907 | */ | |
908 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
909 | serr_int |= GLOBAL_INTR_MASK; | |
910 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
911 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
1da177e4 | 912 | |
75d97c59 | 913 | intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
914 | dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); |
915 | } | |
916 | ||
c4cecc19 | 917 | if (intr_loc & CMD_INTR_PENDING) { |
1da177e4 LT |
918 | /* |
919 | * Command Complete Interrupt Pending | |
f467f618 | 920 | * RO only - clear by writing 1 to the Command Completion |
1da177e4 LT |
921 | * Detect bit in Controller SERR-INT register |
922 | */ | |
c4cecc19 KK |
923 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
924 | serr_int &= ~SERR_INTR_RSVDZ_MASK; | |
925 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
926 | ||
bd62e271 | 927 | ctrl->cmd_busy = 0; |
1da177e4 LT |
928 | wake_up_interruptible(&ctrl->queue); |
929 | } | |
930 | ||
c4cecc19 | 931 | if (!(intr_loc & ~CMD_INTR_PENDING)) |
e4e73041 | 932 | goto out; |
1da177e4 LT |
933 | |
934 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { | |
c4cecc19 KK |
935 | /* To find out which slot has interrupt pending */ |
936 | if (!(intr_loc & SLOT_INTR_PENDING(hp_slot))) | |
937 | continue; | |
938 | ||
939 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); | |
940 | dbg("%s: Slot %x with intr, slot register = %x\n", | |
941 | __FUNCTION__, hp_slot, slot_reg); | |
942 | ||
943 | if (slot_reg & MRL_CHANGE_DETECTED) | |
944 | php_ctlr->switch_change_callback( | |
945 | hp_slot, php_ctlr->callback_instance_id); | |
946 | ||
947 | if (slot_reg & BUTTON_PRESS_DETECTED) | |
948 | php_ctlr->attention_button_callback( | |
949 | hp_slot, php_ctlr->callback_instance_id); | |
950 | ||
951 | if (slot_reg & PRSNT_CHANGE_DETECTED) | |
952 | php_ctlr->presence_change_callback( | |
953 | hp_slot , php_ctlr->callback_instance_id); | |
954 | ||
955 | if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)) | |
956 | php_ctlr->power_fault_callback( | |
957 | hp_slot, php_ctlr->callback_instance_id); | |
958 | ||
959 | /* Clear all slot events */ | |
960 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
961 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 | 962 | } |
e4e73041 | 963 | out: |
1da177e4 LT |
964 | if (!shpchp_poll_mode) { |
965 | /* Unmask Global Interrupt Mask */ | |
c4cecc19 KK |
966 | serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); |
967 | serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); | |
968 | shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); | |
1da177e4 LT |
969 | } |
970 | ||
971 | return IRQ_HANDLED; | |
972 | } | |
973 | ||
974 | static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |
975 | { | |
0afabe90 | 976 | int retval = 0; |
75d97c59 | 977 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 978 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
979 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
980 | u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); | |
981 | u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); | |
1da177e4 LT |
982 | |
983 | DBG_ENTER_ROUTINE | |
984 | ||
1da177e4 | 985 | if (pi == 2) { |
6558b6ab | 986 | if (slot_avail2 & SLOT_133MHZ_PCIX_533) |
0afabe90 | 987 | bus_speed = PCI_SPEED_133MHz_PCIX_533; |
6558b6ab | 988 | else if (slot_avail2 & SLOT_100MHZ_PCIX_533) |
0afabe90 | 989 | bus_speed = PCI_SPEED_100MHz_PCIX_533; |
6558b6ab | 990 | else if (slot_avail2 & SLOT_66MHZ_PCIX_533) |
0afabe90 | 991 | bus_speed = PCI_SPEED_66MHz_PCIX_533; |
6558b6ab | 992 | else if (slot_avail2 & SLOT_133MHZ_PCIX_266) |
0afabe90 | 993 | bus_speed = PCI_SPEED_133MHz_PCIX_266; |
6558b6ab | 994 | else if (slot_avail2 & SLOT_100MHZ_PCIX_266) |
0afabe90 | 995 | bus_speed = PCI_SPEED_100MHz_PCIX_266; |
6558b6ab | 996 | else if (slot_avail2 & SLOT_66MHZ_PCIX_266) |
0afabe90 KK |
997 | bus_speed = PCI_SPEED_66MHz_PCIX_266; |
998 | } | |
999 | ||
1000 | if (bus_speed == PCI_SPEED_UNKNOWN) { | |
6558b6ab | 1001 | if (slot_avail1 & SLOT_133MHZ_PCIX) |
0afabe90 | 1002 | bus_speed = PCI_SPEED_133MHz_PCIX; |
6558b6ab | 1003 | else if (slot_avail1 & SLOT_100MHZ_PCIX) |
0afabe90 | 1004 | bus_speed = PCI_SPEED_100MHz_PCIX; |
6558b6ab | 1005 | else if (slot_avail1 & SLOT_66MHZ_PCIX) |
0afabe90 | 1006 | bus_speed = PCI_SPEED_66MHz_PCIX; |
6558b6ab | 1007 | else if (slot_avail2 & SLOT_66MHZ) |
0afabe90 | 1008 | bus_speed = PCI_SPEED_66MHz; |
6558b6ab | 1009 | else if (slot_avail1 & SLOT_33MHZ) |
0afabe90 KK |
1010 | bus_speed = PCI_SPEED_33MHz; |
1011 | else | |
1012 | retval = -ENODEV; | |
1da177e4 LT |
1013 | } |
1014 | ||
1015 | *value = bus_speed; | |
1016 | dbg("Max bus speed = %d\n", bus_speed); | |
1017 | DBG_LEAVE_ROUTINE | |
1018 | return retval; | |
1019 | } | |
1020 | ||
1021 | static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |
1022 | { | |
0afabe90 | 1023 | int retval = 0; |
75d97c59 | 1024 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 1025 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
1026 | u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); |
1027 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | |
0afabe90 | 1028 | u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); |
1da177e4 LT |
1029 | |
1030 | DBG_ENTER_ROUTINE | |
1031 | ||
0afabe90 KK |
1032 | if ((pi == 1) && (speed_mode > 4)) { |
1033 | *value = PCI_SPEED_UNKNOWN; | |
1034 | return -ENODEV; | |
1da177e4 LT |
1035 | } |
1036 | ||
0afabe90 KK |
1037 | switch (speed_mode) { |
1038 | case 0x0: | |
1039 | *value = PCI_SPEED_33MHz; | |
1040 | break; | |
1041 | case 0x1: | |
1042 | *value = PCI_SPEED_66MHz; | |
1043 | break; | |
1044 | case 0x2: | |
1045 | *value = PCI_SPEED_66MHz_PCIX; | |
1046 | break; | |
1047 | case 0x3: | |
1048 | *value = PCI_SPEED_100MHz_PCIX; | |
1049 | break; | |
1050 | case 0x4: | |
1051 | *value = PCI_SPEED_133MHz_PCIX; | |
1052 | break; | |
1053 | case 0x5: | |
1054 | *value = PCI_SPEED_66MHz_PCIX_ECC; | |
1055 | break; | |
1056 | case 0x6: | |
1057 | *value = PCI_SPEED_100MHz_PCIX_ECC; | |
1058 | break; | |
1059 | case 0x7: | |
1060 | *value = PCI_SPEED_133MHz_PCIX_ECC; | |
1061 | break; | |
1062 | case 0x8: | |
1063 | *value = PCI_SPEED_66MHz_PCIX_266; | |
1064 | break; | |
1065 | case 0x9: | |
1066 | *value = PCI_SPEED_100MHz_PCIX_266; | |
1067 | break; | |
1068 | case 0xa: | |
1069 | *value = PCI_SPEED_133MHz_PCIX_266; | |
1070 | break; | |
1071 | case 0xb: | |
1072 | *value = PCI_SPEED_66MHz_PCIX_533; | |
1073 | break; | |
1074 | case 0xc: | |
1075 | *value = PCI_SPEED_100MHz_PCIX_533; | |
1076 | break; | |
1077 | case 0xd: | |
1078 | *value = PCI_SPEED_133MHz_PCIX_533; | |
1079 | break; | |
1080 | default: | |
1081 | *value = PCI_SPEED_UNKNOWN; | |
1082 | retval = -ENODEV; | |
1083 | break; | |
1da177e4 LT |
1084 | } |
1085 | ||
1da177e4 LT |
1086 | dbg("Current bus speed = %d\n", bus_speed); |
1087 | DBG_LEAVE_ROUTINE | |
1088 | return retval; | |
1089 | } | |
1090 | ||
1091 | static struct hpc_ops shpchp_hpc_ops = { | |
1092 | .power_on_slot = hpc_power_on_slot, | |
1093 | .slot_enable = hpc_slot_enable, | |
1094 | .slot_disable = hpc_slot_disable, | |
1da177e4 LT |
1095 | .set_bus_speed_mode = hpc_set_bus_speed_mode, |
1096 | .set_attention_status = hpc_set_attention_status, | |
1097 | .get_power_status = hpc_get_power_status, | |
1098 | .get_attention_status = hpc_get_attention_status, | |
1099 | .get_latch_status = hpc_get_latch_status, | |
1100 | .get_adapter_status = hpc_get_adapter_status, | |
1101 | ||
1102 | .get_max_bus_speed = hpc_get_max_bus_speed, | |
1103 | .get_cur_bus_speed = hpc_get_cur_bus_speed, | |
1104 | .get_adapter_speed = hpc_get_adapter_speed, | |
1105 | .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, | |
1106 | .get_prog_int = hpc_get_prog_int, | |
1107 | ||
1108 | .query_power_fault = hpc_query_power_fault, | |
1109 | .green_led_on = hpc_set_green_led_on, | |
1110 | .green_led_off = hpc_set_green_led_off, | |
1111 | .green_led_blink = hpc_set_green_led_blink, | |
1112 | ||
1113 | .release_ctlr = hpc_release_ctlr, | |
1da177e4 LT |
1114 | }; |
1115 | ||
ee138334 | 1116 | int shpc_init(struct controller * ctrl, struct pci_dev * pdev) |
1da177e4 LT |
1117 | { |
1118 | struct php_ctlr_state_s *php_ctlr, *p; | |
1119 | void *instance_id = ctrl; | |
0455986c | 1120 | int rc, num_slots = 0; |
1da177e4 | 1121 | u8 hp_slot; |
0455986c | 1122 | u32 shpc_base_offset; |
75d97c59 | 1123 | u32 tempdword, slot_reg, slot_config; |
1da177e4 LT |
1124 | u8 i; |
1125 | ||
1126 | DBG_ENTER_ROUTINE | |
1127 | ||
0455986c KK |
1128 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
1129 | ||
1da177e4 | 1130 | spin_lock_init(&list_lock); |
57c95c0d | 1131 | php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL); |
1da177e4 LT |
1132 | |
1133 | if (!php_ctlr) { /* allocate controller state data */ | |
1134 | err("%s: HPC controller memory allocation error!\n", __FUNCTION__); | |
1135 | goto abort; | |
1136 | } | |
1137 | ||
1da177e4 LT |
1138 | php_ctlr->pci_dev = pdev; /* save pci_dev in context */ |
1139 | ||
ee138334 RS |
1140 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == |
1141 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { | |
0455986c KK |
1142 | /* amd shpc driver doesn't use Base Offset; assume 0 */ |
1143 | ctrl->mmio_base = pci_resource_start(pdev, 0); | |
1144 | ctrl->mmio_size = pci_resource_len(pdev, 0); | |
1da177e4 | 1145 | } else { |
0455986c KK |
1146 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
1147 | if (!ctrl->cap_offset) { | |
1148 | err("%s : cap_offset == 0\n", __FUNCTION__); | |
1da177e4 LT |
1149 | goto abort_free_ctlr; |
1150 | } | |
0455986c KK |
1151 | dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); |
1152 | ||
75d97c59 | 1153 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
1da177e4 | 1154 | if (rc) { |
0455986c | 1155 | err("%s: cannot read base_offset\n", __FUNCTION__); |
1da177e4 LT |
1156 | goto abort_free_ctlr; |
1157 | } | |
0455986c | 1158 | |
75d97c59 | 1159 | rc = shpc_indirect_read(ctrl, 3, &tempdword); |
1da177e4 | 1160 | if (rc) { |
0455986c | 1161 | err("%s: cannot read slot config\n", __FUNCTION__); |
1da177e4 LT |
1162 | goto abort_free_ctlr; |
1163 | } | |
0455986c KK |
1164 | num_slots = tempdword & SLOT_NUM; |
1165 | dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); | |
1da177e4 | 1166 | |
0455986c | 1167 | for (i = 0; i < 9 + num_slots; i++) { |
75d97c59 | 1168 | rc = shpc_indirect_read(ctrl, i, &tempdword); |
1da177e4 | 1169 | if (rc) { |
0455986c KK |
1170 | err("%s: cannot read creg (index = %d)\n", |
1171 | __FUNCTION__, i); | |
1da177e4 LT |
1172 | goto abort_free_ctlr; |
1173 | } | |
7c8942f9 RS |
1174 | dbg("%s: offset %d: value %x\n", __FUNCTION__,i, |
1175 | tempdword); | |
1da177e4 | 1176 | } |
0455986c KK |
1177 | |
1178 | ctrl->mmio_base = | |
1179 | pci_resource_start(pdev, 0) + shpc_base_offset; | |
1180 | ctrl->mmio_size = 0x24 + 0x4 * num_slots; | |
1da177e4 LT |
1181 | } |
1182 | ||
1da177e4 LT |
1183 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, |
1184 | pdev->subsystem_device); | |
1185 | ||
1186 | if (pci_enable_device(pdev)) | |
1187 | goto abort_free_ctlr; | |
1188 | ||
0455986c | 1189 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
1da177e4 LT |
1190 | err("%s: cannot reserve MMIO region\n", __FUNCTION__); |
1191 | goto abort_free_ctlr; | |
1192 | } | |
1193 | ||
0455986c | 1194 | php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
1da177e4 | 1195 | if (!php_ctlr->creg) { |
0455986c KK |
1196 | err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, |
1197 | ctrl->mmio_size, ctrl->mmio_base); | |
1198 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | |
1da177e4 LT |
1199 | goto abort_free_ctlr; |
1200 | } | |
1201 | dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); | |
1da177e4 | 1202 | |
6aa4cdd0 | 1203 | mutex_init(&ctrl->crit_sect); |
d29aadda KK |
1204 | mutex_init(&ctrl->cmd_lock); |
1205 | ||
1da177e4 LT |
1206 | /* Setup wait queue */ |
1207 | init_waitqueue_head(&ctrl->queue); | |
1208 | ||
1209 | /* Find the IRQ */ | |
1210 | php_ctlr->irq = pdev->irq; | |
ee138334 RS |
1211 | php_ctlr->attention_button_callback = shpchp_handle_attention_button, |
1212 | php_ctlr->switch_change_callback = shpchp_handle_switch_change; | |
1213 | php_ctlr->presence_change_callback = shpchp_handle_presence_change; | |
1214 | php_ctlr->power_fault_callback = shpchp_handle_power_fault; | |
1da177e4 LT |
1215 | php_ctlr->callback_instance_id = instance_id; |
1216 | ||
75d97c59 KK |
1217 | ctrl->hpc_ctlr_handle = php_ctlr; |
1218 | ctrl->hpc_ops = &shpchp_hpc_ops; | |
1219 | ||
1da177e4 | 1220 | /* Return PCI Controller Info */ |
75d97c59 KK |
1221 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
1222 | php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; | |
1223 | php_ctlr->num_slots = slot_config & SLOT_NUM; | |
1da177e4 LT |
1224 | dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset); |
1225 | dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots); | |
1226 | ||
1227 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ | |
75d97c59 | 1228 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1da177e4 | 1229 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
e7138723 KK |
1230 | tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
1231 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); | |
1232 | tempdword &= ~SERR_INTR_RSVDZ_MASK; | |
75d97c59 KK |
1233 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1234 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
1da177e4 LT |
1235 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1236 | ||
1237 | /* Mask the MRL sensor SERR Mask of individual slot in | |
1238 | * Slot SERR-INT Mask & clear all the existing event if any | |
1239 | */ | |
1240 | for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { | |
2b34da7e | 1241 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1da177e4 LT |
1242 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, |
1243 | hp_slot, slot_reg); | |
795eb5c4 KK |
1244 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1245 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
1246 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | |
1247 | CON_PFAULT_SERR_MASK); | |
1248 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
1249 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 LT |
1250 | } |
1251 | ||
1252 | if (shpchp_poll_mode) {/* Install interrupt polling code */ | |
1253 | /* Install and start the interrupt polling timer */ | |
1254 | init_timer(&php_ctlr->int_poll_timer); | |
1255 | start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ | |
1256 | } else { | |
1257 | /* Installs the interrupt handler */ | |
1258 | rc = pci_enable_msi(pdev); | |
1259 | if (rc) { | |
1260 | info("Can't get msi for the hotplug controller\n"); | |
1261 | info("Use INTx for the hotplug controller\n"); | |
1da177e4 LT |
1262 | } else |
1263 | php_ctlr->irq = pdev->irq; | |
1264 | ||
6b4486e2 | 1265 | rc = request_irq(php_ctlr->irq, shpc_isr, IRQF_SHARED, MY_NAME, (void *) ctrl); |
1da177e4 LT |
1266 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); |
1267 | if (rc) { | |
1268 | err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); | |
1269 | goto abort_free_ctlr; | |
1270 | } | |
1da177e4 | 1271 | } |
7c8942f9 RS |
1272 | dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, |
1273 | pdev->bus->number, PCI_SLOT(pdev->devfn), | |
1274 | PCI_FUNC(pdev->devfn), pdev->irq); | |
424600f9 | 1275 | get_hp_hw_control_from_firmware(pdev); |
1da177e4 LT |
1276 | |
1277 | /* Add this HPC instance into the HPC list */ | |
1278 | spin_lock(&list_lock); | |
1279 | if (php_ctlr_list_head == 0) { | |
1280 | php_ctlr_list_head = php_ctlr; | |
1281 | p = php_ctlr_list_head; | |
1282 | p->pnext = NULL; | |
1283 | } else { | |
1284 | p = php_ctlr_list_head; | |
1285 | ||
1286 | while (p->pnext) | |
1287 | p = p->pnext; | |
1288 | ||
1289 | p->pnext = php_ctlr; | |
1290 | } | |
1291 | spin_unlock(&list_lock); | |
1292 | ||
1da177e4 | 1293 | ctlr_seq_num++; |
1da177e4 | 1294 | |
82d5f4aa KK |
1295 | /* |
1296 | * If this is the first controller to be initialized, | |
1297 | * initialize the shpchpd work queue | |
1298 | */ | |
1299 | if (atomic_add_return(1, &shpchp_num_controllers) == 1) { | |
1300 | shpchp_wq = create_singlethread_workqueue("shpchpd"); | |
1301 | if (!shpchp_wq) | |
1302 | return -ENOMEM; | |
1303 | } | |
1304 | ||
795eb5c4 KK |
1305 | /* |
1306 | * Unmask all event interrupts of all slots | |
1307 | */ | |
1da177e4 | 1308 | for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { |
2b34da7e | 1309 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1da177e4 LT |
1310 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, |
1311 | hp_slot, slot_reg); | |
795eb5c4 KK |
1312 | slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1313 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
1314 | CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); | |
1315 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 LT |
1316 | } |
1317 | if (!shpchp_poll_mode) { | |
1318 | /* Unmask all general input interrupts and SERR */ | |
75d97c59 | 1319 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
e7138723 KK |
1320 | tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | |
1321 | SERR_INTR_RSVDZ_MASK); | |
75d97c59 KK |
1322 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1323 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
1da177e4 LT |
1324 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1325 | } | |
1326 | ||
1da177e4 LT |
1327 | DBG_LEAVE_ROUTINE |
1328 | return 0; | |
1329 | ||
1330 | /* We end up here for the many possible ways to fail this API. */ | |
1331 | abort_free_ctlr: | |
1332 | kfree(php_ctlr); | |
1333 | abort: | |
1334 | DBG_LEAVE_ROUTINE | |
1335 | return -1; | |
1336 | } |