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1da177e4 LT |
1 | /* |
2 | * Standard PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
d4d28dd4 AM |
34 | #include <linux/interrupt.h> |
35 | ||
1da177e4 LT |
36 | #include "shpchp.h" |
37 | ||
38 | #ifdef DEBUG | |
39 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ | |
40 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ | |
41 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ | |
42 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ | |
43 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) | |
44 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) | |
45 | /* Redefine this flagword to set debug level */ | |
46 | #define DEBUG_LEVEL DBG_K_STANDARD | |
47 | ||
48 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; | |
49 | ||
50 | #define DBG_PRINT( dbg_flags, args... ) \ | |
51 | do { \ | |
52 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ | |
53 | { \ | |
54 | int len; \ | |
55 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ | |
56 | __FILE__, __LINE__, __FUNCTION__ ); \ | |
57 | sprintf( __dbg_str_buf + len, args ); \ | |
58 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ | |
59 | } \ | |
60 | } while (0) | |
61 | ||
62 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); | |
63 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); | |
64 | #else | |
65 | #define DEFINE_DBG_BUFFER | |
66 | #define DBG_ENTER_ROUTINE | |
67 | #define DBG_LEAVE_ROUTINE | |
68 | #endif /* DEBUG */ | |
69 | ||
70 | /* Slot Available Register I field definition */ | |
71 | #define SLOT_33MHZ 0x0000001f | |
72 | #define SLOT_66MHZ_PCIX 0x00001f00 | |
73 | #define SLOT_100MHZ_PCIX 0x001f0000 | |
74 | #define SLOT_133MHZ_PCIX 0x1f000000 | |
75 | ||
76 | /* Slot Available Register II field definition */ | |
77 | #define SLOT_66MHZ 0x0000001f | |
78 | #define SLOT_66MHZ_PCIX_266 0x00000f00 | |
79 | #define SLOT_100MHZ_PCIX_266 0x0000f000 | |
80 | #define SLOT_133MHZ_PCIX_266 0x000f0000 | |
81 | #define SLOT_66MHZ_PCIX_533 0x00f00000 | |
82 | #define SLOT_100MHZ_PCIX_533 0x0f000000 | |
83 | #define SLOT_133MHZ_PCIX_533 0xf0000000 | |
84 | ||
1da177e4 LT |
85 | /* Slot Configuration */ |
86 | #define SLOT_NUM 0x0000001F | |
87 | #define FIRST_DEV_NUM 0x00001F00 | |
88 | #define PSN 0x07FF0000 | |
89 | #define UPDOWN 0x20000000 | |
90 | #define MRLSENSOR 0x40000000 | |
91 | #define ATTN_BUTTON 0x80000000 | |
92 | ||
2b34da7e KK |
93 | /* |
94 | * Logical Slot Register definitions | |
95 | */ | |
96 | #define SLOT_REG(i) (SLOT1 + (4 * i)) | |
97 | ||
5858759c KK |
98 | #define SLOT_STATE_SHIFT (0) |
99 | #define SLOT_STATE_MASK (3 << 0) | |
100 | #define SLOT_STATE_PWRONLY (1) | |
101 | #define SLOT_STATE_ENABLED (2) | |
102 | #define SLOT_STATE_DISABLED (3) | |
103 | #define PWR_LED_STATE_SHIFT (2) | |
104 | #define PWR_LED_STATE_MASK (3 << 2) | |
105 | #define ATN_LED_STATE_SHIFT (4) | |
106 | #define ATN_LED_STATE_MASK (3 << 4) | |
107 | #define ATN_LED_STATE_ON (1) | |
108 | #define ATN_LED_STATE_BLINK (2) | |
109 | #define ATN_LED_STATE_OFF (3) | |
110 | #define POWER_FAULT (1 << 6) | |
111 | #define ATN_BUTTON (1 << 7) | |
112 | #define MRL_SENSOR (1 << 8) | |
113 | #define MHZ66_CAP (1 << 9) | |
114 | #define PRSNT_SHIFT (10) | |
115 | #define PRSNT_MASK (3 << 10) | |
116 | #define PCIX_CAP_SHIFT (12) | |
117 | #define PCIX_CAP_MASK_PI1 (3 << 12) | |
118 | #define PCIX_CAP_MASK_PI2 (7 << 12) | |
119 | #define PRSNT_CHANGE_DETECTED (1 << 16) | |
120 | #define ISO_PFAULT_DETECTED (1 << 17) | |
121 | #define BUTTON_PRESS_DETECTED (1 << 18) | |
122 | #define MRL_CHANGE_DETECTED (1 << 19) | |
123 | #define CON_PFAULT_DETECTED (1 << 20) | |
124 | #define PRSNT_CHANGE_INTR_MASK (1 << 24) | |
125 | #define ISO_PFAULT_INTR_MASK (1 << 25) | |
126 | #define BUTTON_PRESS_INTR_MASK (1 << 26) | |
127 | #define MRL_CHANGE_INTR_MASK (1 << 27) | |
128 | #define CON_PFAULT_INTR_MASK (1 << 28) | |
129 | #define MRL_CHANGE_SERR_MASK (1 << 29) | |
130 | #define CON_PFAULT_SERR_MASK (1 << 30) | |
131 | #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) | |
1da177e4 LT |
132 | |
133 | /* SHPC 'write' operations/commands */ | |
134 | ||
135 | /* Slot operation - 0x00h to 0x3Fh */ | |
136 | ||
137 | #define NO_CHANGE 0x00 | |
138 | ||
139 | /* Slot state - Bits 0 & 1 of controller command register */ | |
140 | #define SET_SLOT_PWR 0x01 | |
141 | #define SET_SLOT_ENABLE 0x02 | |
142 | #define SET_SLOT_DISABLE 0x03 | |
143 | ||
144 | /* Power indicator state - Bits 2 & 3 of controller command register*/ | |
145 | #define SET_PWR_ON 0x04 | |
146 | #define SET_PWR_BLINK 0x08 | |
147 | #define SET_PWR_OFF 0x0C | |
148 | ||
149 | /* Attention indicator state - Bits 4 & 5 of controller command register*/ | |
150 | #define SET_ATTN_ON 0x010 | |
151 | #define SET_ATTN_BLINK 0x020 | |
152 | #define SET_ATTN_OFF 0x030 | |
153 | ||
154 | /* Set bus speed/mode A - 0x40h to 0x47h */ | |
155 | #define SETA_PCI_33MHZ 0x40 | |
156 | #define SETA_PCI_66MHZ 0x41 | |
157 | #define SETA_PCIX_66MHZ 0x42 | |
158 | #define SETA_PCIX_100MHZ 0x43 | |
159 | #define SETA_PCIX_133MHZ 0x44 | |
160 | #define RESERV_1 0x45 | |
161 | #define RESERV_2 0x46 | |
162 | #define RESERV_3 0x47 | |
163 | ||
164 | /* Set bus speed/mode B - 0x50h to 0x5fh */ | |
165 | #define SETB_PCI_33MHZ 0x50 | |
166 | #define SETB_PCI_66MHZ 0x51 | |
167 | #define SETB_PCIX_66MHZ_PM 0x52 | |
168 | #define SETB_PCIX_100MHZ_PM 0x53 | |
169 | #define SETB_PCIX_133MHZ_PM 0x54 | |
170 | #define SETB_PCIX_66MHZ_EM 0x55 | |
171 | #define SETB_PCIX_100MHZ_EM 0x56 | |
172 | #define SETB_PCIX_133MHZ_EM 0x57 | |
173 | #define SETB_PCIX_66MHZ_266 0x58 | |
174 | #define SETB_PCIX_100MHZ_266 0x59 | |
175 | #define SETB_PCIX_133MHZ_266 0x5a | |
176 | #define SETB_PCIX_66MHZ_533 0x5b | |
177 | #define SETB_PCIX_100MHZ_533 0x5c | |
178 | #define SETB_PCIX_133MHZ_533 0x5d | |
179 | ||
180 | ||
181 | /* Power-on all slots - 0x48h */ | |
182 | #define SET_PWR_ON_ALL 0x48 | |
183 | ||
184 | /* Enable all slots - 0x49h */ | |
185 | #define SET_ENABLE_ALL 0x49 | |
186 | ||
187 | /* SHPC controller command error code */ | |
188 | #define SWITCH_OPEN 0x1 | |
189 | #define INVALID_CMD 0x2 | |
190 | #define INVALID_SPEED_MODE 0x4 | |
191 | ||
192 | /* For accessing SHPC Working Register Set */ | |
193 | #define DWORD_SELECT 0x2 | |
194 | #define DWORD_DATA 0x4 | |
195 | #define BASE_OFFSET 0x0 | |
196 | ||
197 | /* Field Offset in Logical Slot Register - byte boundary */ | |
198 | #define SLOT_EVENT_LATCH 0x2 | |
199 | #define SLOT_SERR_INT_MASK 0x3 | |
200 | ||
201 | static spinlock_t hpc_event_lock; | |
202 | ||
203 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ | |
204 | static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ | |
205 | static int ctlr_seq_num = 0; /* Controller sequenc # */ | |
206 | static spinlock_t list_lock; | |
207 | ||
208 | static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs); | |
209 | ||
210 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds); | |
d29aadda | 211 | static int hpc_check_cmd_status(struct controller *ctrl); |
1da177e4 | 212 | |
75d97c59 KK |
213 | static inline u8 shpc_readb(struct controller *ctrl, int reg) |
214 | { | |
215 | return readb(ctrl->hpc_ctlr_handle->creg + reg); | |
216 | } | |
217 | ||
218 | static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) | |
219 | { | |
220 | writeb(val, ctrl->hpc_ctlr_handle->creg + reg); | |
221 | } | |
222 | ||
223 | static inline u16 shpc_readw(struct controller *ctrl, int reg) | |
224 | { | |
225 | return readw(ctrl->hpc_ctlr_handle->creg + reg); | |
226 | } | |
227 | ||
228 | static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) | |
229 | { | |
230 | writew(val, ctrl->hpc_ctlr_handle->creg + reg); | |
231 | } | |
232 | ||
233 | static inline u32 shpc_readl(struct controller *ctrl, int reg) | |
234 | { | |
235 | return readl(ctrl->hpc_ctlr_handle->creg + reg); | |
236 | } | |
237 | ||
238 | static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) | |
239 | { | |
240 | writel(val, ctrl->hpc_ctlr_handle->creg + reg); | |
241 | } | |
242 | ||
243 | static inline int shpc_indirect_read(struct controller *ctrl, int index, | |
244 | u32 *value) | |
245 | { | |
246 | int rc; | |
247 | u32 cap_offset = ctrl->cap_offset; | |
248 | struct pci_dev *pdev = ctrl->pci_dev; | |
249 | ||
250 | rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); | |
251 | if (rc) | |
252 | return rc; | |
253 | return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); | |
254 | } | |
255 | ||
1da177e4 LT |
256 | /* This is the interrupt polling timeout function. */ |
257 | static void int_poll_timeout(unsigned long lphp_ctlr) | |
258 | { | |
259 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr; | |
260 | ||
261 | DBG_ENTER_ROUTINE | |
262 | ||
263 | if ( !php_ctlr ) { | |
264 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
265 | return; | |
266 | } | |
267 | ||
268 | /* Poll for interrupt events. regs == NULL => polling */ | |
269 | shpc_isr( 0, (void *)php_ctlr, NULL ); | |
270 | ||
271 | init_timer(&php_ctlr->int_poll_timer); | |
272 | if (!shpchp_poll_time) | |
273 | shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ | |
274 | ||
275 | start_int_poll_timer(php_ctlr, shpchp_poll_time); | |
276 | ||
277 | return; | |
278 | } | |
279 | ||
280 | /* This function starts the interrupt polling timer. */ | |
281 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds) | |
282 | { | |
283 | if (!php_ctlr) { | |
284 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
285 | return; | |
286 | } | |
287 | ||
288 | if ( ( seconds <= 0 ) || ( seconds > 60 ) ) | |
289 | seconds = 2; /* Clamp to sane value */ | |
290 | ||
291 | php_ctlr->int_poll_timer.function = &int_poll_timeout; | |
292 | php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */ | |
293 | php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ; | |
294 | add_timer(&php_ctlr->int_poll_timer); | |
295 | ||
296 | return; | |
297 | } | |
298 | ||
bd62e271 KK |
299 | static inline int shpc_wait_cmd(struct controller *ctrl) |
300 | { | |
301 | int retval = 0; | |
302 | unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000; | |
303 | unsigned long timeout = msecs_to_jiffies(timeout_msec); | |
304 | int rc = wait_event_interruptible_timeout(ctrl->queue, | |
305 | !ctrl->cmd_busy, timeout); | |
306 | if (!rc) { | |
307 | retval = -EIO; | |
308 | err("Command not completed in %d msec\n", timeout_msec); | |
309 | } else if (rc < 0) { | |
310 | retval = -EINTR; | |
311 | info("Command was interrupted by a signal\n"); | |
312 | } | |
313 | ctrl->cmd_busy = 0; | |
314 | ||
315 | return retval; | |
316 | } | |
317 | ||
1da177e4 LT |
318 | static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) |
319 | { | |
ee138334 | 320 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
75d97c59 | 321 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
322 | u16 cmd_status; |
323 | int retval = 0; | |
324 | u16 temp_word; | |
325 | int i; | |
326 | ||
327 | DBG_ENTER_ROUTINE | |
d29aadda KK |
328 | |
329 | mutex_lock(&slot->ctrl->cmd_lock); | |
330 | ||
1da177e4 LT |
331 | if (!php_ctlr) { |
332 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
d29aadda KK |
333 | retval = -EINVAL; |
334 | goto out; | |
1da177e4 LT |
335 | } |
336 | ||
337 | for (i = 0; i < 10; i++) { | |
75d97c59 | 338 | cmd_status = shpc_readw(ctrl, CMD_STATUS); |
1da177e4 LT |
339 | |
340 | if (!(cmd_status & 0x1)) | |
341 | break; | |
342 | /* Check every 0.1 sec for a total of 1 sec*/ | |
343 | msleep(100); | |
344 | } | |
345 | ||
75d97c59 | 346 | cmd_status = shpc_readw(ctrl, CMD_STATUS); |
1da177e4 LT |
347 | |
348 | if (cmd_status & 0x1) { | |
349 | /* After 1 sec and and the controller is still busy */ | |
350 | err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__); | |
d29aadda KK |
351 | retval = -EBUSY; |
352 | goto out; | |
1da177e4 LT |
353 | } |
354 | ||
355 | ++t_slot; | |
356 | temp_word = (t_slot << 8) | (cmd & 0xFF); | |
357 | dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd); | |
358 | ||
359 | /* To make sure the Controller Busy bit is 0 before we send out the | |
360 | * command. | |
361 | */ | |
bd62e271 | 362 | slot->ctrl->cmd_busy = 1; |
75d97c59 | 363 | shpc_writew(ctrl, CMD, temp_word); |
1da177e4 | 364 | |
bd62e271 KK |
365 | /* |
366 | * Wait for command completion. | |
367 | */ | |
368 | retval = shpc_wait_cmd(slot->ctrl); | |
d29aadda KK |
369 | if (retval) |
370 | goto out; | |
371 | ||
372 | cmd_status = hpc_check_cmd_status(slot->ctrl); | |
373 | if (cmd_status) { | |
374 | err("%s: Failed to issued command 0x%x (error code = %d)\n", | |
375 | __FUNCTION__, cmd, cmd_status); | |
376 | retval = -EIO; | |
377 | } | |
378 | out: | |
379 | mutex_unlock(&slot->ctrl->cmd_lock); | |
bd62e271 | 380 | |
1da177e4 LT |
381 | DBG_LEAVE_ROUTINE |
382 | return retval; | |
383 | } | |
384 | ||
385 | static int hpc_check_cmd_status(struct controller *ctrl) | |
386 | { | |
1da177e4 LT |
387 | u16 cmd_status; |
388 | int retval = 0; | |
389 | ||
390 | DBG_ENTER_ROUTINE | |
391 | ||
392 | if (!ctrl->hpc_ctlr_handle) { | |
393 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
394 | return -1; | |
395 | } | |
396 | ||
75d97c59 | 397 | cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; |
1da177e4 LT |
398 | |
399 | switch (cmd_status >> 1) { | |
400 | case 0: | |
401 | retval = 0; | |
402 | break; | |
403 | case 1: | |
404 | retval = SWITCH_OPEN; | |
405 | err("%s: Switch opened!\n", __FUNCTION__); | |
406 | break; | |
407 | case 2: | |
408 | retval = INVALID_CMD; | |
409 | err("%s: Invalid HPC command!\n", __FUNCTION__); | |
410 | break; | |
411 | case 4: | |
412 | retval = INVALID_SPEED_MODE; | |
413 | err("%s: Invalid bus speed/mode!\n", __FUNCTION__); | |
414 | break; | |
415 | default: | |
416 | retval = cmd_status; | |
417 | } | |
418 | ||
419 | DBG_LEAVE_ROUTINE | |
420 | return retval; | |
421 | } | |
422 | ||
423 | ||
424 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
425 | { | |
75d97c59 | 426 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 427 | u32 slot_reg; |
5858759c | 428 | u8 state; |
1da177e4 LT |
429 | |
430 | DBG_ENTER_ROUTINE | |
431 | ||
432 | if (!slot->ctrl->hpc_ctlr_handle) { | |
433 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
434 | return -1; | |
435 | } | |
436 | ||
2b34da7e | 437 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 438 | state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; |
1da177e4 | 439 | |
5858759c KK |
440 | switch (state) { |
441 | case ATN_LED_STATE_ON: | |
1da177e4 LT |
442 | *status = 1; /* On */ |
443 | break; | |
5858759c | 444 | case ATN_LED_STATE_BLINK: |
1da177e4 LT |
445 | *status = 2; /* Blink */ |
446 | break; | |
5858759c | 447 | case ATN_LED_STATE_OFF: |
1da177e4 LT |
448 | *status = 0; /* Off */ |
449 | break; | |
450 | default: | |
5858759c | 451 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
452 | break; |
453 | } | |
454 | ||
455 | DBG_LEAVE_ROUTINE | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static int hpc_get_power_status(struct slot * slot, u8 *status) | |
460 | { | |
75d97c59 | 461 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 462 | u32 slot_reg; |
5858759c | 463 | u8 state; |
1da177e4 LT |
464 | |
465 | DBG_ENTER_ROUTINE | |
466 | ||
467 | if (!slot->ctrl->hpc_ctlr_handle) { | |
468 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
469 | return -1; | |
470 | } | |
471 | ||
2b34da7e | 472 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 473 | state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; |
1da177e4 | 474 | |
5858759c KK |
475 | switch (state) { |
476 | case SLOT_STATE_PWRONLY: | |
1da177e4 LT |
477 | *status = 2; /* Powered only */ |
478 | break; | |
5858759c | 479 | case SLOT_STATE_ENABLED: |
1da177e4 LT |
480 | *status = 1; /* Enabled */ |
481 | break; | |
5858759c | 482 | case SLOT_STATE_DISABLED: |
1da177e4 LT |
483 | *status = 0; /* Disabled */ |
484 | break; | |
485 | default: | |
5858759c | 486 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
487 | break; |
488 | } | |
489 | ||
490 | DBG_LEAVE_ROUTINE | |
5858759c | 491 | return 0; |
1da177e4 LT |
492 | } |
493 | ||
494 | ||
495 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
496 | { | |
75d97c59 | 497 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 498 | u32 slot_reg; |
1da177e4 LT |
499 | |
500 | DBG_ENTER_ROUTINE | |
501 | ||
502 | if (!slot->ctrl->hpc_ctlr_handle) { | |
503 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
504 | return -1; | |
505 | } | |
506 | ||
2b34da7e | 507 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 508 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
1da177e4 LT |
509 | |
510 | DBG_LEAVE_ROUTINE | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
515 | { | |
75d97c59 | 516 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 517 | u32 slot_reg; |
5858759c | 518 | u8 state; |
1da177e4 LT |
519 | |
520 | DBG_ENTER_ROUTINE | |
521 | ||
522 | if (!slot->ctrl->hpc_ctlr_handle) { | |
523 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
524 | return -1; | |
525 | } | |
526 | ||
2b34da7e | 527 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c KK |
528 | state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; |
529 | *status = (state != 0x3) ? 1 : 0; | |
1da177e4 LT |
530 | |
531 | DBG_LEAVE_ROUTINE | |
532 | return 0; | |
533 | } | |
534 | ||
535 | static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) | |
536 | { | |
75d97c59 | 537 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
538 | |
539 | DBG_ENTER_ROUTINE | |
540 | ||
541 | if (!slot->ctrl->hpc_ctlr_handle) { | |
542 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
543 | return -1; | |
544 | } | |
545 | ||
75d97c59 | 546 | *prog_int = shpc_readb(ctrl, PROG_INTERFACE); |
1da177e4 LT |
547 | |
548 | DBG_LEAVE_ROUTINE | |
549 | return 0; | |
550 | } | |
551 | ||
552 | static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |
553 | { | |
1da177e4 | 554 | int retval = 0; |
75d97c59 | 555 | struct controller *ctrl = slot->ctrl; |
2b34da7e | 556 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c KK |
557 | u8 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; |
558 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); | |
1da177e4 LT |
559 | |
560 | DBG_ENTER_ROUTINE | |
561 | ||
0afabe90 KK |
562 | dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", |
563 | __FUNCTION__, slot_reg, pcix_cap, m66_cap); | |
1da177e4 | 564 | |
0afabe90 KK |
565 | switch (pcix_cap) { |
566 | case 0x0: | |
567 | *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; | |
568 | break; | |
569 | case 0x1: | |
570 | *value = PCI_SPEED_66MHz_PCIX; | |
571 | break; | |
572 | case 0x3: | |
573 | *value = PCI_SPEED_133MHz_PCIX; | |
574 | break; | |
575 | case 0x4: | |
576 | *value = PCI_SPEED_133MHz_PCIX_266; | |
577 | break; | |
578 | case 0x5: | |
579 | *value = PCI_SPEED_133MHz_PCIX_533; | |
580 | break; | |
581 | case 0x2: | |
582 | default: | |
583 | *value = PCI_SPEED_UNKNOWN; | |
584 | retval = -ENODEV; | |
585 | break; | |
1da177e4 LT |
586 | } |
587 | ||
588 | dbg("Adapter speed = %d\n", *value); | |
1da177e4 LT |
589 | DBG_LEAVE_ROUTINE |
590 | return retval; | |
591 | } | |
592 | ||
593 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | |
594 | { | |
75d97c59 | 595 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
596 | u16 sec_bus_status; |
597 | u8 pi; | |
598 | int retval = 0; | |
599 | ||
600 | DBG_ENTER_ROUTINE | |
601 | ||
602 | if (!slot->ctrl->hpc_ctlr_handle) { | |
603 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
604 | return -1; | |
605 | } | |
606 | ||
75d97c59 KK |
607 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
608 | sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); | |
1da177e4 LT |
609 | |
610 | if (pi == 2) { | |
87d6c559 | 611 | *mode = (sec_bus_status & 0x0100) >> 8; |
1da177e4 LT |
612 | } else { |
613 | retval = -1; | |
614 | } | |
615 | ||
616 | dbg("Mode 1 ECC cap = %d\n", *mode); | |
617 | ||
618 | DBG_LEAVE_ROUTINE | |
619 | return retval; | |
620 | } | |
621 | ||
622 | static int hpc_query_power_fault(struct slot * slot) | |
623 | { | |
75d97c59 | 624 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 625 | u32 slot_reg; |
1da177e4 LT |
626 | |
627 | DBG_ENTER_ROUTINE | |
628 | ||
629 | if (!slot->ctrl->hpc_ctlr_handle) { | |
630 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
631 | return -1; | |
632 | } | |
633 | ||
2b34da7e | 634 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
1da177e4 LT |
635 | |
636 | DBG_LEAVE_ROUTINE | |
637 | /* Note: Logic 0 => fault */ | |
5858759c | 638 | return !(slot_reg & POWER_FAULT); |
1da177e4 LT |
639 | } |
640 | ||
641 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
642 | { | |
ee138334 | 643 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
644 | u8 slot_cmd = 0; |
645 | int rc = 0; | |
646 | ||
647 | if (!slot->ctrl->hpc_ctlr_handle) { | |
648 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
649 | return -1; | |
650 | } | |
651 | ||
652 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
653 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
654 | return -1; | |
655 | } | |
656 | ||
657 | switch (value) { | |
658 | case 0 : | |
659 | slot_cmd = 0x30; /* OFF */ | |
660 | break; | |
661 | case 1: | |
662 | slot_cmd = 0x10; /* ON */ | |
663 | break; | |
664 | case 2: | |
665 | slot_cmd = 0x20; /* BLINK */ | |
666 | break; | |
667 | default: | |
668 | return -1; | |
669 | } | |
670 | ||
671 | shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
672 | ||
673 | return rc; | |
674 | } | |
675 | ||
676 | ||
677 | static void hpc_set_green_led_on(struct slot *slot) | |
678 | { | |
ee138334 | 679 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
680 | u8 slot_cmd; |
681 | ||
682 | if (!slot->ctrl->hpc_ctlr_handle) { | |
683 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
684 | return ; | |
685 | } | |
686 | ||
687 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
688 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
689 | return ; | |
690 | } | |
691 | ||
692 | slot_cmd = 0x04; | |
693 | ||
694 | shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
695 | ||
696 | return; | |
697 | } | |
698 | ||
699 | static void hpc_set_green_led_off(struct slot *slot) | |
700 | { | |
ee138334 | 701 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
702 | u8 slot_cmd; |
703 | ||
704 | if (!slot->ctrl->hpc_ctlr_handle) { | |
705 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
706 | return ; | |
707 | } | |
708 | ||
709 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
710 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
711 | return ; | |
712 | } | |
713 | ||
714 | slot_cmd = 0x0C; | |
715 | ||
716 | shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
717 | ||
718 | return; | |
719 | } | |
720 | ||
721 | static void hpc_set_green_led_blink(struct slot *slot) | |
722 | { | |
ee138334 | 723 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
724 | u8 slot_cmd; |
725 | ||
726 | if (!slot->ctrl->hpc_ctlr_handle) { | |
727 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
728 | return ; | |
729 | } | |
730 | ||
731 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
732 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
733 | return ; | |
734 | } | |
735 | ||
736 | slot_cmd = 0x08; | |
737 | ||
738 | shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
739 | ||
740 | return; | |
741 | } | |
742 | ||
743 | int shpc_get_ctlr_slot_config(struct controller *ctrl, | |
744 | int *num_ctlr_slots, /* number of slots in this HPC */ | |
745 | int *first_device_num, /* PCI dev num of the first slot in this SHPC */ | |
746 | int *physical_slot_num, /* phy slot num of the first slot in this SHPC */ | |
747 | int *updown, /* physical_slot_num increament: 1 or -1 */ | |
748 | int *flags) | |
749 | { | |
75d97c59 | 750 | u32 slot_config; |
1da177e4 LT |
751 | |
752 | DBG_ENTER_ROUTINE | |
753 | ||
754 | if (!ctrl->hpc_ctlr_handle) { | |
755 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
756 | return -1; | |
757 | } | |
758 | ||
75d97c59 KK |
759 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
760 | *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8; | |
761 | *num_ctlr_slots = slot_config & SLOT_NUM; | |
762 | *physical_slot_num = (slot_config & PSN) >> 16; | |
763 | *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1; | |
1da177e4 | 764 | |
1da177e4 | 765 | dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num); |
1da177e4 LT |
766 | |
767 | DBG_LEAVE_ROUTINE | |
768 | return 0; | |
769 | } | |
770 | ||
771 | static void hpc_release_ctlr(struct controller *ctrl) | |
772 | { | |
ee138334 | 773 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; |
1da177e4 | 774 | struct php_ctlr_state_s *p, *p_prev; |
f7391f53 | 775 | int i; |
1da177e4 LT |
776 | |
777 | DBG_ENTER_ROUTINE | |
778 | ||
779 | if (!ctrl->hpc_ctlr_handle) { | |
780 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
781 | return ; | |
782 | } | |
783 | ||
f7391f53 KK |
784 | /* |
785 | * Mask all slot event interrupts | |
786 | */ | |
787 | for (i = 0; i < ctrl->num_slots; i++) | |
2b34da7e | 788 | shpc_writel(ctrl, SLOT_REG(i), 0xffff3fff); |
f7391f53 KK |
789 | |
790 | cleanup_slots(ctrl); | |
791 | ||
1da177e4 LT |
792 | if (shpchp_poll_mode) { |
793 | del_timer(&php_ctlr->int_poll_timer); | |
794 | } else { | |
795 | if (php_ctlr->irq) { | |
796 | free_irq(php_ctlr->irq, ctrl); | |
797 | php_ctlr->irq = 0; | |
798 | pci_disable_msi(php_ctlr->pci_dev); | |
799 | } | |
800 | } | |
f7391f53 | 801 | |
1da177e4 | 802 | if (php_ctlr->pci_dev) { |
1da177e4 | 803 | iounmap(php_ctlr->creg); |
0455986c | 804 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
1da177e4 LT |
805 | php_ctlr->pci_dev = NULL; |
806 | } | |
807 | ||
808 | spin_lock(&list_lock); | |
809 | p = php_ctlr_list_head; | |
810 | p_prev = NULL; | |
811 | while (p) { | |
812 | if (p == php_ctlr) { | |
813 | if (p_prev) | |
814 | p_prev->pnext = p->pnext; | |
815 | else | |
816 | php_ctlr_list_head = p->pnext; | |
817 | break; | |
818 | } else { | |
819 | p_prev = p; | |
820 | p = p->pnext; | |
821 | } | |
822 | } | |
823 | spin_unlock(&list_lock); | |
824 | ||
825 | kfree(php_ctlr); | |
826 | ||
827 | DBG_LEAVE_ROUTINE | |
828 | ||
829 | } | |
830 | ||
831 | static int hpc_power_on_slot(struct slot * slot) | |
832 | { | |
ee138334 | 833 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
834 | u8 slot_cmd; |
835 | int retval = 0; | |
836 | ||
837 | DBG_ENTER_ROUTINE | |
838 | ||
839 | if (!slot->ctrl->hpc_ctlr_handle) { | |
840 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
841 | return -1; | |
842 | } | |
843 | ||
844 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
845 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
846 | return -1; | |
847 | } | |
848 | slot_cmd = 0x01; | |
849 | ||
850 | retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
851 | ||
852 | if (retval) { | |
853 | err("%s: Write command failed!\n", __FUNCTION__); | |
854 | return -1; | |
855 | } | |
856 | ||
857 | DBG_LEAVE_ROUTINE | |
858 | ||
859 | return retval; | |
860 | } | |
861 | ||
862 | static int hpc_slot_enable(struct slot * slot) | |
863 | { | |
ee138334 | 864 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
865 | u8 slot_cmd; |
866 | int retval = 0; | |
867 | ||
868 | DBG_ENTER_ROUTINE | |
869 | ||
870 | if (!slot->ctrl->hpc_ctlr_handle) { | |
871 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
872 | return -1; | |
873 | } | |
874 | ||
875 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
876 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
877 | return -1; | |
878 | } | |
879 | /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ | |
880 | slot_cmd = 0x3A; | |
881 | ||
882 | retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
883 | ||
884 | if (retval) { | |
885 | err("%s: Write command failed!\n", __FUNCTION__); | |
886 | return -1; | |
887 | } | |
888 | ||
889 | DBG_LEAVE_ROUTINE | |
890 | return retval; | |
891 | } | |
892 | ||
893 | static int hpc_slot_disable(struct slot * slot) | |
894 | { | |
ee138334 | 895 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
896 | u8 slot_cmd; |
897 | int retval = 0; | |
898 | ||
899 | DBG_ENTER_ROUTINE | |
900 | ||
901 | if (!slot->ctrl->hpc_ctlr_handle) { | |
902 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
903 | return -1; | |
904 | } | |
905 | ||
906 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
907 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
908 | return -1; | |
909 | } | |
910 | ||
911 | /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */ | |
912 | slot_cmd = 0x1F; | |
913 | ||
914 | retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
915 | ||
916 | if (retval) { | |
917 | err("%s: Write command failed!\n", __FUNCTION__); | |
918 | return -1; | |
919 | } | |
920 | ||
921 | DBG_LEAVE_ROUTINE | |
922 | return retval; | |
923 | } | |
924 | ||
1da177e4 LT |
925 | static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) |
926 | { | |
0afabe90 | 927 | int retval; |
75d97c59 | 928 | struct controller *ctrl = slot->ctrl; |
0afabe90 | 929 | u8 pi, cmd; |
1da177e4 LT |
930 | |
931 | DBG_ENTER_ROUTINE | |
1da177e4 | 932 | |
75d97c59 | 933 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
0afabe90 KK |
934 | if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) |
935 | return -EINVAL; | |
1da177e4 | 936 | |
0afabe90 KK |
937 | switch (value) { |
938 | case PCI_SPEED_33MHz: | |
939 | cmd = SETA_PCI_33MHZ; | |
940 | break; | |
941 | case PCI_SPEED_66MHz: | |
942 | cmd = SETA_PCI_66MHZ; | |
943 | break; | |
944 | case PCI_SPEED_66MHz_PCIX: | |
945 | cmd = SETA_PCIX_66MHZ; | |
946 | break; | |
947 | case PCI_SPEED_100MHz_PCIX: | |
948 | cmd = SETA_PCIX_100MHZ; | |
949 | break; | |
950 | case PCI_SPEED_133MHz_PCIX: | |
951 | cmd = SETA_PCIX_133MHZ; | |
952 | break; | |
953 | case PCI_SPEED_66MHz_PCIX_ECC: | |
954 | cmd = SETB_PCIX_66MHZ_EM; | |
955 | break; | |
956 | case PCI_SPEED_100MHz_PCIX_ECC: | |
957 | cmd = SETB_PCIX_100MHZ_EM; | |
958 | break; | |
959 | case PCI_SPEED_133MHz_PCIX_ECC: | |
960 | cmd = SETB_PCIX_133MHZ_EM; | |
961 | break; | |
962 | case PCI_SPEED_66MHz_PCIX_266: | |
963 | cmd = SETB_PCIX_66MHZ_266; | |
964 | break; | |
965 | case PCI_SPEED_100MHz_PCIX_266: | |
966 | cmd = SETB_PCIX_100MHZ_266; | |
967 | break; | |
968 | case PCI_SPEED_133MHz_PCIX_266: | |
969 | cmd = SETB_PCIX_133MHZ_266; | |
970 | break; | |
971 | case PCI_SPEED_66MHz_PCIX_533: | |
972 | cmd = SETB_PCIX_66MHZ_533; | |
973 | break; | |
974 | case PCI_SPEED_100MHz_PCIX_533: | |
975 | cmd = SETB_PCIX_100MHZ_533; | |
976 | break; | |
977 | case PCI_SPEED_133MHz_PCIX_533: | |
978 | cmd = SETB_PCIX_133MHZ_533; | |
979 | break; | |
980 | default: | |
981 | return -EINVAL; | |
1da177e4 | 982 | } |
0afabe90 KK |
983 | |
984 | retval = shpc_write_cmd(slot, 0, cmd); | |
985 | if (retval) | |
1da177e4 | 986 | err("%s: Write command failed!\n", __FUNCTION__); |
1da177e4 LT |
987 | |
988 | DBG_LEAVE_ROUTINE | |
989 | return retval; | |
990 | } | |
991 | ||
992 | static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |
993 | { | |
994 | struct controller *ctrl = NULL; | |
995 | struct php_ctlr_state_s *php_ctlr; | |
996 | u8 schedule_flag = 0; | |
1da177e4 LT |
997 | u32 temp_dword, intr_loc, intr_loc2; |
998 | int hp_slot; | |
999 | ||
1000 | if (!dev_id) | |
1001 | return IRQ_NONE; | |
1002 | ||
1003 | if (!shpchp_poll_mode) { | |
1004 | ctrl = (struct controller *)dev_id; | |
1005 | php_ctlr = ctrl->hpc_ctlr_handle; | |
1006 | } else { | |
1007 | php_ctlr = (struct php_ctlr_state_s *) dev_id; | |
1008 | ctrl = (struct controller *)php_ctlr->callback_instance_id; | |
1009 | } | |
1010 | ||
1011 | if (!ctrl) | |
1012 | return IRQ_NONE; | |
1013 | ||
1014 | if (!php_ctlr || !php_ctlr->creg) | |
1015 | return IRQ_NONE; | |
1016 | ||
1017 | /* Check to see if it was our interrupt */ | |
75d97c59 | 1018 | intr_loc = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
1019 | |
1020 | if (!intr_loc) | |
1021 | return IRQ_NONE; | |
1da177e4 LT |
1022 | dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); |
1023 | ||
1024 | if(!shpchp_poll_mode) { | |
1025 | /* Mask Global Interrupt Mask - see implementation note on p. 139 */ | |
1026 | /* of SHPC spec rev 1.0*/ | |
75d97c59 | 1027 | temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1da177e4 | 1028 | temp_dword |= 0x00000001; |
75d97c59 | 1029 | shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword); |
1da177e4 | 1030 | |
75d97c59 | 1031 | intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
1032 | dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); |
1033 | } | |
1034 | ||
1035 | if (intr_loc & 0x0001) { | |
1036 | /* | |
1037 | * Command Complete Interrupt Pending | |
f467f618 | 1038 | * RO only - clear by writing 1 to the Command Completion |
1da177e4 LT |
1039 | * Detect bit in Controller SERR-INT register |
1040 | */ | |
75d97c59 | 1041 | temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
f467f618 | 1042 | temp_dword &= 0xfffdffff; |
75d97c59 | 1043 | shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword); |
bd62e271 | 1044 | ctrl->cmd_busy = 0; |
1da177e4 LT |
1045 | wake_up_interruptible(&ctrl->queue); |
1046 | } | |
1047 | ||
e4e73041 KK |
1048 | if ((intr_loc = (intr_loc >> 1)) == 0) |
1049 | goto out; | |
1da177e4 LT |
1050 | |
1051 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { | |
1052 | /* To find out which slot has interrupt pending */ | |
1053 | if ((intr_loc >> hp_slot) & 0x01) { | |
2b34da7e | 1054 | temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
7c8942f9 RS |
1055 | dbg("%s: Slot %x with intr, slot register = %x\n", |
1056 | __FUNCTION__, hp_slot, temp_dword); | |
5858759c KK |
1057 | if ((php_ctlr->switch_change_callback) && |
1058 | (temp_dword & MRL_CHANGE_DETECTED)) | |
1da177e4 LT |
1059 | schedule_flag += php_ctlr->switch_change_callback( |
1060 | hp_slot, php_ctlr->callback_instance_id); | |
5858759c KK |
1061 | if ((php_ctlr->attention_button_callback) && |
1062 | (temp_dword & BUTTON_PRESS_DETECTED)) | |
1da177e4 LT |
1063 | schedule_flag += php_ctlr->attention_button_callback( |
1064 | hp_slot, php_ctlr->callback_instance_id); | |
5858759c KK |
1065 | if ((php_ctlr->presence_change_callback) && |
1066 | (temp_dword & PRSNT_CHANGE_DETECTED)) | |
1da177e4 LT |
1067 | schedule_flag += php_ctlr->presence_change_callback( |
1068 | hp_slot , php_ctlr->callback_instance_id); | |
5858759c KK |
1069 | if ((php_ctlr->power_fault_callback) && |
1070 | (temp_dword & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))) | |
1da177e4 LT |
1071 | schedule_flag += php_ctlr->power_fault_callback( |
1072 | hp_slot, php_ctlr->callback_instance_id); | |
1073 | ||
1074 | /* Clear all slot events */ | |
1075 | temp_dword = 0xe01f3fff; | |
2b34da7e | 1076 | shpc_writel(ctrl, SLOT_REG(hp_slot), temp_dword); |
1da177e4 | 1077 | |
75d97c59 | 1078 | intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
1079 | dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); |
1080 | } | |
1081 | } | |
e4e73041 | 1082 | out: |
1da177e4 LT |
1083 | if (!shpchp_poll_mode) { |
1084 | /* Unmask Global Interrupt Mask */ | |
75d97c59 | 1085 | temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1da177e4 | 1086 | temp_dword &= 0xfffffffe; |
75d97c59 | 1087 | shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword); |
1da177e4 LT |
1088 | } |
1089 | ||
1090 | return IRQ_HANDLED; | |
1091 | } | |
1092 | ||
1093 | static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |
1094 | { | |
0afabe90 | 1095 | int retval = 0; |
75d97c59 | 1096 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 1097 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
1098 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
1099 | u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); | |
1100 | u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); | |
1da177e4 LT |
1101 | |
1102 | DBG_ENTER_ROUTINE | |
1103 | ||
1da177e4 | 1104 | if (pi == 2) { |
6558b6ab | 1105 | if (slot_avail2 & SLOT_133MHZ_PCIX_533) |
0afabe90 | 1106 | bus_speed = PCI_SPEED_133MHz_PCIX_533; |
6558b6ab | 1107 | else if (slot_avail2 & SLOT_100MHZ_PCIX_533) |
0afabe90 | 1108 | bus_speed = PCI_SPEED_100MHz_PCIX_533; |
6558b6ab | 1109 | else if (slot_avail2 & SLOT_66MHZ_PCIX_533) |
0afabe90 | 1110 | bus_speed = PCI_SPEED_66MHz_PCIX_533; |
6558b6ab | 1111 | else if (slot_avail2 & SLOT_133MHZ_PCIX_266) |
0afabe90 | 1112 | bus_speed = PCI_SPEED_133MHz_PCIX_266; |
6558b6ab | 1113 | else if (slot_avail2 & SLOT_100MHZ_PCIX_266) |
0afabe90 | 1114 | bus_speed = PCI_SPEED_100MHz_PCIX_266; |
6558b6ab | 1115 | else if (slot_avail2 & SLOT_66MHZ_PCIX_266) |
0afabe90 KK |
1116 | bus_speed = PCI_SPEED_66MHz_PCIX_266; |
1117 | } | |
1118 | ||
1119 | if (bus_speed == PCI_SPEED_UNKNOWN) { | |
6558b6ab | 1120 | if (slot_avail1 & SLOT_133MHZ_PCIX) |
0afabe90 | 1121 | bus_speed = PCI_SPEED_133MHz_PCIX; |
6558b6ab | 1122 | else if (slot_avail1 & SLOT_100MHZ_PCIX) |
0afabe90 | 1123 | bus_speed = PCI_SPEED_100MHz_PCIX; |
6558b6ab | 1124 | else if (slot_avail1 & SLOT_66MHZ_PCIX) |
0afabe90 | 1125 | bus_speed = PCI_SPEED_66MHz_PCIX; |
6558b6ab | 1126 | else if (slot_avail2 & SLOT_66MHZ) |
0afabe90 | 1127 | bus_speed = PCI_SPEED_66MHz; |
6558b6ab | 1128 | else if (slot_avail1 & SLOT_33MHZ) |
0afabe90 KK |
1129 | bus_speed = PCI_SPEED_33MHz; |
1130 | else | |
1131 | retval = -ENODEV; | |
1da177e4 LT |
1132 | } |
1133 | ||
1134 | *value = bus_speed; | |
1135 | dbg("Max bus speed = %d\n", bus_speed); | |
1136 | DBG_LEAVE_ROUTINE | |
1137 | return retval; | |
1138 | } | |
1139 | ||
1140 | static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |
1141 | { | |
0afabe90 | 1142 | int retval = 0; |
75d97c59 | 1143 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 1144 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
1145 | u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); |
1146 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | |
0afabe90 | 1147 | u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); |
1da177e4 LT |
1148 | |
1149 | DBG_ENTER_ROUTINE | |
1150 | ||
0afabe90 KK |
1151 | if ((pi == 1) && (speed_mode > 4)) { |
1152 | *value = PCI_SPEED_UNKNOWN; | |
1153 | return -ENODEV; | |
1da177e4 LT |
1154 | } |
1155 | ||
0afabe90 KK |
1156 | switch (speed_mode) { |
1157 | case 0x0: | |
1158 | *value = PCI_SPEED_33MHz; | |
1159 | break; | |
1160 | case 0x1: | |
1161 | *value = PCI_SPEED_66MHz; | |
1162 | break; | |
1163 | case 0x2: | |
1164 | *value = PCI_SPEED_66MHz_PCIX; | |
1165 | break; | |
1166 | case 0x3: | |
1167 | *value = PCI_SPEED_100MHz_PCIX; | |
1168 | break; | |
1169 | case 0x4: | |
1170 | *value = PCI_SPEED_133MHz_PCIX; | |
1171 | break; | |
1172 | case 0x5: | |
1173 | *value = PCI_SPEED_66MHz_PCIX_ECC; | |
1174 | break; | |
1175 | case 0x6: | |
1176 | *value = PCI_SPEED_100MHz_PCIX_ECC; | |
1177 | break; | |
1178 | case 0x7: | |
1179 | *value = PCI_SPEED_133MHz_PCIX_ECC; | |
1180 | break; | |
1181 | case 0x8: | |
1182 | *value = PCI_SPEED_66MHz_PCIX_266; | |
1183 | break; | |
1184 | case 0x9: | |
1185 | *value = PCI_SPEED_100MHz_PCIX_266; | |
1186 | break; | |
1187 | case 0xa: | |
1188 | *value = PCI_SPEED_133MHz_PCIX_266; | |
1189 | break; | |
1190 | case 0xb: | |
1191 | *value = PCI_SPEED_66MHz_PCIX_533; | |
1192 | break; | |
1193 | case 0xc: | |
1194 | *value = PCI_SPEED_100MHz_PCIX_533; | |
1195 | break; | |
1196 | case 0xd: | |
1197 | *value = PCI_SPEED_133MHz_PCIX_533; | |
1198 | break; | |
1199 | default: | |
1200 | *value = PCI_SPEED_UNKNOWN; | |
1201 | retval = -ENODEV; | |
1202 | break; | |
1da177e4 LT |
1203 | } |
1204 | ||
1da177e4 LT |
1205 | dbg("Current bus speed = %d\n", bus_speed); |
1206 | DBG_LEAVE_ROUTINE | |
1207 | return retval; | |
1208 | } | |
1209 | ||
1210 | static struct hpc_ops shpchp_hpc_ops = { | |
1211 | .power_on_slot = hpc_power_on_slot, | |
1212 | .slot_enable = hpc_slot_enable, | |
1213 | .slot_disable = hpc_slot_disable, | |
1da177e4 LT |
1214 | .set_bus_speed_mode = hpc_set_bus_speed_mode, |
1215 | .set_attention_status = hpc_set_attention_status, | |
1216 | .get_power_status = hpc_get_power_status, | |
1217 | .get_attention_status = hpc_get_attention_status, | |
1218 | .get_latch_status = hpc_get_latch_status, | |
1219 | .get_adapter_status = hpc_get_adapter_status, | |
1220 | ||
1221 | .get_max_bus_speed = hpc_get_max_bus_speed, | |
1222 | .get_cur_bus_speed = hpc_get_cur_bus_speed, | |
1223 | .get_adapter_speed = hpc_get_adapter_speed, | |
1224 | .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, | |
1225 | .get_prog_int = hpc_get_prog_int, | |
1226 | ||
1227 | .query_power_fault = hpc_query_power_fault, | |
1228 | .green_led_on = hpc_set_green_led_on, | |
1229 | .green_led_off = hpc_set_green_led_off, | |
1230 | .green_led_blink = hpc_set_green_led_blink, | |
1231 | ||
1232 | .release_ctlr = hpc_release_ctlr, | |
1da177e4 LT |
1233 | }; |
1234 | ||
ee138334 | 1235 | int shpc_init(struct controller * ctrl, struct pci_dev * pdev) |
1da177e4 LT |
1236 | { |
1237 | struct php_ctlr_state_s *php_ctlr, *p; | |
1238 | void *instance_id = ctrl; | |
0455986c | 1239 | int rc, num_slots = 0; |
1da177e4 LT |
1240 | u8 hp_slot; |
1241 | static int first = 1; | |
0455986c | 1242 | u32 shpc_base_offset; |
75d97c59 | 1243 | u32 tempdword, slot_reg, slot_config; |
1da177e4 LT |
1244 | u8 i; |
1245 | ||
1246 | DBG_ENTER_ROUTINE | |
1247 | ||
0455986c KK |
1248 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
1249 | ||
1da177e4 | 1250 | spin_lock_init(&list_lock); |
57c95c0d | 1251 | php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL); |
1da177e4 LT |
1252 | |
1253 | if (!php_ctlr) { /* allocate controller state data */ | |
1254 | err("%s: HPC controller memory allocation error!\n", __FUNCTION__); | |
1255 | goto abort; | |
1256 | } | |
1257 | ||
1da177e4 LT |
1258 | php_ctlr->pci_dev = pdev; /* save pci_dev in context */ |
1259 | ||
ee138334 RS |
1260 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == |
1261 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { | |
0455986c KK |
1262 | /* amd shpc driver doesn't use Base Offset; assume 0 */ |
1263 | ctrl->mmio_base = pci_resource_start(pdev, 0); | |
1264 | ctrl->mmio_size = pci_resource_len(pdev, 0); | |
1da177e4 | 1265 | } else { |
0455986c KK |
1266 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
1267 | if (!ctrl->cap_offset) { | |
1268 | err("%s : cap_offset == 0\n", __FUNCTION__); | |
1da177e4 LT |
1269 | goto abort_free_ctlr; |
1270 | } | |
0455986c KK |
1271 | dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); |
1272 | ||
75d97c59 | 1273 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
1da177e4 | 1274 | if (rc) { |
0455986c | 1275 | err("%s: cannot read base_offset\n", __FUNCTION__); |
1da177e4 LT |
1276 | goto abort_free_ctlr; |
1277 | } | |
0455986c | 1278 | |
75d97c59 | 1279 | rc = shpc_indirect_read(ctrl, 3, &tempdword); |
1da177e4 | 1280 | if (rc) { |
0455986c | 1281 | err("%s: cannot read slot config\n", __FUNCTION__); |
1da177e4 LT |
1282 | goto abort_free_ctlr; |
1283 | } | |
0455986c KK |
1284 | num_slots = tempdword & SLOT_NUM; |
1285 | dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); | |
1da177e4 | 1286 | |
0455986c | 1287 | for (i = 0; i < 9 + num_slots; i++) { |
75d97c59 | 1288 | rc = shpc_indirect_read(ctrl, i, &tempdword); |
1da177e4 | 1289 | if (rc) { |
0455986c KK |
1290 | err("%s: cannot read creg (index = %d)\n", |
1291 | __FUNCTION__, i); | |
1da177e4 LT |
1292 | goto abort_free_ctlr; |
1293 | } | |
7c8942f9 RS |
1294 | dbg("%s: offset %d: value %x\n", __FUNCTION__,i, |
1295 | tempdword); | |
1da177e4 | 1296 | } |
0455986c KK |
1297 | |
1298 | ctrl->mmio_base = | |
1299 | pci_resource_start(pdev, 0) + shpc_base_offset; | |
1300 | ctrl->mmio_size = 0x24 + 0x4 * num_slots; | |
1da177e4 LT |
1301 | } |
1302 | ||
1303 | if (first) { | |
1304 | spin_lock_init(&hpc_event_lock); | |
1305 | first = 0; | |
1306 | } | |
1307 | ||
1da177e4 LT |
1308 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, |
1309 | pdev->subsystem_device); | |
1310 | ||
1311 | if (pci_enable_device(pdev)) | |
1312 | goto abort_free_ctlr; | |
1313 | ||
0455986c | 1314 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
1da177e4 LT |
1315 | err("%s: cannot reserve MMIO region\n", __FUNCTION__); |
1316 | goto abort_free_ctlr; | |
1317 | } | |
1318 | ||
0455986c | 1319 | php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
1da177e4 | 1320 | if (!php_ctlr->creg) { |
0455986c KK |
1321 | err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, |
1322 | ctrl->mmio_size, ctrl->mmio_base); | |
1323 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | |
1da177e4 LT |
1324 | goto abort_free_ctlr; |
1325 | } | |
1326 | dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); | |
1da177e4 | 1327 | |
6aa4cdd0 | 1328 | mutex_init(&ctrl->crit_sect); |
d29aadda KK |
1329 | mutex_init(&ctrl->cmd_lock); |
1330 | ||
1da177e4 LT |
1331 | /* Setup wait queue */ |
1332 | init_waitqueue_head(&ctrl->queue); | |
1333 | ||
1334 | /* Find the IRQ */ | |
1335 | php_ctlr->irq = pdev->irq; | |
ee138334 RS |
1336 | php_ctlr->attention_button_callback = shpchp_handle_attention_button, |
1337 | php_ctlr->switch_change_callback = shpchp_handle_switch_change; | |
1338 | php_ctlr->presence_change_callback = shpchp_handle_presence_change; | |
1339 | php_ctlr->power_fault_callback = shpchp_handle_power_fault; | |
1da177e4 LT |
1340 | php_ctlr->callback_instance_id = instance_id; |
1341 | ||
75d97c59 KK |
1342 | ctrl->hpc_ctlr_handle = php_ctlr; |
1343 | ctrl->hpc_ops = &shpchp_hpc_ops; | |
1344 | ||
1da177e4 | 1345 | /* Return PCI Controller Info */ |
75d97c59 KK |
1346 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
1347 | php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; | |
1348 | php_ctlr->num_slots = slot_config & SLOT_NUM; | |
1da177e4 LT |
1349 | dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset); |
1350 | dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots); | |
1351 | ||
1352 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ | |
75d97c59 | 1353 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1da177e4 LT |
1354 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1355 | tempdword = 0x0003000f; | |
75d97c59 KK |
1356 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1357 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
1da177e4 LT |
1358 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1359 | ||
1360 | /* Mask the MRL sensor SERR Mask of individual slot in | |
1361 | * Slot SERR-INT Mask & clear all the existing event if any | |
1362 | */ | |
1363 | for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { | |
2b34da7e | 1364 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1da177e4 LT |
1365 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, |
1366 | hp_slot, slot_reg); | |
1367 | tempdword = 0xffff3fff; | |
2b34da7e | 1368 | shpc_writel(ctrl, SLOT_REG(hp_slot), tempdword); |
1da177e4 LT |
1369 | } |
1370 | ||
1371 | if (shpchp_poll_mode) {/* Install interrupt polling code */ | |
1372 | /* Install and start the interrupt polling timer */ | |
1373 | init_timer(&php_ctlr->int_poll_timer); | |
1374 | start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ | |
1375 | } else { | |
1376 | /* Installs the interrupt handler */ | |
1377 | rc = pci_enable_msi(pdev); | |
1378 | if (rc) { | |
1379 | info("Can't get msi for the hotplug controller\n"); | |
1380 | info("Use INTx for the hotplug controller\n"); | |
1da177e4 LT |
1381 | } else |
1382 | php_ctlr->irq = pdev->irq; | |
1383 | ||
1384 | rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl); | |
1385 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); | |
1386 | if (rc) { | |
1387 | err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); | |
1388 | goto abort_free_ctlr; | |
1389 | } | |
1da177e4 | 1390 | } |
7c8942f9 RS |
1391 | dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, |
1392 | pdev->bus->number, PCI_SLOT(pdev->devfn), | |
1393 | PCI_FUNC(pdev->devfn), pdev->irq); | |
424600f9 | 1394 | get_hp_hw_control_from_firmware(pdev); |
1da177e4 LT |
1395 | |
1396 | /* Add this HPC instance into the HPC list */ | |
1397 | spin_lock(&list_lock); | |
1398 | if (php_ctlr_list_head == 0) { | |
1399 | php_ctlr_list_head = php_ctlr; | |
1400 | p = php_ctlr_list_head; | |
1401 | p->pnext = NULL; | |
1402 | } else { | |
1403 | p = php_ctlr_list_head; | |
1404 | ||
1405 | while (p->pnext) | |
1406 | p = p->pnext; | |
1407 | ||
1408 | p->pnext = php_ctlr; | |
1409 | } | |
1410 | spin_unlock(&list_lock); | |
1411 | ||
1da177e4 | 1412 | ctlr_seq_num++; |
1da177e4 LT |
1413 | |
1414 | for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { | |
2b34da7e | 1415 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1da177e4 LT |
1416 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, |
1417 | hp_slot, slot_reg); | |
1418 | tempdword = 0xe01f3fff; | |
2b34da7e | 1419 | shpc_writel(ctrl, SLOT_REG(hp_slot), tempdword); |
1da177e4 LT |
1420 | } |
1421 | if (!shpchp_poll_mode) { | |
1422 | /* Unmask all general input interrupts and SERR */ | |
75d97c59 | 1423 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1da177e4 | 1424 | tempdword = 0x0000000a; |
75d97c59 KK |
1425 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1426 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
1da177e4 LT |
1427 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1428 | } | |
1429 | ||
1da177e4 LT |
1430 | DBG_LEAVE_ROUTINE |
1431 | return 0; | |
1432 | ||
1433 | /* We end up here for the many possible ways to fail this API. */ | |
1434 | abort_free_ctlr: | |
1435 | kfree(php_ctlr); | |
1436 | abort: | |
1437 | DBG_LEAVE_ROUTINE | |
1438 | return -1; | |
1439 | } |