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[PATCH] shpchp: fix improper reference to Mode 1 ECC Capability" bit
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / hotplug / shpchp_hpc.c
CommitLineData
1da177e4
LT		 1/*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
8cf4c195 26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
1da177e4
LT		 27 *
28 */
29
1da177e4
LT		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
1da177e4 33#include <linux/pci.h>
d4d28dd4
AM		 34#include <linux/interrupt.h>
35
1da177e4
LT		 36#include "shpchp.h"
37
38#ifdef DEBUG
39#define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40#define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41#define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42#define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43#define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44#define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45/* Redefine this flagword to set debug level */
46#define DEBUG_LEVEL DBG_K_STANDARD
47
48#define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
49
50#define DBG_PRINT( dbg_flags, args... ) \
51 do { \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
53 { \
54 int len; \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
59 } \
60 } while (0)
61
62#define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63#define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
64#else
65#define DEFINE_DBG_BUFFER
66#define DBG_ENTER_ROUTINE
67#define DBG_LEAVE_ROUTINE
68#endif /* DEBUG */
69
70/* Slot Available Register I field definition */
71#define SLOT_33MHZ 0x0000001f
72#define SLOT_66MHZ_PCIX 0x00001f00
73#define SLOT_100MHZ_PCIX 0x001f0000
74#define SLOT_133MHZ_PCIX 0x1f000000
75
76/* Slot Available Register II field definition */
77#define SLOT_66MHZ 0x0000001f
78#define SLOT_66MHZ_PCIX_266 0x00000f00
79#define SLOT_100MHZ_PCIX_266 0x0000f000
80#define SLOT_133MHZ_PCIX_266 0x000f0000
81#define SLOT_66MHZ_PCIX_533 0x00f00000
82#define SLOT_100MHZ_PCIX_533 0x0f000000
83#define SLOT_133MHZ_PCIX_533 0xf0000000
84
85
86/* Secondary Bus Configuration Register */
87/* For PI = 1, Bits 0 to 2 have been encoded as follows to show current bus speed/mode */
88#define PCI_33MHZ 0x0
89#define PCI_66MHZ 0x1
90#define PCIX_66MHZ 0x2
91#define PCIX_100MHZ 0x3
92#define PCIX_133MHZ 0x4
93
94/* For PI = 2, Bits 0 to 3 have been encoded as follows to show current bus speed/mode */
95#define PCI_33MHZ 0x0
96#define PCI_66MHZ 0x1
97#define PCIX_66MHZ 0x2
98#define PCIX_100MHZ 0x3
99#define PCIX_133MHZ 0x4
100#define PCIX_66MHZ_ECC 0x5
101#define PCIX_100MHZ_ECC 0x6
102#define PCIX_133MHZ_ECC 0x7
103#define PCIX_66MHZ_266 0x9
104#define PCIX_100MHZ_266 0xa
105#define PCIX_133MHZ_266 0xb
106#define PCIX_66MHZ_533 0x11
107#define PCIX_100MHZ_533 0x12
108#define PCIX_133MHZ_533 0x13
109
110/* Slot Configuration */
111#define SLOT_NUM 0x0000001F
112#define FIRST_DEV_NUM 0x00001F00
113#define PSN 0x07FF0000
114#define UPDOWN 0x20000000
115#define MRLSENSOR 0x40000000
116#define ATTN_BUTTON 0x80000000
117
118/* Slot Status Field Definitions */
119/* Slot State */
120#define PWR_ONLY 0x0001
121#define ENABLED 0x0002
122#define DISABLED 0x0003
123
124/* Power Indicator State */
125#define PWR_LED_ON 0x0004
126#define PWR_LED_BLINK 0x0008
127#define PWR_LED_OFF 0x000c
128
129/* Attention Indicator State */
130#define ATTEN_LED_ON 0x0010
131#define ATTEN_LED_BLINK 0x0020
132#define ATTEN_LED_OFF 0x0030
133
134/* Power Fault */
135#define pwr_fault 0x0040
136
137/* Attention Button */
138#define ATTEN_BUTTON 0x0080
139
140/* MRL Sensor */
141#define MRL_SENSOR 0x0100
142
143/* 66 MHz Capable */
144#define IS_66MHZ_CAP 0x0200
145
146/* PRSNT1#/PRSNT2# */
147#define SLOT_EMP 0x0c00
148
149/* PCI-X Capability */
150#define NON_PCIX 0x0000
151#define PCIX_66 0x1000
152#define PCIX_133 0x3000
153#define PCIX_266 0x4000 /* For PI = 2 only */
154#define PCIX_533 0x5000 /* For PI = 2 only */
155
156/* SHPC 'write' operations/commands */
157
158/* Slot operation - 0x00h to 0x3Fh */
159
160#define NO_CHANGE 0x00
161
162/* Slot state - Bits 0 & 1 of controller command register */
163#define SET_SLOT_PWR 0x01
164#define SET_SLOT_ENABLE 0x02
165#define SET_SLOT_DISABLE 0x03
166
167/* Power indicator state - Bits 2 & 3 of controller command register*/
168#define SET_PWR_ON 0x04
169#define SET_PWR_BLINK 0x08
170#define SET_PWR_OFF 0x0C
171
172/* Attention indicator state - Bits 4 & 5 of controller command register*/
173#define SET_ATTN_ON 0x010
174#define SET_ATTN_BLINK 0x020
175#define SET_ATTN_OFF 0x030
176
177/* Set bus speed/mode A - 0x40h to 0x47h */
178#define SETA_PCI_33MHZ 0x40
179#define SETA_PCI_66MHZ 0x41
180#define SETA_PCIX_66MHZ 0x42
181#define SETA_PCIX_100MHZ 0x43
182#define SETA_PCIX_133MHZ 0x44
183#define RESERV_1 0x45
184#define RESERV_2 0x46
185#define RESERV_3 0x47
186
187/* Set bus speed/mode B - 0x50h to 0x5fh */
188#define SETB_PCI_33MHZ 0x50
189#define SETB_PCI_66MHZ 0x51
190#define SETB_PCIX_66MHZ_PM 0x52
191#define SETB_PCIX_100MHZ_PM 0x53
192#define SETB_PCIX_133MHZ_PM 0x54
193#define SETB_PCIX_66MHZ_EM 0x55
194#define SETB_PCIX_100MHZ_EM 0x56
195#define SETB_PCIX_133MHZ_EM 0x57
196#define SETB_PCIX_66MHZ_266 0x58
197#define SETB_PCIX_100MHZ_266 0x59
198#define SETB_PCIX_133MHZ_266 0x5a
199#define SETB_PCIX_66MHZ_533 0x5b
200#define SETB_PCIX_100MHZ_533 0x5c
201#define SETB_PCIX_133MHZ_533 0x5d
202
203
204/* Power-on all slots - 0x48h */
205#define SET_PWR_ON_ALL 0x48
206
207/* Enable all slots - 0x49h */
208#define SET_ENABLE_ALL 0x49
209
210/* SHPC controller command error code */
211#define SWITCH_OPEN 0x1
212#define INVALID_CMD 0x2
213#define INVALID_SPEED_MODE 0x4
214
215/* For accessing SHPC Working Register Set */
216#define DWORD_SELECT 0x2
217#define DWORD_DATA 0x4
218#define BASE_OFFSET 0x0
219
220/* Field Offset in Logical Slot Register - byte boundary */
221#define SLOT_EVENT_LATCH 0x2
222#define SLOT_SERR_INT_MASK 0x3
223
224static spinlock_t hpc_event_lock;
225
226DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
227static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
228static int ctlr_seq_num = 0; /* Controller sequenc # */
229static spinlock_t list_lock;
230
231static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
232
233static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
234
235/* This is the interrupt polling timeout function. */
236static void int_poll_timeout(unsigned long lphp_ctlr)
237{
238 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
239
240 DBG_ENTER_ROUTINE
241
242 if ( !php_ctlr ) {
243 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
244 return;
245 }
246
247 /* Poll for interrupt events. regs == NULL => polling */
248 shpc_isr( 0, (void *)php_ctlr, NULL );
249
250 init_timer(&php_ctlr->int_poll_timer);
251 if (!shpchp_poll_time)
252 shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
253
254 start_int_poll_timer(php_ctlr, shpchp_poll_time);
255
256 return;
257}
258
259/* This function starts the interrupt polling timer. */
260static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
261{
262 if (!php_ctlr) {
263 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
264 return;
265 }
266
267 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
268 seconds = 2; /* Clamp to sane value */
269
270 php_ctlr->int_poll_timer.function = &int_poll_timeout;
271 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
272 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
273 add_timer(&php_ctlr->int_poll_timer);
274
275 return;
276}
277
278static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
279{
ee138334 280 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 281 u16 cmd_status;
282 int retval = 0;
283 u16 temp_word;
284 int i;
285
286 DBG_ENTER_ROUTINE
287
288 if (!php_ctlr) {
289 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
290 return -1;
291 }
292
293 for (i = 0; i < 10; i++) {
294 cmd_status = readw(php_ctlr->creg + CMD_STATUS);
295
296 if (!(cmd_status & 0x1))
297 break;
298 /* Check every 0.1 sec for a total of 1 sec*/
299 msleep(100);
300 }
301
302 cmd_status = readw(php_ctlr->creg + CMD_STATUS);
303
304 if (cmd_status & 0x1) {
305 /* After 1 sec and and the controller is still busy */
306 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
307 return -1;
308 }
309
310 ++t_slot;
311 temp_word = (t_slot << 8) | (cmd & 0xFF);
312 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
313
314 /* To make sure the Controller Busy bit is 0 before we send out the
315 * command.
316 */
317 writew(temp_word, php_ctlr->creg + CMD);
1da177e4
LT		 318
319 DBG_LEAVE_ROUTINE
320 return retval;
321}
322
323static int hpc_check_cmd_status(struct controller *ctrl)
324{
ee138334 325 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
1da177e4
LT		 326 u16 cmd_status;
327 int retval = 0;
328
329 DBG_ENTER_ROUTINE
330
331 if (!ctrl->hpc_ctlr_handle) {
332 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
333 return -1;
334 }
335
336 cmd_status = readw(php_ctlr->creg + CMD_STATUS) & 0x000F;
337
338 switch (cmd_status >> 1) {
339 case 0:
340 retval = 0;
341 break;
342 case 1:
343 retval = SWITCH_OPEN;
344 err("%s: Switch opened!\n", __FUNCTION__);
345 break;
346 case 2:
347 retval = INVALID_CMD;
348 err("%s: Invalid HPC command!\n", __FUNCTION__);
349 break;
350 case 4:
351 retval = INVALID_SPEED_MODE;
352 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
353 break;
354 default:
355 retval = cmd_status;
356 }
357
358 DBG_LEAVE_ROUTINE
359 return retval;
360}
361
362
363static int hpc_get_attention_status(struct slot *slot, u8 *status)
364{
ee138334 365 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 366 u32 slot_reg;
367 u16 slot_status;
368 u8 atten_led_state;
369
370 DBG_ENTER_ROUTINE
371
372 if (!slot->ctrl->hpc_ctlr_handle) {
373 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
374 return -1;
375 }
376
377 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
378 slot_status = (u16) slot_reg;
379 atten_led_state = (slot_status & 0x0030) >> 4;
380
381 switch (atten_led_state) {
382 case 0:
383 *status = 0xFF; /* Reserved */
384 break;
385 case 1:
386 *status = 1; /* On */
387 break;
388 case 2:
389 *status = 2; /* Blink */
390 break;
391 case 3:
392 *status = 0; /* Off */
393 break;
394 default:
395 *status = 0xFF;
396 break;
397 }
398
399 DBG_LEAVE_ROUTINE
400 return 0;
401}
402
403static int hpc_get_power_status(struct slot * slot, u8 *status)
404{
ee138334 405 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 406 u32 slot_reg;
407 u16 slot_status;
408 u8 slot_state;
409 int retval = 0;
410
411 DBG_ENTER_ROUTINE
412
413 if (!slot->ctrl->hpc_ctlr_handle) {
414 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
415 return -1;
416 }
417
418 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
419 slot_status = (u16) slot_reg;
420 slot_state = (slot_status & 0x0003);
421
422 switch (slot_state) {
423 case 0:
424 *status = 0xFF;
425 break;
426 case 1:
427 *status = 2; /* Powered only */
428 break;
429 case 2:
430 *status = 1; /* Enabled */
431 break;
432 case 3:
433 *status = 0; /* Disabled */
434 break;
435 default:
436 *status = 0xFF;
437 break;
438 }
439
440 DBG_LEAVE_ROUTINE
441 return retval;
442}
443
444
445static int hpc_get_latch_status(struct slot *slot, u8 *status)
446{
ee138334 447 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 448 u32 slot_reg;
449 u16 slot_status;
450
451 DBG_ENTER_ROUTINE
452
453 if (!slot->ctrl->hpc_ctlr_handle) {
454 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
455 return -1;
456 }
457
458 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
459 slot_status = (u16)slot_reg;
460
461 *status = ((slot_status & 0x0100) == 0) ? 0 : 1; /* 0 -> close; 1 -> open */
462
463
464 DBG_LEAVE_ROUTINE
465 return 0;
466}
467
468static int hpc_get_adapter_status(struct slot *slot, u8 *status)
469{
ee138334 470 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 471 u32 slot_reg;
472 u16 slot_status;
473 u8 card_state;
474
475 DBG_ENTER_ROUTINE
476
477 if (!slot->ctrl->hpc_ctlr_handle) {
478 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
479 return -1;
480 }
481
482 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
483 slot_status = (u16)slot_reg;
484 card_state = (u8)((slot_status & 0x0C00) >> 10);
485 *status = (card_state != 0x3) ? 1 : 0;
486
487 DBG_LEAVE_ROUTINE
488 return 0;
489}
490
491static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
492{
ee138334 493 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 494
495 DBG_ENTER_ROUTINE
496
497 if (!slot->ctrl->hpc_ctlr_handle) {
498 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
499 return -1;
500 }
501
502 *prog_int = readb(php_ctlr->creg + PROG_INTERFACE);
503
504 DBG_LEAVE_ROUTINE
505 return 0;
506}
507
508static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
509{
ee138334 510 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 511 u32 slot_reg;
512 u16 slot_status, sec_bus_status;
513 u8 m66_cap, pcix_cap, pi;
514 int retval = 0;
515
516 DBG_ENTER_ROUTINE
517
518 if (!slot->ctrl->hpc_ctlr_handle) {
519 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
520 return -1;
521 }
522
523 if (slot->hp_slot >= php_ctlr->num_slots) {
524 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
525 return -1;
526 }
527
528 pi = readb(php_ctlr->creg + PROG_INTERFACE);
529 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
530 dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__, pi, slot_reg);
531 slot_status = (u16) slot_reg;
532 dbg("%s: slot_status = %x\n", __FUNCTION__, slot_status);
533 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
534
535 pcix_cap = (u8) ((slot_status & 0x3000) >> 12);
536 dbg("%s: pcix_cap = %x\n", __FUNCTION__, pcix_cap);
537 m66_cap = (u8) ((slot_status & 0x0200) >> 9);
538 dbg("%s: m66_cap = %x\n", __FUNCTION__, m66_cap);
539
540
541 if (pi == 2) {
542 switch (pcix_cap) {
543 case 0:
544 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
545 break;
546 case 1:
547 *value = PCI_SPEED_66MHz_PCIX;
548 break;
549 case 3:
550 *value = PCI_SPEED_133MHz_PCIX;
551 break;
552 case 4:
553 *value = PCI_SPEED_133MHz_PCIX_266;
554 break;
555 case 5:
556 *value = PCI_SPEED_133MHz_PCIX_533;
557 break;
558 case 2: /* Reserved */
559 default:
560 *value = PCI_SPEED_UNKNOWN;
561 retval = -ENODEV;
562 break;
563 }
564 } else {
565 switch (pcix_cap) {
566 case 0:
567 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
568 break;
569 case 1:
570 *value = PCI_SPEED_66MHz_PCIX;
571 break;
572 case 3:
573 *value = PCI_SPEED_133MHz_PCIX;
574 break;
575 case 2: /* Reserved */
576 default:
577 *value = PCI_SPEED_UNKNOWN;
578 retval = -ENODEV;
579 break;
580 }
581 }
582
583 dbg("Adapter speed = %d\n", *value);
584
585 DBG_LEAVE_ROUTINE
586 return retval;
587}
588
589static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
590{
ee138334 591 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 592 u16 sec_bus_status;
593 u8 pi;
594 int retval = 0;
595
596 DBG_ENTER_ROUTINE
597
598 if (!slot->ctrl->hpc_ctlr_handle) {
599 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
600 return -1;
601 }
602
603 pi = readb(php_ctlr->creg + PROG_INTERFACE);
604 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
605
606 if (pi == 2) {
87d6c559 607 *mode = (sec_bus_status & 0x0100) >> 8;
1da177e4
LT		 608 } else {
609 retval = -1;
610 }
611
612 dbg("Mode 1 ECC cap = %d\n", *mode);
613
614 DBG_LEAVE_ROUTINE
615 return retval;
616}
617
618static int hpc_query_power_fault(struct slot * slot)
619{
ee138334 620 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 621 u32 slot_reg;
622 u16 slot_status;
623 u8 pwr_fault_state, status;
624
625 DBG_ENTER_ROUTINE
626
627 if (!slot->ctrl->hpc_ctlr_handle) {
628 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
629 return -1;
630 }
631
632 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
633 slot_status = (u16) slot_reg;
634 pwr_fault_state = (slot_status & 0x0040) >> 7;
635 status = (pwr_fault_state == 1) ? 0 : 1;
636
637 DBG_LEAVE_ROUTINE
638 /* Note: Logic 0 => fault */
639 return status;
640}
641
642static int hpc_set_attention_status(struct slot *slot, u8 value)
643{
ee138334 644 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 645 u8 slot_cmd = 0;
646 int rc = 0;
647
648 if (!slot->ctrl->hpc_ctlr_handle) {
649 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
650 return -1;
651 }
652
653 if (slot->hp_slot >= php_ctlr->num_slots) {
654 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
655 return -1;
656 }
657
658 switch (value) {
659 case 0 :
660 slot_cmd = 0x30; /* OFF */
661 break;
662 case 1:
663 slot_cmd = 0x10; /* ON */
664 break;
665 case 2:
666 slot_cmd = 0x20; /* BLINK */
667 break;
668 default:
669 return -1;
670 }
671
672 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
673
674 return rc;
675}
676
677
678static void hpc_set_green_led_on(struct slot *slot)
679{
ee138334 680 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 681 u8 slot_cmd;
682
683 if (!slot->ctrl->hpc_ctlr_handle) {
684 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
685 return ;
686 }
687
688 if (slot->hp_slot >= php_ctlr->num_slots) {
689 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
690 return ;
691 }
692
693 slot_cmd = 0x04;
694
695 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
696
697 return;
698}
699
700static void hpc_set_green_led_off(struct slot *slot)
701{
ee138334 702 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 703 u8 slot_cmd;
704
705 if (!slot->ctrl->hpc_ctlr_handle) {
706 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
707 return ;
708 }
709
710 if (slot->hp_slot >= php_ctlr->num_slots) {
711 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
712 return ;
713 }
714
715 slot_cmd = 0x0C;
716
717 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
718
719 return;
720}
721
722static void hpc_set_green_led_blink(struct slot *slot)
723{
ee138334 724 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 725 u8 slot_cmd;
726
727 if (!slot->ctrl->hpc_ctlr_handle) {
728 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
729 return ;
730 }
731
732 if (slot->hp_slot >= php_ctlr->num_slots) {
733 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
734 return ;
735 }
736
737 slot_cmd = 0x08;
738
739 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
740
741 return;
742}
743
744int shpc_get_ctlr_slot_config(struct controller *ctrl,
745 int *num_ctlr_slots, /* number of slots in this HPC */
746 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
747 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
748 int *updown, /* physical_slot_num increament: 1 or -1 */
749 int *flags)
750{
ee138334 751 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
1da177e4
LT		 752
753 DBG_ENTER_ROUTINE
754
755 if (!ctrl->hpc_ctlr_handle) {
756 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
757 return -1;
758 }
759
760 *first_device_num = php_ctlr->slot_device_offset; /* Obtained in shpc_init() */
761 *num_ctlr_slots = php_ctlr->num_slots; /* Obtained in shpc_init() */
762
763 *physical_slot_num = (readl(php_ctlr->creg + SLOT_CONFIG) & PSN) >> 16;
764 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
765 *updown = ((readl(php_ctlr->creg + SLOT_CONFIG) & UPDOWN ) >> 29) ? 1 : -1;
766
767 DBG_LEAVE_ROUTINE
768 return 0;
769}
770
771static void hpc_release_ctlr(struct controller *ctrl)
772{
ee138334 773 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
1da177e4
LT		 774 struct php_ctlr_state_s *p, *p_prev;
775
776 DBG_ENTER_ROUTINE
777
778 if (!ctrl->hpc_ctlr_handle) {
779 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
780 return ;
781 }
782
783 if (shpchp_poll_mode) {
784 del_timer(&php_ctlr->int_poll_timer);
785 } else {
786 if (php_ctlr->irq) {
787 free_irq(php_ctlr->irq, ctrl);
788 php_ctlr->irq = 0;
789 pci_disable_msi(php_ctlr->pci_dev);
790 }
791 }
792 if (php_ctlr->pci_dev) {
1da177e4
LT		 793 iounmap(php_ctlr->creg);
794 release_mem_region(pci_resource_start(php_ctlr->pci_dev, 0), pci_resource_len(php_ctlr->pci_dev, 0));
1da177e4
LT		 795 php_ctlr->pci_dev = NULL;
796 }
797
798 spin_lock(&list_lock);
799 p = php_ctlr_list_head;
800 p_prev = NULL;
801 while (p) {
802 if (p == php_ctlr) {
803 if (p_prev)
804 p_prev->pnext = p->pnext;
805 else
806 php_ctlr_list_head = p->pnext;
807 break;
808 } else {
809 p_prev = p;
810 p = p->pnext;
811 }
812 }
813 spin_unlock(&list_lock);
814
815 kfree(php_ctlr);
816
817DBG_LEAVE_ROUTINE
818
819}
820
821static int hpc_power_on_slot(struct slot * slot)
822{
ee138334 823 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 824 u8 slot_cmd;
825 int retval = 0;
826
827 DBG_ENTER_ROUTINE
828
829 if (!slot->ctrl->hpc_ctlr_handle) {
830 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
831 return -1;
832 }
833
834 if (slot->hp_slot >= php_ctlr->num_slots) {
835 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
836 return -1;
837 }
838 slot_cmd = 0x01;
839
840 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
841
842 if (retval) {
843 err("%s: Write command failed!\n", __FUNCTION__);
844 return -1;
845 }
846
847 DBG_LEAVE_ROUTINE
848
849 return retval;
850}
851
852static int hpc_slot_enable(struct slot * slot)
853{
ee138334 854 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 855 u8 slot_cmd;
856 int retval = 0;
857
858 DBG_ENTER_ROUTINE
859
860 if (!slot->ctrl->hpc_ctlr_handle) {
861 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
862 return -1;
863 }
864
865 if (slot->hp_slot >= php_ctlr->num_slots) {
866 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
867 return -1;
868 }
869 /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
870 slot_cmd = 0x3A;
871
872 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
873
874 if (retval) {
875 err("%s: Write command failed!\n", __FUNCTION__);
876 return -1;
877 }
878
879 DBG_LEAVE_ROUTINE
880 return retval;
881}
882
883static int hpc_slot_disable(struct slot * slot)
884{
ee138334 885 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 886 u8 slot_cmd;
887 int retval = 0;
888
889 DBG_ENTER_ROUTINE
890
891 if (!slot->ctrl->hpc_ctlr_handle) {
892 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
893 return -1;
894 }
895
896 if (slot->hp_slot >= php_ctlr->num_slots) {
897 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
898 return -1;
899 }
900
901 /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
902 slot_cmd = 0x1F;
903
904 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
905
906 if (retval) {
907 err("%s: Write command failed!\n", __FUNCTION__);
908 return -1;
909 }
910
911 DBG_LEAVE_ROUTINE
912 return retval;
913}
914
1da177e4
LT		 915static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
916{
917 u8 slot_cmd;
918 u8 pi;
919 int retval = 0;
ee138334 920 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 921
922 DBG_ENTER_ROUTINE
923
924 if (!slot->ctrl->hpc_ctlr_handle) {
925 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
926 return -1;
927 }
928
929 pi = readb(php_ctlr->creg + PROG_INTERFACE);
930
931 if (pi == 1) {
932 switch (value) {
933 case 0:
934 slot_cmd = SETA_PCI_33MHZ;
935 break;
936 case 1:
937 slot_cmd = SETA_PCI_66MHZ;
938 break;
939 case 2:
940 slot_cmd = SETA_PCIX_66MHZ;
941 break;
942 case 3:
943 slot_cmd = SETA_PCIX_100MHZ;
944 break;
945 case 4:
946 slot_cmd = SETA_PCIX_133MHZ;
947 break;
948 default:
949 slot_cmd = PCI_SPEED_UNKNOWN;
950 retval = -ENODEV;
951 return retval;
952 }
953 } else {
954 switch (value) {
955 case 0:
956 slot_cmd = SETB_PCI_33MHZ;
957 break;
958 case 1:
959 slot_cmd = SETB_PCI_66MHZ;
960 break;
961 case 2:
962 slot_cmd = SETB_PCIX_66MHZ_PM;
963 break;
964 case 3:
965 slot_cmd = SETB_PCIX_100MHZ_PM;
966 break;
967 case 4:
968 slot_cmd = SETB_PCIX_133MHZ_PM;
969 break;
970 case 5:
971 slot_cmd = SETB_PCIX_66MHZ_EM;
972 break;
973 case 6:
974 slot_cmd = SETB_PCIX_100MHZ_EM;
975 break;
976 case 7:
977 slot_cmd = SETB_PCIX_133MHZ_EM;
978 break;
979 case 8:
980 slot_cmd = SETB_PCIX_66MHZ_266;
981 break;
982 case 0x9:
983 slot_cmd = SETB_PCIX_100MHZ_266;
984 break;
985 case 0xa:
986 slot_cmd = SETB_PCIX_133MHZ_266;
987 break;
988 case 0xb:
989 slot_cmd = SETB_PCIX_66MHZ_533;
990 break;
991 case 0xc:
992 slot_cmd = SETB_PCIX_100MHZ_533;
993 break;
994 case 0xd:
995 slot_cmd = SETB_PCIX_133MHZ_533;
996 break;
997 default:
998 slot_cmd = PCI_SPEED_UNKNOWN;
999 retval = -ENODEV;
1000 return retval;
1001 }
1002
1003 }
1004 retval = shpc_write_cmd(slot, 0, slot_cmd);
1005 if (retval) {
1006 err("%s: Write command failed!\n", __FUNCTION__);
1007 return -1;
1008 }
1009
1010 DBG_LEAVE_ROUTINE
1011 return retval;
1012}
1013
1014static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1015{
1016 struct controller *ctrl = NULL;
1017 struct php_ctlr_state_s *php_ctlr;
1018 u8 schedule_flag = 0;
1019 u8 temp_byte;
1020 u32 temp_dword, intr_loc, intr_loc2;
1021 int hp_slot;
1022
1023 if (!dev_id)
1024 return IRQ_NONE;
1025
1026 if (!shpchp_poll_mode) {
1027 ctrl = (struct controller *)dev_id;
1028 php_ctlr = ctrl->hpc_ctlr_handle;
1029 } else {
1030 php_ctlr = (struct php_ctlr_state_s *) dev_id;
1031 ctrl = (struct controller *)php_ctlr->callback_instance_id;
1032 }
1033
1034 if (!ctrl)
1035 return IRQ_NONE;
1036
1037 if (!php_ctlr || !php_ctlr->creg)
1038 return IRQ_NONE;
1039
1040 /* Check to see if it was our interrupt */
1041 intr_loc = readl(php_ctlr->creg + INTR_LOC);
1042
1043 if (!intr_loc)
1044 return IRQ_NONE;
1da177e4
LT		 1045 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
1046
1047 if(!shpchp_poll_mode) {
1048 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
1049 /* of SHPC spec rev 1.0*/
1050 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1da177e4 1051 temp_dword |= 0x00000001;
1da177e4
LT		 1052 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1053
1054 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
1055 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1056 }
1057
1058 if (intr_loc & 0x0001) {
1059 /*
1060 * Command Complete Interrupt Pending
1061 * RO only - clear by writing 0 to the Command Completion
1062 * Detect bit in Controller SERR-INT register
1063 */
1064 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1da177e4 1065 temp_dword &= 0xfffeffff;
1da177e4
LT		 1066 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1067 wake_up_interruptible(&ctrl->queue);
1068 }
1069
1070 if ((intr_loc = (intr_loc >> 1)) == 0) {
1071 /* Unmask Global Interrupt Mask */
1072 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1da177e4 1073 temp_dword &= 0xfffffffe;
1da177e4
LT		 1074 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1075
1076 return IRQ_NONE;
1077 }
1078
1079 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1080 /* To find out which slot has interrupt pending */
1081 if ((intr_loc >> hp_slot) & 0x01) {
1082 temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot));
7c8942f9
RS		 1083 dbg("%s: Slot %x with intr, slot register = %x\n",
1084 __FUNCTION__, hp_slot, temp_dword);
1da177e4 1085 temp_byte = (temp_dword >> 16) & 0xFF;
1da177e4
LT		 1086 if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08))
1087 schedule_flag += php_ctlr->switch_change_callback(
1088 hp_slot, php_ctlr->callback_instance_id);
1089 if ((php_ctlr->attention_button_callback) && (temp_byte & 0x04))
1090 schedule_flag += php_ctlr->attention_button_callback(
1091 hp_slot, php_ctlr->callback_instance_id);
1092 if ((php_ctlr->presence_change_callback) && (temp_byte & 0x01))
1093 schedule_flag += php_ctlr->presence_change_callback(
1094 hp_slot , php_ctlr->callback_instance_id);
1095 if ((php_ctlr->power_fault_callback) && (temp_byte & 0x12))
1096 schedule_flag += php_ctlr->power_fault_callback(
1097 hp_slot, php_ctlr->callback_instance_id);
1098
1099 /* Clear all slot events */
1100 temp_dword = 0xe01f3fff;
1da177e4
LT		 1101 writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1102
1103 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
1104 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1105 }
1106 }
1107 if (!shpchp_poll_mode) {
1108 /* Unmask Global Interrupt Mask */
1109 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1da177e4 1110 temp_dword &= 0xfffffffe;
1da177e4
LT		 1111 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1112 }
1113
1114 return IRQ_HANDLED;
1115}
1116
1117static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1118{
ee138334 1119 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 1120 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1121 int retval = 0;
1122 u8 pi;
1123 u32 slot_avail1, slot_avail2;
1da177e4
LT		 1124
1125 DBG_ENTER_ROUTINE
1126
1127 if (!slot->ctrl->hpc_ctlr_handle) {
1128 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1129 return -1;
1130 }
1131
1132 if (slot->hp_slot >= php_ctlr->num_slots) {
1133 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1134 return -1;
1135 }
1136
1137 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1138 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
1139 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
1140
1141 if (pi == 2) {
6558b6ab 1142 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
1da177e4 1143 bus_speed = PCIX_133MHZ_533;
6558b6ab 1144 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
1da177e4 1145 bus_speed = PCIX_100MHZ_533;
6558b6ab 1146 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
1da177e4 1147 bus_speed = PCIX_66MHZ_533;
6558b6ab 1148 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
1da177e4 1149 bus_speed = PCIX_133MHZ_266;
6558b6ab 1150 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
1da177e4 1151 bus_speed = PCIX_100MHZ_266;
6558b6ab 1152 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
1da177e4 1153 bus_speed = PCIX_66MHZ_266;
6558b6ab 1154 else if (slot_avail1 & SLOT_133MHZ_PCIX)
1da177e4 1155 bus_speed = PCIX_133MHZ;
6558b6ab 1156 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1da177e4 1157 bus_speed = PCIX_100MHZ;
6558b6ab 1158 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1da177e4 1159 bus_speed = PCIX_66MHZ;
6558b6ab 1160 else if (slot_avail2 & SLOT_66MHZ)
1da177e4 1161 bus_speed = PCI_66MHZ;
6558b6ab 1162 else if (slot_avail1 & SLOT_33MHZ)
1da177e4
LT		 1163 bus_speed = PCI_33MHZ;
1164 else bus_speed = PCI_SPEED_UNKNOWN;
1165 } else {
6558b6ab 1166 if (slot_avail1 & SLOT_133MHZ_PCIX)
1da177e4 1167 bus_speed = PCIX_133MHZ;
6558b6ab 1168 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1da177e4 1169 bus_speed = PCIX_100MHZ;
6558b6ab 1170 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1da177e4 1171 bus_speed = PCIX_66MHZ;
6558b6ab 1172 else if (slot_avail2 & SLOT_66MHZ)
1da177e4 1173 bus_speed = PCI_66MHZ;
6558b6ab 1174 else if (slot_avail1 & SLOT_33MHZ)
1da177e4
LT		 1175 bus_speed = PCI_33MHZ;
1176 else bus_speed = PCI_SPEED_UNKNOWN;
1177 }
1178
1179 *value = bus_speed;
1180 dbg("Max bus speed = %d\n", bus_speed);
1181 DBG_LEAVE_ROUTINE
1182 return retval;
1183}
1184
1185static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1186{
ee138334 1187 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1da177e4
LT		 1188 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1189 u16 sec_bus_status;
1190 int retval = 0;
1191 u8 pi;
1192
1193 DBG_ENTER_ROUTINE
1194
1195 if (!slot->ctrl->hpc_ctlr_handle) {
1196 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1197 return -1;
1198 }
1199
1200 if (slot->hp_slot >= php_ctlr->num_slots) {
1201 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1202 return -1;
1203 }
1204
1205 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1206 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
1207
1208 if (pi == 2) {
1209 switch (sec_bus_status & 0x000f) {
1210 case 0:
1211 bus_speed = PCI_SPEED_33MHz;
1212 break;
1213 case 1:
1214 bus_speed = PCI_SPEED_66MHz;
1215 break;
1216 case 2:
1217 bus_speed = PCI_SPEED_66MHz_PCIX;
1218 break;
1219 case 3:
1220 bus_speed = PCI_SPEED_100MHz_PCIX;
1221 break;
1222 case 4:
1223 bus_speed = PCI_SPEED_133MHz_PCIX;
1224 break;
1225 case 5:
1226 bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
1227 break;
1228 case 6:
1229 bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
1230 break;
1231 case 7:
1232 bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
1233 break;
1234 case 8:
1235 bus_speed = PCI_SPEED_66MHz_PCIX_266;
1236 break;
1237 case 9:
1238 bus_speed = PCI_SPEED_100MHz_PCIX_266;
1239 break;
1240 case 0xa:
1241 bus_speed = PCI_SPEED_133MHz_PCIX_266;
1242 break;
1243 case 0xb:
1244 bus_speed = PCI_SPEED_66MHz_PCIX_533;
1245 break;
1246 case 0xc:
1247 bus_speed = PCI_SPEED_100MHz_PCIX_533;
1248 break;
1249 case 0xd:
1250 bus_speed = PCI_SPEED_133MHz_PCIX_533;
1251 break;
1252 case 0xe:
1253 case 0xf:
1254 default:
1255 bus_speed = PCI_SPEED_UNKNOWN;
1256 break;
1257 }
1258 } else {
1259 /* In the case where pi is undefined, default it to 1 */
1260 switch (sec_bus_status & 0x0007) {
1261 case 0:
1262 bus_speed = PCI_SPEED_33MHz;
1263 break;
1264 case 1:
1265 bus_speed = PCI_SPEED_66MHz;
1266 break;
1267 case 2:
1268 bus_speed = PCI_SPEED_66MHz_PCIX;
1269 break;
1270 case 3:
1271 bus_speed = PCI_SPEED_100MHz_PCIX;
1272 break;
1273 case 4:
1274 bus_speed = PCI_SPEED_133MHz_PCIX;
1275 break;
1276 case 5:
1277 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1278 break;
1279 case 6:
1280 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1281 break;
1282 case 7:
1283 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1284 break;
1285 default:
1286 bus_speed = PCI_SPEED_UNKNOWN;
1287 break;
1288 }
1289 }
1290
1291 *value = bus_speed;
1292 dbg("Current bus speed = %d\n", bus_speed);
1293 DBG_LEAVE_ROUTINE
1294 return retval;
1295}
1296
1297static struct hpc_ops shpchp_hpc_ops = {
1298 .power_on_slot = hpc_power_on_slot,
1299 .slot_enable = hpc_slot_enable,
1300 .slot_disable = hpc_slot_disable,
1da177e4
LT		 1301 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1302 .set_attention_status = hpc_set_attention_status,
1303 .get_power_status = hpc_get_power_status,
1304 .get_attention_status = hpc_get_attention_status,
1305 .get_latch_status = hpc_get_latch_status,
1306 .get_adapter_status = hpc_get_adapter_status,
1307
1308 .get_max_bus_speed = hpc_get_max_bus_speed,
1309 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1310 .get_adapter_speed = hpc_get_adapter_speed,
1311 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1312 .get_prog_int = hpc_get_prog_int,
1313
1314 .query_power_fault = hpc_query_power_fault,
1315 .green_led_on = hpc_set_green_led_on,
1316 .green_led_off = hpc_set_green_led_off,
1317 .green_led_blink = hpc_set_green_led_blink,
1318
1319 .release_ctlr = hpc_release_ctlr,
1320 .check_cmd_status = hpc_check_cmd_status,
1321};
1322
ee138334 1323int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1da177e4
LT		 1324{
1325 struct php_ctlr_state_s *php_ctlr, *p;
1326 void *instance_id = ctrl;
1327 int rc;
1328 u8 hp_slot;
1329 static int first = 1;
1330 u32 shpc_cap_offset, shpc_base_offset;
1331 u32 tempdword, slot_reg;
1da177e4
LT		 1332 u8 i;
1333
1334 DBG_ENTER_ROUTINE
1335
1336 spin_lock_init(&list_lock);
1337 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1338
1339 if (!php_ctlr) { /* allocate controller state data */
1340 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1341 goto abort;
1342 }
1343
1344 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1345
1346 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1347
ee138334
RS		 1348 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1349 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1da177e4
LT		 1350 shpc_base_offset = 0; /* amd shpc driver doesn't use this; assume 0 */
1351 } else {
1352 if ((shpc_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC)) == 0) {
1353 err("%s : shpc_cap_offset == 0\n", __FUNCTION__);
1354 goto abort_free_ctlr;
1355 }
1356 dbg("%s: shpc_cap_offset = %x\n", __FUNCTION__, shpc_cap_offset);
1357
1358 rc = pci_write_config_byte(pdev, (u8)shpc_cap_offset + DWORD_SELECT , BASE_OFFSET);
1359 if (rc) {
1360 err("%s : pci_word_config_byte failed\n", __FUNCTION__);
1361 goto abort_free_ctlr;
1362 }
1363
1364 rc = pci_read_config_dword(pdev, (u8)shpc_cap_offset + DWORD_DATA, &shpc_base_offset);
1365 if (rc) {
1366 err("%s : pci_read_config_dword failed\n", __FUNCTION__);
1367 goto abort_free_ctlr;
1368 }
1369
1370 for (i = 0; i <= 14; i++) {
1371 rc = pci_write_config_byte(pdev, (u8)shpc_cap_offset + DWORD_SELECT , i);
1372 if (rc) {
1373 err("%s : pci_word_config_byte failed\n", __FUNCTION__);
1374 goto abort_free_ctlr;
1375 }
1376
1377 rc = pci_read_config_dword(pdev, (u8)shpc_cap_offset + DWORD_DATA, &tempdword);
1378 if (rc) {
1379 err("%s : pci_read_config_dword failed\n", __FUNCTION__);
1380 goto abort_free_ctlr;
1381 }
7c8942f9
RS		 1382 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1383 tempdword);
1da177e4
LT		 1384 }
1385 }
1386
1387 if (first) {
1388 spin_lock_init(&hpc_event_lock);
1389 first = 0;
1390 }
1391
1da177e4
LT		 1392 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1393 pdev->subsystem_device);
1394
1395 if (pci_enable_device(pdev))
1396 goto abort_free_ctlr;
1397
1398 if (!request_mem_region(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0), MY_NAME)) {
1399 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1400 goto abort_free_ctlr;
1401 }
1402
1403 php_ctlr->creg = ioremap(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0));
1404 if (!php_ctlr->creg) {
1405 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, pci_resource_len(pdev, 0),
1406 pci_resource_start(pdev, 0) + shpc_base_offset);
1407 release_mem_region(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0));
1408 goto abort_free_ctlr;
1409 }
1410 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1da177e4
LT		 1411
1412 init_MUTEX(&ctrl->crit_sect);
1413 /* Setup wait queue */
1414 init_waitqueue_head(&ctrl->queue);
1415
1416 /* Find the IRQ */
1417 php_ctlr->irq = pdev->irq;
ee138334
RS		 1418 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1419 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1420 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1421 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1da177e4
LT		 1422 php_ctlr->callback_instance_id = instance_id;
1423
1424 /* Return PCI Controller Info */
1425 php_ctlr->slot_device_offset = (readl(php_ctlr->creg + SLOT_CONFIG) & FIRST_DEV_NUM ) >> 8;
1426 php_ctlr->num_slots = readl(php_ctlr->creg + SLOT_CONFIG) & SLOT_NUM;
1427 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1428 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1429
1430 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1431 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1432 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1433 tempdword = 0x0003000f;
1434 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
1435 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1436 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1437
1438 /* Mask the MRL sensor SERR Mask of individual slot in
1439 * Slot SERR-INT Mask & clear all the existing event if any
1440 */
1441 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1442 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
1443 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1444 hp_slot, slot_reg);
1445 tempdword = 0xffff3fff;
1446 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1447 }
1448
1449 if (shpchp_poll_mode) {/* Install interrupt polling code */
1450 /* Install and start the interrupt polling timer */
1451 init_timer(&php_ctlr->int_poll_timer);
1452 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1453 } else {
1454 /* Installs the interrupt handler */
1455 rc = pci_enable_msi(pdev);
1456 if (rc) {
1457 info("Can't get msi for the hotplug controller\n");
1458 info("Use INTx for the hotplug controller\n");
1da177e4
LT		 1459 } else
1460 php_ctlr->irq = pdev->irq;
1461
1462 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1463 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1464 if (rc) {
1465 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1466 goto abort_free_ctlr;
1467 }
1da177e4 1468 }
7c8942f9
RS		 1469 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1470 pdev->bus->number, PCI_SLOT(pdev->devfn),
1471 PCI_FUNC(pdev->devfn), pdev->irq);
424600f9 1472 get_hp_hw_control_from_firmware(pdev);
1da177e4
LT		 1473
1474 /* Add this HPC instance into the HPC list */
1475 spin_lock(&list_lock);
1476 if (php_ctlr_list_head == 0) {
1477 php_ctlr_list_head = php_ctlr;
1478 p = php_ctlr_list_head;
1479 p->pnext = NULL;
1480 } else {
1481 p = php_ctlr_list_head;
1482
1483 while (p->pnext)
1484 p = p->pnext;
1485
1486 p->pnext = php_ctlr;
1487 }
1488 spin_unlock(&list_lock);
1489
1490
1491 ctlr_seq_num++;
1492 ctrl->hpc_ctlr_handle = php_ctlr;
1493 ctrl->hpc_ops = &shpchp_hpc_ops;
1494
1495 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1496 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
1497 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1498 hp_slot, slot_reg);
1499 tempdword = 0xe01f3fff;
1500 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1501 }
1502 if (!shpchp_poll_mode) {
1503 /* Unmask all general input interrupts and SERR */
1504 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1505 tempdword = 0x0000000a;
1506 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
1507 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1508 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1509 }
1510
1da177e4
LT		 1511 DBG_LEAVE_ROUTINE
1512 return 0;
1513
1514 /* We end up here for the many possible ways to fail this API. */
1515abort_free_ctlr:
1516 kfree(php_ctlr);
1517abort:
1518 DBG_LEAVE_ROUTINE
1519 return -1;
1520}
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