]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Standard PCI Hot Plug Driver | |
3 | * | |
4 | * Copyright (C) 1995,2001 Compaq Computer Corporation | |
5 | * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) | |
6 | * Copyright (C) 2001 IBM Corp. | |
7 | * Copyright (C) 2003-2004 Intel Corporation | |
8 | * | |
9 | * All rights reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
19 | * NON INFRINGEMENT. See the GNU General Public License for more | |
20 | * details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
8cf4c195 | 26 | * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/types.h> | |
1da177e4 | 33 | #include <linux/pci.h> |
d4d28dd4 AM |
34 | #include <linux/interrupt.h> |
35 | ||
1da177e4 LT |
36 | #include "shpchp.h" |
37 | ||
38 | #ifdef DEBUG | |
39 | #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */ | |
40 | #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */ | |
41 | #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */ | |
42 | #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */ | |
43 | #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT) | |
44 | #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE) | |
45 | /* Redefine this flagword to set debug level */ | |
46 | #define DEBUG_LEVEL DBG_K_STANDARD | |
47 | ||
48 | #define DEFINE_DBG_BUFFER char __dbg_str_buf[256]; | |
49 | ||
50 | #define DBG_PRINT( dbg_flags, args... ) \ | |
51 | do { \ | |
52 | if ( DEBUG_LEVEL & ( dbg_flags ) ) \ | |
53 | { \ | |
54 | int len; \ | |
55 | len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \ | |
56 | __FILE__, __LINE__, __FUNCTION__ ); \ | |
57 | sprintf( __dbg_str_buf + len, args ); \ | |
58 | printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \ | |
59 | } \ | |
60 | } while (0) | |
61 | ||
62 | #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]"); | |
63 | #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]"); | |
64 | #else | |
65 | #define DEFINE_DBG_BUFFER | |
66 | #define DBG_ENTER_ROUTINE | |
67 | #define DBG_LEAVE_ROUTINE | |
68 | #endif /* DEBUG */ | |
69 | ||
70 | /* Slot Available Register I field definition */ | |
71 | #define SLOT_33MHZ 0x0000001f | |
72 | #define SLOT_66MHZ_PCIX 0x00001f00 | |
73 | #define SLOT_100MHZ_PCIX 0x001f0000 | |
74 | #define SLOT_133MHZ_PCIX 0x1f000000 | |
75 | ||
76 | /* Slot Available Register II field definition */ | |
77 | #define SLOT_66MHZ 0x0000001f | |
78 | #define SLOT_66MHZ_PCIX_266 0x00000f00 | |
79 | #define SLOT_100MHZ_PCIX_266 0x0000f000 | |
80 | #define SLOT_133MHZ_PCIX_266 0x000f0000 | |
81 | #define SLOT_66MHZ_PCIX_533 0x00f00000 | |
82 | #define SLOT_100MHZ_PCIX_533 0x0f000000 | |
83 | #define SLOT_133MHZ_PCIX_533 0xf0000000 | |
84 | ||
1da177e4 LT |
85 | /* Slot Configuration */ |
86 | #define SLOT_NUM 0x0000001F | |
87 | #define FIRST_DEV_NUM 0x00001F00 | |
88 | #define PSN 0x07FF0000 | |
89 | #define UPDOWN 0x20000000 | |
90 | #define MRLSENSOR 0x40000000 | |
91 | #define ATTN_BUTTON 0x80000000 | |
92 | ||
e7138723 KK |
93 | /* |
94 | * Controller SERR-INT Register | |
95 | */ | |
96 | #define GLOBAL_INTR_MASK (1 << 0) | |
97 | #define GLOBAL_SERR_MASK (1 << 1) | |
98 | #define COMMAND_INTR_MASK (1 << 2) | |
99 | #define ARBITER_SERR_MASK (1 << 3) | |
100 | #define COMMAND_DETECTED (1 << 16) | |
101 | #define ARBITER_DETECTED (1 << 17) | |
102 | #define SERR_INTR_RSVDZ_MASK 0xfffc0000 | |
103 | ||
2b34da7e KK |
104 | /* |
105 | * Logical Slot Register definitions | |
106 | */ | |
107 | #define SLOT_REG(i) (SLOT1 + (4 * i)) | |
108 | ||
5858759c KK |
109 | #define SLOT_STATE_SHIFT (0) |
110 | #define SLOT_STATE_MASK (3 << 0) | |
111 | #define SLOT_STATE_PWRONLY (1) | |
112 | #define SLOT_STATE_ENABLED (2) | |
113 | #define SLOT_STATE_DISABLED (3) | |
114 | #define PWR_LED_STATE_SHIFT (2) | |
115 | #define PWR_LED_STATE_MASK (3 << 2) | |
116 | #define ATN_LED_STATE_SHIFT (4) | |
117 | #define ATN_LED_STATE_MASK (3 << 4) | |
118 | #define ATN_LED_STATE_ON (1) | |
119 | #define ATN_LED_STATE_BLINK (2) | |
120 | #define ATN_LED_STATE_OFF (3) | |
121 | #define POWER_FAULT (1 << 6) | |
122 | #define ATN_BUTTON (1 << 7) | |
123 | #define MRL_SENSOR (1 << 8) | |
124 | #define MHZ66_CAP (1 << 9) | |
125 | #define PRSNT_SHIFT (10) | |
126 | #define PRSNT_MASK (3 << 10) | |
127 | #define PCIX_CAP_SHIFT (12) | |
128 | #define PCIX_CAP_MASK_PI1 (3 << 12) | |
129 | #define PCIX_CAP_MASK_PI2 (7 << 12) | |
130 | #define PRSNT_CHANGE_DETECTED (1 << 16) | |
131 | #define ISO_PFAULT_DETECTED (1 << 17) | |
132 | #define BUTTON_PRESS_DETECTED (1 << 18) | |
133 | #define MRL_CHANGE_DETECTED (1 << 19) | |
134 | #define CON_PFAULT_DETECTED (1 << 20) | |
135 | #define PRSNT_CHANGE_INTR_MASK (1 << 24) | |
136 | #define ISO_PFAULT_INTR_MASK (1 << 25) | |
137 | #define BUTTON_PRESS_INTR_MASK (1 << 26) | |
138 | #define MRL_CHANGE_INTR_MASK (1 << 27) | |
139 | #define CON_PFAULT_INTR_MASK (1 << 28) | |
140 | #define MRL_CHANGE_SERR_MASK (1 << 29) | |
141 | #define CON_PFAULT_SERR_MASK (1 << 30) | |
142 | #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21) | |
1da177e4 LT |
143 | |
144 | /* SHPC 'write' operations/commands */ | |
145 | ||
146 | /* Slot operation - 0x00h to 0x3Fh */ | |
147 | ||
148 | #define NO_CHANGE 0x00 | |
149 | ||
150 | /* Slot state - Bits 0 & 1 of controller command register */ | |
151 | #define SET_SLOT_PWR 0x01 | |
152 | #define SET_SLOT_ENABLE 0x02 | |
153 | #define SET_SLOT_DISABLE 0x03 | |
154 | ||
155 | /* Power indicator state - Bits 2 & 3 of controller command register*/ | |
156 | #define SET_PWR_ON 0x04 | |
157 | #define SET_PWR_BLINK 0x08 | |
158 | #define SET_PWR_OFF 0x0C | |
159 | ||
160 | /* Attention indicator state - Bits 4 & 5 of controller command register*/ | |
161 | #define SET_ATTN_ON 0x010 | |
162 | #define SET_ATTN_BLINK 0x020 | |
163 | #define SET_ATTN_OFF 0x030 | |
164 | ||
165 | /* Set bus speed/mode A - 0x40h to 0x47h */ | |
166 | #define SETA_PCI_33MHZ 0x40 | |
167 | #define SETA_PCI_66MHZ 0x41 | |
168 | #define SETA_PCIX_66MHZ 0x42 | |
169 | #define SETA_PCIX_100MHZ 0x43 | |
170 | #define SETA_PCIX_133MHZ 0x44 | |
171 | #define RESERV_1 0x45 | |
172 | #define RESERV_2 0x46 | |
173 | #define RESERV_3 0x47 | |
174 | ||
175 | /* Set bus speed/mode B - 0x50h to 0x5fh */ | |
176 | #define SETB_PCI_33MHZ 0x50 | |
177 | #define SETB_PCI_66MHZ 0x51 | |
178 | #define SETB_PCIX_66MHZ_PM 0x52 | |
179 | #define SETB_PCIX_100MHZ_PM 0x53 | |
180 | #define SETB_PCIX_133MHZ_PM 0x54 | |
181 | #define SETB_PCIX_66MHZ_EM 0x55 | |
182 | #define SETB_PCIX_100MHZ_EM 0x56 | |
183 | #define SETB_PCIX_133MHZ_EM 0x57 | |
184 | #define SETB_PCIX_66MHZ_266 0x58 | |
185 | #define SETB_PCIX_100MHZ_266 0x59 | |
186 | #define SETB_PCIX_133MHZ_266 0x5a | |
187 | #define SETB_PCIX_66MHZ_533 0x5b | |
188 | #define SETB_PCIX_100MHZ_533 0x5c | |
189 | #define SETB_PCIX_133MHZ_533 0x5d | |
190 | ||
191 | ||
192 | /* Power-on all slots - 0x48h */ | |
193 | #define SET_PWR_ON_ALL 0x48 | |
194 | ||
195 | /* Enable all slots - 0x49h */ | |
196 | #define SET_ENABLE_ALL 0x49 | |
197 | ||
198 | /* SHPC controller command error code */ | |
199 | #define SWITCH_OPEN 0x1 | |
200 | #define INVALID_CMD 0x2 | |
201 | #define INVALID_SPEED_MODE 0x4 | |
202 | ||
203 | /* For accessing SHPC Working Register Set */ | |
204 | #define DWORD_SELECT 0x2 | |
205 | #define DWORD_DATA 0x4 | |
206 | #define BASE_OFFSET 0x0 | |
207 | ||
208 | /* Field Offset in Logical Slot Register - byte boundary */ | |
209 | #define SLOT_EVENT_LATCH 0x2 | |
210 | #define SLOT_SERR_INT_MASK 0x3 | |
211 | ||
212 | static spinlock_t hpc_event_lock; | |
213 | ||
214 | DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */ | |
215 | static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */ | |
216 | static int ctlr_seq_num = 0; /* Controller sequenc # */ | |
217 | static spinlock_t list_lock; | |
218 | ||
219 | static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs); | |
220 | ||
221 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds); | |
d29aadda | 222 | static int hpc_check_cmd_status(struct controller *ctrl); |
1da177e4 | 223 | |
75d97c59 KK |
224 | static inline u8 shpc_readb(struct controller *ctrl, int reg) |
225 | { | |
226 | return readb(ctrl->hpc_ctlr_handle->creg + reg); | |
227 | } | |
228 | ||
229 | static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) | |
230 | { | |
231 | writeb(val, ctrl->hpc_ctlr_handle->creg + reg); | |
232 | } | |
233 | ||
234 | static inline u16 shpc_readw(struct controller *ctrl, int reg) | |
235 | { | |
236 | return readw(ctrl->hpc_ctlr_handle->creg + reg); | |
237 | } | |
238 | ||
239 | static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) | |
240 | { | |
241 | writew(val, ctrl->hpc_ctlr_handle->creg + reg); | |
242 | } | |
243 | ||
244 | static inline u32 shpc_readl(struct controller *ctrl, int reg) | |
245 | { | |
246 | return readl(ctrl->hpc_ctlr_handle->creg + reg); | |
247 | } | |
248 | ||
249 | static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) | |
250 | { | |
251 | writel(val, ctrl->hpc_ctlr_handle->creg + reg); | |
252 | } | |
253 | ||
254 | static inline int shpc_indirect_read(struct controller *ctrl, int index, | |
255 | u32 *value) | |
256 | { | |
257 | int rc; | |
258 | u32 cap_offset = ctrl->cap_offset; | |
259 | struct pci_dev *pdev = ctrl->pci_dev; | |
260 | ||
261 | rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index); | |
262 | if (rc) | |
263 | return rc; | |
264 | return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value); | |
265 | } | |
266 | ||
1da177e4 LT |
267 | /* This is the interrupt polling timeout function. */ |
268 | static void int_poll_timeout(unsigned long lphp_ctlr) | |
269 | { | |
270 | struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr; | |
271 | ||
272 | DBG_ENTER_ROUTINE | |
273 | ||
274 | if ( !php_ctlr ) { | |
275 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
276 | return; | |
277 | } | |
278 | ||
279 | /* Poll for interrupt events. regs == NULL => polling */ | |
280 | shpc_isr( 0, (void *)php_ctlr, NULL ); | |
281 | ||
282 | init_timer(&php_ctlr->int_poll_timer); | |
283 | if (!shpchp_poll_time) | |
284 | shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/ | |
285 | ||
286 | start_int_poll_timer(php_ctlr, shpchp_poll_time); | |
287 | ||
288 | return; | |
289 | } | |
290 | ||
291 | /* This function starts the interrupt polling timer. */ | |
292 | static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds) | |
293 | { | |
294 | if (!php_ctlr) { | |
295 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
296 | return; | |
297 | } | |
298 | ||
299 | if ( ( seconds <= 0 ) || ( seconds > 60 ) ) | |
300 | seconds = 2; /* Clamp to sane value */ | |
301 | ||
302 | php_ctlr->int_poll_timer.function = &int_poll_timeout; | |
303 | php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */ | |
304 | php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ; | |
305 | add_timer(&php_ctlr->int_poll_timer); | |
306 | ||
307 | return; | |
308 | } | |
309 | ||
bd62e271 KK |
310 | static inline int shpc_wait_cmd(struct controller *ctrl) |
311 | { | |
312 | int retval = 0; | |
313 | unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000; | |
314 | unsigned long timeout = msecs_to_jiffies(timeout_msec); | |
315 | int rc = wait_event_interruptible_timeout(ctrl->queue, | |
316 | !ctrl->cmd_busy, timeout); | |
317 | if (!rc) { | |
318 | retval = -EIO; | |
319 | err("Command not completed in %d msec\n", timeout_msec); | |
320 | } else if (rc < 0) { | |
321 | retval = -EINTR; | |
322 | info("Command was interrupted by a signal\n"); | |
323 | } | |
324 | ctrl->cmd_busy = 0; | |
325 | ||
326 | return retval; | |
327 | } | |
328 | ||
1da177e4 LT |
329 | static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd) |
330 | { | |
ee138334 | 331 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
75d97c59 | 332 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
333 | u16 cmd_status; |
334 | int retval = 0; | |
335 | u16 temp_word; | |
336 | int i; | |
337 | ||
338 | DBG_ENTER_ROUTINE | |
d29aadda KK |
339 | |
340 | mutex_lock(&slot->ctrl->cmd_lock); | |
341 | ||
1da177e4 LT |
342 | if (!php_ctlr) { |
343 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
d29aadda KK |
344 | retval = -EINVAL; |
345 | goto out; | |
1da177e4 LT |
346 | } |
347 | ||
348 | for (i = 0; i < 10; i++) { | |
75d97c59 | 349 | cmd_status = shpc_readw(ctrl, CMD_STATUS); |
1da177e4 LT |
350 | |
351 | if (!(cmd_status & 0x1)) | |
352 | break; | |
353 | /* Check every 0.1 sec for a total of 1 sec*/ | |
354 | msleep(100); | |
355 | } | |
356 | ||
75d97c59 | 357 | cmd_status = shpc_readw(ctrl, CMD_STATUS); |
1da177e4 LT |
358 | |
359 | if (cmd_status & 0x1) { | |
360 | /* After 1 sec and and the controller is still busy */ | |
361 | err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__); | |
d29aadda KK |
362 | retval = -EBUSY; |
363 | goto out; | |
1da177e4 LT |
364 | } |
365 | ||
366 | ++t_slot; | |
367 | temp_word = (t_slot << 8) | (cmd & 0xFF); | |
368 | dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd); | |
369 | ||
370 | /* To make sure the Controller Busy bit is 0 before we send out the | |
371 | * command. | |
372 | */ | |
bd62e271 | 373 | slot->ctrl->cmd_busy = 1; |
75d97c59 | 374 | shpc_writew(ctrl, CMD, temp_word); |
1da177e4 | 375 | |
bd62e271 KK |
376 | /* |
377 | * Wait for command completion. | |
378 | */ | |
379 | retval = shpc_wait_cmd(slot->ctrl); | |
d29aadda KK |
380 | if (retval) |
381 | goto out; | |
382 | ||
383 | cmd_status = hpc_check_cmd_status(slot->ctrl); | |
384 | if (cmd_status) { | |
385 | err("%s: Failed to issued command 0x%x (error code = %d)\n", | |
386 | __FUNCTION__, cmd, cmd_status); | |
387 | retval = -EIO; | |
388 | } | |
389 | out: | |
390 | mutex_unlock(&slot->ctrl->cmd_lock); | |
bd62e271 | 391 | |
1da177e4 LT |
392 | DBG_LEAVE_ROUTINE |
393 | return retval; | |
394 | } | |
395 | ||
396 | static int hpc_check_cmd_status(struct controller *ctrl) | |
397 | { | |
1da177e4 LT |
398 | u16 cmd_status; |
399 | int retval = 0; | |
400 | ||
401 | DBG_ENTER_ROUTINE | |
402 | ||
403 | if (!ctrl->hpc_ctlr_handle) { | |
404 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
405 | return -1; | |
406 | } | |
407 | ||
75d97c59 | 408 | cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; |
1da177e4 LT |
409 | |
410 | switch (cmd_status >> 1) { | |
411 | case 0: | |
412 | retval = 0; | |
413 | break; | |
414 | case 1: | |
415 | retval = SWITCH_OPEN; | |
416 | err("%s: Switch opened!\n", __FUNCTION__); | |
417 | break; | |
418 | case 2: | |
419 | retval = INVALID_CMD; | |
420 | err("%s: Invalid HPC command!\n", __FUNCTION__); | |
421 | break; | |
422 | case 4: | |
423 | retval = INVALID_SPEED_MODE; | |
424 | err("%s: Invalid bus speed/mode!\n", __FUNCTION__); | |
425 | break; | |
426 | default: | |
427 | retval = cmd_status; | |
428 | } | |
429 | ||
430 | DBG_LEAVE_ROUTINE | |
431 | return retval; | |
432 | } | |
433 | ||
434 | ||
435 | static int hpc_get_attention_status(struct slot *slot, u8 *status) | |
436 | { | |
75d97c59 | 437 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 438 | u32 slot_reg; |
5858759c | 439 | u8 state; |
1da177e4 LT |
440 | |
441 | DBG_ENTER_ROUTINE | |
442 | ||
443 | if (!slot->ctrl->hpc_ctlr_handle) { | |
444 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
445 | return -1; | |
446 | } | |
447 | ||
2b34da7e | 448 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 449 | state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT; |
1da177e4 | 450 | |
5858759c KK |
451 | switch (state) { |
452 | case ATN_LED_STATE_ON: | |
1da177e4 LT |
453 | *status = 1; /* On */ |
454 | break; | |
5858759c | 455 | case ATN_LED_STATE_BLINK: |
1da177e4 LT |
456 | *status = 2; /* Blink */ |
457 | break; | |
5858759c | 458 | case ATN_LED_STATE_OFF: |
1da177e4 LT |
459 | *status = 0; /* Off */ |
460 | break; | |
461 | default: | |
5858759c | 462 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
463 | break; |
464 | } | |
465 | ||
466 | DBG_LEAVE_ROUTINE | |
467 | return 0; | |
468 | } | |
469 | ||
470 | static int hpc_get_power_status(struct slot * slot, u8 *status) | |
471 | { | |
75d97c59 | 472 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 473 | u32 slot_reg; |
5858759c | 474 | u8 state; |
1da177e4 LT |
475 | |
476 | DBG_ENTER_ROUTINE | |
477 | ||
478 | if (!slot->ctrl->hpc_ctlr_handle) { | |
479 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
480 | return -1; | |
481 | } | |
482 | ||
2b34da7e | 483 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 484 | state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT; |
1da177e4 | 485 | |
5858759c KK |
486 | switch (state) { |
487 | case SLOT_STATE_PWRONLY: | |
1da177e4 LT |
488 | *status = 2; /* Powered only */ |
489 | break; | |
5858759c | 490 | case SLOT_STATE_ENABLED: |
1da177e4 LT |
491 | *status = 1; /* Enabled */ |
492 | break; | |
5858759c | 493 | case SLOT_STATE_DISABLED: |
1da177e4 LT |
494 | *status = 0; /* Disabled */ |
495 | break; | |
496 | default: | |
5858759c | 497 | *status = 0xFF; /* Reserved */ |
1da177e4 LT |
498 | break; |
499 | } | |
500 | ||
501 | DBG_LEAVE_ROUTINE | |
5858759c | 502 | return 0; |
1da177e4 LT |
503 | } |
504 | ||
505 | ||
506 | static int hpc_get_latch_status(struct slot *slot, u8 *status) | |
507 | { | |
75d97c59 | 508 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 509 | u32 slot_reg; |
1da177e4 LT |
510 | |
511 | DBG_ENTER_ROUTINE | |
512 | ||
513 | if (!slot->ctrl->hpc_ctlr_handle) { | |
514 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
515 | return -1; | |
516 | } | |
517 | ||
2b34da7e | 518 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 519 | *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */ |
1da177e4 LT |
520 | |
521 | DBG_LEAVE_ROUTINE | |
522 | return 0; | |
523 | } | |
524 | ||
525 | static int hpc_get_adapter_status(struct slot *slot, u8 *status) | |
526 | { | |
75d97c59 | 527 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 528 | u32 slot_reg; |
5858759c | 529 | u8 state; |
1da177e4 LT |
530 | |
531 | DBG_ENTER_ROUTINE | |
532 | ||
533 | if (!slot->ctrl->hpc_ctlr_handle) { | |
534 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
535 | return -1; | |
536 | } | |
537 | ||
2b34da7e | 538 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c KK |
539 | state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT; |
540 | *status = (state != 0x3) ? 1 : 0; | |
1da177e4 LT |
541 | |
542 | DBG_LEAVE_ROUTINE | |
543 | return 0; | |
544 | } | |
545 | ||
546 | static int hpc_get_prog_int(struct slot *slot, u8 *prog_int) | |
547 | { | |
75d97c59 | 548 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
549 | |
550 | DBG_ENTER_ROUTINE | |
551 | ||
552 | if (!slot->ctrl->hpc_ctlr_handle) { | |
553 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
554 | return -1; | |
555 | } | |
556 | ||
75d97c59 | 557 | *prog_int = shpc_readb(ctrl, PROG_INTERFACE); |
1da177e4 LT |
558 | |
559 | DBG_LEAVE_ROUTINE | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) | |
564 | { | |
1da177e4 | 565 | int retval = 0; |
75d97c59 | 566 | struct controller *ctrl = slot->ctrl; |
2b34da7e | 567 | u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
5858759c | 568 | u8 m66_cap = !!(slot_reg & MHZ66_CAP); |
795eb5c4 | 569 | u8 pi, pcix_cap; |
1da177e4 LT |
570 | |
571 | DBG_ENTER_ROUTINE | |
572 | ||
795eb5c4 KK |
573 | if ((retval = hpc_get_prog_int(slot, &pi))) |
574 | return retval; | |
575 | ||
576 | switch (pi) { | |
577 | case 1: | |
578 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT; | |
579 | break; | |
580 | case 2: | |
581 | pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT; | |
582 | break; | |
583 | default: | |
584 | return -ENODEV; | |
585 | } | |
586 | ||
0afabe90 KK |
587 | dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", |
588 | __FUNCTION__, slot_reg, pcix_cap, m66_cap); | |
1da177e4 | 589 | |
0afabe90 KK |
590 | switch (pcix_cap) { |
591 | case 0x0: | |
592 | *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; | |
593 | break; | |
594 | case 0x1: | |
595 | *value = PCI_SPEED_66MHz_PCIX; | |
596 | break; | |
597 | case 0x3: | |
598 | *value = PCI_SPEED_133MHz_PCIX; | |
599 | break; | |
600 | case 0x4: | |
601 | *value = PCI_SPEED_133MHz_PCIX_266; | |
602 | break; | |
603 | case 0x5: | |
604 | *value = PCI_SPEED_133MHz_PCIX_533; | |
605 | break; | |
606 | case 0x2: | |
607 | default: | |
608 | *value = PCI_SPEED_UNKNOWN; | |
609 | retval = -ENODEV; | |
610 | break; | |
1da177e4 LT |
611 | } |
612 | ||
613 | dbg("Adapter speed = %d\n", *value); | |
1da177e4 LT |
614 | DBG_LEAVE_ROUTINE |
615 | return retval; | |
616 | } | |
617 | ||
618 | static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode) | |
619 | { | |
75d97c59 | 620 | struct controller *ctrl = slot->ctrl; |
1da177e4 LT |
621 | u16 sec_bus_status; |
622 | u8 pi; | |
623 | int retval = 0; | |
624 | ||
625 | DBG_ENTER_ROUTINE | |
626 | ||
627 | if (!slot->ctrl->hpc_ctlr_handle) { | |
628 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
629 | return -1; | |
630 | } | |
631 | ||
75d97c59 KK |
632 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
633 | sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); | |
1da177e4 LT |
634 | |
635 | if (pi == 2) { | |
87d6c559 | 636 | *mode = (sec_bus_status & 0x0100) >> 8; |
1da177e4 LT |
637 | } else { |
638 | retval = -1; | |
639 | } | |
640 | ||
641 | dbg("Mode 1 ECC cap = %d\n", *mode); | |
642 | ||
643 | DBG_LEAVE_ROUTINE | |
644 | return retval; | |
645 | } | |
646 | ||
647 | static int hpc_query_power_fault(struct slot * slot) | |
648 | { | |
75d97c59 | 649 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 650 | u32 slot_reg; |
1da177e4 LT |
651 | |
652 | DBG_ENTER_ROUTINE | |
653 | ||
654 | if (!slot->ctrl->hpc_ctlr_handle) { | |
655 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
656 | return -1; | |
657 | } | |
658 | ||
2b34da7e | 659 | slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); |
1da177e4 LT |
660 | |
661 | DBG_LEAVE_ROUTINE | |
662 | /* Note: Logic 0 => fault */ | |
5858759c | 663 | return !(slot_reg & POWER_FAULT); |
1da177e4 LT |
664 | } |
665 | ||
666 | static int hpc_set_attention_status(struct slot *slot, u8 value) | |
667 | { | |
ee138334 | 668 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
669 | u8 slot_cmd = 0; |
670 | int rc = 0; | |
671 | ||
672 | if (!slot->ctrl->hpc_ctlr_handle) { | |
673 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
674 | return -1; | |
675 | } | |
676 | ||
677 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
678 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
679 | return -1; | |
680 | } | |
681 | ||
682 | switch (value) { | |
683 | case 0 : | |
684 | slot_cmd = 0x30; /* OFF */ | |
685 | break; | |
686 | case 1: | |
687 | slot_cmd = 0x10; /* ON */ | |
688 | break; | |
689 | case 2: | |
690 | slot_cmd = 0x20; /* BLINK */ | |
691 | break; | |
692 | default: | |
693 | return -1; | |
694 | } | |
695 | ||
696 | shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
697 | ||
698 | return rc; | |
699 | } | |
700 | ||
701 | ||
702 | static void hpc_set_green_led_on(struct slot *slot) | |
703 | { | |
ee138334 | 704 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
705 | u8 slot_cmd; |
706 | ||
707 | if (!slot->ctrl->hpc_ctlr_handle) { | |
708 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
709 | return ; | |
710 | } | |
711 | ||
712 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
713 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
714 | return ; | |
715 | } | |
716 | ||
717 | slot_cmd = 0x04; | |
718 | ||
719 | shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
720 | ||
721 | return; | |
722 | } | |
723 | ||
724 | static void hpc_set_green_led_off(struct slot *slot) | |
725 | { | |
ee138334 | 726 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
727 | u8 slot_cmd; |
728 | ||
729 | if (!slot->ctrl->hpc_ctlr_handle) { | |
730 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
731 | return ; | |
732 | } | |
733 | ||
734 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
735 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
736 | return ; | |
737 | } | |
738 | ||
739 | slot_cmd = 0x0C; | |
740 | ||
741 | shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
742 | ||
743 | return; | |
744 | } | |
745 | ||
746 | static void hpc_set_green_led_blink(struct slot *slot) | |
747 | { | |
ee138334 | 748 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
749 | u8 slot_cmd; |
750 | ||
751 | if (!slot->ctrl->hpc_ctlr_handle) { | |
752 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
753 | return ; | |
754 | } | |
755 | ||
756 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
757 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
758 | return ; | |
759 | } | |
760 | ||
761 | slot_cmd = 0x08; | |
762 | ||
763 | shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
764 | ||
765 | return; | |
766 | } | |
767 | ||
768 | int shpc_get_ctlr_slot_config(struct controller *ctrl, | |
769 | int *num_ctlr_slots, /* number of slots in this HPC */ | |
770 | int *first_device_num, /* PCI dev num of the first slot in this SHPC */ | |
771 | int *physical_slot_num, /* phy slot num of the first slot in this SHPC */ | |
772 | int *updown, /* physical_slot_num increament: 1 or -1 */ | |
773 | int *flags) | |
774 | { | |
75d97c59 | 775 | u32 slot_config; |
1da177e4 LT |
776 | |
777 | DBG_ENTER_ROUTINE | |
778 | ||
779 | if (!ctrl->hpc_ctlr_handle) { | |
780 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
781 | return -1; | |
782 | } | |
783 | ||
75d97c59 KK |
784 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
785 | *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8; | |
786 | *num_ctlr_slots = slot_config & SLOT_NUM; | |
787 | *physical_slot_num = (slot_config & PSN) >> 16; | |
788 | *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1; | |
1da177e4 | 789 | |
1da177e4 | 790 | dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num); |
1da177e4 LT |
791 | |
792 | DBG_LEAVE_ROUTINE | |
793 | return 0; | |
794 | } | |
795 | ||
796 | static void hpc_release_ctlr(struct controller *ctrl) | |
797 | { | |
ee138334 | 798 | struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle; |
1da177e4 | 799 | struct php_ctlr_state_s *p, *p_prev; |
f7391f53 | 800 | int i; |
795eb5c4 | 801 | u32 slot_reg; |
1da177e4 LT |
802 | |
803 | DBG_ENTER_ROUTINE | |
804 | ||
805 | if (!ctrl->hpc_ctlr_handle) { | |
806 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
807 | return ; | |
808 | } | |
809 | ||
f7391f53 | 810 | /* |
795eb5c4 | 811 | * Mask event interrupts and SERRs of all slots |
f7391f53 | 812 | */ |
795eb5c4 KK |
813 | for (i = 0; i < ctrl->num_slots; i++) { |
814 | slot_reg = shpc_readl(ctrl, SLOT_REG(i)); | |
815 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | | |
816 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
817 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | |
818 | CON_PFAULT_SERR_MASK); | |
819 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
820 | shpc_writel(ctrl, SLOT_REG(i), slot_reg); | |
821 | } | |
f7391f53 KK |
822 | |
823 | cleanup_slots(ctrl); | |
824 | ||
1da177e4 LT |
825 | if (shpchp_poll_mode) { |
826 | del_timer(&php_ctlr->int_poll_timer); | |
827 | } else { | |
828 | if (php_ctlr->irq) { | |
829 | free_irq(php_ctlr->irq, ctrl); | |
830 | php_ctlr->irq = 0; | |
831 | pci_disable_msi(php_ctlr->pci_dev); | |
832 | } | |
833 | } | |
f7391f53 | 834 | |
1da177e4 | 835 | if (php_ctlr->pci_dev) { |
1da177e4 | 836 | iounmap(php_ctlr->creg); |
0455986c | 837 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); |
1da177e4 LT |
838 | php_ctlr->pci_dev = NULL; |
839 | } | |
840 | ||
841 | spin_lock(&list_lock); | |
842 | p = php_ctlr_list_head; | |
843 | p_prev = NULL; | |
844 | while (p) { | |
845 | if (p == php_ctlr) { | |
846 | if (p_prev) | |
847 | p_prev->pnext = p->pnext; | |
848 | else | |
849 | php_ctlr_list_head = p->pnext; | |
850 | break; | |
851 | } else { | |
852 | p_prev = p; | |
853 | p = p->pnext; | |
854 | } | |
855 | } | |
856 | spin_unlock(&list_lock); | |
857 | ||
858 | kfree(php_ctlr); | |
859 | ||
860 | DBG_LEAVE_ROUTINE | |
861 | ||
862 | } | |
863 | ||
864 | static int hpc_power_on_slot(struct slot * slot) | |
865 | { | |
ee138334 | 866 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
867 | u8 slot_cmd; |
868 | int retval = 0; | |
869 | ||
870 | DBG_ENTER_ROUTINE | |
871 | ||
872 | if (!slot->ctrl->hpc_ctlr_handle) { | |
873 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
874 | return -1; | |
875 | } | |
876 | ||
877 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
878 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
879 | return -1; | |
880 | } | |
881 | slot_cmd = 0x01; | |
882 | ||
883 | retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
884 | ||
885 | if (retval) { | |
886 | err("%s: Write command failed!\n", __FUNCTION__); | |
887 | return -1; | |
888 | } | |
889 | ||
890 | DBG_LEAVE_ROUTINE | |
891 | ||
892 | return retval; | |
893 | } | |
894 | ||
895 | static int hpc_slot_enable(struct slot * slot) | |
896 | { | |
ee138334 | 897 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
898 | u8 slot_cmd; |
899 | int retval = 0; | |
900 | ||
901 | DBG_ENTER_ROUTINE | |
902 | ||
903 | if (!slot->ctrl->hpc_ctlr_handle) { | |
904 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
905 | return -1; | |
906 | } | |
907 | ||
908 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
909 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
910 | return -1; | |
911 | } | |
912 | /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */ | |
913 | slot_cmd = 0x3A; | |
914 | ||
915 | retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
916 | ||
917 | if (retval) { | |
918 | err("%s: Write command failed!\n", __FUNCTION__); | |
919 | return -1; | |
920 | } | |
921 | ||
922 | DBG_LEAVE_ROUTINE | |
923 | return retval; | |
924 | } | |
925 | ||
926 | static int hpc_slot_disable(struct slot * slot) | |
927 | { | |
ee138334 | 928 | struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; |
1da177e4 LT |
929 | u8 slot_cmd; |
930 | int retval = 0; | |
931 | ||
932 | DBG_ENTER_ROUTINE | |
933 | ||
934 | if (!slot->ctrl->hpc_ctlr_handle) { | |
935 | err("%s: Invalid HPC controller handle!\n", __FUNCTION__); | |
936 | return -1; | |
937 | } | |
938 | ||
939 | if (slot->hp_slot >= php_ctlr->num_slots) { | |
940 | err("%s: Invalid HPC slot number!\n", __FUNCTION__); | |
941 | return -1; | |
942 | } | |
943 | ||
944 | /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */ | |
945 | slot_cmd = 0x1F; | |
946 | ||
947 | retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd); | |
948 | ||
949 | if (retval) { | |
950 | err("%s: Write command failed!\n", __FUNCTION__); | |
951 | return -1; | |
952 | } | |
953 | ||
954 | DBG_LEAVE_ROUTINE | |
955 | return retval; | |
956 | } | |
957 | ||
1da177e4 LT |
958 | static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) |
959 | { | |
0afabe90 | 960 | int retval; |
75d97c59 | 961 | struct controller *ctrl = slot->ctrl; |
0afabe90 | 962 | u8 pi, cmd; |
1da177e4 LT |
963 | |
964 | DBG_ENTER_ROUTINE | |
1da177e4 | 965 | |
75d97c59 | 966 | pi = shpc_readb(ctrl, PROG_INTERFACE); |
0afabe90 KK |
967 | if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX)) |
968 | return -EINVAL; | |
1da177e4 | 969 | |
0afabe90 KK |
970 | switch (value) { |
971 | case PCI_SPEED_33MHz: | |
972 | cmd = SETA_PCI_33MHZ; | |
973 | break; | |
974 | case PCI_SPEED_66MHz: | |
975 | cmd = SETA_PCI_66MHZ; | |
976 | break; | |
977 | case PCI_SPEED_66MHz_PCIX: | |
978 | cmd = SETA_PCIX_66MHZ; | |
979 | break; | |
980 | case PCI_SPEED_100MHz_PCIX: | |
981 | cmd = SETA_PCIX_100MHZ; | |
982 | break; | |
983 | case PCI_SPEED_133MHz_PCIX: | |
984 | cmd = SETA_PCIX_133MHZ; | |
985 | break; | |
986 | case PCI_SPEED_66MHz_PCIX_ECC: | |
987 | cmd = SETB_PCIX_66MHZ_EM; | |
988 | break; | |
989 | case PCI_SPEED_100MHz_PCIX_ECC: | |
990 | cmd = SETB_PCIX_100MHZ_EM; | |
991 | break; | |
992 | case PCI_SPEED_133MHz_PCIX_ECC: | |
993 | cmd = SETB_PCIX_133MHZ_EM; | |
994 | break; | |
995 | case PCI_SPEED_66MHz_PCIX_266: | |
996 | cmd = SETB_PCIX_66MHZ_266; | |
997 | break; | |
998 | case PCI_SPEED_100MHz_PCIX_266: | |
999 | cmd = SETB_PCIX_100MHZ_266; | |
1000 | break; | |
1001 | case PCI_SPEED_133MHz_PCIX_266: | |
1002 | cmd = SETB_PCIX_133MHZ_266; | |
1003 | break; | |
1004 | case PCI_SPEED_66MHz_PCIX_533: | |
1005 | cmd = SETB_PCIX_66MHZ_533; | |
1006 | break; | |
1007 | case PCI_SPEED_100MHz_PCIX_533: | |
1008 | cmd = SETB_PCIX_100MHZ_533; | |
1009 | break; | |
1010 | case PCI_SPEED_133MHz_PCIX_533: | |
1011 | cmd = SETB_PCIX_133MHZ_533; | |
1012 | break; | |
1013 | default: | |
1014 | return -EINVAL; | |
1da177e4 | 1015 | } |
0afabe90 KK |
1016 | |
1017 | retval = shpc_write_cmd(slot, 0, cmd); | |
1018 | if (retval) | |
1da177e4 | 1019 | err("%s: Write command failed!\n", __FUNCTION__); |
1da177e4 LT |
1020 | |
1021 | DBG_LEAVE_ROUTINE | |
1022 | return retval; | |
1023 | } | |
1024 | ||
1025 | static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs) | |
1026 | { | |
1027 | struct controller *ctrl = NULL; | |
1028 | struct php_ctlr_state_s *php_ctlr; | |
1029 | u8 schedule_flag = 0; | |
1da177e4 LT |
1030 | u32 temp_dword, intr_loc, intr_loc2; |
1031 | int hp_slot; | |
1032 | ||
1033 | if (!dev_id) | |
1034 | return IRQ_NONE; | |
1035 | ||
1036 | if (!shpchp_poll_mode) { | |
1037 | ctrl = (struct controller *)dev_id; | |
1038 | php_ctlr = ctrl->hpc_ctlr_handle; | |
1039 | } else { | |
1040 | php_ctlr = (struct php_ctlr_state_s *) dev_id; | |
1041 | ctrl = (struct controller *)php_ctlr->callback_instance_id; | |
1042 | } | |
1043 | ||
1044 | if (!ctrl) | |
1045 | return IRQ_NONE; | |
1046 | ||
1047 | if (!php_ctlr || !php_ctlr->creg) | |
1048 | return IRQ_NONE; | |
1049 | ||
1050 | /* Check to see if it was our interrupt */ | |
75d97c59 | 1051 | intr_loc = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
1052 | |
1053 | if (!intr_loc) | |
1054 | return IRQ_NONE; | |
1da177e4 LT |
1055 | dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); |
1056 | ||
1057 | if(!shpchp_poll_mode) { | |
1058 | /* Mask Global Interrupt Mask - see implementation note on p. 139 */ | |
1059 | /* of SHPC spec rev 1.0*/ | |
75d97c59 | 1060 | temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
e7138723 KK |
1061 | temp_dword |= GLOBAL_INTR_MASK; |
1062 | temp_dword &= ~SERR_INTR_RSVDZ_MASK; | |
75d97c59 | 1063 | shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword); |
1da177e4 | 1064 | |
75d97c59 | 1065 | intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
1066 | dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); |
1067 | } | |
1068 | ||
1069 | if (intr_loc & 0x0001) { | |
1070 | /* | |
1071 | * Command Complete Interrupt Pending | |
f467f618 | 1072 | * RO only - clear by writing 1 to the Command Completion |
1da177e4 LT |
1073 | * Detect bit in Controller SERR-INT register |
1074 | */ | |
75d97c59 | 1075 | temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
e7138723 | 1076 | temp_dword &= ~SERR_INTR_RSVDZ_MASK; |
75d97c59 | 1077 | shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword); |
bd62e271 | 1078 | ctrl->cmd_busy = 0; |
1da177e4 LT |
1079 | wake_up_interruptible(&ctrl->queue); |
1080 | } | |
1081 | ||
e4e73041 KK |
1082 | if ((intr_loc = (intr_loc >> 1)) == 0) |
1083 | goto out; | |
1da177e4 LT |
1084 | |
1085 | for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { | |
1086 | /* To find out which slot has interrupt pending */ | |
1087 | if ((intr_loc >> hp_slot) & 0x01) { | |
2b34da7e | 1088 | temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
7c8942f9 RS |
1089 | dbg("%s: Slot %x with intr, slot register = %x\n", |
1090 | __FUNCTION__, hp_slot, temp_dword); | |
5858759c KK |
1091 | if ((php_ctlr->switch_change_callback) && |
1092 | (temp_dword & MRL_CHANGE_DETECTED)) | |
1da177e4 LT |
1093 | schedule_flag += php_ctlr->switch_change_callback( |
1094 | hp_slot, php_ctlr->callback_instance_id); | |
5858759c KK |
1095 | if ((php_ctlr->attention_button_callback) && |
1096 | (temp_dword & BUTTON_PRESS_DETECTED)) | |
1da177e4 LT |
1097 | schedule_flag += php_ctlr->attention_button_callback( |
1098 | hp_slot, php_ctlr->callback_instance_id); | |
5858759c KK |
1099 | if ((php_ctlr->presence_change_callback) && |
1100 | (temp_dword & PRSNT_CHANGE_DETECTED)) | |
1da177e4 LT |
1101 | schedule_flag += php_ctlr->presence_change_callback( |
1102 | hp_slot , php_ctlr->callback_instance_id); | |
5858759c KK |
1103 | if ((php_ctlr->power_fault_callback) && |
1104 | (temp_dword & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))) | |
1da177e4 LT |
1105 | schedule_flag += php_ctlr->power_fault_callback( |
1106 | hp_slot, php_ctlr->callback_instance_id); | |
1107 | ||
1108 | /* Clear all slot events */ | |
795eb5c4 | 1109 | temp_dword &= ~SLOT_REG_RSVDZ_MASK; |
2b34da7e | 1110 | shpc_writel(ctrl, SLOT_REG(hp_slot), temp_dword); |
1da177e4 | 1111 | |
75d97c59 | 1112 | intr_loc2 = shpc_readl(ctrl, INTR_LOC); |
1da177e4 LT |
1113 | dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); |
1114 | } | |
1115 | } | |
e4e73041 | 1116 | out: |
1da177e4 LT |
1117 | if (!shpchp_poll_mode) { |
1118 | /* Unmask Global Interrupt Mask */ | |
75d97c59 | 1119 | temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
e7138723 | 1120 | temp_dword &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); |
75d97c59 | 1121 | shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword); |
1da177e4 LT |
1122 | } |
1123 | ||
1124 | return IRQ_HANDLED; | |
1125 | } | |
1126 | ||
1127 | static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |
1128 | { | |
0afabe90 | 1129 | int retval = 0; |
75d97c59 | 1130 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 1131 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
1132 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); |
1133 | u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); | |
1134 | u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); | |
1da177e4 LT |
1135 | |
1136 | DBG_ENTER_ROUTINE | |
1137 | ||
1da177e4 | 1138 | if (pi == 2) { |
6558b6ab | 1139 | if (slot_avail2 & SLOT_133MHZ_PCIX_533) |
0afabe90 | 1140 | bus_speed = PCI_SPEED_133MHz_PCIX_533; |
6558b6ab | 1141 | else if (slot_avail2 & SLOT_100MHZ_PCIX_533) |
0afabe90 | 1142 | bus_speed = PCI_SPEED_100MHz_PCIX_533; |
6558b6ab | 1143 | else if (slot_avail2 & SLOT_66MHZ_PCIX_533) |
0afabe90 | 1144 | bus_speed = PCI_SPEED_66MHz_PCIX_533; |
6558b6ab | 1145 | else if (slot_avail2 & SLOT_133MHZ_PCIX_266) |
0afabe90 | 1146 | bus_speed = PCI_SPEED_133MHz_PCIX_266; |
6558b6ab | 1147 | else if (slot_avail2 & SLOT_100MHZ_PCIX_266) |
0afabe90 | 1148 | bus_speed = PCI_SPEED_100MHz_PCIX_266; |
6558b6ab | 1149 | else if (slot_avail2 & SLOT_66MHZ_PCIX_266) |
0afabe90 KK |
1150 | bus_speed = PCI_SPEED_66MHz_PCIX_266; |
1151 | } | |
1152 | ||
1153 | if (bus_speed == PCI_SPEED_UNKNOWN) { | |
6558b6ab | 1154 | if (slot_avail1 & SLOT_133MHZ_PCIX) |
0afabe90 | 1155 | bus_speed = PCI_SPEED_133MHz_PCIX; |
6558b6ab | 1156 | else if (slot_avail1 & SLOT_100MHZ_PCIX) |
0afabe90 | 1157 | bus_speed = PCI_SPEED_100MHz_PCIX; |
6558b6ab | 1158 | else if (slot_avail1 & SLOT_66MHZ_PCIX) |
0afabe90 | 1159 | bus_speed = PCI_SPEED_66MHz_PCIX; |
6558b6ab | 1160 | else if (slot_avail2 & SLOT_66MHZ) |
0afabe90 | 1161 | bus_speed = PCI_SPEED_66MHz; |
6558b6ab | 1162 | else if (slot_avail1 & SLOT_33MHZ) |
0afabe90 KK |
1163 | bus_speed = PCI_SPEED_33MHz; |
1164 | else | |
1165 | retval = -ENODEV; | |
1da177e4 LT |
1166 | } |
1167 | ||
1168 | *value = bus_speed; | |
1169 | dbg("Max bus speed = %d\n", bus_speed); | |
1170 | DBG_LEAVE_ROUTINE | |
1171 | return retval; | |
1172 | } | |
1173 | ||
1174 | static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) | |
1175 | { | |
0afabe90 | 1176 | int retval = 0; |
75d97c59 | 1177 | struct controller *ctrl = slot->ctrl; |
1da177e4 | 1178 | enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; |
75d97c59 KK |
1179 | u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); |
1180 | u8 pi = shpc_readb(ctrl, PROG_INTERFACE); | |
0afabe90 | 1181 | u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7); |
1da177e4 LT |
1182 | |
1183 | DBG_ENTER_ROUTINE | |
1184 | ||
0afabe90 KK |
1185 | if ((pi == 1) && (speed_mode > 4)) { |
1186 | *value = PCI_SPEED_UNKNOWN; | |
1187 | return -ENODEV; | |
1da177e4 LT |
1188 | } |
1189 | ||
0afabe90 KK |
1190 | switch (speed_mode) { |
1191 | case 0x0: | |
1192 | *value = PCI_SPEED_33MHz; | |
1193 | break; | |
1194 | case 0x1: | |
1195 | *value = PCI_SPEED_66MHz; | |
1196 | break; | |
1197 | case 0x2: | |
1198 | *value = PCI_SPEED_66MHz_PCIX; | |
1199 | break; | |
1200 | case 0x3: | |
1201 | *value = PCI_SPEED_100MHz_PCIX; | |
1202 | break; | |
1203 | case 0x4: | |
1204 | *value = PCI_SPEED_133MHz_PCIX; | |
1205 | break; | |
1206 | case 0x5: | |
1207 | *value = PCI_SPEED_66MHz_PCIX_ECC; | |
1208 | break; | |
1209 | case 0x6: | |
1210 | *value = PCI_SPEED_100MHz_PCIX_ECC; | |
1211 | break; | |
1212 | case 0x7: | |
1213 | *value = PCI_SPEED_133MHz_PCIX_ECC; | |
1214 | break; | |
1215 | case 0x8: | |
1216 | *value = PCI_SPEED_66MHz_PCIX_266; | |
1217 | break; | |
1218 | case 0x9: | |
1219 | *value = PCI_SPEED_100MHz_PCIX_266; | |
1220 | break; | |
1221 | case 0xa: | |
1222 | *value = PCI_SPEED_133MHz_PCIX_266; | |
1223 | break; | |
1224 | case 0xb: | |
1225 | *value = PCI_SPEED_66MHz_PCIX_533; | |
1226 | break; | |
1227 | case 0xc: | |
1228 | *value = PCI_SPEED_100MHz_PCIX_533; | |
1229 | break; | |
1230 | case 0xd: | |
1231 | *value = PCI_SPEED_133MHz_PCIX_533; | |
1232 | break; | |
1233 | default: | |
1234 | *value = PCI_SPEED_UNKNOWN; | |
1235 | retval = -ENODEV; | |
1236 | break; | |
1da177e4 LT |
1237 | } |
1238 | ||
1da177e4 LT |
1239 | dbg("Current bus speed = %d\n", bus_speed); |
1240 | DBG_LEAVE_ROUTINE | |
1241 | return retval; | |
1242 | } | |
1243 | ||
1244 | static struct hpc_ops shpchp_hpc_ops = { | |
1245 | .power_on_slot = hpc_power_on_slot, | |
1246 | .slot_enable = hpc_slot_enable, | |
1247 | .slot_disable = hpc_slot_disable, | |
1da177e4 LT |
1248 | .set_bus_speed_mode = hpc_set_bus_speed_mode, |
1249 | .set_attention_status = hpc_set_attention_status, | |
1250 | .get_power_status = hpc_get_power_status, | |
1251 | .get_attention_status = hpc_get_attention_status, | |
1252 | .get_latch_status = hpc_get_latch_status, | |
1253 | .get_adapter_status = hpc_get_adapter_status, | |
1254 | ||
1255 | .get_max_bus_speed = hpc_get_max_bus_speed, | |
1256 | .get_cur_bus_speed = hpc_get_cur_bus_speed, | |
1257 | .get_adapter_speed = hpc_get_adapter_speed, | |
1258 | .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap, | |
1259 | .get_prog_int = hpc_get_prog_int, | |
1260 | ||
1261 | .query_power_fault = hpc_query_power_fault, | |
1262 | .green_led_on = hpc_set_green_led_on, | |
1263 | .green_led_off = hpc_set_green_led_off, | |
1264 | .green_led_blink = hpc_set_green_led_blink, | |
1265 | ||
1266 | .release_ctlr = hpc_release_ctlr, | |
1da177e4 LT |
1267 | }; |
1268 | ||
ee138334 | 1269 | int shpc_init(struct controller * ctrl, struct pci_dev * pdev) |
1da177e4 LT |
1270 | { |
1271 | struct php_ctlr_state_s *php_ctlr, *p; | |
1272 | void *instance_id = ctrl; | |
0455986c | 1273 | int rc, num_slots = 0; |
1da177e4 LT |
1274 | u8 hp_slot; |
1275 | static int first = 1; | |
0455986c | 1276 | u32 shpc_base_offset; |
75d97c59 | 1277 | u32 tempdword, slot_reg, slot_config; |
1da177e4 LT |
1278 | u8 i; |
1279 | ||
1280 | DBG_ENTER_ROUTINE | |
1281 | ||
0455986c KK |
1282 | ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ |
1283 | ||
1da177e4 | 1284 | spin_lock_init(&list_lock); |
57c95c0d | 1285 | php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL); |
1da177e4 LT |
1286 | |
1287 | if (!php_ctlr) { /* allocate controller state data */ | |
1288 | err("%s: HPC controller memory allocation error!\n", __FUNCTION__); | |
1289 | goto abort; | |
1290 | } | |
1291 | ||
1da177e4 LT |
1292 | php_ctlr->pci_dev = pdev; /* save pci_dev in context */ |
1293 | ||
ee138334 RS |
1294 | if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == |
1295 | PCI_DEVICE_ID_AMD_GOLAM_7450)) { | |
0455986c KK |
1296 | /* amd shpc driver doesn't use Base Offset; assume 0 */ |
1297 | ctrl->mmio_base = pci_resource_start(pdev, 0); | |
1298 | ctrl->mmio_size = pci_resource_len(pdev, 0); | |
1da177e4 | 1299 | } else { |
0455986c KK |
1300 | ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); |
1301 | if (!ctrl->cap_offset) { | |
1302 | err("%s : cap_offset == 0\n", __FUNCTION__); | |
1da177e4 LT |
1303 | goto abort_free_ctlr; |
1304 | } | |
0455986c KK |
1305 | dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset); |
1306 | ||
75d97c59 | 1307 | rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); |
1da177e4 | 1308 | if (rc) { |
0455986c | 1309 | err("%s: cannot read base_offset\n", __FUNCTION__); |
1da177e4 LT |
1310 | goto abort_free_ctlr; |
1311 | } | |
0455986c | 1312 | |
75d97c59 | 1313 | rc = shpc_indirect_read(ctrl, 3, &tempdword); |
1da177e4 | 1314 | if (rc) { |
0455986c | 1315 | err("%s: cannot read slot config\n", __FUNCTION__); |
1da177e4 LT |
1316 | goto abort_free_ctlr; |
1317 | } | |
0455986c KK |
1318 | num_slots = tempdword & SLOT_NUM; |
1319 | dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots); | |
1da177e4 | 1320 | |
0455986c | 1321 | for (i = 0; i < 9 + num_slots; i++) { |
75d97c59 | 1322 | rc = shpc_indirect_read(ctrl, i, &tempdword); |
1da177e4 | 1323 | if (rc) { |
0455986c KK |
1324 | err("%s: cannot read creg (index = %d)\n", |
1325 | __FUNCTION__, i); | |
1da177e4 LT |
1326 | goto abort_free_ctlr; |
1327 | } | |
7c8942f9 RS |
1328 | dbg("%s: offset %d: value %x\n", __FUNCTION__,i, |
1329 | tempdword); | |
1da177e4 | 1330 | } |
0455986c KK |
1331 | |
1332 | ctrl->mmio_base = | |
1333 | pci_resource_start(pdev, 0) + shpc_base_offset; | |
1334 | ctrl->mmio_size = 0x24 + 0x4 * num_slots; | |
1da177e4 LT |
1335 | } |
1336 | ||
1337 | if (first) { | |
1338 | spin_lock_init(&hpc_event_lock); | |
1339 | first = 0; | |
1340 | } | |
1341 | ||
1da177e4 LT |
1342 | info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, |
1343 | pdev->subsystem_device); | |
1344 | ||
1345 | if (pci_enable_device(pdev)) | |
1346 | goto abort_free_ctlr; | |
1347 | ||
0455986c | 1348 | if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { |
1da177e4 LT |
1349 | err("%s: cannot reserve MMIO region\n", __FUNCTION__); |
1350 | goto abort_free_ctlr; | |
1351 | } | |
1352 | ||
0455986c | 1353 | php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); |
1da177e4 | 1354 | if (!php_ctlr->creg) { |
0455986c KK |
1355 | err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, |
1356 | ctrl->mmio_size, ctrl->mmio_base); | |
1357 | release_mem_region(ctrl->mmio_base, ctrl->mmio_size); | |
1da177e4 LT |
1358 | goto abort_free_ctlr; |
1359 | } | |
1360 | dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg); | |
1da177e4 | 1361 | |
6aa4cdd0 | 1362 | mutex_init(&ctrl->crit_sect); |
d29aadda KK |
1363 | mutex_init(&ctrl->cmd_lock); |
1364 | ||
1da177e4 LT |
1365 | /* Setup wait queue */ |
1366 | init_waitqueue_head(&ctrl->queue); | |
1367 | ||
1368 | /* Find the IRQ */ | |
1369 | php_ctlr->irq = pdev->irq; | |
ee138334 RS |
1370 | php_ctlr->attention_button_callback = shpchp_handle_attention_button, |
1371 | php_ctlr->switch_change_callback = shpchp_handle_switch_change; | |
1372 | php_ctlr->presence_change_callback = shpchp_handle_presence_change; | |
1373 | php_ctlr->power_fault_callback = shpchp_handle_power_fault; | |
1da177e4 LT |
1374 | php_ctlr->callback_instance_id = instance_id; |
1375 | ||
75d97c59 KK |
1376 | ctrl->hpc_ctlr_handle = php_ctlr; |
1377 | ctrl->hpc_ops = &shpchp_hpc_ops; | |
1378 | ||
1da177e4 | 1379 | /* Return PCI Controller Info */ |
75d97c59 KK |
1380 | slot_config = shpc_readl(ctrl, SLOT_CONFIG); |
1381 | php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; | |
1382 | php_ctlr->num_slots = slot_config & SLOT_NUM; | |
1da177e4 LT |
1383 | dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset); |
1384 | dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots); | |
1385 | ||
1386 | /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */ | |
75d97c59 | 1387 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
1da177e4 | 1388 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
e7138723 KK |
1389 | tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | |
1390 | COMMAND_INTR_MASK | ARBITER_SERR_MASK); | |
1391 | tempdword &= ~SERR_INTR_RSVDZ_MASK; | |
75d97c59 KK |
1392 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1393 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
1da177e4 LT |
1394 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1395 | ||
1396 | /* Mask the MRL sensor SERR Mask of individual slot in | |
1397 | * Slot SERR-INT Mask & clear all the existing event if any | |
1398 | */ | |
1399 | for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { | |
2b34da7e | 1400 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1da177e4 LT |
1401 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, |
1402 | hp_slot, slot_reg); | |
795eb5c4 KK |
1403 | slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1404 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
1405 | CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK | | |
1406 | CON_PFAULT_SERR_MASK); | |
1407 | slot_reg &= ~SLOT_REG_RSVDZ_MASK; | |
1408 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 LT |
1409 | } |
1410 | ||
1411 | if (shpchp_poll_mode) {/* Install interrupt polling code */ | |
1412 | /* Install and start the interrupt polling timer */ | |
1413 | init_timer(&php_ctlr->int_poll_timer); | |
1414 | start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */ | |
1415 | } else { | |
1416 | /* Installs the interrupt handler */ | |
1417 | rc = pci_enable_msi(pdev); | |
1418 | if (rc) { | |
1419 | info("Can't get msi for the hotplug controller\n"); | |
1420 | info("Use INTx for the hotplug controller\n"); | |
1da177e4 LT |
1421 | } else |
1422 | php_ctlr->irq = pdev->irq; | |
1423 | ||
1424 | rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl); | |
1425 | dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc); | |
1426 | if (rc) { | |
1427 | err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq); | |
1428 | goto abort_free_ctlr; | |
1429 | } | |
1da177e4 | 1430 | } |
7c8942f9 RS |
1431 | dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__, |
1432 | pdev->bus->number, PCI_SLOT(pdev->devfn), | |
1433 | PCI_FUNC(pdev->devfn), pdev->irq); | |
424600f9 | 1434 | get_hp_hw_control_from_firmware(pdev); |
1da177e4 LT |
1435 | |
1436 | /* Add this HPC instance into the HPC list */ | |
1437 | spin_lock(&list_lock); | |
1438 | if (php_ctlr_list_head == 0) { | |
1439 | php_ctlr_list_head = php_ctlr; | |
1440 | p = php_ctlr_list_head; | |
1441 | p->pnext = NULL; | |
1442 | } else { | |
1443 | p = php_ctlr_list_head; | |
1444 | ||
1445 | while (p->pnext) | |
1446 | p = p->pnext; | |
1447 | ||
1448 | p->pnext = php_ctlr; | |
1449 | } | |
1450 | spin_unlock(&list_lock); | |
1451 | ||
1da177e4 | 1452 | ctlr_seq_num++; |
1da177e4 | 1453 | |
795eb5c4 KK |
1454 | /* |
1455 | * Unmask all event interrupts of all slots | |
1456 | */ | |
1da177e4 | 1457 | for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) { |
2b34da7e | 1458 | slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); |
1da177e4 LT |
1459 | dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__, |
1460 | hp_slot, slot_reg); | |
795eb5c4 KK |
1461 | slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK | |
1462 | BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK | | |
1463 | CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK); | |
1464 | shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); | |
1da177e4 LT |
1465 | } |
1466 | if (!shpchp_poll_mode) { | |
1467 | /* Unmask all general input interrupts and SERR */ | |
75d97c59 | 1468 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); |
e7138723 KK |
1469 | tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK | |
1470 | SERR_INTR_RSVDZ_MASK); | |
75d97c59 KK |
1471 | shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); |
1472 | tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); | |
1da177e4 LT |
1473 | dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword); |
1474 | } | |
1475 | ||
1da177e4 LT |
1476 | DBG_LEAVE_ROUTINE |
1477 | return 0; | |
1478 | ||
1479 | /* We end up here for the many possible ways to fail this API. */ | |
1480 | abort_free_ctlr: | |
1481 | kfree(php_ctlr); | |
1482 | abort: | |
1483 | DBG_LEAVE_ROUTINE | |
1484 | return -1; | |
1485 | } |