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Merge git://git.kernel.org/pub/scm/linux/kernel/git/hch/xfs-icache-races
[mirror_ubuntu-artful-kernel.git] / drivers / pci / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
5e0d2a6f 35#include <linux/timer.h>
38717946 36#include <linux/iova.h>
5d450806 37#include <linux/iommu.h>
38717946 38#include <linux/intel-iommu.h>
f59c7b69 39#include <linux/sysdev.h>
ba395927 40#include <asm/cacheflush.h>
46a7fa27 41#include <asm/iommu.h>
ba395927
KA		 42#include "pci.h"
43
5b6985ce
FY		 44#define ROOT_SIZE VTD_PAGE_SIZE
45#define CONTEXT_SIZE VTD_PAGE_SIZE
46
ba395927
KA		 47#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50#define IOAPIC_RANGE_START (0xfee00000)
51#define IOAPIC_RANGE_END (0xfeefffff)
52#define IOVA_START_ADDR (0x1000)
53
54#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
4ed0d3e6
FY		 56#define MAX_AGAW_WIDTH 64
57
ba395927 58#define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
595badf5 59#define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
ba395927 60
f27be03b 61#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 62#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 63#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 64
fd18de50 65
dd4e8319
DW		 66/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67 are never going to work. */
68static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
69{
70 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
71}
72
73static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
74{
75 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
76}
77static inline unsigned long page_to_dma_pfn(struct page *pg)
78{
79 return mm_to_dma_pfn(page_to_pfn(pg));
80}
81static inline unsigned long virt_to_dma_pfn(void *p)
82{
83 return page_to_dma_pfn(virt_to_page(p));
84}
85
d9630fe9
WH		 86/* global iommu list, set NULL for ignored DMAR units */
87static struct intel_iommu **g_iommus;
88
9af88143
DW		 89static int rwbf_quirk;
90
46b08e1a
MM		 91/*
92 * 0: Present
93 * 1-11: Reserved
94 * 12-63: Context Ptr (12 - (haw-1))
95 * 64-127: Reserved
96 */
97struct root_entry {
98 u64 val;
99 u64 rsvd1;
100};
101#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102static inline bool root_present(struct root_entry *root)
103{
104 return (root->val & 1);
105}
106static inline void set_root_present(struct root_entry *root)
107{
108 root->val |= 1;
109}
110static inline void set_root_value(struct root_entry *root, unsigned long value)
111{
112 root->val |= value & VTD_PAGE_MASK;
113}
114
115static inline struct context_entry *
116get_context_addr_from_root(struct root_entry *root)
117{
118 return (struct context_entry *)
119 (root_present(root)?phys_to_virt(
120 root->val & VTD_PAGE_MASK) :
121 NULL);
122}
123
7a8fc25e
MM		 124/*
125 * low 64 bits:
126 * 0: present
127 * 1: fault processing disable
128 * 2-3: translation type
129 * 12-63: address space root
130 * high 64 bits:
131 * 0-2: address width
132 * 3-6: aval
133 * 8-23: domain id
134 */
135struct context_entry {
136 u64 lo;
137 u64 hi;
138};
c07e7d21
MM		 139
140static inline bool context_present(struct context_entry *context)
141{
142 return (context->lo & 1);
143}
144static inline void context_set_present(struct context_entry *context)
145{
146 context->lo |= 1;
147}
148
149static inline void context_set_fault_enable(struct context_entry *context)
150{
151 context->lo &= (((u64)-1) << 2) | 1;
152}
153
c07e7d21
MM		 154static inline void context_set_translation_type(struct context_entry *context,
155 unsigned long value)
156{
157 context->lo &= (((u64)-1) << 4) | 3;
158 context->lo |= (value & 3) << 2;
159}
160
161static inline void context_set_address_root(struct context_entry *context,
162 unsigned long value)
163{
164 context->lo |= value & VTD_PAGE_MASK;
165}
166
167static inline void context_set_address_width(struct context_entry *context,
168 unsigned long value)
169{
170 context->hi |= value & 7;
171}
172
173static inline void context_set_domain_id(struct context_entry *context,
174 unsigned long value)
175{
176 context->hi |= (value & ((1 << 16) - 1)) << 8;
177}
178
179static inline void context_clear_entry(struct context_entry *context)
180{
181 context->lo = 0;
182 context->hi = 0;
183}
7a8fc25e 184
622ba12a
MM		 185/*
186 * 0: readable
187 * 1: writable
188 * 2-6: reserved
189 * 7: super page
9cf06697
SY		 190 * 8-10: available
191 * 11: snoop behavior
622ba12a
MM		 192 * 12-63: Host physcial address
193 */
194struct dma_pte {
195 u64 val;
196};
622ba12a 197
19c239ce
MM		 198static inline void dma_clear_pte(struct dma_pte *pte)
199{
200 pte->val = 0;
201}
202
203static inline void dma_set_pte_readable(struct dma_pte *pte)
204{
205 pte->val |= DMA_PTE_READ;
206}
207
208static inline void dma_set_pte_writable(struct dma_pte *pte)
209{
210 pte->val |= DMA_PTE_WRITE;
211}
212
9cf06697
SY		 213static inline void dma_set_pte_snp(struct dma_pte *pte)
214{
215 pte->val |= DMA_PTE_SNP;
216}
217
19c239ce
MM		 218static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
219{
220 pte->val = (pte->val & ~3) | (prot & 3);
221}
222
223static inline u64 dma_pte_addr(struct dma_pte *pte)
224{
c85994e4
DW		 225#ifdef CONFIG_64BIT
226 return pte->val & VTD_PAGE_MASK;
227#else
228 /* Must have a full atomic 64-bit read */
229 return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
230#endif
19c239ce
MM		 231}
232
dd4e8319 233static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
19c239ce 234{
dd4e8319 235 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
19c239ce
MM		 236}
237
238static inline bool dma_pte_present(struct dma_pte *pte)
239{
240 return (pte->val & 3) != 0;
241}
622ba12a 242
75e6bf96
DW		 243static inline int first_pte_in_page(struct dma_pte *pte)
244{
245 return !((unsigned long)pte & ~VTD_PAGE_MASK);
246}
247
2c2e2c38
FY		 248/*
249 * This domain is a statically identity mapping domain.
250 * 1. This domain creats a static 1:1 mapping to all usable memory.
251 * 2. It maps to each iommu if successful.
252 * 3. Each iommu mapps to this domain if successful.
253 */
254struct dmar_domain *si_domain;
255
3b5410e7 256/* devices under the same p2p bridge are owned in one domain */
cdc7b837 257#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 258
1ce28feb
WH		 259/* domain represents a virtual machine, more than one devices
260 * across iommus may be owned in one domain, e.g. kvm guest.
261 */
262#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
263
2c2e2c38
FY		 264/* si_domain contains mulitple devices */
265#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
266
99126f7c
MM		 267struct dmar_domain {
268 int id; /* domain id */
8c11e798 269 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
99126f7c
MM		 270
271 struct list_head devices; /* all devices' list */
272 struct iova_domain iovad; /* iova's that belong to this domain */
273
274 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 275 int gaw; /* max guest address width */
276
277 /* adjusted guest address width, 0 is level 2 30-bit */
278 int agaw;
279
3b5410e7 280 int flags; /* flags to find out type of domain */
8e604097
WH		 281
282 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 283 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d
WH		 284 int iommu_count; /* reference count of iommu */
285 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 286 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 287};
288
a647dacb
MM		 289/* PCI domain-device relationship */
290struct device_domain_info {
291 struct list_head link; /* link to domain siblings */
292 struct list_head global; /* link to global list */
276dbf99
DW		 293 int segment; /* PCI domain */
294 u8 bus; /* PCI bus number */
a647dacb
MM		 295 u8 devfn; /* PCI devfn number */
296 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
93a23a72 297 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 298 struct dmar_domain *domain; /* pointer to domain */
299};
300
5e0d2a6f 301static void flush_unmaps_timeout(unsigned long data);
302
303DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
304
80b20dd8 305#define HIGH_WATER_MARK 250
306struct deferred_flush_tables {
307 int next;
308 struct iova *iova[HIGH_WATER_MARK];
309 struct dmar_domain *domain[HIGH_WATER_MARK];
310};
311
312static struct deferred_flush_tables *deferred_flush;
313
5e0d2a6f 314/* bitmap for indexing intel_iommus */
5e0d2a6f 315static int g_num_of_iommus;
316
317static DEFINE_SPINLOCK(async_umap_flush_lock);
318static LIST_HEAD(unmaps_to_do);
319
320static int timer_on;
321static long list_size;
5e0d2a6f 322
ba395927
KA		 323static void domain_remove_dev_info(struct dmar_domain *domain);
324
0cd5c3c8
KM		 325#ifdef CONFIG_DMAR_DEFAULT_ON
326int dmar_disabled = 0;
327#else
328int dmar_disabled = 1;
329#endif /*CONFIG_DMAR_DEFAULT_ON*/
330
ba395927 331static int __initdata dmar_map_gfx = 1;
7d3b03ce 332static int dmar_forcedac;
5e0d2a6f 333static int intel_iommu_strict;
ba395927
KA		 334
335#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
336static DEFINE_SPINLOCK(device_domain_lock);
337static LIST_HEAD(device_domain_list);
338
a8bcbb0d
JR		 339static struct iommu_ops intel_iommu_ops;
340
ba395927
KA		 341static int __init intel_iommu_setup(char *str)
342{
343 if (!str)
344 return -EINVAL;
345 while (*str) {
0cd5c3c8
KM		 346 if (!strncmp(str, "on", 2)) {
347 dmar_disabled = 0;
348 printk(KERN_INFO "Intel-IOMMU: enabled\n");
349 } else if (!strncmp(str, "off", 3)) {
ba395927 350 dmar_disabled = 1;
0cd5c3c8 351 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 352 } else if (!strncmp(str, "igfx_off", 8)) {
353 dmar_map_gfx = 0;
354 printk(KERN_INFO
355 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 356 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 357 printk(KERN_INFO
7d3b03ce
KA		 358 "Intel-IOMMU: Forcing DAC for PCI devices\n");
359 dmar_forcedac = 1;
5e0d2a6f 360 } else if (!strncmp(str, "strict", 6)) {
361 printk(KERN_INFO
362 "Intel-IOMMU: disable batched IOTLB flush\n");
363 intel_iommu_strict = 1;
ba395927
KA		 364 }
365
366 str += strcspn(str, ",");
367 while (*str == ',')
368 str++;
369 }
370 return 0;
371}
372__setup("intel_iommu=", intel_iommu_setup);
373
374static struct kmem_cache *iommu_domain_cache;
375static struct kmem_cache *iommu_devinfo_cache;
376static struct kmem_cache *iommu_iova_cache;
377
eb3fa7cb
KA		 378static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
379{
380 unsigned int flags;
381 void *vaddr;
382
383 /* trying to avoid low memory issues */
384 flags = current->flags & PF_MEMALLOC;
385 current->flags |= PF_MEMALLOC;
386 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
387 current->flags &= (~PF_MEMALLOC | flags);
388 return vaddr;
389}
390
391
ba395927
KA		 392static inline void *alloc_pgtable_page(void)
393{
eb3fa7cb
KA		 394 unsigned int flags;
395 void *vaddr;
396
397 /* trying to avoid low memory issues */
398 flags = current->flags & PF_MEMALLOC;
399 current->flags |= PF_MEMALLOC;
400 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
401 current->flags &= (~PF_MEMALLOC | flags);
402 return vaddr;
ba395927
KA		 403}
404
405static inline void free_pgtable_page(void *vaddr)
406{
407 free_page((unsigned long)vaddr);
408}
409
410static inline void *alloc_domain_mem(void)
411{
eb3fa7cb 412 return iommu_kmem_cache_alloc(iommu_domain_cache);
ba395927
KA		 413}
414
38717946 415static void free_domain_mem(void *vaddr)
ba395927
KA		 416{
417 kmem_cache_free(iommu_domain_cache, vaddr);
418}
419
420static inline void * alloc_devinfo_mem(void)
421{
eb3fa7cb 422 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
ba395927
KA		 423}
424
425static inline void free_devinfo_mem(void *vaddr)
426{
427 kmem_cache_free(iommu_devinfo_cache, vaddr);
428}
429
430struct iova *alloc_iova_mem(void)
431{
eb3fa7cb 432 return iommu_kmem_cache_alloc(iommu_iova_cache);
ba395927
KA		 433}
434
435void free_iova_mem(struct iova *iova)
436{
437 kmem_cache_free(iommu_iova_cache, iova);
438}
439
1b573683
WH		 440
441static inline int width_to_agaw(int width);
442
4ed0d3e6 443static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 444{
445 unsigned long sagaw;
446 int agaw = -1;
447
448 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 449 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 450 agaw >= 0; agaw--) {
451 if (test_bit(agaw, &sagaw))
452 break;
453 }
454
455 return agaw;
456}
457
4ed0d3e6
FY		 458/*
459 * Calculate max SAGAW for each iommu.
460 */
461int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
462{
463 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
464}
465
466/*
467 * calculate agaw for each iommu.
468 * "SAGAW" may be different across iommus, use a default agaw, and
469 * get a supported less agaw for iommus that don't support the default agaw.
470 */
471int iommu_calculate_agaw(struct intel_iommu *iommu)
472{
473 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
474}
475
2c2e2c38 476/* This functionin only returns single iommu in a domain */
8c11e798
WH		 477static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
478{
479 int iommu_id;
480
2c2e2c38 481 /* si_domain and vm domain should not get here. */
1ce28feb 482 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 483 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 484
8c11e798
WH		 485 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
486 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
487 return NULL;
488
489 return g_iommus[iommu_id];
490}
491
8e604097
WH		 492static void domain_update_iommu_coherency(struct dmar_domain *domain)
493{
494 int i;
495
496 domain->iommu_coherency = 1;
497
498 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
499 for (; i < g_num_of_iommus; ) {
500 if (!ecap_coherent(g_iommus[i]->ecap)) {
501 domain->iommu_coherency = 0;
502 break;
503 }
504 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
505 }
506}
507
58c610bd
SY		 508static void domain_update_iommu_snooping(struct dmar_domain *domain)
509{
510 int i;
511
512 domain->iommu_snooping = 1;
513
514 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
515 for (; i < g_num_of_iommus; ) {
516 if (!ecap_sc_support(g_iommus[i]->ecap)) {
517 domain->iommu_snooping = 0;
518 break;
519 }
520 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
521 }
522}
523
524/* Some capabilities may be different across iommus */
525static void domain_update_iommu_cap(struct dmar_domain *domain)
526{
527 domain_update_iommu_coherency(domain);
528 domain_update_iommu_snooping(domain);
529}
530
276dbf99 531static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 532{
533 struct dmar_drhd_unit *drhd = NULL;
534 int i;
535
536 for_each_drhd_unit(drhd) {
537 if (drhd->ignored)
538 continue;
276dbf99
DW		 539 if (segment != drhd->segment)
540 continue;
c7151a8d 541
924b6231 542 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 543 if (drhd->devices[i] &&
544 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 545 drhd->devices[i]->devfn == devfn)
546 return drhd->iommu;
4958c5dc
DW		 547 if (drhd->devices[i] &&
548 drhd->devices[i]->subordinate &&
924b6231
DW		 549 drhd->devices[i]->subordinate->number <= bus &&
550 drhd->devices[i]->subordinate->subordinate >= bus)
551 return drhd->iommu;
552 }
c7151a8d
WH		 553
554 if (drhd->include_all)
555 return drhd->iommu;
556 }
557
558 return NULL;
559}
560
5331fe6f
WH		 561static void domain_flush_cache(struct dmar_domain *domain,
562 void *addr, int size)
563{
564 if (!domain->iommu_coherency)
565 clflush_cache_range(addr, size);
566}
567
ba395927
KA		 568/* Gets context entry for a given bus and devfn */
569static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
570 u8 bus, u8 devfn)
571{
572 struct root_entry *root;
573 struct context_entry *context;
574 unsigned long phy_addr;
575 unsigned long flags;
576
577 spin_lock_irqsave(&iommu->lock, flags);
578 root = &iommu->root_entry[bus];
579 context = get_context_addr_from_root(root);
580 if (!context) {
581 context = (struct context_entry *)alloc_pgtable_page();
582 if (!context) {
583 spin_unlock_irqrestore(&iommu->lock, flags);
584 return NULL;
585 }
5b6985ce 586 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 587 phy_addr = virt_to_phys((void *)context);
588 set_root_value(root, phy_addr);
589 set_root_present(root);
590 __iommu_flush_cache(iommu, root, sizeof(*root));
591 }
592 spin_unlock_irqrestore(&iommu->lock, flags);
593 return &context[devfn];
594}
595
596static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
597{
598 struct root_entry *root;
599 struct context_entry *context;
600 int ret;
601 unsigned long flags;
602
603 spin_lock_irqsave(&iommu->lock, flags);
604 root = &iommu->root_entry[bus];
605 context = get_context_addr_from_root(root);
606 if (!context) {
607 ret = 0;
608 goto out;
609 }
c07e7d21 610 ret = context_present(&context[devfn]);
ba395927
KA		 611out:
612 spin_unlock_irqrestore(&iommu->lock, flags);
613 return ret;
614}
615
616static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
617{
618 struct root_entry *root;
619 struct context_entry *context;
620 unsigned long flags;
621
622 spin_lock_irqsave(&iommu->lock, flags);
623 root = &iommu->root_entry[bus];
624 context = get_context_addr_from_root(root);
625 if (context) {
c07e7d21 626 context_clear_entry(&context[devfn]);
ba395927
KA		 627 __iommu_flush_cache(iommu, &context[devfn], \
628 sizeof(*context));
629 }
630 spin_unlock_irqrestore(&iommu->lock, flags);
631}
632
633static void free_context_table(struct intel_iommu *iommu)
634{
635 struct root_entry *root;
636 int i;
637 unsigned long flags;
638 struct context_entry *context;
639
640 spin_lock_irqsave(&iommu->lock, flags);
641 if (!iommu->root_entry) {
642 goto out;
643 }
644 for (i = 0; i < ROOT_ENTRY_NR; i++) {
645 root = &iommu->root_entry[i];
646 context = get_context_addr_from_root(root);
647 if (context)
648 free_pgtable_page(context);
649 }
650 free_pgtable_page(iommu->root_entry);
651 iommu->root_entry = NULL;
652out:
653 spin_unlock_irqrestore(&iommu->lock, flags);
654}
655
656/* page table handling */
657#define LEVEL_STRIDE (9)
658#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
659
660static inline int agaw_to_level(int agaw)
661{
662 return agaw + 2;
663}
664
665static inline int agaw_to_width(int agaw)
666{
667 return 30 + agaw * LEVEL_STRIDE;
668
669}
670
671static inline int width_to_agaw(int width)
672{
673 return (width - 30) / LEVEL_STRIDE;
674}
675
676static inline unsigned int level_to_offset_bits(int level)
677{
6660c63a 678 return (level - 1) * LEVEL_STRIDE;
ba395927
KA		 679}
680
77dfa56c 681static inline int pfn_level_offset(unsigned long pfn, int level)
ba395927 682{
6660c63a 683 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
ba395927
KA		 684}
685
6660c63a 686static inline unsigned long level_mask(int level)
ba395927 687{
6660c63a 688 return -1UL << level_to_offset_bits(level);
ba395927
KA		 689}
690
6660c63a 691static inline unsigned long level_size(int level)
ba395927 692{
6660c63a 693 return 1UL << level_to_offset_bits(level);
ba395927
KA		 694}
695
6660c63a 696static inline unsigned long align_to_level(unsigned long pfn, int level)
ba395927 697{
6660c63a 698 return (pfn + level_size(level) - 1) & level_mask(level);
ba395927
KA		 699}
700
b026fd28
DW		 701static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
702 unsigned long pfn)
ba395927 703{
b026fd28 704 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 705 struct dma_pte *parent, *pte = NULL;
706 int level = agaw_to_level(domain->agaw);
707 int offset;
ba395927
KA		 708
709 BUG_ON(!domain->pgd);
b026fd28 710 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
ba395927
KA		 711 parent = domain->pgd;
712
ba395927
KA		 713 while (level > 0) {
714 void *tmp_page;
715
b026fd28 716 offset = pfn_level_offset(pfn, level);
ba395927
KA		 717 pte = &parent[offset];
718 if (level == 1)
719 break;
720
19c239ce 721 if (!dma_pte_present(pte)) {
c85994e4
DW		 722 uint64_t pteval;
723
ba395927
KA		 724 tmp_page = alloc_pgtable_page();
725
206a73c1 726 if (!tmp_page)
ba395927 727 return NULL;
206a73c1 728
c85994e4
DW		 729 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
730 pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
731 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
732 /* Someone else set it while we were thinking; use theirs. */
733 free_pgtable_page(tmp_page);
734 } else {
735 dma_pte_addr(pte);
736 domain_flush_cache(domain, pte, sizeof(*pte));
737 }
ba395927 738 }
19c239ce 739 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 740 level--;
741 }
742
ba395927
KA		 743 return pte;
744}
745
746/* return address's pte at specific level */
90dcfb5e
DW		 747static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
748 unsigned long pfn,
749 int level)
ba395927
KA		 750{
751 struct dma_pte *parent, *pte = NULL;
752 int total = agaw_to_level(domain->agaw);
753 int offset;
754
755 parent = domain->pgd;
756 while (level <= total) {
90dcfb5e 757 offset = pfn_level_offset(pfn, total);
ba395927
KA		 758 pte = &parent[offset];
759 if (level == total)
760 return pte;
761
19c239ce 762 if (!dma_pte_present(pte))
ba395927 763 break;
19c239ce 764 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 765 total--;
766 }
767 return NULL;
768}
769
ba395927 770/* clear last level pte, a tlb flush should be followed */
595badf5
DW		 771static void dma_pte_clear_range(struct dmar_domain *domain,
772 unsigned long start_pfn,
773 unsigned long last_pfn)
ba395927 774{
04b18e65 775 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
310a5ab9 776 struct dma_pte *first_pte, *pte;
66eae846 777
04b18e65 778 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 779 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
ba395927 780
04b18e65 781 /* we don't need lock here; nobody else touches the iova range */
595badf5 782 while (start_pfn <= last_pfn) {
310a5ab9
DW		 783 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
784 if (!pte) {
785 start_pfn = align_to_level(start_pfn + 1, 2);
786 continue;
787 }
75e6bf96 788 do {
310a5ab9
DW		 789 dma_clear_pte(pte);
790 start_pfn++;
791 pte++;
75e6bf96
DW		 792 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
793
310a5ab9
DW		 794 domain_flush_cache(domain, first_pte,
795 (void *)pte - (void *)first_pte);
ba395927
KA		 796 }
797}
798
799/* free page table pages. last level pte should already be cleared */
800static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 801 unsigned long start_pfn,
802 unsigned long last_pfn)
ba395927 803{
6660c63a 804 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
f3a0a52f 805 struct dma_pte *first_pte, *pte;
ba395927
KA		 806 int total = agaw_to_level(domain->agaw);
807 int level;
6660c63a 808 unsigned long tmp;
ba395927 809
6660c63a
DW		 810 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
811 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
ba395927 812
f3a0a52f 813 /* We don't need lock here; nobody else touches the iova range */
ba395927
KA		 814 level = 2;
815 while (level <= total) {
6660c63a
DW		 816 tmp = align_to_level(start_pfn, level);
817
f3a0a52f 818 /* If we can't even clear one PTE at this level, we're done */
6660c63a 819 if (tmp + level_size(level) - 1 > last_pfn)
ba395927
KA		 820 return;
821
3d7b0e41 822 while (tmp + level_size(level) - 1 <= last_pfn) {
f3a0a52f
DW		 823 first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
824 if (!pte) {
825 tmp = align_to_level(tmp + 1, level + 1);
826 continue;
827 }
75e6bf96 828 do {
6a43e574
DW		 829 if (dma_pte_present(pte)) {
830 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
831 dma_clear_pte(pte);
832 }
f3a0a52f
DW		 833 pte++;
834 tmp += level_size(level);
75e6bf96
DW		 835 } while (!first_pte_in_page(pte) &&
836 tmp + level_size(level) - 1 <= last_pfn);
837
f3a0a52f
DW		 838 domain_flush_cache(domain, first_pte,
839 (void *)pte - (void *)first_pte);
840
ba395927
KA		 841 }
842 level++;
843 }
844 /* free pgd */
d794dc9b 845 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 846 free_pgtable_page(domain->pgd);
847 domain->pgd = NULL;
848 }
849}
850
851/* iommu handling */
852static int iommu_alloc_root_entry(struct intel_iommu *iommu)
853{
854 struct root_entry *root;
855 unsigned long flags;
856
857 root = (struct root_entry *)alloc_pgtable_page();
858 if (!root)
859 return -ENOMEM;
860
5b6985ce 861 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 862
863 spin_lock_irqsave(&iommu->lock, flags);
864 iommu->root_entry = root;
865 spin_unlock_irqrestore(&iommu->lock, flags);
866
867 return 0;
868}
869
ba395927
KA		 870static void iommu_set_root_entry(struct intel_iommu *iommu)
871{
872 void *addr;
c416daa9 873 u32 sts;
ba395927
KA		 874 unsigned long flag;
875
876 addr = iommu->root_entry;
877
878 spin_lock_irqsave(&iommu->register_lock, flag);
879 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
880
c416daa9 881 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 882
883 /* Make sure hardware complete it */
884 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 885 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927
KA		 886
887 spin_unlock_irqrestore(&iommu->register_lock, flag);
888}
889
890static void iommu_flush_write_buffer(struct intel_iommu *iommu)
891{
892 u32 val;
893 unsigned long flag;
894
9af88143 895 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 896 return;
ba395927
KA		 897
898 spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 899 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 900
901 /* Make sure hardware complete it */
902 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 903 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927
KA		 904
905 spin_unlock_irqrestore(&iommu->register_lock, flag);
906}
907
908/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 909static void __iommu_flush_context(struct intel_iommu *iommu,
910 u16 did, u16 source_id, u8 function_mask,
911 u64 type)
ba395927
KA		 912{
913 u64 val = 0;
914 unsigned long flag;
915
ba395927
KA		 916 switch (type) {
917 case DMA_CCMD_GLOBAL_INVL:
918 val = DMA_CCMD_GLOBAL_INVL;
919 break;
920 case DMA_CCMD_DOMAIN_INVL:
921 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
922 break;
923 case DMA_CCMD_DEVICE_INVL:
924 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
925 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
926 break;
927 default:
928 BUG();
929 }
930 val |= DMA_CCMD_ICC;
931
932 spin_lock_irqsave(&iommu->register_lock, flag);
933 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
934
935 /* Make sure hardware complete it */
936 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
937 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
938
939 spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 940}
941
ba395927 942/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 943static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
944 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 945{
946 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
947 u64 val = 0, val_iva = 0;
948 unsigned long flag;
949
ba395927
KA		 950 switch (type) {
951 case DMA_TLB_GLOBAL_FLUSH:
952 /* global flush doesn't need set IVA_REG */
953 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
954 break;
955 case DMA_TLB_DSI_FLUSH:
956 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
957 break;
958 case DMA_TLB_PSI_FLUSH:
959 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
960 /* Note: always flush non-leaf currently */
961 val_iva = size_order | addr;
962 break;
963 default:
964 BUG();
965 }
966 /* Note: set drain read/write */
967#if 0
968 /*
969 * This is probably to be super secure.. Looks like we can
970 * ignore it without any impact.
971 */
972 if (cap_read_drain(iommu->cap))
973 val |= DMA_TLB_READ_DRAIN;
974#endif
975 if (cap_write_drain(iommu->cap))
976 val |= DMA_TLB_WRITE_DRAIN;
977
978 spin_lock_irqsave(&iommu->register_lock, flag);
979 /* Note: Only uses first TLB reg currently */
980 if (val_iva)
981 dmar_writeq(iommu->reg + tlb_offset, val_iva);
982 dmar_writeq(iommu->reg + tlb_offset + 8, val);
983
984 /* Make sure hardware complete it */
985 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
986 dmar_readq, (!(val & DMA_TLB_IVT)), val);
987
988 spin_unlock_irqrestore(&iommu->register_lock, flag);
989
990 /* check IOTLB invalidation granularity */
991 if (DMA_TLB_IAIG(val) == 0)
992 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
993 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
994 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 995 (unsigned long long)DMA_TLB_IIRG(type),
996 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 997}
998
93a23a72
YZ		 999static struct device_domain_info *iommu_support_dev_iotlb(
1000 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1001{
1002 int found = 0;
1003 unsigned long flags;
1004 struct device_domain_info *info;
1005 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1006
1007 if (!ecap_dev_iotlb_support(iommu->ecap))
1008 return NULL;
1009
1010 if (!iommu->qi)
1011 return NULL;
1012
1013 spin_lock_irqsave(&device_domain_lock, flags);
1014 list_for_each_entry(info, &domain->devices, link)
1015 if (info->bus == bus && info->devfn == devfn) {
1016 found = 1;
1017 break;
1018 }
1019 spin_unlock_irqrestore(&device_domain_lock, flags);
1020
1021 if (!found || !info->dev)
1022 return NULL;
1023
1024 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1025 return NULL;
1026
1027 if (!dmar_find_matched_atsr_unit(info->dev))
1028 return NULL;
1029
1030 info->iommu = iommu;
1031
1032 return info;
1033}
1034
1035static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1036{
93a23a72
YZ		 1037 if (!info)
1038 return;
1039
1040 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1041}
1042
1043static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1044{
1045 if (!info->dev || !pci_ats_enabled(info->dev))
1046 return;
1047
1048 pci_disable_ats(info->dev);
1049}
1050
1051static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1052 u64 addr, unsigned mask)
1053{
1054 u16 sid, qdep;
1055 unsigned long flags;
1056 struct device_domain_info *info;
1057
1058 spin_lock_irqsave(&device_domain_lock, flags);
1059 list_for_each_entry(info, &domain->devices, link) {
1060 if (!info->dev || !pci_ats_enabled(info->dev))
1061 continue;
1062
1063 sid = info->bus << 8 | info->devfn;
1064 qdep = pci_ats_queue_depth(info->dev);
1065 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1066 }
1067 spin_unlock_irqrestore(&device_domain_lock, flags);
1068}
1069
1f0ef2aa 1070static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
03d6a246 1071 unsigned long pfn, unsigned int pages)
ba395927 1072{
9dd2fe89 1073 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1074 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1075
ba395927
KA		 1076 BUG_ON(pages == 0);
1077
ba395927 1078 /*
9dd2fe89
YZ		 1079 * Fallback to domain selective flush if no PSI support or the size is
1080 * too big.
ba395927
KA		 1081 * PSI requires page size to be 2 ^ x, and the base address is naturally
1082 * aligned to the size
1083 */
9dd2fe89
YZ		 1084 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1085 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1086 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1087 else
1088 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1089 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1090
1091 /*
1092 * In caching mode, domain ID 0 is reserved for non-present to present
1093 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1094 */
1095 if (!cap_caching_mode(iommu->cap) || did)
93a23a72 1096 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1097}
1098
f8bab735 1099static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1100{
1101 u32 pmen;
1102 unsigned long flags;
1103
1104 spin_lock_irqsave(&iommu->register_lock, flags);
1105 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1106 pmen &= ~DMA_PMEN_EPM;
1107 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1108
1109 /* wait for the protected region status bit to clear */
1110 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1111 readl, !(pmen & DMA_PMEN_PRS), pmen);
1112
1113 spin_unlock_irqrestore(&iommu->register_lock, flags);
1114}
1115
ba395927
KA		 1116static int iommu_enable_translation(struct intel_iommu *iommu)
1117{
1118 u32 sts;
1119 unsigned long flags;
1120
1121 spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1122 iommu->gcmd |= DMA_GCMD_TE;
1123 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1124
1125 /* Make sure hardware complete it */
1126 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1127 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1128
ba395927
KA		 1129 spin_unlock_irqrestore(&iommu->register_lock, flags);
1130 return 0;
1131}
1132
1133static int iommu_disable_translation(struct intel_iommu *iommu)
1134{
1135 u32 sts;
1136 unsigned long flag;
1137
1138 spin_lock_irqsave(&iommu->register_lock, flag);
1139 iommu->gcmd &= ~DMA_GCMD_TE;
1140 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1141
1142 /* Make sure hardware complete it */
1143 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1144 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927
KA		 1145
1146 spin_unlock_irqrestore(&iommu->register_lock, flag);
1147 return 0;
1148}
1149
3460a6d9 1150
ba395927
KA		 1151static int iommu_init_domains(struct intel_iommu *iommu)
1152{
1153 unsigned long ndomains;
1154 unsigned long nlongs;
1155
1156 ndomains = cap_ndoms(iommu->cap);
1157 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1158 nlongs = BITS_TO_LONGS(ndomains);
1159
1160 /* TBD: there might be 64K domains,
1161 * consider other allocation for future chip
1162 */
1163 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1164 if (!iommu->domain_ids) {
1165 printk(KERN_ERR "Allocating domain id array failed\n");
1166 return -ENOMEM;
1167 }
1168 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1169 GFP_KERNEL);
1170 if (!iommu->domains) {
1171 printk(KERN_ERR "Allocating domain array failed\n");
1172 kfree(iommu->domain_ids);
1173 return -ENOMEM;
1174 }
1175
e61d98d8
SS		 1176 spin_lock_init(&iommu->lock);
1177
ba395927
KA		 1178 /*
1179 * if Caching mode is set, then invalid translations are tagged
1180 * with domainid 0. Hence we need to pre-allocate it.
1181 */
1182 if (cap_caching_mode(iommu->cap))
1183 set_bit(0, iommu->domain_ids);
1184 return 0;
1185}
ba395927 1186
ba395927
KA		 1187
1188static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1189static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8
SS		 1190
1191void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1192{
1193 struct dmar_domain *domain;
1194 int i;
c7151a8d 1195 unsigned long flags;
ba395927 1196
ba395927
KA		 1197 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1198 for (; i < cap_ndoms(iommu->cap); ) {
1199 domain = iommu->domains[i];
1200 clear_bit(i, iommu->domain_ids);
c7151a8d
WH		 1201
1202 spin_lock_irqsave(&domain->iommu_lock, flags);
5e98c4b1
WH		 1203 if (--domain->iommu_count == 0) {
1204 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1205 vm_domain_exit(domain);
1206 else
1207 domain_exit(domain);
1208 }
c7151a8d
WH		 1209 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1210
ba395927
KA		 1211 i = find_next_bit(iommu->domain_ids,
1212 cap_ndoms(iommu->cap), i+1);
1213 }
1214
1215 if (iommu->gcmd & DMA_GCMD_TE)
1216 iommu_disable_translation(iommu);
1217
1218 if (iommu->irq) {
1219 set_irq_data(iommu->irq, NULL);
1220 /* This will mask the irq */
1221 free_irq(iommu->irq, iommu);
1222 destroy_irq(iommu->irq);
1223 }
1224
1225 kfree(iommu->domains);
1226 kfree(iommu->domain_ids);
1227
d9630fe9
WH		 1228 g_iommus[iommu->seq_id] = NULL;
1229
1230 /* if all iommus are freed, free g_iommus */
1231 for (i = 0; i < g_num_of_iommus; i++) {
1232 if (g_iommus[i])
1233 break;
1234 }
1235
1236 if (i == g_num_of_iommus)
1237 kfree(g_iommus);
1238
ba395927
KA		 1239 /* free context mapping */
1240 free_context_table(iommu);
ba395927
KA		 1241}
1242
2c2e2c38 1243static struct dmar_domain *alloc_domain(void)
ba395927 1244{
ba395927 1245 struct dmar_domain *domain;
ba395927
KA		 1246
1247 domain = alloc_domain_mem();
1248 if (!domain)
1249 return NULL;
1250
2c2e2c38
FY		 1251 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1252 domain->flags = 0;
1253
1254 return domain;
1255}
1256
1257static int iommu_attach_domain(struct dmar_domain *domain,
1258 struct intel_iommu *iommu)
1259{
1260 int num;
1261 unsigned long ndomains;
1262 unsigned long flags;
1263
ba395927
KA		 1264 ndomains = cap_ndoms(iommu->cap);
1265
1266 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1267
ba395927
KA		 1268 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1269 if (num >= ndomains) {
1270 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1271 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1272 return -ENOMEM;
ba395927
KA		 1273 }
1274
ba395927 1275 domain->id = num;
2c2e2c38 1276 set_bit(num, iommu->domain_ids);
8c11e798 1277 set_bit(iommu->seq_id, &domain->iommu_bmp);
ba395927
KA		 1278 iommu->domains[num] = domain;
1279 spin_unlock_irqrestore(&iommu->lock, flags);
1280
2c2e2c38 1281 return 0;
ba395927
KA		 1282}
1283
2c2e2c38
FY		 1284static void iommu_detach_domain(struct dmar_domain *domain,
1285 struct intel_iommu *iommu)
ba395927
KA		 1286{
1287 unsigned long flags;
2c2e2c38
FY		 1288 int num, ndomains;
1289 int found = 0;
ba395927 1290
8c11e798 1291 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38
FY		 1292 ndomains = cap_ndoms(iommu->cap);
1293 num = find_first_bit(iommu->domain_ids, ndomains);
1294 for (; num < ndomains; ) {
1295 if (iommu->domains[num] == domain) {
1296 found = 1;
1297 break;
1298 }
1299 num = find_next_bit(iommu->domain_ids,
1300 cap_ndoms(iommu->cap), num+1);
1301 }
1302
1303 if (found) {
1304 clear_bit(num, iommu->domain_ids);
1305 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1306 iommu->domains[num] = NULL;
1307 }
8c11e798 1308 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1309}
1310
1311static struct iova_domain reserved_iova_list;
8a443df4
MG		 1312static struct lock_class_key reserved_alloc_key;
1313static struct lock_class_key reserved_rbtree_key;
ba395927
KA		 1314
1315static void dmar_init_reserved_ranges(void)
1316{
1317 struct pci_dev *pdev = NULL;
1318 struct iova *iova;
1319 int i;
ba395927 1320
f661197e 1321 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1322
8a443df4
MG		 1323 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1324 &reserved_alloc_key);
1325 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1326 &reserved_rbtree_key);
1327
ba395927
KA		 1328 /* IOAPIC ranges shouldn't be accessed by DMA */
1329 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1330 IOVA_PFN(IOAPIC_RANGE_END));
1331 if (!iova)
1332 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1333
1334 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1335 for_each_pci_dev(pdev) {
1336 struct resource *r;
1337
1338 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1339 r = &pdev->resource[i];
1340 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1341 continue;
1a4a4551
DW		 1342 iova = reserve_iova(&reserved_iova_list,
1343 IOVA_PFN(r->start),
1344 IOVA_PFN(r->end));
ba395927
KA		 1345 if (!iova)
1346 printk(KERN_ERR "Reserve iova failed\n");
1347 }
1348 }
1349
1350}
1351
1352static void domain_reserve_special_ranges(struct dmar_domain *domain)
1353{
1354 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1355}
1356
1357static inline int guestwidth_to_adjustwidth(int gaw)
1358{
1359 int agaw;
1360 int r = (gaw - 12) % 9;
1361
1362 if (r == 0)
1363 agaw = gaw;
1364 else
1365 agaw = gaw + 9 - r;
1366 if (agaw > 64)
1367 agaw = 64;
1368 return agaw;
1369}
1370
1371static int domain_init(struct dmar_domain *domain, int guest_width)
1372{
1373 struct intel_iommu *iommu;
1374 int adjust_width, agaw;
1375 unsigned long sagaw;
1376
f661197e 1377 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
c7151a8d 1378 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1379
1380 domain_reserve_special_ranges(domain);
1381
1382 /* calculate AGAW */
8c11e798 1383 iommu = domain_get_iommu(domain);
ba395927
KA		 1384 if (guest_width > cap_mgaw(iommu->cap))
1385 guest_width = cap_mgaw(iommu->cap);
1386 domain->gaw = guest_width;
1387 adjust_width = guestwidth_to_adjustwidth(guest_width);
1388 agaw = width_to_agaw(adjust_width);
1389 sagaw = cap_sagaw(iommu->cap);
1390 if (!test_bit(agaw, &sagaw)) {
1391 /* hardware doesn't support it, choose a bigger one */
1392 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1393 agaw = find_next_bit(&sagaw, 5, agaw);
1394 if (agaw >= 5)
1395 return -ENODEV;
1396 }
1397 domain->agaw = agaw;
1398 INIT_LIST_HEAD(&domain->devices);
1399
8e604097
WH		 1400 if (ecap_coherent(iommu->ecap))
1401 domain->iommu_coherency = 1;
1402 else
1403 domain->iommu_coherency = 0;
1404
58c610bd
SY		 1405 if (ecap_sc_support(iommu->ecap))
1406 domain->iommu_snooping = 1;
1407 else
1408 domain->iommu_snooping = 0;
1409
c7151a8d
WH		 1410 domain->iommu_count = 1;
1411
ba395927
KA		 1412 /* always allocate the top pgd */
1413 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1414 if (!domain->pgd)
1415 return -ENOMEM;
5b6985ce 1416 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1417 return 0;
1418}
1419
1420static void domain_exit(struct dmar_domain *domain)
1421{
2c2e2c38
FY		 1422 struct dmar_drhd_unit *drhd;
1423 struct intel_iommu *iommu;
ba395927
KA		 1424
1425 /* Domain 0 is reserved, so dont process it */
1426 if (!domain)
1427 return;
1428
1429 domain_remove_dev_info(domain);
1430 /* destroy iovas */
1431 put_iova_domain(&domain->iovad);
ba395927
KA		 1432
1433 /* clear ptes */
595badf5 1434 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927
KA		 1435
1436 /* free page tables */
d794dc9b 1437 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1438
2c2e2c38
FY		 1439 for_each_active_iommu(iommu, drhd)
1440 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1441 iommu_detach_domain(domain, iommu);
1442
ba395927
KA		 1443 free_domain_mem(domain);
1444}
1445
4ed0d3e6
FY		 1446static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1447 u8 bus, u8 devfn, int translation)
ba395927
KA		 1448{
1449 struct context_entry *context;
ba395927 1450 unsigned long flags;
5331fe6f 1451 struct intel_iommu *iommu;
ea6606b0
WH		 1452 struct dma_pte *pgd;
1453 unsigned long num;
1454 unsigned long ndomains;
1455 int id;
1456 int agaw;
93a23a72 1457 struct device_domain_info *info = NULL;
ba395927
KA		 1458
1459 pr_debug("Set context mapping for %02x:%02x.%d\n",
1460 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1461
ba395927 1462 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1463 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1464 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1465
276dbf99 1466 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1467 if (!iommu)
1468 return -ENODEV;
1469
ba395927
KA		 1470 context = device_to_context_entry(iommu, bus, devfn);
1471 if (!context)
1472 return -ENOMEM;
1473 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1474 if (context_present(context)) {
ba395927
KA		 1475 spin_unlock_irqrestore(&iommu->lock, flags);
1476 return 0;
1477 }
1478
ea6606b0
WH		 1479 id = domain->id;
1480 pgd = domain->pgd;
1481
2c2e2c38
FY		 1482 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1483 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1484 int found = 0;
1485
1486 /* find an available domain id for this device in iommu */
1487 ndomains = cap_ndoms(iommu->cap);
1488 num = find_first_bit(iommu->domain_ids, ndomains);
1489 for (; num < ndomains; ) {
1490 if (iommu->domains[num] == domain) {
1491 id = num;
1492 found = 1;
1493 break;
1494 }
1495 num = find_next_bit(iommu->domain_ids,
1496 cap_ndoms(iommu->cap), num+1);
1497 }
1498
1499 if (found == 0) {
1500 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1501 if (num >= ndomains) {
1502 spin_unlock_irqrestore(&iommu->lock, flags);
1503 printk(KERN_ERR "IOMMU: no free domain ids\n");
1504 return -EFAULT;
1505 }
1506
1507 set_bit(num, iommu->domain_ids);
1508 iommu->domains[num] = domain;
1509 id = num;
1510 }
1511
1512 /* Skip top levels of page tables for
1513 * iommu which has less agaw than default.
1514 */
1515 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1516 pgd = phys_to_virt(dma_pte_addr(pgd));
1517 if (!dma_pte_present(pgd)) {
1518 spin_unlock_irqrestore(&iommu->lock, flags);
1519 return -ENOMEM;
1520 }
1521 }
1522 }
1523
1524 context_set_domain_id(context, id);
4ed0d3e6 1525
93a23a72
YZ		 1526 if (translation != CONTEXT_TT_PASS_THROUGH) {
1527 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1528 translation = info ? CONTEXT_TT_DEV_IOTLB :
1529 CONTEXT_TT_MULTI_LEVEL;
1530 }
4ed0d3e6
FY		 1531 /*
1532 * In pass through mode, AW must be programmed to indicate the largest
1533 * AGAW value supported by hardware. And ASR is ignored by hardware.
1534 */
93a23a72 1535 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1536 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1537 else {
1538 context_set_address_root(context, virt_to_phys(pgd));
1539 context_set_address_width(context, iommu->agaw);
1540 }
4ed0d3e6
FY		 1541
1542 context_set_translation_type(context, translation);
c07e7d21
MM		 1543 context_set_fault_enable(context);
1544 context_set_present(context);
5331fe6f 1545 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1546
4c25a2c1
DW		 1547 /*
1548 * It's a non-present to present mapping. If hardware doesn't cache
1549 * non-present entry we only need to flush the write-buffer. If the
1550 * _does_ cache non-present entries, then it does so in the special
1551 * domain #0, which we have to flush:
1552 */
1553 if (cap_caching_mode(iommu->cap)) {
1554 iommu->flush.flush_context(iommu, 0,
1555 (((u16)bus) << 8) | devfn,
1556 DMA_CCMD_MASK_NOBIT,
1557 DMA_CCMD_DEVICE_INVL);
1f0ef2aa 1558 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1559 } else {
ba395927 1560 iommu_flush_write_buffer(iommu);
4c25a2c1 1561 }
93a23a72 1562 iommu_enable_dev_iotlb(info);
ba395927 1563 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1564
1565 spin_lock_irqsave(&domain->iommu_lock, flags);
1566 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1567 domain->iommu_count++;
58c610bd 1568 domain_update_iommu_cap(domain);
c7151a8d
WH		 1569 }
1570 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1571 return 0;
1572}
1573
1574static int
4ed0d3e6
FY		 1575domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1576 int translation)
ba395927
KA		 1577{
1578 int ret;
1579 struct pci_dev *tmp, *parent;
1580
276dbf99 1581 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1582 pdev->bus->number, pdev->devfn,
1583 translation);
ba395927
KA		 1584 if (ret)
1585 return ret;
1586
1587 /* dependent device mapping */
1588 tmp = pci_find_upstream_pcie_bridge(pdev);
1589 if (!tmp)
1590 return 0;
1591 /* Secondary interface's bus number and devfn 0 */
1592 parent = pdev->bus->self;
1593 while (parent != tmp) {
276dbf99
DW		 1594 ret = domain_context_mapping_one(domain,
1595 pci_domain_nr(parent->bus),
1596 parent->bus->number,
4ed0d3e6 1597 parent->devfn, translation);
ba395927
KA		 1598 if (ret)
1599 return ret;
1600 parent = parent->bus->self;
1601 }
1602 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1603 return domain_context_mapping_one(domain,
276dbf99 1604 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1605 tmp->subordinate->number, 0,
1606 translation);
ba395927
KA		 1607 else /* this is a legacy PCI bridge */
1608 return domain_context_mapping_one(domain,
276dbf99
DW		 1609 pci_domain_nr(tmp->bus),
1610 tmp->bus->number,
4ed0d3e6
FY		 1611 tmp->devfn,
1612 translation);
ba395927
KA		 1613}
1614
5331fe6f 1615static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1616{
1617 int ret;
1618 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1619 struct intel_iommu *iommu;
1620
276dbf99
DW		 1621 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1622 pdev->devfn);
5331fe6f
WH		 1623 if (!iommu)
1624 return -ENODEV;
ba395927 1625
276dbf99 1626 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1627 if (!ret)
1628 return ret;
1629 /* dependent device mapping */
1630 tmp = pci_find_upstream_pcie_bridge(pdev);
1631 if (!tmp)
1632 return ret;
1633 /* Secondary interface's bus number and devfn 0 */
1634 parent = pdev->bus->self;
1635 while (parent != tmp) {
8c11e798 1636 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1637 parent->devfn);
ba395927
KA		 1638 if (!ret)
1639 return ret;
1640 parent = parent->bus->self;
1641 }
1642 if (tmp->is_pcie)
276dbf99
DW		 1643 return device_context_mapped(iommu, tmp->subordinate->number,
1644 0);
ba395927 1645 else
276dbf99
DW		 1646 return device_context_mapped(iommu, tmp->bus->number,
1647 tmp->devfn);
ba395927
KA		 1648}
1649
f532959b
FY		 1650/* Returns a number of VTD pages, but aligned to MM page size */
1651static inline unsigned long aligned_nrpages(unsigned long host_addr,
1652 size_t size)
1653{
1654 host_addr &= ~PAGE_MASK;
1655 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1656}
1657
9051aa02
DW		 1658static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1659 struct scatterlist *sg, unsigned long phys_pfn,
1660 unsigned long nr_pages, int prot)
e1605495
DW		 1661{
1662 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1663 phys_addr_t uninitialized_var(pteval);
e1605495 1664 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1665 unsigned long sg_res;
e1605495
DW		 1666
1667 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1668
1669 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1670 return -EINVAL;
1671
1672 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1673
9051aa02
DW		 1674 if (sg)
1675 sg_res = 0;
1676 else {
1677 sg_res = nr_pages + 1;
1678 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1679 }
1680
e1605495 1681 while (nr_pages--) {
c85994e4
DW		 1682 uint64_t tmp;
1683
e1605495 1684 if (!sg_res) {
f532959b 1685 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1686 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1687 sg->dma_length = sg->length;
1688 pteval = page_to_phys(sg_page(sg)) | prot;
1689 }
1690 if (!pte) {
1691 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1692 if (!pte)
1693 return -ENOMEM;
1694 }
1695 /* We don't need lock here, nobody else
1696 * touches the iova range
1697 */
7766a3fb 1698 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 1699 if (tmp) {
1bf20f0d 1700 static int dumps = 5;
c85994e4
DW		 1701 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1702 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 1703 if (dumps) {
1704 dumps--;
1705 debug_dma_dump_mappings(NULL);
1706 }
1707 WARN_ON(1);
1708 }
e1605495 1709 pte++;
75e6bf96 1710 if (!nr_pages || first_pte_in_page(pte)) {
e1605495
DW		 1711 domain_flush_cache(domain, first_pte,
1712 (void *)pte - (void *)first_pte);
1713 pte = NULL;
1714 }
1715 iov_pfn++;
1716 pteval += VTD_PAGE_SIZE;
1717 sg_res--;
1718 if (!sg_res)
1719 sg = sg_next(sg);
1720 }
1721 return 0;
1722}
1723
9051aa02
DW		 1724static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1725 struct scatterlist *sg, unsigned long nr_pages,
1726 int prot)
ba395927 1727{
9051aa02
DW		 1728 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1729}
6f6a00e4 1730
9051aa02
DW		 1731static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1732 unsigned long phys_pfn, unsigned long nr_pages,
1733 int prot)
1734{
1735 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 1736}
1737
c7151a8d 1738static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1739{
c7151a8d
WH		 1740 if (!iommu)
1741 return;
8c11e798
WH		 1742
1743 clear_context_table(iommu, bus, devfn);
1744 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1745 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1746 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1747}
1748
1749static void domain_remove_dev_info(struct dmar_domain *domain)
1750{
1751 struct device_domain_info *info;
1752 unsigned long flags;
c7151a8d 1753 struct intel_iommu *iommu;
ba395927
KA		 1754
1755 spin_lock_irqsave(&device_domain_lock, flags);
1756 while (!list_empty(&domain->devices)) {
1757 info = list_entry(domain->devices.next,
1758 struct device_domain_info, link);
1759 list_del(&info->link);
1760 list_del(&info->global);
1761 if (info->dev)
358dd8ac 1762 info->dev->dev.archdata.iommu = NULL;
ba395927
KA		 1763 spin_unlock_irqrestore(&device_domain_lock, flags);
1764
93a23a72 1765 iommu_disable_dev_iotlb(info);
276dbf99 1766 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1767 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1768 free_devinfo_mem(info);
1769
1770 spin_lock_irqsave(&device_domain_lock, flags);
1771 }
1772 spin_unlock_irqrestore(&device_domain_lock, flags);
1773}
1774
1775/*
1776 * find_domain
358dd8ac 1777 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1778 */
38717946 1779static struct dmar_domain *
ba395927
KA		 1780find_domain(struct pci_dev *pdev)
1781{
1782 struct device_domain_info *info;
1783
1784 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1785 info = pdev->dev.archdata.iommu;
ba395927
KA		 1786 if (info)
1787 return info->domain;
1788 return NULL;
1789}
1790
ba395927
KA		 1791/* domain is initialized */
1792static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1793{
1794 struct dmar_domain *domain, *found = NULL;
1795 struct intel_iommu *iommu;
1796 struct dmar_drhd_unit *drhd;
1797 struct device_domain_info *info, *tmp;
1798 struct pci_dev *dev_tmp;
1799 unsigned long flags;
1800 int bus = 0, devfn = 0;
276dbf99 1801 int segment;
2c2e2c38 1802 int ret;
ba395927
KA		 1803
1804 domain = find_domain(pdev);
1805 if (domain)
1806 return domain;
1807
276dbf99
DW		 1808 segment = pci_domain_nr(pdev->bus);
1809
ba395927
KA		 1810 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1811 if (dev_tmp) {
1812 if (dev_tmp->is_pcie) {
1813 bus = dev_tmp->subordinate->number;
1814 devfn = 0;
1815 } else {
1816 bus = dev_tmp->bus->number;
1817 devfn = dev_tmp->devfn;
1818 }
1819 spin_lock_irqsave(&device_domain_lock, flags);
1820 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1821 if (info->segment == segment &&
1822 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1823 found = info->domain;
1824 break;
1825 }
1826 }
1827 spin_unlock_irqrestore(&device_domain_lock, flags);
1828 /* pcie-pci bridge already has a domain, uses it */
1829 if (found) {
1830 domain = found;
1831 goto found_domain;
1832 }
1833 }
1834
2c2e2c38
FY		 1835 domain = alloc_domain();
1836 if (!domain)
1837 goto error;
1838
ba395927
KA		 1839 /* Allocate new domain for the device */
1840 drhd = dmar_find_matched_drhd_unit(pdev);
1841 if (!drhd) {
1842 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1843 pci_name(pdev));
1844 return NULL;
1845 }
1846 iommu = drhd->iommu;
1847
2c2e2c38
FY		 1848 ret = iommu_attach_domain(domain, iommu);
1849 if (ret) {
1850 domain_exit(domain);
ba395927 1851 goto error;
2c2e2c38 1852 }
ba395927
KA		 1853
1854 if (domain_init(domain, gaw)) {
1855 domain_exit(domain);
1856 goto error;
1857 }
1858
1859 /* register pcie-to-pci device */
1860 if (dev_tmp) {
1861 info = alloc_devinfo_mem();
1862 if (!info) {
1863 domain_exit(domain);
1864 goto error;
1865 }
276dbf99 1866 info->segment = segment;
ba395927
KA		 1867 info->bus = bus;
1868 info->devfn = devfn;
1869 info->dev = NULL;
1870 info->domain = domain;
1871 /* This domain is shared by devices under p2p bridge */
3b5410e7 1872 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 1873
1874 /* pcie-to-pci bridge already has a domain, uses it */
1875 found = NULL;
1876 spin_lock_irqsave(&device_domain_lock, flags);
1877 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 1878 if (tmp->segment == segment &&
1879 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 1880 found = tmp->domain;
1881 break;
1882 }
1883 }
1884 if (found) {
1885 free_devinfo_mem(info);
1886 domain_exit(domain);
1887 domain = found;
1888 } else {
1889 list_add(&info->link, &domain->devices);
1890 list_add(&info->global, &device_domain_list);
1891 }
1892 spin_unlock_irqrestore(&device_domain_lock, flags);
1893 }
1894
1895found_domain:
1896 info = alloc_devinfo_mem();
1897 if (!info)
1898 goto error;
276dbf99 1899 info->segment = segment;
ba395927
KA		 1900 info->bus = pdev->bus->number;
1901 info->devfn = pdev->devfn;
1902 info->dev = pdev;
1903 info->domain = domain;
1904 spin_lock_irqsave(&device_domain_lock, flags);
1905 /* somebody is fast */
1906 found = find_domain(pdev);
1907 if (found != NULL) {
1908 spin_unlock_irqrestore(&device_domain_lock, flags);
1909 if (found != domain) {
1910 domain_exit(domain);
1911 domain = found;
1912 }
1913 free_devinfo_mem(info);
1914 return domain;
1915 }
1916 list_add(&info->link, &domain->devices);
1917 list_add(&info->global, &device_domain_list);
358dd8ac 1918 pdev->dev.archdata.iommu = info;
ba395927
KA		 1919 spin_unlock_irqrestore(&device_domain_lock, flags);
1920 return domain;
1921error:
1922 /* recheck it here, maybe others set it */
1923 return find_domain(pdev);
1924}
1925
2c2e2c38
FY		 1926static int iommu_identity_mapping;
1927
b213203e
DW		 1928static int iommu_domain_identity_map(struct dmar_domain *domain,
1929 unsigned long long start,
1930 unsigned long long end)
ba395927 1931{
c5395d5c
DW		 1932 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1933 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1934
1935 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1936 dma_to_mm_pfn(last_vpfn))) {
ba395927 1937 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 1938 return -ENOMEM;
ba395927
KA		 1939 }
1940
c5395d5c
DW		 1941 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1942 start, end, domain->id);
ba395927
KA		 1943 /*
1944 * RMRR range might have overlap with physical memory range,
1945 * clear it first
1946 */
c5395d5c 1947 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 1948
c5395d5c
DW		 1949 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1950 last_vpfn - first_vpfn + 1,
61df7443 1951 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 1952}
1953
1954static int iommu_prepare_identity_map(struct pci_dev *pdev,
1955 unsigned long long start,
1956 unsigned long long end)
1957{
1958 struct dmar_domain *domain;
1959 int ret;
1960
1961 printk(KERN_INFO
1962 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1963 pci_name(pdev), start, end);
1964
c7ab48d2 1965 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 1966 if (!domain)
1967 return -ENOMEM;
1968
1969 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 1970 if (ret)
1971 goto error;
1972
1973 /* context entry init */
4ed0d3e6 1974 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 1975 if (ret)
1976 goto error;
1977
1978 return 0;
1979
1980 error:
ba395927
KA		 1981 domain_exit(domain);
1982 return ret;
ba395927
KA		 1983}
1984
1985static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1986 struct pci_dev *pdev)
1987{
358dd8ac 1988 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 1989 return 0;
1990 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1991 rmrr->end_address + 1);
1992}
1993
49a0429e
KA		 1994#ifdef CONFIG_DMAR_FLOPPY_WA
1995static inline void iommu_prepare_isa(void)
1996{
1997 struct pci_dev *pdev;
1998 int ret;
1999
2000 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2001 if (!pdev)
2002 return;
2003
c7ab48d2 2004 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
49a0429e
KA		 2005 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2006
2007 if (ret)
c7ab48d2
DW		 2008 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2009 "floppy might not work\n");
49a0429e
KA		 2010
2011}
2012#else
2013static inline void iommu_prepare_isa(void)
2014{
2015 return;
2016}
2017#endif /* !CONFIG_DMAR_FLPY_WA */
2018
4ed0d3e6
FY		 2019/* Initialize each context entry as pass through.*/
2020static int __init init_context_pass_through(void)
2021{
2022 struct pci_dev *pdev = NULL;
2023 struct dmar_domain *domain;
2024 int ret;
2025
2026 for_each_pci_dev(pdev) {
2027 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2028 ret = domain_context_mapping(domain, pdev,
2029 CONTEXT_TT_PASS_THROUGH);
2030 if (ret)
2031 return ret;
2032 }
2033 return 0;
2034}
2035
2c2e2c38 2036static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2
DW		 2037
2038static int __init si_domain_work_fn(unsigned long start_pfn,
2039 unsigned long end_pfn, void *datax)
2040{
2041 int *ret = datax;
2042
2043 *ret = iommu_domain_identity_map(si_domain,
2044 (uint64_t)start_pfn << PAGE_SHIFT,
2045 (uint64_t)end_pfn << PAGE_SHIFT);
2046 return *ret;
2047
2048}
2049
2c2e2c38
FY		 2050static int si_domain_init(void)
2051{
2052 struct dmar_drhd_unit *drhd;
2053 struct intel_iommu *iommu;
c7ab48d2 2054 int nid, ret = 0;
2c2e2c38
FY		 2055
2056 si_domain = alloc_domain();
2057 if (!si_domain)
2058 return -EFAULT;
2059
c7ab48d2 2060 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2c2e2c38
FY		 2061
2062 for_each_active_iommu(iommu, drhd) {
2063 ret = iommu_attach_domain(si_domain, iommu);
2064 if (ret) {
2065 domain_exit(si_domain);
2066 return -EFAULT;
2067 }
2068 }
2069
2070 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2071 domain_exit(si_domain);
2072 return -EFAULT;
2073 }
2074
2075 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2076
c7ab48d2
DW		 2077 for_each_online_node(nid) {
2078 work_with_active_regions(nid, si_domain_work_fn, &ret);
2079 if (ret)
2080 return ret;
2081 }
2082
2c2e2c38
FY		 2083 return 0;
2084}
2085
2086static void domain_remove_one_dev_info(struct dmar_domain *domain,
2087 struct pci_dev *pdev);
2088static int identity_mapping(struct pci_dev *pdev)
2089{
2090 struct device_domain_info *info;
2091
2092 if (likely(!iommu_identity_mapping))
2093 return 0;
2094
2095
2096 list_for_each_entry(info, &si_domain->devices, link)
2097 if (info->dev == pdev)
2098 return 1;
2099 return 0;
2100}
2101
2102static int domain_add_dev_info(struct dmar_domain *domain,
2103 struct pci_dev *pdev)
2104{
2105 struct device_domain_info *info;
2106 unsigned long flags;
2107
2108 info = alloc_devinfo_mem();
2109 if (!info)
2110 return -ENOMEM;
2111
2112 info->segment = pci_domain_nr(pdev->bus);
2113 info->bus = pdev->bus->number;
2114 info->devfn = pdev->devfn;
2115 info->dev = pdev;
2116 info->domain = domain;
2117
2118 spin_lock_irqsave(&device_domain_lock, flags);
2119 list_add(&info->link, &domain->devices);
2120 list_add(&info->global, &device_domain_list);
2121 pdev->dev.archdata.iommu = info;
2122 spin_unlock_irqrestore(&device_domain_lock, flags);
2123
2124 return 0;
2125}
2126
6941af28
DW		 2127static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2128{
2129 if (iommu_identity_mapping == 2)
2130 return IS_GFX_DEVICE(pdev);
2131
3dfc813d
DW		 2132 /*
2133 * We want to start off with all devices in the 1:1 domain, and
2134 * take them out later if we find they can't access all of memory.
2135 *
2136 * However, we can't do this for PCI devices behind bridges,
2137 * because all PCI devices behind the same bridge will end up
2138 * with the same source-id on their transactions.
2139 *
2140 * Practically speaking, we can't change things around for these
2141 * devices at run-time, because we can't be sure there'll be no
2142 * DMA transactions in flight for any of their siblings.
2143 *
2144 * So PCI devices (unless they're on the root bus) as well as
2145 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2146 * the 1:1 domain, just in _case_ one of their siblings turns out
2147 * not to be able to map all of memory.
2148 */
2149 if (!pdev->is_pcie) {
2150 if (!pci_is_root_bus(pdev->bus))
2151 return 0;
2152 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2153 return 0;
2154 } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2155 return 0;
2156
2157 /*
2158 * At boot time, we don't yet know if devices will be 64-bit capable.
2159 * Assume that they will -- if they turn out not to be, then we can
2160 * take them out of the 1:1 domain later.
2161 */
6941af28
DW		 2162 if (!startup)
2163 return pdev->dma_mask > DMA_BIT_MASK(32);
2164
2165 return 1;
2166}
2167
2c2e2c38
FY		 2168static int iommu_prepare_static_identity_mapping(void)
2169{
2c2e2c38
FY		 2170 struct pci_dev *pdev = NULL;
2171 int ret;
2172
2173 ret = si_domain_init();
2174 if (ret)
2175 return -EFAULT;
2176
2c2e2c38 2177 for_each_pci_dev(pdev) {
6941af28 2178 if (iommu_should_identity_map(pdev, 1)) {
62edf5dc
DW		 2179 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2180 pci_name(pdev));
2181
2182 ret = domain_context_mapping(si_domain, pdev,
2183 CONTEXT_TT_MULTI_LEVEL);
2184 if (ret)
2185 return ret;
2186 ret = domain_add_dev_info(si_domain, pdev);
2187 if (ret)
2188 return ret;
2189 }
2c2e2c38
FY		 2190 }
2191
2192 return 0;
2193}
2194
2195int __init init_dmars(void)
ba395927
KA		 2196{
2197 struct dmar_drhd_unit *drhd;
2198 struct dmar_rmrr_unit *rmrr;
2199 struct pci_dev *pdev;
2200 struct intel_iommu *iommu;
9d783ba0 2201 int i, ret;
4ed0d3e6 2202 int pass_through = 1;
ba395927 2203
2c2e2c38
FY		 2204 /*
2205 * In case pass through can not be enabled, iommu tries to use identity
2206 * mapping.
2207 */
2208 if (iommu_pass_through)
2209 iommu_identity_mapping = 1;
2210
ba395927
KA		 2211 /*
2212 * for each drhd
2213 * allocate root
2214 * initialize and program root entry to not present
2215 * endfor
2216 */
2217 for_each_drhd_unit(drhd) {
5e0d2a6f 2218 g_num_of_iommus++;
2219 /*
2220 * lock not needed as this is only incremented in the single
2221 * threaded kernel __init code path all other access are read
2222 * only
2223 */
2224 }
2225
d9630fe9
WH		 2226 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2227 GFP_KERNEL);
2228 if (!g_iommus) {
2229 printk(KERN_ERR "Allocating global iommu array failed\n");
2230 ret = -ENOMEM;
2231 goto error;
2232 }
2233
80b20dd8 2234 deferred_flush = kzalloc(g_num_of_iommus *
2235 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2236 if (!deferred_flush) {
d9630fe9 2237 kfree(g_iommus);
5e0d2a6f 2238 ret = -ENOMEM;
2239 goto error;
2240 }
2241
5e0d2a6f 2242 for_each_drhd_unit(drhd) {
2243 if (drhd->ignored)
2244 continue;
1886e8a9
SS		 2245
2246 iommu = drhd->iommu;
d9630fe9 2247 g_iommus[iommu->seq_id] = iommu;
ba395927 2248
e61d98d8
SS		 2249 ret = iommu_init_domains(iommu);
2250 if (ret)
2251 goto error;
2252
ba395927
KA		 2253 /*
2254 * TBD:
2255 * we could share the same root & context tables
2256 * amoung all IOMMU's. Need to Split it later.
2257 */
2258 ret = iommu_alloc_root_entry(iommu);
2259 if (ret) {
2260 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2261 goto error;
2262 }
4ed0d3e6
FY		 2263 if (!ecap_pass_through(iommu->ecap))
2264 pass_through = 0;
ba395927 2265 }
4ed0d3e6
FY		 2266 if (iommu_pass_through)
2267 if (!pass_through) {
2268 printk(KERN_INFO
2269 "Pass Through is not supported by hardware.\n");
2270 iommu_pass_through = 0;
2271 }
ba395927 2272
1531a6a6
SS		 2273 /*
2274 * Start from the sane iommu hardware state.
2275 */
a77b67d4
YS		 2276 for_each_drhd_unit(drhd) {
2277 if (drhd->ignored)
2278 continue;
2279
2280 iommu = drhd->iommu;
1531a6a6
SS		 2281
2282 /*
2283 * If the queued invalidation is already initialized by us
2284 * (for example, while enabling interrupt-remapping) then
2285 * we got the things already rolling from a sane state.
2286 */
2287 if (iommu->qi)
2288 continue;
2289
2290 /*
2291 * Clear any previous faults.
2292 */
2293 dmar_fault(-1, iommu);
2294 /*
2295 * Disable queued invalidation if supported and already enabled
2296 * before OS handover.
2297 */
2298 dmar_disable_qi(iommu);
2299 }
2300
2301 for_each_drhd_unit(drhd) {
2302 if (drhd->ignored)
2303 continue;
2304
2305 iommu = drhd->iommu;
2306
a77b67d4
YS		 2307 if (dmar_enable_qi(iommu)) {
2308 /*
2309 * Queued Invalidate not enabled, use Register Based
2310 * Invalidate
2311 */
2312 iommu->flush.flush_context = __iommu_flush_context;
2313 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2314 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
b4e0f9eb
FT		 2315 "invalidation\n",
2316 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2317 } else {
2318 iommu->flush.flush_context = qi_flush_context;
2319 iommu->flush.flush_iotlb = qi_flush_iotlb;
2320 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
b4e0f9eb
FT		 2321 "invalidation\n",
2322 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2323 }
2324 }
2325
ba395927 2326 /*
4ed0d3e6
FY		 2327 * If pass through is set and enabled, context entries of all pci
2328 * devices are intialized by pass through translation type.
ba395927 2329 */
4ed0d3e6
FY		 2330 if (iommu_pass_through) {
2331 ret = init_context_pass_through();
2332 if (ret) {
2333 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2334 iommu_pass_through = 0;
ba395927
KA		 2335 }
2336 }
2337
ba395927 2338 /*
4ed0d3e6 2339 * If pass through is not set or not enabled, setup context entries for
2c2e2c38
FY		 2340 * identity mappings for rmrr, gfx, and isa and may fall back to static
2341 * identity mapping if iommu_identity_mapping is set.
ba395927 2342 */
4ed0d3e6 2343 if (!iommu_pass_through) {
62edf5dc
DW		 2344#ifdef CONFIG_DMAR_BROKEN_GFX_WA
2345 if (!iommu_identity_mapping)
2346 iommu_identity_mapping = 2;
2347#endif
2c2e2c38
FY		 2348 if (iommu_identity_mapping)
2349 iommu_prepare_static_identity_mapping();
4ed0d3e6
FY		 2350 /*
2351 * For each rmrr
2352 * for each dev attached to rmrr
2353 * do
2354 * locate drhd for dev, alloc domain for dev
2355 * allocate free domain
2356 * allocate page table entries for rmrr
2357 * if context not allocated for bus
2358 * allocate and init context
2359 * set present in root table for this bus
2360 * init context with domain, translation etc
2361 * endfor
2362 * endfor
2363 */
2c2e2c38 2364 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
4ed0d3e6
FY		 2365 for_each_rmrr_units(rmrr) {
2366 for (i = 0; i < rmrr->devices_cnt; i++) {
2367 pdev = rmrr->devices[i];
2368 /*
2369 * some BIOS lists non-exist devices in DMAR
2370 * table.
2371 */
2372 if (!pdev)
2373 continue;
2374 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2375 if (ret)
2376 printk(KERN_ERR
ba395927 2377 "IOMMU: mapping reserved region failed\n");
4ed0d3e6 2378 }
ba395927 2379 }
ba395927 2380
4ed0d3e6
FY		 2381 iommu_prepare_isa();
2382 }
49a0429e 2383
ba395927
KA		 2384 /*
2385 * for each drhd
2386 * enable fault log
2387 * global invalidate context cache
2388 * global invalidate iotlb
2389 * enable translation
2390 */
2391 for_each_drhd_unit(drhd) {
2392 if (drhd->ignored)
2393 continue;
2394 iommu = drhd->iommu;
ba395927
KA		 2395
2396 iommu_flush_write_buffer(iommu);
2397
3460a6d9
KA		 2398 ret = dmar_set_interrupt(iommu);
2399 if (ret)
2400 goto error;
2401
ba395927
KA		 2402 iommu_set_root_entry(iommu);
2403
4c25a2c1 2404 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2405 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2406 iommu_disable_protect_mem_regions(iommu);
2407
ba395927
KA		 2408 ret = iommu_enable_translation(iommu);
2409 if (ret)
2410 goto error;
2411 }
2412
2413 return 0;
2414error:
2415 for_each_drhd_unit(drhd) {
2416 if (drhd->ignored)
2417 continue;
2418 iommu = drhd->iommu;
2419 free_iommu(iommu);
2420 }
d9630fe9 2421 kfree(g_iommus);
ba395927
KA		 2422 return ret;
2423}
2424
5a5e02a6 2425/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2426static struct iova *intel_alloc_iova(struct device *dev,
2427 struct dmar_domain *domain,
2428 unsigned long nrpages, uint64_t dma_mask)
ba395927 2429{
ba395927 2430 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2431 struct iova *iova = NULL;
ba395927 2432
875764de
DW		 2433 /* Restrict dma_mask to the width that the iommu can handle */
2434 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2435
2436 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2437 /*
2438 * First try to allocate an io virtual address in
284901a9 2439 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2440 * from higher range
ba395927 2441 */
875764de
DW		 2442 iova = alloc_iova(&domain->iovad, nrpages,
2443 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2444 if (iova)
2445 return iova;
2446 }
2447 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2448 if (unlikely(!iova)) {
2449 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2450 nrpages, pci_name(pdev));
f76aec76
KA		 2451 return NULL;
2452 }
2453
2454 return iova;
2455}
2456
2457static struct dmar_domain *
2458get_valid_domain_for_dev(struct pci_dev *pdev)
2459{
2460 struct dmar_domain *domain;
2461 int ret;
2462
2463 domain = get_domain_for_dev(pdev,
2464 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2465 if (!domain) {
2466 printk(KERN_ERR
2467 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2468 return NULL;
ba395927
KA		 2469 }
2470
2471 /* make sure context mapping is ok */
5331fe6f 2472 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2473 ret = domain_context_mapping(domain, pdev,
2474 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2475 if (ret) {
2476 printk(KERN_ERR
2477 "Domain context map for %s failed",
2478 pci_name(pdev));
4fe05bbc 2479 return NULL;
f76aec76 2480 }
ba395927
KA		 2481 }
2482
f76aec76
KA		 2483 return domain;
2484}
2485
2c2e2c38
FY		 2486static int iommu_dummy(struct pci_dev *pdev)
2487{
2488 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2489}
2490
2491/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2492static int iommu_no_mapping(struct device *dev)
2c2e2c38 2493{
73676832 2494 struct pci_dev *pdev;
2c2e2c38
FY		 2495 int found;
2496
73676832
DW		 2497 if (unlikely(dev->bus != &pci_bus_type))
2498 return 1;
2499
2500 pdev = to_pci_dev(dev);
1e4c64c4
DW		 2501 if (iommu_dummy(pdev))
2502 return 1;
2503
2c2e2c38 2504 if (!iommu_identity_mapping)
1e4c64c4 2505 return 0;
2c2e2c38
FY		 2506
2507 found = identity_mapping(pdev);
2508 if (found) {
6941af28 2509 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2510 return 1;
2511 else {
2512 /*
2513 * 32 bit DMA is removed from si_domain and fall back
2514 * to non-identity mapping.
2515 */
2516 domain_remove_one_dev_info(si_domain, pdev);
2517 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2518 pci_name(pdev));
2519 return 0;
2520 }
2521 } else {
2522 /*
2523 * In case of a detached 64 bit DMA device from vm, the device
2524 * is put into si_domain for identity mapping.
2525 */
6941af28 2526 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38
FY		 2527 int ret;
2528 ret = domain_add_dev_info(si_domain, pdev);
1b7bc0a1
DW		 2529 if (ret)
2530 return 0;
2531 ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2532 if (!ret) {
2533 printk(KERN_INFO "64bit %s uses identity mapping\n",
2534 pci_name(pdev));
2535 return 1;
2536 }
2537 }
2538 }
2539
1e4c64c4 2540 return 0;
2c2e2c38
FY		 2541}
2542
bb9e6d65
FT		 2543static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2544 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2545{
2546 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2547 struct dmar_domain *domain;
5b6985ce 2548 phys_addr_t start_paddr;
f76aec76
KA		 2549 struct iova *iova;
2550 int prot = 0;
6865f0d1 2551 int ret;
8c11e798 2552 struct intel_iommu *iommu;
33041ec0 2553 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2554
2555 BUG_ON(dir == DMA_NONE);
2c2e2c38 2556
73676832 2557 if (iommu_no_mapping(hwdev))
6865f0d1 2558 return paddr;
f76aec76
KA		 2559
2560 domain = get_valid_domain_for_dev(pdev);
2561 if (!domain)
2562 return 0;
2563
8c11e798 2564 iommu = domain_get_iommu(domain);
88cb6a74 2565 size = aligned_nrpages(paddr, size);
f76aec76 2566
5a5e02a6
DW		 2567 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2568 pdev->dma_mask);
f76aec76
KA		 2569 if (!iova)
2570 goto error;
2571
ba395927
KA		 2572 /*
2573 * Check if DMAR supports zero-length reads on write only
2574 * mappings..
2575 */
2576 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2577 !cap_zlr(iommu->cap))
ba395927
KA		 2578 prot |= DMA_PTE_READ;
2579 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2580 prot |= DMA_PTE_WRITE;
2581 /*
6865f0d1 2582 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2583 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2584 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2585 * is not a big problem
2586 */
0ab36de2 2587 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2588 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2589 if (ret)
2590 goto error;
2591
1f0ef2aa
DW		 2592 /* it's a non-present to present mapping. Only flush if caching mode */
2593 if (cap_caching_mode(iommu->cap))
03d6a246 2594 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
1f0ef2aa 2595 else
8c11e798 2596 iommu_flush_write_buffer(iommu);
f76aec76 2597
03d6a246
DW		 2598 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2599 start_paddr += paddr & ~PAGE_MASK;
2600 return start_paddr;
ba395927 2601
ba395927 2602error:
f76aec76
KA		 2603 if (iova)
2604 __free_iova(&domain->iovad, iova);
4cf2e75d 2605 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2606 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2607 return 0;
2608}
2609
ffbbef5c
FT		 2610static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2611 unsigned long offset, size_t size,
2612 enum dma_data_direction dir,
2613 struct dma_attrs *attrs)
bb9e6d65 2614{
ffbbef5c
FT		 2615 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2616 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2617}
2618
5e0d2a6f 2619static void flush_unmaps(void)
2620{
80b20dd8 2621 int i, j;
5e0d2a6f 2622
5e0d2a6f 2623 timer_on = 0;
2624
2625 /* just flush them all */
2626 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2627 struct intel_iommu *iommu = g_iommus[i];
2628 if (!iommu)
2629 continue;
c42d9f32 2630
9dd2fe89
YZ		 2631 if (!deferred_flush[i].next)
2632 continue;
2633
2634 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2635 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2636 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2637 unsigned long mask;
2638 struct iova *iova = deferred_flush[i].iova[j];
2639
2640 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2641 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2642 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2643 iova->pfn_lo << PAGE_SHIFT, mask);
2644 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2645 }
9dd2fe89 2646 deferred_flush[i].next = 0;
5e0d2a6f 2647 }
2648
5e0d2a6f 2649 list_size = 0;
5e0d2a6f 2650}
2651
2652static void flush_unmaps_timeout(unsigned long data)
2653{
80b20dd8 2654 unsigned long flags;
2655
2656 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2657 flush_unmaps();
80b20dd8 2658 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2659}
2660
2661static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2662{
2663 unsigned long flags;
80b20dd8 2664 int next, iommu_id;
8c11e798 2665 struct intel_iommu *iommu;
5e0d2a6f 2666
2667 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2668 if (list_size == HIGH_WATER_MARK)
2669 flush_unmaps();
2670
8c11e798
WH		 2671 iommu = domain_get_iommu(dom);
2672 iommu_id = iommu->seq_id;
c42d9f32 2673
80b20dd8 2674 next = deferred_flush[iommu_id].next;
2675 deferred_flush[iommu_id].domain[next] = dom;
2676 deferred_flush[iommu_id].iova[next] = iova;
2677 deferred_flush[iommu_id].next++;
5e0d2a6f 2678
2679 if (!timer_on) {
2680 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2681 timer_on = 1;
2682 }
2683 list_size++;
2684 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2685}
2686
ffbbef5c
FT		 2687static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2688 size_t size, enum dma_data_direction dir,
2689 struct dma_attrs *attrs)
ba395927 2690{
ba395927 2691 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 2692 struct dmar_domain *domain;
d794dc9b 2693 unsigned long start_pfn, last_pfn;
ba395927 2694 struct iova *iova;
8c11e798 2695 struct intel_iommu *iommu;
ba395927 2696
73676832 2697 if (iommu_no_mapping(dev))
f76aec76 2698 return;
2c2e2c38 2699
ba395927
KA		 2700 domain = find_domain(pdev);
2701 BUG_ON(!domain);
2702
8c11e798
WH		 2703 iommu = domain_get_iommu(domain);
2704
ba395927 2705 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 2706 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2707 (unsigned long long)dev_addr))
ba395927 2708 return;
ba395927 2709
d794dc9b
DW		 2710 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2711 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 2712
d794dc9b
DW		 2713 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2714 pci_name(pdev), start_pfn, last_pfn);
ba395927 2715
f76aec76 2716 /* clear the whole page */
d794dc9b
DW		 2717 dma_pte_clear_range(domain, start_pfn, last_pfn);
2718
f76aec76 2719 /* free page tables */
d794dc9b
DW		 2720 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2721
5e0d2a6f 2722 if (intel_iommu_strict) {
03d6a246 2723 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
d794dc9b 2724 last_pfn - start_pfn + 1);
5e0d2a6f 2725 /* free iova */
2726 __free_iova(&domain->iovad, iova);
2727 } else {
2728 add_unmap(domain, iova);
2729 /*
2730 * queue up the release of the unmap to save the 1/6th of the
2731 * cpu used up by the iotlb flush operation...
2732 */
5e0d2a6f 2733 }
ba395927
KA		 2734}
2735
d7ab5c46
FT		 2736static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2737 int dir)
ffbbef5c
FT		 2738{
2739 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2740}
2741
d7ab5c46
FT		 2742static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2743 dma_addr_t *dma_handle, gfp_t flags)
ba395927
KA		 2744{
2745 void *vaddr;
2746 int order;
2747
5b6985ce 2748 size = PAGE_ALIGN(size);
ba395927
KA		 2749 order = get_order(size);
2750 flags &= ~(GFP_DMA | GFP_DMA32);
2751
2752 vaddr = (void *)__get_free_pages(flags, order);
2753 if (!vaddr)
2754 return NULL;
2755 memset(vaddr, 0, size);
2756
bb9e6d65
FT		 2757 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2758 DMA_BIDIRECTIONAL,
2759 hwdev->coherent_dma_mask);
ba395927
KA		 2760 if (*dma_handle)
2761 return vaddr;
2762 free_pages((unsigned long)vaddr, order);
2763 return NULL;
2764}
2765
d7ab5c46
FT		 2766static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2767 dma_addr_t dma_handle)
ba395927
KA		 2768{
2769 int order;
2770
5b6985ce 2771 size = PAGE_ALIGN(size);
ba395927
KA		 2772 order = get_order(size);
2773
2774 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2775 free_pages((unsigned long)vaddr, order);
2776}
2777
d7ab5c46
FT		 2778static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2779 int nelems, enum dma_data_direction dir,
2780 struct dma_attrs *attrs)
ba395927 2781{
ba395927
KA		 2782 struct pci_dev *pdev = to_pci_dev(hwdev);
2783 struct dmar_domain *domain;
d794dc9b 2784 unsigned long start_pfn, last_pfn;
f76aec76 2785 struct iova *iova;
8c11e798 2786 struct intel_iommu *iommu;
ba395927 2787
73676832 2788 if (iommu_no_mapping(hwdev))
ba395927
KA		 2789 return;
2790
2791 domain = find_domain(pdev);
8c11e798
WH		 2792 BUG_ON(!domain);
2793
2794 iommu = domain_get_iommu(domain);
ba395927 2795
c03ab37c 2796 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 2797 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2798 (unsigned long long)sglist[0].dma_address))
f76aec76 2799 return;
f76aec76 2800
d794dc9b
DW		 2801 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2802 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76
KA		 2803
2804 /* clear the whole page */
d794dc9b
DW		 2805 dma_pte_clear_range(domain, start_pfn, last_pfn);
2806
f76aec76 2807 /* free page tables */
d794dc9b 2808 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
f76aec76 2809
03d6a246 2810 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
d794dc9b 2811 (last_pfn - start_pfn + 1));
f76aec76
KA		 2812
2813 /* free iova */
2814 __free_iova(&domain->iovad, iova);
ba395927
KA		 2815}
2816
ba395927 2817static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 2818 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 2819{
2820 int i;
c03ab37c 2821 struct scatterlist *sg;
ba395927 2822
c03ab37c 2823 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 2824 BUG_ON(!sg_page(sg));
4cf2e75d 2825 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 2826 sg->dma_length = sg->length;
ba395927
KA		 2827 }
2828 return nelems;
2829}
2830
d7ab5c46
FT		 2831static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2832 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 2833{
ba395927 2834 int i;
ba395927
KA		 2835 struct pci_dev *pdev = to_pci_dev(hwdev);
2836 struct dmar_domain *domain;
f76aec76
KA		 2837 size_t size = 0;
2838 int prot = 0;
b536d24d 2839 size_t offset_pfn = 0;
f76aec76
KA		 2840 struct iova *iova = NULL;
2841 int ret;
c03ab37c 2842 struct scatterlist *sg;
b536d24d 2843 unsigned long start_vpfn;
8c11e798 2844 struct intel_iommu *iommu;
ba395927
KA		 2845
2846 BUG_ON(dir == DMA_NONE);
73676832 2847 if (iommu_no_mapping(hwdev))
c03ab37c 2848 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 2849
f76aec76
KA		 2850 domain = get_valid_domain_for_dev(pdev);
2851 if (!domain)
2852 return 0;
2853
8c11e798
WH		 2854 iommu = domain_get_iommu(domain);
2855
b536d24d 2856 for_each_sg(sglist, sg, nelems, i)
88cb6a74 2857 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 2858
5a5e02a6
DW		 2859 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2860 pdev->dma_mask);
f76aec76 2861 if (!iova) {
c03ab37c 2862 sglist->dma_length = 0;
f76aec76
KA		 2863 return 0;
2864 }
2865
2866 /*
2867 * Check if DMAR supports zero-length reads on write only
2868 * mappings..
2869 */
2870 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2871 !cap_zlr(iommu->cap))
f76aec76
KA		 2872 prot |= DMA_PTE_READ;
2873 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2874 prot |= DMA_PTE_WRITE;
2875
b536d24d 2876 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 2877
f532959b 2878 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 2879 if (unlikely(ret)) {
2880 /* clear the page */
2881 dma_pte_clear_range(domain, start_vpfn,
2882 start_vpfn + size - 1);
2883 /* free page tables */
2884 dma_pte_free_pagetable(domain, start_vpfn,
2885 start_vpfn + size - 1);
2886 /* free iova */
2887 __free_iova(&domain->iovad, iova);
2888 return 0;
ba395927
KA		 2889 }
2890
1f0ef2aa
DW		 2891 /* it's a non-present to present mapping. Only flush if caching mode */
2892 if (cap_caching_mode(iommu->cap))
03d6a246 2893 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
1f0ef2aa 2894 else
8c11e798 2895 iommu_flush_write_buffer(iommu);
1f0ef2aa 2896
ba395927
KA		 2897 return nelems;
2898}
2899
dfb805e8
FT		 2900static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2901{
2902 return !dma_addr;
2903}
2904
160c1d8e 2905struct dma_map_ops intel_dma_ops = {
ba395927
KA		 2906 .alloc_coherent = intel_alloc_coherent,
2907 .free_coherent = intel_free_coherent,
ba395927
KA		 2908 .map_sg = intel_map_sg,
2909 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 2910 .map_page = intel_map_page,
2911 .unmap_page = intel_unmap_page,
dfb805e8 2912 .mapping_error = intel_mapping_error,
ba395927
KA		 2913};
2914
2915static inline int iommu_domain_cache_init(void)
2916{
2917 int ret = 0;
2918
2919 iommu_domain_cache = kmem_cache_create("iommu_domain",
2920 sizeof(struct dmar_domain),
2921 0,
2922 SLAB_HWCACHE_ALIGN,
2923
2924 NULL);
2925 if (!iommu_domain_cache) {
2926 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2927 ret = -ENOMEM;
2928 }
2929
2930 return ret;
2931}
2932
2933static inline int iommu_devinfo_cache_init(void)
2934{
2935 int ret = 0;
2936
2937 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2938 sizeof(struct device_domain_info),
2939 0,
2940 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2941 NULL);
2942 if (!iommu_devinfo_cache) {
2943 printk(KERN_ERR "Couldn't create devinfo cache\n");
2944 ret = -ENOMEM;
2945 }
2946
2947 return ret;
2948}
2949
2950static inline int iommu_iova_cache_init(void)
2951{
2952 int ret = 0;
2953
2954 iommu_iova_cache = kmem_cache_create("iommu_iova",
2955 sizeof(struct iova),
2956 0,
2957 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2958 NULL);
2959 if (!iommu_iova_cache) {
2960 printk(KERN_ERR "Couldn't create iova cache\n");
2961 ret = -ENOMEM;
2962 }
2963
2964 return ret;
2965}
2966
2967static int __init iommu_init_mempool(void)
2968{
2969 int ret;
2970 ret = iommu_iova_cache_init();
2971 if (ret)
2972 return ret;
2973
2974 ret = iommu_domain_cache_init();
2975 if (ret)
2976 goto domain_error;
2977
2978 ret = iommu_devinfo_cache_init();
2979 if (!ret)
2980 return ret;
2981
2982 kmem_cache_destroy(iommu_domain_cache);
2983domain_error:
2984 kmem_cache_destroy(iommu_iova_cache);
2985
2986 return -ENOMEM;
2987}
2988
2989static void __init iommu_exit_mempool(void)
2990{
2991 kmem_cache_destroy(iommu_devinfo_cache);
2992 kmem_cache_destroy(iommu_domain_cache);
2993 kmem_cache_destroy(iommu_iova_cache);
2994
2995}
2996
ba395927
KA		 2997static void __init init_no_remapping_devices(void)
2998{
2999 struct dmar_drhd_unit *drhd;
3000
3001 for_each_drhd_unit(drhd) {
3002 if (!drhd->include_all) {
3003 int i;
3004 for (i = 0; i < drhd->devices_cnt; i++)
3005 if (drhd->devices[i] != NULL)
3006 break;
3007 /* ignore DMAR unit if no pci devices exist */
3008 if (i == drhd->devices_cnt)
3009 drhd->ignored = 1;
3010 }
3011 }
3012
3013 if (dmar_map_gfx)
3014 return;
3015
3016 for_each_drhd_unit(drhd) {
3017 int i;
3018 if (drhd->ignored || drhd->include_all)
3019 continue;
3020
3021 for (i = 0; i < drhd->devices_cnt; i++)
3022 if (drhd->devices[i] &&
3023 !IS_GFX_DEVICE(drhd->devices[i]))
3024 break;
3025
3026 if (i < drhd->devices_cnt)
3027 continue;
3028
3029 /* bypass IOMMU if it is just for gfx devices */
3030 drhd->ignored = 1;
3031 for (i = 0; i < drhd->devices_cnt; i++) {
3032 if (!drhd->devices[i])
3033 continue;
358dd8ac 3034 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3035 }
3036 }
3037}
3038
f59c7b69
FY		 3039#ifdef CONFIG_SUSPEND
3040static int init_iommu_hw(void)
3041{
3042 struct dmar_drhd_unit *drhd;
3043 struct intel_iommu *iommu = NULL;
3044
3045 for_each_active_iommu(iommu, drhd)
3046 if (iommu->qi)
3047 dmar_reenable_qi(iommu);
3048
3049 for_each_active_iommu(iommu, drhd) {
3050 iommu_flush_write_buffer(iommu);
3051
3052 iommu_set_root_entry(iommu);
3053
3054 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3055 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3056 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3057 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3058 iommu_disable_protect_mem_regions(iommu);
3059 iommu_enable_translation(iommu);
3060 }
3061
3062 return 0;
3063}
3064
3065static void iommu_flush_all(void)
3066{
3067 struct dmar_drhd_unit *drhd;
3068 struct intel_iommu *iommu;
3069
3070 for_each_active_iommu(iommu, drhd) {
3071 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3072 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3073 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3074 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3075 }
3076}
3077
3078static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3079{
3080 struct dmar_drhd_unit *drhd;
3081 struct intel_iommu *iommu = NULL;
3082 unsigned long flag;
3083
3084 for_each_active_iommu(iommu, drhd) {
3085 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3086 GFP_ATOMIC);
3087 if (!iommu->iommu_state)
3088 goto nomem;
3089 }
3090
3091 iommu_flush_all();
3092
3093 for_each_active_iommu(iommu, drhd) {
3094 iommu_disable_translation(iommu);
3095
3096 spin_lock_irqsave(&iommu->register_lock, flag);
3097
3098 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3099 readl(iommu->reg + DMAR_FECTL_REG);
3100 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3101 readl(iommu->reg + DMAR_FEDATA_REG);
3102 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3103 readl(iommu->reg + DMAR_FEADDR_REG);
3104 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3105 readl(iommu->reg + DMAR_FEUADDR_REG);
3106
3107 spin_unlock_irqrestore(&iommu->register_lock, flag);
3108 }
3109 return 0;
3110
3111nomem:
3112 for_each_active_iommu(iommu, drhd)
3113 kfree(iommu->iommu_state);
3114
3115 return -ENOMEM;
3116}
3117
3118static int iommu_resume(struct sys_device *dev)
3119{
3120 struct dmar_drhd_unit *drhd;
3121 struct intel_iommu *iommu = NULL;
3122 unsigned long flag;
3123
3124 if (init_iommu_hw()) {
3125 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3126 return -EIO;
3127 }
3128
3129 for_each_active_iommu(iommu, drhd) {
3130
3131 spin_lock_irqsave(&iommu->register_lock, flag);
3132
3133 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3134 iommu->reg + DMAR_FECTL_REG);
3135 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3136 iommu->reg + DMAR_FEDATA_REG);
3137 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3138 iommu->reg + DMAR_FEADDR_REG);
3139 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3140 iommu->reg + DMAR_FEUADDR_REG);
3141
3142 spin_unlock_irqrestore(&iommu->register_lock, flag);
3143 }
3144
3145 for_each_active_iommu(iommu, drhd)
3146 kfree(iommu->iommu_state);
3147
3148 return 0;
3149}
3150
3151static struct sysdev_class iommu_sysclass = {
3152 .name = "iommu",
3153 .resume = iommu_resume,
3154 .suspend = iommu_suspend,
3155};
3156
3157static struct sys_device device_iommu = {
3158 .cls = &iommu_sysclass,
3159};
3160
3161static int __init init_iommu_sysfs(void)
3162{
3163 int error;
3164
3165 error = sysdev_class_register(&iommu_sysclass);
3166 if (error)
3167 return error;
3168
3169 error = sysdev_register(&device_iommu);
3170 if (error)
3171 sysdev_class_unregister(&iommu_sysclass);
3172
3173 return error;
3174}
3175
3176#else
3177static int __init init_iommu_sysfs(void)
3178{
3179 return 0;
3180}
3181#endif /* CONFIG_PM */
3182
ba395927
KA		 3183int __init intel_iommu_init(void)
3184{
3185 int ret = 0;
3186
ba395927
KA		 3187 if (dmar_table_init())
3188 return -ENODEV;
3189
1886e8a9
SS		 3190 if (dmar_dev_scope_init())
3191 return -ENODEV;
3192
2ae21010
SS		 3193 /*
3194 * Check the need for DMA-remapping initialization now.
3195 * Above initialization will also be used by Interrupt-remapping.
3196 */
4ed0d3e6 3197 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
2ae21010
SS		 3198 return -ENODEV;
3199
ba395927
KA		 3200 iommu_init_mempool();
3201 dmar_init_reserved_ranges();
3202
3203 init_no_remapping_devices();
3204
3205 ret = init_dmars();
3206 if (ret) {
3207 printk(KERN_ERR "IOMMU: dmar init failed\n");
3208 put_iova_domain(&reserved_iova_list);
3209 iommu_exit_mempool();
3210 return ret;
3211 }
3212 printk(KERN_INFO
3213 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3214
5e0d2a6f 3215 init_timer(&unmap_timer);
ba395927 3216 force_iommu = 1;
4ed0d3e6
FY		 3217
3218 if (!iommu_pass_through) {
3219 printk(KERN_INFO
3220 "Multi-level page-table translation for DMAR.\n");
3221 dma_ops = &intel_dma_ops;
3222 } else
3223 printk(KERN_INFO
3224 "DMAR: Pass through translation for DMAR.\n");
3225
f59c7b69 3226 init_iommu_sysfs();
a8bcbb0d
JR		 3227
3228 register_iommu(&intel_iommu_ops);
3229
ba395927
KA		 3230 return 0;
3231}
e820482c 3232
3199aa6b
HW		 3233static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3234 struct pci_dev *pdev)
3235{
3236 struct pci_dev *tmp, *parent;
3237
3238 if (!iommu || !pdev)
3239 return;
3240
3241 /* dependent device detach */
3242 tmp = pci_find_upstream_pcie_bridge(pdev);
3243 /* Secondary interface's bus number and devfn 0 */
3244 if (tmp) {
3245 parent = pdev->bus->self;
3246 while (parent != tmp) {
3247 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3248 parent->devfn);
3199aa6b
HW		 3249 parent = parent->bus->self;
3250 }
3251 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3252 iommu_detach_dev(iommu,
3253 tmp->subordinate->number, 0);
3254 else /* this is a legacy PCI bridge */
276dbf99
DW		 3255 iommu_detach_dev(iommu, tmp->bus->number,
3256 tmp->devfn);
3199aa6b
HW		 3257 }
3258}
3259
2c2e2c38 3260static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3261 struct pci_dev *pdev)
3262{
3263 struct device_domain_info *info;
3264 struct intel_iommu *iommu;
3265 unsigned long flags;
3266 int found = 0;
3267 struct list_head *entry, *tmp;
3268
276dbf99
DW		 3269 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3270 pdev->devfn);
c7151a8d
WH		 3271 if (!iommu)
3272 return;
3273
3274 spin_lock_irqsave(&device_domain_lock, flags);
3275 list_for_each_safe(entry, tmp, &domain->devices) {
3276 info = list_entry(entry, struct device_domain_info, link);
276dbf99 3277 /* No need to compare PCI domain; it has to be the same */
c7151a8d
WH		 3278 if (info->bus == pdev->bus->number &&
3279 info->devfn == pdev->devfn) {
3280 list_del(&info->link);
3281 list_del(&info->global);
3282 if (info->dev)
3283 info->dev->dev.archdata.iommu = NULL;
3284 spin_unlock_irqrestore(&device_domain_lock, flags);
3285
93a23a72 3286 iommu_disable_dev_iotlb(info);
c7151a8d 3287 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3288 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3289 free_devinfo_mem(info);
3290
3291 spin_lock_irqsave(&device_domain_lock, flags);
3292
3293 if (found)
3294 break;
3295 else
3296 continue;
3297 }
3298
3299 /* if there is no other devices under the same iommu
3300 * owned by this domain, clear this iommu in iommu_bmp
3301 * update iommu count and coherency
3302 */
276dbf99
DW		 3303 if (iommu == device_to_iommu(info->segment, info->bus,
3304 info->devfn))
c7151a8d
WH		 3305 found = 1;
3306 }
3307
3308 if (found == 0) {
3309 unsigned long tmp_flags;
3310 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3311 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3312 domain->iommu_count--;
58c610bd 3313 domain_update_iommu_cap(domain);
c7151a8d
WH		 3314 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3315 }
3316
3317 spin_unlock_irqrestore(&device_domain_lock, flags);
3318}
3319
3320static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3321{
3322 struct device_domain_info *info;
3323 struct intel_iommu *iommu;
3324 unsigned long flags1, flags2;
3325
3326 spin_lock_irqsave(&device_domain_lock, flags1);
3327 while (!list_empty(&domain->devices)) {
3328 info = list_entry(domain->devices.next,
3329 struct device_domain_info, link);
3330 list_del(&info->link);
3331 list_del(&info->global);
3332 if (info->dev)
3333 info->dev->dev.archdata.iommu = NULL;
3334
3335 spin_unlock_irqrestore(&device_domain_lock, flags1);
3336
93a23a72 3337 iommu_disable_dev_iotlb(info);
276dbf99 3338 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3339 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3340 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3341
3342 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3343 * and capabilities
c7151a8d
WH		 3344 */
3345 spin_lock_irqsave(&domain->iommu_lock, flags2);
3346 if (test_and_clear_bit(iommu->seq_id,
3347 &domain->iommu_bmp)) {
3348 domain->iommu_count--;
58c610bd 3349 domain_update_iommu_cap(domain);
c7151a8d
WH		 3350 }
3351 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3352
3353 free_devinfo_mem(info);
3354 spin_lock_irqsave(&device_domain_lock, flags1);
3355 }
3356 spin_unlock_irqrestore(&device_domain_lock, flags1);
3357}
3358
5e98c4b1
WH		 3359/* domain id for virtual machine, it won't be set in context */
3360static unsigned long vm_domid;
3361
fe40f1e0
WH		 3362static int vm_domain_min_agaw(struct dmar_domain *domain)
3363{
3364 int i;
3365 int min_agaw = domain->agaw;
3366
3367 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3368 for (; i < g_num_of_iommus; ) {
3369 if (min_agaw > g_iommus[i]->agaw)
3370 min_agaw = g_iommus[i]->agaw;
3371
3372 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3373 }
3374
3375 return min_agaw;
3376}
3377
5e98c4b1
WH		 3378static struct dmar_domain *iommu_alloc_vm_domain(void)
3379{
3380 struct dmar_domain *domain;
3381
3382 domain = alloc_domain_mem();
3383 if (!domain)
3384 return NULL;
3385
3386 domain->id = vm_domid++;
3387 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3388 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3389
3390 return domain;
3391}
3392
2c2e2c38 3393static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3394{
3395 int adjust_width;
3396
3397 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 3398 spin_lock_init(&domain->iommu_lock);
3399
3400 domain_reserve_special_ranges(domain);
3401
3402 /* calculate AGAW */
3403 domain->gaw = guest_width;
3404 adjust_width = guestwidth_to_adjustwidth(guest_width);
3405 domain->agaw = width_to_agaw(adjust_width);
3406
3407 INIT_LIST_HEAD(&domain->devices);
3408
3409 domain->iommu_count = 0;
3410 domain->iommu_coherency = 0;
c5b15255 3411 domain->iommu_snooping = 0;
fe40f1e0 3412 domain->max_addr = 0;
5e98c4b1
WH		 3413
3414 /* always allocate the top pgd */
3415 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3416 if (!domain->pgd)
3417 return -ENOMEM;
3418 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3419 return 0;
3420}
3421
3422static void iommu_free_vm_domain(struct dmar_domain *domain)
3423{
3424 unsigned long flags;
3425 struct dmar_drhd_unit *drhd;
3426 struct intel_iommu *iommu;
3427 unsigned long i;
3428 unsigned long ndomains;
3429
3430 for_each_drhd_unit(drhd) {
3431 if (drhd->ignored)
3432 continue;
3433 iommu = drhd->iommu;
3434
3435 ndomains = cap_ndoms(iommu->cap);
3436 i = find_first_bit(iommu->domain_ids, ndomains);
3437 for (; i < ndomains; ) {
3438 if (iommu->domains[i] == domain) {
3439 spin_lock_irqsave(&iommu->lock, flags);
3440 clear_bit(i, iommu->domain_ids);
3441 iommu->domains[i] = NULL;
3442 spin_unlock_irqrestore(&iommu->lock, flags);
3443 break;
3444 }
3445 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3446 }
3447 }
3448}
3449
3450static void vm_domain_exit(struct dmar_domain *domain)
3451{
5e98c4b1
WH		 3452 /* Domain 0 is reserved, so dont process it */
3453 if (!domain)
3454 return;
3455
3456 vm_domain_remove_all_dev_info(domain);
3457 /* destroy iovas */
3458 put_iova_domain(&domain->iovad);
5e98c4b1
WH		 3459
3460 /* clear ptes */
595badf5 3461 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3462
3463 /* free page tables */
d794dc9b 3464 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3465
3466 iommu_free_vm_domain(domain);
3467 free_domain_mem(domain);
3468}
3469
5d450806 3470static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3471{
5d450806 3472 struct dmar_domain *dmar_domain;
38717946 3473
5d450806
JR		 3474 dmar_domain = iommu_alloc_vm_domain();
3475 if (!dmar_domain) {
38717946 3476 printk(KERN_ERR
5d450806
JR		 3477 "intel_iommu_domain_init: dmar_domain == NULL\n");
3478 return -ENOMEM;
38717946 3479 }
2c2e2c38 3480 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3481 printk(KERN_ERR
5d450806
JR		 3482 "intel_iommu_domain_init() failed\n");
3483 vm_domain_exit(dmar_domain);
3484 return -ENOMEM;
38717946 3485 }
5d450806 3486 domain->priv = dmar_domain;
faa3d6f5 3487
5d450806 3488 return 0;
38717946 3489}
38717946 3490
5d450806 3491static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3492{
5d450806
JR		 3493 struct dmar_domain *dmar_domain = domain->priv;
3494
3495 domain->priv = NULL;
3496 vm_domain_exit(dmar_domain);
38717946 3497}
38717946 3498
4c5478c9
JR		 3499static int intel_iommu_attach_device(struct iommu_domain *domain,
3500 struct device *dev)
38717946 3501{
4c5478c9
JR		 3502 struct dmar_domain *dmar_domain = domain->priv;
3503 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3504 struct intel_iommu *iommu;
3505 int addr_width;
3506 u64 end;
faa3d6f5
WH		 3507 int ret;
3508
3509 /* normally pdev is not mapped */
3510 if (unlikely(domain_context_mapped(pdev))) {
3511 struct dmar_domain *old_domain;
3512
3513 old_domain = find_domain(pdev);
3514 if (old_domain) {
2c2e2c38
FY		 3515 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3516 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3517 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 3518 else
3519 domain_remove_dev_info(old_domain);
3520 }
3521 }
3522
276dbf99
DW		 3523 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3524 pdev->devfn);
fe40f1e0
WH		 3525 if (!iommu)
3526 return -ENODEV;
3527
3528 /* check if this iommu agaw is sufficient for max mapped address */
3529 addr_width = agaw_to_width(iommu->agaw);
3530 end = DOMAIN_MAX_ADDR(addr_width);
3531 end = end & VTD_PAGE_MASK;
4c5478c9 3532 if (end < dmar_domain->max_addr) {
fe40f1e0
WH		 3533 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3534 "sufficient for the mapped address (%llx)\n",
4c5478c9 3535 __func__, iommu->agaw, dmar_domain->max_addr);
fe40f1e0
WH		 3536 return -EFAULT;
3537 }
3538
2c2e2c38 3539 ret = domain_add_dev_info(dmar_domain, pdev);
faa3d6f5
WH		 3540 if (ret)
3541 return ret;
3542
93a23a72 3543 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
faa3d6f5 3544 return ret;
38717946 3545}
38717946 3546
4c5478c9
JR		 3547static void intel_iommu_detach_device(struct iommu_domain *domain,
3548 struct device *dev)
38717946 3549{
4c5478c9
JR		 3550 struct dmar_domain *dmar_domain = domain->priv;
3551 struct pci_dev *pdev = to_pci_dev(dev);
3552
2c2e2c38 3553 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 3554}
c7151a8d 3555
dde57a21
JR		 3556static int intel_iommu_map_range(struct iommu_domain *domain,
3557 unsigned long iova, phys_addr_t hpa,
3558 size_t size, int iommu_prot)
faa3d6f5 3559{
dde57a21 3560 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0
WH		 3561 u64 max_addr;
3562 int addr_width;
dde57a21 3563 int prot = 0;
faa3d6f5 3564 int ret;
fe40f1e0 3565
dde57a21
JR		 3566 if (iommu_prot & IOMMU_READ)
3567 prot |= DMA_PTE_READ;
3568 if (iommu_prot & IOMMU_WRITE)
3569 prot |= DMA_PTE_WRITE;
9cf06697
SY		 3570 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3571 prot |= DMA_PTE_SNP;
dde57a21 3572
163cc52c 3573 max_addr = iova + size;
dde57a21 3574 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 3575 int min_agaw;
3576 u64 end;
3577
3578 /* check if minimum agaw is sufficient for mapped address */
dde57a21 3579 min_agaw = vm_domain_min_agaw(dmar_domain);
fe40f1e0
WH		 3580 addr_width = agaw_to_width(min_agaw);
3581 end = DOMAIN_MAX_ADDR(addr_width);
3582 end = end & VTD_PAGE_MASK;
3583 if (end < max_addr) {
3584 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3585 "sufficient for the mapped address (%llx)\n",
3586 __func__, min_agaw, max_addr);
3587 return -EFAULT;
3588 }
dde57a21 3589 dmar_domain->max_addr = max_addr;
fe40f1e0 3590 }
ad051221
DW		 3591 /* Round up size to next multiple of PAGE_SIZE, if it and
3592 the low bits of hpa would take us onto the next page */
88cb6a74 3593 size = aligned_nrpages(hpa, size);
ad051221
DW		 3594 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3595 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 3596 return ret;
38717946 3597}
38717946 3598
dde57a21
JR		 3599static void intel_iommu_unmap_range(struct iommu_domain *domain,
3600 unsigned long iova, size_t size)
38717946 3601{
dde57a21 3602 struct dmar_domain *dmar_domain = domain->priv;
faa3d6f5 3603
4b99d352
SY		 3604 if (!size)
3605 return;
3606
163cc52c
DW		 3607 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3608 (iova + size - 1) >> VTD_PAGE_SHIFT);
fe40f1e0 3609
163cc52c
DW		 3610 if (dmar_domain->max_addr == iova + size)
3611 dmar_domain->max_addr = iova;
38717946 3612}
38717946 3613
d14d6577
JR		 3614static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3615 unsigned long iova)
38717946 3616{
d14d6577 3617 struct dmar_domain *dmar_domain = domain->priv;
38717946 3618 struct dma_pte *pte;
faa3d6f5 3619 u64 phys = 0;
38717946 3620
b026fd28 3621 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
38717946 3622 if (pte)
faa3d6f5 3623 phys = dma_pte_addr(pte);
38717946 3624
faa3d6f5 3625 return phys;
38717946 3626}
a8bcbb0d 3627
dbb9fd86
SY		 3628static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3629 unsigned long cap)
3630{
3631 struct dmar_domain *dmar_domain = domain->priv;
3632
3633 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3634 return dmar_domain->iommu_snooping;
3635
3636 return 0;
3637}
3638
a8bcbb0d
JR		 3639static struct iommu_ops intel_iommu_ops = {
3640 .domain_init = intel_iommu_domain_init,
3641 .domain_destroy = intel_iommu_domain_destroy,
3642 .attach_dev = intel_iommu_attach_device,
3643 .detach_dev = intel_iommu_detach_device,
3644 .map = intel_iommu_map_range,
3645 .unmap = intel_iommu_unmap_range,
3646 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 3647 .domain_has_cap = intel_iommu_domain_has_cap,
a8bcbb0d 3648};
9af88143
DW		 3649
3650static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3651{
3652 /*
3653 * Mobile 4 Series Chipset neglects to set RWBF capability,
3654 * but needs it:
3655 */
3656 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3657 rwbf_quirk = 1;
3658}
3659
3660DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
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