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ba395927 KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Shaohua Li <shaohua.li@intel.com> | |
20 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
5b6985ce | 21 | * Author: Fenghua Yu <fenghua.yu@intel.com> |
ba395927 KA |
22 | */ |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/bitmap.h> | |
5e0d2a6f | 26 | #include <linux/debugfs.h> |
ba395927 KA |
27 | #include <linux/slab.h> |
28 | #include <linux/irq.h> | |
29 | #include <linux/interrupt.h> | |
ba395927 KA |
30 | #include <linux/spinlock.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/dmar.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/mempool.h> | |
5e0d2a6f | 35 | #include <linux/timer.h> |
38717946 | 36 | #include <linux/iova.h> |
5d450806 | 37 | #include <linux/iommu.h> |
38717946 | 38 | #include <linux/intel-iommu.h> |
f59c7b69 | 39 | #include <linux/sysdev.h> |
ba395927 | 40 | #include <asm/cacheflush.h> |
46a7fa27 | 41 | #include <asm/iommu.h> |
ba395927 KA |
42 | #include "pci.h" |
43 | ||
5b6985ce FY |
44 | #define ROOT_SIZE VTD_PAGE_SIZE |
45 | #define CONTEXT_SIZE VTD_PAGE_SIZE | |
46 | ||
ba395927 KA |
47 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
48 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) | |
49 | ||
50 | #define IOAPIC_RANGE_START (0xfee00000) | |
51 | #define IOAPIC_RANGE_END (0xfeefffff) | |
52 | #define IOVA_START_ADDR (0x1000) | |
53 | ||
54 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
55 | ||
4ed0d3e6 FY |
56 | #define MAX_AGAW_WIDTH 64 |
57 | ||
ba395927 | 58 | #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1) |
595badf5 | 59 | #define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
ba395927 | 60 | |
f27be03b | 61 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
284901a9 | 62 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
6a35528a | 63 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
5e0d2a6f | 64 | |
fd18de50 | 65 | |
dd4e8319 DW |
66 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
67 | are never going to work. */ | |
68 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) | |
69 | { | |
70 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
71 | } | |
72 | ||
73 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) | |
74 | { | |
75 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
76 | } | |
77 | static inline unsigned long page_to_dma_pfn(struct page *pg) | |
78 | { | |
79 | return mm_to_dma_pfn(page_to_pfn(pg)); | |
80 | } | |
81 | static inline unsigned long virt_to_dma_pfn(void *p) | |
82 | { | |
83 | return page_to_dma_pfn(virt_to_page(p)); | |
84 | } | |
85 | ||
d9630fe9 WH |
86 | /* global iommu list, set NULL for ignored DMAR units */ |
87 | static struct intel_iommu **g_iommus; | |
88 | ||
9af88143 DW |
89 | static int rwbf_quirk; |
90 | ||
46b08e1a MM |
91 | /* |
92 | * 0: Present | |
93 | * 1-11: Reserved | |
94 | * 12-63: Context Ptr (12 - (haw-1)) | |
95 | * 64-127: Reserved | |
96 | */ | |
97 | struct root_entry { | |
98 | u64 val; | |
99 | u64 rsvd1; | |
100 | }; | |
101 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) | |
102 | static inline bool root_present(struct root_entry *root) | |
103 | { | |
104 | return (root->val & 1); | |
105 | } | |
106 | static inline void set_root_present(struct root_entry *root) | |
107 | { | |
108 | root->val |= 1; | |
109 | } | |
110 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
111 | { | |
112 | root->val |= value & VTD_PAGE_MASK; | |
113 | } | |
114 | ||
115 | static inline struct context_entry * | |
116 | get_context_addr_from_root(struct root_entry *root) | |
117 | { | |
118 | return (struct context_entry *) | |
119 | (root_present(root)?phys_to_virt( | |
120 | root->val & VTD_PAGE_MASK) : | |
121 | NULL); | |
122 | } | |
123 | ||
7a8fc25e MM |
124 | /* |
125 | * low 64 bits: | |
126 | * 0: present | |
127 | * 1: fault processing disable | |
128 | * 2-3: translation type | |
129 | * 12-63: address space root | |
130 | * high 64 bits: | |
131 | * 0-2: address width | |
132 | * 3-6: aval | |
133 | * 8-23: domain id | |
134 | */ | |
135 | struct context_entry { | |
136 | u64 lo; | |
137 | u64 hi; | |
138 | }; | |
c07e7d21 MM |
139 | |
140 | static inline bool context_present(struct context_entry *context) | |
141 | { | |
142 | return (context->lo & 1); | |
143 | } | |
144 | static inline void context_set_present(struct context_entry *context) | |
145 | { | |
146 | context->lo |= 1; | |
147 | } | |
148 | ||
149 | static inline void context_set_fault_enable(struct context_entry *context) | |
150 | { | |
151 | context->lo &= (((u64)-1) << 2) | 1; | |
152 | } | |
153 | ||
c07e7d21 MM |
154 | static inline void context_set_translation_type(struct context_entry *context, |
155 | unsigned long value) | |
156 | { | |
157 | context->lo &= (((u64)-1) << 4) | 3; | |
158 | context->lo |= (value & 3) << 2; | |
159 | } | |
160 | ||
161 | static inline void context_set_address_root(struct context_entry *context, | |
162 | unsigned long value) | |
163 | { | |
164 | context->lo |= value & VTD_PAGE_MASK; | |
165 | } | |
166 | ||
167 | static inline void context_set_address_width(struct context_entry *context, | |
168 | unsigned long value) | |
169 | { | |
170 | context->hi |= value & 7; | |
171 | } | |
172 | ||
173 | static inline void context_set_domain_id(struct context_entry *context, | |
174 | unsigned long value) | |
175 | { | |
176 | context->hi |= (value & ((1 << 16) - 1)) << 8; | |
177 | } | |
178 | ||
179 | static inline void context_clear_entry(struct context_entry *context) | |
180 | { | |
181 | context->lo = 0; | |
182 | context->hi = 0; | |
183 | } | |
7a8fc25e | 184 | |
622ba12a MM |
185 | /* |
186 | * 0: readable | |
187 | * 1: writable | |
188 | * 2-6: reserved | |
189 | * 7: super page | |
9cf06697 SY |
190 | * 8-10: available |
191 | * 11: snoop behavior | |
622ba12a MM |
192 | * 12-63: Host physcial address |
193 | */ | |
194 | struct dma_pte { | |
195 | u64 val; | |
196 | }; | |
622ba12a | 197 | |
19c239ce MM |
198 | static inline void dma_clear_pte(struct dma_pte *pte) |
199 | { | |
200 | pte->val = 0; | |
201 | } | |
202 | ||
203 | static inline void dma_set_pte_readable(struct dma_pte *pte) | |
204 | { | |
205 | pte->val |= DMA_PTE_READ; | |
206 | } | |
207 | ||
208 | static inline void dma_set_pte_writable(struct dma_pte *pte) | |
209 | { | |
210 | pte->val |= DMA_PTE_WRITE; | |
211 | } | |
212 | ||
9cf06697 SY |
213 | static inline void dma_set_pte_snp(struct dma_pte *pte) |
214 | { | |
215 | pte->val |= DMA_PTE_SNP; | |
216 | } | |
217 | ||
19c239ce MM |
218 | static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot) |
219 | { | |
220 | pte->val = (pte->val & ~3) | (prot & 3); | |
221 | } | |
222 | ||
223 | static inline u64 dma_pte_addr(struct dma_pte *pte) | |
224 | { | |
c85994e4 DW |
225 | #ifdef CONFIG_64BIT |
226 | return pte->val & VTD_PAGE_MASK; | |
227 | #else | |
228 | /* Must have a full atomic 64-bit read */ | |
229 | return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK; | |
230 | #endif | |
19c239ce MM |
231 | } |
232 | ||
dd4e8319 | 233 | static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn) |
19c239ce | 234 | { |
dd4e8319 | 235 | pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT; |
19c239ce MM |
236 | } |
237 | ||
238 | static inline bool dma_pte_present(struct dma_pte *pte) | |
239 | { | |
240 | return (pte->val & 3) != 0; | |
241 | } | |
622ba12a | 242 | |
75e6bf96 DW |
243 | static inline int first_pte_in_page(struct dma_pte *pte) |
244 | { | |
245 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
246 | } | |
247 | ||
2c2e2c38 FY |
248 | /* |
249 | * This domain is a statically identity mapping domain. | |
250 | * 1. This domain creats a static 1:1 mapping to all usable memory. | |
251 | * 2. It maps to each iommu if successful. | |
252 | * 3. Each iommu mapps to this domain if successful. | |
253 | */ | |
254 | struct dmar_domain *si_domain; | |
255 | ||
3b5410e7 | 256 | /* devices under the same p2p bridge are owned in one domain */ |
cdc7b837 | 257 | #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0) |
3b5410e7 | 258 | |
1ce28feb WH |
259 | /* domain represents a virtual machine, more than one devices |
260 | * across iommus may be owned in one domain, e.g. kvm guest. | |
261 | */ | |
262 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1) | |
263 | ||
2c2e2c38 FY |
264 | /* si_domain contains mulitple devices */ |
265 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2) | |
266 | ||
99126f7c MM |
267 | struct dmar_domain { |
268 | int id; /* domain id */ | |
8c11e798 | 269 | unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/ |
99126f7c MM |
270 | |
271 | struct list_head devices; /* all devices' list */ | |
272 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
273 | ||
274 | struct dma_pte *pgd; /* virtual address */ | |
99126f7c MM |
275 | int gaw; /* max guest address width */ |
276 | ||
277 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
278 | int agaw; | |
279 | ||
3b5410e7 | 280 | int flags; /* flags to find out type of domain */ |
8e604097 WH |
281 | |
282 | int iommu_coherency;/* indicate coherency of iommu access */ | |
58c610bd | 283 | int iommu_snooping; /* indicate snooping control feature*/ |
c7151a8d WH |
284 | int iommu_count; /* reference count of iommu */ |
285 | spinlock_t iommu_lock; /* protect iommu set in domain */ | |
fe40f1e0 | 286 | u64 max_addr; /* maximum mapped address */ |
99126f7c MM |
287 | }; |
288 | ||
a647dacb MM |
289 | /* PCI domain-device relationship */ |
290 | struct device_domain_info { | |
291 | struct list_head link; /* link to domain siblings */ | |
292 | struct list_head global; /* link to global list */ | |
276dbf99 DW |
293 | int segment; /* PCI domain */ |
294 | u8 bus; /* PCI bus number */ | |
a647dacb MM |
295 | u8 devfn; /* PCI devfn number */ |
296 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ | |
93a23a72 | 297 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
a647dacb MM |
298 | struct dmar_domain *domain; /* pointer to domain */ |
299 | }; | |
300 | ||
5e0d2a6f | 301 | static void flush_unmaps_timeout(unsigned long data); |
302 | ||
303 | DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); | |
304 | ||
80b20dd8 | 305 | #define HIGH_WATER_MARK 250 |
306 | struct deferred_flush_tables { | |
307 | int next; | |
308 | struct iova *iova[HIGH_WATER_MARK]; | |
309 | struct dmar_domain *domain[HIGH_WATER_MARK]; | |
310 | }; | |
311 | ||
312 | static struct deferred_flush_tables *deferred_flush; | |
313 | ||
5e0d2a6f | 314 | /* bitmap for indexing intel_iommus */ |
5e0d2a6f | 315 | static int g_num_of_iommus; |
316 | ||
317 | static DEFINE_SPINLOCK(async_umap_flush_lock); | |
318 | static LIST_HEAD(unmaps_to_do); | |
319 | ||
320 | static int timer_on; | |
321 | static long list_size; | |
5e0d2a6f | 322 | |
ba395927 KA |
323 | static void domain_remove_dev_info(struct dmar_domain *domain); |
324 | ||
0cd5c3c8 KM |
325 | #ifdef CONFIG_DMAR_DEFAULT_ON |
326 | int dmar_disabled = 0; | |
327 | #else | |
328 | int dmar_disabled = 1; | |
329 | #endif /*CONFIG_DMAR_DEFAULT_ON*/ | |
330 | ||
ba395927 | 331 | static int __initdata dmar_map_gfx = 1; |
7d3b03ce | 332 | static int dmar_forcedac; |
5e0d2a6f | 333 | static int intel_iommu_strict; |
ba395927 KA |
334 | |
335 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) | |
336 | static DEFINE_SPINLOCK(device_domain_lock); | |
337 | static LIST_HEAD(device_domain_list); | |
338 | ||
a8bcbb0d JR |
339 | static struct iommu_ops intel_iommu_ops; |
340 | ||
ba395927 KA |
341 | static int __init intel_iommu_setup(char *str) |
342 | { | |
343 | if (!str) | |
344 | return -EINVAL; | |
345 | while (*str) { | |
0cd5c3c8 KM |
346 | if (!strncmp(str, "on", 2)) { |
347 | dmar_disabled = 0; | |
348 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); | |
349 | } else if (!strncmp(str, "off", 3)) { | |
ba395927 | 350 | dmar_disabled = 1; |
0cd5c3c8 | 351 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
ba395927 KA |
352 | } else if (!strncmp(str, "igfx_off", 8)) { |
353 | dmar_map_gfx = 0; | |
354 | printk(KERN_INFO | |
355 | "Intel-IOMMU: disable GFX device mapping\n"); | |
7d3b03ce | 356 | } else if (!strncmp(str, "forcedac", 8)) { |
5e0d2a6f | 357 | printk(KERN_INFO |
7d3b03ce KA |
358 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
359 | dmar_forcedac = 1; | |
5e0d2a6f | 360 | } else if (!strncmp(str, "strict", 6)) { |
361 | printk(KERN_INFO | |
362 | "Intel-IOMMU: disable batched IOTLB flush\n"); | |
363 | intel_iommu_strict = 1; | |
ba395927 KA |
364 | } |
365 | ||
366 | str += strcspn(str, ","); | |
367 | while (*str == ',') | |
368 | str++; | |
369 | } | |
370 | return 0; | |
371 | } | |
372 | __setup("intel_iommu=", intel_iommu_setup); | |
373 | ||
374 | static struct kmem_cache *iommu_domain_cache; | |
375 | static struct kmem_cache *iommu_devinfo_cache; | |
376 | static struct kmem_cache *iommu_iova_cache; | |
377 | ||
eb3fa7cb KA |
378 | static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep) |
379 | { | |
380 | unsigned int flags; | |
381 | void *vaddr; | |
382 | ||
383 | /* trying to avoid low memory issues */ | |
384 | flags = current->flags & PF_MEMALLOC; | |
385 | current->flags |= PF_MEMALLOC; | |
386 | vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC); | |
387 | current->flags &= (~PF_MEMALLOC | flags); | |
388 | return vaddr; | |
389 | } | |
390 | ||
391 | ||
ba395927 KA |
392 | static inline void *alloc_pgtable_page(void) |
393 | { | |
eb3fa7cb KA |
394 | unsigned int flags; |
395 | void *vaddr; | |
396 | ||
397 | /* trying to avoid low memory issues */ | |
398 | flags = current->flags & PF_MEMALLOC; | |
399 | current->flags |= PF_MEMALLOC; | |
400 | vaddr = (void *)get_zeroed_page(GFP_ATOMIC); | |
401 | current->flags &= (~PF_MEMALLOC | flags); | |
402 | return vaddr; | |
ba395927 KA |
403 | } |
404 | ||
405 | static inline void free_pgtable_page(void *vaddr) | |
406 | { | |
407 | free_page((unsigned long)vaddr); | |
408 | } | |
409 | ||
410 | static inline void *alloc_domain_mem(void) | |
411 | { | |
eb3fa7cb | 412 | return iommu_kmem_cache_alloc(iommu_domain_cache); |
ba395927 KA |
413 | } |
414 | ||
38717946 | 415 | static void free_domain_mem(void *vaddr) |
ba395927 KA |
416 | { |
417 | kmem_cache_free(iommu_domain_cache, vaddr); | |
418 | } | |
419 | ||
420 | static inline void * alloc_devinfo_mem(void) | |
421 | { | |
eb3fa7cb | 422 | return iommu_kmem_cache_alloc(iommu_devinfo_cache); |
ba395927 KA |
423 | } |
424 | ||
425 | static inline void free_devinfo_mem(void *vaddr) | |
426 | { | |
427 | kmem_cache_free(iommu_devinfo_cache, vaddr); | |
428 | } | |
429 | ||
430 | struct iova *alloc_iova_mem(void) | |
431 | { | |
eb3fa7cb | 432 | return iommu_kmem_cache_alloc(iommu_iova_cache); |
ba395927 KA |
433 | } |
434 | ||
435 | void free_iova_mem(struct iova *iova) | |
436 | { | |
437 | kmem_cache_free(iommu_iova_cache, iova); | |
438 | } | |
439 | ||
1b573683 WH |
440 | |
441 | static inline int width_to_agaw(int width); | |
442 | ||
4ed0d3e6 | 443 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
1b573683 WH |
444 | { |
445 | unsigned long sagaw; | |
446 | int agaw = -1; | |
447 | ||
448 | sagaw = cap_sagaw(iommu->cap); | |
4ed0d3e6 | 449 | for (agaw = width_to_agaw(max_gaw); |
1b573683 WH |
450 | agaw >= 0; agaw--) { |
451 | if (test_bit(agaw, &sagaw)) | |
452 | break; | |
453 | } | |
454 | ||
455 | return agaw; | |
456 | } | |
457 | ||
4ed0d3e6 FY |
458 | /* |
459 | * Calculate max SAGAW for each iommu. | |
460 | */ | |
461 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
462 | { | |
463 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); | |
464 | } | |
465 | ||
466 | /* | |
467 | * calculate agaw for each iommu. | |
468 | * "SAGAW" may be different across iommus, use a default agaw, and | |
469 | * get a supported less agaw for iommus that don't support the default agaw. | |
470 | */ | |
471 | int iommu_calculate_agaw(struct intel_iommu *iommu) | |
472 | { | |
473 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
474 | } | |
475 | ||
2c2e2c38 | 476 | /* This functionin only returns single iommu in a domain */ |
8c11e798 WH |
477 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
478 | { | |
479 | int iommu_id; | |
480 | ||
2c2e2c38 | 481 | /* si_domain and vm domain should not get here. */ |
1ce28feb | 482 | BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE); |
2c2e2c38 | 483 | BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY); |
1ce28feb | 484 | |
8c11e798 WH |
485 | iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); |
486 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) | |
487 | return NULL; | |
488 | ||
489 | return g_iommus[iommu_id]; | |
490 | } | |
491 | ||
8e604097 WH |
492 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
493 | { | |
494 | int i; | |
495 | ||
496 | domain->iommu_coherency = 1; | |
497 | ||
498 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
499 | for (; i < g_num_of_iommus; ) { | |
500 | if (!ecap_coherent(g_iommus[i]->ecap)) { | |
501 | domain->iommu_coherency = 0; | |
502 | break; | |
503 | } | |
504 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
505 | } | |
506 | } | |
507 | ||
58c610bd SY |
508 | static void domain_update_iommu_snooping(struct dmar_domain *domain) |
509 | { | |
510 | int i; | |
511 | ||
512 | domain->iommu_snooping = 1; | |
513 | ||
514 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
515 | for (; i < g_num_of_iommus; ) { | |
516 | if (!ecap_sc_support(g_iommus[i]->ecap)) { | |
517 | domain->iommu_snooping = 0; | |
518 | break; | |
519 | } | |
520 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
521 | } | |
522 | } | |
523 | ||
524 | /* Some capabilities may be different across iommus */ | |
525 | static void domain_update_iommu_cap(struct dmar_domain *domain) | |
526 | { | |
527 | domain_update_iommu_coherency(domain); | |
528 | domain_update_iommu_snooping(domain); | |
529 | } | |
530 | ||
276dbf99 | 531 | static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn) |
c7151a8d WH |
532 | { |
533 | struct dmar_drhd_unit *drhd = NULL; | |
534 | int i; | |
535 | ||
536 | for_each_drhd_unit(drhd) { | |
537 | if (drhd->ignored) | |
538 | continue; | |
276dbf99 DW |
539 | if (segment != drhd->segment) |
540 | continue; | |
c7151a8d | 541 | |
924b6231 | 542 | for (i = 0; i < drhd->devices_cnt; i++) { |
288e4877 DH |
543 | if (drhd->devices[i] && |
544 | drhd->devices[i]->bus->number == bus && | |
c7151a8d WH |
545 | drhd->devices[i]->devfn == devfn) |
546 | return drhd->iommu; | |
4958c5dc DW |
547 | if (drhd->devices[i] && |
548 | drhd->devices[i]->subordinate && | |
924b6231 DW |
549 | drhd->devices[i]->subordinate->number <= bus && |
550 | drhd->devices[i]->subordinate->subordinate >= bus) | |
551 | return drhd->iommu; | |
552 | } | |
c7151a8d WH |
553 | |
554 | if (drhd->include_all) | |
555 | return drhd->iommu; | |
556 | } | |
557 | ||
558 | return NULL; | |
559 | } | |
560 | ||
5331fe6f WH |
561 | static void domain_flush_cache(struct dmar_domain *domain, |
562 | void *addr, int size) | |
563 | { | |
564 | if (!domain->iommu_coherency) | |
565 | clflush_cache_range(addr, size); | |
566 | } | |
567 | ||
ba395927 KA |
568 | /* Gets context entry for a given bus and devfn */ |
569 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, | |
570 | u8 bus, u8 devfn) | |
571 | { | |
572 | struct root_entry *root; | |
573 | struct context_entry *context; | |
574 | unsigned long phy_addr; | |
575 | unsigned long flags; | |
576 | ||
577 | spin_lock_irqsave(&iommu->lock, flags); | |
578 | root = &iommu->root_entry[bus]; | |
579 | context = get_context_addr_from_root(root); | |
580 | if (!context) { | |
581 | context = (struct context_entry *)alloc_pgtable_page(); | |
582 | if (!context) { | |
583 | spin_unlock_irqrestore(&iommu->lock, flags); | |
584 | return NULL; | |
585 | } | |
5b6985ce | 586 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
ba395927 KA |
587 | phy_addr = virt_to_phys((void *)context); |
588 | set_root_value(root, phy_addr); | |
589 | set_root_present(root); | |
590 | __iommu_flush_cache(iommu, root, sizeof(*root)); | |
591 | } | |
592 | spin_unlock_irqrestore(&iommu->lock, flags); | |
593 | return &context[devfn]; | |
594 | } | |
595 | ||
596 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
597 | { | |
598 | struct root_entry *root; | |
599 | struct context_entry *context; | |
600 | int ret; | |
601 | unsigned long flags; | |
602 | ||
603 | spin_lock_irqsave(&iommu->lock, flags); | |
604 | root = &iommu->root_entry[bus]; | |
605 | context = get_context_addr_from_root(root); | |
606 | if (!context) { | |
607 | ret = 0; | |
608 | goto out; | |
609 | } | |
c07e7d21 | 610 | ret = context_present(&context[devfn]); |
ba395927 KA |
611 | out: |
612 | spin_unlock_irqrestore(&iommu->lock, flags); | |
613 | return ret; | |
614 | } | |
615 | ||
616 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
617 | { | |
618 | struct root_entry *root; | |
619 | struct context_entry *context; | |
620 | unsigned long flags; | |
621 | ||
622 | spin_lock_irqsave(&iommu->lock, flags); | |
623 | root = &iommu->root_entry[bus]; | |
624 | context = get_context_addr_from_root(root); | |
625 | if (context) { | |
c07e7d21 | 626 | context_clear_entry(&context[devfn]); |
ba395927 KA |
627 | __iommu_flush_cache(iommu, &context[devfn], \ |
628 | sizeof(*context)); | |
629 | } | |
630 | spin_unlock_irqrestore(&iommu->lock, flags); | |
631 | } | |
632 | ||
633 | static void free_context_table(struct intel_iommu *iommu) | |
634 | { | |
635 | struct root_entry *root; | |
636 | int i; | |
637 | unsigned long flags; | |
638 | struct context_entry *context; | |
639 | ||
640 | spin_lock_irqsave(&iommu->lock, flags); | |
641 | if (!iommu->root_entry) { | |
642 | goto out; | |
643 | } | |
644 | for (i = 0; i < ROOT_ENTRY_NR; i++) { | |
645 | root = &iommu->root_entry[i]; | |
646 | context = get_context_addr_from_root(root); | |
647 | if (context) | |
648 | free_pgtable_page(context); | |
649 | } | |
650 | free_pgtable_page(iommu->root_entry); | |
651 | iommu->root_entry = NULL; | |
652 | out: | |
653 | spin_unlock_irqrestore(&iommu->lock, flags); | |
654 | } | |
655 | ||
656 | /* page table handling */ | |
657 | #define LEVEL_STRIDE (9) | |
658 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) | |
659 | ||
660 | static inline int agaw_to_level(int agaw) | |
661 | { | |
662 | return agaw + 2; | |
663 | } | |
664 | ||
665 | static inline int agaw_to_width(int agaw) | |
666 | { | |
667 | return 30 + agaw * LEVEL_STRIDE; | |
668 | ||
669 | } | |
670 | ||
671 | static inline int width_to_agaw(int width) | |
672 | { | |
673 | return (width - 30) / LEVEL_STRIDE; | |
674 | } | |
675 | ||
676 | static inline unsigned int level_to_offset_bits(int level) | |
677 | { | |
6660c63a | 678 | return (level - 1) * LEVEL_STRIDE; |
ba395927 KA |
679 | } |
680 | ||
77dfa56c | 681 | static inline int pfn_level_offset(unsigned long pfn, int level) |
ba395927 | 682 | { |
6660c63a | 683 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; |
ba395927 KA |
684 | } |
685 | ||
6660c63a | 686 | static inline unsigned long level_mask(int level) |
ba395927 | 687 | { |
6660c63a | 688 | return -1UL << level_to_offset_bits(level); |
ba395927 KA |
689 | } |
690 | ||
6660c63a | 691 | static inline unsigned long level_size(int level) |
ba395927 | 692 | { |
6660c63a | 693 | return 1UL << level_to_offset_bits(level); |
ba395927 KA |
694 | } |
695 | ||
6660c63a | 696 | static inline unsigned long align_to_level(unsigned long pfn, int level) |
ba395927 | 697 | { |
6660c63a | 698 | return (pfn + level_size(level) - 1) & level_mask(level); |
ba395927 KA |
699 | } |
700 | ||
b026fd28 DW |
701 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
702 | unsigned long pfn) | |
ba395927 | 703 | { |
b026fd28 | 704 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
ba395927 KA |
705 | struct dma_pte *parent, *pte = NULL; |
706 | int level = agaw_to_level(domain->agaw); | |
707 | int offset; | |
ba395927 KA |
708 | |
709 | BUG_ON(!domain->pgd); | |
b026fd28 | 710 | BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width); |
ba395927 KA |
711 | parent = domain->pgd; |
712 | ||
ba395927 KA |
713 | while (level > 0) { |
714 | void *tmp_page; | |
715 | ||
b026fd28 | 716 | offset = pfn_level_offset(pfn, level); |
ba395927 KA |
717 | pte = &parent[offset]; |
718 | if (level == 1) | |
719 | break; | |
720 | ||
19c239ce | 721 | if (!dma_pte_present(pte)) { |
c85994e4 DW |
722 | uint64_t pteval; |
723 | ||
ba395927 KA |
724 | tmp_page = alloc_pgtable_page(); |
725 | ||
206a73c1 | 726 | if (!tmp_page) |
ba395927 | 727 | return NULL; |
206a73c1 | 728 | |
c85994e4 DW |
729 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
730 | pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; | |
731 | if (cmpxchg64(&pte->val, 0ULL, pteval)) { | |
732 | /* Someone else set it while we were thinking; use theirs. */ | |
733 | free_pgtable_page(tmp_page); | |
734 | } else { | |
735 | dma_pte_addr(pte); | |
736 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
737 | } | |
ba395927 | 738 | } |
19c239ce | 739 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
740 | level--; |
741 | } | |
742 | ||
ba395927 KA |
743 | return pte; |
744 | } | |
745 | ||
746 | /* return address's pte at specific level */ | |
90dcfb5e DW |
747 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
748 | unsigned long pfn, | |
749 | int level) | |
ba395927 KA |
750 | { |
751 | struct dma_pte *parent, *pte = NULL; | |
752 | int total = agaw_to_level(domain->agaw); | |
753 | int offset; | |
754 | ||
755 | parent = domain->pgd; | |
756 | while (level <= total) { | |
90dcfb5e | 757 | offset = pfn_level_offset(pfn, total); |
ba395927 KA |
758 | pte = &parent[offset]; |
759 | if (level == total) | |
760 | return pte; | |
761 | ||
19c239ce | 762 | if (!dma_pte_present(pte)) |
ba395927 | 763 | break; |
19c239ce | 764 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
765 | total--; |
766 | } | |
767 | return NULL; | |
768 | } | |
769 | ||
ba395927 | 770 | /* clear last level pte, a tlb flush should be followed */ |
595badf5 DW |
771 | static void dma_pte_clear_range(struct dmar_domain *domain, |
772 | unsigned long start_pfn, | |
773 | unsigned long last_pfn) | |
ba395927 | 774 | { |
04b18e65 | 775 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
310a5ab9 | 776 | struct dma_pte *first_pte, *pte; |
66eae846 | 777 | |
04b18e65 | 778 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
595badf5 | 779 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
ba395927 | 780 | |
04b18e65 | 781 | /* we don't need lock here; nobody else touches the iova range */ |
595badf5 | 782 | while (start_pfn <= last_pfn) { |
310a5ab9 DW |
783 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1); |
784 | if (!pte) { | |
785 | start_pfn = align_to_level(start_pfn + 1, 2); | |
786 | continue; | |
787 | } | |
75e6bf96 | 788 | do { |
310a5ab9 DW |
789 | dma_clear_pte(pte); |
790 | start_pfn++; | |
791 | pte++; | |
75e6bf96 DW |
792 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
793 | ||
310a5ab9 DW |
794 | domain_flush_cache(domain, first_pte, |
795 | (void *)pte - (void *)first_pte); | |
ba395927 KA |
796 | } |
797 | } | |
798 | ||
799 | /* free page table pages. last level pte should already be cleared */ | |
800 | static void dma_pte_free_pagetable(struct dmar_domain *domain, | |
d794dc9b DW |
801 | unsigned long start_pfn, |
802 | unsigned long last_pfn) | |
ba395927 | 803 | { |
6660c63a | 804 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
f3a0a52f | 805 | struct dma_pte *first_pte, *pte; |
ba395927 KA |
806 | int total = agaw_to_level(domain->agaw); |
807 | int level; | |
6660c63a | 808 | unsigned long tmp; |
ba395927 | 809 | |
6660c63a DW |
810 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
811 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); | |
ba395927 | 812 | |
f3a0a52f | 813 | /* We don't need lock here; nobody else touches the iova range */ |
ba395927 KA |
814 | level = 2; |
815 | while (level <= total) { | |
6660c63a DW |
816 | tmp = align_to_level(start_pfn, level); |
817 | ||
f3a0a52f | 818 | /* If we can't even clear one PTE at this level, we're done */ |
6660c63a | 819 | if (tmp + level_size(level) - 1 > last_pfn) |
ba395927 KA |
820 | return; |
821 | ||
3d7b0e41 | 822 | while (tmp + level_size(level) - 1 <= last_pfn) { |
f3a0a52f DW |
823 | first_pte = pte = dma_pfn_level_pte(domain, tmp, level); |
824 | if (!pte) { | |
825 | tmp = align_to_level(tmp + 1, level + 1); | |
826 | continue; | |
827 | } | |
75e6bf96 | 828 | do { |
6a43e574 DW |
829 | if (dma_pte_present(pte)) { |
830 | free_pgtable_page(phys_to_virt(dma_pte_addr(pte))); | |
831 | dma_clear_pte(pte); | |
832 | } | |
f3a0a52f DW |
833 | pte++; |
834 | tmp += level_size(level); | |
75e6bf96 DW |
835 | } while (!first_pte_in_page(pte) && |
836 | tmp + level_size(level) - 1 <= last_pfn); | |
837 | ||
f3a0a52f DW |
838 | domain_flush_cache(domain, first_pte, |
839 | (void *)pte - (void *)first_pte); | |
840 | ||
ba395927 KA |
841 | } |
842 | level++; | |
843 | } | |
844 | /* free pgd */ | |
d794dc9b | 845 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
ba395927 KA |
846 | free_pgtable_page(domain->pgd); |
847 | domain->pgd = NULL; | |
848 | } | |
849 | } | |
850 | ||
851 | /* iommu handling */ | |
852 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |
853 | { | |
854 | struct root_entry *root; | |
855 | unsigned long flags; | |
856 | ||
857 | root = (struct root_entry *)alloc_pgtable_page(); | |
858 | if (!root) | |
859 | return -ENOMEM; | |
860 | ||
5b6985ce | 861 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
ba395927 KA |
862 | |
863 | spin_lock_irqsave(&iommu->lock, flags); | |
864 | iommu->root_entry = root; | |
865 | spin_unlock_irqrestore(&iommu->lock, flags); | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
ba395927 KA |
870 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
871 | { | |
872 | void *addr; | |
c416daa9 | 873 | u32 sts; |
ba395927 KA |
874 | unsigned long flag; |
875 | ||
876 | addr = iommu->root_entry; | |
877 | ||
878 | spin_lock_irqsave(&iommu->register_lock, flag); | |
879 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); | |
880 | ||
c416daa9 | 881 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
882 | |
883 | /* Make sure hardware complete it */ | |
884 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 885 | readl, (sts & DMA_GSTS_RTPS), sts); |
ba395927 KA |
886 | |
887 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
888 | } | |
889 | ||
890 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |
891 | { | |
892 | u32 val; | |
893 | unsigned long flag; | |
894 | ||
9af88143 | 895 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
ba395927 | 896 | return; |
ba395927 KA |
897 | |
898 | spin_lock_irqsave(&iommu->register_lock, flag); | |
462b60f6 | 899 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
900 | |
901 | /* Make sure hardware complete it */ | |
902 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 903 | readl, (!(val & DMA_GSTS_WBFS)), val); |
ba395927 KA |
904 | |
905 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
906 | } | |
907 | ||
908 | /* return value determine if we need a write buffer flush */ | |
4c25a2c1 DW |
909 | static void __iommu_flush_context(struct intel_iommu *iommu, |
910 | u16 did, u16 source_id, u8 function_mask, | |
911 | u64 type) | |
ba395927 KA |
912 | { |
913 | u64 val = 0; | |
914 | unsigned long flag; | |
915 | ||
ba395927 KA |
916 | switch (type) { |
917 | case DMA_CCMD_GLOBAL_INVL: | |
918 | val = DMA_CCMD_GLOBAL_INVL; | |
919 | break; | |
920 | case DMA_CCMD_DOMAIN_INVL: | |
921 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); | |
922 | break; | |
923 | case DMA_CCMD_DEVICE_INVL: | |
924 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) | |
925 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); | |
926 | break; | |
927 | default: | |
928 | BUG(); | |
929 | } | |
930 | val |= DMA_CCMD_ICC; | |
931 | ||
932 | spin_lock_irqsave(&iommu->register_lock, flag); | |
933 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); | |
934 | ||
935 | /* Make sure hardware complete it */ | |
936 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, | |
937 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); | |
938 | ||
939 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
ba395927 KA |
940 | } |
941 | ||
ba395927 | 942 | /* return value determine if we need a write buffer flush */ |
1f0ef2aa DW |
943 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
944 | u64 addr, unsigned int size_order, u64 type) | |
ba395927 KA |
945 | { |
946 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); | |
947 | u64 val = 0, val_iva = 0; | |
948 | unsigned long flag; | |
949 | ||
ba395927 KA |
950 | switch (type) { |
951 | case DMA_TLB_GLOBAL_FLUSH: | |
952 | /* global flush doesn't need set IVA_REG */ | |
953 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; | |
954 | break; | |
955 | case DMA_TLB_DSI_FLUSH: | |
956 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
957 | break; | |
958 | case DMA_TLB_PSI_FLUSH: | |
959 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
960 | /* Note: always flush non-leaf currently */ | |
961 | val_iva = size_order | addr; | |
962 | break; | |
963 | default: | |
964 | BUG(); | |
965 | } | |
966 | /* Note: set drain read/write */ | |
967 | #if 0 | |
968 | /* | |
969 | * This is probably to be super secure.. Looks like we can | |
970 | * ignore it without any impact. | |
971 | */ | |
972 | if (cap_read_drain(iommu->cap)) | |
973 | val |= DMA_TLB_READ_DRAIN; | |
974 | #endif | |
975 | if (cap_write_drain(iommu->cap)) | |
976 | val |= DMA_TLB_WRITE_DRAIN; | |
977 | ||
978 | spin_lock_irqsave(&iommu->register_lock, flag); | |
979 | /* Note: Only uses first TLB reg currently */ | |
980 | if (val_iva) | |
981 | dmar_writeq(iommu->reg + tlb_offset, val_iva); | |
982 | dmar_writeq(iommu->reg + tlb_offset + 8, val); | |
983 | ||
984 | /* Make sure hardware complete it */ | |
985 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, | |
986 | dmar_readq, (!(val & DMA_TLB_IVT)), val); | |
987 | ||
988 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
989 | ||
990 | /* check IOTLB invalidation granularity */ | |
991 | if (DMA_TLB_IAIG(val) == 0) | |
992 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); | |
993 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) | |
994 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", | |
5b6985ce FY |
995 | (unsigned long long)DMA_TLB_IIRG(type), |
996 | (unsigned long long)DMA_TLB_IAIG(val)); | |
ba395927 KA |
997 | } |
998 | ||
93a23a72 YZ |
999 | static struct device_domain_info *iommu_support_dev_iotlb( |
1000 | struct dmar_domain *domain, int segment, u8 bus, u8 devfn) | |
1001 | { | |
1002 | int found = 0; | |
1003 | unsigned long flags; | |
1004 | struct device_domain_info *info; | |
1005 | struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn); | |
1006 | ||
1007 | if (!ecap_dev_iotlb_support(iommu->ecap)) | |
1008 | return NULL; | |
1009 | ||
1010 | if (!iommu->qi) | |
1011 | return NULL; | |
1012 | ||
1013 | spin_lock_irqsave(&device_domain_lock, flags); | |
1014 | list_for_each_entry(info, &domain->devices, link) | |
1015 | if (info->bus == bus && info->devfn == devfn) { | |
1016 | found = 1; | |
1017 | break; | |
1018 | } | |
1019 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1020 | ||
1021 | if (!found || !info->dev) | |
1022 | return NULL; | |
1023 | ||
1024 | if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS)) | |
1025 | return NULL; | |
1026 | ||
1027 | if (!dmar_find_matched_atsr_unit(info->dev)) | |
1028 | return NULL; | |
1029 | ||
1030 | info->iommu = iommu; | |
1031 | ||
1032 | return info; | |
1033 | } | |
1034 | ||
1035 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) | |
ba395927 | 1036 | { |
93a23a72 YZ |
1037 | if (!info) |
1038 | return; | |
1039 | ||
1040 | pci_enable_ats(info->dev, VTD_PAGE_SHIFT); | |
1041 | } | |
1042 | ||
1043 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) | |
1044 | { | |
1045 | if (!info->dev || !pci_ats_enabled(info->dev)) | |
1046 | return; | |
1047 | ||
1048 | pci_disable_ats(info->dev); | |
1049 | } | |
1050 | ||
1051 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, | |
1052 | u64 addr, unsigned mask) | |
1053 | { | |
1054 | u16 sid, qdep; | |
1055 | unsigned long flags; | |
1056 | struct device_domain_info *info; | |
1057 | ||
1058 | spin_lock_irqsave(&device_domain_lock, flags); | |
1059 | list_for_each_entry(info, &domain->devices, link) { | |
1060 | if (!info->dev || !pci_ats_enabled(info->dev)) | |
1061 | continue; | |
1062 | ||
1063 | sid = info->bus << 8 | info->devfn; | |
1064 | qdep = pci_ats_queue_depth(info->dev); | |
1065 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); | |
1066 | } | |
1067 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1068 | } | |
1069 | ||
1f0ef2aa | 1070 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
03d6a246 | 1071 | unsigned long pfn, unsigned int pages) |
ba395927 | 1072 | { |
9dd2fe89 | 1073 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
03d6a246 | 1074 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
ba395927 | 1075 | |
ba395927 KA |
1076 | BUG_ON(pages == 0); |
1077 | ||
ba395927 | 1078 | /* |
9dd2fe89 YZ |
1079 | * Fallback to domain selective flush if no PSI support or the size is |
1080 | * too big. | |
ba395927 KA |
1081 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
1082 | * aligned to the size | |
1083 | */ | |
9dd2fe89 YZ |
1084 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
1085 | iommu->flush.flush_iotlb(iommu, did, 0, 0, | |
1f0ef2aa | 1086 | DMA_TLB_DSI_FLUSH); |
9dd2fe89 YZ |
1087 | else |
1088 | iommu->flush.flush_iotlb(iommu, did, addr, mask, | |
1089 | DMA_TLB_PSI_FLUSH); | |
bf92df30 YZ |
1090 | |
1091 | /* | |
1092 | * In caching mode, domain ID 0 is reserved for non-present to present | |
1093 | * mapping flush. Device IOTLB doesn't need to be flushed in this case. | |
1094 | */ | |
1095 | if (!cap_caching_mode(iommu->cap) || did) | |
93a23a72 | 1096 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
ba395927 KA |
1097 | } |
1098 | ||
f8bab735 | 1099 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
1100 | { | |
1101 | u32 pmen; | |
1102 | unsigned long flags; | |
1103 | ||
1104 | spin_lock_irqsave(&iommu->register_lock, flags); | |
1105 | pmen = readl(iommu->reg + DMAR_PMEN_REG); | |
1106 | pmen &= ~DMA_PMEN_EPM; | |
1107 | writel(pmen, iommu->reg + DMAR_PMEN_REG); | |
1108 | ||
1109 | /* wait for the protected region status bit to clear */ | |
1110 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, | |
1111 | readl, !(pmen & DMA_PMEN_PRS), pmen); | |
1112 | ||
1113 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
1114 | } | |
1115 | ||
ba395927 KA |
1116 | static int iommu_enable_translation(struct intel_iommu *iommu) |
1117 | { | |
1118 | u32 sts; | |
1119 | unsigned long flags; | |
1120 | ||
1121 | spin_lock_irqsave(&iommu->register_lock, flags); | |
c416daa9 DW |
1122 | iommu->gcmd |= DMA_GCMD_TE; |
1123 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
ba395927 KA |
1124 | |
1125 | /* Make sure hardware complete it */ | |
1126 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1127 | readl, (sts & DMA_GSTS_TES), sts); |
ba395927 | 1128 | |
ba395927 KA |
1129 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
1130 | return 0; | |
1131 | } | |
1132 | ||
1133 | static int iommu_disable_translation(struct intel_iommu *iommu) | |
1134 | { | |
1135 | u32 sts; | |
1136 | unsigned long flag; | |
1137 | ||
1138 | spin_lock_irqsave(&iommu->register_lock, flag); | |
1139 | iommu->gcmd &= ~DMA_GCMD_TE; | |
1140 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
1141 | ||
1142 | /* Make sure hardware complete it */ | |
1143 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1144 | readl, (!(sts & DMA_GSTS_TES)), sts); |
ba395927 KA |
1145 | |
1146 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
1147 | return 0; | |
1148 | } | |
1149 | ||
3460a6d9 | 1150 | |
ba395927 KA |
1151 | static int iommu_init_domains(struct intel_iommu *iommu) |
1152 | { | |
1153 | unsigned long ndomains; | |
1154 | unsigned long nlongs; | |
1155 | ||
1156 | ndomains = cap_ndoms(iommu->cap); | |
1157 | pr_debug("Number of Domains supportd <%ld>\n", ndomains); | |
1158 | nlongs = BITS_TO_LONGS(ndomains); | |
1159 | ||
1160 | /* TBD: there might be 64K domains, | |
1161 | * consider other allocation for future chip | |
1162 | */ | |
1163 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); | |
1164 | if (!iommu->domain_ids) { | |
1165 | printk(KERN_ERR "Allocating domain id array failed\n"); | |
1166 | return -ENOMEM; | |
1167 | } | |
1168 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), | |
1169 | GFP_KERNEL); | |
1170 | if (!iommu->domains) { | |
1171 | printk(KERN_ERR "Allocating domain array failed\n"); | |
1172 | kfree(iommu->domain_ids); | |
1173 | return -ENOMEM; | |
1174 | } | |
1175 | ||
e61d98d8 SS |
1176 | spin_lock_init(&iommu->lock); |
1177 | ||
ba395927 KA |
1178 | /* |
1179 | * if Caching mode is set, then invalid translations are tagged | |
1180 | * with domainid 0. Hence we need to pre-allocate it. | |
1181 | */ | |
1182 | if (cap_caching_mode(iommu->cap)) | |
1183 | set_bit(0, iommu->domain_ids); | |
1184 | return 0; | |
1185 | } | |
ba395927 | 1186 | |
ba395927 KA |
1187 | |
1188 | static void domain_exit(struct dmar_domain *domain); | |
5e98c4b1 | 1189 | static void vm_domain_exit(struct dmar_domain *domain); |
e61d98d8 SS |
1190 | |
1191 | void free_dmar_iommu(struct intel_iommu *iommu) | |
ba395927 KA |
1192 | { |
1193 | struct dmar_domain *domain; | |
1194 | int i; | |
c7151a8d | 1195 | unsigned long flags; |
ba395927 | 1196 | |
ba395927 KA |
1197 | i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap)); |
1198 | for (; i < cap_ndoms(iommu->cap); ) { | |
1199 | domain = iommu->domains[i]; | |
1200 | clear_bit(i, iommu->domain_ids); | |
c7151a8d WH |
1201 | |
1202 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
5e98c4b1 WH |
1203 | if (--domain->iommu_count == 0) { |
1204 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) | |
1205 | vm_domain_exit(domain); | |
1206 | else | |
1207 | domain_exit(domain); | |
1208 | } | |
c7151a8d WH |
1209 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
1210 | ||
ba395927 KA |
1211 | i = find_next_bit(iommu->domain_ids, |
1212 | cap_ndoms(iommu->cap), i+1); | |
1213 | } | |
1214 | ||
1215 | if (iommu->gcmd & DMA_GCMD_TE) | |
1216 | iommu_disable_translation(iommu); | |
1217 | ||
1218 | if (iommu->irq) { | |
1219 | set_irq_data(iommu->irq, NULL); | |
1220 | /* This will mask the irq */ | |
1221 | free_irq(iommu->irq, iommu); | |
1222 | destroy_irq(iommu->irq); | |
1223 | } | |
1224 | ||
1225 | kfree(iommu->domains); | |
1226 | kfree(iommu->domain_ids); | |
1227 | ||
d9630fe9 WH |
1228 | g_iommus[iommu->seq_id] = NULL; |
1229 | ||
1230 | /* if all iommus are freed, free g_iommus */ | |
1231 | for (i = 0; i < g_num_of_iommus; i++) { | |
1232 | if (g_iommus[i]) | |
1233 | break; | |
1234 | } | |
1235 | ||
1236 | if (i == g_num_of_iommus) | |
1237 | kfree(g_iommus); | |
1238 | ||
ba395927 KA |
1239 | /* free context mapping */ |
1240 | free_context_table(iommu); | |
ba395927 KA |
1241 | } |
1242 | ||
2c2e2c38 | 1243 | static struct dmar_domain *alloc_domain(void) |
ba395927 | 1244 | { |
ba395927 | 1245 | struct dmar_domain *domain; |
ba395927 KA |
1246 | |
1247 | domain = alloc_domain_mem(); | |
1248 | if (!domain) | |
1249 | return NULL; | |
1250 | ||
2c2e2c38 FY |
1251 | memset(&domain->iommu_bmp, 0, sizeof(unsigned long)); |
1252 | domain->flags = 0; | |
1253 | ||
1254 | return domain; | |
1255 | } | |
1256 | ||
1257 | static int iommu_attach_domain(struct dmar_domain *domain, | |
1258 | struct intel_iommu *iommu) | |
1259 | { | |
1260 | int num; | |
1261 | unsigned long ndomains; | |
1262 | unsigned long flags; | |
1263 | ||
ba395927 KA |
1264 | ndomains = cap_ndoms(iommu->cap); |
1265 | ||
1266 | spin_lock_irqsave(&iommu->lock, flags); | |
2c2e2c38 | 1267 | |
ba395927 KA |
1268 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
1269 | if (num >= ndomains) { | |
1270 | spin_unlock_irqrestore(&iommu->lock, flags); | |
ba395927 | 1271 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
2c2e2c38 | 1272 | return -ENOMEM; |
ba395927 KA |
1273 | } |
1274 | ||
ba395927 | 1275 | domain->id = num; |
2c2e2c38 | 1276 | set_bit(num, iommu->domain_ids); |
8c11e798 | 1277 | set_bit(iommu->seq_id, &domain->iommu_bmp); |
ba395927 KA |
1278 | iommu->domains[num] = domain; |
1279 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1280 | ||
2c2e2c38 | 1281 | return 0; |
ba395927 KA |
1282 | } |
1283 | ||
2c2e2c38 FY |
1284 | static void iommu_detach_domain(struct dmar_domain *domain, |
1285 | struct intel_iommu *iommu) | |
ba395927 KA |
1286 | { |
1287 | unsigned long flags; | |
2c2e2c38 FY |
1288 | int num, ndomains; |
1289 | int found = 0; | |
ba395927 | 1290 | |
8c11e798 | 1291 | spin_lock_irqsave(&iommu->lock, flags); |
2c2e2c38 FY |
1292 | ndomains = cap_ndoms(iommu->cap); |
1293 | num = find_first_bit(iommu->domain_ids, ndomains); | |
1294 | for (; num < ndomains; ) { | |
1295 | if (iommu->domains[num] == domain) { | |
1296 | found = 1; | |
1297 | break; | |
1298 | } | |
1299 | num = find_next_bit(iommu->domain_ids, | |
1300 | cap_ndoms(iommu->cap), num+1); | |
1301 | } | |
1302 | ||
1303 | if (found) { | |
1304 | clear_bit(num, iommu->domain_ids); | |
1305 | clear_bit(iommu->seq_id, &domain->iommu_bmp); | |
1306 | iommu->domains[num] = NULL; | |
1307 | } | |
8c11e798 | 1308 | spin_unlock_irqrestore(&iommu->lock, flags); |
ba395927 KA |
1309 | } |
1310 | ||
1311 | static struct iova_domain reserved_iova_list; | |
8a443df4 MG |
1312 | static struct lock_class_key reserved_alloc_key; |
1313 | static struct lock_class_key reserved_rbtree_key; | |
ba395927 KA |
1314 | |
1315 | static void dmar_init_reserved_ranges(void) | |
1316 | { | |
1317 | struct pci_dev *pdev = NULL; | |
1318 | struct iova *iova; | |
1319 | int i; | |
ba395927 | 1320 | |
f661197e | 1321 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
ba395927 | 1322 | |
8a443df4 MG |
1323 | lockdep_set_class(&reserved_iova_list.iova_alloc_lock, |
1324 | &reserved_alloc_key); | |
1325 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, | |
1326 | &reserved_rbtree_key); | |
1327 | ||
ba395927 KA |
1328 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
1329 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), | |
1330 | IOVA_PFN(IOAPIC_RANGE_END)); | |
1331 | if (!iova) | |
1332 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); | |
1333 | ||
1334 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ | |
1335 | for_each_pci_dev(pdev) { | |
1336 | struct resource *r; | |
1337 | ||
1338 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1339 | r = &pdev->resource[i]; | |
1340 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) | |
1341 | continue; | |
1a4a4551 DW |
1342 | iova = reserve_iova(&reserved_iova_list, |
1343 | IOVA_PFN(r->start), | |
1344 | IOVA_PFN(r->end)); | |
ba395927 KA |
1345 | if (!iova) |
1346 | printk(KERN_ERR "Reserve iova failed\n"); | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | } | |
1351 | ||
1352 | static void domain_reserve_special_ranges(struct dmar_domain *domain) | |
1353 | { | |
1354 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); | |
1355 | } | |
1356 | ||
1357 | static inline int guestwidth_to_adjustwidth(int gaw) | |
1358 | { | |
1359 | int agaw; | |
1360 | int r = (gaw - 12) % 9; | |
1361 | ||
1362 | if (r == 0) | |
1363 | agaw = gaw; | |
1364 | else | |
1365 | agaw = gaw + 9 - r; | |
1366 | if (agaw > 64) | |
1367 | agaw = 64; | |
1368 | return agaw; | |
1369 | } | |
1370 | ||
1371 | static int domain_init(struct dmar_domain *domain, int guest_width) | |
1372 | { | |
1373 | struct intel_iommu *iommu; | |
1374 | int adjust_width, agaw; | |
1375 | unsigned long sagaw; | |
1376 | ||
f661197e | 1377 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
c7151a8d | 1378 | spin_lock_init(&domain->iommu_lock); |
ba395927 KA |
1379 | |
1380 | domain_reserve_special_ranges(domain); | |
1381 | ||
1382 | /* calculate AGAW */ | |
8c11e798 | 1383 | iommu = domain_get_iommu(domain); |
ba395927 KA |
1384 | if (guest_width > cap_mgaw(iommu->cap)) |
1385 | guest_width = cap_mgaw(iommu->cap); | |
1386 | domain->gaw = guest_width; | |
1387 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
1388 | agaw = width_to_agaw(adjust_width); | |
1389 | sagaw = cap_sagaw(iommu->cap); | |
1390 | if (!test_bit(agaw, &sagaw)) { | |
1391 | /* hardware doesn't support it, choose a bigger one */ | |
1392 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); | |
1393 | agaw = find_next_bit(&sagaw, 5, agaw); | |
1394 | if (agaw >= 5) | |
1395 | return -ENODEV; | |
1396 | } | |
1397 | domain->agaw = agaw; | |
1398 | INIT_LIST_HEAD(&domain->devices); | |
1399 | ||
8e604097 WH |
1400 | if (ecap_coherent(iommu->ecap)) |
1401 | domain->iommu_coherency = 1; | |
1402 | else | |
1403 | domain->iommu_coherency = 0; | |
1404 | ||
58c610bd SY |
1405 | if (ecap_sc_support(iommu->ecap)) |
1406 | domain->iommu_snooping = 1; | |
1407 | else | |
1408 | domain->iommu_snooping = 0; | |
1409 | ||
c7151a8d WH |
1410 | domain->iommu_count = 1; |
1411 | ||
ba395927 KA |
1412 | /* always allocate the top pgd */ |
1413 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(); | |
1414 | if (!domain->pgd) | |
1415 | return -ENOMEM; | |
5b6985ce | 1416 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
ba395927 KA |
1417 | return 0; |
1418 | } | |
1419 | ||
1420 | static void domain_exit(struct dmar_domain *domain) | |
1421 | { | |
2c2e2c38 FY |
1422 | struct dmar_drhd_unit *drhd; |
1423 | struct intel_iommu *iommu; | |
ba395927 KA |
1424 | |
1425 | /* Domain 0 is reserved, so dont process it */ | |
1426 | if (!domain) | |
1427 | return; | |
1428 | ||
1429 | domain_remove_dev_info(domain); | |
1430 | /* destroy iovas */ | |
1431 | put_iova_domain(&domain->iovad); | |
ba395927 KA |
1432 | |
1433 | /* clear ptes */ | |
595badf5 | 1434 | dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 KA |
1435 | |
1436 | /* free page tables */ | |
d794dc9b | 1437 | dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 | 1438 | |
2c2e2c38 FY |
1439 | for_each_active_iommu(iommu, drhd) |
1440 | if (test_bit(iommu->seq_id, &domain->iommu_bmp)) | |
1441 | iommu_detach_domain(domain, iommu); | |
1442 | ||
ba395927 KA |
1443 | free_domain_mem(domain); |
1444 | } | |
1445 | ||
4ed0d3e6 FY |
1446 | static int domain_context_mapping_one(struct dmar_domain *domain, int segment, |
1447 | u8 bus, u8 devfn, int translation) | |
ba395927 KA |
1448 | { |
1449 | struct context_entry *context; | |
ba395927 | 1450 | unsigned long flags; |
5331fe6f | 1451 | struct intel_iommu *iommu; |
ea6606b0 WH |
1452 | struct dma_pte *pgd; |
1453 | unsigned long num; | |
1454 | unsigned long ndomains; | |
1455 | int id; | |
1456 | int agaw; | |
93a23a72 | 1457 | struct device_domain_info *info = NULL; |
ba395927 KA |
1458 | |
1459 | pr_debug("Set context mapping for %02x:%02x.%d\n", | |
1460 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
4ed0d3e6 | 1461 | |
ba395927 | 1462 | BUG_ON(!domain->pgd); |
4ed0d3e6 FY |
1463 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
1464 | translation != CONTEXT_TT_MULTI_LEVEL); | |
5331fe6f | 1465 | |
276dbf99 | 1466 | iommu = device_to_iommu(segment, bus, devfn); |
5331fe6f WH |
1467 | if (!iommu) |
1468 | return -ENODEV; | |
1469 | ||
ba395927 KA |
1470 | context = device_to_context_entry(iommu, bus, devfn); |
1471 | if (!context) | |
1472 | return -ENOMEM; | |
1473 | spin_lock_irqsave(&iommu->lock, flags); | |
c07e7d21 | 1474 | if (context_present(context)) { |
ba395927 KA |
1475 | spin_unlock_irqrestore(&iommu->lock, flags); |
1476 | return 0; | |
1477 | } | |
1478 | ||
ea6606b0 WH |
1479 | id = domain->id; |
1480 | pgd = domain->pgd; | |
1481 | ||
2c2e2c38 FY |
1482 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
1483 | domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) { | |
ea6606b0 WH |
1484 | int found = 0; |
1485 | ||
1486 | /* find an available domain id for this device in iommu */ | |
1487 | ndomains = cap_ndoms(iommu->cap); | |
1488 | num = find_first_bit(iommu->domain_ids, ndomains); | |
1489 | for (; num < ndomains; ) { | |
1490 | if (iommu->domains[num] == domain) { | |
1491 | id = num; | |
1492 | found = 1; | |
1493 | break; | |
1494 | } | |
1495 | num = find_next_bit(iommu->domain_ids, | |
1496 | cap_ndoms(iommu->cap), num+1); | |
1497 | } | |
1498 | ||
1499 | if (found == 0) { | |
1500 | num = find_first_zero_bit(iommu->domain_ids, ndomains); | |
1501 | if (num >= ndomains) { | |
1502 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1503 | printk(KERN_ERR "IOMMU: no free domain ids\n"); | |
1504 | return -EFAULT; | |
1505 | } | |
1506 | ||
1507 | set_bit(num, iommu->domain_ids); | |
2c2e2c38 | 1508 | set_bit(iommu->seq_id, &domain->iommu_bmp); |
ea6606b0 WH |
1509 | iommu->domains[num] = domain; |
1510 | id = num; | |
1511 | } | |
1512 | ||
1513 | /* Skip top levels of page tables for | |
1514 | * iommu which has less agaw than default. | |
1515 | */ | |
1516 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { | |
1517 | pgd = phys_to_virt(dma_pte_addr(pgd)); | |
1518 | if (!dma_pte_present(pgd)) { | |
1519 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1520 | return -ENOMEM; | |
1521 | } | |
1522 | } | |
1523 | } | |
1524 | ||
1525 | context_set_domain_id(context, id); | |
4ed0d3e6 | 1526 | |
93a23a72 YZ |
1527 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
1528 | info = iommu_support_dev_iotlb(domain, segment, bus, devfn); | |
1529 | translation = info ? CONTEXT_TT_DEV_IOTLB : | |
1530 | CONTEXT_TT_MULTI_LEVEL; | |
1531 | } | |
4ed0d3e6 FY |
1532 | /* |
1533 | * In pass through mode, AW must be programmed to indicate the largest | |
1534 | * AGAW value supported by hardware. And ASR is ignored by hardware. | |
1535 | */ | |
93a23a72 | 1536 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
4ed0d3e6 | 1537 | context_set_address_width(context, iommu->msagaw); |
93a23a72 YZ |
1538 | else { |
1539 | context_set_address_root(context, virt_to_phys(pgd)); | |
1540 | context_set_address_width(context, iommu->agaw); | |
1541 | } | |
4ed0d3e6 FY |
1542 | |
1543 | context_set_translation_type(context, translation); | |
c07e7d21 MM |
1544 | context_set_fault_enable(context); |
1545 | context_set_present(context); | |
5331fe6f | 1546 | domain_flush_cache(domain, context, sizeof(*context)); |
ba395927 | 1547 | |
4c25a2c1 DW |
1548 | /* |
1549 | * It's a non-present to present mapping. If hardware doesn't cache | |
1550 | * non-present entry we only need to flush the write-buffer. If the | |
1551 | * _does_ cache non-present entries, then it does so in the special | |
1552 | * domain #0, which we have to flush: | |
1553 | */ | |
1554 | if (cap_caching_mode(iommu->cap)) { | |
1555 | iommu->flush.flush_context(iommu, 0, | |
1556 | (((u16)bus) << 8) | devfn, | |
1557 | DMA_CCMD_MASK_NOBIT, | |
1558 | DMA_CCMD_DEVICE_INVL); | |
1f0ef2aa | 1559 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH); |
4c25a2c1 | 1560 | } else { |
ba395927 | 1561 | iommu_flush_write_buffer(iommu); |
4c25a2c1 | 1562 | } |
93a23a72 | 1563 | iommu_enable_dev_iotlb(info); |
ba395927 | 1564 | spin_unlock_irqrestore(&iommu->lock, flags); |
c7151a8d WH |
1565 | |
1566 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
1567 | if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) { | |
1568 | domain->iommu_count++; | |
58c610bd | 1569 | domain_update_iommu_cap(domain); |
c7151a8d WH |
1570 | } |
1571 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
ba395927 KA |
1572 | return 0; |
1573 | } | |
1574 | ||
1575 | static int | |
4ed0d3e6 FY |
1576 | domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev, |
1577 | int translation) | |
ba395927 KA |
1578 | { |
1579 | int ret; | |
1580 | struct pci_dev *tmp, *parent; | |
1581 | ||
276dbf99 | 1582 | ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus), |
4ed0d3e6 FY |
1583 | pdev->bus->number, pdev->devfn, |
1584 | translation); | |
ba395927 KA |
1585 | if (ret) |
1586 | return ret; | |
1587 | ||
1588 | /* dependent device mapping */ | |
1589 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
1590 | if (!tmp) | |
1591 | return 0; | |
1592 | /* Secondary interface's bus number and devfn 0 */ | |
1593 | parent = pdev->bus->self; | |
1594 | while (parent != tmp) { | |
276dbf99 DW |
1595 | ret = domain_context_mapping_one(domain, |
1596 | pci_domain_nr(parent->bus), | |
1597 | parent->bus->number, | |
4ed0d3e6 | 1598 | parent->devfn, translation); |
ba395927 KA |
1599 | if (ret) |
1600 | return ret; | |
1601 | parent = parent->bus->self; | |
1602 | } | |
1603 | if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */ | |
1604 | return domain_context_mapping_one(domain, | |
276dbf99 | 1605 | pci_domain_nr(tmp->subordinate), |
4ed0d3e6 FY |
1606 | tmp->subordinate->number, 0, |
1607 | translation); | |
ba395927 KA |
1608 | else /* this is a legacy PCI bridge */ |
1609 | return domain_context_mapping_one(domain, | |
276dbf99 DW |
1610 | pci_domain_nr(tmp->bus), |
1611 | tmp->bus->number, | |
4ed0d3e6 FY |
1612 | tmp->devfn, |
1613 | translation); | |
ba395927 KA |
1614 | } |
1615 | ||
5331fe6f | 1616 | static int domain_context_mapped(struct pci_dev *pdev) |
ba395927 KA |
1617 | { |
1618 | int ret; | |
1619 | struct pci_dev *tmp, *parent; | |
5331fe6f WH |
1620 | struct intel_iommu *iommu; |
1621 | ||
276dbf99 DW |
1622 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
1623 | pdev->devfn); | |
5331fe6f WH |
1624 | if (!iommu) |
1625 | return -ENODEV; | |
ba395927 | 1626 | |
276dbf99 | 1627 | ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn); |
ba395927 KA |
1628 | if (!ret) |
1629 | return ret; | |
1630 | /* dependent device mapping */ | |
1631 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
1632 | if (!tmp) | |
1633 | return ret; | |
1634 | /* Secondary interface's bus number and devfn 0 */ | |
1635 | parent = pdev->bus->self; | |
1636 | while (parent != tmp) { | |
8c11e798 | 1637 | ret = device_context_mapped(iommu, parent->bus->number, |
276dbf99 | 1638 | parent->devfn); |
ba395927 KA |
1639 | if (!ret) |
1640 | return ret; | |
1641 | parent = parent->bus->self; | |
1642 | } | |
1643 | if (tmp->is_pcie) | |
276dbf99 DW |
1644 | return device_context_mapped(iommu, tmp->subordinate->number, |
1645 | 0); | |
ba395927 | 1646 | else |
276dbf99 DW |
1647 | return device_context_mapped(iommu, tmp->bus->number, |
1648 | tmp->devfn); | |
ba395927 KA |
1649 | } |
1650 | ||
9051aa02 DW |
1651 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1652 | struct scatterlist *sg, unsigned long phys_pfn, | |
1653 | unsigned long nr_pages, int prot) | |
e1605495 DW |
1654 | { |
1655 | struct dma_pte *first_pte = NULL, *pte = NULL; | |
9051aa02 | 1656 | phys_addr_t uninitialized_var(pteval); |
e1605495 | 1657 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
9051aa02 | 1658 | unsigned long sg_res; |
e1605495 DW |
1659 | |
1660 | BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width); | |
1661 | ||
1662 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | |
1663 | return -EINVAL; | |
1664 | ||
1665 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; | |
1666 | ||
9051aa02 DW |
1667 | if (sg) |
1668 | sg_res = 0; | |
1669 | else { | |
1670 | sg_res = nr_pages + 1; | |
1671 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; | |
1672 | } | |
1673 | ||
e1605495 | 1674 | while (nr_pages--) { |
c85994e4 DW |
1675 | uint64_t tmp; |
1676 | ||
e1605495 DW |
1677 | if (!sg_res) { |
1678 | sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT; | |
1679 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; | |
1680 | sg->dma_length = sg->length; | |
1681 | pteval = page_to_phys(sg_page(sg)) | prot; | |
1682 | } | |
1683 | if (!pte) { | |
1684 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn); | |
1685 | if (!pte) | |
1686 | return -ENOMEM; | |
1687 | } | |
1688 | /* We don't need lock here, nobody else | |
1689 | * touches the iova range | |
1690 | */ | |
7766a3fb | 1691 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
c85994e4 | 1692 | if (tmp) { |
1bf20f0d | 1693 | static int dumps = 5; |
c85994e4 DW |
1694 | printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
1695 | iov_pfn, tmp, (unsigned long long)pteval); | |
1bf20f0d DW |
1696 | if (dumps) { |
1697 | dumps--; | |
1698 | debug_dma_dump_mappings(NULL); | |
1699 | } | |
1700 | WARN_ON(1); | |
1701 | } | |
e1605495 | 1702 | pte++; |
75e6bf96 | 1703 | if (!nr_pages || first_pte_in_page(pte)) { |
e1605495 DW |
1704 | domain_flush_cache(domain, first_pte, |
1705 | (void *)pte - (void *)first_pte); | |
1706 | pte = NULL; | |
1707 | } | |
1708 | iov_pfn++; | |
1709 | pteval += VTD_PAGE_SIZE; | |
1710 | sg_res--; | |
1711 | if (!sg_res) | |
1712 | sg = sg_next(sg); | |
1713 | } | |
1714 | return 0; | |
1715 | } | |
1716 | ||
9051aa02 DW |
1717 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1718 | struct scatterlist *sg, unsigned long nr_pages, | |
1719 | int prot) | |
ba395927 | 1720 | { |
9051aa02 DW |
1721 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
1722 | } | |
6f6a00e4 | 1723 | |
9051aa02 DW |
1724 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1725 | unsigned long phys_pfn, unsigned long nr_pages, | |
1726 | int prot) | |
1727 | { | |
1728 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); | |
ba395927 KA |
1729 | } |
1730 | ||
c7151a8d | 1731 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
ba395927 | 1732 | { |
c7151a8d WH |
1733 | if (!iommu) |
1734 | return; | |
8c11e798 WH |
1735 | |
1736 | clear_context_table(iommu, bus, devfn); | |
1737 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
4c25a2c1 | 1738 | DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 1739 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
ba395927 KA |
1740 | } |
1741 | ||
1742 | static void domain_remove_dev_info(struct dmar_domain *domain) | |
1743 | { | |
1744 | struct device_domain_info *info; | |
1745 | unsigned long flags; | |
c7151a8d | 1746 | struct intel_iommu *iommu; |
ba395927 KA |
1747 | |
1748 | spin_lock_irqsave(&device_domain_lock, flags); | |
1749 | while (!list_empty(&domain->devices)) { | |
1750 | info = list_entry(domain->devices.next, | |
1751 | struct device_domain_info, link); | |
1752 | list_del(&info->link); | |
1753 | list_del(&info->global); | |
1754 | if (info->dev) | |
358dd8ac | 1755 | info->dev->dev.archdata.iommu = NULL; |
ba395927 KA |
1756 | spin_unlock_irqrestore(&device_domain_lock, flags); |
1757 | ||
93a23a72 | 1758 | iommu_disable_dev_iotlb(info); |
276dbf99 | 1759 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
c7151a8d | 1760 | iommu_detach_dev(iommu, info->bus, info->devfn); |
ba395927 KA |
1761 | free_devinfo_mem(info); |
1762 | ||
1763 | spin_lock_irqsave(&device_domain_lock, flags); | |
1764 | } | |
1765 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1766 | } | |
1767 | ||
1768 | /* | |
1769 | * find_domain | |
358dd8ac | 1770 | * Note: we use struct pci_dev->dev.archdata.iommu stores the info |
ba395927 | 1771 | */ |
38717946 | 1772 | static struct dmar_domain * |
ba395927 KA |
1773 | find_domain(struct pci_dev *pdev) |
1774 | { | |
1775 | struct device_domain_info *info; | |
1776 | ||
1777 | /* No lock here, assumes no domain exit in normal case */ | |
358dd8ac | 1778 | info = pdev->dev.archdata.iommu; |
ba395927 KA |
1779 | if (info) |
1780 | return info->domain; | |
1781 | return NULL; | |
1782 | } | |
1783 | ||
ba395927 KA |
1784 | /* domain is initialized */ |
1785 | static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw) | |
1786 | { | |
1787 | struct dmar_domain *domain, *found = NULL; | |
1788 | struct intel_iommu *iommu; | |
1789 | struct dmar_drhd_unit *drhd; | |
1790 | struct device_domain_info *info, *tmp; | |
1791 | struct pci_dev *dev_tmp; | |
1792 | unsigned long flags; | |
1793 | int bus = 0, devfn = 0; | |
276dbf99 | 1794 | int segment; |
2c2e2c38 | 1795 | int ret; |
ba395927 KA |
1796 | |
1797 | domain = find_domain(pdev); | |
1798 | if (domain) | |
1799 | return domain; | |
1800 | ||
276dbf99 DW |
1801 | segment = pci_domain_nr(pdev->bus); |
1802 | ||
ba395927 KA |
1803 | dev_tmp = pci_find_upstream_pcie_bridge(pdev); |
1804 | if (dev_tmp) { | |
1805 | if (dev_tmp->is_pcie) { | |
1806 | bus = dev_tmp->subordinate->number; | |
1807 | devfn = 0; | |
1808 | } else { | |
1809 | bus = dev_tmp->bus->number; | |
1810 | devfn = dev_tmp->devfn; | |
1811 | } | |
1812 | spin_lock_irqsave(&device_domain_lock, flags); | |
1813 | list_for_each_entry(info, &device_domain_list, global) { | |
276dbf99 DW |
1814 | if (info->segment == segment && |
1815 | info->bus == bus && info->devfn == devfn) { | |
ba395927 KA |
1816 | found = info->domain; |
1817 | break; | |
1818 | } | |
1819 | } | |
1820 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1821 | /* pcie-pci bridge already has a domain, uses it */ | |
1822 | if (found) { | |
1823 | domain = found; | |
1824 | goto found_domain; | |
1825 | } | |
1826 | } | |
1827 | ||
2c2e2c38 FY |
1828 | domain = alloc_domain(); |
1829 | if (!domain) | |
1830 | goto error; | |
1831 | ||
ba395927 KA |
1832 | /* Allocate new domain for the device */ |
1833 | drhd = dmar_find_matched_drhd_unit(pdev); | |
1834 | if (!drhd) { | |
1835 | printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n", | |
1836 | pci_name(pdev)); | |
1837 | return NULL; | |
1838 | } | |
1839 | iommu = drhd->iommu; | |
1840 | ||
2c2e2c38 FY |
1841 | ret = iommu_attach_domain(domain, iommu); |
1842 | if (ret) { | |
1843 | domain_exit(domain); | |
ba395927 | 1844 | goto error; |
2c2e2c38 | 1845 | } |
ba395927 KA |
1846 | |
1847 | if (domain_init(domain, gaw)) { | |
1848 | domain_exit(domain); | |
1849 | goto error; | |
1850 | } | |
1851 | ||
1852 | /* register pcie-to-pci device */ | |
1853 | if (dev_tmp) { | |
1854 | info = alloc_devinfo_mem(); | |
1855 | if (!info) { | |
1856 | domain_exit(domain); | |
1857 | goto error; | |
1858 | } | |
276dbf99 | 1859 | info->segment = segment; |
ba395927 KA |
1860 | info->bus = bus; |
1861 | info->devfn = devfn; | |
1862 | info->dev = NULL; | |
1863 | info->domain = domain; | |
1864 | /* This domain is shared by devices under p2p bridge */ | |
3b5410e7 | 1865 | domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES; |
ba395927 KA |
1866 | |
1867 | /* pcie-to-pci bridge already has a domain, uses it */ | |
1868 | found = NULL; | |
1869 | spin_lock_irqsave(&device_domain_lock, flags); | |
1870 | list_for_each_entry(tmp, &device_domain_list, global) { | |
276dbf99 DW |
1871 | if (tmp->segment == segment && |
1872 | tmp->bus == bus && tmp->devfn == devfn) { | |
ba395927 KA |
1873 | found = tmp->domain; |
1874 | break; | |
1875 | } | |
1876 | } | |
1877 | if (found) { | |
1878 | free_devinfo_mem(info); | |
1879 | domain_exit(domain); | |
1880 | domain = found; | |
1881 | } else { | |
1882 | list_add(&info->link, &domain->devices); | |
1883 | list_add(&info->global, &device_domain_list); | |
1884 | } | |
1885 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1886 | } | |
1887 | ||
1888 | found_domain: | |
1889 | info = alloc_devinfo_mem(); | |
1890 | if (!info) | |
1891 | goto error; | |
276dbf99 | 1892 | info->segment = segment; |
ba395927 KA |
1893 | info->bus = pdev->bus->number; |
1894 | info->devfn = pdev->devfn; | |
1895 | info->dev = pdev; | |
1896 | info->domain = domain; | |
1897 | spin_lock_irqsave(&device_domain_lock, flags); | |
1898 | /* somebody is fast */ | |
1899 | found = find_domain(pdev); | |
1900 | if (found != NULL) { | |
1901 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1902 | if (found != domain) { | |
1903 | domain_exit(domain); | |
1904 | domain = found; | |
1905 | } | |
1906 | free_devinfo_mem(info); | |
1907 | return domain; | |
1908 | } | |
1909 | list_add(&info->link, &domain->devices); | |
1910 | list_add(&info->global, &device_domain_list); | |
358dd8ac | 1911 | pdev->dev.archdata.iommu = info; |
ba395927 KA |
1912 | spin_unlock_irqrestore(&device_domain_lock, flags); |
1913 | return domain; | |
1914 | error: | |
1915 | /* recheck it here, maybe others set it */ | |
1916 | return find_domain(pdev); | |
1917 | } | |
1918 | ||
2c2e2c38 FY |
1919 | static int iommu_identity_mapping; |
1920 | ||
b213203e DW |
1921 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
1922 | unsigned long long start, | |
1923 | unsigned long long end) | |
ba395927 | 1924 | { |
c5395d5c DW |
1925 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
1926 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; | |
1927 | ||
1928 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), | |
1929 | dma_to_mm_pfn(last_vpfn))) { | |
ba395927 | 1930 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); |
b213203e | 1931 | return -ENOMEM; |
ba395927 KA |
1932 | } |
1933 | ||
c5395d5c DW |
1934 | pr_debug("Mapping reserved region %llx-%llx for domain %d\n", |
1935 | start, end, domain->id); | |
ba395927 KA |
1936 | /* |
1937 | * RMRR range might have overlap with physical memory range, | |
1938 | * clear it first | |
1939 | */ | |
c5395d5c | 1940 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
ba395927 | 1941 | |
c5395d5c DW |
1942 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
1943 | last_vpfn - first_vpfn + 1, | |
61df7443 | 1944 | DMA_PTE_READ|DMA_PTE_WRITE); |
b213203e DW |
1945 | } |
1946 | ||
1947 | static int iommu_prepare_identity_map(struct pci_dev *pdev, | |
1948 | unsigned long long start, | |
1949 | unsigned long long end) | |
1950 | { | |
1951 | struct dmar_domain *domain; | |
1952 | int ret; | |
1953 | ||
1954 | printk(KERN_INFO | |
1955 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", | |
1956 | pci_name(pdev), start, end); | |
1957 | ||
c7ab48d2 | 1958 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
b213203e DW |
1959 | if (!domain) |
1960 | return -ENOMEM; | |
1961 | ||
1962 | ret = iommu_domain_identity_map(domain, start, end); | |
ba395927 KA |
1963 | if (ret) |
1964 | goto error; | |
1965 | ||
1966 | /* context entry init */ | |
4ed0d3e6 | 1967 | ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
b213203e DW |
1968 | if (ret) |
1969 | goto error; | |
1970 | ||
1971 | return 0; | |
1972 | ||
1973 | error: | |
ba395927 KA |
1974 | domain_exit(domain); |
1975 | return ret; | |
ba395927 KA |
1976 | } |
1977 | ||
1978 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, | |
1979 | struct pci_dev *pdev) | |
1980 | { | |
358dd8ac | 1981 | if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
ba395927 KA |
1982 | return 0; |
1983 | return iommu_prepare_identity_map(pdev, rmrr->base_address, | |
1984 | rmrr->end_address + 1); | |
1985 | } | |
1986 | ||
49a0429e KA |
1987 | #ifdef CONFIG_DMAR_FLOPPY_WA |
1988 | static inline void iommu_prepare_isa(void) | |
1989 | { | |
1990 | struct pci_dev *pdev; | |
1991 | int ret; | |
1992 | ||
1993 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
1994 | if (!pdev) | |
1995 | return; | |
1996 | ||
c7ab48d2 | 1997 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
49a0429e KA |
1998 | ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024); |
1999 | ||
2000 | if (ret) | |
c7ab48d2 DW |
2001 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
2002 | "floppy might not work\n"); | |
49a0429e KA |
2003 | |
2004 | } | |
2005 | #else | |
2006 | static inline void iommu_prepare_isa(void) | |
2007 | { | |
2008 | return; | |
2009 | } | |
2010 | #endif /* !CONFIG_DMAR_FLPY_WA */ | |
2011 | ||
4ed0d3e6 FY |
2012 | /* Initialize each context entry as pass through.*/ |
2013 | static int __init init_context_pass_through(void) | |
2014 | { | |
2015 | struct pci_dev *pdev = NULL; | |
2016 | struct dmar_domain *domain; | |
2017 | int ret; | |
2018 | ||
2019 | for_each_pci_dev(pdev) { | |
2020 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
2021 | ret = domain_context_mapping(domain, pdev, | |
2022 | CONTEXT_TT_PASS_THROUGH); | |
2023 | if (ret) | |
2024 | return ret; | |
2025 | } | |
2026 | return 0; | |
2027 | } | |
2028 | ||
2c2e2c38 | 2029 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
c7ab48d2 DW |
2030 | |
2031 | static int __init si_domain_work_fn(unsigned long start_pfn, | |
2032 | unsigned long end_pfn, void *datax) | |
2033 | { | |
2034 | int *ret = datax; | |
2035 | ||
2036 | *ret = iommu_domain_identity_map(si_domain, | |
2037 | (uint64_t)start_pfn << PAGE_SHIFT, | |
2038 | (uint64_t)end_pfn << PAGE_SHIFT); | |
2039 | return *ret; | |
2040 | ||
2041 | } | |
2042 | ||
2c2e2c38 FY |
2043 | static int si_domain_init(void) |
2044 | { | |
2045 | struct dmar_drhd_unit *drhd; | |
2046 | struct intel_iommu *iommu; | |
c7ab48d2 | 2047 | int nid, ret = 0; |
2c2e2c38 FY |
2048 | |
2049 | si_domain = alloc_domain(); | |
2050 | if (!si_domain) | |
2051 | return -EFAULT; | |
2052 | ||
c7ab48d2 | 2053 | pr_debug("Identity mapping domain is domain %d\n", si_domain->id); |
2c2e2c38 FY |
2054 | |
2055 | for_each_active_iommu(iommu, drhd) { | |
2056 | ret = iommu_attach_domain(si_domain, iommu); | |
2057 | if (ret) { | |
2058 | domain_exit(si_domain); | |
2059 | return -EFAULT; | |
2060 | } | |
2061 | } | |
2062 | ||
2063 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { | |
2064 | domain_exit(si_domain); | |
2065 | return -EFAULT; | |
2066 | } | |
2067 | ||
2068 | si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY; | |
2069 | ||
c7ab48d2 DW |
2070 | for_each_online_node(nid) { |
2071 | work_with_active_regions(nid, si_domain_work_fn, &ret); | |
2072 | if (ret) | |
2073 | return ret; | |
2074 | } | |
2075 | ||
2c2e2c38 FY |
2076 | return 0; |
2077 | } | |
2078 | ||
2079 | static void domain_remove_one_dev_info(struct dmar_domain *domain, | |
2080 | struct pci_dev *pdev); | |
2081 | static int identity_mapping(struct pci_dev *pdev) | |
2082 | { | |
2083 | struct device_domain_info *info; | |
2084 | ||
2085 | if (likely(!iommu_identity_mapping)) | |
2086 | return 0; | |
2087 | ||
2088 | ||
2089 | list_for_each_entry(info, &si_domain->devices, link) | |
2090 | if (info->dev == pdev) | |
2091 | return 1; | |
2092 | return 0; | |
2093 | } | |
2094 | ||
2095 | static int domain_add_dev_info(struct dmar_domain *domain, | |
2096 | struct pci_dev *pdev) | |
2097 | { | |
2098 | struct device_domain_info *info; | |
2099 | unsigned long flags; | |
2100 | ||
2101 | info = alloc_devinfo_mem(); | |
2102 | if (!info) | |
2103 | return -ENOMEM; | |
2104 | ||
2105 | info->segment = pci_domain_nr(pdev->bus); | |
2106 | info->bus = pdev->bus->number; | |
2107 | info->devfn = pdev->devfn; | |
2108 | info->dev = pdev; | |
2109 | info->domain = domain; | |
2110 | ||
2111 | spin_lock_irqsave(&device_domain_lock, flags); | |
2112 | list_add(&info->link, &domain->devices); | |
2113 | list_add(&info->global, &device_domain_list); | |
2114 | pdev->dev.archdata.iommu = info; | |
2115 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2116 | ||
2117 | return 0; | |
2118 | } | |
2119 | ||
2120 | static int iommu_prepare_static_identity_mapping(void) | |
2121 | { | |
2c2e2c38 FY |
2122 | struct pci_dev *pdev = NULL; |
2123 | int ret; | |
2124 | ||
2125 | ret = si_domain_init(); | |
2126 | if (ret) | |
2127 | return -EFAULT; | |
2128 | ||
2c2e2c38 | 2129 | for_each_pci_dev(pdev) { |
62edf5dc DW |
2130 | if (iommu_identity_mapping == 1 || IS_GFX_DEVICE(pdev)) { |
2131 | printk(KERN_INFO "IOMMU: identity mapping for device %s\n", | |
2132 | pci_name(pdev)); | |
2133 | ||
2134 | ret = domain_context_mapping(si_domain, pdev, | |
2135 | CONTEXT_TT_MULTI_LEVEL); | |
2136 | if (ret) | |
2137 | return ret; | |
2138 | ret = domain_add_dev_info(si_domain, pdev); | |
2139 | if (ret) | |
2140 | return ret; | |
2141 | } | |
2c2e2c38 FY |
2142 | } |
2143 | ||
2144 | return 0; | |
2145 | } | |
2146 | ||
2147 | int __init init_dmars(void) | |
ba395927 KA |
2148 | { |
2149 | struct dmar_drhd_unit *drhd; | |
2150 | struct dmar_rmrr_unit *rmrr; | |
2151 | struct pci_dev *pdev; | |
2152 | struct intel_iommu *iommu; | |
9d783ba0 | 2153 | int i, ret; |
4ed0d3e6 | 2154 | int pass_through = 1; |
ba395927 | 2155 | |
2c2e2c38 FY |
2156 | /* |
2157 | * In case pass through can not be enabled, iommu tries to use identity | |
2158 | * mapping. | |
2159 | */ | |
2160 | if (iommu_pass_through) | |
2161 | iommu_identity_mapping = 1; | |
2162 | ||
ba395927 KA |
2163 | /* |
2164 | * for each drhd | |
2165 | * allocate root | |
2166 | * initialize and program root entry to not present | |
2167 | * endfor | |
2168 | */ | |
2169 | for_each_drhd_unit(drhd) { | |
5e0d2a6f | 2170 | g_num_of_iommus++; |
2171 | /* | |
2172 | * lock not needed as this is only incremented in the single | |
2173 | * threaded kernel __init code path all other access are read | |
2174 | * only | |
2175 | */ | |
2176 | } | |
2177 | ||
d9630fe9 WH |
2178 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
2179 | GFP_KERNEL); | |
2180 | if (!g_iommus) { | |
2181 | printk(KERN_ERR "Allocating global iommu array failed\n"); | |
2182 | ret = -ENOMEM; | |
2183 | goto error; | |
2184 | } | |
2185 | ||
80b20dd8 | 2186 | deferred_flush = kzalloc(g_num_of_iommus * |
2187 | sizeof(struct deferred_flush_tables), GFP_KERNEL); | |
2188 | if (!deferred_flush) { | |
d9630fe9 | 2189 | kfree(g_iommus); |
5e0d2a6f | 2190 | ret = -ENOMEM; |
2191 | goto error; | |
2192 | } | |
2193 | ||
5e0d2a6f | 2194 | for_each_drhd_unit(drhd) { |
2195 | if (drhd->ignored) | |
2196 | continue; | |
1886e8a9 SS |
2197 | |
2198 | iommu = drhd->iommu; | |
d9630fe9 | 2199 | g_iommus[iommu->seq_id] = iommu; |
ba395927 | 2200 | |
e61d98d8 SS |
2201 | ret = iommu_init_domains(iommu); |
2202 | if (ret) | |
2203 | goto error; | |
2204 | ||
ba395927 KA |
2205 | /* |
2206 | * TBD: | |
2207 | * we could share the same root & context tables | |
2208 | * amoung all IOMMU's. Need to Split it later. | |
2209 | */ | |
2210 | ret = iommu_alloc_root_entry(iommu); | |
2211 | if (ret) { | |
2212 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); | |
2213 | goto error; | |
2214 | } | |
4ed0d3e6 FY |
2215 | if (!ecap_pass_through(iommu->ecap)) |
2216 | pass_through = 0; | |
ba395927 | 2217 | } |
4ed0d3e6 FY |
2218 | if (iommu_pass_through) |
2219 | if (!pass_through) { | |
2220 | printk(KERN_INFO | |
2221 | "Pass Through is not supported by hardware.\n"); | |
2222 | iommu_pass_through = 0; | |
2223 | } | |
ba395927 | 2224 | |
1531a6a6 SS |
2225 | /* |
2226 | * Start from the sane iommu hardware state. | |
2227 | */ | |
a77b67d4 YS |
2228 | for_each_drhd_unit(drhd) { |
2229 | if (drhd->ignored) | |
2230 | continue; | |
2231 | ||
2232 | iommu = drhd->iommu; | |
1531a6a6 SS |
2233 | |
2234 | /* | |
2235 | * If the queued invalidation is already initialized by us | |
2236 | * (for example, while enabling interrupt-remapping) then | |
2237 | * we got the things already rolling from a sane state. | |
2238 | */ | |
2239 | if (iommu->qi) | |
2240 | continue; | |
2241 | ||
2242 | /* | |
2243 | * Clear any previous faults. | |
2244 | */ | |
2245 | dmar_fault(-1, iommu); | |
2246 | /* | |
2247 | * Disable queued invalidation if supported and already enabled | |
2248 | * before OS handover. | |
2249 | */ | |
2250 | dmar_disable_qi(iommu); | |
2251 | } | |
2252 | ||
2253 | for_each_drhd_unit(drhd) { | |
2254 | if (drhd->ignored) | |
2255 | continue; | |
2256 | ||
2257 | iommu = drhd->iommu; | |
2258 | ||
a77b67d4 YS |
2259 | if (dmar_enable_qi(iommu)) { |
2260 | /* | |
2261 | * Queued Invalidate not enabled, use Register Based | |
2262 | * Invalidate | |
2263 | */ | |
2264 | iommu->flush.flush_context = __iommu_flush_context; | |
2265 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; | |
2266 | printk(KERN_INFO "IOMMU 0x%Lx: using Register based " | |
b4e0f9eb FT |
2267 | "invalidation\n", |
2268 | (unsigned long long)drhd->reg_base_addr); | |
a77b67d4 YS |
2269 | } else { |
2270 | iommu->flush.flush_context = qi_flush_context; | |
2271 | iommu->flush.flush_iotlb = qi_flush_iotlb; | |
2272 | printk(KERN_INFO "IOMMU 0x%Lx: using Queued " | |
b4e0f9eb FT |
2273 | "invalidation\n", |
2274 | (unsigned long long)drhd->reg_base_addr); | |
a77b67d4 YS |
2275 | } |
2276 | } | |
2277 | ||
ba395927 | 2278 | /* |
4ed0d3e6 FY |
2279 | * If pass through is set and enabled, context entries of all pci |
2280 | * devices are intialized by pass through translation type. | |
ba395927 | 2281 | */ |
4ed0d3e6 FY |
2282 | if (iommu_pass_through) { |
2283 | ret = init_context_pass_through(); | |
2284 | if (ret) { | |
2285 | printk(KERN_ERR "IOMMU: Pass through init failed.\n"); | |
2286 | iommu_pass_through = 0; | |
ba395927 KA |
2287 | } |
2288 | } | |
2289 | ||
ba395927 | 2290 | /* |
4ed0d3e6 | 2291 | * If pass through is not set or not enabled, setup context entries for |
2c2e2c38 FY |
2292 | * identity mappings for rmrr, gfx, and isa and may fall back to static |
2293 | * identity mapping if iommu_identity_mapping is set. | |
ba395927 | 2294 | */ |
4ed0d3e6 | 2295 | if (!iommu_pass_through) { |
62edf5dc DW |
2296 | #ifdef CONFIG_DMAR_BROKEN_GFX_WA |
2297 | if (!iommu_identity_mapping) | |
2298 | iommu_identity_mapping = 2; | |
2299 | #endif | |
2c2e2c38 FY |
2300 | if (iommu_identity_mapping) |
2301 | iommu_prepare_static_identity_mapping(); | |
4ed0d3e6 FY |
2302 | /* |
2303 | * For each rmrr | |
2304 | * for each dev attached to rmrr | |
2305 | * do | |
2306 | * locate drhd for dev, alloc domain for dev | |
2307 | * allocate free domain | |
2308 | * allocate page table entries for rmrr | |
2309 | * if context not allocated for bus | |
2310 | * allocate and init context | |
2311 | * set present in root table for this bus | |
2312 | * init context with domain, translation etc | |
2313 | * endfor | |
2314 | * endfor | |
2315 | */ | |
2c2e2c38 | 2316 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
4ed0d3e6 FY |
2317 | for_each_rmrr_units(rmrr) { |
2318 | for (i = 0; i < rmrr->devices_cnt; i++) { | |
2319 | pdev = rmrr->devices[i]; | |
2320 | /* | |
2321 | * some BIOS lists non-exist devices in DMAR | |
2322 | * table. | |
2323 | */ | |
2324 | if (!pdev) | |
2325 | continue; | |
2326 | ret = iommu_prepare_rmrr_dev(rmrr, pdev); | |
2327 | if (ret) | |
2328 | printk(KERN_ERR | |
ba395927 | 2329 | "IOMMU: mapping reserved region failed\n"); |
4ed0d3e6 | 2330 | } |
ba395927 | 2331 | } |
ba395927 | 2332 | |
4ed0d3e6 FY |
2333 | iommu_prepare_isa(); |
2334 | } | |
49a0429e | 2335 | |
ba395927 KA |
2336 | /* |
2337 | * for each drhd | |
2338 | * enable fault log | |
2339 | * global invalidate context cache | |
2340 | * global invalidate iotlb | |
2341 | * enable translation | |
2342 | */ | |
2343 | for_each_drhd_unit(drhd) { | |
2344 | if (drhd->ignored) | |
2345 | continue; | |
2346 | iommu = drhd->iommu; | |
ba395927 KA |
2347 | |
2348 | iommu_flush_write_buffer(iommu); | |
2349 | ||
3460a6d9 KA |
2350 | ret = dmar_set_interrupt(iommu); |
2351 | if (ret) | |
2352 | goto error; | |
2353 | ||
ba395927 KA |
2354 | iommu_set_root_entry(iommu); |
2355 | ||
4c25a2c1 | 2356 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2357 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
f8bab735 | 2358 | iommu_disable_protect_mem_regions(iommu); |
2359 | ||
ba395927 KA |
2360 | ret = iommu_enable_translation(iommu); |
2361 | if (ret) | |
2362 | goto error; | |
2363 | } | |
2364 | ||
2365 | return 0; | |
2366 | error: | |
2367 | for_each_drhd_unit(drhd) { | |
2368 | if (drhd->ignored) | |
2369 | continue; | |
2370 | iommu = drhd->iommu; | |
2371 | free_iommu(iommu); | |
2372 | } | |
d9630fe9 | 2373 | kfree(g_iommus); |
ba395927 KA |
2374 | return ret; |
2375 | } | |
2376 | ||
5a5e02a6 | 2377 | /* Returns a number of VTD pages, but aligned to MM page size */ |
88cb6a74 DW |
2378 | static inline unsigned long aligned_nrpages(unsigned long host_addr, |
2379 | size_t size) | |
ba395927 | 2380 | { |
88cb6a74 | 2381 | host_addr &= ~PAGE_MASK; |
5a5e02a6 | 2382 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; |
ba395927 KA |
2383 | } |
2384 | ||
5a5e02a6 | 2385 | /* This takes a number of _MM_ pages, not VTD pages */ |
875764de DW |
2386 | static struct iova *intel_alloc_iova(struct device *dev, |
2387 | struct dmar_domain *domain, | |
2388 | unsigned long nrpages, uint64_t dma_mask) | |
ba395927 | 2389 | { |
ba395927 | 2390 | struct pci_dev *pdev = to_pci_dev(dev); |
ba395927 | 2391 | struct iova *iova = NULL; |
ba395927 | 2392 | |
875764de DW |
2393 | /* Restrict dma_mask to the width that the iommu can handle */ |
2394 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); | |
2395 | ||
2396 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { | |
ba395927 KA |
2397 | /* |
2398 | * First try to allocate an io virtual address in | |
284901a9 | 2399 | * DMA_BIT_MASK(32) and if that fails then try allocating |
3609801e | 2400 | * from higher range |
ba395927 | 2401 | */ |
875764de DW |
2402 | iova = alloc_iova(&domain->iovad, nrpages, |
2403 | IOVA_PFN(DMA_BIT_MASK(32)), 1); | |
2404 | if (iova) | |
2405 | return iova; | |
2406 | } | |
2407 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); | |
2408 | if (unlikely(!iova)) { | |
2409 | printk(KERN_ERR "Allocating %ld-page iova for %s failed", | |
2410 | nrpages, pci_name(pdev)); | |
f76aec76 KA |
2411 | return NULL; |
2412 | } | |
2413 | ||
2414 | return iova; | |
2415 | } | |
2416 | ||
2417 | static struct dmar_domain * | |
2418 | get_valid_domain_for_dev(struct pci_dev *pdev) | |
2419 | { | |
2420 | struct dmar_domain *domain; | |
2421 | int ret; | |
2422 | ||
2423 | domain = get_domain_for_dev(pdev, | |
2424 | DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
2425 | if (!domain) { | |
2426 | printk(KERN_ERR | |
2427 | "Allocating domain for %s failed", pci_name(pdev)); | |
4fe05bbc | 2428 | return NULL; |
ba395927 KA |
2429 | } |
2430 | ||
2431 | /* make sure context mapping is ok */ | |
5331fe6f | 2432 | if (unlikely(!domain_context_mapped(pdev))) { |
4ed0d3e6 FY |
2433 | ret = domain_context_mapping(domain, pdev, |
2434 | CONTEXT_TT_MULTI_LEVEL); | |
f76aec76 KA |
2435 | if (ret) { |
2436 | printk(KERN_ERR | |
2437 | "Domain context map for %s failed", | |
2438 | pci_name(pdev)); | |
4fe05bbc | 2439 | return NULL; |
f76aec76 | 2440 | } |
ba395927 KA |
2441 | } |
2442 | ||
f76aec76 KA |
2443 | return domain; |
2444 | } | |
2445 | ||
2c2e2c38 FY |
2446 | static int iommu_dummy(struct pci_dev *pdev) |
2447 | { | |
2448 | return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; | |
2449 | } | |
2450 | ||
40e4aa34 DW |
2451 | static int iommu_should_identity_map(struct pci_dev *pdev) |
2452 | { | |
62edf5dc DW |
2453 | if (iommu_identity_mapping == 2) |
2454 | return IS_GFX_DEVICE(pdev); | |
2455 | else | |
2456 | return pdev->dma_mask > DMA_BIT_MASK(32); | |
40e4aa34 DW |
2457 | } |
2458 | ||
2c2e2c38 FY |
2459 | /* Check if the pdev needs to go through non-identity map and unmap process.*/ |
2460 | static int iommu_no_mapping(struct pci_dev *pdev) | |
2461 | { | |
2462 | int found; | |
2463 | ||
1e4c64c4 DW |
2464 | if (iommu_dummy(pdev)) |
2465 | return 1; | |
2466 | ||
2c2e2c38 | 2467 | if (!iommu_identity_mapping) |
1e4c64c4 | 2468 | return 0; |
2c2e2c38 FY |
2469 | |
2470 | found = identity_mapping(pdev); | |
2471 | if (found) { | |
40e4aa34 | 2472 | if (iommu_should_identity_map(pdev)) |
2c2e2c38 FY |
2473 | return 1; |
2474 | else { | |
2475 | /* | |
2476 | * 32 bit DMA is removed from si_domain and fall back | |
2477 | * to non-identity mapping. | |
2478 | */ | |
2479 | domain_remove_one_dev_info(si_domain, pdev); | |
2480 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", | |
2481 | pci_name(pdev)); | |
2482 | return 0; | |
2483 | } | |
2484 | } else { | |
2485 | /* | |
2486 | * In case of a detached 64 bit DMA device from vm, the device | |
2487 | * is put into si_domain for identity mapping. | |
2488 | */ | |
40e4aa34 | 2489 | if (iommu_should_identity_map(pdev)) { |
2c2e2c38 FY |
2490 | int ret; |
2491 | ret = domain_add_dev_info(si_domain, pdev); | |
1b7bc0a1 DW |
2492 | if (ret) |
2493 | return 0; | |
2494 | ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL); | |
2c2e2c38 FY |
2495 | if (!ret) { |
2496 | printk(KERN_INFO "64bit %s uses identity mapping\n", | |
2497 | pci_name(pdev)); | |
2498 | return 1; | |
2499 | } | |
2500 | } | |
2501 | } | |
2502 | ||
1e4c64c4 | 2503 | return 0; |
2c2e2c38 FY |
2504 | } |
2505 | ||
bb9e6d65 FT |
2506 | static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr, |
2507 | size_t size, int dir, u64 dma_mask) | |
f76aec76 KA |
2508 | { |
2509 | struct pci_dev *pdev = to_pci_dev(hwdev); | |
f76aec76 | 2510 | struct dmar_domain *domain; |
5b6985ce | 2511 | phys_addr_t start_paddr; |
f76aec76 KA |
2512 | struct iova *iova; |
2513 | int prot = 0; | |
6865f0d1 | 2514 | int ret; |
8c11e798 | 2515 | struct intel_iommu *iommu; |
f76aec76 KA |
2516 | |
2517 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 FY |
2518 | |
2519 | if (iommu_no_mapping(pdev)) | |
6865f0d1 | 2520 | return paddr; |
f76aec76 KA |
2521 | |
2522 | domain = get_valid_domain_for_dev(pdev); | |
2523 | if (!domain) | |
2524 | return 0; | |
2525 | ||
8c11e798 | 2526 | iommu = domain_get_iommu(domain); |
88cb6a74 | 2527 | size = aligned_nrpages(paddr, size); |
f76aec76 | 2528 | |
5a5e02a6 DW |
2529 | iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), |
2530 | pdev->dma_mask); | |
f76aec76 KA |
2531 | if (!iova) |
2532 | goto error; | |
2533 | ||
ba395927 KA |
2534 | /* |
2535 | * Check if DMAR supports zero-length reads on write only | |
2536 | * mappings.. | |
2537 | */ | |
2538 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 2539 | !cap_zlr(iommu->cap)) |
ba395927 KA |
2540 | prot |= DMA_PTE_READ; |
2541 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
2542 | prot |= DMA_PTE_WRITE; | |
2543 | /* | |
6865f0d1 | 2544 | * paddr - (paddr + size) might be partial page, we should map the whole |
ba395927 | 2545 | * page. Note: if two part of one page are separately mapped, we |
6865f0d1 | 2546 | * might have two guest_addr mapping to the same host paddr, but this |
ba395927 KA |
2547 | * is not a big problem |
2548 | */ | |
0ab36de2 DW |
2549 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
2550 | paddr >> VTD_PAGE_SHIFT, size, prot); | |
ba395927 KA |
2551 | if (ret) |
2552 | goto error; | |
2553 | ||
1f0ef2aa DW |
2554 | /* it's a non-present to present mapping. Only flush if caching mode */ |
2555 | if (cap_caching_mode(iommu->cap)) | |
03d6a246 | 2556 | iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size); |
1f0ef2aa | 2557 | else |
8c11e798 | 2558 | iommu_flush_write_buffer(iommu); |
f76aec76 | 2559 | |
03d6a246 DW |
2560 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
2561 | start_paddr += paddr & ~PAGE_MASK; | |
2562 | return start_paddr; | |
ba395927 | 2563 | |
ba395927 | 2564 | error: |
f76aec76 KA |
2565 | if (iova) |
2566 | __free_iova(&domain->iovad, iova); | |
4cf2e75d | 2567 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
5b6985ce | 2568 | pci_name(pdev), size, (unsigned long long)paddr, dir); |
ba395927 KA |
2569 | return 0; |
2570 | } | |
2571 | ||
ffbbef5c FT |
2572 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
2573 | unsigned long offset, size_t size, | |
2574 | enum dma_data_direction dir, | |
2575 | struct dma_attrs *attrs) | |
bb9e6d65 | 2576 | { |
ffbbef5c FT |
2577 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
2578 | dir, to_pci_dev(dev)->dma_mask); | |
bb9e6d65 FT |
2579 | } |
2580 | ||
5e0d2a6f | 2581 | static void flush_unmaps(void) |
2582 | { | |
80b20dd8 | 2583 | int i, j; |
5e0d2a6f | 2584 | |
5e0d2a6f | 2585 | timer_on = 0; |
2586 | ||
2587 | /* just flush them all */ | |
2588 | for (i = 0; i < g_num_of_iommus; i++) { | |
a2bb8459 WH |
2589 | struct intel_iommu *iommu = g_iommus[i]; |
2590 | if (!iommu) | |
2591 | continue; | |
c42d9f32 | 2592 | |
9dd2fe89 YZ |
2593 | if (!deferred_flush[i].next) |
2594 | continue; | |
2595 | ||
2596 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, | |
93a23a72 | 2597 | DMA_TLB_GLOBAL_FLUSH); |
9dd2fe89 | 2598 | for (j = 0; j < deferred_flush[i].next; j++) { |
93a23a72 YZ |
2599 | unsigned long mask; |
2600 | struct iova *iova = deferred_flush[i].iova[j]; | |
2601 | ||
2602 | mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT; | |
2603 | mask = ilog2(mask >> VTD_PAGE_SHIFT); | |
2604 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], | |
2605 | iova->pfn_lo << PAGE_SHIFT, mask); | |
2606 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); | |
80b20dd8 | 2607 | } |
9dd2fe89 | 2608 | deferred_flush[i].next = 0; |
5e0d2a6f | 2609 | } |
2610 | ||
5e0d2a6f | 2611 | list_size = 0; |
5e0d2a6f | 2612 | } |
2613 | ||
2614 | static void flush_unmaps_timeout(unsigned long data) | |
2615 | { | |
80b20dd8 | 2616 | unsigned long flags; |
2617 | ||
2618 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
5e0d2a6f | 2619 | flush_unmaps(); |
80b20dd8 | 2620 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
5e0d2a6f | 2621 | } |
2622 | ||
2623 | static void add_unmap(struct dmar_domain *dom, struct iova *iova) | |
2624 | { | |
2625 | unsigned long flags; | |
80b20dd8 | 2626 | int next, iommu_id; |
8c11e798 | 2627 | struct intel_iommu *iommu; |
5e0d2a6f | 2628 | |
2629 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
80b20dd8 | 2630 | if (list_size == HIGH_WATER_MARK) |
2631 | flush_unmaps(); | |
2632 | ||
8c11e798 WH |
2633 | iommu = domain_get_iommu(dom); |
2634 | iommu_id = iommu->seq_id; | |
c42d9f32 | 2635 | |
80b20dd8 | 2636 | next = deferred_flush[iommu_id].next; |
2637 | deferred_flush[iommu_id].domain[next] = dom; | |
2638 | deferred_flush[iommu_id].iova[next] = iova; | |
2639 | deferred_flush[iommu_id].next++; | |
5e0d2a6f | 2640 | |
2641 | if (!timer_on) { | |
2642 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); | |
2643 | timer_on = 1; | |
2644 | } | |
2645 | list_size++; | |
2646 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); | |
2647 | } | |
2648 | ||
ffbbef5c FT |
2649 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
2650 | size_t size, enum dma_data_direction dir, | |
2651 | struct dma_attrs *attrs) | |
ba395927 | 2652 | { |
ba395927 | 2653 | struct pci_dev *pdev = to_pci_dev(dev); |
f76aec76 | 2654 | struct dmar_domain *domain; |
d794dc9b | 2655 | unsigned long start_pfn, last_pfn; |
ba395927 | 2656 | struct iova *iova; |
8c11e798 | 2657 | struct intel_iommu *iommu; |
ba395927 | 2658 | |
2c2e2c38 | 2659 | if (iommu_no_mapping(pdev)) |
f76aec76 | 2660 | return; |
2c2e2c38 | 2661 | |
ba395927 KA |
2662 | domain = find_domain(pdev); |
2663 | BUG_ON(!domain); | |
2664 | ||
8c11e798 WH |
2665 | iommu = domain_get_iommu(domain); |
2666 | ||
ba395927 | 2667 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
85b98276 DW |
2668 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
2669 | (unsigned long long)dev_addr)) | |
ba395927 | 2670 | return; |
ba395927 | 2671 | |
d794dc9b DW |
2672 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
2673 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
ba395927 | 2674 | |
d794dc9b DW |
2675 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
2676 | pci_name(pdev), start_pfn, last_pfn); | |
ba395927 | 2677 | |
f76aec76 | 2678 | /* clear the whole page */ |
d794dc9b DW |
2679 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
2680 | ||
f76aec76 | 2681 | /* free page tables */ |
d794dc9b DW |
2682 | dma_pte_free_pagetable(domain, start_pfn, last_pfn); |
2683 | ||
5e0d2a6f | 2684 | if (intel_iommu_strict) { |
03d6a246 | 2685 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
d794dc9b | 2686 | last_pfn - start_pfn + 1); |
5e0d2a6f | 2687 | /* free iova */ |
2688 | __free_iova(&domain->iovad, iova); | |
2689 | } else { | |
2690 | add_unmap(domain, iova); | |
2691 | /* | |
2692 | * queue up the release of the unmap to save the 1/6th of the | |
2693 | * cpu used up by the iotlb flush operation... | |
2694 | */ | |
5e0d2a6f | 2695 | } |
ba395927 KA |
2696 | } |
2697 | ||
d7ab5c46 FT |
2698 | static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size, |
2699 | int dir) | |
ffbbef5c FT |
2700 | { |
2701 | intel_unmap_page(dev, dev_addr, size, dir, NULL); | |
2702 | } | |
2703 | ||
d7ab5c46 FT |
2704 | static void *intel_alloc_coherent(struct device *hwdev, size_t size, |
2705 | dma_addr_t *dma_handle, gfp_t flags) | |
ba395927 KA |
2706 | { |
2707 | void *vaddr; | |
2708 | int order; | |
2709 | ||
5b6985ce | 2710 | size = PAGE_ALIGN(size); |
ba395927 KA |
2711 | order = get_order(size); |
2712 | flags &= ~(GFP_DMA | GFP_DMA32); | |
2713 | ||
2714 | vaddr = (void *)__get_free_pages(flags, order); | |
2715 | if (!vaddr) | |
2716 | return NULL; | |
2717 | memset(vaddr, 0, size); | |
2718 | ||
bb9e6d65 FT |
2719 | *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size, |
2720 | DMA_BIDIRECTIONAL, | |
2721 | hwdev->coherent_dma_mask); | |
ba395927 KA |
2722 | if (*dma_handle) |
2723 | return vaddr; | |
2724 | free_pages((unsigned long)vaddr, order); | |
2725 | return NULL; | |
2726 | } | |
2727 | ||
d7ab5c46 FT |
2728 | static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr, |
2729 | dma_addr_t dma_handle) | |
ba395927 KA |
2730 | { |
2731 | int order; | |
2732 | ||
5b6985ce | 2733 | size = PAGE_ALIGN(size); |
ba395927 KA |
2734 | order = get_order(size); |
2735 | ||
2736 | intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL); | |
2737 | free_pages((unsigned long)vaddr, order); | |
2738 | } | |
2739 | ||
d7ab5c46 FT |
2740 | static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist, |
2741 | int nelems, enum dma_data_direction dir, | |
2742 | struct dma_attrs *attrs) | |
ba395927 | 2743 | { |
ba395927 KA |
2744 | struct pci_dev *pdev = to_pci_dev(hwdev); |
2745 | struct dmar_domain *domain; | |
d794dc9b | 2746 | unsigned long start_pfn, last_pfn; |
f76aec76 | 2747 | struct iova *iova; |
8c11e798 | 2748 | struct intel_iommu *iommu; |
ba395927 | 2749 | |
2c2e2c38 | 2750 | if (iommu_no_mapping(pdev)) |
ba395927 KA |
2751 | return; |
2752 | ||
2753 | domain = find_domain(pdev); | |
8c11e798 WH |
2754 | BUG_ON(!domain); |
2755 | ||
2756 | iommu = domain_get_iommu(domain); | |
ba395927 | 2757 | |
c03ab37c | 2758 | iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address)); |
85b98276 DW |
2759 | if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n", |
2760 | (unsigned long long)sglist[0].dma_address)) | |
f76aec76 | 2761 | return; |
f76aec76 | 2762 | |
d794dc9b DW |
2763 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
2764 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
f76aec76 KA |
2765 | |
2766 | /* clear the whole page */ | |
d794dc9b DW |
2767 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
2768 | ||
f76aec76 | 2769 | /* free page tables */ |
d794dc9b | 2770 | dma_pte_free_pagetable(domain, start_pfn, last_pfn); |
f76aec76 | 2771 | |
03d6a246 | 2772 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
d794dc9b | 2773 | (last_pfn - start_pfn + 1)); |
f76aec76 KA |
2774 | |
2775 | /* free iova */ | |
2776 | __free_iova(&domain->iovad, iova); | |
ba395927 KA |
2777 | } |
2778 | ||
ba395927 | 2779 | static int intel_nontranslate_map_sg(struct device *hddev, |
c03ab37c | 2780 | struct scatterlist *sglist, int nelems, int dir) |
ba395927 KA |
2781 | { |
2782 | int i; | |
c03ab37c | 2783 | struct scatterlist *sg; |
ba395927 | 2784 | |
c03ab37c | 2785 | for_each_sg(sglist, sg, nelems, i) { |
12d4d40e | 2786 | BUG_ON(!sg_page(sg)); |
4cf2e75d | 2787 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
c03ab37c | 2788 | sg->dma_length = sg->length; |
ba395927 KA |
2789 | } |
2790 | return nelems; | |
2791 | } | |
2792 | ||
d7ab5c46 FT |
2793 | static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems, |
2794 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
ba395927 | 2795 | { |
ba395927 | 2796 | int i; |
ba395927 KA |
2797 | struct pci_dev *pdev = to_pci_dev(hwdev); |
2798 | struct dmar_domain *domain; | |
f76aec76 KA |
2799 | size_t size = 0; |
2800 | int prot = 0; | |
b536d24d | 2801 | size_t offset_pfn = 0; |
f76aec76 KA |
2802 | struct iova *iova = NULL; |
2803 | int ret; | |
c03ab37c | 2804 | struct scatterlist *sg; |
b536d24d | 2805 | unsigned long start_vpfn; |
8c11e798 | 2806 | struct intel_iommu *iommu; |
ba395927 KA |
2807 | |
2808 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 | 2809 | if (iommu_no_mapping(pdev)) |
c03ab37c | 2810 | return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir); |
ba395927 | 2811 | |
f76aec76 KA |
2812 | domain = get_valid_domain_for_dev(pdev); |
2813 | if (!domain) | |
2814 | return 0; | |
2815 | ||
8c11e798 WH |
2816 | iommu = domain_get_iommu(domain); |
2817 | ||
b536d24d | 2818 | for_each_sg(sglist, sg, nelems, i) |
88cb6a74 | 2819 | size += aligned_nrpages(sg->offset, sg->length); |
f76aec76 | 2820 | |
5a5e02a6 DW |
2821 | iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), |
2822 | pdev->dma_mask); | |
f76aec76 | 2823 | if (!iova) { |
c03ab37c | 2824 | sglist->dma_length = 0; |
f76aec76 KA |
2825 | return 0; |
2826 | } | |
2827 | ||
2828 | /* | |
2829 | * Check if DMAR supports zero-length reads on write only | |
2830 | * mappings.. | |
2831 | */ | |
2832 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 2833 | !cap_zlr(iommu->cap)) |
f76aec76 KA |
2834 | prot |= DMA_PTE_READ; |
2835 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
2836 | prot |= DMA_PTE_WRITE; | |
2837 | ||
b536d24d | 2838 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
e1605495 DW |
2839 | |
2840 | ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot); | |
2841 | if (unlikely(ret)) { | |
2842 | /* clear the page */ | |
2843 | dma_pte_clear_range(domain, start_vpfn, | |
2844 | start_vpfn + size - 1); | |
2845 | /* free page tables */ | |
2846 | dma_pte_free_pagetable(domain, start_vpfn, | |
2847 | start_vpfn + size - 1); | |
2848 | /* free iova */ | |
2849 | __free_iova(&domain->iovad, iova); | |
2850 | return 0; | |
ba395927 KA |
2851 | } |
2852 | ||
1f0ef2aa DW |
2853 | /* it's a non-present to present mapping. Only flush if caching mode */ |
2854 | if (cap_caching_mode(iommu->cap)) | |
03d6a246 | 2855 | iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn); |
1f0ef2aa | 2856 | else |
8c11e798 | 2857 | iommu_flush_write_buffer(iommu); |
1f0ef2aa | 2858 | |
ba395927 KA |
2859 | return nelems; |
2860 | } | |
2861 | ||
dfb805e8 FT |
2862 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
2863 | { | |
2864 | return !dma_addr; | |
2865 | } | |
2866 | ||
160c1d8e | 2867 | struct dma_map_ops intel_dma_ops = { |
ba395927 KA |
2868 | .alloc_coherent = intel_alloc_coherent, |
2869 | .free_coherent = intel_free_coherent, | |
ba395927 KA |
2870 | .map_sg = intel_map_sg, |
2871 | .unmap_sg = intel_unmap_sg, | |
ffbbef5c FT |
2872 | .map_page = intel_map_page, |
2873 | .unmap_page = intel_unmap_page, | |
dfb805e8 | 2874 | .mapping_error = intel_mapping_error, |
ba395927 KA |
2875 | }; |
2876 | ||
2877 | static inline int iommu_domain_cache_init(void) | |
2878 | { | |
2879 | int ret = 0; | |
2880 | ||
2881 | iommu_domain_cache = kmem_cache_create("iommu_domain", | |
2882 | sizeof(struct dmar_domain), | |
2883 | 0, | |
2884 | SLAB_HWCACHE_ALIGN, | |
2885 | ||
2886 | NULL); | |
2887 | if (!iommu_domain_cache) { | |
2888 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); | |
2889 | ret = -ENOMEM; | |
2890 | } | |
2891 | ||
2892 | return ret; | |
2893 | } | |
2894 | ||
2895 | static inline int iommu_devinfo_cache_init(void) | |
2896 | { | |
2897 | int ret = 0; | |
2898 | ||
2899 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", | |
2900 | sizeof(struct device_domain_info), | |
2901 | 0, | |
2902 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
2903 | NULL); |
2904 | if (!iommu_devinfo_cache) { | |
2905 | printk(KERN_ERR "Couldn't create devinfo cache\n"); | |
2906 | ret = -ENOMEM; | |
2907 | } | |
2908 | ||
2909 | return ret; | |
2910 | } | |
2911 | ||
2912 | static inline int iommu_iova_cache_init(void) | |
2913 | { | |
2914 | int ret = 0; | |
2915 | ||
2916 | iommu_iova_cache = kmem_cache_create("iommu_iova", | |
2917 | sizeof(struct iova), | |
2918 | 0, | |
2919 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
2920 | NULL); |
2921 | if (!iommu_iova_cache) { | |
2922 | printk(KERN_ERR "Couldn't create iova cache\n"); | |
2923 | ret = -ENOMEM; | |
2924 | } | |
2925 | ||
2926 | return ret; | |
2927 | } | |
2928 | ||
2929 | static int __init iommu_init_mempool(void) | |
2930 | { | |
2931 | int ret; | |
2932 | ret = iommu_iova_cache_init(); | |
2933 | if (ret) | |
2934 | return ret; | |
2935 | ||
2936 | ret = iommu_domain_cache_init(); | |
2937 | if (ret) | |
2938 | goto domain_error; | |
2939 | ||
2940 | ret = iommu_devinfo_cache_init(); | |
2941 | if (!ret) | |
2942 | return ret; | |
2943 | ||
2944 | kmem_cache_destroy(iommu_domain_cache); | |
2945 | domain_error: | |
2946 | kmem_cache_destroy(iommu_iova_cache); | |
2947 | ||
2948 | return -ENOMEM; | |
2949 | } | |
2950 | ||
2951 | static void __init iommu_exit_mempool(void) | |
2952 | { | |
2953 | kmem_cache_destroy(iommu_devinfo_cache); | |
2954 | kmem_cache_destroy(iommu_domain_cache); | |
2955 | kmem_cache_destroy(iommu_iova_cache); | |
2956 | ||
2957 | } | |
2958 | ||
ba395927 KA |
2959 | static void __init init_no_remapping_devices(void) |
2960 | { | |
2961 | struct dmar_drhd_unit *drhd; | |
2962 | ||
2963 | for_each_drhd_unit(drhd) { | |
2964 | if (!drhd->include_all) { | |
2965 | int i; | |
2966 | for (i = 0; i < drhd->devices_cnt; i++) | |
2967 | if (drhd->devices[i] != NULL) | |
2968 | break; | |
2969 | /* ignore DMAR unit if no pci devices exist */ | |
2970 | if (i == drhd->devices_cnt) | |
2971 | drhd->ignored = 1; | |
2972 | } | |
2973 | } | |
2974 | ||
2975 | if (dmar_map_gfx) | |
2976 | return; | |
2977 | ||
2978 | for_each_drhd_unit(drhd) { | |
2979 | int i; | |
2980 | if (drhd->ignored || drhd->include_all) | |
2981 | continue; | |
2982 | ||
2983 | for (i = 0; i < drhd->devices_cnt; i++) | |
2984 | if (drhd->devices[i] && | |
2985 | !IS_GFX_DEVICE(drhd->devices[i])) | |
2986 | break; | |
2987 | ||
2988 | if (i < drhd->devices_cnt) | |
2989 | continue; | |
2990 | ||
2991 | /* bypass IOMMU if it is just for gfx devices */ | |
2992 | drhd->ignored = 1; | |
2993 | for (i = 0; i < drhd->devices_cnt; i++) { | |
2994 | if (!drhd->devices[i]) | |
2995 | continue; | |
358dd8ac | 2996 | drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
ba395927 KA |
2997 | } |
2998 | } | |
2999 | } | |
3000 | ||
f59c7b69 FY |
3001 | #ifdef CONFIG_SUSPEND |
3002 | static int init_iommu_hw(void) | |
3003 | { | |
3004 | struct dmar_drhd_unit *drhd; | |
3005 | struct intel_iommu *iommu = NULL; | |
3006 | ||
3007 | for_each_active_iommu(iommu, drhd) | |
3008 | if (iommu->qi) | |
3009 | dmar_reenable_qi(iommu); | |
3010 | ||
3011 | for_each_active_iommu(iommu, drhd) { | |
3012 | iommu_flush_write_buffer(iommu); | |
3013 | ||
3014 | iommu_set_root_entry(iommu); | |
3015 | ||
3016 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3017 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3018 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3019 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
3020 | iommu_disable_protect_mem_regions(iommu); |
3021 | iommu_enable_translation(iommu); | |
3022 | } | |
3023 | ||
3024 | return 0; | |
3025 | } | |
3026 | ||
3027 | static void iommu_flush_all(void) | |
3028 | { | |
3029 | struct dmar_drhd_unit *drhd; | |
3030 | struct intel_iommu *iommu; | |
3031 | ||
3032 | for_each_active_iommu(iommu, drhd) { | |
3033 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3034 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3035 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3036 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
3037 | } |
3038 | } | |
3039 | ||
3040 | static int iommu_suspend(struct sys_device *dev, pm_message_t state) | |
3041 | { | |
3042 | struct dmar_drhd_unit *drhd; | |
3043 | struct intel_iommu *iommu = NULL; | |
3044 | unsigned long flag; | |
3045 | ||
3046 | for_each_active_iommu(iommu, drhd) { | |
3047 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, | |
3048 | GFP_ATOMIC); | |
3049 | if (!iommu->iommu_state) | |
3050 | goto nomem; | |
3051 | } | |
3052 | ||
3053 | iommu_flush_all(); | |
3054 | ||
3055 | for_each_active_iommu(iommu, drhd) { | |
3056 | iommu_disable_translation(iommu); | |
3057 | ||
3058 | spin_lock_irqsave(&iommu->register_lock, flag); | |
3059 | ||
3060 | iommu->iommu_state[SR_DMAR_FECTL_REG] = | |
3061 | readl(iommu->reg + DMAR_FECTL_REG); | |
3062 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = | |
3063 | readl(iommu->reg + DMAR_FEDATA_REG); | |
3064 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = | |
3065 | readl(iommu->reg + DMAR_FEADDR_REG); | |
3066 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = | |
3067 | readl(iommu->reg + DMAR_FEUADDR_REG); | |
3068 | ||
3069 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
3070 | } | |
3071 | return 0; | |
3072 | ||
3073 | nomem: | |
3074 | for_each_active_iommu(iommu, drhd) | |
3075 | kfree(iommu->iommu_state); | |
3076 | ||
3077 | return -ENOMEM; | |
3078 | } | |
3079 | ||
3080 | static int iommu_resume(struct sys_device *dev) | |
3081 | { | |
3082 | struct dmar_drhd_unit *drhd; | |
3083 | struct intel_iommu *iommu = NULL; | |
3084 | unsigned long flag; | |
3085 | ||
3086 | if (init_iommu_hw()) { | |
3087 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); | |
3088 | return -EIO; | |
3089 | } | |
3090 | ||
3091 | for_each_active_iommu(iommu, drhd) { | |
3092 | ||
3093 | spin_lock_irqsave(&iommu->register_lock, flag); | |
3094 | ||
3095 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], | |
3096 | iommu->reg + DMAR_FECTL_REG); | |
3097 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], | |
3098 | iommu->reg + DMAR_FEDATA_REG); | |
3099 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], | |
3100 | iommu->reg + DMAR_FEADDR_REG); | |
3101 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], | |
3102 | iommu->reg + DMAR_FEUADDR_REG); | |
3103 | ||
3104 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
3105 | } | |
3106 | ||
3107 | for_each_active_iommu(iommu, drhd) | |
3108 | kfree(iommu->iommu_state); | |
3109 | ||
3110 | return 0; | |
3111 | } | |
3112 | ||
3113 | static struct sysdev_class iommu_sysclass = { | |
3114 | .name = "iommu", | |
3115 | .resume = iommu_resume, | |
3116 | .suspend = iommu_suspend, | |
3117 | }; | |
3118 | ||
3119 | static struct sys_device device_iommu = { | |
3120 | .cls = &iommu_sysclass, | |
3121 | }; | |
3122 | ||
3123 | static int __init init_iommu_sysfs(void) | |
3124 | { | |
3125 | int error; | |
3126 | ||
3127 | error = sysdev_class_register(&iommu_sysclass); | |
3128 | if (error) | |
3129 | return error; | |
3130 | ||
3131 | error = sysdev_register(&device_iommu); | |
3132 | if (error) | |
3133 | sysdev_class_unregister(&iommu_sysclass); | |
3134 | ||
3135 | return error; | |
3136 | } | |
3137 | ||
3138 | #else | |
3139 | static int __init init_iommu_sysfs(void) | |
3140 | { | |
3141 | return 0; | |
3142 | } | |
3143 | #endif /* CONFIG_PM */ | |
3144 | ||
ba395927 KA |
3145 | int __init intel_iommu_init(void) |
3146 | { | |
3147 | int ret = 0; | |
3148 | ||
ba395927 KA |
3149 | if (dmar_table_init()) |
3150 | return -ENODEV; | |
3151 | ||
1886e8a9 SS |
3152 | if (dmar_dev_scope_init()) |
3153 | return -ENODEV; | |
3154 | ||
2ae21010 SS |
3155 | /* |
3156 | * Check the need for DMA-remapping initialization now. | |
3157 | * Above initialization will also be used by Interrupt-remapping. | |
3158 | */ | |
4ed0d3e6 | 3159 | if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled) |
2ae21010 SS |
3160 | return -ENODEV; |
3161 | ||
ba395927 KA |
3162 | iommu_init_mempool(); |
3163 | dmar_init_reserved_ranges(); | |
3164 | ||
3165 | init_no_remapping_devices(); | |
3166 | ||
3167 | ret = init_dmars(); | |
3168 | if (ret) { | |
3169 | printk(KERN_ERR "IOMMU: dmar init failed\n"); | |
3170 | put_iova_domain(&reserved_iova_list); | |
3171 | iommu_exit_mempool(); | |
3172 | return ret; | |
3173 | } | |
3174 | printk(KERN_INFO | |
3175 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); | |
3176 | ||
5e0d2a6f | 3177 | init_timer(&unmap_timer); |
ba395927 | 3178 | force_iommu = 1; |
4ed0d3e6 FY |
3179 | |
3180 | if (!iommu_pass_through) { | |
3181 | printk(KERN_INFO | |
3182 | "Multi-level page-table translation for DMAR.\n"); | |
3183 | dma_ops = &intel_dma_ops; | |
3184 | } else | |
3185 | printk(KERN_INFO | |
3186 | "DMAR: Pass through translation for DMAR.\n"); | |
3187 | ||
f59c7b69 | 3188 | init_iommu_sysfs(); |
a8bcbb0d JR |
3189 | |
3190 | register_iommu(&intel_iommu_ops); | |
3191 | ||
ba395927 KA |
3192 | return 0; |
3193 | } | |
e820482c | 3194 | |
3199aa6b HW |
3195 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
3196 | struct pci_dev *pdev) | |
3197 | { | |
3198 | struct pci_dev *tmp, *parent; | |
3199 | ||
3200 | if (!iommu || !pdev) | |
3201 | return; | |
3202 | ||
3203 | /* dependent device detach */ | |
3204 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
3205 | /* Secondary interface's bus number and devfn 0 */ | |
3206 | if (tmp) { | |
3207 | parent = pdev->bus->self; | |
3208 | while (parent != tmp) { | |
3209 | iommu_detach_dev(iommu, parent->bus->number, | |
276dbf99 | 3210 | parent->devfn); |
3199aa6b HW |
3211 | parent = parent->bus->self; |
3212 | } | |
3213 | if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */ | |
3214 | iommu_detach_dev(iommu, | |
3215 | tmp->subordinate->number, 0); | |
3216 | else /* this is a legacy PCI bridge */ | |
276dbf99 DW |
3217 | iommu_detach_dev(iommu, tmp->bus->number, |
3218 | tmp->devfn); | |
3199aa6b HW |
3219 | } |
3220 | } | |
3221 | ||
2c2e2c38 | 3222 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
c7151a8d WH |
3223 | struct pci_dev *pdev) |
3224 | { | |
3225 | struct device_domain_info *info; | |
3226 | struct intel_iommu *iommu; | |
3227 | unsigned long flags; | |
3228 | int found = 0; | |
3229 | struct list_head *entry, *tmp; | |
3230 | ||
276dbf99 DW |
3231 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
3232 | pdev->devfn); | |
c7151a8d WH |
3233 | if (!iommu) |
3234 | return; | |
3235 | ||
3236 | spin_lock_irqsave(&device_domain_lock, flags); | |
3237 | list_for_each_safe(entry, tmp, &domain->devices) { | |
3238 | info = list_entry(entry, struct device_domain_info, link); | |
276dbf99 | 3239 | /* No need to compare PCI domain; it has to be the same */ |
c7151a8d WH |
3240 | if (info->bus == pdev->bus->number && |
3241 | info->devfn == pdev->devfn) { | |
3242 | list_del(&info->link); | |
3243 | list_del(&info->global); | |
3244 | if (info->dev) | |
3245 | info->dev->dev.archdata.iommu = NULL; | |
3246 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
3247 | ||
93a23a72 | 3248 | iommu_disable_dev_iotlb(info); |
c7151a8d | 3249 | iommu_detach_dev(iommu, info->bus, info->devfn); |
3199aa6b | 3250 | iommu_detach_dependent_devices(iommu, pdev); |
c7151a8d WH |
3251 | free_devinfo_mem(info); |
3252 | ||
3253 | spin_lock_irqsave(&device_domain_lock, flags); | |
3254 | ||
3255 | if (found) | |
3256 | break; | |
3257 | else | |
3258 | continue; | |
3259 | } | |
3260 | ||
3261 | /* if there is no other devices under the same iommu | |
3262 | * owned by this domain, clear this iommu in iommu_bmp | |
3263 | * update iommu count and coherency | |
3264 | */ | |
276dbf99 DW |
3265 | if (iommu == device_to_iommu(info->segment, info->bus, |
3266 | info->devfn)) | |
c7151a8d WH |
3267 | found = 1; |
3268 | } | |
3269 | ||
3270 | if (found == 0) { | |
3271 | unsigned long tmp_flags; | |
3272 | spin_lock_irqsave(&domain->iommu_lock, tmp_flags); | |
3273 | clear_bit(iommu->seq_id, &domain->iommu_bmp); | |
3274 | domain->iommu_count--; | |
58c610bd | 3275 | domain_update_iommu_cap(domain); |
c7151a8d WH |
3276 | spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags); |
3277 | } | |
3278 | ||
3279 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
3280 | } | |
3281 | ||
3282 | static void vm_domain_remove_all_dev_info(struct dmar_domain *domain) | |
3283 | { | |
3284 | struct device_domain_info *info; | |
3285 | struct intel_iommu *iommu; | |
3286 | unsigned long flags1, flags2; | |
3287 | ||
3288 | spin_lock_irqsave(&device_domain_lock, flags1); | |
3289 | while (!list_empty(&domain->devices)) { | |
3290 | info = list_entry(domain->devices.next, | |
3291 | struct device_domain_info, link); | |
3292 | list_del(&info->link); | |
3293 | list_del(&info->global); | |
3294 | if (info->dev) | |
3295 | info->dev->dev.archdata.iommu = NULL; | |
3296 | ||
3297 | spin_unlock_irqrestore(&device_domain_lock, flags1); | |
3298 | ||
93a23a72 | 3299 | iommu_disable_dev_iotlb(info); |
276dbf99 | 3300 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
c7151a8d | 3301 | iommu_detach_dev(iommu, info->bus, info->devfn); |
3199aa6b | 3302 | iommu_detach_dependent_devices(iommu, info->dev); |
c7151a8d WH |
3303 | |
3304 | /* clear this iommu in iommu_bmp, update iommu count | |
58c610bd | 3305 | * and capabilities |
c7151a8d WH |
3306 | */ |
3307 | spin_lock_irqsave(&domain->iommu_lock, flags2); | |
3308 | if (test_and_clear_bit(iommu->seq_id, | |
3309 | &domain->iommu_bmp)) { | |
3310 | domain->iommu_count--; | |
58c610bd | 3311 | domain_update_iommu_cap(domain); |
c7151a8d WH |
3312 | } |
3313 | spin_unlock_irqrestore(&domain->iommu_lock, flags2); | |
3314 | ||
3315 | free_devinfo_mem(info); | |
3316 | spin_lock_irqsave(&device_domain_lock, flags1); | |
3317 | } | |
3318 | spin_unlock_irqrestore(&device_domain_lock, flags1); | |
3319 | } | |
3320 | ||
5e98c4b1 WH |
3321 | /* domain id for virtual machine, it won't be set in context */ |
3322 | static unsigned long vm_domid; | |
3323 | ||
fe40f1e0 WH |
3324 | static int vm_domain_min_agaw(struct dmar_domain *domain) |
3325 | { | |
3326 | int i; | |
3327 | int min_agaw = domain->agaw; | |
3328 | ||
3329 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
3330 | for (; i < g_num_of_iommus; ) { | |
3331 | if (min_agaw > g_iommus[i]->agaw) | |
3332 | min_agaw = g_iommus[i]->agaw; | |
3333 | ||
3334 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
3335 | } | |
3336 | ||
3337 | return min_agaw; | |
3338 | } | |
3339 | ||
5e98c4b1 WH |
3340 | static struct dmar_domain *iommu_alloc_vm_domain(void) |
3341 | { | |
3342 | struct dmar_domain *domain; | |
3343 | ||
3344 | domain = alloc_domain_mem(); | |
3345 | if (!domain) | |
3346 | return NULL; | |
3347 | ||
3348 | domain->id = vm_domid++; | |
3349 | memset(&domain->iommu_bmp, 0, sizeof(unsigned long)); | |
3350 | domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE; | |
3351 | ||
3352 | return domain; | |
3353 | } | |
3354 | ||
2c2e2c38 | 3355 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
5e98c4b1 WH |
3356 | { |
3357 | int adjust_width; | |
3358 | ||
3359 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); | |
5e98c4b1 WH |
3360 | spin_lock_init(&domain->iommu_lock); |
3361 | ||
3362 | domain_reserve_special_ranges(domain); | |
3363 | ||
3364 | /* calculate AGAW */ | |
3365 | domain->gaw = guest_width; | |
3366 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
3367 | domain->agaw = width_to_agaw(adjust_width); | |
3368 | ||
3369 | INIT_LIST_HEAD(&domain->devices); | |
3370 | ||
3371 | domain->iommu_count = 0; | |
3372 | domain->iommu_coherency = 0; | |
fe40f1e0 | 3373 | domain->max_addr = 0; |
5e98c4b1 WH |
3374 | |
3375 | /* always allocate the top pgd */ | |
3376 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(); | |
3377 | if (!domain->pgd) | |
3378 | return -ENOMEM; | |
3379 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); | |
3380 | return 0; | |
3381 | } | |
3382 | ||
3383 | static void iommu_free_vm_domain(struct dmar_domain *domain) | |
3384 | { | |
3385 | unsigned long flags; | |
3386 | struct dmar_drhd_unit *drhd; | |
3387 | struct intel_iommu *iommu; | |
3388 | unsigned long i; | |
3389 | unsigned long ndomains; | |
3390 | ||
3391 | for_each_drhd_unit(drhd) { | |
3392 | if (drhd->ignored) | |
3393 | continue; | |
3394 | iommu = drhd->iommu; | |
3395 | ||
3396 | ndomains = cap_ndoms(iommu->cap); | |
3397 | i = find_first_bit(iommu->domain_ids, ndomains); | |
3398 | for (; i < ndomains; ) { | |
3399 | if (iommu->domains[i] == domain) { | |
3400 | spin_lock_irqsave(&iommu->lock, flags); | |
3401 | clear_bit(i, iommu->domain_ids); | |
3402 | iommu->domains[i] = NULL; | |
3403 | spin_unlock_irqrestore(&iommu->lock, flags); | |
3404 | break; | |
3405 | } | |
3406 | i = find_next_bit(iommu->domain_ids, ndomains, i+1); | |
3407 | } | |
3408 | } | |
3409 | } | |
3410 | ||
3411 | static void vm_domain_exit(struct dmar_domain *domain) | |
3412 | { | |
5e98c4b1 WH |
3413 | /* Domain 0 is reserved, so dont process it */ |
3414 | if (!domain) | |
3415 | return; | |
3416 | ||
3417 | vm_domain_remove_all_dev_info(domain); | |
3418 | /* destroy iovas */ | |
3419 | put_iova_domain(&domain->iovad); | |
5e98c4b1 WH |
3420 | |
3421 | /* clear ptes */ | |
595badf5 | 3422 | dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
5e98c4b1 WH |
3423 | |
3424 | /* free page tables */ | |
d794dc9b | 3425 | dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
5e98c4b1 WH |
3426 | |
3427 | iommu_free_vm_domain(domain); | |
3428 | free_domain_mem(domain); | |
3429 | } | |
3430 | ||
5d450806 | 3431 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
38717946 | 3432 | { |
5d450806 | 3433 | struct dmar_domain *dmar_domain; |
38717946 | 3434 | |
5d450806 JR |
3435 | dmar_domain = iommu_alloc_vm_domain(); |
3436 | if (!dmar_domain) { | |
38717946 | 3437 | printk(KERN_ERR |
5d450806 JR |
3438 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
3439 | return -ENOMEM; | |
38717946 | 3440 | } |
2c2e2c38 | 3441 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
38717946 | 3442 | printk(KERN_ERR |
5d450806 JR |
3443 | "intel_iommu_domain_init() failed\n"); |
3444 | vm_domain_exit(dmar_domain); | |
3445 | return -ENOMEM; | |
38717946 | 3446 | } |
5d450806 | 3447 | domain->priv = dmar_domain; |
faa3d6f5 | 3448 | |
5d450806 | 3449 | return 0; |
38717946 | 3450 | } |
38717946 | 3451 | |
5d450806 | 3452 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
38717946 | 3453 | { |
5d450806 JR |
3454 | struct dmar_domain *dmar_domain = domain->priv; |
3455 | ||
3456 | domain->priv = NULL; | |
3457 | vm_domain_exit(dmar_domain); | |
38717946 | 3458 | } |
38717946 | 3459 | |
4c5478c9 JR |
3460 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
3461 | struct device *dev) | |
38717946 | 3462 | { |
4c5478c9 JR |
3463 | struct dmar_domain *dmar_domain = domain->priv; |
3464 | struct pci_dev *pdev = to_pci_dev(dev); | |
fe40f1e0 WH |
3465 | struct intel_iommu *iommu; |
3466 | int addr_width; | |
3467 | u64 end; | |
faa3d6f5 WH |
3468 | int ret; |
3469 | ||
3470 | /* normally pdev is not mapped */ | |
3471 | if (unlikely(domain_context_mapped(pdev))) { | |
3472 | struct dmar_domain *old_domain; | |
3473 | ||
3474 | old_domain = find_domain(pdev); | |
3475 | if (old_domain) { | |
2c2e2c38 FY |
3476 | if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
3477 | dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) | |
3478 | domain_remove_one_dev_info(old_domain, pdev); | |
faa3d6f5 WH |
3479 | else |
3480 | domain_remove_dev_info(old_domain); | |
3481 | } | |
3482 | } | |
3483 | ||
276dbf99 DW |
3484 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
3485 | pdev->devfn); | |
fe40f1e0 WH |
3486 | if (!iommu) |
3487 | return -ENODEV; | |
3488 | ||
3489 | /* check if this iommu agaw is sufficient for max mapped address */ | |
3490 | addr_width = agaw_to_width(iommu->agaw); | |
3491 | end = DOMAIN_MAX_ADDR(addr_width); | |
3492 | end = end & VTD_PAGE_MASK; | |
4c5478c9 | 3493 | if (end < dmar_domain->max_addr) { |
fe40f1e0 WH |
3494 | printk(KERN_ERR "%s: iommu agaw (%d) is not " |
3495 | "sufficient for the mapped address (%llx)\n", | |
4c5478c9 | 3496 | __func__, iommu->agaw, dmar_domain->max_addr); |
fe40f1e0 WH |
3497 | return -EFAULT; |
3498 | } | |
3499 | ||
2c2e2c38 | 3500 | ret = domain_add_dev_info(dmar_domain, pdev); |
faa3d6f5 WH |
3501 | if (ret) |
3502 | return ret; | |
3503 | ||
93a23a72 | 3504 | ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
faa3d6f5 | 3505 | return ret; |
38717946 | 3506 | } |
38717946 | 3507 | |
4c5478c9 JR |
3508 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
3509 | struct device *dev) | |
38717946 | 3510 | { |
4c5478c9 JR |
3511 | struct dmar_domain *dmar_domain = domain->priv; |
3512 | struct pci_dev *pdev = to_pci_dev(dev); | |
3513 | ||
2c2e2c38 | 3514 | domain_remove_one_dev_info(dmar_domain, pdev); |
faa3d6f5 | 3515 | } |
c7151a8d | 3516 | |
dde57a21 JR |
3517 | static int intel_iommu_map_range(struct iommu_domain *domain, |
3518 | unsigned long iova, phys_addr_t hpa, | |
3519 | size_t size, int iommu_prot) | |
faa3d6f5 | 3520 | { |
dde57a21 | 3521 | struct dmar_domain *dmar_domain = domain->priv; |
fe40f1e0 WH |
3522 | u64 max_addr; |
3523 | int addr_width; | |
dde57a21 | 3524 | int prot = 0; |
faa3d6f5 | 3525 | int ret; |
fe40f1e0 | 3526 | |
dde57a21 JR |
3527 | if (iommu_prot & IOMMU_READ) |
3528 | prot |= DMA_PTE_READ; | |
3529 | if (iommu_prot & IOMMU_WRITE) | |
3530 | prot |= DMA_PTE_WRITE; | |
9cf06697 SY |
3531 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
3532 | prot |= DMA_PTE_SNP; | |
dde57a21 | 3533 | |
163cc52c | 3534 | max_addr = iova + size; |
dde57a21 | 3535 | if (dmar_domain->max_addr < max_addr) { |
fe40f1e0 WH |
3536 | int min_agaw; |
3537 | u64 end; | |
3538 | ||
3539 | /* check if minimum agaw is sufficient for mapped address */ | |
dde57a21 | 3540 | min_agaw = vm_domain_min_agaw(dmar_domain); |
fe40f1e0 WH |
3541 | addr_width = agaw_to_width(min_agaw); |
3542 | end = DOMAIN_MAX_ADDR(addr_width); | |
3543 | end = end & VTD_PAGE_MASK; | |
3544 | if (end < max_addr) { | |
3545 | printk(KERN_ERR "%s: iommu agaw (%d) is not " | |
3546 | "sufficient for the mapped address (%llx)\n", | |
3547 | __func__, min_agaw, max_addr); | |
3548 | return -EFAULT; | |
3549 | } | |
dde57a21 | 3550 | dmar_domain->max_addr = max_addr; |
fe40f1e0 | 3551 | } |
ad051221 DW |
3552 | /* Round up size to next multiple of PAGE_SIZE, if it and |
3553 | the low bits of hpa would take us onto the next page */ | |
88cb6a74 | 3554 | size = aligned_nrpages(hpa, size); |
ad051221 DW |
3555 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
3556 | hpa >> VTD_PAGE_SHIFT, size, prot); | |
faa3d6f5 | 3557 | return ret; |
38717946 | 3558 | } |
38717946 | 3559 | |
dde57a21 JR |
3560 | static void intel_iommu_unmap_range(struct iommu_domain *domain, |
3561 | unsigned long iova, size_t size) | |
38717946 | 3562 | { |
dde57a21 | 3563 | struct dmar_domain *dmar_domain = domain->priv; |
faa3d6f5 | 3564 | |
163cc52c DW |
3565 | dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT, |
3566 | (iova + size - 1) >> VTD_PAGE_SHIFT); | |
fe40f1e0 | 3567 | |
163cc52c DW |
3568 | if (dmar_domain->max_addr == iova + size) |
3569 | dmar_domain->max_addr = iova; | |
38717946 | 3570 | } |
38717946 | 3571 | |
d14d6577 JR |
3572 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
3573 | unsigned long iova) | |
38717946 | 3574 | { |
d14d6577 | 3575 | struct dmar_domain *dmar_domain = domain->priv; |
38717946 | 3576 | struct dma_pte *pte; |
faa3d6f5 | 3577 | u64 phys = 0; |
38717946 | 3578 | |
b026fd28 | 3579 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT); |
38717946 | 3580 | if (pte) |
faa3d6f5 | 3581 | phys = dma_pte_addr(pte); |
38717946 | 3582 | |
faa3d6f5 | 3583 | return phys; |
38717946 | 3584 | } |
a8bcbb0d | 3585 | |
dbb9fd86 SY |
3586 | static int intel_iommu_domain_has_cap(struct iommu_domain *domain, |
3587 | unsigned long cap) | |
3588 | { | |
3589 | struct dmar_domain *dmar_domain = domain->priv; | |
3590 | ||
3591 | if (cap == IOMMU_CAP_CACHE_COHERENCY) | |
3592 | return dmar_domain->iommu_snooping; | |
3593 | ||
3594 | return 0; | |
3595 | } | |
3596 | ||
a8bcbb0d JR |
3597 | static struct iommu_ops intel_iommu_ops = { |
3598 | .domain_init = intel_iommu_domain_init, | |
3599 | .domain_destroy = intel_iommu_domain_destroy, | |
3600 | .attach_dev = intel_iommu_attach_device, | |
3601 | .detach_dev = intel_iommu_detach_device, | |
3602 | .map = intel_iommu_map_range, | |
3603 | .unmap = intel_iommu_unmap_range, | |
3604 | .iova_to_phys = intel_iommu_iova_to_phys, | |
dbb9fd86 | 3605 | .domain_has_cap = intel_iommu_domain_has_cap, |
a8bcbb0d | 3606 | }; |
9af88143 DW |
3607 | |
3608 | static void __devinit quirk_iommu_rwbf(struct pci_dev *dev) | |
3609 | { | |
3610 | /* | |
3611 | * Mobile 4 Series Chipset neglects to set RWBF capability, | |
3612 | * but needs it: | |
3613 | */ | |
3614 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); | |
3615 | rwbf_quirk = 1; | |
3616 | } | |
3617 | ||
3618 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |