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ba395927 KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Shaohua Li <shaohua.li@intel.com> | |
20 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
5b6985ce | 21 | * Author: Fenghua Yu <fenghua.yu@intel.com> |
ba395927 KA |
22 | */ |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/bitmap.h> | |
5e0d2a6f | 26 | #include <linux/debugfs.h> |
ba395927 KA |
27 | #include <linux/slab.h> |
28 | #include <linux/irq.h> | |
29 | #include <linux/interrupt.h> | |
ba395927 KA |
30 | #include <linux/spinlock.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/dmar.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/mempool.h> | |
5e0d2a6f | 35 | #include <linux/timer.h> |
38717946 | 36 | #include <linux/iova.h> |
5d450806 | 37 | #include <linux/iommu.h> |
38717946 | 38 | #include <linux/intel-iommu.h> |
f59c7b69 | 39 | #include <linux/sysdev.h> |
ba395927 | 40 | #include <asm/cacheflush.h> |
46a7fa27 | 41 | #include <asm/iommu.h> |
ba395927 KA |
42 | #include "pci.h" |
43 | ||
5b6985ce FY |
44 | #define ROOT_SIZE VTD_PAGE_SIZE |
45 | #define CONTEXT_SIZE VTD_PAGE_SIZE | |
46 | ||
ba395927 KA |
47 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
48 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) | |
49 | ||
50 | #define IOAPIC_RANGE_START (0xfee00000) | |
51 | #define IOAPIC_RANGE_END (0xfeefffff) | |
52 | #define IOVA_START_ADDR (0x1000) | |
53 | ||
54 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
55 | ||
4ed0d3e6 FY |
56 | #define MAX_AGAW_WIDTH 64 |
57 | ||
ba395927 | 58 | #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1) |
595badf5 | 59 | #define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
ba395927 | 60 | |
f27be03b | 61 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
284901a9 | 62 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
6a35528a | 63 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
5e0d2a6f | 64 | |
fd18de50 | 65 | |
dd4e8319 DW |
66 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
67 | are never going to work. */ | |
68 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) | |
69 | { | |
70 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
71 | } | |
72 | ||
73 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) | |
74 | { | |
75 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
76 | } | |
77 | static inline unsigned long page_to_dma_pfn(struct page *pg) | |
78 | { | |
79 | return mm_to_dma_pfn(page_to_pfn(pg)); | |
80 | } | |
81 | static inline unsigned long virt_to_dma_pfn(void *p) | |
82 | { | |
83 | return page_to_dma_pfn(virt_to_page(p)); | |
84 | } | |
85 | ||
d9630fe9 WH |
86 | /* global iommu list, set NULL for ignored DMAR units */ |
87 | static struct intel_iommu **g_iommus; | |
88 | ||
9af88143 DW |
89 | static int rwbf_quirk; |
90 | ||
46b08e1a MM |
91 | /* |
92 | * 0: Present | |
93 | * 1-11: Reserved | |
94 | * 12-63: Context Ptr (12 - (haw-1)) | |
95 | * 64-127: Reserved | |
96 | */ | |
97 | struct root_entry { | |
98 | u64 val; | |
99 | u64 rsvd1; | |
100 | }; | |
101 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) | |
102 | static inline bool root_present(struct root_entry *root) | |
103 | { | |
104 | return (root->val & 1); | |
105 | } | |
106 | static inline void set_root_present(struct root_entry *root) | |
107 | { | |
108 | root->val |= 1; | |
109 | } | |
110 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
111 | { | |
112 | root->val |= value & VTD_PAGE_MASK; | |
113 | } | |
114 | ||
115 | static inline struct context_entry * | |
116 | get_context_addr_from_root(struct root_entry *root) | |
117 | { | |
118 | return (struct context_entry *) | |
119 | (root_present(root)?phys_to_virt( | |
120 | root->val & VTD_PAGE_MASK) : | |
121 | NULL); | |
122 | } | |
123 | ||
7a8fc25e MM |
124 | /* |
125 | * low 64 bits: | |
126 | * 0: present | |
127 | * 1: fault processing disable | |
128 | * 2-3: translation type | |
129 | * 12-63: address space root | |
130 | * high 64 bits: | |
131 | * 0-2: address width | |
132 | * 3-6: aval | |
133 | * 8-23: domain id | |
134 | */ | |
135 | struct context_entry { | |
136 | u64 lo; | |
137 | u64 hi; | |
138 | }; | |
c07e7d21 MM |
139 | |
140 | static inline bool context_present(struct context_entry *context) | |
141 | { | |
142 | return (context->lo & 1); | |
143 | } | |
144 | static inline void context_set_present(struct context_entry *context) | |
145 | { | |
146 | context->lo |= 1; | |
147 | } | |
148 | ||
149 | static inline void context_set_fault_enable(struct context_entry *context) | |
150 | { | |
151 | context->lo &= (((u64)-1) << 2) | 1; | |
152 | } | |
153 | ||
c07e7d21 MM |
154 | static inline void context_set_translation_type(struct context_entry *context, |
155 | unsigned long value) | |
156 | { | |
157 | context->lo &= (((u64)-1) << 4) | 3; | |
158 | context->lo |= (value & 3) << 2; | |
159 | } | |
160 | ||
161 | static inline void context_set_address_root(struct context_entry *context, | |
162 | unsigned long value) | |
163 | { | |
164 | context->lo |= value & VTD_PAGE_MASK; | |
165 | } | |
166 | ||
167 | static inline void context_set_address_width(struct context_entry *context, | |
168 | unsigned long value) | |
169 | { | |
170 | context->hi |= value & 7; | |
171 | } | |
172 | ||
173 | static inline void context_set_domain_id(struct context_entry *context, | |
174 | unsigned long value) | |
175 | { | |
176 | context->hi |= (value & ((1 << 16) - 1)) << 8; | |
177 | } | |
178 | ||
179 | static inline void context_clear_entry(struct context_entry *context) | |
180 | { | |
181 | context->lo = 0; | |
182 | context->hi = 0; | |
183 | } | |
7a8fc25e | 184 | |
622ba12a MM |
185 | /* |
186 | * 0: readable | |
187 | * 1: writable | |
188 | * 2-6: reserved | |
189 | * 7: super page | |
9cf06697 SY |
190 | * 8-10: available |
191 | * 11: snoop behavior | |
622ba12a MM |
192 | * 12-63: Host physcial address |
193 | */ | |
194 | struct dma_pte { | |
195 | u64 val; | |
196 | }; | |
622ba12a | 197 | |
19c239ce MM |
198 | static inline void dma_clear_pte(struct dma_pte *pte) |
199 | { | |
200 | pte->val = 0; | |
201 | } | |
202 | ||
203 | static inline void dma_set_pte_readable(struct dma_pte *pte) | |
204 | { | |
205 | pte->val |= DMA_PTE_READ; | |
206 | } | |
207 | ||
208 | static inline void dma_set_pte_writable(struct dma_pte *pte) | |
209 | { | |
210 | pte->val |= DMA_PTE_WRITE; | |
211 | } | |
212 | ||
9cf06697 SY |
213 | static inline void dma_set_pte_snp(struct dma_pte *pte) |
214 | { | |
215 | pte->val |= DMA_PTE_SNP; | |
216 | } | |
217 | ||
19c239ce MM |
218 | static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot) |
219 | { | |
220 | pte->val = (pte->val & ~3) | (prot & 3); | |
221 | } | |
222 | ||
223 | static inline u64 dma_pte_addr(struct dma_pte *pte) | |
224 | { | |
c85994e4 DW |
225 | #ifdef CONFIG_64BIT |
226 | return pte->val & VTD_PAGE_MASK; | |
227 | #else | |
228 | /* Must have a full atomic 64-bit read */ | |
229 | return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK; | |
230 | #endif | |
19c239ce MM |
231 | } |
232 | ||
dd4e8319 | 233 | static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn) |
19c239ce | 234 | { |
dd4e8319 | 235 | pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT; |
19c239ce MM |
236 | } |
237 | ||
238 | static inline bool dma_pte_present(struct dma_pte *pte) | |
239 | { | |
240 | return (pte->val & 3) != 0; | |
241 | } | |
622ba12a | 242 | |
75e6bf96 DW |
243 | static inline int first_pte_in_page(struct dma_pte *pte) |
244 | { | |
245 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
246 | } | |
247 | ||
2c2e2c38 FY |
248 | /* |
249 | * This domain is a statically identity mapping domain. | |
250 | * 1. This domain creats a static 1:1 mapping to all usable memory. | |
251 | * 2. It maps to each iommu if successful. | |
252 | * 3. Each iommu mapps to this domain if successful. | |
253 | */ | |
254 | struct dmar_domain *si_domain; | |
255 | ||
3b5410e7 | 256 | /* devices under the same p2p bridge are owned in one domain */ |
cdc7b837 | 257 | #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0) |
3b5410e7 | 258 | |
1ce28feb WH |
259 | /* domain represents a virtual machine, more than one devices |
260 | * across iommus may be owned in one domain, e.g. kvm guest. | |
261 | */ | |
262 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1) | |
263 | ||
2c2e2c38 FY |
264 | /* si_domain contains mulitple devices */ |
265 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2) | |
266 | ||
99126f7c MM |
267 | struct dmar_domain { |
268 | int id; /* domain id */ | |
8c11e798 | 269 | unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/ |
99126f7c MM |
270 | |
271 | struct list_head devices; /* all devices' list */ | |
272 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
273 | ||
274 | struct dma_pte *pgd; /* virtual address */ | |
99126f7c MM |
275 | int gaw; /* max guest address width */ |
276 | ||
277 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
278 | int agaw; | |
279 | ||
3b5410e7 | 280 | int flags; /* flags to find out type of domain */ |
8e604097 WH |
281 | |
282 | int iommu_coherency;/* indicate coherency of iommu access */ | |
58c610bd | 283 | int iommu_snooping; /* indicate snooping control feature*/ |
c7151a8d WH |
284 | int iommu_count; /* reference count of iommu */ |
285 | spinlock_t iommu_lock; /* protect iommu set in domain */ | |
fe40f1e0 | 286 | u64 max_addr; /* maximum mapped address */ |
99126f7c MM |
287 | }; |
288 | ||
a647dacb MM |
289 | /* PCI domain-device relationship */ |
290 | struct device_domain_info { | |
291 | struct list_head link; /* link to domain siblings */ | |
292 | struct list_head global; /* link to global list */ | |
276dbf99 DW |
293 | int segment; /* PCI domain */ |
294 | u8 bus; /* PCI bus number */ | |
a647dacb MM |
295 | u8 devfn; /* PCI devfn number */ |
296 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ | |
93a23a72 | 297 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
a647dacb MM |
298 | struct dmar_domain *domain; /* pointer to domain */ |
299 | }; | |
300 | ||
5e0d2a6f | 301 | static void flush_unmaps_timeout(unsigned long data); |
302 | ||
303 | DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); | |
304 | ||
80b20dd8 | 305 | #define HIGH_WATER_MARK 250 |
306 | struct deferred_flush_tables { | |
307 | int next; | |
308 | struct iova *iova[HIGH_WATER_MARK]; | |
309 | struct dmar_domain *domain[HIGH_WATER_MARK]; | |
310 | }; | |
311 | ||
312 | static struct deferred_flush_tables *deferred_flush; | |
313 | ||
5e0d2a6f | 314 | /* bitmap for indexing intel_iommus */ |
5e0d2a6f | 315 | static int g_num_of_iommus; |
316 | ||
317 | static DEFINE_SPINLOCK(async_umap_flush_lock); | |
318 | static LIST_HEAD(unmaps_to_do); | |
319 | ||
320 | static int timer_on; | |
321 | static long list_size; | |
5e0d2a6f | 322 | |
ba395927 KA |
323 | static void domain_remove_dev_info(struct dmar_domain *domain); |
324 | ||
0cd5c3c8 KM |
325 | #ifdef CONFIG_DMAR_DEFAULT_ON |
326 | int dmar_disabled = 0; | |
327 | #else | |
328 | int dmar_disabled = 1; | |
329 | #endif /*CONFIG_DMAR_DEFAULT_ON*/ | |
330 | ||
ba395927 | 331 | static int __initdata dmar_map_gfx = 1; |
7d3b03ce | 332 | static int dmar_forcedac; |
5e0d2a6f | 333 | static int intel_iommu_strict; |
ba395927 KA |
334 | |
335 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) | |
336 | static DEFINE_SPINLOCK(device_domain_lock); | |
337 | static LIST_HEAD(device_domain_list); | |
338 | ||
a8bcbb0d JR |
339 | static struct iommu_ops intel_iommu_ops; |
340 | ||
ba395927 KA |
341 | static int __init intel_iommu_setup(char *str) |
342 | { | |
343 | if (!str) | |
344 | return -EINVAL; | |
345 | while (*str) { | |
0cd5c3c8 KM |
346 | if (!strncmp(str, "on", 2)) { |
347 | dmar_disabled = 0; | |
348 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); | |
349 | } else if (!strncmp(str, "off", 3)) { | |
ba395927 | 350 | dmar_disabled = 1; |
0cd5c3c8 | 351 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
ba395927 KA |
352 | } else if (!strncmp(str, "igfx_off", 8)) { |
353 | dmar_map_gfx = 0; | |
354 | printk(KERN_INFO | |
355 | "Intel-IOMMU: disable GFX device mapping\n"); | |
7d3b03ce | 356 | } else if (!strncmp(str, "forcedac", 8)) { |
5e0d2a6f | 357 | printk(KERN_INFO |
7d3b03ce KA |
358 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
359 | dmar_forcedac = 1; | |
5e0d2a6f | 360 | } else if (!strncmp(str, "strict", 6)) { |
361 | printk(KERN_INFO | |
362 | "Intel-IOMMU: disable batched IOTLB flush\n"); | |
363 | intel_iommu_strict = 1; | |
ba395927 KA |
364 | } |
365 | ||
366 | str += strcspn(str, ","); | |
367 | while (*str == ',') | |
368 | str++; | |
369 | } | |
370 | return 0; | |
371 | } | |
372 | __setup("intel_iommu=", intel_iommu_setup); | |
373 | ||
374 | static struct kmem_cache *iommu_domain_cache; | |
375 | static struct kmem_cache *iommu_devinfo_cache; | |
376 | static struct kmem_cache *iommu_iova_cache; | |
377 | ||
eb3fa7cb KA |
378 | static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep) |
379 | { | |
380 | unsigned int flags; | |
381 | void *vaddr; | |
382 | ||
383 | /* trying to avoid low memory issues */ | |
384 | flags = current->flags & PF_MEMALLOC; | |
385 | current->flags |= PF_MEMALLOC; | |
386 | vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC); | |
387 | current->flags &= (~PF_MEMALLOC | flags); | |
388 | return vaddr; | |
389 | } | |
390 | ||
391 | ||
ba395927 KA |
392 | static inline void *alloc_pgtable_page(void) |
393 | { | |
eb3fa7cb KA |
394 | unsigned int flags; |
395 | void *vaddr; | |
396 | ||
397 | /* trying to avoid low memory issues */ | |
398 | flags = current->flags & PF_MEMALLOC; | |
399 | current->flags |= PF_MEMALLOC; | |
400 | vaddr = (void *)get_zeroed_page(GFP_ATOMIC); | |
401 | current->flags &= (~PF_MEMALLOC | flags); | |
402 | return vaddr; | |
ba395927 KA |
403 | } |
404 | ||
405 | static inline void free_pgtable_page(void *vaddr) | |
406 | { | |
407 | free_page((unsigned long)vaddr); | |
408 | } | |
409 | ||
410 | static inline void *alloc_domain_mem(void) | |
411 | { | |
eb3fa7cb | 412 | return iommu_kmem_cache_alloc(iommu_domain_cache); |
ba395927 KA |
413 | } |
414 | ||
38717946 | 415 | static void free_domain_mem(void *vaddr) |
ba395927 KA |
416 | { |
417 | kmem_cache_free(iommu_domain_cache, vaddr); | |
418 | } | |
419 | ||
420 | static inline void * alloc_devinfo_mem(void) | |
421 | { | |
eb3fa7cb | 422 | return iommu_kmem_cache_alloc(iommu_devinfo_cache); |
ba395927 KA |
423 | } |
424 | ||
425 | static inline void free_devinfo_mem(void *vaddr) | |
426 | { | |
427 | kmem_cache_free(iommu_devinfo_cache, vaddr); | |
428 | } | |
429 | ||
430 | struct iova *alloc_iova_mem(void) | |
431 | { | |
eb3fa7cb | 432 | return iommu_kmem_cache_alloc(iommu_iova_cache); |
ba395927 KA |
433 | } |
434 | ||
435 | void free_iova_mem(struct iova *iova) | |
436 | { | |
437 | kmem_cache_free(iommu_iova_cache, iova); | |
438 | } | |
439 | ||
1b573683 WH |
440 | |
441 | static inline int width_to_agaw(int width); | |
442 | ||
4ed0d3e6 | 443 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
1b573683 WH |
444 | { |
445 | unsigned long sagaw; | |
446 | int agaw = -1; | |
447 | ||
448 | sagaw = cap_sagaw(iommu->cap); | |
4ed0d3e6 | 449 | for (agaw = width_to_agaw(max_gaw); |
1b573683 WH |
450 | agaw >= 0; agaw--) { |
451 | if (test_bit(agaw, &sagaw)) | |
452 | break; | |
453 | } | |
454 | ||
455 | return agaw; | |
456 | } | |
457 | ||
4ed0d3e6 FY |
458 | /* |
459 | * Calculate max SAGAW for each iommu. | |
460 | */ | |
461 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
462 | { | |
463 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); | |
464 | } | |
465 | ||
466 | /* | |
467 | * calculate agaw for each iommu. | |
468 | * "SAGAW" may be different across iommus, use a default agaw, and | |
469 | * get a supported less agaw for iommus that don't support the default agaw. | |
470 | */ | |
471 | int iommu_calculate_agaw(struct intel_iommu *iommu) | |
472 | { | |
473 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
474 | } | |
475 | ||
2c2e2c38 | 476 | /* This functionin only returns single iommu in a domain */ |
8c11e798 WH |
477 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
478 | { | |
479 | int iommu_id; | |
480 | ||
2c2e2c38 | 481 | /* si_domain and vm domain should not get here. */ |
1ce28feb | 482 | BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE); |
2c2e2c38 | 483 | BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY); |
1ce28feb | 484 | |
8c11e798 WH |
485 | iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); |
486 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) | |
487 | return NULL; | |
488 | ||
489 | return g_iommus[iommu_id]; | |
490 | } | |
491 | ||
8e604097 WH |
492 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
493 | { | |
494 | int i; | |
495 | ||
496 | domain->iommu_coherency = 1; | |
497 | ||
498 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
499 | for (; i < g_num_of_iommus; ) { | |
500 | if (!ecap_coherent(g_iommus[i]->ecap)) { | |
501 | domain->iommu_coherency = 0; | |
502 | break; | |
503 | } | |
504 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
505 | } | |
506 | } | |
507 | ||
58c610bd SY |
508 | static void domain_update_iommu_snooping(struct dmar_domain *domain) |
509 | { | |
510 | int i; | |
511 | ||
512 | domain->iommu_snooping = 1; | |
513 | ||
514 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
515 | for (; i < g_num_of_iommus; ) { | |
516 | if (!ecap_sc_support(g_iommus[i]->ecap)) { | |
517 | domain->iommu_snooping = 0; | |
518 | break; | |
519 | } | |
520 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
521 | } | |
522 | } | |
523 | ||
524 | /* Some capabilities may be different across iommus */ | |
525 | static void domain_update_iommu_cap(struct dmar_domain *domain) | |
526 | { | |
527 | domain_update_iommu_coherency(domain); | |
528 | domain_update_iommu_snooping(domain); | |
529 | } | |
530 | ||
276dbf99 | 531 | static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn) |
c7151a8d WH |
532 | { |
533 | struct dmar_drhd_unit *drhd = NULL; | |
534 | int i; | |
535 | ||
536 | for_each_drhd_unit(drhd) { | |
537 | if (drhd->ignored) | |
538 | continue; | |
276dbf99 DW |
539 | if (segment != drhd->segment) |
540 | continue; | |
c7151a8d | 541 | |
924b6231 | 542 | for (i = 0; i < drhd->devices_cnt; i++) { |
288e4877 DH |
543 | if (drhd->devices[i] && |
544 | drhd->devices[i]->bus->number == bus && | |
c7151a8d WH |
545 | drhd->devices[i]->devfn == devfn) |
546 | return drhd->iommu; | |
4958c5dc DW |
547 | if (drhd->devices[i] && |
548 | drhd->devices[i]->subordinate && | |
924b6231 DW |
549 | drhd->devices[i]->subordinate->number <= bus && |
550 | drhd->devices[i]->subordinate->subordinate >= bus) | |
551 | return drhd->iommu; | |
552 | } | |
c7151a8d WH |
553 | |
554 | if (drhd->include_all) | |
555 | return drhd->iommu; | |
556 | } | |
557 | ||
558 | return NULL; | |
559 | } | |
560 | ||
5331fe6f WH |
561 | static void domain_flush_cache(struct dmar_domain *domain, |
562 | void *addr, int size) | |
563 | { | |
564 | if (!domain->iommu_coherency) | |
565 | clflush_cache_range(addr, size); | |
566 | } | |
567 | ||
ba395927 KA |
568 | /* Gets context entry for a given bus and devfn */ |
569 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, | |
570 | u8 bus, u8 devfn) | |
571 | { | |
572 | struct root_entry *root; | |
573 | struct context_entry *context; | |
574 | unsigned long phy_addr; | |
575 | unsigned long flags; | |
576 | ||
577 | spin_lock_irqsave(&iommu->lock, flags); | |
578 | root = &iommu->root_entry[bus]; | |
579 | context = get_context_addr_from_root(root); | |
580 | if (!context) { | |
581 | context = (struct context_entry *)alloc_pgtable_page(); | |
582 | if (!context) { | |
583 | spin_unlock_irqrestore(&iommu->lock, flags); | |
584 | return NULL; | |
585 | } | |
5b6985ce | 586 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
ba395927 KA |
587 | phy_addr = virt_to_phys((void *)context); |
588 | set_root_value(root, phy_addr); | |
589 | set_root_present(root); | |
590 | __iommu_flush_cache(iommu, root, sizeof(*root)); | |
591 | } | |
592 | spin_unlock_irqrestore(&iommu->lock, flags); | |
593 | return &context[devfn]; | |
594 | } | |
595 | ||
596 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
597 | { | |
598 | struct root_entry *root; | |
599 | struct context_entry *context; | |
600 | int ret; | |
601 | unsigned long flags; | |
602 | ||
603 | spin_lock_irqsave(&iommu->lock, flags); | |
604 | root = &iommu->root_entry[bus]; | |
605 | context = get_context_addr_from_root(root); | |
606 | if (!context) { | |
607 | ret = 0; | |
608 | goto out; | |
609 | } | |
c07e7d21 | 610 | ret = context_present(&context[devfn]); |
ba395927 KA |
611 | out: |
612 | spin_unlock_irqrestore(&iommu->lock, flags); | |
613 | return ret; | |
614 | } | |
615 | ||
616 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
617 | { | |
618 | struct root_entry *root; | |
619 | struct context_entry *context; | |
620 | unsigned long flags; | |
621 | ||
622 | spin_lock_irqsave(&iommu->lock, flags); | |
623 | root = &iommu->root_entry[bus]; | |
624 | context = get_context_addr_from_root(root); | |
625 | if (context) { | |
c07e7d21 | 626 | context_clear_entry(&context[devfn]); |
ba395927 KA |
627 | __iommu_flush_cache(iommu, &context[devfn], \ |
628 | sizeof(*context)); | |
629 | } | |
630 | spin_unlock_irqrestore(&iommu->lock, flags); | |
631 | } | |
632 | ||
633 | static void free_context_table(struct intel_iommu *iommu) | |
634 | { | |
635 | struct root_entry *root; | |
636 | int i; | |
637 | unsigned long flags; | |
638 | struct context_entry *context; | |
639 | ||
640 | spin_lock_irqsave(&iommu->lock, flags); | |
641 | if (!iommu->root_entry) { | |
642 | goto out; | |
643 | } | |
644 | for (i = 0; i < ROOT_ENTRY_NR; i++) { | |
645 | root = &iommu->root_entry[i]; | |
646 | context = get_context_addr_from_root(root); | |
647 | if (context) | |
648 | free_pgtable_page(context); | |
649 | } | |
650 | free_pgtable_page(iommu->root_entry); | |
651 | iommu->root_entry = NULL; | |
652 | out: | |
653 | spin_unlock_irqrestore(&iommu->lock, flags); | |
654 | } | |
655 | ||
656 | /* page table handling */ | |
657 | #define LEVEL_STRIDE (9) | |
658 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) | |
659 | ||
660 | static inline int agaw_to_level(int agaw) | |
661 | { | |
662 | return agaw + 2; | |
663 | } | |
664 | ||
665 | static inline int agaw_to_width(int agaw) | |
666 | { | |
667 | return 30 + agaw * LEVEL_STRIDE; | |
668 | ||
669 | } | |
670 | ||
671 | static inline int width_to_agaw(int width) | |
672 | { | |
673 | return (width - 30) / LEVEL_STRIDE; | |
674 | } | |
675 | ||
676 | static inline unsigned int level_to_offset_bits(int level) | |
677 | { | |
6660c63a | 678 | return (level - 1) * LEVEL_STRIDE; |
ba395927 KA |
679 | } |
680 | ||
77dfa56c | 681 | static inline int pfn_level_offset(unsigned long pfn, int level) |
ba395927 | 682 | { |
6660c63a | 683 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; |
ba395927 KA |
684 | } |
685 | ||
6660c63a | 686 | static inline unsigned long level_mask(int level) |
ba395927 | 687 | { |
6660c63a | 688 | return -1UL << level_to_offset_bits(level); |
ba395927 KA |
689 | } |
690 | ||
6660c63a | 691 | static inline unsigned long level_size(int level) |
ba395927 | 692 | { |
6660c63a | 693 | return 1UL << level_to_offset_bits(level); |
ba395927 KA |
694 | } |
695 | ||
6660c63a | 696 | static inline unsigned long align_to_level(unsigned long pfn, int level) |
ba395927 | 697 | { |
6660c63a | 698 | return (pfn + level_size(level) - 1) & level_mask(level); |
ba395927 KA |
699 | } |
700 | ||
b026fd28 DW |
701 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
702 | unsigned long pfn) | |
ba395927 | 703 | { |
b026fd28 | 704 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
ba395927 KA |
705 | struct dma_pte *parent, *pte = NULL; |
706 | int level = agaw_to_level(domain->agaw); | |
707 | int offset; | |
ba395927 KA |
708 | |
709 | BUG_ON(!domain->pgd); | |
b026fd28 | 710 | BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width); |
ba395927 KA |
711 | parent = domain->pgd; |
712 | ||
ba395927 KA |
713 | while (level > 0) { |
714 | void *tmp_page; | |
715 | ||
b026fd28 | 716 | offset = pfn_level_offset(pfn, level); |
ba395927 KA |
717 | pte = &parent[offset]; |
718 | if (level == 1) | |
719 | break; | |
720 | ||
19c239ce | 721 | if (!dma_pte_present(pte)) { |
c85994e4 DW |
722 | uint64_t pteval; |
723 | ||
ba395927 KA |
724 | tmp_page = alloc_pgtable_page(); |
725 | ||
206a73c1 | 726 | if (!tmp_page) |
ba395927 | 727 | return NULL; |
206a73c1 | 728 | |
c85994e4 DW |
729 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
730 | pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; | |
731 | if (cmpxchg64(&pte->val, 0ULL, pteval)) { | |
732 | /* Someone else set it while we were thinking; use theirs. */ | |
733 | free_pgtable_page(tmp_page); | |
734 | } else { | |
735 | dma_pte_addr(pte); | |
736 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
737 | } | |
ba395927 | 738 | } |
19c239ce | 739 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
740 | level--; |
741 | } | |
742 | ||
ba395927 KA |
743 | return pte; |
744 | } | |
745 | ||
746 | /* return address's pte at specific level */ | |
90dcfb5e DW |
747 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
748 | unsigned long pfn, | |
749 | int level) | |
ba395927 KA |
750 | { |
751 | struct dma_pte *parent, *pte = NULL; | |
752 | int total = agaw_to_level(domain->agaw); | |
753 | int offset; | |
754 | ||
755 | parent = domain->pgd; | |
756 | while (level <= total) { | |
90dcfb5e | 757 | offset = pfn_level_offset(pfn, total); |
ba395927 KA |
758 | pte = &parent[offset]; |
759 | if (level == total) | |
760 | return pte; | |
761 | ||
19c239ce | 762 | if (!dma_pte_present(pte)) |
ba395927 | 763 | break; |
19c239ce | 764 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
765 | total--; |
766 | } | |
767 | return NULL; | |
768 | } | |
769 | ||
ba395927 | 770 | /* clear last level pte, a tlb flush should be followed */ |
595badf5 DW |
771 | static void dma_pte_clear_range(struct dmar_domain *domain, |
772 | unsigned long start_pfn, | |
773 | unsigned long last_pfn) | |
ba395927 | 774 | { |
04b18e65 | 775 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
310a5ab9 | 776 | struct dma_pte *first_pte, *pte; |
66eae846 | 777 | |
04b18e65 | 778 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
595badf5 | 779 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
ba395927 | 780 | |
04b18e65 | 781 | /* we don't need lock here; nobody else touches the iova range */ |
595badf5 | 782 | while (start_pfn <= last_pfn) { |
310a5ab9 DW |
783 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1); |
784 | if (!pte) { | |
785 | start_pfn = align_to_level(start_pfn + 1, 2); | |
786 | continue; | |
787 | } | |
75e6bf96 | 788 | do { |
310a5ab9 DW |
789 | dma_clear_pte(pte); |
790 | start_pfn++; | |
791 | pte++; | |
75e6bf96 DW |
792 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
793 | ||
310a5ab9 DW |
794 | domain_flush_cache(domain, first_pte, |
795 | (void *)pte - (void *)first_pte); | |
ba395927 KA |
796 | } |
797 | } | |
798 | ||
799 | /* free page table pages. last level pte should already be cleared */ | |
800 | static void dma_pte_free_pagetable(struct dmar_domain *domain, | |
d794dc9b DW |
801 | unsigned long start_pfn, |
802 | unsigned long last_pfn) | |
ba395927 | 803 | { |
6660c63a | 804 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
f3a0a52f | 805 | struct dma_pte *first_pte, *pte; |
ba395927 KA |
806 | int total = agaw_to_level(domain->agaw); |
807 | int level; | |
6660c63a | 808 | unsigned long tmp; |
ba395927 | 809 | |
6660c63a DW |
810 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
811 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); | |
ba395927 | 812 | |
f3a0a52f | 813 | /* We don't need lock here; nobody else touches the iova range */ |
ba395927 KA |
814 | level = 2; |
815 | while (level <= total) { | |
6660c63a DW |
816 | tmp = align_to_level(start_pfn, level); |
817 | ||
f3a0a52f | 818 | /* If we can't even clear one PTE at this level, we're done */ |
6660c63a | 819 | if (tmp + level_size(level) - 1 > last_pfn) |
ba395927 KA |
820 | return; |
821 | ||
3d7b0e41 | 822 | while (tmp + level_size(level) - 1 <= last_pfn) { |
f3a0a52f DW |
823 | first_pte = pte = dma_pfn_level_pte(domain, tmp, level); |
824 | if (!pte) { | |
825 | tmp = align_to_level(tmp + 1, level + 1); | |
826 | continue; | |
827 | } | |
75e6bf96 | 828 | do { |
f3a0a52f | 829 | free_pgtable_page(phys_to_virt(dma_pte_addr(pte))); |
19c239ce | 830 | dma_clear_pte(pte); |
f3a0a52f DW |
831 | pte++; |
832 | tmp += level_size(level); | |
75e6bf96 DW |
833 | } while (!first_pte_in_page(pte) && |
834 | tmp + level_size(level) - 1 <= last_pfn); | |
835 | ||
f3a0a52f DW |
836 | domain_flush_cache(domain, first_pte, |
837 | (void *)pte - (void *)first_pte); | |
838 | ||
ba395927 KA |
839 | } |
840 | level++; | |
841 | } | |
842 | /* free pgd */ | |
d794dc9b | 843 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
ba395927 KA |
844 | free_pgtable_page(domain->pgd); |
845 | domain->pgd = NULL; | |
846 | } | |
847 | } | |
848 | ||
849 | /* iommu handling */ | |
850 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |
851 | { | |
852 | struct root_entry *root; | |
853 | unsigned long flags; | |
854 | ||
855 | root = (struct root_entry *)alloc_pgtable_page(); | |
856 | if (!root) | |
857 | return -ENOMEM; | |
858 | ||
5b6985ce | 859 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
ba395927 KA |
860 | |
861 | spin_lock_irqsave(&iommu->lock, flags); | |
862 | iommu->root_entry = root; | |
863 | spin_unlock_irqrestore(&iommu->lock, flags); | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
ba395927 KA |
868 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
869 | { | |
870 | void *addr; | |
c416daa9 | 871 | u32 sts; |
ba395927 KA |
872 | unsigned long flag; |
873 | ||
874 | addr = iommu->root_entry; | |
875 | ||
876 | spin_lock_irqsave(&iommu->register_lock, flag); | |
877 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); | |
878 | ||
c416daa9 | 879 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
880 | |
881 | /* Make sure hardware complete it */ | |
882 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 883 | readl, (sts & DMA_GSTS_RTPS), sts); |
ba395927 KA |
884 | |
885 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
886 | } | |
887 | ||
888 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |
889 | { | |
890 | u32 val; | |
891 | unsigned long flag; | |
892 | ||
9af88143 | 893 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
ba395927 | 894 | return; |
ba395927 KA |
895 | |
896 | spin_lock_irqsave(&iommu->register_lock, flag); | |
462b60f6 | 897 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
898 | |
899 | /* Make sure hardware complete it */ | |
900 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 901 | readl, (!(val & DMA_GSTS_WBFS)), val); |
ba395927 KA |
902 | |
903 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
904 | } | |
905 | ||
906 | /* return value determine if we need a write buffer flush */ | |
4c25a2c1 DW |
907 | static void __iommu_flush_context(struct intel_iommu *iommu, |
908 | u16 did, u16 source_id, u8 function_mask, | |
909 | u64 type) | |
ba395927 KA |
910 | { |
911 | u64 val = 0; | |
912 | unsigned long flag; | |
913 | ||
ba395927 KA |
914 | switch (type) { |
915 | case DMA_CCMD_GLOBAL_INVL: | |
916 | val = DMA_CCMD_GLOBAL_INVL; | |
917 | break; | |
918 | case DMA_CCMD_DOMAIN_INVL: | |
919 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); | |
920 | break; | |
921 | case DMA_CCMD_DEVICE_INVL: | |
922 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) | |
923 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); | |
924 | break; | |
925 | default: | |
926 | BUG(); | |
927 | } | |
928 | val |= DMA_CCMD_ICC; | |
929 | ||
930 | spin_lock_irqsave(&iommu->register_lock, flag); | |
931 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); | |
932 | ||
933 | /* Make sure hardware complete it */ | |
934 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, | |
935 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); | |
936 | ||
937 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
ba395927 KA |
938 | } |
939 | ||
ba395927 | 940 | /* return value determine if we need a write buffer flush */ |
1f0ef2aa DW |
941 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
942 | u64 addr, unsigned int size_order, u64 type) | |
ba395927 KA |
943 | { |
944 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); | |
945 | u64 val = 0, val_iva = 0; | |
946 | unsigned long flag; | |
947 | ||
ba395927 KA |
948 | switch (type) { |
949 | case DMA_TLB_GLOBAL_FLUSH: | |
950 | /* global flush doesn't need set IVA_REG */ | |
951 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; | |
952 | break; | |
953 | case DMA_TLB_DSI_FLUSH: | |
954 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
955 | break; | |
956 | case DMA_TLB_PSI_FLUSH: | |
957 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
958 | /* Note: always flush non-leaf currently */ | |
959 | val_iva = size_order | addr; | |
960 | break; | |
961 | default: | |
962 | BUG(); | |
963 | } | |
964 | /* Note: set drain read/write */ | |
965 | #if 0 | |
966 | /* | |
967 | * This is probably to be super secure.. Looks like we can | |
968 | * ignore it without any impact. | |
969 | */ | |
970 | if (cap_read_drain(iommu->cap)) | |
971 | val |= DMA_TLB_READ_DRAIN; | |
972 | #endif | |
973 | if (cap_write_drain(iommu->cap)) | |
974 | val |= DMA_TLB_WRITE_DRAIN; | |
975 | ||
976 | spin_lock_irqsave(&iommu->register_lock, flag); | |
977 | /* Note: Only uses first TLB reg currently */ | |
978 | if (val_iva) | |
979 | dmar_writeq(iommu->reg + tlb_offset, val_iva); | |
980 | dmar_writeq(iommu->reg + tlb_offset + 8, val); | |
981 | ||
982 | /* Make sure hardware complete it */ | |
983 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, | |
984 | dmar_readq, (!(val & DMA_TLB_IVT)), val); | |
985 | ||
986 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
987 | ||
988 | /* check IOTLB invalidation granularity */ | |
989 | if (DMA_TLB_IAIG(val) == 0) | |
990 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); | |
991 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) | |
992 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", | |
5b6985ce FY |
993 | (unsigned long long)DMA_TLB_IIRG(type), |
994 | (unsigned long long)DMA_TLB_IAIG(val)); | |
ba395927 KA |
995 | } |
996 | ||
93a23a72 YZ |
997 | static struct device_domain_info *iommu_support_dev_iotlb( |
998 | struct dmar_domain *domain, int segment, u8 bus, u8 devfn) | |
999 | { | |
1000 | int found = 0; | |
1001 | unsigned long flags; | |
1002 | struct device_domain_info *info; | |
1003 | struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn); | |
1004 | ||
1005 | if (!ecap_dev_iotlb_support(iommu->ecap)) | |
1006 | return NULL; | |
1007 | ||
1008 | if (!iommu->qi) | |
1009 | return NULL; | |
1010 | ||
1011 | spin_lock_irqsave(&device_domain_lock, flags); | |
1012 | list_for_each_entry(info, &domain->devices, link) | |
1013 | if (info->bus == bus && info->devfn == devfn) { | |
1014 | found = 1; | |
1015 | break; | |
1016 | } | |
1017 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1018 | ||
1019 | if (!found || !info->dev) | |
1020 | return NULL; | |
1021 | ||
1022 | if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS)) | |
1023 | return NULL; | |
1024 | ||
1025 | if (!dmar_find_matched_atsr_unit(info->dev)) | |
1026 | return NULL; | |
1027 | ||
1028 | info->iommu = iommu; | |
1029 | ||
1030 | return info; | |
1031 | } | |
1032 | ||
1033 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) | |
ba395927 | 1034 | { |
93a23a72 YZ |
1035 | if (!info) |
1036 | return; | |
1037 | ||
1038 | pci_enable_ats(info->dev, VTD_PAGE_SHIFT); | |
1039 | } | |
1040 | ||
1041 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) | |
1042 | { | |
1043 | if (!info->dev || !pci_ats_enabled(info->dev)) | |
1044 | return; | |
1045 | ||
1046 | pci_disable_ats(info->dev); | |
1047 | } | |
1048 | ||
1049 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, | |
1050 | u64 addr, unsigned mask) | |
1051 | { | |
1052 | u16 sid, qdep; | |
1053 | unsigned long flags; | |
1054 | struct device_domain_info *info; | |
1055 | ||
1056 | spin_lock_irqsave(&device_domain_lock, flags); | |
1057 | list_for_each_entry(info, &domain->devices, link) { | |
1058 | if (!info->dev || !pci_ats_enabled(info->dev)) | |
1059 | continue; | |
1060 | ||
1061 | sid = info->bus << 8 | info->devfn; | |
1062 | qdep = pci_ats_queue_depth(info->dev); | |
1063 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); | |
1064 | } | |
1065 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1066 | } | |
1067 | ||
1f0ef2aa | 1068 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
03d6a246 | 1069 | unsigned long pfn, unsigned int pages) |
ba395927 | 1070 | { |
9dd2fe89 | 1071 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
03d6a246 | 1072 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
ba395927 | 1073 | |
ba395927 KA |
1074 | BUG_ON(pages == 0); |
1075 | ||
ba395927 | 1076 | /* |
9dd2fe89 YZ |
1077 | * Fallback to domain selective flush if no PSI support or the size is |
1078 | * too big. | |
ba395927 KA |
1079 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
1080 | * aligned to the size | |
1081 | */ | |
9dd2fe89 YZ |
1082 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
1083 | iommu->flush.flush_iotlb(iommu, did, 0, 0, | |
1f0ef2aa | 1084 | DMA_TLB_DSI_FLUSH); |
9dd2fe89 YZ |
1085 | else |
1086 | iommu->flush.flush_iotlb(iommu, did, addr, mask, | |
1087 | DMA_TLB_PSI_FLUSH); | |
bf92df30 YZ |
1088 | |
1089 | /* | |
1090 | * In caching mode, domain ID 0 is reserved for non-present to present | |
1091 | * mapping flush. Device IOTLB doesn't need to be flushed in this case. | |
1092 | */ | |
1093 | if (!cap_caching_mode(iommu->cap) || did) | |
93a23a72 | 1094 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
ba395927 KA |
1095 | } |
1096 | ||
f8bab735 | 1097 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
1098 | { | |
1099 | u32 pmen; | |
1100 | unsigned long flags; | |
1101 | ||
1102 | spin_lock_irqsave(&iommu->register_lock, flags); | |
1103 | pmen = readl(iommu->reg + DMAR_PMEN_REG); | |
1104 | pmen &= ~DMA_PMEN_EPM; | |
1105 | writel(pmen, iommu->reg + DMAR_PMEN_REG); | |
1106 | ||
1107 | /* wait for the protected region status bit to clear */ | |
1108 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, | |
1109 | readl, !(pmen & DMA_PMEN_PRS), pmen); | |
1110 | ||
1111 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
1112 | } | |
1113 | ||
ba395927 KA |
1114 | static int iommu_enable_translation(struct intel_iommu *iommu) |
1115 | { | |
1116 | u32 sts; | |
1117 | unsigned long flags; | |
1118 | ||
1119 | spin_lock_irqsave(&iommu->register_lock, flags); | |
c416daa9 DW |
1120 | iommu->gcmd |= DMA_GCMD_TE; |
1121 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
ba395927 KA |
1122 | |
1123 | /* Make sure hardware complete it */ | |
1124 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1125 | readl, (sts & DMA_GSTS_TES), sts); |
ba395927 | 1126 | |
ba395927 KA |
1127 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
1128 | return 0; | |
1129 | } | |
1130 | ||
1131 | static int iommu_disable_translation(struct intel_iommu *iommu) | |
1132 | { | |
1133 | u32 sts; | |
1134 | unsigned long flag; | |
1135 | ||
1136 | spin_lock_irqsave(&iommu->register_lock, flag); | |
1137 | iommu->gcmd &= ~DMA_GCMD_TE; | |
1138 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
1139 | ||
1140 | /* Make sure hardware complete it */ | |
1141 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1142 | readl, (!(sts & DMA_GSTS_TES)), sts); |
ba395927 KA |
1143 | |
1144 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
1145 | return 0; | |
1146 | } | |
1147 | ||
3460a6d9 | 1148 | |
ba395927 KA |
1149 | static int iommu_init_domains(struct intel_iommu *iommu) |
1150 | { | |
1151 | unsigned long ndomains; | |
1152 | unsigned long nlongs; | |
1153 | ||
1154 | ndomains = cap_ndoms(iommu->cap); | |
1155 | pr_debug("Number of Domains supportd <%ld>\n", ndomains); | |
1156 | nlongs = BITS_TO_LONGS(ndomains); | |
1157 | ||
1158 | /* TBD: there might be 64K domains, | |
1159 | * consider other allocation for future chip | |
1160 | */ | |
1161 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); | |
1162 | if (!iommu->domain_ids) { | |
1163 | printk(KERN_ERR "Allocating domain id array failed\n"); | |
1164 | return -ENOMEM; | |
1165 | } | |
1166 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), | |
1167 | GFP_KERNEL); | |
1168 | if (!iommu->domains) { | |
1169 | printk(KERN_ERR "Allocating domain array failed\n"); | |
1170 | kfree(iommu->domain_ids); | |
1171 | return -ENOMEM; | |
1172 | } | |
1173 | ||
e61d98d8 SS |
1174 | spin_lock_init(&iommu->lock); |
1175 | ||
ba395927 KA |
1176 | /* |
1177 | * if Caching mode is set, then invalid translations are tagged | |
1178 | * with domainid 0. Hence we need to pre-allocate it. | |
1179 | */ | |
1180 | if (cap_caching_mode(iommu->cap)) | |
1181 | set_bit(0, iommu->domain_ids); | |
1182 | return 0; | |
1183 | } | |
ba395927 | 1184 | |
ba395927 KA |
1185 | |
1186 | static void domain_exit(struct dmar_domain *domain); | |
5e98c4b1 | 1187 | static void vm_domain_exit(struct dmar_domain *domain); |
e61d98d8 SS |
1188 | |
1189 | void free_dmar_iommu(struct intel_iommu *iommu) | |
ba395927 KA |
1190 | { |
1191 | struct dmar_domain *domain; | |
1192 | int i; | |
c7151a8d | 1193 | unsigned long flags; |
ba395927 | 1194 | |
ba395927 KA |
1195 | i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap)); |
1196 | for (; i < cap_ndoms(iommu->cap); ) { | |
1197 | domain = iommu->domains[i]; | |
1198 | clear_bit(i, iommu->domain_ids); | |
c7151a8d WH |
1199 | |
1200 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
5e98c4b1 WH |
1201 | if (--domain->iommu_count == 0) { |
1202 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) | |
1203 | vm_domain_exit(domain); | |
1204 | else | |
1205 | domain_exit(domain); | |
1206 | } | |
c7151a8d WH |
1207 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
1208 | ||
ba395927 KA |
1209 | i = find_next_bit(iommu->domain_ids, |
1210 | cap_ndoms(iommu->cap), i+1); | |
1211 | } | |
1212 | ||
1213 | if (iommu->gcmd & DMA_GCMD_TE) | |
1214 | iommu_disable_translation(iommu); | |
1215 | ||
1216 | if (iommu->irq) { | |
1217 | set_irq_data(iommu->irq, NULL); | |
1218 | /* This will mask the irq */ | |
1219 | free_irq(iommu->irq, iommu); | |
1220 | destroy_irq(iommu->irq); | |
1221 | } | |
1222 | ||
1223 | kfree(iommu->domains); | |
1224 | kfree(iommu->domain_ids); | |
1225 | ||
d9630fe9 WH |
1226 | g_iommus[iommu->seq_id] = NULL; |
1227 | ||
1228 | /* if all iommus are freed, free g_iommus */ | |
1229 | for (i = 0; i < g_num_of_iommus; i++) { | |
1230 | if (g_iommus[i]) | |
1231 | break; | |
1232 | } | |
1233 | ||
1234 | if (i == g_num_of_iommus) | |
1235 | kfree(g_iommus); | |
1236 | ||
ba395927 KA |
1237 | /* free context mapping */ |
1238 | free_context_table(iommu); | |
ba395927 KA |
1239 | } |
1240 | ||
2c2e2c38 | 1241 | static struct dmar_domain *alloc_domain(void) |
ba395927 | 1242 | { |
ba395927 | 1243 | struct dmar_domain *domain; |
ba395927 KA |
1244 | |
1245 | domain = alloc_domain_mem(); | |
1246 | if (!domain) | |
1247 | return NULL; | |
1248 | ||
2c2e2c38 FY |
1249 | memset(&domain->iommu_bmp, 0, sizeof(unsigned long)); |
1250 | domain->flags = 0; | |
1251 | ||
1252 | return domain; | |
1253 | } | |
1254 | ||
1255 | static int iommu_attach_domain(struct dmar_domain *domain, | |
1256 | struct intel_iommu *iommu) | |
1257 | { | |
1258 | int num; | |
1259 | unsigned long ndomains; | |
1260 | unsigned long flags; | |
1261 | ||
ba395927 KA |
1262 | ndomains = cap_ndoms(iommu->cap); |
1263 | ||
1264 | spin_lock_irqsave(&iommu->lock, flags); | |
2c2e2c38 | 1265 | |
ba395927 KA |
1266 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
1267 | if (num >= ndomains) { | |
1268 | spin_unlock_irqrestore(&iommu->lock, flags); | |
ba395927 | 1269 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
2c2e2c38 | 1270 | return -ENOMEM; |
ba395927 KA |
1271 | } |
1272 | ||
ba395927 | 1273 | domain->id = num; |
2c2e2c38 | 1274 | set_bit(num, iommu->domain_ids); |
8c11e798 | 1275 | set_bit(iommu->seq_id, &domain->iommu_bmp); |
ba395927 KA |
1276 | iommu->domains[num] = domain; |
1277 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1278 | ||
2c2e2c38 | 1279 | return 0; |
ba395927 KA |
1280 | } |
1281 | ||
2c2e2c38 FY |
1282 | static void iommu_detach_domain(struct dmar_domain *domain, |
1283 | struct intel_iommu *iommu) | |
ba395927 KA |
1284 | { |
1285 | unsigned long flags; | |
2c2e2c38 FY |
1286 | int num, ndomains; |
1287 | int found = 0; | |
ba395927 | 1288 | |
8c11e798 | 1289 | spin_lock_irqsave(&iommu->lock, flags); |
2c2e2c38 FY |
1290 | ndomains = cap_ndoms(iommu->cap); |
1291 | num = find_first_bit(iommu->domain_ids, ndomains); | |
1292 | for (; num < ndomains; ) { | |
1293 | if (iommu->domains[num] == domain) { | |
1294 | found = 1; | |
1295 | break; | |
1296 | } | |
1297 | num = find_next_bit(iommu->domain_ids, | |
1298 | cap_ndoms(iommu->cap), num+1); | |
1299 | } | |
1300 | ||
1301 | if (found) { | |
1302 | clear_bit(num, iommu->domain_ids); | |
1303 | clear_bit(iommu->seq_id, &domain->iommu_bmp); | |
1304 | iommu->domains[num] = NULL; | |
1305 | } | |
8c11e798 | 1306 | spin_unlock_irqrestore(&iommu->lock, flags); |
ba395927 KA |
1307 | } |
1308 | ||
1309 | static struct iova_domain reserved_iova_list; | |
8a443df4 MG |
1310 | static struct lock_class_key reserved_alloc_key; |
1311 | static struct lock_class_key reserved_rbtree_key; | |
ba395927 KA |
1312 | |
1313 | static void dmar_init_reserved_ranges(void) | |
1314 | { | |
1315 | struct pci_dev *pdev = NULL; | |
1316 | struct iova *iova; | |
1317 | int i; | |
ba395927 | 1318 | |
f661197e | 1319 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
ba395927 | 1320 | |
8a443df4 MG |
1321 | lockdep_set_class(&reserved_iova_list.iova_alloc_lock, |
1322 | &reserved_alloc_key); | |
1323 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, | |
1324 | &reserved_rbtree_key); | |
1325 | ||
ba395927 KA |
1326 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
1327 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), | |
1328 | IOVA_PFN(IOAPIC_RANGE_END)); | |
1329 | if (!iova) | |
1330 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); | |
1331 | ||
1332 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ | |
1333 | for_each_pci_dev(pdev) { | |
1334 | struct resource *r; | |
1335 | ||
1336 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1337 | r = &pdev->resource[i]; | |
1338 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) | |
1339 | continue; | |
1a4a4551 DW |
1340 | iova = reserve_iova(&reserved_iova_list, |
1341 | IOVA_PFN(r->start), | |
1342 | IOVA_PFN(r->end)); | |
ba395927 KA |
1343 | if (!iova) |
1344 | printk(KERN_ERR "Reserve iova failed\n"); | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | } | |
1349 | ||
1350 | static void domain_reserve_special_ranges(struct dmar_domain *domain) | |
1351 | { | |
1352 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); | |
1353 | } | |
1354 | ||
1355 | static inline int guestwidth_to_adjustwidth(int gaw) | |
1356 | { | |
1357 | int agaw; | |
1358 | int r = (gaw - 12) % 9; | |
1359 | ||
1360 | if (r == 0) | |
1361 | agaw = gaw; | |
1362 | else | |
1363 | agaw = gaw + 9 - r; | |
1364 | if (agaw > 64) | |
1365 | agaw = 64; | |
1366 | return agaw; | |
1367 | } | |
1368 | ||
1369 | static int domain_init(struct dmar_domain *domain, int guest_width) | |
1370 | { | |
1371 | struct intel_iommu *iommu; | |
1372 | int adjust_width, agaw; | |
1373 | unsigned long sagaw; | |
1374 | ||
f661197e | 1375 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
c7151a8d | 1376 | spin_lock_init(&domain->iommu_lock); |
ba395927 KA |
1377 | |
1378 | domain_reserve_special_ranges(domain); | |
1379 | ||
1380 | /* calculate AGAW */ | |
8c11e798 | 1381 | iommu = domain_get_iommu(domain); |
ba395927 KA |
1382 | if (guest_width > cap_mgaw(iommu->cap)) |
1383 | guest_width = cap_mgaw(iommu->cap); | |
1384 | domain->gaw = guest_width; | |
1385 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
1386 | agaw = width_to_agaw(adjust_width); | |
1387 | sagaw = cap_sagaw(iommu->cap); | |
1388 | if (!test_bit(agaw, &sagaw)) { | |
1389 | /* hardware doesn't support it, choose a bigger one */ | |
1390 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); | |
1391 | agaw = find_next_bit(&sagaw, 5, agaw); | |
1392 | if (agaw >= 5) | |
1393 | return -ENODEV; | |
1394 | } | |
1395 | domain->agaw = agaw; | |
1396 | INIT_LIST_HEAD(&domain->devices); | |
1397 | ||
8e604097 WH |
1398 | if (ecap_coherent(iommu->ecap)) |
1399 | domain->iommu_coherency = 1; | |
1400 | else | |
1401 | domain->iommu_coherency = 0; | |
1402 | ||
58c610bd SY |
1403 | if (ecap_sc_support(iommu->ecap)) |
1404 | domain->iommu_snooping = 1; | |
1405 | else | |
1406 | domain->iommu_snooping = 0; | |
1407 | ||
c7151a8d WH |
1408 | domain->iommu_count = 1; |
1409 | ||
ba395927 KA |
1410 | /* always allocate the top pgd */ |
1411 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(); | |
1412 | if (!domain->pgd) | |
1413 | return -ENOMEM; | |
5b6985ce | 1414 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
ba395927 KA |
1415 | return 0; |
1416 | } | |
1417 | ||
1418 | static void domain_exit(struct dmar_domain *domain) | |
1419 | { | |
2c2e2c38 FY |
1420 | struct dmar_drhd_unit *drhd; |
1421 | struct intel_iommu *iommu; | |
ba395927 KA |
1422 | |
1423 | /* Domain 0 is reserved, so dont process it */ | |
1424 | if (!domain) | |
1425 | return; | |
1426 | ||
1427 | domain_remove_dev_info(domain); | |
1428 | /* destroy iovas */ | |
1429 | put_iova_domain(&domain->iovad); | |
ba395927 KA |
1430 | |
1431 | /* clear ptes */ | |
595badf5 | 1432 | dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 KA |
1433 | |
1434 | /* free page tables */ | |
d794dc9b | 1435 | dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 | 1436 | |
2c2e2c38 FY |
1437 | for_each_active_iommu(iommu, drhd) |
1438 | if (test_bit(iommu->seq_id, &domain->iommu_bmp)) | |
1439 | iommu_detach_domain(domain, iommu); | |
1440 | ||
ba395927 KA |
1441 | free_domain_mem(domain); |
1442 | } | |
1443 | ||
4ed0d3e6 FY |
1444 | static int domain_context_mapping_one(struct dmar_domain *domain, int segment, |
1445 | u8 bus, u8 devfn, int translation) | |
ba395927 KA |
1446 | { |
1447 | struct context_entry *context; | |
ba395927 | 1448 | unsigned long flags; |
5331fe6f | 1449 | struct intel_iommu *iommu; |
ea6606b0 WH |
1450 | struct dma_pte *pgd; |
1451 | unsigned long num; | |
1452 | unsigned long ndomains; | |
1453 | int id; | |
1454 | int agaw; | |
93a23a72 | 1455 | struct device_domain_info *info = NULL; |
ba395927 KA |
1456 | |
1457 | pr_debug("Set context mapping for %02x:%02x.%d\n", | |
1458 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
4ed0d3e6 | 1459 | |
ba395927 | 1460 | BUG_ON(!domain->pgd); |
4ed0d3e6 FY |
1461 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
1462 | translation != CONTEXT_TT_MULTI_LEVEL); | |
5331fe6f | 1463 | |
276dbf99 | 1464 | iommu = device_to_iommu(segment, bus, devfn); |
5331fe6f WH |
1465 | if (!iommu) |
1466 | return -ENODEV; | |
1467 | ||
ba395927 KA |
1468 | context = device_to_context_entry(iommu, bus, devfn); |
1469 | if (!context) | |
1470 | return -ENOMEM; | |
1471 | spin_lock_irqsave(&iommu->lock, flags); | |
c07e7d21 | 1472 | if (context_present(context)) { |
ba395927 KA |
1473 | spin_unlock_irqrestore(&iommu->lock, flags); |
1474 | return 0; | |
1475 | } | |
1476 | ||
ea6606b0 WH |
1477 | id = domain->id; |
1478 | pgd = domain->pgd; | |
1479 | ||
2c2e2c38 FY |
1480 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
1481 | domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) { | |
ea6606b0 WH |
1482 | int found = 0; |
1483 | ||
1484 | /* find an available domain id for this device in iommu */ | |
1485 | ndomains = cap_ndoms(iommu->cap); | |
1486 | num = find_first_bit(iommu->domain_ids, ndomains); | |
1487 | for (; num < ndomains; ) { | |
1488 | if (iommu->domains[num] == domain) { | |
1489 | id = num; | |
1490 | found = 1; | |
1491 | break; | |
1492 | } | |
1493 | num = find_next_bit(iommu->domain_ids, | |
1494 | cap_ndoms(iommu->cap), num+1); | |
1495 | } | |
1496 | ||
1497 | if (found == 0) { | |
1498 | num = find_first_zero_bit(iommu->domain_ids, ndomains); | |
1499 | if (num >= ndomains) { | |
1500 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1501 | printk(KERN_ERR "IOMMU: no free domain ids\n"); | |
1502 | return -EFAULT; | |
1503 | } | |
1504 | ||
1505 | set_bit(num, iommu->domain_ids); | |
2c2e2c38 | 1506 | set_bit(iommu->seq_id, &domain->iommu_bmp); |
ea6606b0 WH |
1507 | iommu->domains[num] = domain; |
1508 | id = num; | |
1509 | } | |
1510 | ||
1511 | /* Skip top levels of page tables for | |
1512 | * iommu which has less agaw than default. | |
1513 | */ | |
1514 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { | |
1515 | pgd = phys_to_virt(dma_pte_addr(pgd)); | |
1516 | if (!dma_pte_present(pgd)) { | |
1517 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1518 | return -ENOMEM; | |
1519 | } | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | context_set_domain_id(context, id); | |
4ed0d3e6 | 1524 | |
93a23a72 YZ |
1525 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
1526 | info = iommu_support_dev_iotlb(domain, segment, bus, devfn); | |
1527 | translation = info ? CONTEXT_TT_DEV_IOTLB : | |
1528 | CONTEXT_TT_MULTI_LEVEL; | |
1529 | } | |
4ed0d3e6 FY |
1530 | /* |
1531 | * In pass through mode, AW must be programmed to indicate the largest | |
1532 | * AGAW value supported by hardware. And ASR is ignored by hardware. | |
1533 | */ | |
93a23a72 | 1534 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
4ed0d3e6 | 1535 | context_set_address_width(context, iommu->msagaw); |
93a23a72 YZ |
1536 | else { |
1537 | context_set_address_root(context, virt_to_phys(pgd)); | |
1538 | context_set_address_width(context, iommu->agaw); | |
1539 | } | |
4ed0d3e6 FY |
1540 | |
1541 | context_set_translation_type(context, translation); | |
c07e7d21 MM |
1542 | context_set_fault_enable(context); |
1543 | context_set_present(context); | |
5331fe6f | 1544 | domain_flush_cache(domain, context, sizeof(*context)); |
ba395927 | 1545 | |
4c25a2c1 DW |
1546 | /* |
1547 | * It's a non-present to present mapping. If hardware doesn't cache | |
1548 | * non-present entry we only need to flush the write-buffer. If the | |
1549 | * _does_ cache non-present entries, then it does so in the special | |
1550 | * domain #0, which we have to flush: | |
1551 | */ | |
1552 | if (cap_caching_mode(iommu->cap)) { | |
1553 | iommu->flush.flush_context(iommu, 0, | |
1554 | (((u16)bus) << 8) | devfn, | |
1555 | DMA_CCMD_MASK_NOBIT, | |
1556 | DMA_CCMD_DEVICE_INVL); | |
1f0ef2aa | 1557 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH); |
4c25a2c1 | 1558 | } else { |
ba395927 | 1559 | iommu_flush_write_buffer(iommu); |
4c25a2c1 | 1560 | } |
93a23a72 | 1561 | iommu_enable_dev_iotlb(info); |
ba395927 | 1562 | spin_unlock_irqrestore(&iommu->lock, flags); |
c7151a8d WH |
1563 | |
1564 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
1565 | if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) { | |
1566 | domain->iommu_count++; | |
58c610bd | 1567 | domain_update_iommu_cap(domain); |
c7151a8d WH |
1568 | } |
1569 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
ba395927 KA |
1570 | return 0; |
1571 | } | |
1572 | ||
1573 | static int | |
4ed0d3e6 FY |
1574 | domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev, |
1575 | int translation) | |
ba395927 KA |
1576 | { |
1577 | int ret; | |
1578 | struct pci_dev *tmp, *parent; | |
1579 | ||
276dbf99 | 1580 | ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus), |
4ed0d3e6 FY |
1581 | pdev->bus->number, pdev->devfn, |
1582 | translation); | |
ba395927 KA |
1583 | if (ret) |
1584 | return ret; | |
1585 | ||
1586 | /* dependent device mapping */ | |
1587 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
1588 | if (!tmp) | |
1589 | return 0; | |
1590 | /* Secondary interface's bus number and devfn 0 */ | |
1591 | parent = pdev->bus->self; | |
1592 | while (parent != tmp) { | |
276dbf99 DW |
1593 | ret = domain_context_mapping_one(domain, |
1594 | pci_domain_nr(parent->bus), | |
1595 | parent->bus->number, | |
4ed0d3e6 | 1596 | parent->devfn, translation); |
ba395927 KA |
1597 | if (ret) |
1598 | return ret; | |
1599 | parent = parent->bus->self; | |
1600 | } | |
1601 | if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */ | |
1602 | return domain_context_mapping_one(domain, | |
276dbf99 | 1603 | pci_domain_nr(tmp->subordinate), |
4ed0d3e6 FY |
1604 | tmp->subordinate->number, 0, |
1605 | translation); | |
ba395927 KA |
1606 | else /* this is a legacy PCI bridge */ |
1607 | return domain_context_mapping_one(domain, | |
276dbf99 DW |
1608 | pci_domain_nr(tmp->bus), |
1609 | tmp->bus->number, | |
4ed0d3e6 FY |
1610 | tmp->devfn, |
1611 | translation); | |
ba395927 KA |
1612 | } |
1613 | ||
5331fe6f | 1614 | static int domain_context_mapped(struct pci_dev *pdev) |
ba395927 KA |
1615 | { |
1616 | int ret; | |
1617 | struct pci_dev *tmp, *parent; | |
5331fe6f WH |
1618 | struct intel_iommu *iommu; |
1619 | ||
276dbf99 DW |
1620 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
1621 | pdev->devfn); | |
5331fe6f WH |
1622 | if (!iommu) |
1623 | return -ENODEV; | |
ba395927 | 1624 | |
276dbf99 | 1625 | ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn); |
ba395927 KA |
1626 | if (!ret) |
1627 | return ret; | |
1628 | /* dependent device mapping */ | |
1629 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
1630 | if (!tmp) | |
1631 | return ret; | |
1632 | /* Secondary interface's bus number and devfn 0 */ | |
1633 | parent = pdev->bus->self; | |
1634 | while (parent != tmp) { | |
8c11e798 | 1635 | ret = device_context_mapped(iommu, parent->bus->number, |
276dbf99 | 1636 | parent->devfn); |
ba395927 KA |
1637 | if (!ret) |
1638 | return ret; | |
1639 | parent = parent->bus->self; | |
1640 | } | |
1641 | if (tmp->is_pcie) | |
276dbf99 DW |
1642 | return device_context_mapped(iommu, tmp->subordinate->number, |
1643 | 0); | |
ba395927 | 1644 | else |
276dbf99 DW |
1645 | return device_context_mapped(iommu, tmp->bus->number, |
1646 | tmp->devfn); | |
ba395927 KA |
1647 | } |
1648 | ||
9051aa02 DW |
1649 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1650 | struct scatterlist *sg, unsigned long phys_pfn, | |
1651 | unsigned long nr_pages, int prot) | |
e1605495 DW |
1652 | { |
1653 | struct dma_pte *first_pte = NULL, *pte = NULL; | |
9051aa02 | 1654 | phys_addr_t uninitialized_var(pteval); |
e1605495 | 1655 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
9051aa02 | 1656 | unsigned long sg_res; |
e1605495 DW |
1657 | |
1658 | BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width); | |
1659 | ||
1660 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | |
1661 | return -EINVAL; | |
1662 | ||
1663 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; | |
1664 | ||
9051aa02 DW |
1665 | if (sg) |
1666 | sg_res = 0; | |
1667 | else { | |
1668 | sg_res = nr_pages + 1; | |
1669 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; | |
1670 | } | |
1671 | ||
e1605495 | 1672 | while (nr_pages--) { |
c85994e4 DW |
1673 | uint64_t tmp; |
1674 | ||
e1605495 DW |
1675 | if (!sg_res) { |
1676 | sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT; | |
1677 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; | |
1678 | sg->dma_length = sg->length; | |
1679 | pteval = page_to_phys(sg_page(sg)) | prot; | |
1680 | } | |
1681 | if (!pte) { | |
1682 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn); | |
1683 | if (!pte) | |
1684 | return -ENOMEM; | |
1685 | } | |
1686 | /* We don't need lock here, nobody else | |
1687 | * touches the iova range | |
1688 | */ | |
7766a3fb | 1689 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
c85994e4 | 1690 | if (tmp) { |
1bf20f0d | 1691 | static int dumps = 5; |
c85994e4 DW |
1692 | printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
1693 | iov_pfn, tmp, (unsigned long long)pteval); | |
1bf20f0d DW |
1694 | if (dumps) { |
1695 | dumps--; | |
1696 | debug_dma_dump_mappings(NULL); | |
1697 | } | |
1698 | WARN_ON(1); | |
1699 | } | |
e1605495 | 1700 | pte++; |
75e6bf96 | 1701 | if (!nr_pages || first_pte_in_page(pte)) { |
e1605495 DW |
1702 | domain_flush_cache(domain, first_pte, |
1703 | (void *)pte - (void *)first_pte); | |
1704 | pte = NULL; | |
1705 | } | |
1706 | iov_pfn++; | |
1707 | pteval += VTD_PAGE_SIZE; | |
1708 | sg_res--; | |
1709 | if (!sg_res) | |
1710 | sg = sg_next(sg); | |
1711 | } | |
1712 | return 0; | |
1713 | } | |
1714 | ||
9051aa02 DW |
1715 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1716 | struct scatterlist *sg, unsigned long nr_pages, | |
1717 | int prot) | |
ba395927 | 1718 | { |
9051aa02 DW |
1719 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
1720 | } | |
6f6a00e4 | 1721 | |
9051aa02 DW |
1722 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1723 | unsigned long phys_pfn, unsigned long nr_pages, | |
1724 | int prot) | |
1725 | { | |
1726 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); | |
ba395927 KA |
1727 | } |
1728 | ||
c7151a8d | 1729 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
ba395927 | 1730 | { |
c7151a8d WH |
1731 | if (!iommu) |
1732 | return; | |
8c11e798 WH |
1733 | |
1734 | clear_context_table(iommu, bus, devfn); | |
1735 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
4c25a2c1 | 1736 | DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 1737 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
ba395927 KA |
1738 | } |
1739 | ||
1740 | static void domain_remove_dev_info(struct dmar_domain *domain) | |
1741 | { | |
1742 | struct device_domain_info *info; | |
1743 | unsigned long flags; | |
c7151a8d | 1744 | struct intel_iommu *iommu; |
ba395927 KA |
1745 | |
1746 | spin_lock_irqsave(&device_domain_lock, flags); | |
1747 | while (!list_empty(&domain->devices)) { | |
1748 | info = list_entry(domain->devices.next, | |
1749 | struct device_domain_info, link); | |
1750 | list_del(&info->link); | |
1751 | list_del(&info->global); | |
1752 | if (info->dev) | |
358dd8ac | 1753 | info->dev->dev.archdata.iommu = NULL; |
ba395927 KA |
1754 | spin_unlock_irqrestore(&device_domain_lock, flags); |
1755 | ||
93a23a72 | 1756 | iommu_disable_dev_iotlb(info); |
276dbf99 | 1757 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
c7151a8d | 1758 | iommu_detach_dev(iommu, info->bus, info->devfn); |
ba395927 KA |
1759 | free_devinfo_mem(info); |
1760 | ||
1761 | spin_lock_irqsave(&device_domain_lock, flags); | |
1762 | } | |
1763 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1764 | } | |
1765 | ||
1766 | /* | |
1767 | * find_domain | |
358dd8ac | 1768 | * Note: we use struct pci_dev->dev.archdata.iommu stores the info |
ba395927 | 1769 | */ |
38717946 | 1770 | static struct dmar_domain * |
ba395927 KA |
1771 | find_domain(struct pci_dev *pdev) |
1772 | { | |
1773 | struct device_domain_info *info; | |
1774 | ||
1775 | /* No lock here, assumes no domain exit in normal case */ | |
358dd8ac | 1776 | info = pdev->dev.archdata.iommu; |
ba395927 KA |
1777 | if (info) |
1778 | return info->domain; | |
1779 | return NULL; | |
1780 | } | |
1781 | ||
ba395927 KA |
1782 | /* domain is initialized */ |
1783 | static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw) | |
1784 | { | |
1785 | struct dmar_domain *domain, *found = NULL; | |
1786 | struct intel_iommu *iommu; | |
1787 | struct dmar_drhd_unit *drhd; | |
1788 | struct device_domain_info *info, *tmp; | |
1789 | struct pci_dev *dev_tmp; | |
1790 | unsigned long flags; | |
1791 | int bus = 0, devfn = 0; | |
276dbf99 | 1792 | int segment; |
2c2e2c38 | 1793 | int ret; |
ba395927 KA |
1794 | |
1795 | domain = find_domain(pdev); | |
1796 | if (domain) | |
1797 | return domain; | |
1798 | ||
276dbf99 DW |
1799 | segment = pci_domain_nr(pdev->bus); |
1800 | ||
ba395927 KA |
1801 | dev_tmp = pci_find_upstream_pcie_bridge(pdev); |
1802 | if (dev_tmp) { | |
1803 | if (dev_tmp->is_pcie) { | |
1804 | bus = dev_tmp->subordinate->number; | |
1805 | devfn = 0; | |
1806 | } else { | |
1807 | bus = dev_tmp->bus->number; | |
1808 | devfn = dev_tmp->devfn; | |
1809 | } | |
1810 | spin_lock_irqsave(&device_domain_lock, flags); | |
1811 | list_for_each_entry(info, &device_domain_list, global) { | |
276dbf99 DW |
1812 | if (info->segment == segment && |
1813 | info->bus == bus && info->devfn == devfn) { | |
ba395927 KA |
1814 | found = info->domain; |
1815 | break; | |
1816 | } | |
1817 | } | |
1818 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1819 | /* pcie-pci bridge already has a domain, uses it */ | |
1820 | if (found) { | |
1821 | domain = found; | |
1822 | goto found_domain; | |
1823 | } | |
1824 | } | |
1825 | ||
2c2e2c38 FY |
1826 | domain = alloc_domain(); |
1827 | if (!domain) | |
1828 | goto error; | |
1829 | ||
ba395927 KA |
1830 | /* Allocate new domain for the device */ |
1831 | drhd = dmar_find_matched_drhd_unit(pdev); | |
1832 | if (!drhd) { | |
1833 | printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n", | |
1834 | pci_name(pdev)); | |
1835 | return NULL; | |
1836 | } | |
1837 | iommu = drhd->iommu; | |
1838 | ||
2c2e2c38 FY |
1839 | ret = iommu_attach_domain(domain, iommu); |
1840 | if (ret) { | |
1841 | domain_exit(domain); | |
ba395927 | 1842 | goto error; |
2c2e2c38 | 1843 | } |
ba395927 KA |
1844 | |
1845 | if (domain_init(domain, gaw)) { | |
1846 | domain_exit(domain); | |
1847 | goto error; | |
1848 | } | |
1849 | ||
1850 | /* register pcie-to-pci device */ | |
1851 | if (dev_tmp) { | |
1852 | info = alloc_devinfo_mem(); | |
1853 | if (!info) { | |
1854 | domain_exit(domain); | |
1855 | goto error; | |
1856 | } | |
276dbf99 | 1857 | info->segment = segment; |
ba395927 KA |
1858 | info->bus = bus; |
1859 | info->devfn = devfn; | |
1860 | info->dev = NULL; | |
1861 | info->domain = domain; | |
1862 | /* This domain is shared by devices under p2p bridge */ | |
3b5410e7 | 1863 | domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES; |
ba395927 KA |
1864 | |
1865 | /* pcie-to-pci bridge already has a domain, uses it */ | |
1866 | found = NULL; | |
1867 | spin_lock_irqsave(&device_domain_lock, flags); | |
1868 | list_for_each_entry(tmp, &device_domain_list, global) { | |
276dbf99 DW |
1869 | if (tmp->segment == segment && |
1870 | tmp->bus == bus && tmp->devfn == devfn) { | |
ba395927 KA |
1871 | found = tmp->domain; |
1872 | break; | |
1873 | } | |
1874 | } | |
1875 | if (found) { | |
1876 | free_devinfo_mem(info); | |
1877 | domain_exit(domain); | |
1878 | domain = found; | |
1879 | } else { | |
1880 | list_add(&info->link, &domain->devices); | |
1881 | list_add(&info->global, &device_domain_list); | |
1882 | } | |
1883 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1884 | } | |
1885 | ||
1886 | found_domain: | |
1887 | info = alloc_devinfo_mem(); | |
1888 | if (!info) | |
1889 | goto error; | |
276dbf99 | 1890 | info->segment = segment; |
ba395927 KA |
1891 | info->bus = pdev->bus->number; |
1892 | info->devfn = pdev->devfn; | |
1893 | info->dev = pdev; | |
1894 | info->domain = domain; | |
1895 | spin_lock_irqsave(&device_domain_lock, flags); | |
1896 | /* somebody is fast */ | |
1897 | found = find_domain(pdev); | |
1898 | if (found != NULL) { | |
1899 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1900 | if (found != domain) { | |
1901 | domain_exit(domain); | |
1902 | domain = found; | |
1903 | } | |
1904 | free_devinfo_mem(info); | |
1905 | return domain; | |
1906 | } | |
1907 | list_add(&info->link, &domain->devices); | |
1908 | list_add(&info->global, &device_domain_list); | |
358dd8ac | 1909 | pdev->dev.archdata.iommu = info; |
ba395927 KA |
1910 | spin_unlock_irqrestore(&device_domain_lock, flags); |
1911 | return domain; | |
1912 | error: | |
1913 | /* recheck it here, maybe others set it */ | |
1914 | return find_domain(pdev); | |
1915 | } | |
1916 | ||
2c2e2c38 FY |
1917 | static int iommu_identity_mapping; |
1918 | ||
b213203e DW |
1919 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
1920 | unsigned long long start, | |
1921 | unsigned long long end) | |
ba395927 | 1922 | { |
c5395d5c DW |
1923 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
1924 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; | |
1925 | ||
1926 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), | |
1927 | dma_to_mm_pfn(last_vpfn))) { | |
ba395927 | 1928 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); |
b213203e | 1929 | return -ENOMEM; |
ba395927 KA |
1930 | } |
1931 | ||
c5395d5c DW |
1932 | pr_debug("Mapping reserved region %llx-%llx for domain %d\n", |
1933 | start, end, domain->id); | |
ba395927 KA |
1934 | /* |
1935 | * RMRR range might have overlap with physical memory range, | |
1936 | * clear it first | |
1937 | */ | |
c5395d5c | 1938 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
ba395927 | 1939 | |
c5395d5c DW |
1940 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
1941 | last_vpfn - first_vpfn + 1, | |
61df7443 | 1942 | DMA_PTE_READ|DMA_PTE_WRITE); |
b213203e DW |
1943 | } |
1944 | ||
1945 | static int iommu_prepare_identity_map(struct pci_dev *pdev, | |
1946 | unsigned long long start, | |
1947 | unsigned long long end) | |
1948 | { | |
1949 | struct dmar_domain *domain; | |
1950 | int ret; | |
1951 | ||
1952 | printk(KERN_INFO | |
1953 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", | |
1954 | pci_name(pdev), start, end); | |
1955 | ||
c7ab48d2 | 1956 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
b213203e DW |
1957 | if (!domain) |
1958 | return -ENOMEM; | |
1959 | ||
1960 | ret = iommu_domain_identity_map(domain, start, end); | |
ba395927 KA |
1961 | if (ret) |
1962 | goto error; | |
1963 | ||
1964 | /* context entry init */ | |
4ed0d3e6 | 1965 | ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
b213203e DW |
1966 | if (ret) |
1967 | goto error; | |
1968 | ||
1969 | return 0; | |
1970 | ||
1971 | error: | |
ba395927 KA |
1972 | domain_exit(domain); |
1973 | return ret; | |
ba395927 KA |
1974 | } |
1975 | ||
1976 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, | |
1977 | struct pci_dev *pdev) | |
1978 | { | |
358dd8ac | 1979 | if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
ba395927 KA |
1980 | return 0; |
1981 | return iommu_prepare_identity_map(pdev, rmrr->base_address, | |
1982 | rmrr->end_address + 1); | |
1983 | } | |
1984 | ||
49a0429e KA |
1985 | #ifdef CONFIG_DMAR_FLOPPY_WA |
1986 | static inline void iommu_prepare_isa(void) | |
1987 | { | |
1988 | struct pci_dev *pdev; | |
1989 | int ret; | |
1990 | ||
1991 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
1992 | if (!pdev) | |
1993 | return; | |
1994 | ||
c7ab48d2 | 1995 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
49a0429e KA |
1996 | ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024); |
1997 | ||
1998 | if (ret) | |
c7ab48d2 DW |
1999 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
2000 | "floppy might not work\n"); | |
49a0429e KA |
2001 | |
2002 | } | |
2003 | #else | |
2004 | static inline void iommu_prepare_isa(void) | |
2005 | { | |
2006 | return; | |
2007 | } | |
2008 | #endif /* !CONFIG_DMAR_FLPY_WA */ | |
2009 | ||
4ed0d3e6 FY |
2010 | /* Initialize each context entry as pass through.*/ |
2011 | static int __init init_context_pass_through(void) | |
2012 | { | |
2013 | struct pci_dev *pdev = NULL; | |
2014 | struct dmar_domain *domain; | |
2015 | int ret; | |
2016 | ||
2017 | for_each_pci_dev(pdev) { | |
2018 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
2019 | ret = domain_context_mapping(domain, pdev, | |
2020 | CONTEXT_TT_PASS_THROUGH); | |
2021 | if (ret) | |
2022 | return ret; | |
2023 | } | |
2024 | return 0; | |
2025 | } | |
2026 | ||
2c2e2c38 | 2027 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
c7ab48d2 DW |
2028 | |
2029 | static int __init si_domain_work_fn(unsigned long start_pfn, | |
2030 | unsigned long end_pfn, void *datax) | |
2031 | { | |
2032 | int *ret = datax; | |
2033 | ||
2034 | *ret = iommu_domain_identity_map(si_domain, | |
2035 | (uint64_t)start_pfn << PAGE_SHIFT, | |
2036 | (uint64_t)end_pfn << PAGE_SHIFT); | |
2037 | return *ret; | |
2038 | ||
2039 | } | |
2040 | ||
2c2e2c38 FY |
2041 | static int si_domain_init(void) |
2042 | { | |
2043 | struct dmar_drhd_unit *drhd; | |
2044 | struct intel_iommu *iommu; | |
c7ab48d2 | 2045 | int nid, ret = 0; |
2c2e2c38 FY |
2046 | |
2047 | si_domain = alloc_domain(); | |
2048 | if (!si_domain) | |
2049 | return -EFAULT; | |
2050 | ||
c7ab48d2 | 2051 | pr_debug("Identity mapping domain is domain %d\n", si_domain->id); |
2c2e2c38 FY |
2052 | |
2053 | for_each_active_iommu(iommu, drhd) { | |
2054 | ret = iommu_attach_domain(si_domain, iommu); | |
2055 | if (ret) { | |
2056 | domain_exit(si_domain); | |
2057 | return -EFAULT; | |
2058 | } | |
2059 | } | |
2060 | ||
2061 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { | |
2062 | domain_exit(si_domain); | |
2063 | return -EFAULT; | |
2064 | } | |
2065 | ||
2066 | si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY; | |
2067 | ||
c7ab48d2 DW |
2068 | for_each_online_node(nid) { |
2069 | work_with_active_regions(nid, si_domain_work_fn, &ret); | |
2070 | if (ret) | |
2071 | return ret; | |
2072 | } | |
2073 | ||
2c2e2c38 FY |
2074 | return 0; |
2075 | } | |
2076 | ||
2077 | static void domain_remove_one_dev_info(struct dmar_domain *domain, | |
2078 | struct pci_dev *pdev); | |
2079 | static int identity_mapping(struct pci_dev *pdev) | |
2080 | { | |
2081 | struct device_domain_info *info; | |
2082 | ||
2083 | if (likely(!iommu_identity_mapping)) | |
2084 | return 0; | |
2085 | ||
2086 | ||
2087 | list_for_each_entry(info, &si_domain->devices, link) | |
2088 | if (info->dev == pdev) | |
2089 | return 1; | |
2090 | return 0; | |
2091 | } | |
2092 | ||
2093 | static int domain_add_dev_info(struct dmar_domain *domain, | |
2094 | struct pci_dev *pdev) | |
2095 | { | |
2096 | struct device_domain_info *info; | |
2097 | unsigned long flags; | |
2098 | ||
2099 | info = alloc_devinfo_mem(); | |
2100 | if (!info) | |
2101 | return -ENOMEM; | |
2102 | ||
2103 | info->segment = pci_domain_nr(pdev->bus); | |
2104 | info->bus = pdev->bus->number; | |
2105 | info->devfn = pdev->devfn; | |
2106 | info->dev = pdev; | |
2107 | info->domain = domain; | |
2108 | ||
2109 | spin_lock_irqsave(&device_domain_lock, flags); | |
2110 | list_add(&info->link, &domain->devices); | |
2111 | list_add(&info->global, &device_domain_list); | |
2112 | pdev->dev.archdata.iommu = info; | |
2113 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2114 | ||
2115 | return 0; | |
2116 | } | |
2117 | ||
2118 | static int iommu_prepare_static_identity_mapping(void) | |
2119 | { | |
2c2e2c38 FY |
2120 | struct pci_dev *pdev = NULL; |
2121 | int ret; | |
2122 | ||
2123 | ret = si_domain_init(); | |
2124 | if (ret) | |
2125 | return -EFAULT; | |
2126 | ||
2c2e2c38 | 2127 | for_each_pci_dev(pdev) { |
c7ab48d2 DW |
2128 | printk(KERN_INFO "IOMMU: identity mapping for device %s\n", |
2129 | pci_name(pdev)); | |
2130 | ||
2131 | ret = domain_context_mapping(si_domain, pdev, | |
2132 | CONTEXT_TT_MULTI_LEVEL); | |
2133 | if (ret) | |
2134 | return ret; | |
2c2e2c38 FY |
2135 | ret = domain_add_dev_info(si_domain, pdev); |
2136 | if (ret) | |
2137 | return ret; | |
2138 | } | |
2139 | ||
2140 | return 0; | |
2141 | } | |
2142 | ||
2143 | int __init init_dmars(void) | |
ba395927 KA |
2144 | { |
2145 | struct dmar_drhd_unit *drhd; | |
2146 | struct dmar_rmrr_unit *rmrr; | |
2147 | struct pci_dev *pdev; | |
2148 | struct intel_iommu *iommu; | |
9d783ba0 | 2149 | int i, ret; |
4ed0d3e6 | 2150 | int pass_through = 1; |
ba395927 | 2151 | |
2c2e2c38 FY |
2152 | /* |
2153 | * In case pass through can not be enabled, iommu tries to use identity | |
2154 | * mapping. | |
2155 | */ | |
2156 | if (iommu_pass_through) | |
2157 | iommu_identity_mapping = 1; | |
2158 | ||
ba395927 KA |
2159 | /* |
2160 | * for each drhd | |
2161 | * allocate root | |
2162 | * initialize and program root entry to not present | |
2163 | * endfor | |
2164 | */ | |
2165 | for_each_drhd_unit(drhd) { | |
5e0d2a6f | 2166 | g_num_of_iommus++; |
2167 | /* | |
2168 | * lock not needed as this is only incremented in the single | |
2169 | * threaded kernel __init code path all other access are read | |
2170 | * only | |
2171 | */ | |
2172 | } | |
2173 | ||
d9630fe9 WH |
2174 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
2175 | GFP_KERNEL); | |
2176 | if (!g_iommus) { | |
2177 | printk(KERN_ERR "Allocating global iommu array failed\n"); | |
2178 | ret = -ENOMEM; | |
2179 | goto error; | |
2180 | } | |
2181 | ||
80b20dd8 | 2182 | deferred_flush = kzalloc(g_num_of_iommus * |
2183 | sizeof(struct deferred_flush_tables), GFP_KERNEL); | |
2184 | if (!deferred_flush) { | |
d9630fe9 | 2185 | kfree(g_iommus); |
5e0d2a6f | 2186 | ret = -ENOMEM; |
2187 | goto error; | |
2188 | } | |
2189 | ||
5e0d2a6f | 2190 | for_each_drhd_unit(drhd) { |
2191 | if (drhd->ignored) | |
2192 | continue; | |
1886e8a9 SS |
2193 | |
2194 | iommu = drhd->iommu; | |
d9630fe9 | 2195 | g_iommus[iommu->seq_id] = iommu; |
ba395927 | 2196 | |
e61d98d8 SS |
2197 | ret = iommu_init_domains(iommu); |
2198 | if (ret) | |
2199 | goto error; | |
2200 | ||
ba395927 KA |
2201 | /* |
2202 | * TBD: | |
2203 | * we could share the same root & context tables | |
2204 | * amoung all IOMMU's. Need to Split it later. | |
2205 | */ | |
2206 | ret = iommu_alloc_root_entry(iommu); | |
2207 | if (ret) { | |
2208 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); | |
2209 | goto error; | |
2210 | } | |
4ed0d3e6 FY |
2211 | if (!ecap_pass_through(iommu->ecap)) |
2212 | pass_through = 0; | |
ba395927 | 2213 | } |
4ed0d3e6 FY |
2214 | if (iommu_pass_through) |
2215 | if (!pass_through) { | |
2216 | printk(KERN_INFO | |
2217 | "Pass Through is not supported by hardware.\n"); | |
2218 | iommu_pass_through = 0; | |
2219 | } | |
ba395927 | 2220 | |
1531a6a6 SS |
2221 | /* |
2222 | * Start from the sane iommu hardware state. | |
2223 | */ | |
a77b67d4 YS |
2224 | for_each_drhd_unit(drhd) { |
2225 | if (drhd->ignored) | |
2226 | continue; | |
2227 | ||
2228 | iommu = drhd->iommu; | |
1531a6a6 SS |
2229 | |
2230 | /* | |
2231 | * If the queued invalidation is already initialized by us | |
2232 | * (for example, while enabling interrupt-remapping) then | |
2233 | * we got the things already rolling from a sane state. | |
2234 | */ | |
2235 | if (iommu->qi) | |
2236 | continue; | |
2237 | ||
2238 | /* | |
2239 | * Clear any previous faults. | |
2240 | */ | |
2241 | dmar_fault(-1, iommu); | |
2242 | /* | |
2243 | * Disable queued invalidation if supported and already enabled | |
2244 | * before OS handover. | |
2245 | */ | |
2246 | dmar_disable_qi(iommu); | |
2247 | } | |
2248 | ||
2249 | for_each_drhd_unit(drhd) { | |
2250 | if (drhd->ignored) | |
2251 | continue; | |
2252 | ||
2253 | iommu = drhd->iommu; | |
2254 | ||
a77b67d4 YS |
2255 | if (dmar_enable_qi(iommu)) { |
2256 | /* | |
2257 | * Queued Invalidate not enabled, use Register Based | |
2258 | * Invalidate | |
2259 | */ | |
2260 | iommu->flush.flush_context = __iommu_flush_context; | |
2261 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; | |
2262 | printk(KERN_INFO "IOMMU 0x%Lx: using Register based " | |
b4e0f9eb FT |
2263 | "invalidation\n", |
2264 | (unsigned long long)drhd->reg_base_addr); | |
a77b67d4 YS |
2265 | } else { |
2266 | iommu->flush.flush_context = qi_flush_context; | |
2267 | iommu->flush.flush_iotlb = qi_flush_iotlb; | |
2268 | printk(KERN_INFO "IOMMU 0x%Lx: using Queued " | |
b4e0f9eb FT |
2269 | "invalidation\n", |
2270 | (unsigned long long)drhd->reg_base_addr); | |
a77b67d4 YS |
2271 | } |
2272 | } | |
2273 | ||
ba395927 | 2274 | /* |
4ed0d3e6 FY |
2275 | * If pass through is set and enabled, context entries of all pci |
2276 | * devices are intialized by pass through translation type. | |
ba395927 | 2277 | */ |
4ed0d3e6 FY |
2278 | if (iommu_pass_through) { |
2279 | ret = init_context_pass_through(); | |
2280 | if (ret) { | |
2281 | printk(KERN_ERR "IOMMU: Pass through init failed.\n"); | |
2282 | iommu_pass_through = 0; | |
ba395927 KA |
2283 | } |
2284 | } | |
2285 | ||
ba395927 | 2286 | /* |
4ed0d3e6 | 2287 | * If pass through is not set or not enabled, setup context entries for |
2c2e2c38 FY |
2288 | * identity mappings for rmrr, gfx, and isa and may fall back to static |
2289 | * identity mapping if iommu_identity_mapping is set. | |
ba395927 | 2290 | */ |
4ed0d3e6 | 2291 | if (!iommu_pass_through) { |
2c2e2c38 FY |
2292 | if (iommu_identity_mapping) |
2293 | iommu_prepare_static_identity_mapping(); | |
4ed0d3e6 FY |
2294 | /* |
2295 | * For each rmrr | |
2296 | * for each dev attached to rmrr | |
2297 | * do | |
2298 | * locate drhd for dev, alloc domain for dev | |
2299 | * allocate free domain | |
2300 | * allocate page table entries for rmrr | |
2301 | * if context not allocated for bus | |
2302 | * allocate and init context | |
2303 | * set present in root table for this bus | |
2304 | * init context with domain, translation etc | |
2305 | * endfor | |
2306 | * endfor | |
2307 | */ | |
2c2e2c38 | 2308 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
4ed0d3e6 FY |
2309 | for_each_rmrr_units(rmrr) { |
2310 | for (i = 0; i < rmrr->devices_cnt; i++) { | |
2311 | pdev = rmrr->devices[i]; | |
2312 | /* | |
2313 | * some BIOS lists non-exist devices in DMAR | |
2314 | * table. | |
2315 | */ | |
2316 | if (!pdev) | |
2317 | continue; | |
2318 | ret = iommu_prepare_rmrr_dev(rmrr, pdev); | |
2319 | if (ret) | |
2320 | printk(KERN_ERR | |
ba395927 | 2321 | "IOMMU: mapping reserved region failed\n"); |
4ed0d3e6 | 2322 | } |
ba395927 | 2323 | } |
ba395927 | 2324 | |
4ed0d3e6 FY |
2325 | iommu_prepare_isa(); |
2326 | } | |
49a0429e | 2327 | |
ba395927 KA |
2328 | /* |
2329 | * for each drhd | |
2330 | * enable fault log | |
2331 | * global invalidate context cache | |
2332 | * global invalidate iotlb | |
2333 | * enable translation | |
2334 | */ | |
2335 | for_each_drhd_unit(drhd) { | |
2336 | if (drhd->ignored) | |
2337 | continue; | |
2338 | iommu = drhd->iommu; | |
ba395927 KA |
2339 | |
2340 | iommu_flush_write_buffer(iommu); | |
2341 | ||
3460a6d9 KA |
2342 | ret = dmar_set_interrupt(iommu); |
2343 | if (ret) | |
2344 | goto error; | |
2345 | ||
ba395927 KA |
2346 | iommu_set_root_entry(iommu); |
2347 | ||
4c25a2c1 | 2348 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2349 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
f8bab735 | 2350 | iommu_disable_protect_mem_regions(iommu); |
2351 | ||
ba395927 KA |
2352 | ret = iommu_enable_translation(iommu); |
2353 | if (ret) | |
2354 | goto error; | |
2355 | } | |
2356 | ||
2357 | return 0; | |
2358 | error: | |
2359 | for_each_drhd_unit(drhd) { | |
2360 | if (drhd->ignored) | |
2361 | continue; | |
2362 | iommu = drhd->iommu; | |
2363 | free_iommu(iommu); | |
2364 | } | |
d9630fe9 | 2365 | kfree(g_iommus); |
ba395927 KA |
2366 | return ret; |
2367 | } | |
2368 | ||
88cb6a74 DW |
2369 | static inline unsigned long aligned_nrpages(unsigned long host_addr, |
2370 | size_t size) | |
ba395927 | 2371 | { |
88cb6a74 DW |
2372 | host_addr &= ~PAGE_MASK; |
2373 | host_addr += size + PAGE_SIZE - 1; | |
2374 | ||
2375 | return host_addr >> VTD_PAGE_SHIFT; | |
ba395927 KA |
2376 | } |
2377 | ||
875764de DW |
2378 | static struct iova *intel_alloc_iova(struct device *dev, |
2379 | struct dmar_domain *domain, | |
2380 | unsigned long nrpages, uint64_t dma_mask) | |
ba395927 | 2381 | { |
ba395927 | 2382 | struct pci_dev *pdev = to_pci_dev(dev); |
ba395927 | 2383 | struct iova *iova = NULL; |
ba395927 | 2384 | |
875764de DW |
2385 | /* Restrict dma_mask to the width that the iommu can handle */ |
2386 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); | |
2387 | ||
2388 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { | |
ba395927 KA |
2389 | /* |
2390 | * First try to allocate an io virtual address in | |
284901a9 | 2391 | * DMA_BIT_MASK(32) and if that fails then try allocating |
3609801e | 2392 | * from higher range |
ba395927 | 2393 | */ |
875764de DW |
2394 | iova = alloc_iova(&domain->iovad, nrpages, |
2395 | IOVA_PFN(DMA_BIT_MASK(32)), 1); | |
2396 | if (iova) | |
2397 | return iova; | |
2398 | } | |
2399 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); | |
2400 | if (unlikely(!iova)) { | |
2401 | printk(KERN_ERR "Allocating %ld-page iova for %s failed", | |
2402 | nrpages, pci_name(pdev)); | |
f76aec76 KA |
2403 | return NULL; |
2404 | } | |
2405 | ||
2406 | return iova; | |
2407 | } | |
2408 | ||
2409 | static struct dmar_domain * | |
2410 | get_valid_domain_for_dev(struct pci_dev *pdev) | |
2411 | { | |
2412 | struct dmar_domain *domain; | |
2413 | int ret; | |
2414 | ||
2415 | domain = get_domain_for_dev(pdev, | |
2416 | DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
2417 | if (!domain) { | |
2418 | printk(KERN_ERR | |
2419 | "Allocating domain for %s failed", pci_name(pdev)); | |
4fe05bbc | 2420 | return NULL; |
ba395927 KA |
2421 | } |
2422 | ||
2423 | /* make sure context mapping is ok */ | |
5331fe6f | 2424 | if (unlikely(!domain_context_mapped(pdev))) { |
4ed0d3e6 FY |
2425 | ret = domain_context_mapping(domain, pdev, |
2426 | CONTEXT_TT_MULTI_LEVEL); | |
f76aec76 KA |
2427 | if (ret) { |
2428 | printk(KERN_ERR | |
2429 | "Domain context map for %s failed", | |
2430 | pci_name(pdev)); | |
4fe05bbc | 2431 | return NULL; |
f76aec76 | 2432 | } |
ba395927 KA |
2433 | } |
2434 | ||
f76aec76 KA |
2435 | return domain; |
2436 | } | |
2437 | ||
2c2e2c38 FY |
2438 | static int iommu_dummy(struct pci_dev *pdev) |
2439 | { | |
2440 | return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; | |
2441 | } | |
2442 | ||
2443 | /* Check if the pdev needs to go through non-identity map and unmap process.*/ | |
2444 | static int iommu_no_mapping(struct pci_dev *pdev) | |
2445 | { | |
2446 | int found; | |
2447 | ||
2448 | if (!iommu_identity_mapping) | |
2449 | return iommu_dummy(pdev); | |
2450 | ||
2451 | found = identity_mapping(pdev); | |
2452 | if (found) { | |
2453 | if (pdev->dma_mask > DMA_BIT_MASK(32)) | |
2454 | return 1; | |
2455 | else { | |
2456 | /* | |
2457 | * 32 bit DMA is removed from si_domain and fall back | |
2458 | * to non-identity mapping. | |
2459 | */ | |
2460 | domain_remove_one_dev_info(si_domain, pdev); | |
2461 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", | |
2462 | pci_name(pdev)); | |
2463 | return 0; | |
2464 | } | |
2465 | } else { | |
2466 | /* | |
2467 | * In case of a detached 64 bit DMA device from vm, the device | |
2468 | * is put into si_domain for identity mapping. | |
2469 | */ | |
2470 | if (pdev->dma_mask > DMA_BIT_MASK(32)) { | |
2471 | int ret; | |
2472 | ret = domain_add_dev_info(si_domain, pdev); | |
2473 | if (!ret) { | |
2474 | printk(KERN_INFO "64bit %s uses identity mapping\n", | |
2475 | pci_name(pdev)); | |
2476 | return 1; | |
2477 | } | |
2478 | } | |
2479 | } | |
2480 | ||
2481 | return iommu_dummy(pdev); | |
2482 | } | |
2483 | ||
bb9e6d65 FT |
2484 | static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr, |
2485 | size_t size, int dir, u64 dma_mask) | |
f76aec76 KA |
2486 | { |
2487 | struct pci_dev *pdev = to_pci_dev(hwdev); | |
f76aec76 | 2488 | struct dmar_domain *domain; |
5b6985ce | 2489 | phys_addr_t start_paddr; |
f76aec76 KA |
2490 | struct iova *iova; |
2491 | int prot = 0; | |
6865f0d1 | 2492 | int ret; |
8c11e798 | 2493 | struct intel_iommu *iommu; |
f76aec76 KA |
2494 | |
2495 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 FY |
2496 | |
2497 | if (iommu_no_mapping(pdev)) | |
6865f0d1 | 2498 | return paddr; |
f76aec76 KA |
2499 | |
2500 | domain = get_valid_domain_for_dev(pdev); | |
2501 | if (!domain) | |
2502 | return 0; | |
2503 | ||
8c11e798 | 2504 | iommu = domain_get_iommu(domain); |
88cb6a74 | 2505 | size = aligned_nrpages(paddr, size); |
f76aec76 | 2506 | |
875764de | 2507 | iova = intel_alloc_iova(hwdev, domain, size, pdev->dma_mask); |
f76aec76 KA |
2508 | if (!iova) |
2509 | goto error; | |
2510 | ||
ba395927 KA |
2511 | /* |
2512 | * Check if DMAR supports zero-length reads on write only | |
2513 | * mappings.. | |
2514 | */ | |
2515 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 2516 | !cap_zlr(iommu->cap)) |
ba395927 KA |
2517 | prot |= DMA_PTE_READ; |
2518 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
2519 | prot |= DMA_PTE_WRITE; | |
2520 | /* | |
6865f0d1 | 2521 | * paddr - (paddr + size) might be partial page, we should map the whole |
ba395927 | 2522 | * page. Note: if two part of one page are separately mapped, we |
6865f0d1 | 2523 | * might have two guest_addr mapping to the same host paddr, but this |
ba395927 KA |
2524 | * is not a big problem |
2525 | */ | |
0ab36de2 DW |
2526 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
2527 | paddr >> VTD_PAGE_SHIFT, size, prot); | |
ba395927 KA |
2528 | if (ret) |
2529 | goto error; | |
2530 | ||
1f0ef2aa DW |
2531 | /* it's a non-present to present mapping. Only flush if caching mode */ |
2532 | if (cap_caching_mode(iommu->cap)) | |
03d6a246 | 2533 | iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size); |
1f0ef2aa | 2534 | else |
8c11e798 | 2535 | iommu_flush_write_buffer(iommu); |
f76aec76 | 2536 | |
03d6a246 DW |
2537 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
2538 | start_paddr += paddr & ~PAGE_MASK; | |
2539 | return start_paddr; | |
ba395927 | 2540 | |
ba395927 | 2541 | error: |
f76aec76 KA |
2542 | if (iova) |
2543 | __free_iova(&domain->iovad, iova); | |
4cf2e75d | 2544 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
5b6985ce | 2545 | pci_name(pdev), size, (unsigned long long)paddr, dir); |
ba395927 KA |
2546 | return 0; |
2547 | } | |
2548 | ||
ffbbef5c FT |
2549 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
2550 | unsigned long offset, size_t size, | |
2551 | enum dma_data_direction dir, | |
2552 | struct dma_attrs *attrs) | |
bb9e6d65 | 2553 | { |
ffbbef5c FT |
2554 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
2555 | dir, to_pci_dev(dev)->dma_mask); | |
bb9e6d65 FT |
2556 | } |
2557 | ||
5e0d2a6f | 2558 | static void flush_unmaps(void) |
2559 | { | |
80b20dd8 | 2560 | int i, j; |
5e0d2a6f | 2561 | |
5e0d2a6f | 2562 | timer_on = 0; |
2563 | ||
2564 | /* just flush them all */ | |
2565 | for (i = 0; i < g_num_of_iommus; i++) { | |
a2bb8459 WH |
2566 | struct intel_iommu *iommu = g_iommus[i]; |
2567 | if (!iommu) | |
2568 | continue; | |
c42d9f32 | 2569 | |
9dd2fe89 YZ |
2570 | if (!deferred_flush[i].next) |
2571 | continue; | |
2572 | ||
2573 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, | |
93a23a72 | 2574 | DMA_TLB_GLOBAL_FLUSH); |
9dd2fe89 | 2575 | for (j = 0; j < deferred_flush[i].next; j++) { |
93a23a72 YZ |
2576 | unsigned long mask; |
2577 | struct iova *iova = deferred_flush[i].iova[j]; | |
2578 | ||
2579 | mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT; | |
2580 | mask = ilog2(mask >> VTD_PAGE_SHIFT); | |
2581 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], | |
2582 | iova->pfn_lo << PAGE_SHIFT, mask); | |
2583 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); | |
80b20dd8 | 2584 | } |
9dd2fe89 | 2585 | deferred_flush[i].next = 0; |
5e0d2a6f | 2586 | } |
2587 | ||
5e0d2a6f | 2588 | list_size = 0; |
5e0d2a6f | 2589 | } |
2590 | ||
2591 | static void flush_unmaps_timeout(unsigned long data) | |
2592 | { | |
80b20dd8 | 2593 | unsigned long flags; |
2594 | ||
2595 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
5e0d2a6f | 2596 | flush_unmaps(); |
80b20dd8 | 2597 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
5e0d2a6f | 2598 | } |
2599 | ||
2600 | static void add_unmap(struct dmar_domain *dom, struct iova *iova) | |
2601 | { | |
2602 | unsigned long flags; | |
80b20dd8 | 2603 | int next, iommu_id; |
8c11e798 | 2604 | struct intel_iommu *iommu; |
5e0d2a6f | 2605 | |
2606 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
80b20dd8 | 2607 | if (list_size == HIGH_WATER_MARK) |
2608 | flush_unmaps(); | |
2609 | ||
8c11e798 WH |
2610 | iommu = domain_get_iommu(dom); |
2611 | iommu_id = iommu->seq_id; | |
c42d9f32 | 2612 | |
80b20dd8 | 2613 | next = deferred_flush[iommu_id].next; |
2614 | deferred_flush[iommu_id].domain[next] = dom; | |
2615 | deferred_flush[iommu_id].iova[next] = iova; | |
2616 | deferred_flush[iommu_id].next++; | |
5e0d2a6f | 2617 | |
2618 | if (!timer_on) { | |
2619 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); | |
2620 | timer_on = 1; | |
2621 | } | |
2622 | list_size++; | |
2623 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); | |
2624 | } | |
2625 | ||
ffbbef5c FT |
2626 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
2627 | size_t size, enum dma_data_direction dir, | |
2628 | struct dma_attrs *attrs) | |
ba395927 | 2629 | { |
ba395927 | 2630 | struct pci_dev *pdev = to_pci_dev(dev); |
f76aec76 | 2631 | struct dmar_domain *domain; |
d794dc9b | 2632 | unsigned long start_pfn, last_pfn; |
ba395927 | 2633 | struct iova *iova; |
8c11e798 | 2634 | struct intel_iommu *iommu; |
ba395927 | 2635 | |
2c2e2c38 | 2636 | if (iommu_no_mapping(pdev)) |
f76aec76 | 2637 | return; |
2c2e2c38 | 2638 | |
ba395927 KA |
2639 | domain = find_domain(pdev); |
2640 | BUG_ON(!domain); | |
2641 | ||
8c11e798 WH |
2642 | iommu = domain_get_iommu(domain); |
2643 | ||
ba395927 | 2644 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
85b98276 DW |
2645 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
2646 | (unsigned long long)dev_addr)) | |
ba395927 | 2647 | return; |
ba395927 | 2648 | |
d794dc9b DW |
2649 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
2650 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
ba395927 | 2651 | |
d794dc9b DW |
2652 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
2653 | pci_name(pdev), start_pfn, last_pfn); | |
ba395927 | 2654 | |
f76aec76 | 2655 | /* clear the whole page */ |
d794dc9b DW |
2656 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
2657 | ||
f76aec76 | 2658 | /* free page tables */ |
d794dc9b DW |
2659 | dma_pte_free_pagetable(domain, start_pfn, last_pfn); |
2660 | ||
5e0d2a6f | 2661 | if (intel_iommu_strict) { |
03d6a246 | 2662 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
d794dc9b | 2663 | last_pfn - start_pfn + 1); |
5e0d2a6f | 2664 | /* free iova */ |
2665 | __free_iova(&domain->iovad, iova); | |
2666 | } else { | |
2667 | add_unmap(domain, iova); | |
2668 | /* | |
2669 | * queue up the release of the unmap to save the 1/6th of the | |
2670 | * cpu used up by the iotlb flush operation... | |
2671 | */ | |
5e0d2a6f | 2672 | } |
ba395927 KA |
2673 | } |
2674 | ||
d7ab5c46 FT |
2675 | static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size, |
2676 | int dir) | |
ffbbef5c FT |
2677 | { |
2678 | intel_unmap_page(dev, dev_addr, size, dir, NULL); | |
2679 | } | |
2680 | ||
d7ab5c46 FT |
2681 | static void *intel_alloc_coherent(struct device *hwdev, size_t size, |
2682 | dma_addr_t *dma_handle, gfp_t flags) | |
ba395927 KA |
2683 | { |
2684 | void *vaddr; | |
2685 | int order; | |
2686 | ||
5b6985ce | 2687 | size = PAGE_ALIGN(size); |
ba395927 KA |
2688 | order = get_order(size); |
2689 | flags &= ~(GFP_DMA | GFP_DMA32); | |
2690 | ||
2691 | vaddr = (void *)__get_free_pages(flags, order); | |
2692 | if (!vaddr) | |
2693 | return NULL; | |
2694 | memset(vaddr, 0, size); | |
2695 | ||
bb9e6d65 FT |
2696 | *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size, |
2697 | DMA_BIDIRECTIONAL, | |
2698 | hwdev->coherent_dma_mask); | |
ba395927 KA |
2699 | if (*dma_handle) |
2700 | return vaddr; | |
2701 | free_pages((unsigned long)vaddr, order); | |
2702 | return NULL; | |
2703 | } | |
2704 | ||
d7ab5c46 FT |
2705 | static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr, |
2706 | dma_addr_t dma_handle) | |
ba395927 KA |
2707 | { |
2708 | int order; | |
2709 | ||
5b6985ce | 2710 | size = PAGE_ALIGN(size); |
ba395927 KA |
2711 | order = get_order(size); |
2712 | ||
2713 | intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL); | |
2714 | free_pages((unsigned long)vaddr, order); | |
2715 | } | |
2716 | ||
d7ab5c46 FT |
2717 | static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist, |
2718 | int nelems, enum dma_data_direction dir, | |
2719 | struct dma_attrs *attrs) | |
ba395927 | 2720 | { |
ba395927 KA |
2721 | struct pci_dev *pdev = to_pci_dev(hwdev); |
2722 | struct dmar_domain *domain; | |
d794dc9b | 2723 | unsigned long start_pfn, last_pfn; |
f76aec76 | 2724 | struct iova *iova; |
8c11e798 | 2725 | struct intel_iommu *iommu; |
ba395927 | 2726 | |
2c2e2c38 | 2727 | if (iommu_no_mapping(pdev)) |
ba395927 KA |
2728 | return; |
2729 | ||
2730 | domain = find_domain(pdev); | |
8c11e798 WH |
2731 | BUG_ON(!domain); |
2732 | ||
2733 | iommu = domain_get_iommu(domain); | |
ba395927 | 2734 | |
c03ab37c | 2735 | iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address)); |
85b98276 DW |
2736 | if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n", |
2737 | (unsigned long long)sglist[0].dma_address)) | |
f76aec76 | 2738 | return; |
f76aec76 | 2739 | |
d794dc9b DW |
2740 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
2741 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
f76aec76 KA |
2742 | |
2743 | /* clear the whole page */ | |
d794dc9b DW |
2744 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
2745 | ||
f76aec76 | 2746 | /* free page tables */ |
d794dc9b | 2747 | dma_pte_free_pagetable(domain, start_pfn, last_pfn); |
f76aec76 | 2748 | |
03d6a246 | 2749 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
d794dc9b | 2750 | (last_pfn - start_pfn + 1)); |
f76aec76 KA |
2751 | |
2752 | /* free iova */ | |
2753 | __free_iova(&domain->iovad, iova); | |
ba395927 KA |
2754 | } |
2755 | ||
ba395927 | 2756 | static int intel_nontranslate_map_sg(struct device *hddev, |
c03ab37c | 2757 | struct scatterlist *sglist, int nelems, int dir) |
ba395927 KA |
2758 | { |
2759 | int i; | |
c03ab37c | 2760 | struct scatterlist *sg; |
ba395927 | 2761 | |
c03ab37c | 2762 | for_each_sg(sglist, sg, nelems, i) { |
12d4d40e | 2763 | BUG_ON(!sg_page(sg)); |
4cf2e75d | 2764 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
c03ab37c | 2765 | sg->dma_length = sg->length; |
ba395927 KA |
2766 | } |
2767 | return nelems; | |
2768 | } | |
2769 | ||
d7ab5c46 FT |
2770 | static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems, |
2771 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
ba395927 | 2772 | { |
ba395927 | 2773 | int i; |
ba395927 KA |
2774 | struct pci_dev *pdev = to_pci_dev(hwdev); |
2775 | struct dmar_domain *domain; | |
f76aec76 KA |
2776 | size_t size = 0; |
2777 | int prot = 0; | |
b536d24d | 2778 | size_t offset_pfn = 0; |
f76aec76 KA |
2779 | struct iova *iova = NULL; |
2780 | int ret; | |
c03ab37c | 2781 | struct scatterlist *sg; |
b536d24d | 2782 | unsigned long start_vpfn; |
8c11e798 | 2783 | struct intel_iommu *iommu; |
ba395927 KA |
2784 | |
2785 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 | 2786 | if (iommu_no_mapping(pdev)) |
c03ab37c | 2787 | return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir); |
ba395927 | 2788 | |
f76aec76 KA |
2789 | domain = get_valid_domain_for_dev(pdev); |
2790 | if (!domain) | |
2791 | return 0; | |
2792 | ||
8c11e798 WH |
2793 | iommu = domain_get_iommu(domain); |
2794 | ||
b536d24d | 2795 | for_each_sg(sglist, sg, nelems, i) |
88cb6a74 | 2796 | size += aligned_nrpages(sg->offset, sg->length); |
f76aec76 | 2797 | |
875764de | 2798 | iova = intel_alloc_iova(hwdev, domain, size, pdev->dma_mask); |
f76aec76 | 2799 | if (!iova) { |
c03ab37c | 2800 | sglist->dma_length = 0; |
f76aec76 KA |
2801 | return 0; |
2802 | } | |
2803 | ||
2804 | /* | |
2805 | * Check if DMAR supports zero-length reads on write only | |
2806 | * mappings.. | |
2807 | */ | |
2808 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 2809 | !cap_zlr(iommu->cap)) |
f76aec76 KA |
2810 | prot |= DMA_PTE_READ; |
2811 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
2812 | prot |= DMA_PTE_WRITE; | |
2813 | ||
b536d24d | 2814 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
e1605495 DW |
2815 | |
2816 | ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot); | |
2817 | if (unlikely(ret)) { | |
2818 | /* clear the page */ | |
2819 | dma_pte_clear_range(domain, start_vpfn, | |
2820 | start_vpfn + size - 1); | |
2821 | /* free page tables */ | |
2822 | dma_pte_free_pagetable(domain, start_vpfn, | |
2823 | start_vpfn + size - 1); | |
2824 | /* free iova */ | |
2825 | __free_iova(&domain->iovad, iova); | |
2826 | return 0; | |
ba395927 KA |
2827 | } |
2828 | ||
1f0ef2aa DW |
2829 | /* it's a non-present to present mapping. Only flush if caching mode */ |
2830 | if (cap_caching_mode(iommu->cap)) | |
03d6a246 | 2831 | iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn); |
1f0ef2aa | 2832 | else |
8c11e798 | 2833 | iommu_flush_write_buffer(iommu); |
1f0ef2aa | 2834 | |
ba395927 KA |
2835 | return nelems; |
2836 | } | |
2837 | ||
dfb805e8 FT |
2838 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
2839 | { | |
2840 | return !dma_addr; | |
2841 | } | |
2842 | ||
160c1d8e | 2843 | struct dma_map_ops intel_dma_ops = { |
ba395927 KA |
2844 | .alloc_coherent = intel_alloc_coherent, |
2845 | .free_coherent = intel_free_coherent, | |
ba395927 KA |
2846 | .map_sg = intel_map_sg, |
2847 | .unmap_sg = intel_unmap_sg, | |
ffbbef5c FT |
2848 | .map_page = intel_map_page, |
2849 | .unmap_page = intel_unmap_page, | |
dfb805e8 | 2850 | .mapping_error = intel_mapping_error, |
ba395927 KA |
2851 | }; |
2852 | ||
2853 | static inline int iommu_domain_cache_init(void) | |
2854 | { | |
2855 | int ret = 0; | |
2856 | ||
2857 | iommu_domain_cache = kmem_cache_create("iommu_domain", | |
2858 | sizeof(struct dmar_domain), | |
2859 | 0, | |
2860 | SLAB_HWCACHE_ALIGN, | |
2861 | ||
2862 | NULL); | |
2863 | if (!iommu_domain_cache) { | |
2864 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); | |
2865 | ret = -ENOMEM; | |
2866 | } | |
2867 | ||
2868 | return ret; | |
2869 | } | |
2870 | ||
2871 | static inline int iommu_devinfo_cache_init(void) | |
2872 | { | |
2873 | int ret = 0; | |
2874 | ||
2875 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", | |
2876 | sizeof(struct device_domain_info), | |
2877 | 0, | |
2878 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
2879 | NULL); |
2880 | if (!iommu_devinfo_cache) { | |
2881 | printk(KERN_ERR "Couldn't create devinfo cache\n"); | |
2882 | ret = -ENOMEM; | |
2883 | } | |
2884 | ||
2885 | return ret; | |
2886 | } | |
2887 | ||
2888 | static inline int iommu_iova_cache_init(void) | |
2889 | { | |
2890 | int ret = 0; | |
2891 | ||
2892 | iommu_iova_cache = kmem_cache_create("iommu_iova", | |
2893 | sizeof(struct iova), | |
2894 | 0, | |
2895 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
2896 | NULL); |
2897 | if (!iommu_iova_cache) { | |
2898 | printk(KERN_ERR "Couldn't create iova cache\n"); | |
2899 | ret = -ENOMEM; | |
2900 | } | |
2901 | ||
2902 | return ret; | |
2903 | } | |
2904 | ||
2905 | static int __init iommu_init_mempool(void) | |
2906 | { | |
2907 | int ret; | |
2908 | ret = iommu_iova_cache_init(); | |
2909 | if (ret) | |
2910 | return ret; | |
2911 | ||
2912 | ret = iommu_domain_cache_init(); | |
2913 | if (ret) | |
2914 | goto domain_error; | |
2915 | ||
2916 | ret = iommu_devinfo_cache_init(); | |
2917 | if (!ret) | |
2918 | return ret; | |
2919 | ||
2920 | kmem_cache_destroy(iommu_domain_cache); | |
2921 | domain_error: | |
2922 | kmem_cache_destroy(iommu_iova_cache); | |
2923 | ||
2924 | return -ENOMEM; | |
2925 | } | |
2926 | ||
2927 | static void __init iommu_exit_mempool(void) | |
2928 | { | |
2929 | kmem_cache_destroy(iommu_devinfo_cache); | |
2930 | kmem_cache_destroy(iommu_domain_cache); | |
2931 | kmem_cache_destroy(iommu_iova_cache); | |
2932 | ||
2933 | } | |
2934 | ||
ba395927 KA |
2935 | static void __init init_no_remapping_devices(void) |
2936 | { | |
2937 | struct dmar_drhd_unit *drhd; | |
2938 | ||
2939 | for_each_drhd_unit(drhd) { | |
2940 | if (!drhd->include_all) { | |
2941 | int i; | |
2942 | for (i = 0; i < drhd->devices_cnt; i++) | |
2943 | if (drhd->devices[i] != NULL) | |
2944 | break; | |
2945 | /* ignore DMAR unit if no pci devices exist */ | |
2946 | if (i == drhd->devices_cnt) | |
2947 | drhd->ignored = 1; | |
2948 | } | |
2949 | } | |
2950 | ||
2951 | if (dmar_map_gfx) | |
2952 | return; | |
2953 | ||
2954 | for_each_drhd_unit(drhd) { | |
2955 | int i; | |
2956 | if (drhd->ignored || drhd->include_all) | |
2957 | continue; | |
2958 | ||
2959 | for (i = 0; i < drhd->devices_cnt; i++) | |
2960 | if (drhd->devices[i] && | |
2961 | !IS_GFX_DEVICE(drhd->devices[i])) | |
2962 | break; | |
2963 | ||
2964 | if (i < drhd->devices_cnt) | |
2965 | continue; | |
2966 | ||
2967 | /* bypass IOMMU if it is just for gfx devices */ | |
2968 | drhd->ignored = 1; | |
2969 | for (i = 0; i < drhd->devices_cnt; i++) { | |
2970 | if (!drhd->devices[i]) | |
2971 | continue; | |
358dd8ac | 2972 | drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
ba395927 KA |
2973 | } |
2974 | } | |
2975 | } | |
2976 | ||
f59c7b69 FY |
2977 | #ifdef CONFIG_SUSPEND |
2978 | static int init_iommu_hw(void) | |
2979 | { | |
2980 | struct dmar_drhd_unit *drhd; | |
2981 | struct intel_iommu *iommu = NULL; | |
2982 | ||
2983 | for_each_active_iommu(iommu, drhd) | |
2984 | if (iommu->qi) | |
2985 | dmar_reenable_qi(iommu); | |
2986 | ||
2987 | for_each_active_iommu(iommu, drhd) { | |
2988 | iommu_flush_write_buffer(iommu); | |
2989 | ||
2990 | iommu_set_root_entry(iommu); | |
2991 | ||
2992 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 2993 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 2994 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 2995 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
2996 | iommu_disable_protect_mem_regions(iommu); |
2997 | iommu_enable_translation(iommu); | |
2998 | } | |
2999 | ||
3000 | return 0; | |
3001 | } | |
3002 | ||
3003 | static void iommu_flush_all(void) | |
3004 | { | |
3005 | struct dmar_drhd_unit *drhd; | |
3006 | struct intel_iommu *iommu; | |
3007 | ||
3008 | for_each_active_iommu(iommu, drhd) { | |
3009 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3010 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3011 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3012 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
3013 | } |
3014 | } | |
3015 | ||
3016 | static int iommu_suspend(struct sys_device *dev, pm_message_t state) | |
3017 | { | |
3018 | struct dmar_drhd_unit *drhd; | |
3019 | struct intel_iommu *iommu = NULL; | |
3020 | unsigned long flag; | |
3021 | ||
3022 | for_each_active_iommu(iommu, drhd) { | |
3023 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, | |
3024 | GFP_ATOMIC); | |
3025 | if (!iommu->iommu_state) | |
3026 | goto nomem; | |
3027 | } | |
3028 | ||
3029 | iommu_flush_all(); | |
3030 | ||
3031 | for_each_active_iommu(iommu, drhd) { | |
3032 | iommu_disable_translation(iommu); | |
3033 | ||
3034 | spin_lock_irqsave(&iommu->register_lock, flag); | |
3035 | ||
3036 | iommu->iommu_state[SR_DMAR_FECTL_REG] = | |
3037 | readl(iommu->reg + DMAR_FECTL_REG); | |
3038 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = | |
3039 | readl(iommu->reg + DMAR_FEDATA_REG); | |
3040 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = | |
3041 | readl(iommu->reg + DMAR_FEADDR_REG); | |
3042 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = | |
3043 | readl(iommu->reg + DMAR_FEUADDR_REG); | |
3044 | ||
3045 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
3046 | } | |
3047 | return 0; | |
3048 | ||
3049 | nomem: | |
3050 | for_each_active_iommu(iommu, drhd) | |
3051 | kfree(iommu->iommu_state); | |
3052 | ||
3053 | return -ENOMEM; | |
3054 | } | |
3055 | ||
3056 | static int iommu_resume(struct sys_device *dev) | |
3057 | { | |
3058 | struct dmar_drhd_unit *drhd; | |
3059 | struct intel_iommu *iommu = NULL; | |
3060 | unsigned long flag; | |
3061 | ||
3062 | if (init_iommu_hw()) { | |
3063 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); | |
3064 | return -EIO; | |
3065 | } | |
3066 | ||
3067 | for_each_active_iommu(iommu, drhd) { | |
3068 | ||
3069 | spin_lock_irqsave(&iommu->register_lock, flag); | |
3070 | ||
3071 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], | |
3072 | iommu->reg + DMAR_FECTL_REG); | |
3073 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], | |
3074 | iommu->reg + DMAR_FEDATA_REG); | |
3075 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], | |
3076 | iommu->reg + DMAR_FEADDR_REG); | |
3077 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], | |
3078 | iommu->reg + DMAR_FEUADDR_REG); | |
3079 | ||
3080 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
3081 | } | |
3082 | ||
3083 | for_each_active_iommu(iommu, drhd) | |
3084 | kfree(iommu->iommu_state); | |
3085 | ||
3086 | return 0; | |
3087 | } | |
3088 | ||
3089 | static struct sysdev_class iommu_sysclass = { | |
3090 | .name = "iommu", | |
3091 | .resume = iommu_resume, | |
3092 | .suspend = iommu_suspend, | |
3093 | }; | |
3094 | ||
3095 | static struct sys_device device_iommu = { | |
3096 | .cls = &iommu_sysclass, | |
3097 | }; | |
3098 | ||
3099 | static int __init init_iommu_sysfs(void) | |
3100 | { | |
3101 | int error; | |
3102 | ||
3103 | error = sysdev_class_register(&iommu_sysclass); | |
3104 | if (error) | |
3105 | return error; | |
3106 | ||
3107 | error = sysdev_register(&device_iommu); | |
3108 | if (error) | |
3109 | sysdev_class_unregister(&iommu_sysclass); | |
3110 | ||
3111 | return error; | |
3112 | } | |
3113 | ||
3114 | #else | |
3115 | static int __init init_iommu_sysfs(void) | |
3116 | { | |
3117 | return 0; | |
3118 | } | |
3119 | #endif /* CONFIG_PM */ | |
3120 | ||
ba395927 KA |
3121 | int __init intel_iommu_init(void) |
3122 | { | |
3123 | int ret = 0; | |
3124 | ||
ba395927 KA |
3125 | if (dmar_table_init()) |
3126 | return -ENODEV; | |
3127 | ||
1886e8a9 SS |
3128 | if (dmar_dev_scope_init()) |
3129 | return -ENODEV; | |
3130 | ||
2ae21010 SS |
3131 | /* |
3132 | * Check the need for DMA-remapping initialization now. | |
3133 | * Above initialization will also be used by Interrupt-remapping. | |
3134 | */ | |
4ed0d3e6 | 3135 | if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled) |
2ae21010 SS |
3136 | return -ENODEV; |
3137 | ||
ba395927 KA |
3138 | iommu_init_mempool(); |
3139 | dmar_init_reserved_ranges(); | |
3140 | ||
3141 | init_no_remapping_devices(); | |
3142 | ||
3143 | ret = init_dmars(); | |
3144 | if (ret) { | |
3145 | printk(KERN_ERR "IOMMU: dmar init failed\n"); | |
3146 | put_iova_domain(&reserved_iova_list); | |
3147 | iommu_exit_mempool(); | |
3148 | return ret; | |
3149 | } | |
3150 | printk(KERN_INFO | |
3151 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); | |
3152 | ||
5e0d2a6f | 3153 | init_timer(&unmap_timer); |
ba395927 | 3154 | force_iommu = 1; |
4ed0d3e6 FY |
3155 | |
3156 | if (!iommu_pass_through) { | |
3157 | printk(KERN_INFO | |
3158 | "Multi-level page-table translation for DMAR.\n"); | |
3159 | dma_ops = &intel_dma_ops; | |
3160 | } else | |
3161 | printk(KERN_INFO | |
3162 | "DMAR: Pass through translation for DMAR.\n"); | |
3163 | ||
f59c7b69 | 3164 | init_iommu_sysfs(); |
a8bcbb0d JR |
3165 | |
3166 | register_iommu(&intel_iommu_ops); | |
3167 | ||
ba395927 KA |
3168 | return 0; |
3169 | } | |
e820482c | 3170 | |
3199aa6b HW |
3171 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
3172 | struct pci_dev *pdev) | |
3173 | { | |
3174 | struct pci_dev *tmp, *parent; | |
3175 | ||
3176 | if (!iommu || !pdev) | |
3177 | return; | |
3178 | ||
3179 | /* dependent device detach */ | |
3180 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
3181 | /* Secondary interface's bus number and devfn 0 */ | |
3182 | if (tmp) { | |
3183 | parent = pdev->bus->self; | |
3184 | while (parent != tmp) { | |
3185 | iommu_detach_dev(iommu, parent->bus->number, | |
276dbf99 | 3186 | parent->devfn); |
3199aa6b HW |
3187 | parent = parent->bus->self; |
3188 | } | |
3189 | if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */ | |
3190 | iommu_detach_dev(iommu, | |
3191 | tmp->subordinate->number, 0); | |
3192 | else /* this is a legacy PCI bridge */ | |
276dbf99 DW |
3193 | iommu_detach_dev(iommu, tmp->bus->number, |
3194 | tmp->devfn); | |
3199aa6b HW |
3195 | } |
3196 | } | |
3197 | ||
2c2e2c38 | 3198 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
c7151a8d WH |
3199 | struct pci_dev *pdev) |
3200 | { | |
3201 | struct device_domain_info *info; | |
3202 | struct intel_iommu *iommu; | |
3203 | unsigned long flags; | |
3204 | int found = 0; | |
3205 | struct list_head *entry, *tmp; | |
3206 | ||
276dbf99 DW |
3207 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
3208 | pdev->devfn); | |
c7151a8d WH |
3209 | if (!iommu) |
3210 | return; | |
3211 | ||
3212 | spin_lock_irqsave(&device_domain_lock, flags); | |
3213 | list_for_each_safe(entry, tmp, &domain->devices) { | |
3214 | info = list_entry(entry, struct device_domain_info, link); | |
276dbf99 | 3215 | /* No need to compare PCI domain; it has to be the same */ |
c7151a8d WH |
3216 | if (info->bus == pdev->bus->number && |
3217 | info->devfn == pdev->devfn) { | |
3218 | list_del(&info->link); | |
3219 | list_del(&info->global); | |
3220 | if (info->dev) | |
3221 | info->dev->dev.archdata.iommu = NULL; | |
3222 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
3223 | ||
93a23a72 | 3224 | iommu_disable_dev_iotlb(info); |
c7151a8d | 3225 | iommu_detach_dev(iommu, info->bus, info->devfn); |
3199aa6b | 3226 | iommu_detach_dependent_devices(iommu, pdev); |
c7151a8d WH |
3227 | free_devinfo_mem(info); |
3228 | ||
3229 | spin_lock_irqsave(&device_domain_lock, flags); | |
3230 | ||
3231 | if (found) | |
3232 | break; | |
3233 | else | |
3234 | continue; | |
3235 | } | |
3236 | ||
3237 | /* if there is no other devices under the same iommu | |
3238 | * owned by this domain, clear this iommu in iommu_bmp | |
3239 | * update iommu count and coherency | |
3240 | */ | |
276dbf99 DW |
3241 | if (iommu == device_to_iommu(info->segment, info->bus, |
3242 | info->devfn)) | |
c7151a8d WH |
3243 | found = 1; |
3244 | } | |
3245 | ||
3246 | if (found == 0) { | |
3247 | unsigned long tmp_flags; | |
3248 | spin_lock_irqsave(&domain->iommu_lock, tmp_flags); | |
3249 | clear_bit(iommu->seq_id, &domain->iommu_bmp); | |
3250 | domain->iommu_count--; | |
58c610bd | 3251 | domain_update_iommu_cap(domain); |
c7151a8d WH |
3252 | spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags); |
3253 | } | |
3254 | ||
3255 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
3256 | } | |
3257 | ||
3258 | static void vm_domain_remove_all_dev_info(struct dmar_domain *domain) | |
3259 | { | |
3260 | struct device_domain_info *info; | |
3261 | struct intel_iommu *iommu; | |
3262 | unsigned long flags1, flags2; | |
3263 | ||
3264 | spin_lock_irqsave(&device_domain_lock, flags1); | |
3265 | while (!list_empty(&domain->devices)) { | |
3266 | info = list_entry(domain->devices.next, | |
3267 | struct device_domain_info, link); | |
3268 | list_del(&info->link); | |
3269 | list_del(&info->global); | |
3270 | if (info->dev) | |
3271 | info->dev->dev.archdata.iommu = NULL; | |
3272 | ||
3273 | spin_unlock_irqrestore(&device_domain_lock, flags1); | |
3274 | ||
93a23a72 | 3275 | iommu_disable_dev_iotlb(info); |
276dbf99 | 3276 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
c7151a8d | 3277 | iommu_detach_dev(iommu, info->bus, info->devfn); |
3199aa6b | 3278 | iommu_detach_dependent_devices(iommu, info->dev); |
c7151a8d WH |
3279 | |
3280 | /* clear this iommu in iommu_bmp, update iommu count | |
58c610bd | 3281 | * and capabilities |
c7151a8d WH |
3282 | */ |
3283 | spin_lock_irqsave(&domain->iommu_lock, flags2); | |
3284 | if (test_and_clear_bit(iommu->seq_id, | |
3285 | &domain->iommu_bmp)) { | |
3286 | domain->iommu_count--; | |
58c610bd | 3287 | domain_update_iommu_cap(domain); |
c7151a8d WH |
3288 | } |
3289 | spin_unlock_irqrestore(&domain->iommu_lock, flags2); | |
3290 | ||
3291 | free_devinfo_mem(info); | |
3292 | spin_lock_irqsave(&device_domain_lock, flags1); | |
3293 | } | |
3294 | spin_unlock_irqrestore(&device_domain_lock, flags1); | |
3295 | } | |
3296 | ||
5e98c4b1 WH |
3297 | /* domain id for virtual machine, it won't be set in context */ |
3298 | static unsigned long vm_domid; | |
3299 | ||
fe40f1e0 WH |
3300 | static int vm_domain_min_agaw(struct dmar_domain *domain) |
3301 | { | |
3302 | int i; | |
3303 | int min_agaw = domain->agaw; | |
3304 | ||
3305 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
3306 | for (; i < g_num_of_iommus; ) { | |
3307 | if (min_agaw > g_iommus[i]->agaw) | |
3308 | min_agaw = g_iommus[i]->agaw; | |
3309 | ||
3310 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
3311 | } | |
3312 | ||
3313 | return min_agaw; | |
3314 | } | |
3315 | ||
5e98c4b1 WH |
3316 | static struct dmar_domain *iommu_alloc_vm_domain(void) |
3317 | { | |
3318 | struct dmar_domain *domain; | |
3319 | ||
3320 | domain = alloc_domain_mem(); | |
3321 | if (!domain) | |
3322 | return NULL; | |
3323 | ||
3324 | domain->id = vm_domid++; | |
3325 | memset(&domain->iommu_bmp, 0, sizeof(unsigned long)); | |
3326 | domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE; | |
3327 | ||
3328 | return domain; | |
3329 | } | |
3330 | ||
2c2e2c38 | 3331 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
5e98c4b1 WH |
3332 | { |
3333 | int adjust_width; | |
3334 | ||
3335 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); | |
5e98c4b1 WH |
3336 | spin_lock_init(&domain->iommu_lock); |
3337 | ||
3338 | domain_reserve_special_ranges(domain); | |
3339 | ||
3340 | /* calculate AGAW */ | |
3341 | domain->gaw = guest_width; | |
3342 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
3343 | domain->agaw = width_to_agaw(adjust_width); | |
3344 | ||
3345 | INIT_LIST_HEAD(&domain->devices); | |
3346 | ||
3347 | domain->iommu_count = 0; | |
3348 | domain->iommu_coherency = 0; | |
fe40f1e0 | 3349 | domain->max_addr = 0; |
5e98c4b1 WH |
3350 | |
3351 | /* always allocate the top pgd */ | |
3352 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(); | |
3353 | if (!domain->pgd) | |
3354 | return -ENOMEM; | |
3355 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); | |
3356 | return 0; | |
3357 | } | |
3358 | ||
3359 | static void iommu_free_vm_domain(struct dmar_domain *domain) | |
3360 | { | |
3361 | unsigned long flags; | |
3362 | struct dmar_drhd_unit *drhd; | |
3363 | struct intel_iommu *iommu; | |
3364 | unsigned long i; | |
3365 | unsigned long ndomains; | |
3366 | ||
3367 | for_each_drhd_unit(drhd) { | |
3368 | if (drhd->ignored) | |
3369 | continue; | |
3370 | iommu = drhd->iommu; | |
3371 | ||
3372 | ndomains = cap_ndoms(iommu->cap); | |
3373 | i = find_first_bit(iommu->domain_ids, ndomains); | |
3374 | for (; i < ndomains; ) { | |
3375 | if (iommu->domains[i] == domain) { | |
3376 | spin_lock_irqsave(&iommu->lock, flags); | |
3377 | clear_bit(i, iommu->domain_ids); | |
3378 | iommu->domains[i] = NULL; | |
3379 | spin_unlock_irqrestore(&iommu->lock, flags); | |
3380 | break; | |
3381 | } | |
3382 | i = find_next_bit(iommu->domain_ids, ndomains, i+1); | |
3383 | } | |
3384 | } | |
3385 | } | |
3386 | ||
3387 | static void vm_domain_exit(struct dmar_domain *domain) | |
3388 | { | |
5e98c4b1 WH |
3389 | /* Domain 0 is reserved, so dont process it */ |
3390 | if (!domain) | |
3391 | return; | |
3392 | ||
3393 | vm_domain_remove_all_dev_info(domain); | |
3394 | /* destroy iovas */ | |
3395 | put_iova_domain(&domain->iovad); | |
5e98c4b1 WH |
3396 | |
3397 | /* clear ptes */ | |
595badf5 | 3398 | dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
5e98c4b1 WH |
3399 | |
3400 | /* free page tables */ | |
d794dc9b | 3401 | dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
5e98c4b1 WH |
3402 | |
3403 | iommu_free_vm_domain(domain); | |
3404 | free_domain_mem(domain); | |
3405 | } | |
3406 | ||
5d450806 | 3407 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
38717946 | 3408 | { |
5d450806 | 3409 | struct dmar_domain *dmar_domain; |
38717946 | 3410 | |
5d450806 JR |
3411 | dmar_domain = iommu_alloc_vm_domain(); |
3412 | if (!dmar_domain) { | |
38717946 | 3413 | printk(KERN_ERR |
5d450806 JR |
3414 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
3415 | return -ENOMEM; | |
38717946 | 3416 | } |
2c2e2c38 | 3417 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
38717946 | 3418 | printk(KERN_ERR |
5d450806 JR |
3419 | "intel_iommu_domain_init() failed\n"); |
3420 | vm_domain_exit(dmar_domain); | |
3421 | return -ENOMEM; | |
38717946 | 3422 | } |
5d450806 | 3423 | domain->priv = dmar_domain; |
faa3d6f5 | 3424 | |
5d450806 | 3425 | return 0; |
38717946 | 3426 | } |
38717946 | 3427 | |
5d450806 | 3428 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
38717946 | 3429 | { |
5d450806 JR |
3430 | struct dmar_domain *dmar_domain = domain->priv; |
3431 | ||
3432 | domain->priv = NULL; | |
3433 | vm_domain_exit(dmar_domain); | |
38717946 | 3434 | } |
38717946 | 3435 | |
4c5478c9 JR |
3436 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
3437 | struct device *dev) | |
38717946 | 3438 | { |
4c5478c9 JR |
3439 | struct dmar_domain *dmar_domain = domain->priv; |
3440 | struct pci_dev *pdev = to_pci_dev(dev); | |
fe40f1e0 WH |
3441 | struct intel_iommu *iommu; |
3442 | int addr_width; | |
3443 | u64 end; | |
faa3d6f5 WH |
3444 | int ret; |
3445 | ||
3446 | /* normally pdev is not mapped */ | |
3447 | if (unlikely(domain_context_mapped(pdev))) { | |
3448 | struct dmar_domain *old_domain; | |
3449 | ||
3450 | old_domain = find_domain(pdev); | |
3451 | if (old_domain) { | |
2c2e2c38 FY |
3452 | if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
3453 | dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) | |
3454 | domain_remove_one_dev_info(old_domain, pdev); | |
faa3d6f5 WH |
3455 | else |
3456 | domain_remove_dev_info(old_domain); | |
3457 | } | |
3458 | } | |
3459 | ||
276dbf99 DW |
3460 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
3461 | pdev->devfn); | |
fe40f1e0 WH |
3462 | if (!iommu) |
3463 | return -ENODEV; | |
3464 | ||
3465 | /* check if this iommu agaw is sufficient for max mapped address */ | |
3466 | addr_width = agaw_to_width(iommu->agaw); | |
3467 | end = DOMAIN_MAX_ADDR(addr_width); | |
3468 | end = end & VTD_PAGE_MASK; | |
4c5478c9 | 3469 | if (end < dmar_domain->max_addr) { |
fe40f1e0 WH |
3470 | printk(KERN_ERR "%s: iommu agaw (%d) is not " |
3471 | "sufficient for the mapped address (%llx)\n", | |
4c5478c9 | 3472 | __func__, iommu->agaw, dmar_domain->max_addr); |
fe40f1e0 WH |
3473 | return -EFAULT; |
3474 | } | |
3475 | ||
2c2e2c38 | 3476 | ret = domain_add_dev_info(dmar_domain, pdev); |
faa3d6f5 WH |
3477 | if (ret) |
3478 | return ret; | |
3479 | ||
93a23a72 | 3480 | ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
faa3d6f5 | 3481 | return ret; |
38717946 | 3482 | } |
38717946 | 3483 | |
4c5478c9 JR |
3484 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
3485 | struct device *dev) | |
38717946 | 3486 | { |
4c5478c9 JR |
3487 | struct dmar_domain *dmar_domain = domain->priv; |
3488 | struct pci_dev *pdev = to_pci_dev(dev); | |
3489 | ||
2c2e2c38 | 3490 | domain_remove_one_dev_info(dmar_domain, pdev); |
faa3d6f5 | 3491 | } |
c7151a8d | 3492 | |
dde57a21 JR |
3493 | static int intel_iommu_map_range(struct iommu_domain *domain, |
3494 | unsigned long iova, phys_addr_t hpa, | |
3495 | size_t size, int iommu_prot) | |
faa3d6f5 | 3496 | { |
dde57a21 | 3497 | struct dmar_domain *dmar_domain = domain->priv; |
fe40f1e0 WH |
3498 | u64 max_addr; |
3499 | int addr_width; | |
dde57a21 | 3500 | int prot = 0; |
faa3d6f5 | 3501 | int ret; |
fe40f1e0 | 3502 | |
dde57a21 JR |
3503 | if (iommu_prot & IOMMU_READ) |
3504 | prot |= DMA_PTE_READ; | |
3505 | if (iommu_prot & IOMMU_WRITE) | |
3506 | prot |= DMA_PTE_WRITE; | |
9cf06697 SY |
3507 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
3508 | prot |= DMA_PTE_SNP; | |
dde57a21 | 3509 | |
163cc52c | 3510 | max_addr = iova + size; |
dde57a21 | 3511 | if (dmar_domain->max_addr < max_addr) { |
fe40f1e0 WH |
3512 | int min_agaw; |
3513 | u64 end; | |
3514 | ||
3515 | /* check if minimum agaw is sufficient for mapped address */ | |
dde57a21 | 3516 | min_agaw = vm_domain_min_agaw(dmar_domain); |
fe40f1e0 WH |
3517 | addr_width = agaw_to_width(min_agaw); |
3518 | end = DOMAIN_MAX_ADDR(addr_width); | |
3519 | end = end & VTD_PAGE_MASK; | |
3520 | if (end < max_addr) { | |
3521 | printk(KERN_ERR "%s: iommu agaw (%d) is not " | |
3522 | "sufficient for the mapped address (%llx)\n", | |
3523 | __func__, min_agaw, max_addr); | |
3524 | return -EFAULT; | |
3525 | } | |
dde57a21 | 3526 | dmar_domain->max_addr = max_addr; |
fe40f1e0 | 3527 | } |
ad051221 DW |
3528 | /* Round up size to next multiple of PAGE_SIZE, if it and |
3529 | the low bits of hpa would take us onto the next page */ | |
88cb6a74 | 3530 | size = aligned_nrpages(hpa, size); |
ad051221 DW |
3531 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
3532 | hpa >> VTD_PAGE_SHIFT, size, prot); | |
faa3d6f5 | 3533 | return ret; |
38717946 | 3534 | } |
38717946 | 3535 | |
dde57a21 JR |
3536 | static void intel_iommu_unmap_range(struct iommu_domain *domain, |
3537 | unsigned long iova, size_t size) | |
38717946 | 3538 | { |
dde57a21 | 3539 | struct dmar_domain *dmar_domain = domain->priv; |
faa3d6f5 | 3540 | |
163cc52c DW |
3541 | dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT, |
3542 | (iova + size - 1) >> VTD_PAGE_SHIFT); | |
fe40f1e0 | 3543 | |
163cc52c DW |
3544 | if (dmar_domain->max_addr == iova + size) |
3545 | dmar_domain->max_addr = iova; | |
38717946 | 3546 | } |
38717946 | 3547 | |
d14d6577 JR |
3548 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
3549 | unsigned long iova) | |
38717946 | 3550 | { |
d14d6577 | 3551 | struct dmar_domain *dmar_domain = domain->priv; |
38717946 | 3552 | struct dma_pte *pte; |
faa3d6f5 | 3553 | u64 phys = 0; |
38717946 | 3554 | |
b026fd28 | 3555 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT); |
38717946 | 3556 | if (pte) |
faa3d6f5 | 3557 | phys = dma_pte_addr(pte); |
38717946 | 3558 | |
faa3d6f5 | 3559 | return phys; |
38717946 | 3560 | } |
a8bcbb0d | 3561 | |
dbb9fd86 SY |
3562 | static int intel_iommu_domain_has_cap(struct iommu_domain *domain, |
3563 | unsigned long cap) | |
3564 | { | |
3565 | struct dmar_domain *dmar_domain = domain->priv; | |
3566 | ||
3567 | if (cap == IOMMU_CAP_CACHE_COHERENCY) | |
3568 | return dmar_domain->iommu_snooping; | |
3569 | ||
3570 | return 0; | |
3571 | } | |
3572 | ||
a8bcbb0d JR |
3573 | static struct iommu_ops intel_iommu_ops = { |
3574 | .domain_init = intel_iommu_domain_init, | |
3575 | .domain_destroy = intel_iommu_domain_destroy, | |
3576 | .attach_dev = intel_iommu_attach_device, | |
3577 | .detach_dev = intel_iommu_detach_device, | |
3578 | .map = intel_iommu_map_range, | |
3579 | .unmap = intel_iommu_unmap_range, | |
3580 | .iova_to_phys = intel_iommu_iova_to_phys, | |
dbb9fd86 | 3581 | .domain_has_cap = intel_iommu_domain_has_cap, |
a8bcbb0d | 3582 | }; |
9af88143 DW |
3583 | |
3584 | static void __devinit quirk_iommu_rwbf(struct pci_dev *dev) | |
3585 | { | |
3586 | /* | |
3587 | * Mobile 4 Series Chipset neglects to set RWBF capability, | |
3588 | * but needs it: | |
3589 | */ | |
3590 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); | |
3591 | rwbf_quirk = 1; | |
3592 | } | |
3593 | ||
3594 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |