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intel-iommu: Use cmpxchg64_local() for setting PTEs
[mirror_ubuntu-artful-kernel.git] / drivers / pci / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
5e0d2a6f 35#include <linux/timer.h>
38717946 36#include <linux/iova.h>
5d450806 37#include <linux/iommu.h>
38717946 38#include <linux/intel-iommu.h>
f59c7b69 39#include <linux/sysdev.h>
ba395927 40#include <asm/cacheflush.h>
46a7fa27 41#include <asm/iommu.h>
ba395927
KA		 42#include "pci.h"
43
5b6985ce
FY		 44#define ROOT_SIZE VTD_PAGE_SIZE
45#define CONTEXT_SIZE VTD_PAGE_SIZE
46
ba395927
KA		 47#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50#define IOAPIC_RANGE_START (0xfee00000)
51#define IOAPIC_RANGE_END (0xfeefffff)
52#define IOVA_START_ADDR (0x1000)
53
54#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
4ed0d3e6
FY		 56#define MAX_AGAW_WIDTH 64
57
ba395927 58#define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
595badf5 59#define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
ba395927 60
f27be03b 61#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 62#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 63#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 64
fd18de50 65
dd4e8319
DW		 66/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67 are never going to work. */
68static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
69{
70 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
71}
72
73static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
74{
75 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
76}
77static inline unsigned long page_to_dma_pfn(struct page *pg)
78{
79 return mm_to_dma_pfn(page_to_pfn(pg));
80}
81static inline unsigned long virt_to_dma_pfn(void *p)
82{
83 return page_to_dma_pfn(virt_to_page(p));
84}
85
d9630fe9
WH		 86/* global iommu list, set NULL for ignored DMAR units */
87static struct intel_iommu **g_iommus;
88
9af88143
DW		 89static int rwbf_quirk;
90
46b08e1a
MM		 91/*
92 * 0: Present
93 * 1-11: Reserved
94 * 12-63: Context Ptr (12 - (haw-1))
95 * 64-127: Reserved
96 */
97struct root_entry {
98 u64 val;
99 u64 rsvd1;
100};
101#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102static inline bool root_present(struct root_entry *root)
103{
104 return (root->val & 1);
105}
106static inline void set_root_present(struct root_entry *root)
107{
108 root->val |= 1;
109}
110static inline void set_root_value(struct root_entry *root, unsigned long value)
111{
112 root->val |= value & VTD_PAGE_MASK;
113}
114
115static inline struct context_entry *
116get_context_addr_from_root(struct root_entry *root)
117{
118 return (struct context_entry *)
119 (root_present(root)?phys_to_virt(
120 root->val & VTD_PAGE_MASK) :
121 NULL);
122}
123
7a8fc25e
MM		 124/*
125 * low 64 bits:
126 * 0: present
127 * 1: fault processing disable
128 * 2-3: translation type
129 * 12-63: address space root
130 * high 64 bits:
131 * 0-2: address width
132 * 3-6: aval
133 * 8-23: domain id
134 */
135struct context_entry {
136 u64 lo;
137 u64 hi;
138};
c07e7d21
MM		 139
140static inline bool context_present(struct context_entry *context)
141{
142 return (context->lo & 1);
143}
144static inline void context_set_present(struct context_entry *context)
145{
146 context->lo |= 1;
147}
148
149static inline void context_set_fault_enable(struct context_entry *context)
150{
151 context->lo &= (((u64)-1) << 2) | 1;
152}
153
c07e7d21
MM		 154static inline void context_set_translation_type(struct context_entry *context,
155 unsigned long value)
156{
157 context->lo &= (((u64)-1) << 4) | 3;
158 context->lo |= (value & 3) << 2;
159}
160
161static inline void context_set_address_root(struct context_entry *context,
162 unsigned long value)
163{
164 context->lo |= value & VTD_PAGE_MASK;
165}
166
167static inline void context_set_address_width(struct context_entry *context,
168 unsigned long value)
169{
170 context->hi |= value & 7;
171}
172
173static inline void context_set_domain_id(struct context_entry *context,
174 unsigned long value)
175{
176 context->hi |= (value & ((1 << 16) - 1)) << 8;
177}
178
179static inline void context_clear_entry(struct context_entry *context)
180{
181 context->lo = 0;
182 context->hi = 0;
183}
7a8fc25e 184
622ba12a
MM		 185/*
186 * 0: readable
187 * 1: writable
188 * 2-6: reserved
189 * 7: super page
9cf06697
SY		 190 * 8-10: available
191 * 11: snoop behavior
622ba12a
MM		 192 * 12-63: Host physcial address
193 */
194struct dma_pte {
195 u64 val;
196};
622ba12a 197
19c239ce
MM		 198static inline void dma_clear_pte(struct dma_pte *pte)
199{
200 pte->val = 0;
201}
202
203static inline void dma_set_pte_readable(struct dma_pte *pte)
204{
205 pte->val |= DMA_PTE_READ;
206}
207
208static inline void dma_set_pte_writable(struct dma_pte *pte)
209{
210 pte->val |= DMA_PTE_WRITE;
211}
212
9cf06697
SY		 213static inline void dma_set_pte_snp(struct dma_pte *pte)
214{
215 pte->val |= DMA_PTE_SNP;
216}
217
19c239ce
MM		 218static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
219{
220 pte->val = (pte->val & ~3) | (prot & 3);
221}
222
223static inline u64 dma_pte_addr(struct dma_pte *pte)
224{
c85994e4
DW		 225#ifdef CONFIG_64BIT
226 return pte->val & VTD_PAGE_MASK;
227#else
228 /* Must have a full atomic 64-bit read */
229 return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
230#endif
19c239ce
MM		 231}
232
dd4e8319 233static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
19c239ce 234{
dd4e8319 235 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
19c239ce
MM		 236}
237
238static inline bool dma_pte_present(struct dma_pte *pte)
239{
240 return (pte->val & 3) != 0;
241}
622ba12a 242
2c2e2c38
FY		 243/*
244 * This domain is a statically identity mapping domain.
245 * 1. This domain creats a static 1:1 mapping to all usable memory.
246 * 2. It maps to each iommu if successful.
247 * 3. Each iommu mapps to this domain if successful.
248 */
249struct dmar_domain *si_domain;
250
3b5410e7 251/* devices under the same p2p bridge are owned in one domain */
cdc7b837 252#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 253
1ce28feb
WH		 254/* domain represents a virtual machine, more than one devices
255 * across iommus may be owned in one domain, e.g. kvm guest.
256 */
257#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
258
2c2e2c38
FY		 259/* si_domain contains mulitple devices */
260#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
261
99126f7c
MM		 262struct dmar_domain {
263 int id; /* domain id */
8c11e798 264 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
99126f7c
MM		 265
266 struct list_head devices; /* all devices' list */
267 struct iova_domain iovad; /* iova's that belong to this domain */
268
269 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 270 int gaw; /* max guest address width */
271
272 /* adjusted guest address width, 0 is level 2 30-bit */
273 int agaw;
274
3b5410e7 275 int flags; /* flags to find out type of domain */
8e604097
WH		 276
277 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 278 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d
WH		 279 int iommu_count; /* reference count of iommu */
280 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 281 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 282};
283
a647dacb
MM		 284/* PCI domain-device relationship */
285struct device_domain_info {
286 struct list_head link; /* link to domain siblings */
287 struct list_head global; /* link to global list */
276dbf99
DW		 288 int segment; /* PCI domain */
289 u8 bus; /* PCI bus number */
a647dacb
MM		 290 u8 devfn; /* PCI devfn number */
291 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
93a23a72 292 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 293 struct dmar_domain *domain; /* pointer to domain */
294};
295
5e0d2a6f 296static void flush_unmaps_timeout(unsigned long data);
297
298DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
299
80b20dd8 300#define HIGH_WATER_MARK 250
301struct deferred_flush_tables {
302 int next;
303 struct iova *iova[HIGH_WATER_MARK];
304 struct dmar_domain *domain[HIGH_WATER_MARK];
305};
306
307static struct deferred_flush_tables *deferred_flush;
308
5e0d2a6f 309/* bitmap for indexing intel_iommus */
5e0d2a6f 310static int g_num_of_iommus;
311
312static DEFINE_SPINLOCK(async_umap_flush_lock);
313static LIST_HEAD(unmaps_to_do);
314
315static int timer_on;
316static long list_size;
5e0d2a6f 317
ba395927
KA		 318static void domain_remove_dev_info(struct dmar_domain *domain);
319
0cd5c3c8
KM		 320#ifdef CONFIG_DMAR_DEFAULT_ON
321int dmar_disabled = 0;
322#else
323int dmar_disabled = 1;
324#endif /*CONFIG_DMAR_DEFAULT_ON*/
325
ba395927 326static int __initdata dmar_map_gfx = 1;
7d3b03ce 327static int dmar_forcedac;
5e0d2a6f 328static int intel_iommu_strict;
ba395927
KA		 329
330#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
331static DEFINE_SPINLOCK(device_domain_lock);
332static LIST_HEAD(device_domain_list);
333
a8bcbb0d
JR		 334static struct iommu_ops intel_iommu_ops;
335
ba395927
KA		 336static int __init intel_iommu_setup(char *str)
337{
338 if (!str)
339 return -EINVAL;
340 while (*str) {
0cd5c3c8
KM		 341 if (!strncmp(str, "on", 2)) {
342 dmar_disabled = 0;
343 printk(KERN_INFO "Intel-IOMMU: enabled\n");
344 } else if (!strncmp(str, "off", 3)) {
ba395927 345 dmar_disabled = 1;
0cd5c3c8 346 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 347 } else if (!strncmp(str, "igfx_off", 8)) {
348 dmar_map_gfx = 0;
349 printk(KERN_INFO
350 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 351 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 352 printk(KERN_INFO
7d3b03ce
KA		 353 "Intel-IOMMU: Forcing DAC for PCI devices\n");
354 dmar_forcedac = 1;
5e0d2a6f 355 } else if (!strncmp(str, "strict", 6)) {
356 printk(KERN_INFO
357 "Intel-IOMMU: disable batched IOTLB flush\n");
358 intel_iommu_strict = 1;
ba395927
KA		 359 }
360
361 str += strcspn(str, ",");
362 while (*str == ',')
363 str++;
364 }
365 return 0;
366}
367__setup("intel_iommu=", intel_iommu_setup);
368
369static struct kmem_cache *iommu_domain_cache;
370static struct kmem_cache *iommu_devinfo_cache;
371static struct kmem_cache *iommu_iova_cache;
372
eb3fa7cb
KA		 373static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
374{
375 unsigned int flags;
376 void *vaddr;
377
378 /* trying to avoid low memory issues */
379 flags = current->flags & PF_MEMALLOC;
380 current->flags |= PF_MEMALLOC;
381 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
382 current->flags &= (~PF_MEMALLOC | flags);
383 return vaddr;
384}
385
386
ba395927
KA		 387static inline void *alloc_pgtable_page(void)
388{
eb3fa7cb
KA		 389 unsigned int flags;
390 void *vaddr;
391
392 /* trying to avoid low memory issues */
393 flags = current->flags & PF_MEMALLOC;
394 current->flags |= PF_MEMALLOC;
395 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
396 current->flags &= (~PF_MEMALLOC | flags);
397 return vaddr;
ba395927
KA		 398}
399
400static inline void free_pgtable_page(void *vaddr)
401{
402 free_page((unsigned long)vaddr);
403}
404
405static inline void *alloc_domain_mem(void)
406{
eb3fa7cb 407 return iommu_kmem_cache_alloc(iommu_domain_cache);
ba395927
KA		 408}
409
38717946 410static void free_domain_mem(void *vaddr)
ba395927
KA		 411{
412 kmem_cache_free(iommu_domain_cache, vaddr);
413}
414
415static inline void * alloc_devinfo_mem(void)
416{
eb3fa7cb 417 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
ba395927
KA		 418}
419
420static inline void free_devinfo_mem(void *vaddr)
421{
422 kmem_cache_free(iommu_devinfo_cache, vaddr);
423}
424
425struct iova *alloc_iova_mem(void)
426{
eb3fa7cb 427 return iommu_kmem_cache_alloc(iommu_iova_cache);
ba395927
KA		 428}
429
430void free_iova_mem(struct iova *iova)
431{
432 kmem_cache_free(iommu_iova_cache, iova);
433}
434
1b573683
WH		 435
436static inline int width_to_agaw(int width);
437
4ed0d3e6 438static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 439{
440 unsigned long sagaw;
441 int agaw = -1;
442
443 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 444 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 445 agaw >= 0; agaw--) {
446 if (test_bit(agaw, &sagaw))
447 break;
448 }
449
450 return agaw;
451}
452
4ed0d3e6
FY		 453/*
454 * Calculate max SAGAW for each iommu.
455 */
456int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
457{
458 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
459}
460
461/*
462 * calculate agaw for each iommu.
463 * "SAGAW" may be different across iommus, use a default agaw, and
464 * get a supported less agaw for iommus that don't support the default agaw.
465 */
466int iommu_calculate_agaw(struct intel_iommu *iommu)
467{
468 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
469}
470
2c2e2c38 471/* This functionin only returns single iommu in a domain */
8c11e798
WH		 472static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
473{
474 int iommu_id;
475
2c2e2c38 476 /* si_domain and vm domain should not get here. */
1ce28feb 477 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 478 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 479
8c11e798
WH		 480 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
481 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
482 return NULL;
483
484 return g_iommus[iommu_id];
485}
486
8e604097
WH		 487static void domain_update_iommu_coherency(struct dmar_domain *domain)
488{
489 int i;
490
491 domain->iommu_coherency = 1;
492
493 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
494 for (; i < g_num_of_iommus; ) {
495 if (!ecap_coherent(g_iommus[i]->ecap)) {
496 domain->iommu_coherency = 0;
497 break;
498 }
499 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
500 }
501}
502
58c610bd
SY		 503static void domain_update_iommu_snooping(struct dmar_domain *domain)
504{
505 int i;
506
507 domain->iommu_snooping = 1;
508
509 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
510 for (; i < g_num_of_iommus; ) {
511 if (!ecap_sc_support(g_iommus[i]->ecap)) {
512 domain->iommu_snooping = 0;
513 break;
514 }
515 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
516 }
517}
518
519/* Some capabilities may be different across iommus */
520static void domain_update_iommu_cap(struct dmar_domain *domain)
521{
522 domain_update_iommu_coherency(domain);
523 domain_update_iommu_snooping(domain);
524}
525
276dbf99 526static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 527{
528 struct dmar_drhd_unit *drhd = NULL;
529 int i;
530
531 for_each_drhd_unit(drhd) {
532 if (drhd->ignored)
533 continue;
276dbf99
DW		 534 if (segment != drhd->segment)
535 continue;
c7151a8d 536
924b6231 537 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 538 if (drhd->devices[i] &&
539 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 540 drhd->devices[i]->devfn == devfn)
541 return drhd->iommu;
4958c5dc
DW		 542 if (drhd->devices[i] &&
543 drhd->devices[i]->subordinate &&
924b6231
DW		 544 drhd->devices[i]->subordinate->number <= bus &&
545 drhd->devices[i]->subordinate->subordinate >= bus)
546 return drhd->iommu;
547 }
c7151a8d
WH		 548
549 if (drhd->include_all)
550 return drhd->iommu;
551 }
552
553 return NULL;
554}
555
5331fe6f
WH		 556static void domain_flush_cache(struct dmar_domain *domain,
557 void *addr, int size)
558{
559 if (!domain->iommu_coherency)
560 clflush_cache_range(addr, size);
561}
562
ba395927
KA		 563/* Gets context entry for a given bus and devfn */
564static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
565 u8 bus, u8 devfn)
566{
567 struct root_entry *root;
568 struct context_entry *context;
569 unsigned long phy_addr;
570 unsigned long flags;
571
572 spin_lock_irqsave(&iommu->lock, flags);
573 root = &iommu->root_entry[bus];
574 context = get_context_addr_from_root(root);
575 if (!context) {
576 context = (struct context_entry *)alloc_pgtable_page();
577 if (!context) {
578 spin_unlock_irqrestore(&iommu->lock, flags);
579 return NULL;
580 }
5b6985ce 581 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 582 phy_addr = virt_to_phys((void *)context);
583 set_root_value(root, phy_addr);
584 set_root_present(root);
585 __iommu_flush_cache(iommu, root, sizeof(*root));
586 }
587 spin_unlock_irqrestore(&iommu->lock, flags);
588 return &context[devfn];
589}
590
591static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
592{
593 struct root_entry *root;
594 struct context_entry *context;
595 int ret;
596 unsigned long flags;
597
598 spin_lock_irqsave(&iommu->lock, flags);
599 root = &iommu->root_entry[bus];
600 context = get_context_addr_from_root(root);
601 if (!context) {
602 ret = 0;
603 goto out;
604 }
c07e7d21 605 ret = context_present(&context[devfn]);
ba395927
KA		 606out:
607 spin_unlock_irqrestore(&iommu->lock, flags);
608 return ret;
609}
610
611static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
612{
613 struct root_entry *root;
614 struct context_entry *context;
615 unsigned long flags;
616
617 spin_lock_irqsave(&iommu->lock, flags);
618 root = &iommu->root_entry[bus];
619 context = get_context_addr_from_root(root);
620 if (context) {
c07e7d21 621 context_clear_entry(&context[devfn]);
ba395927
KA		 622 __iommu_flush_cache(iommu, &context[devfn], \
623 sizeof(*context));
624 }
625 spin_unlock_irqrestore(&iommu->lock, flags);
626}
627
628static void free_context_table(struct intel_iommu *iommu)
629{
630 struct root_entry *root;
631 int i;
632 unsigned long flags;
633 struct context_entry *context;
634
635 spin_lock_irqsave(&iommu->lock, flags);
636 if (!iommu->root_entry) {
637 goto out;
638 }
639 for (i = 0; i < ROOT_ENTRY_NR; i++) {
640 root = &iommu->root_entry[i];
641 context = get_context_addr_from_root(root);
642 if (context)
643 free_pgtable_page(context);
644 }
645 free_pgtable_page(iommu->root_entry);
646 iommu->root_entry = NULL;
647out:
648 spin_unlock_irqrestore(&iommu->lock, flags);
649}
650
651/* page table handling */
652#define LEVEL_STRIDE (9)
653#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
654
655static inline int agaw_to_level(int agaw)
656{
657 return agaw + 2;
658}
659
660static inline int agaw_to_width(int agaw)
661{
662 return 30 + agaw * LEVEL_STRIDE;
663
664}
665
666static inline int width_to_agaw(int width)
667{
668 return (width - 30) / LEVEL_STRIDE;
669}
670
671static inline unsigned int level_to_offset_bits(int level)
672{
6660c63a 673 return (level - 1) * LEVEL_STRIDE;
ba395927
KA		 674}
675
77dfa56c 676static inline int pfn_level_offset(unsigned long pfn, int level)
ba395927 677{
6660c63a 678 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
ba395927
KA		 679}
680
6660c63a 681static inline unsigned long level_mask(int level)
ba395927 682{
6660c63a 683 return -1UL << level_to_offset_bits(level);
ba395927
KA		 684}
685
6660c63a 686static inline unsigned long level_size(int level)
ba395927 687{
6660c63a 688 return 1UL << level_to_offset_bits(level);
ba395927
KA		 689}
690
6660c63a 691static inline unsigned long align_to_level(unsigned long pfn, int level)
ba395927 692{
6660c63a 693 return (pfn + level_size(level) - 1) & level_mask(level);
ba395927
KA		 694}
695
b026fd28
DW		 696static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
697 unsigned long pfn)
ba395927 698{
b026fd28 699 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 700 struct dma_pte *parent, *pte = NULL;
701 int level = agaw_to_level(domain->agaw);
702 int offset;
ba395927
KA		 703
704 BUG_ON(!domain->pgd);
b026fd28 705 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
ba395927
KA		 706 parent = domain->pgd;
707
ba395927
KA		 708 while (level > 0) {
709 void *tmp_page;
710
b026fd28 711 offset = pfn_level_offset(pfn, level);
ba395927
KA		 712 pte = &parent[offset];
713 if (level == 1)
714 break;
715
19c239ce 716 if (!dma_pte_present(pte)) {
c85994e4
DW		 717 uint64_t pteval;
718
ba395927
KA		 719 tmp_page = alloc_pgtable_page();
720
206a73c1 721 if (!tmp_page)
ba395927 722 return NULL;
206a73c1 723
c85994e4
DW		 724 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
725 pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
726 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
727 /* Someone else set it while we were thinking; use theirs. */
728 free_pgtable_page(tmp_page);
729 } else {
730 dma_pte_addr(pte);
731 domain_flush_cache(domain, pte, sizeof(*pte));
732 }
ba395927 733 }
19c239ce 734 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 735 level--;
736 }
737
ba395927
KA		 738 return pte;
739}
740
741/* return address's pte at specific level */
90dcfb5e
DW		 742static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
743 unsigned long pfn,
744 int level)
ba395927
KA		 745{
746 struct dma_pte *parent, *pte = NULL;
747 int total = agaw_to_level(domain->agaw);
748 int offset;
749
750 parent = domain->pgd;
751 while (level <= total) {
90dcfb5e 752 offset = pfn_level_offset(pfn, total);
ba395927
KA		 753 pte = &parent[offset];
754 if (level == total)
755 return pte;
756
19c239ce 757 if (!dma_pte_present(pte))
ba395927 758 break;
19c239ce 759 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 760 total--;
761 }
762 return NULL;
763}
764
ba395927 765/* clear last level pte, a tlb flush should be followed */
595badf5
DW		 766static void dma_pte_clear_range(struct dmar_domain *domain,
767 unsigned long start_pfn,
768 unsigned long last_pfn)
ba395927 769{
04b18e65 770 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
310a5ab9 771 struct dma_pte *first_pte, *pte;
66eae846 772
04b18e65 773 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 774 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
ba395927 775
04b18e65 776 /* we don't need lock here; nobody else touches the iova range */
595badf5 777 while (start_pfn <= last_pfn) {
310a5ab9
DW		 778 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
779 if (!pte) {
780 start_pfn = align_to_level(start_pfn + 1, 2);
781 continue;
782 }
783 while (start_pfn <= last_pfn &&
784 (unsigned long)pte >> VTD_PAGE_SHIFT ==
785 (unsigned long)first_pte >> VTD_PAGE_SHIFT) {
786 dma_clear_pte(pte);
787 start_pfn++;
788 pte++;
789 }
790 domain_flush_cache(domain, first_pte,
791 (void *)pte - (void *)first_pte);
ba395927
KA		 792 }
793}
794
795/* free page table pages. last level pte should already be cleared */
796static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 797 unsigned long start_pfn,
798 unsigned long last_pfn)
ba395927 799{
6660c63a 800 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
f3a0a52f 801 struct dma_pte *first_pte, *pte;
ba395927
KA		 802 int total = agaw_to_level(domain->agaw);
803 int level;
6660c63a 804 unsigned long tmp;
ba395927 805
6660c63a
DW		 806 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
807 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
ba395927 808
f3a0a52f 809 /* We don't need lock here; nobody else touches the iova range */
ba395927
KA		 810 level = 2;
811 while (level <= total) {
6660c63a
DW		 812 tmp = align_to_level(start_pfn, level);
813
f3a0a52f 814 /* If we can't even clear one PTE at this level, we're done */
6660c63a 815 if (tmp + level_size(level) - 1 > last_pfn)
ba395927
KA		 816 return;
817
3d7b0e41 818 while (tmp + level_size(level) - 1 <= last_pfn) {
f3a0a52f
DW		 819 first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
820 if (!pte) {
821 tmp = align_to_level(tmp + 1, level + 1);
822 continue;
823 }
824 while (tmp + level_size(level) - 1 <= last_pfn &&
825 (unsigned long)pte >> VTD_PAGE_SHIFT ==
826 (unsigned long)first_pte >> VTD_PAGE_SHIFT) {
827 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
19c239ce 828 dma_clear_pte(pte);
f3a0a52f
DW		 829 pte++;
830 tmp += level_size(level);
ba395927 831 }
f3a0a52f
DW		 832 domain_flush_cache(domain, first_pte,
833 (void *)pte - (void *)first_pte);
834
ba395927
KA		 835 }
836 level++;
837 }
838 /* free pgd */
d794dc9b 839 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 840 free_pgtable_page(domain->pgd);
841 domain->pgd = NULL;
842 }
843}
844
845/* iommu handling */
846static int iommu_alloc_root_entry(struct intel_iommu *iommu)
847{
848 struct root_entry *root;
849 unsigned long flags;
850
851 root = (struct root_entry *)alloc_pgtable_page();
852 if (!root)
853 return -ENOMEM;
854
5b6985ce 855 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 856
857 spin_lock_irqsave(&iommu->lock, flags);
858 iommu->root_entry = root;
859 spin_unlock_irqrestore(&iommu->lock, flags);
860
861 return 0;
862}
863
ba395927
KA		 864static void iommu_set_root_entry(struct intel_iommu *iommu)
865{
866 void *addr;
c416daa9 867 u32 sts;
ba395927
KA		 868 unsigned long flag;
869
870 addr = iommu->root_entry;
871
872 spin_lock_irqsave(&iommu->register_lock, flag);
873 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
874
c416daa9 875 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 876
877 /* Make sure hardware complete it */
878 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 879 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927
KA		 880
881 spin_unlock_irqrestore(&iommu->register_lock, flag);
882}
883
884static void iommu_flush_write_buffer(struct intel_iommu *iommu)
885{
886 u32 val;
887 unsigned long flag;
888
9af88143 889 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 890 return;
ba395927
KA		 891
892 spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 893 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 894
895 /* Make sure hardware complete it */
896 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 897 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927
KA		 898
899 spin_unlock_irqrestore(&iommu->register_lock, flag);
900}
901
902/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 903static void __iommu_flush_context(struct intel_iommu *iommu,
904 u16 did, u16 source_id, u8 function_mask,
905 u64 type)
ba395927
KA		 906{
907 u64 val = 0;
908 unsigned long flag;
909
ba395927
KA		 910 switch (type) {
911 case DMA_CCMD_GLOBAL_INVL:
912 val = DMA_CCMD_GLOBAL_INVL;
913 break;
914 case DMA_CCMD_DOMAIN_INVL:
915 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
916 break;
917 case DMA_CCMD_DEVICE_INVL:
918 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
919 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
920 break;
921 default:
922 BUG();
923 }
924 val |= DMA_CCMD_ICC;
925
926 spin_lock_irqsave(&iommu->register_lock, flag);
927 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
928
929 /* Make sure hardware complete it */
930 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
931 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
932
933 spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 934}
935
ba395927 936/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 937static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
938 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 939{
940 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
941 u64 val = 0, val_iva = 0;
942 unsigned long flag;
943
ba395927
KA		 944 switch (type) {
945 case DMA_TLB_GLOBAL_FLUSH:
946 /* global flush doesn't need set IVA_REG */
947 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
948 break;
949 case DMA_TLB_DSI_FLUSH:
950 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
951 break;
952 case DMA_TLB_PSI_FLUSH:
953 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
954 /* Note: always flush non-leaf currently */
955 val_iva = size_order | addr;
956 break;
957 default:
958 BUG();
959 }
960 /* Note: set drain read/write */
961#if 0
962 /*
963 * This is probably to be super secure.. Looks like we can
964 * ignore it without any impact.
965 */
966 if (cap_read_drain(iommu->cap))
967 val |= DMA_TLB_READ_DRAIN;
968#endif
969 if (cap_write_drain(iommu->cap))
970 val |= DMA_TLB_WRITE_DRAIN;
971
972 spin_lock_irqsave(&iommu->register_lock, flag);
973 /* Note: Only uses first TLB reg currently */
974 if (val_iva)
975 dmar_writeq(iommu->reg + tlb_offset, val_iva);
976 dmar_writeq(iommu->reg + tlb_offset + 8, val);
977
978 /* Make sure hardware complete it */
979 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
980 dmar_readq, (!(val & DMA_TLB_IVT)), val);
981
982 spin_unlock_irqrestore(&iommu->register_lock, flag);
983
984 /* check IOTLB invalidation granularity */
985 if (DMA_TLB_IAIG(val) == 0)
986 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
987 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
988 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 989 (unsigned long long)DMA_TLB_IIRG(type),
990 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 991}
992
93a23a72
YZ		 993static struct device_domain_info *iommu_support_dev_iotlb(
994 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
995{
996 int found = 0;
997 unsigned long flags;
998 struct device_domain_info *info;
999 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1000
1001 if (!ecap_dev_iotlb_support(iommu->ecap))
1002 return NULL;
1003
1004 if (!iommu->qi)
1005 return NULL;
1006
1007 spin_lock_irqsave(&device_domain_lock, flags);
1008 list_for_each_entry(info, &domain->devices, link)
1009 if (info->bus == bus && info->devfn == devfn) {
1010 found = 1;
1011 break;
1012 }
1013 spin_unlock_irqrestore(&device_domain_lock, flags);
1014
1015 if (!found || !info->dev)
1016 return NULL;
1017
1018 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1019 return NULL;
1020
1021 if (!dmar_find_matched_atsr_unit(info->dev))
1022 return NULL;
1023
1024 info->iommu = iommu;
1025
1026 return info;
1027}
1028
1029static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1030{
93a23a72
YZ		 1031 if (!info)
1032 return;
1033
1034 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1035}
1036
1037static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1038{
1039 if (!info->dev || !pci_ats_enabled(info->dev))
1040 return;
1041
1042 pci_disable_ats(info->dev);
1043}
1044
1045static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1046 u64 addr, unsigned mask)
1047{
1048 u16 sid, qdep;
1049 unsigned long flags;
1050 struct device_domain_info *info;
1051
1052 spin_lock_irqsave(&device_domain_lock, flags);
1053 list_for_each_entry(info, &domain->devices, link) {
1054 if (!info->dev || !pci_ats_enabled(info->dev))
1055 continue;
1056
1057 sid = info->bus << 8 | info->devfn;
1058 qdep = pci_ats_queue_depth(info->dev);
1059 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1060 }
1061 spin_unlock_irqrestore(&device_domain_lock, flags);
1062}
1063
1f0ef2aa 1064static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
03d6a246 1065 unsigned long pfn, unsigned int pages)
ba395927 1066{
9dd2fe89 1067 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1068 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1069
ba395927
KA		 1070 BUG_ON(pages == 0);
1071
ba395927 1072 /*
9dd2fe89
YZ		 1073 * Fallback to domain selective flush if no PSI support or the size is
1074 * too big.
ba395927
KA		 1075 * PSI requires page size to be 2 ^ x, and the base address is naturally
1076 * aligned to the size
1077 */
9dd2fe89
YZ		 1078 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1079 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1080 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1081 else
1082 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1083 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1084
1085 /*
1086 * In caching mode, domain ID 0 is reserved for non-present to present
1087 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1088 */
1089 if (!cap_caching_mode(iommu->cap) || did)
93a23a72 1090 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1091}
1092
f8bab735 1093static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1094{
1095 u32 pmen;
1096 unsigned long flags;
1097
1098 spin_lock_irqsave(&iommu->register_lock, flags);
1099 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1100 pmen &= ~DMA_PMEN_EPM;
1101 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1102
1103 /* wait for the protected region status bit to clear */
1104 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1105 readl, !(pmen & DMA_PMEN_PRS), pmen);
1106
1107 spin_unlock_irqrestore(&iommu->register_lock, flags);
1108}
1109
ba395927
KA		 1110static int iommu_enable_translation(struct intel_iommu *iommu)
1111{
1112 u32 sts;
1113 unsigned long flags;
1114
1115 spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1116 iommu->gcmd |= DMA_GCMD_TE;
1117 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1118
1119 /* Make sure hardware complete it */
1120 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1121 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1122
ba395927
KA		 1123 spin_unlock_irqrestore(&iommu->register_lock, flags);
1124 return 0;
1125}
1126
1127static int iommu_disable_translation(struct intel_iommu *iommu)
1128{
1129 u32 sts;
1130 unsigned long flag;
1131
1132 spin_lock_irqsave(&iommu->register_lock, flag);
1133 iommu->gcmd &= ~DMA_GCMD_TE;
1134 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1135
1136 /* Make sure hardware complete it */
1137 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1138 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927
KA		 1139
1140 spin_unlock_irqrestore(&iommu->register_lock, flag);
1141 return 0;
1142}
1143
3460a6d9 1144
ba395927
KA		 1145static int iommu_init_domains(struct intel_iommu *iommu)
1146{
1147 unsigned long ndomains;
1148 unsigned long nlongs;
1149
1150 ndomains = cap_ndoms(iommu->cap);
1151 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1152 nlongs = BITS_TO_LONGS(ndomains);
1153
1154 /* TBD: there might be 64K domains,
1155 * consider other allocation for future chip
1156 */
1157 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1158 if (!iommu->domain_ids) {
1159 printk(KERN_ERR "Allocating domain id array failed\n");
1160 return -ENOMEM;
1161 }
1162 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1163 GFP_KERNEL);
1164 if (!iommu->domains) {
1165 printk(KERN_ERR "Allocating domain array failed\n");
1166 kfree(iommu->domain_ids);
1167 return -ENOMEM;
1168 }
1169
e61d98d8
SS		 1170 spin_lock_init(&iommu->lock);
1171
ba395927
KA		 1172 /*
1173 * if Caching mode is set, then invalid translations are tagged
1174 * with domainid 0. Hence we need to pre-allocate it.
1175 */
1176 if (cap_caching_mode(iommu->cap))
1177 set_bit(0, iommu->domain_ids);
1178 return 0;
1179}
ba395927 1180
ba395927
KA		 1181
1182static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1183static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8
SS		 1184
1185void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1186{
1187 struct dmar_domain *domain;
1188 int i;
c7151a8d 1189 unsigned long flags;
ba395927 1190
ba395927
KA		 1191 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1192 for (; i < cap_ndoms(iommu->cap); ) {
1193 domain = iommu->domains[i];
1194 clear_bit(i, iommu->domain_ids);
c7151a8d
WH		 1195
1196 spin_lock_irqsave(&domain->iommu_lock, flags);
5e98c4b1
WH		 1197 if (--domain->iommu_count == 0) {
1198 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1199 vm_domain_exit(domain);
1200 else
1201 domain_exit(domain);
1202 }
c7151a8d
WH		 1203 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1204
ba395927
KA		 1205 i = find_next_bit(iommu->domain_ids,
1206 cap_ndoms(iommu->cap), i+1);
1207 }
1208
1209 if (iommu->gcmd & DMA_GCMD_TE)
1210 iommu_disable_translation(iommu);
1211
1212 if (iommu->irq) {
1213 set_irq_data(iommu->irq, NULL);
1214 /* This will mask the irq */
1215 free_irq(iommu->irq, iommu);
1216 destroy_irq(iommu->irq);
1217 }
1218
1219 kfree(iommu->domains);
1220 kfree(iommu->domain_ids);
1221
d9630fe9
WH		 1222 g_iommus[iommu->seq_id] = NULL;
1223
1224 /* if all iommus are freed, free g_iommus */
1225 for (i = 0; i < g_num_of_iommus; i++) {
1226 if (g_iommus[i])
1227 break;
1228 }
1229
1230 if (i == g_num_of_iommus)
1231 kfree(g_iommus);
1232
ba395927
KA		 1233 /* free context mapping */
1234 free_context_table(iommu);
ba395927
KA		 1235}
1236
2c2e2c38 1237static struct dmar_domain *alloc_domain(void)
ba395927 1238{
ba395927 1239 struct dmar_domain *domain;
ba395927
KA		 1240
1241 domain = alloc_domain_mem();
1242 if (!domain)
1243 return NULL;
1244
2c2e2c38
FY		 1245 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1246 domain->flags = 0;
1247
1248 return domain;
1249}
1250
1251static int iommu_attach_domain(struct dmar_domain *domain,
1252 struct intel_iommu *iommu)
1253{
1254 int num;
1255 unsigned long ndomains;
1256 unsigned long flags;
1257
ba395927
KA		 1258 ndomains = cap_ndoms(iommu->cap);
1259
1260 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1261
ba395927
KA		 1262 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1263 if (num >= ndomains) {
1264 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1265 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1266 return -ENOMEM;
ba395927
KA		 1267 }
1268
ba395927 1269 domain->id = num;
2c2e2c38 1270 set_bit(num, iommu->domain_ids);
8c11e798 1271 set_bit(iommu->seq_id, &domain->iommu_bmp);
ba395927
KA		 1272 iommu->domains[num] = domain;
1273 spin_unlock_irqrestore(&iommu->lock, flags);
1274
2c2e2c38 1275 return 0;
ba395927
KA		 1276}
1277
2c2e2c38
FY		 1278static void iommu_detach_domain(struct dmar_domain *domain,
1279 struct intel_iommu *iommu)
ba395927
KA		 1280{
1281 unsigned long flags;
2c2e2c38
FY		 1282 int num, ndomains;
1283 int found = 0;
ba395927 1284
8c11e798 1285 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38
FY		 1286 ndomains = cap_ndoms(iommu->cap);
1287 num = find_first_bit(iommu->domain_ids, ndomains);
1288 for (; num < ndomains; ) {
1289 if (iommu->domains[num] == domain) {
1290 found = 1;
1291 break;
1292 }
1293 num = find_next_bit(iommu->domain_ids,
1294 cap_ndoms(iommu->cap), num+1);
1295 }
1296
1297 if (found) {
1298 clear_bit(num, iommu->domain_ids);
1299 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1300 iommu->domains[num] = NULL;
1301 }
8c11e798 1302 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1303}
1304
1305static struct iova_domain reserved_iova_list;
8a443df4
MG		 1306static struct lock_class_key reserved_alloc_key;
1307static struct lock_class_key reserved_rbtree_key;
ba395927
KA		 1308
1309static void dmar_init_reserved_ranges(void)
1310{
1311 struct pci_dev *pdev = NULL;
1312 struct iova *iova;
1313 int i;
ba395927 1314
f661197e 1315 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1316
8a443df4
MG		 1317 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1318 &reserved_alloc_key);
1319 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1320 &reserved_rbtree_key);
1321
ba395927
KA		 1322 /* IOAPIC ranges shouldn't be accessed by DMA */
1323 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1324 IOVA_PFN(IOAPIC_RANGE_END));
1325 if (!iova)
1326 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1327
1328 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1329 for_each_pci_dev(pdev) {
1330 struct resource *r;
1331
1332 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1333 r = &pdev->resource[i];
1334 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1335 continue;
1a4a4551
DW		 1336 iova = reserve_iova(&reserved_iova_list,
1337 IOVA_PFN(r->start),
1338 IOVA_PFN(r->end));
ba395927
KA		 1339 if (!iova)
1340 printk(KERN_ERR "Reserve iova failed\n");
1341 }
1342 }
1343
1344}
1345
1346static void domain_reserve_special_ranges(struct dmar_domain *domain)
1347{
1348 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1349}
1350
1351static inline int guestwidth_to_adjustwidth(int gaw)
1352{
1353 int agaw;
1354 int r = (gaw - 12) % 9;
1355
1356 if (r == 0)
1357 agaw = gaw;
1358 else
1359 agaw = gaw + 9 - r;
1360 if (agaw > 64)
1361 agaw = 64;
1362 return agaw;
1363}
1364
1365static int domain_init(struct dmar_domain *domain, int guest_width)
1366{
1367 struct intel_iommu *iommu;
1368 int adjust_width, agaw;
1369 unsigned long sagaw;
1370
f661197e 1371 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
c7151a8d 1372 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1373
1374 domain_reserve_special_ranges(domain);
1375
1376 /* calculate AGAW */
8c11e798 1377 iommu = domain_get_iommu(domain);
ba395927
KA		 1378 if (guest_width > cap_mgaw(iommu->cap))
1379 guest_width = cap_mgaw(iommu->cap);
1380 domain->gaw = guest_width;
1381 adjust_width = guestwidth_to_adjustwidth(guest_width);
1382 agaw = width_to_agaw(adjust_width);
1383 sagaw = cap_sagaw(iommu->cap);
1384 if (!test_bit(agaw, &sagaw)) {
1385 /* hardware doesn't support it, choose a bigger one */
1386 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1387 agaw = find_next_bit(&sagaw, 5, agaw);
1388 if (agaw >= 5)
1389 return -ENODEV;
1390 }
1391 domain->agaw = agaw;
1392 INIT_LIST_HEAD(&domain->devices);
1393
8e604097
WH		 1394 if (ecap_coherent(iommu->ecap))
1395 domain->iommu_coherency = 1;
1396 else
1397 domain->iommu_coherency = 0;
1398
58c610bd
SY		 1399 if (ecap_sc_support(iommu->ecap))
1400 domain->iommu_snooping = 1;
1401 else
1402 domain->iommu_snooping = 0;
1403
c7151a8d
WH		 1404 domain->iommu_count = 1;
1405
ba395927
KA		 1406 /* always allocate the top pgd */
1407 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1408 if (!domain->pgd)
1409 return -ENOMEM;
5b6985ce 1410 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1411 return 0;
1412}
1413
1414static void domain_exit(struct dmar_domain *domain)
1415{
2c2e2c38
FY		 1416 struct dmar_drhd_unit *drhd;
1417 struct intel_iommu *iommu;
ba395927
KA		 1418
1419 /* Domain 0 is reserved, so dont process it */
1420 if (!domain)
1421 return;
1422
1423 domain_remove_dev_info(domain);
1424 /* destroy iovas */
1425 put_iova_domain(&domain->iovad);
ba395927
KA		 1426
1427 /* clear ptes */
595badf5 1428 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927
KA		 1429
1430 /* free page tables */
d794dc9b 1431 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1432
2c2e2c38
FY		 1433 for_each_active_iommu(iommu, drhd)
1434 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1435 iommu_detach_domain(domain, iommu);
1436
ba395927
KA		 1437 free_domain_mem(domain);
1438}
1439
4ed0d3e6
FY		 1440static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1441 u8 bus, u8 devfn, int translation)
ba395927
KA		 1442{
1443 struct context_entry *context;
ba395927 1444 unsigned long flags;
5331fe6f 1445 struct intel_iommu *iommu;
ea6606b0
WH		 1446 struct dma_pte *pgd;
1447 unsigned long num;
1448 unsigned long ndomains;
1449 int id;
1450 int agaw;
93a23a72 1451 struct device_domain_info *info = NULL;
ba395927
KA		 1452
1453 pr_debug("Set context mapping for %02x:%02x.%d\n",
1454 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1455
ba395927 1456 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1457 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1458 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1459
276dbf99 1460 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1461 if (!iommu)
1462 return -ENODEV;
1463
ba395927
KA		 1464 context = device_to_context_entry(iommu, bus, devfn);
1465 if (!context)
1466 return -ENOMEM;
1467 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1468 if (context_present(context)) {
ba395927
KA		 1469 spin_unlock_irqrestore(&iommu->lock, flags);
1470 return 0;
1471 }
1472
ea6606b0
WH		 1473 id = domain->id;
1474 pgd = domain->pgd;
1475
2c2e2c38
FY		 1476 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1477 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1478 int found = 0;
1479
1480 /* find an available domain id for this device in iommu */
1481 ndomains = cap_ndoms(iommu->cap);
1482 num = find_first_bit(iommu->domain_ids, ndomains);
1483 for (; num < ndomains; ) {
1484 if (iommu->domains[num] == domain) {
1485 id = num;
1486 found = 1;
1487 break;
1488 }
1489 num = find_next_bit(iommu->domain_ids,
1490 cap_ndoms(iommu->cap), num+1);
1491 }
1492
1493 if (found == 0) {
1494 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1495 if (num >= ndomains) {
1496 spin_unlock_irqrestore(&iommu->lock, flags);
1497 printk(KERN_ERR "IOMMU: no free domain ids\n");
1498 return -EFAULT;
1499 }
1500
1501 set_bit(num, iommu->domain_ids);
2c2e2c38 1502 set_bit(iommu->seq_id, &domain->iommu_bmp);
ea6606b0
WH		 1503 iommu->domains[num] = domain;
1504 id = num;
1505 }
1506
1507 /* Skip top levels of page tables for
1508 * iommu which has less agaw than default.
1509 */
1510 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1511 pgd = phys_to_virt(dma_pte_addr(pgd));
1512 if (!dma_pte_present(pgd)) {
1513 spin_unlock_irqrestore(&iommu->lock, flags);
1514 return -ENOMEM;
1515 }
1516 }
1517 }
1518
1519 context_set_domain_id(context, id);
4ed0d3e6 1520
93a23a72
YZ		 1521 if (translation != CONTEXT_TT_PASS_THROUGH) {
1522 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1523 translation = info ? CONTEXT_TT_DEV_IOTLB :
1524 CONTEXT_TT_MULTI_LEVEL;
1525 }
4ed0d3e6
FY		 1526 /*
1527 * In pass through mode, AW must be programmed to indicate the largest
1528 * AGAW value supported by hardware. And ASR is ignored by hardware.
1529 */
93a23a72 1530 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1531 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1532 else {
1533 context_set_address_root(context, virt_to_phys(pgd));
1534 context_set_address_width(context, iommu->agaw);
1535 }
4ed0d3e6
FY		 1536
1537 context_set_translation_type(context, translation);
c07e7d21
MM		 1538 context_set_fault_enable(context);
1539 context_set_present(context);
5331fe6f 1540 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1541
4c25a2c1
DW		 1542 /*
1543 * It's a non-present to present mapping. If hardware doesn't cache
1544 * non-present entry we only need to flush the write-buffer. If the
1545 * _does_ cache non-present entries, then it does so in the special
1546 * domain #0, which we have to flush:
1547 */
1548 if (cap_caching_mode(iommu->cap)) {
1549 iommu->flush.flush_context(iommu, 0,
1550 (((u16)bus) << 8) | devfn,
1551 DMA_CCMD_MASK_NOBIT,
1552 DMA_CCMD_DEVICE_INVL);
1f0ef2aa 1553 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1554 } else {
ba395927 1555 iommu_flush_write_buffer(iommu);
4c25a2c1 1556 }
93a23a72 1557 iommu_enable_dev_iotlb(info);
ba395927 1558 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1559
1560 spin_lock_irqsave(&domain->iommu_lock, flags);
1561 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1562 domain->iommu_count++;
58c610bd 1563 domain_update_iommu_cap(domain);
c7151a8d
WH		 1564 }
1565 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1566 return 0;
1567}
1568
1569static int
4ed0d3e6
FY		 1570domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1571 int translation)
ba395927
KA		 1572{
1573 int ret;
1574 struct pci_dev *tmp, *parent;
1575
276dbf99 1576 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1577 pdev->bus->number, pdev->devfn,
1578 translation);
ba395927
KA		 1579 if (ret)
1580 return ret;
1581
1582 /* dependent device mapping */
1583 tmp = pci_find_upstream_pcie_bridge(pdev);
1584 if (!tmp)
1585 return 0;
1586 /* Secondary interface's bus number and devfn 0 */
1587 parent = pdev->bus->self;
1588 while (parent != tmp) {
276dbf99
DW		 1589 ret = domain_context_mapping_one(domain,
1590 pci_domain_nr(parent->bus),
1591 parent->bus->number,
4ed0d3e6 1592 parent->devfn, translation);
ba395927
KA		 1593 if (ret)
1594 return ret;
1595 parent = parent->bus->self;
1596 }
1597 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1598 return domain_context_mapping_one(domain,
276dbf99 1599 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1600 tmp->subordinate->number, 0,
1601 translation);
ba395927
KA		 1602 else /* this is a legacy PCI bridge */
1603 return domain_context_mapping_one(domain,
276dbf99
DW		 1604 pci_domain_nr(tmp->bus),
1605 tmp->bus->number,
4ed0d3e6
FY		 1606 tmp->devfn,
1607 translation);
ba395927
KA		 1608}
1609
5331fe6f 1610static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1611{
1612 int ret;
1613 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1614 struct intel_iommu *iommu;
1615
276dbf99
DW		 1616 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1617 pdev->devfn);
5331fe6f
WH		 1618 if (!iommu)
1619 return -ENODEV;
ba395927 1620
276dbf99 1621 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1622 if (!ret)
1623 return ret;
1624 /* dependent device mapping */
1625 tmp = pci_find_upstream_pcie_bridge(pdev);
1626 if (!tmp)
1627 return ret;
1628 /* Secondary interface's bus number and devfn 0 */
1629 parent = pdev->bus->self;
1630 while (parent != tmp) {
8c11e798 1631 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1632 parent->devfn);
ba395927
KA		 1633 if (!ret)
1634 return ret;
1635 parent = parent->bus->self;
1636 }
1637 if (tmp->is_pcie)
276dbf99
DW		 1638 return device_context_mapped(iommu, tmp->subordinate->number,
1639 0);
ba395927 1640 else
276dbf99
DW		 1641 return device_context_mapped(iommu, tmp->bus->number,
1642 tmp->devfn);
ba395927
KA		 1643}
1644
9051aa02
DW		 1645static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1646 struct scatterlist *sg, unsigned long phys_pfn,
1647 unsigned long nr_pages, int prot)
e1605495
DW		 1648{
1649 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1650 phys_addr_t uninitialized_var(pteval);
e1605495 1651 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1652 unsigned long sg_res;
e1605495
DW		 1653
1654 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1655
1656 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1657 return -EINVAL;
1658
1659 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1660
9051aa02
DW		 1661 if (sg)
1662 sg_res = 0;
1663 else {
1664 sg_res = nr_pages + 1;
1665 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1666 }
1667
e1605495 1668 while (nr_pages--) {
c85994e4
DW		 1669 uint64_t tmp;
1670
e1605495
DW		 1671 if (!sg_res) {
1672 sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT;
1673 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1674 sg->dma_length = sg->length;
1675 pteval = page_to_phys(sg_page(sg)) | prot;
1676 }
1677 if (!pte) {
1678 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1679 if (!pte)
1680 return -ENOMEM;
1681 }
1682 /* We don't need lock here, nobody else
1683 * touches the iova range
1684 */
7766a3fb 1685 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 1686 if (tmp) {
1bf20f0d 1687 static int dumps = 5;
c85994e4
DW		 1688 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1689 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 1690 if (dumps) {
1691 dumps--;
1692 debug_dma_dump_mappings(NULL);
1693 }
1694 WARN_ON(1);
1695 }
e1605495
DW		 1696 pte++;
1697 if (!nr_pages ||
1698 (unsigned long)pte >> VTD_PAGE_SHIFT !=
1699 (unsigned long)first_pte >> VTD_PAGE_SHIFT) {
1700 domain_flush_cache(domain, first_pte,
1701 (void *)pte - (void *)first_pte);
1702 pte = NULL;
1703 }
1704 iov_pfn++;
1705 pteval += VTD_PAGE_SIZE;
1706 sg_res--;
1707 if (!sg_res)
1708 sg = sg_next(sg);
1709 }
1710 return 0;
1711}
1712
9051aa02
DW		 1713static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1714 struct scatterlist *sg, unsigned long nr_pages,
1715 int prot)
ba395927 1716{
9051aa02
DW		 1717 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1718}
6f6a00e4 1719
9051aa02
DW		 1720static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1721 unsigned long phys_pfn, unsigned long nr_pages,
1722 int prot)
1723{
1724 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 1725}
1726
c7151a8d 1727static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1728{
c7151a8d
WH		 1729 if (!iommu)
1730 return;
8c11e798
WH		 1731
1732 clear_context_table(iommu, bus, devfn);
1733 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1734 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1735 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1736}
1737
1738static void domain_remove_dev_info(struct dmar_domain *domain)
1739{
1740 struct device_domain_info *info;
1741 unsigned long flags;
c7151a8d 1742 struct intel_iommu *iommu;
ba395927
KA		 1743
1744 spin_lock_irqsave(&device_domain_lock, flags);
1745 while (!list_empty(&domain->devices)) {
1746 info = list_entry(domain->devices.next,
1747 struct device_domain_info, link);
1748 list_del(&info->link);
1749 list_del(&info->global);
1750 if (info->dev)
358dd8ac 1751 info->dev->dev.archdata.iommu = NULL;
ba395927
KA		 1752 spin_unlock_irqrestore(&device_domain_lock, flags);
1753
93a23a72 1754 iommu_disable_dev_iotlb(info);
276dbf99 1755 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1756 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1757 free_devinfo_mem(info);
1758
1759 spin_lock_irqsave(&device_domain_lock, flags);
1760 }
1761 spin_unlock_irqrestore(&device_domain_lock, flags);
1762}
1763
1764/*
1765 * find_domain
358dd8ac 1766 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1767 */
38717946 1768static struct dmar_domain *
ba395927
KA		 1769find_domain(struct pci_dev *pdev)
1770{
1771 struct device_domain_info *info;
1772
1773 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1774 info = pdev->dev.archdata.iommu;
ba395927
KA		 1775 if (info)
1776 return info->domain;
1777 return NULL;
1778}
1779
ba395927
KA		 1780/* domain is initialized */
1781static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1782{
1783 struct dmar_domain *domain, *found = NULL;
1784 struct intel_iommu *iommu;
1785 struct dmar_drhd_unit *drhd;
1786 struct device_domain_info *info, *tmp;
1787 struct pci_dev *dev_tmp;
1788 unsigned long flags;
1789 int bus = 0, devfn = 0;
276dbf99 1790 int segment;
2c2e2c38 1791 int ret;
ba395927
KA		 1792
1793 domain = find_domain(pdev);
1794 if (domain)
1795 return domain;
1796
276dbf99
DW		 1797 segment = pci_domain_nr(pdev->bus);
1798
ba395927
KA		 1799 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1800 if (dev_tmp) {
1801 if (dev_tmp->is_pcie) {
1802 bus = dev_tmp->subordinate->number;
1803 devfn = 0;
1804 } else {
1805 bus = dev_tmp->bus->number;
1806 devfn = dev_tmp->devfn;
1807 }
1808 spin_lock_irqsave(&device_domain_lock, flags);
1809 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1810 if (info->segment == segment &&
1811 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1812 found = info->domain;
1813 break;
1814 }
1815 }
1816 spin_unlock_irqrestore(&device_domain_lock, flags);
1817 /* pcie-pci bridge already has a domain, uses it */
1818 if (found) {
1819 domain = found;
1820 goto found_domain;
1821 }
1822 }
1823
2c2e2c38
FY		 1824 domain = alloc_domain();
1825 if (!domain)
1826 goto error;
1827
ba395927
KA		 1828 /* Allocate new domain for the device */
1829 drhd = dmar_find_matched_drhd_unit(pdev);
1830 if (!drhd) {
1831 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1832 pci_name(pdev));
1833 return NULL;
1834 }
1835 iommu = drhd->iommu;
1836
2c2e2c38
FY		 1837 ret = iommu_attach_domain(domain, iommu);
1838 if (ret) {
1839 domain_exit(domain);
ba395927 1840 goto error;
2c2e2c38 1841 }
ba395927
KA		 1842
1843 if (domain_init(domain, gaw)) {
1844 domain_exit(domain);
1845 goto error;
1846 }
1847
1848 /* register pcie-to-pci device */
1849 if (dev_tmp) {
1850 info = alloc_devinfo_mem();
1851 if (!info) {
1852 domain_exit(domain);
1853 goto error;
1854 }
276dbf99 1855 info->segment = segment;
ba395927
KA		 1856 info->bus = bus;
1857 info->devfn = devfn;
1858 info->dev = NULL;
1859 info->domain = domain;
1860 /* This domain is shared by devices under p2p bridge */
3b5410e7 1861 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 1862
1863 /* pcie-to-pci bridge already has a domain, uses it */
1864 found = NULL;
1865 spin_lock_irqsave(&device_domain_lock, flags);
1866 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 1867 if (tmp->segment == segment &&
1868 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 1869 found = tmp->domain;
1870 break;
1871 }
1872 }
1873 if (found) {
1874 free_devinfo_mem(info);
1875 domain_exit(domain);
1876 domain = found;
1877 } else {
1878 list_add(&info->link, &domain->devices);
1879 list_add(&info->global, &device_domain_list);
1880 }
1881 spin_unlock_irqrestore(&device_domain_lock, flags);
1882 }
1883
1884found_domain:
1885 info = alloc_devinfo_mem();
1886 if (!info)
1887 goto error;
276dbf99 1888 info->segment = segment;
ba395927
KA		 1889 info->bus = pdev->bus->number;
1890 info->devfn = pdev->devfn;
1891 info->dev = pdev;
1892 info->domain = domain;
1893 spin_lock_irqsave(&device_domain_lock, flags);
1894 /* somebody is fast */
1895 found = find_domain(pdev);
1896 if (found != NULL) {
1897 spin_unlock_irqrestore(&device_domain_lock, flags);
1898 if (found != domain) {
1899 domain_exit(domain);
1900 domain = found;
1901 }
1902 free_devinfo_mem(info);
1903 return domain;
1904 }
1905 list_add(&info->link, &domain->devices);
1906 list_add(&info->global, &device_domain_list);
358dd8ac 1907 pdev->dev.archdata.iommu = info;
ba395927
KA		 1908 spin_unlock_irqrestore(&device_domain_lock, flags);
1909 return domain;
1910error:
1911 /* recheck it here, maybe others set it */
1912 return find_domain(pdev);
1913}
1914
2c2e2c38
FY		 1915static int iommu_identity_mapping;
1916
b213203e
DW		 1917static int iommu_domain_identity_map(struct dmar_domain *domain,
1918 unsigned long long start,
1919 unsigned long long end)
ba395927 1920{
c5395d5c
DW		 1921 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1922 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1923
1924 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1925 dma_to_mm_pfn(last_vpfn))) {
ba395927 1926 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 1927 return -ENOMEM;
ba395927
KA		 1928 }
1929
c5395d5c
DW		 1930 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1931 start, end, domain->id);
ba395927
KA		 1932 /*
1933 * RMRR range might have overlap with physical memory range,
1934 * clear it first
1935 */
c5395d5c 1936 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 1937
c5395d5c
DW		 1938 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1939 last_vpfn - first_vpfn + 1,
61df7443 1940 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 1941}
1942
1943static int iommu_prepare_identity_map(struct pci_dev *pdev,
1944 unsigned long long start,
1945 unsigned long long end)
1946{
1947 struct dmar_domain *domain;
1948 int ret;
1949
1950 printk(KERN_INFO
1951 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1952 pci_name(pdev), start, end);
1953
c7ab48d2 1954 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 1955 if (!domain)
1956 return -ENOMEM;
1957
1958 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 1959 if (ret)
1960 goto error;
1961
1962 /* context entry init */
4ed0d3e6 1963 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 1964 if (ret)
1965 goto error;
1966
1967 return 0;
1968
1969 error:
ba395927
KA		 1970 domain_exit(domain);
1971 return ret;
ba395927
KA		 1972}
1973
1974static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1975 struct pci_dev *pdev)
1976{
358dd8ac 1977 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 1978 return 0;
1979 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1980 rmrr->end_address + 1);
1981}
1982
49a0429e
KA		 1983#ifdef CONFIG_DMAR_FLOPPY_WA
1984static inline void iommu_prepare_isa(void)
1985{
1986 struct pci_dev *pdev;
1987 int ret;
1988
1989 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1990 if (!pdev)
1991 return;
1992
c7ab48d2 1993 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
49a0429e
KA		 1994 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1995
1996 if (ret)
c7ab48d2
DW		 1997 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
1998 "floppy might not work\n");
49a0429e
KA		 1999
2000}
2001#else
2002static inline void iommu_prepare_isa(void)
2003{
2004 return;
2005}
2006#endif /* !CONFIG_DMAR_FLPY_WA */
2007
4ed0d3e6
FY		 2008/* Initialize each context entry as pass through.*/
2009static int __init init_context_pass_through(void)
2010{
2011 struct pci_dev *pdev = NULL;
2012 struct dmar_domain *domain;
2013 int ret;
2014
2015 for_each_pci_dev(pdev) {
2016 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2017 ret = domain_context_mapping(domain, pdev,
2018 CONTEXT_TT_PASS_THROUGH);
2019 if (ret)
2020 return ret;
2021 }
2022 return 0;
2023}
2024
2c2e2c38 2025static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2
DW		 2026
2027static int __init si_domain_work_fn(unsigned long start_pfn,
2028 unsigned long end_pfn, void *datax)
2029{
2030 int *ret = datax;
2031
2032 *ret = iommu_domain_identity_map(si_domain,
2033 (uint64_t)start_pfn << PAGE_SHIFT,
2034 (uint64_t)end_pfn << PAGE_SHIFT);
2035 return *ret;
2036
2037}
2038
2c2e2c38
FY		 2039static int si_domain_init(void)
2040{
2041 struct dmar_drhd_unit *drhd;
2042 struct intel_iommu *iommu;
c7ab48d2 2043 int nid, ret = 0;
2c2e2c38
FY		 2044
2045 si_domain = alloc_domain();
2046 if (!si_domain)
2047 return -EFAULT;
2048
c7ab48d2 2049 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2c2e2c38
FY		 2050
2051 for_each_active_iommu(iommu, drhd) {
2052 ret = iommu_attach_domain(si_domain, iommu);
2053 if (ret) {
2054 domain_exit(si_domain);
2055 return -EFAULT;
2056 }
2057 }
2058
2059 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2060 domain_exit(si_domain);
2061 return -EFAULT;
2062 }
2063
2064 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2065
c7ab48d2
DW		 2066 for_each_online_node(nid) {
2067 work_with_active_regions(nid, si_domain_work_fn, &ret);
2068 if (ret)
2069 return ret;
2070 }
2071
2c2e2c38
FY		 2072 return 0;
2073}
2074
2075static void domain_remove_one_dev_info(struct dmar_domain *domain,
2076 struct pci_dev *pdev);
2077static int identity_mapping(struct pci_dev *pdev)
2078{
2079 struct device_domain_info *info;
2080
2081 if (likely(!iommu_identity_mapping))
2082 return 0;
2083
2084
2085 list_for_each_entry(info, &si_domain->devices, link)
2086 if (info->dev == pdev)
2087 return 1;
2088 return 0;
2089}
2090
2091static int domain_add_dev_info(struct dmar_domain *domain,
2092 struct pci_dev *pdev)
2093{
2094 struct device_domain_info *info;
2095 unsigned long flags;
2096
2097 info = alloc_devinfo_mem();
2098 if (!info)
2099 return -ENOMEM;
2100
2101 info->segment = pci_domain_nr(pdev->bus);
2102 info->bus = pdev->bus->number;
2103 info->devfn = pdev->devfn;
2104 info->dev = pdev;
2105 info->domain = domain;
2106
2107 spin_lock_irqsave(&device_domain_lock, flags);
2108 list_add(&info->link, &domain->devices);
2109 list_add(&info->global, &device_domain_list);
2110 pdev->dev.archdata.iommu = info;
2111 spin_unlock_irqrestore(&device_domain_lock, flags);
2112
2113 return 0;
2114}
2115
2116static int iommu_prepare_static_identity_mapping(void)
2117{
2c2e2c38
FY		 2118 struct pci_dev *pdev = NULL;
2119 int ret;
2120
2121 ret = si_domain_init();
2122 if (ret)
2123 return -EFAULT;
2124
2c2e2c38 2125 for_each_pci_dev(pdev) {
c7ab48d2
DW		 2126 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2127 pci_name(pdev));
2128
2129 ret = domain_context_mapping(si_domain, pdev,
2130 CONTEXT_TT_MULTI_LEVEL);
2131 if (ret)
2132 return ret;
2c2e2c38
FY		 2133 ret = domain_add_dev_info(si_domain, pdev);
2134 if (ret)
2135 return ret;
2136 }
2137
2138 return 0;
2139}
2140
2141int __init init_dmars(void)
ba395927
KA		 2142{
2143 struct dmar_drhd_unit *drhd;
2144 struct dmar_rmrr_unit *rmrr;
2145 struct pci_dev *pdev;
2146 struct intel_iommu *iommu;
9d783ba0 2147 int i, ret;
4ed0d3e6 2148 int pass_through = 1;
ba395927 2149
2c2e2c38
FY		 2150 /*
2151 * In case pass through can not be enabled, iommu tries to use identity
2152 * mapping.
2153 */
2154 if (iommu_pass_through)
2155 iommu_identity_mapping = 1;
2156
ba395927
KA		 2157 /*
2158 * for each drhd
2159 * allocate root
2160 * initialize and program root entry to not present
2161 * endfor
2162 */
2163 for_each_drhd_unit(drhd) {
5e0d2a6f 2164 g_num_of_iommus++;
2165 /*
2166 * lock not needed as this is only incremented in the single
2167 * threaded kernel __init code path all other access are read
2168 * only
2169 */
2170 }
2171
d9630fe9
WH		 2172 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2173 GFP_KERNEL);
2174 if (!g_iommus) {
2175 printk(KERN_ERR "Allocating global iommu array failed\n");
2176 ret = -ENOMEM;
2177 goto error;
2178 }
2179
80b20dd8 2180 deferred_flush = kzalloc(g_num_of_iommus *
2181 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2182 if (!deferred_flush) {
d9630fe9 2183 kfree(g_iommus);
5e0d2a6f 2184 ret = -ENOMEM;
2185 goto error;
2186 }
2187
5e0d2a6f 2188 for_each_drhd_unit(drhd) {
2189 if (drhd->ignored)
2190 continue;
1886e8a9
SS		 2191
2192 iommu = drhd->iommu;
d9630fe9 2193 g_iommus[iommu->seq_id] = iommu;
ba395927 2194
e61d98d8
SS		 2195 ret = iommu_init_domains(iommu);
2196 if (ret)
2197 goto error;
2198
ba395927
KA		 2199 /*
2200 * TBD:
2201 * we could share the same root & context tables
2202 * amoung all IOMMU's. Need to Split it later.
2203 */
2204 ret = iommu_alloc_root_entry(iommu);
2205 if (ret) {
2206 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2207 goto error;
2208 }
4ed0d3e6
FY		 2209 if (!ecap_pass_through(iommu->ecap))
2210 pass_through = 0;
ba395927 2211 }
4ed0d3e6
FY		 2212 if (iommu_pass_through)
2213 if (!pass_through) {
2214 printk(KERN_INFO
2215 "Pass Through is not supported by hardware.\n");
2216 iommu_pass_through = 0;
2217 }
ba395927 2218
1531a6a6
SS		 2219 /*
2220 * Start from the sane iommu hardware state.
2221 */
a77b67d4
YS		 2222 for_each_drhd_unit(drhd) {
2223 if (drhd->ignored)
2224 continue;
2225
2226 iommu = drhd->iommu;
1531a6a6
SS		 2227
2228 /*
2229 * If the queued invalidation is already initialized by us
2230 * (for example, while enabling interrupt-remapping) then
2231 * we got the things already rolling from a sane state.
2232 */
2233 if (iommu->qi)
2234 continue;
2235
2236 /*
2237 * Clear any previous faults.
2238 */
2239 dmar_fault(-1, iommu);
2240 /*
2241 * Disable queued invalidation if supported and already enabled
2242 * before OS handover.
2243 */
2244 dmar_disable_qi(iommu);
2245 }
2246
2247 for_each_drhd_unit(drhd) {
2248 if (drhd->ignored)
2249 continue;
2250
2251 iommu = drhd->iommu;
2252
a77b67d4
YS		 2253 if (dmar_enable_qi(iommu)) {
2254 /*
2255 * Queued Invalidate not enabled, use Register Based
2256 * Invalidate
2257 */
2258 iommu->flush.flush_context = __iommu_flush_context;
2259 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2260 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
b4e0f9eb
FT		 2261 "invalidation\n",
2262 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2263 } else {
2264 iommu->flush.flush_context = qi_flush_context;
2265 iommu->flush.flush_iotlb = qi_flush_iotlb;
2266 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
b4e0f9eb
FT		 2267 "invalidation\n",
2268 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2269 }
2270 }
2271
ba395927 2272 /*
4ed0d3e6
FY		 2273 * If pass through is set and enabled, context entries of all pci
2274 * devices are intialized by pass through translation type.
ba395927 2275 */
4ed0d3e6
FY		 2276 if (iommu_pass_through) {
2277 ret = init_context_pass_through();
2278 if (ret) {
2279 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2280 iommu_pass_through = 0;
ba395927
KA		 2281 }
2282 }
2283
ba395927 2284 /*
4ed0d3e6 2285 * If pass through is not set or not enabled, setup context entries for
2c2e2c38
FY		 2286 * identity mappings for rmrr, gfx, and isa and may fall back to static
2287 * identity mapping if iommu_identity_mapping is set.
ba395927 2288 */
4ed0d3e6 2289 if (!iommu_pass_through) {
2c2e2c38
FY		 2290 if (iommu_identity_mapping)
2291 iommu_prepare_static_identity_mapping();
4ed0d3e6
FY		 2292 /*
2293 * For each rmrr
2294 * for each dev attached to rmrr
2295 * do
2296 * locate drhd for dev, alloc domain for dev
2297 * allocate free domain
2298 * allocate page table entries for rmrr
2299 * if context not allocated for bus
2300 * allocate and init context
2301 * set present in root table for this bus
2302 * init context with domain, translation etc
2303 * endfor
2304 * endfor
2305 */
2c2e2c38 2306 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
4ed0d3e6
FY		 2307 for_each_rmrr_units(rmrr) {
2308 for (i = 0; i < rmrr->devices_cnt; i++) {
2309 pdev = rmrr->devices[i];
2310 /*
2311 * some BIOS lists non-exist devices in DMAR
2312 * table.
2313 */
2314 if (!pdev)
2315 continue;
2316 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2317 if (ret)
2318 printk(KERN_ERR
ba395927 2319 "IOMMU: mapping reserved region failed\n");
4ed0d3e6 2320 }
ba395927 2321 }
ba395927 2322
4ed0d3e6
FY		 2323 iommu_prepare_isa();
2324 }
49a0429e 2325
ba395927
KA		 2326 /*
2327 * for each drhd
2328 * enable fault log
2329 * global invalidate context cache
2330 * global invalidate iotlb
2331 * enable translation
2332 */
2333 for_each_drhd_unit(drhd) {
2334 if (drhd->ignored)
2335 continue;
2336 iommu = drhd->iommu;
ba395927
KA		 2337
2338 iommu_flush_write_buffer(iommu);
2339
3460a6d9
KA		 2340 ret = dmar_set_interrupt(iommu);
2341 if (ret)
2342 goto error;
2343
ba395927
KA		 2344 iommu_set_root_entry(iommu);
2345
4c25a2c1 2346 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2347 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2348 iommu_disable_protect_mem_regions(iommu);
2349
ba395927
KA		 2350 ret = iommu_enable_translation(iommu);
2351 if (ret)
2352 goto error;
2353 }
2354
2355 return 0;
2356error:
2357 for_each_drhd_unit(drhd) {
2358 if (drhd->ignored)
2359 continue;
2360 iommu = drhd->iommu;
2361 free_iommu(iommu);
2362 }
d9630fe9 2363 kfree(g_iommus);
ba395927
KA		 2364 return ret;
2365}
2366
88cb6a74
DW		 2367static inline unsigned long aligned_nrpages(unsigned long host_addr,
2368 size_t size)
ba395927 2369{
88cb6a74
DW		 2370 host_addr &= ~PAGE_MASK;
2371 host_addr += size + PAGE_SIZE - 1;
2372
2373 return host_addr >> VTD_PAGE_SHIFT;
ba395927
KA		 2374}
2375
875764de
DW		 2376static struct iova *intel_alloc_iova(struct device *dev,
2377 struct dmar_domain *domain,
2378 unsigned long nrpages, uint64_t dma_mask)
ba395927 2379{
ba395927 2380 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2381 struct iova *iova = NULL;
ba395927 2382
875764de
DW		 2383 /* Restrict dma_mask to the width that the iommu can handle */
2384 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2385
2386 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2387 /*
2388 * First try to allocate an io virtual address in
284901a9 2389 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2390 * from higher range
ba395927 2391 */
875764de
DW		 2392 iova = alloc_iova(&domain->iovad, nrpages,
2393 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2394 if (iova)
2395 return iova;
2396 }
2397 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2398 if (unlikely(!iova)) {
2399 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2400 nrpages, pci_name(pdev));
f76aec76
KA		 2401 return NULL;
2402 }
2403
2404 return iova;
2405}
2406
2407static struct dmar_domain *
2408get_valid_domain_for_dev(struct pci_dev *pdev)
2409{
2410 struct dmar_domain *domain;
2411 int ret;
2412
2413 domain = get_domain_for_dev(pdev,
2414 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2415 if (!domain) {
2416 printk(KERN_ERR
2417 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2418 return NULL;
ba395927
KA		 2419 }
2420
2421 /* make sure context mapping is ok */
5331fe6f 2422 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2423 ret = domain_context_mapping(domain, pdev,
2424 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2425 if (ret) {
2426 printk(KERN_ERR
2427 "Domain context map for %s failed",
2428 pci_name(pdev));
4fe05bbc 2429 return NULL;
f76aec76 2430 }
ba395927
KA		 2431 }
2432
f76aec76
KA		 2433 return domain;
2434}
2435
2c2e2c38
FY		 2436static int iommu_dummy(struct pci_dev *pdev)
2437{
2438 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2439}
2440
2441/* Check if the pdev needs to go through non-identity map and unmap process.*/
2442static int iommu_no_mapping(struct pci_dev *pdev)
2443{
2444 int found;
2445
2446 if (!iommu_identity_mapping)
2447 return iommu_dummy(pdev);
2448
2449 found = identity_mapping(pdev);
2450 if (found) {
2451 if (pdev->dma_mask > DMA_BIT_MASK(32))
2452 return 1;
2453 else {
2454 /*
2455 * 32 bit DMA is removed from si_domain and fall back
2456 * to non-identity mapping.
2457 */
2458 domain_remove_one_dev_info(si_domain, pdev);
2459 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2460 pci_name(pdev));
2461 return 0;
2462 }
2463 } else {
2464 /*
2465 * In case of a detached 64 bit DMA device from vm, the device
2466 * is put into si_domain for identity mapping.
2467 */
2468 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2469 int ret;
2470 ret = domain_add_dev_info(si_domain, pdev);
2471 if (!ret) {
2472 printk(KERN_INFO "64bit %s uses identity mapping\n",
2473 pci_name(pdev));
2474 return 1;
2475 }
2476 }
2477 }
2478
2479 return iommu_dummy(pdev);
2480}
2481
bb9e6d65
FT		 2482static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2483 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2484{
2485 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2486 struct dmar_domain *domain;
5b6985ce 2487 phys_addr_t start_paddr;
f76aec76
KA		 2488 struct iova *iova;
2489 int prot = 0;
6865f0d1 2490 int ret;
8c11e798 2491 struct intel_iommu *iommu;
f76aec76
KA		 2492
2493 BUG_ON(dir == DMA_NONE);
2c2e2c38
FY		 2494
2495 if (iommu_no_mapping(pdev))
6865f0d1 2496 return paddr;
f76aec76
KA		 2497
2498 domain = get_valid_domain_for_dev(pdev);
2499 if (!domain)
2500 return 0;
2501
8c11e798 2502 iommu = domain_get_iommu(domain);
88cb6a74 2503 size = aligned_nrpages(paddr, size);
f76aec76 2504
875764de 2505 iova = intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
f76aec76
KA		 2506 if (!iova)
2507 goto error;
2508
ba395927
KA		 2509 /*
2510 * Check if DMAR supports zero-length reads on write only
2511 * mappings..
2512 */
2513 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2514 !cap_zlr(iommu->cap))
ba395927
KA		 2515 prot |= DMA_PTE_READ;
2516 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2517 prot |= DMA_PTE_WRITE;
2518 /*
6865f0d1 2519 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2520 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2521 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2522 * is not a big problem
2523 */
0ab36de2
DW		 2524 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2525 paddr >> VTD_PAGE_SHIFT, size, prot);
ba395927
KA		 2526 if (ret)
2527 goto error;
2528
1f0ef2aa
DW		 2529 /* it's a non-present to present mapping. Only flush if caching mode */
2530 if (cap_caching_mode(iommu->cap))
03d6a246 2531 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
1f0ef2aa 2532 else
8c11e798 2533 iommu_flush_write_buffer(iommu);
f76aec76 2534
03d6a246
DW		 2535 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2536 start_paddr += paddr & ~PAGE_MASK;
2537 return start_paddr;
ba395927 2538
ba395927 2539error:
f76aec76
KA		 2540 if (iova)
2541 __free_iova(&domain->iovad, iova);
4cf2e75d 2542 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2543 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2544 return 0;
2545}
2546
ffbbef5c
FT		 2547static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2548 unsigned long offset, size_t size,
2549 enum dma_data_direction dir,
2550 struct dma_attrs *attrs)
bb9e6d65 2551{
ffbbef5c
FT		 2552 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2553 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2554}
2555
5e0d2a6f 2556static void flush_unmaps(void)
2557{
80b20dd8 2558 int i, j;
5e0d2a6f 2559
5e0d2a6f 2560 timer_on = 0;
2561
2562 /* just flush them all */
2563 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2564 struct intel_iommu *iommu = g_iommus[i];
2565 if (!iommu)
2566 continue;
c42d9f32 2567
9dd2fe89
YZ		 2568 if (!deferred_flush[i].next)
2569 continue;
2570
2571 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2572 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2573 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2574 unsigned long mask;
2575 struct iova *iova = deferred_flush[i].iova[j];
2576
2577 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2578 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2579 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2580 iova->pfn_lo << PAGE_SHIFT, mask);
2581 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2582 }
9dd2fe89 2583 deferred_flush[i].next = 0;
5e0d2a6f 2584 }
2585
5e0d2a6f 2586 list_size = 0;
5e0d2a6f 2587}
2588
2589static void flush_unmaps_timeout(unsigned long data)
2590{
80b20dd8 2591 unsigned long flags;
2592
2593 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2594 flush_unmaps();
80b20dd8 2595 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2596}
2597
2598static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2599{
2600 unsigned long flags;
80b20dd8 2601 int next, iommu_id;
8c11e798 2602 struct intel_iommu *iommu;
5e0d2a6f 2603
2604 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2605 if (list_size == HIGH_WATER_MARK)
2606 flush_unmaps();
2607
8c11e798
WH		 2608 iommu = domain_get_iommu(dom);
2609 iommu_id = iommu->seq_id;
c42d9f32 2610
80b20dd8 2611 next = deferred_flush[iommu_id].next;
2612 deferred_flush[iommu_id].domain[next] = dom;
2613 deferred_flush[iommu_id].iova[next] = iova;
2614 deferred_flush[iommu_id].next++;
5e0d2a6f 2615
2616 if (!timer_on) {
2617 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2618 timer_on = 1;
2619 }
2620 list_size++;
2621 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2622}
2623
ffbbef5c
FT		 2624static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2625 size_t size, enum dma_data_direction dir,
2626 struct dma_attrs *attrs)
ba395927 2627{
ba395927 2628 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 2629 struct dmar_domain *domain;
d794dc9b 2630 unsigned long start_pfn, last_pfn;
ba395927 2631 struct iova *iova;
8c11e798 2632 struct intel_iommu *iommu;
ba395927 2633
2c2e2c38 2634 if (iommu_no_mapping(pdev))
f76aec76 2635 return;
2c2e2c38 2636
ba395927
KA		 2637 domain = find_domain(pdev);
2638 BUG_ON(!domain);
2639
8c11e798
WH		 2640 iommu = domain_get_iommu(domain);
2641
ba395927 2642 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 2643 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2644 (unsigned long long)dev_addr))
ba395927 2645 return;
ba395927 2646
d794dc9b
DW		 2647 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2648 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 2649
d794dc9b
DW		 2650 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2651 pci_name(pdev), start_pfn, last_pfn);
ba395927 2652
f76aec76 2653 /* clear the whole page */
d794dc9b
DW		 2654 dma_pte_clear_range(domain, start_pfn, last_pfn);
2655
f76aec76 2656 /* free page tables */
d794dc9b
DW		 2657 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2658
5e0d2a6f 2659 if (intel_iommu_strict) {
03d6a246 2660 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
d794dc9b 2661 last_pfn - start_pfn + 1);
5e0d2a6f 2662 /* free iova */
2663 __free_iova(&domain->iovad, iova);
2664 } else {
2665 add_unmap(domain, iova);
2666 /*
2667 * queue up the release of the unmap to save the 1/6th of the
2668 * cpu used up by the iotlb flush operation...
2669 */
5e0d2a6f 2670 }
ba395927
KA		 2671}
2672
d7ab5c46
FT		 2673static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2674 int dir)
ffbbef5c
FT		 2675{
2676 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2677}
2678
d7ab5c46
FT		 2679static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2680 dma_addr_t *dma_handle, gfp_t flags)
ba395927
KA		 2681{
2682 void *vaddr;
2683 int order;
2684
5b6985ce 2685 size = PAGE_ALIGN(size);
ba395927
KA		 2686 order = get_order(size);
2687 flags &= ~(GFP_DMA | GFP_DMA32);
2688
2689 vaddr = (void *)__get_free_pages(flags, order);
2690 if (!vaddr)
2691 return NULL;
2692 memset(vaddr, 0, size);
2693
bb9e6d65
FT		 2694 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2695 DMA_BIDIRECTIONAL,
2696 hwdev->coherent_dma_mask);
ba395927
KA		 2697 if (*dma_handle)
2698 return vaddr;
2699 free_pages((unsigned long)vaddr, order);
2700 return NULL;
2701}
2702
d7ab5c46
FT		 2703static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2704 dma_addr_t dma_handle)
ba395927
KA		 2705{
2706 int order;
2707
5b6985ce 2708 size = PAGE_ALIGN(size);
ba395927
KA		 2709 order = get_order(size);
2710
2711 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2712 free_pages((unsigned long)vaddr, order);
2713}
2714
d7ab5c46
FT		 2715static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2716 int nelems, enum dma_data_direction dir,
2717 struct dma_attrs *attrs)
ba395927 2718{
ba395927
KA		 2719 struct pci_dev *pdev = to_pci_dev(hwdev);
2720 struct dmar_domain *domain;
d794dc9b 2721 unsigned long start_pfn, last_pfn;
f76aec76 2722 struct iova *iova;
8c11e798 2723 struct intel_iommu *iommu;
ba395927 2724
2c2e2c38 2725 if (iommu_no_mapping(pdev))
ba395927
KA		 2726 return;
2727
2728 domain = find_domain(pdev);
8c11e798
WH		 2729 BUG_ON(!domain);
2730
2731 iommu = domain_get_iommu(domain);
ba395927 2732
c03ab37c 2733 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 2734 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2735 (unsigned long long)sglist[0].dma_address))
f76aec76 2736 return;
f76aec76 2737
d794dc9b
DW		 2738 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2739 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76
KA		 2740
2741 /* clear the whole page */
d794dc9b
DW		 2742 dma_pte_clear_range(domain, start_pfn, last_pfn);
2743
f76aec76 2744 /* free page tables */
d794dc9b 2745 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
f76aec76 2746
03d6a246 2747 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
d794dc9b 2748 (last_pfn - start_pfn + 1));
f76aec76
KA		 2749
2750 /* free iova */
2751 __free_iova(&domain->iovad, iova);
ba395927
KA		 2752}
2753
ba395927 2754static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 2755 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 2756{
2757 int i;
c03ab37c 2758 struct scatterlist *sg;
ba395927 2759
c03ab37c 2760 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 2761 BUG_ON(!sg_page(sg));
4cf2e75d 2762 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 2763 sg->dma_length = sg->length;
ba395927
KA		 2764 }
2765 return nelems;
2766}
2767
d7ab5c46
FT		 2768static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2769 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 2770{
ba395927 2771 int i;
ba395927
KA		 2772 struct pci_dev *pdev = to_pci_dev(hwdev);
2773 struct dmar_domain *domain;
f76aec76
KA		 2774 size_t size = 0;
2775 int prot = 0;
b536d24d 2776 size_t offset_pfn = 0;
f76aec76
KA		 2777 struct iova *iova = NULL;
2778 int ret;
c03ab37c 2779 struct scatterlist *sg;
b536d24d 2780 unsigned long start_vpfn;
8c11e798 2781 struct intel_iommu *iommu;
ba395927
KA		 2782
2783 BUG_ON(dir == DMA_NONE);
2c2e2c38 2784 if (iommu_no_mapping(pdev))
c03ab37c 2785 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 2786
f76aec76
KA		 2787 domain = get_valid_domain_for_dev(pdev);
2788 if (!domain)
2789 return 0;
2790
8c11e798
WH		 2791 iommu = domain_get_iommu(domain);
2792
b536d24d 2793 for_each_sg(sglist, sg, nelems, i)
88cb6a74 2794 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 2795
875764de 2796 iova = intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
f76aec76 2797 if (!iova) {
c03ab37c 2798 sglist->dma_length = 0;
f76aec76
KA		 2799 return 0;
2800 }
2801
2802 /*
2803 * Check if DMAR supports zero-length reads on write only
2804 * mappings..
2805 */
2806 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2807 !cap_zlr(iommu->cap))
f76aec76
KA		 2808 prot |= DMA_PTE_READ;
2809 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2810 prot |= DMA_PTE_WRITE;
2811
b536d24d 2812 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495
DW		 2813
2814 ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot);
2815 if (unlikely(ret)) {
2816 /* clear the page */
2817 dma_pte_clear_range(domain, start_vpfn,
2818 start_vpfn + size - 1);
2819 /* free page tables */
2820 dma_pte_free_pagetable(domain, start_vpfn,
2821 start_vpfn + size - 1);
2822 /* free iova */
2823 __free_iova(&domain->iovad, iova);
2824 return 0;
ba395927
KA		 2825 }
2826
1f0ef2aa
DW		 2827 /* it's a non-present to present mapping. Only flush if caching mode */
2828 if (cap_caching_mode(iommu->cap))
03d6a246 2829 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
1f0ef2aa 2830 else
8c11e798 2831 iommu_flush_write_buffer(iommu);
1f0ef2aa 2832
ba395927
KA		 2833 return nelems;
2834}
2835
dfb805e8
FT		 2836static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2837{
2838 return !dma_addr;
2839}
2840
160c1d8e 2841struct dma_map_ops intel_dma_ops = {
ba395927
KA		 2842 .alloc_coherent = intel_alloc_coherent,
2843 .free_coherent = intel_free_coherent,
ba395927
KA		 2844 .map_sg = intel_map_sg,
2845 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 2846 .map_page = intel_map_page,
2847 .unmap_page = intel_unmap_page,
dfb805e8 2848 .mapping_error = intel_mapping_error,
ba395927
KA		 2849};
2850
2851static inline int iommu_domain_cache_init(void)
2852{
2853 int ret = 0;
2854
2855 iommu_domain_cache = kmem_cache_create("iommu_domain",
2856 sizeof(struct dmar_domain),
2857 0,
2858 SLAB_HWCACHE_ALIGN,
2859
2860 NULL);
2861 if (!iommu_domain_cache) {
2862 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2863 ret = -ENOMEM;
2864 }
2865
2866 return ret;
2867}
2868
2869static inline int iommu_devinfo_cache_init(void)
2870{
2871 int ret = 0;
2872
2873 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2874 sizeof(struct device_domain_info),
2875 0,
2876 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2877 NULL);
2878 if (!iommu_devinfo_cache) {
2879 printk(KERN_ERR "Couldn't create devinfo cache\n");
2880 ret = -ENOMEM;
2881 }
2882
2883 return ret;
2884}
2885
2886static inline int iommu_iova_cache_init(void)
2887{
2888 int ret = 0;
2889
2890 iommu_iova_cache = kmem_cache_create("iommu_iova",
2891 sizeof(struct iova),
2892 0,
2893 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2894 NULL);
2895 if (!iommu_iova_cache) {
2896 printk(KERN_ERR "Couldn't create iova cache\n");
2897 ret = -ENOMEM;
2898 }
2899
2900 return ret;
2901}
2902
2903static int __init iommu_init_mempool(void)
2904{
2905 int ret;
2906 ret = iommu_iova_cache_init();
2907 if (ret)
2908 return ret;
2909
2910 ret = iommu_domain_cache_init();
2911 if (ret)
2912 goto domain_error;
2913
2914 ret = iommu_devinfo_cache_init();
2915 if (!ret)
2916 return ret;
2917
2918 kmem_cache_destroy(iommu_domain_cache);
2919domain_error:
2920 kmem_cache_destroy(iommu_iova_cache);
2921
2922 return -ENOMEM;
2923}
2924
2925static void __init iommu_exit_mempool(void)
2926{
2927 kmem_cache_destroy(iommu_devinfo_cache);
2928 kmem_cache_destroy(iommu_domain_cache);
2929 kmem_cache_destroy(iommu_iova_cache);
2930
2931}
2932
ba395927
KA		 2933static void __init init_no_remapping_devices(void)
2934{
2935 struct dmar_drhd_unit *drhd;
2936
2937 for_each_drhd_unit(drhd) {
2938 if (!drhd->include_all) {
2939 int i;
2940 for (i = 0; i < drhd->devices_cnt; i++)
2941 if (drhd->devices[i] != NULL)
2942 break;
2943 /* ignore DMAR unit if no pci devices exist */
2944 if (i == drhd->devices_cnt)
2945 drhd->ignored = 1;
2946 }
2947 }
2948
2949 if (dmar_map_gfx)
2950 return;
2951
2952 for_each_drhd_unit(drhd) {
2953 int i;
2954 if (drhd->ignored || drhd->include_all)
2955 continue;
2956
2957 for (i = 0; i < drhd->devices_cnt; i++)
2958 if (drhd->devices[i] &&
2959 !IS_GFX_DEVICE(drhd->devices[i]))
2960 break;
2961
2962 if (i < drhd->devices_cnt)
2963 continue;
2964
2965 /* bypass IOMMU if it is just for gfx devices */
2966 drhd->ignored = 1;
2967 for (i = 0; i < drhd->devices_cnt; i++) {
2968 if (!drhd->devices[i])
2969 continue;
358dd8ac 2970 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 2971 }
2972 }
2973}
2974
f59c7b69
FY		 2975#ifdef CONFIG_SUSPEND
2976static int init_iommu_hw(void)
2977{
2978 struct dmar_drhd_unit *drhd;
2979 struct intel_iommu *iommu = NULL;
2980
2981 for_each_active_iommu(iommu, drhd)
2982 if (iommu->qi)
2983 dmar_reenable_qi(iommu);
2984
2985 for_each_active_iommu(iommu, drhd) {
2986 iommu_flush_write_buffer(iommu);
2987
2988 iommu_set_root_entry(iommu);
2989
2990 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 2991 DMA_CCMD_GLOBAL_INVL);
f59c7b69 2992 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 2993 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 2994 iommu_disable_protect_mem_regions(iommu);
2995 iommu_enable_translation(iommu);
2996 }
2997
2998 return 0;
2999}
3000
3001static void iommu_flush_all(void)
3002{
3003 struct dmar_drhd_unit *drhd;
3004 struct intel_iommu *iommu;
3005
3006 for_each_active_iommu(iommu, drhd) {
3007 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3008 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3009 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3010 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3011 }
3012}
3013
3014static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3015{
3016 struct dmar_drhd_unit *drhd;
3017 struct intel_iommu *iommu = NULL;
3018 unsigned long flag;
3019
3020 for_each_active_iommu(iommu, drhd) {
3021 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3022 GFP_ATOMIC);
3023 if (!iommu->iommu_state)
3024 goto nomem;
3025 }
3026
3027 iommu_flush_all();
3028
3029 for_each_active_iommu(iommu, drhd) {
3030 iommu_disable_translation(iommu);
3031
3032 spin_lock_irqsave(&iommu->register_lock, flag);
3033
3034 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3035 readl(iommu->reg + DMAR_FECTL_REG);
3036 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3037 readl(iommu->reg + DMAR_FEDATA_REG);
3038 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3039 readl(iommu->reg + DMAR_FEADDR_REG);
3040 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3041 readl(iommu->reg + DMAR_FEUADDR_REG);
3042
3043 spin_unlock_irqrestore(&iommu->register_lock, flag);
3044 }
3045 return 0;
3046
3047nomem:
3048 for_each_active_iommu(iommu, drhd)
3049 kfree(iommu->iommu_state);
3050
3051 return -ENOMEM;
3052}
3053
3054static int iommu_resume(struct sys_device *dev)
3055{
3056 struct dmar_drhd_unit *drhd;
3057 struct intel_iommu *iommu = NULL;
3058 unsigned long flag;
3059
3060 if (init_iommu_hw()) {
3061 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3062 return -EIO;
3063 }
3064
3065 for_each_active_iommu(iommu, drhd) {
3066
3067 spin_lock_irqsave(&iommu->register_lock, flag);
3068
3069 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3070 iommu->reg + DMAR_FECTL_REG);
3071 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3072 iommu->reg + DMAR_FEDATA_REG);
3073 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3074 iommu->reg + DMAR_FEADDR_REG);
3075 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3076 iommu->reg + DMAR_FEUADDR_REG);
3077
3078 spin_unlock_irqrestore(&iommu->register_lock, flag);
3079 }
3080
3081 for_each_active_iommu(iommu, drhd)
3082 kfree(iommu->iommu_state);
3083
3084 return 0;
3085}
3086
3087static struct sysdev_class iommu_sysclass = {
3088 .name = "iommu",
3089 .resume = iommu_resume,
3090 .suspend = iommu_suspend,
3091};
3092
3093static struct sys_device device_iommu = {
3094 .cls = &iommu_sysclass,
3095};
3096
3097static int __init init_iommu_sysfs(void)
3098{
3099 int error;
3100
3101 error = sysdev_class_register(&iommu_sysclass);
3102 if (error)
3103 return error;
3104
3105 error = sysdev_register(&device_iommu);
3106 if (error)
3107 sysdev_class_unregister(&iommu_sysclass);
3108
3109 return error;
3110}
3111
3112#else
3113static int __init init_iommu_sysfs(void)
3114{
3115 return 0;
3116}
3117#endif /* CONFIG_PM */
3118
ba395927
KA		 3119int __init intel_iommu_init(void)
3120{
3121 int ret = 0;
3122
ba395927
KA		 3123 if (dmar_table_init())
3124 return -ENODEV;
3125
1886e8a9
SS		 3126 if (dmar_dev_scope_init())
3127 return -ENODEV;
3128
2ae21010
SS		 3129 /*
3130 * Check the need for DMA-remapping initialization now.
3131 * Above initialization will also be used by Interrupt-remapping.
3132 */
4ed0d3e6 3133 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
2ae21010
SS		 3134 return -ENODEV;
3135
ba395927
KA		 3136 iommu_init_mempool();
3137 dmar_init_reserved_ranges();
3138
3139 init_no_remapping_devices();
3140
3141 ret = init_dmars();
3142 if (ret) {
3143 printk(KERN_ERR "IOMMU: dmar init failed\n");
3144 put_iova_domain(&reserved_iova_list);
3145 iommu_exit_mempool();
3146 return ret;
3147 }
3148 printk(KERN_INFO
3149 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3150
5e0d2a6f 3151 init_timer(&unmap_timer);
ba395927 3152 force_iommu = 1;
4ed0d3e6
FY		 3153
3154 if (!iommu_pass_through) {
3155 printk(KERN_INFO
3156 "Multi-level page-table translation for DMAR.\n");
3157 dma_ops = &intel_dma_ops;
3158 } else
3159 printk(KERN_INFO
3160 "DMAR: Pass through translation for DMAR.\n");
3161
f59c7b69 3162 init_iommu_sysfs();
a8bcbb0d
JR		 3163
3164 register_iommu(&intel_iommu_ops);
3165
ba395927
KA		 3166 return 0;
3167}
e820482c 3168
3199aa6b
HW		 3169static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3170 struct pci_dev *pdev)
3171{
3172 struct pci_dev *tmp, *parent;
3173
3174 if (!iommu || !pdev)
3175 return;
3176
3177 /* dependent device detach */
3178 tmp = pci_find_upstream_pcie_bridge(pdev);
3179 /* Secondary interface's bus number and devfn 0 */
3180 if (tmp) {
3181 parent = pdev->bus->self;
3182 while (parent != tmp) {
3183 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3184 parent->devfn);
3199aa6b
HW		 3185 parent = parent->bus->self;
3186 }
3187 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3188 iommu_detach_dev(iommu,
3189 tmp->subordinate->number, 0);
3190 else /* this is a legacy PCI bridge */
276dbf99
DW		 3191 iommu_detach_dev(iommu, tmp->bus->number,
3192 tmp->devfn);
3199aa6b
HW		 3193 }
3194}
3195
2c2e2c38 3196static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3197 struct pci_dev *pdev)
3198{
3199 struct device_domain_info *info;
3200 struct intel_iommu *iommu;
3201 unsigned long flags;
3202 int found = 0;
3203 struct list_head *entry, *tmp;
3204
276dbf99
DW		 3205 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3206 pdev->devfn);
c7151a8d
WH		 3207 if (!iommu)
3208 return;
3209
3210 spin_lock_irqsave(&device_domain_lock, flags);
3211 list_for_each_safe(entry, tmp, &domain->devices) {
3212 info = list_entry(entry, struct device_domain_info, link);
276dbf99 3213 /* No need to compare PCI domain; it has to be the same */
c7151a8d
WH		 3214 if (info->bus == pdev->bus->number &&
3215 info->devfn == pdev->devfn) {
3216 list_del(&info->link);
3217 list_del(&info->global);
3218 if (info->dev)
3219 info->dev->dev.archdata.iommu = NULL;
3220 spin_unlock_irqrestore(&device_domain_lock, flags);
3221
93a23a72 3222 iommu_disable_dev_iotlb(info);
c7151a8d 3223 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3224 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3225 free_devinfo_mem(info);
3226
3227 spin_lock_irqsave(&device_domain_lock, flags);
3228
3229 if (found)
3230 break;
3231 else
3232 continue;
3233 }
3234
3235 /* if there is no other devices under the same iommu
3236 * owned by this domain, clear this iommu in iommu_bmp
3237 * update iommu count and coherency
3238 */
276dbf99
DW		 3239 if (iommu == device_to_iommu(info->segment, info->bus,
3240 info->devfn))
c7151a8d
WH		 3241 found = 1;
3242 }
3243
3244 if (found == 0) {
3245 unsigned long tmp_flags;
3246 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3247 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3248 domain->iommu_count--;
58c610bd 3249 domain_update_iommu_cap(domain);
c7151a8d
WH		 3250 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3251 }
3252
3253 spin_unlock_irqrestore(&device_domain_lock, flags);
3254}
3255
3256static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3257{
3258 struct device_domain_info *info;
3259 struct intel_iommu *iommu;
3260 unsigned long flags1, flags2;
3261
3262 spin_lock_irqsave(&device_domain_lock, flags1);
3263 while (!list_empty(&domain->devices)) {
3264 info = list_entry(domain->devices.next,
3265 struct device_domain_info, link);
3266 list_del(&info->link);
3267 list_del(&info->global);
3268 if (info->dev)
3269 info->dev->dev.archdata.iommu = NULL;
3270
3271 spin_unlock_irqrestore(&device_domain_lock, flags1);
3272
93a23a72 3273 iommu_disable_dev_iotlb(info);
276dbf99 3274 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3275 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3276 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3277
3278 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3279 * and capabilities
c7151a8d
WH		 3280 */
3281 spin_lock_irqsave(&domain->iommu_lock, flags2);
3282 if (test_and_clear_bit(iommu->seq_id,
3283 &domain->iommu_bmp)) {
3284 domain->iommu_count--;
58c610bd 3285 domain_update_iommu_cap(domain);
c7151a8d
WH		 3286 }
3287 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3288
3289 free_devinfo_mem(info);
3290 spin_lock_irqsave(&device_domain_lock, flags1);
3291 }
3292 spin_unlock_irqrestore(&device_domain_lock, flags1);
3293}
3294
5e98c4b1
WH		 3295/* domain id for virtual machine, it won't be set in context */
3296static unsigned long vm_domid;
3297
fe40f1e0
WH		 3298static int vm_domain_min_agaw(struct dmar_domain *domain)
3299{
3300 int i;
3301 int min_agaw = domain->agaw;
3302
3303 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3304 for (; i < g_num_of_iommus; ) {
3305 if (min_agaw > g_iommus[i]->agaw)
3306 min_agaw = g_iommus[i]->agaw;
3307
3308 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3309 }
3310
3311 return min_agaw;
3312}
3313
5e98c4b1
WH		 3314static struct dmar_domain *iommu_alloc_vm_domain(void)
3315{
3316 struct dmar_domain *domain;
3317
3318 domain = alloc_domain_mem();
3319 if (!domain)
3320 return NULL;
3321
3322 domain->id = vm_domid++;
3323 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3324 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3325
3326 return domain;
3327}
3328
2c2e2c38 3329static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3330{
3331 int adjust_width;
3332
3333 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 3334 spin_lock_init(&domain->iommu_lock);
3335
3336 domain_reserve_special_ranges(domain);
3337
3338 /* calculate AGAW */
3339 domain->gaw = guest_width;
3340 adjust_width = guestwidth_to_adjustwidth(guest_width);
3341 domain->agaw = width_to_agaw(adjust_width);
3342
3343 INIT_LIST_HEAD(&domain->devices);
3344
3345 domain->iommu_count = 0;
3346 domain->iommu_coherency = 0;
fe40f1e0 3347 domain->max_addr = 0;
5e98c4b1
WH		 3348
3349 /* always allocate the top pgd */
3350 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3351 if (!domain->pgd)
3352 return -ENOMEM;
3353 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3354 return 0;
3355}
3356
3357static void iommu_free_vm_domain(struct dmar_domain *domain)
3358{
3359 unsigned long flags;
3360 struct dmar_drhd_unit *drhd;
3361 struct intel_iommu *iommu;
3362 unsigned long i;
3363 unsigned long ndomains;
3364
3365 for_each_drhd_unit(drhd) {
3366 if (drhd->ignored)
3367 continue;
3368 iommu = drhd->iommu;
3369
3370 ndomains = cap_ndoms(iommu->cap);
3371 i = find_first_bit(iommu->domain_ids, ndomains);
3372 for (; i < ndomains; ) {
3373 if (iommu->domains[i] == domain) {
3374 spin_lock_irqsave(&iommu->lock, flags);
3375 clear_bit(i, iommu->domain_ids);
3376 iommu->domains[i] = NULL;
3377 spin_unlock_irqrestore(&iommu->lock, flags);
3378 break;
3379 }
3380 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3381 }
3382 }
3383}
3384
3385static void vm_domain_exit(struct dmar_domain *domain)
3386{
5e98c4b1
WH		 3387 /* Domain 0 is reserved, so dont process it */
3388 if (!domain)
3389 return;
3390
3391 vm_domain_remove_all_dev_info(domain);
3392 /* destroy iovas */
3393 put_iova_domain(&domain->iovad);
5e98c4b1
WH		 3394
3395 /* clear ptes */
595badf5 3396 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3397
3398 /* free page tables */
d794dc9b 3399 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3400
3401 iommu_free_vm_domain(domain);
3402 free_domain_mem(domain);
3403}
3404
5d450806 3405static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3406{
5d450806 3407 struct dmar_domain *dmar_domain;
38717946 3408
5d450806
JR		 3409 dmar_domain = iommu_alloc_vm_domain();
3410 if (!dmar_domain) {
38717946 3411 printk(KERN_ERR
5d450806
JR		 3412 "intel_iommu_domain_init: dmar_domain == NULL\n");
3413 return -ENOMEM;
38717946 3414 }
2c2e2c38 3415 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3416 printk(KERN_ERR
5d450806
JR		 3417 "intel_iommu_domain_init() failed\n");
3418 vm_domain_exit(dmar_domain);
3419 return -ENOMEM;
38717946 3420 }
5d450806 3421 domain->priv = dmar_domain;
faa3d6f5 3422
5d450806 3423 return 0;
38717946 3424}
38717946 3425
5d450806 3426static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3427{
5d450806
JR		 3428 struct dmar_domain *dmar_domain = domain->priv;
3429
3430 domain->priv = NULL;
3431 vm_domain_exit(dmar_domain);
38717946 3432}
38717946 3433
4c5478c9
JR		 3434static int intel_iommu_attach_device(struct iommu_domain *domain,
3435 struct device *dev)
38717946 3436{
4c5478c9
JR		 3437 struct dmar_domain *dmar_domain = domain->priv;
3438 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3439 struct intel_iommu *iommu;
3440 int addr_width;
3441 u64 end;
faa3d6f5
WH		 3442 int ret;
3443
3444 /* normally pdev is not mapped */
3445 if (unlikely(domain_context_mapped(pdev))) {
3446 struct dmar_domain *old_domain;
3447
3448 old_domain = find_domain(pdev);
3449 if (old_domain) {
2c2e2c38
FY		 3450 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3451 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3452 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 3453 else
3454 domain_remove_dev_info(old_domain);
3455 }
3456 }
3457
276dbf99
DW		 3458 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3459 pdev->devfn);
fe40f1e0
WH		 3460 if (!iommu)
3461 return -ENODEV;
3462
3463 /* check if this iommu agaw is sufficient for max mapped address */
3464 addr_width = agaw_to_width(iommu->agaw);
3465 end = DOMAIN_MAX_ADDR(addr_width);
3466 end = end & VTD_PAGE_MASK;
4c5478c9 3467 if (end < dmar_domain->max_addr) {
fe40f1e0
WH		 3468 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3469 "sufficient for the mapped address (%llx)\n",
4c5478c9 3470 __func__, iommu->agaw, dmar_domain->max_addr);
fe40f1e0
WH		 3471 return -EFAULT;
3472 }
3473
2c2e2c38 3474 ret = domain_add_dev_info(dmar_domain, pdev);
faa3d6f5
WH		 3475 if (ret)
3476 return ret;
3477
93a23a72 3478 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
faa3d6f5 3479 return ret;
38717946 3480}
38717946 3481
4c5478c9
JR		 3482static void intel_iommu_detach_device(struct iommu_domain *domain,
3483 struct device *dev)
38717946 3484{
4c5478c9
JR		 3485 struct dmar_domain *dmar_domain = domain->priv;
3486 struct pci_dev *pdev = to_pci_dev(dev);
3487
2c2e2c38 3488 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 3489}
c7151a8d 3490
dde57a21
JR		 3491static int intel_iommu_map_range(struct iommu_domain *domain,
3492 unsigned long iova, phys_addr_t hpa,
3493 size_t size, int iommu_prot)
faa3d6f5 3494{
dde57a21 3495 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0
WH		 3496 u64 max_addr;
3497 int addr_width;
dde57a21 3498 int prot = 0;
faa3d6f5 3499 int ret;
fe40f1e0 3500
dde57a21
JR		 3501 if (iommu_prot & IOMMU_READ)
3502 prot |= DMA_PTE_READ;
3503 if (iommu_prot & IOMMU_WRITE)
3504 prot |= DMA_PTE_WRITE;
9cf06697
SY		 3505 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3506 prot |= DMA_PTE_SNP;
dde57a21 3507
163cc52c 3508 max_addr = iova + size;
dde57a21 3509 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 3510 int min_agaw;
3511 u64 end;
3512
3513 /* check if minimum agaw is sufficient for mapped address */
dde57a21 3514 min_agaw = vm_domain_min_agaw(dmar_domain);
fe40f1e0
WH		 3515 addr_width = agaw_to_width(min_agaw);
3516 end = DOMAIN_MAX_ADDR(addr_width);
3517 end = end & VTD_PAGE_MASK;
3518 if (end < max_addr) {
3519 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3520 "sufficient for the mapped address (%llx)\n",
3521 __func__, min_agaw, max_addr);
3522 return -EFAULT;
3523 }
dde57a21 3524 dmar_domain->max_addr = max_addr;
fe40f1e0 3525 }
ad051221
DW		 3526 /* Round up size to next multiple of PAGE_SIZE, if it and
3527 the low bits of hpa would take us onto the next page */
88cb6a74 3528 size = aligned_nrpages(hpa, size);
ad051221
DW		 3529 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3530 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 3531 return ret;
38717946 3532}
38717946 3533
dde57a21
JR		 3534static void intel_iommu_unmap_range(struct iommu_domain *domain,
3535 unsigned long iova, size_t size)
38717946 3536{
dde57a21 3537 struct dmar_domain *dmar_domain = domain->priv;
faa3d6f5 3538
163cc52c
DW		 3539 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3540 (iova + size - 1) >> VTD_PAGE_SHIFT);
fe40f1e0 3541
163cc52c
DW		 3542 if (dmar_domain->max_addr == iova + size)
3543 dmar_domain->max_addr = iova;
38717946 3544}
38717946 3545
d14d6577
JR		 3546static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3547 unsigned long iova)
38717946 3548{
d14d6577 3549 struct dmar_domain *dmar_domain = domain->priv;
38717946 3550 struct dma_pte *pte;
faa3d6f5 3551 u64 phys = 0;
38717946 3552
b026fd28 3553 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
38717946 3554 if (pte)
faa3d6f5 3555 phys = dma_pte_addr(pte);
38717946 3556
faa3d6f5 3557 return phys;
38717946 3558}
a8bcbb0d 3559
dbb9fd86
SY		 3560static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3561 unsigned long cap)
3562{
3563 struct dmar_domain *dmar_domain = domain->priv;
3564
3565 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3566 return dmar_domain->iommu_snooping;
3567
3568 return 0;
3569}
3570
a8bcbb0d
JR		 3571static struct iommu_ops intel_iommu_ops = {
3572 .domain_init = intel_iommu_domain_init,
3573 .domain_destroy = intel_iommu_domain_destroy,
3574 .attach_dev = intel_iommu_attach_device,
3575 .detach_dev = intel_iommu_detach_device,
3576 .map = intel_iommu_map_range,
3577 .unmap = intel_iommu_unmap_range,
3578 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 3579 .domain_has_cap = intel_iommu_domain_has_cap,
a8bcbb0d 3580};
9af88143
DW		 3581
3582static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3583{
3584 /*
3585 * Mobile 4 Series Chipset neglects to set RWBF capability,
3586 * but needs it:
3587 */
3588 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3589 rwbf_quirk = 1;
3590}
3591
3592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
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