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intel-iommu: Clean up iommu_domain_identity_map()
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
5e0d2a6f 35#include <linux/timer.h>
38717946 36#include <linux/iova.h>
5d450806 37#include <linux/iommu.h>
38717946 38#include <linux/intel-iommu.h>
f59c7b69 39#include <linux/sysdev.h>
ba395927 40#include <asm/cacheflush.h>
46a7fa27 41#include <asm/iommu.h>
ba395927
KA		 42#include "pci.h"
43
5b6985ce
FY		 44#define ROOT_SIZE VTD_PAGE_SIZE
45#define CONTEXT_SIZE VTD_PAGE_SIZE
46
ba395927
KA		 47#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50#define IOAPIC_RANGE_START (0xfee00000)
51#define IOAPIC_RANGE_END (0xfeefffff)
52#define IOVA_START_ADDR (0x1000)
53
54#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
4ed0d3e6
FY		 56#define MAX_AGAW_WIDTH 64
57
ba395927 58#define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
595badf5 59#define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
ba395927 60
f27be03b 61#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 62#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 63#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 64
fd18de50 65
dd4e8319
DW		 66/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67 are never going to work. */
68static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
69{
70 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
71}
72
73static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
74{
75 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
76}
77static inline unsigned long page_to_dma_pfn(struct page *pg)
78{
79 return mm_to_dma_pfn(page_to_pfn(pg));
80}
81static inline unsigned long virt_to_dma_pfn(void *p)
82{
83 return page_to_dma_pfn(virt_to_page(p));
84}
85
d9630fe9
WH		 86/* global iommu list, set NULL for ignored DMAR units */
87static struct intel_iommu **g_iommus;
88
9af88143
DW		 89static int rwbf_quirk;
90
46b08e1a
MM		 91/*
92 * 0: Present
93 * 1-11: Reserved
94 * 12-63: Context Ptr (12 - (haw-1))
95 * 64-127: Reserved
96 */
97struct root_entry {
98 u64 val;
99 u64 rsvd1;
100};
101#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102static inline bool root_present(struct root_entry *root)
103{
104 return (root->val & 1);
105}
106static inline void set_root_present(struct root_entry *root)
107{
108 root->val |= 1;
109}
110static inline void set_root_value(struct root_entry *root, unsigned long value)
111{
112 root->val |= value & VTD_PAGE_MASK;
113}
114
115static inline struct context_entry *
116get_context_addr_from_root(struct root_entry *root)
117{
118 return (struct context_entry *)
119 (root_present(root)?phys_to_virt(
120 root->val & VTD_PAGE_MASK) :
121 NULL);
122}
123
7a8fc25e
MM		 124/*
125 * low 64 bits:
126 * 0: present
127 * 1: fault processing disable
128 * 2-3: translation type
129 * 12-63: address space root
130 * high 64 bits:
131 * 0-2: address width
132 * 3-6: aval
133 * 8-23: domain id
134 */
135struct context_entry {
136 u64 lo;
137 u64 hi;
138};
c07e7d21
MM		 139
140static inline bool context_present(struct context_entry *context)
141{
142 return (context->lo & 1);
143}
144static inline void context_set_present(struct context_entry *context)
145{
146 context->lo |= 1;
147}
148
149static inline void context_set_fault_enable(struct context_entry *context)
150{
151 context->lo &= (((u64)-1) << 2) | 1;
152}
153
c07e7d21
MM		 154static inline void context_set_translation_type(struct context_entry *context,
155 unsigned long value)
156{
157 context->lo &= (((u64)-1) << 4) | 3;
158 context->lo |= (value & 3) << 2;
159}
160
161static inline void context_set_address_root(struct context_entry *context,
162 unsigned long value)
163{
164 context->lo |= value & VTD_PAGE_MASK;
165}
166
167static inline void context_set_address_width(struct context_entry *context,
168 unsigned long value)
169{
170 context->hi |= value & 7;
171}
172
173static inline void context_set_domain_id(struct context_entry *context,
174 unsigned long value)
175{
176 context->hi |= (value & ((1 << 16) - 1)) << 8;
177}
178
179static inline void context_clear_entry(struct context_entry *context)
180{
181 context->lo = 0;
182 context->hi = 0;
183}
7a8fc25e 184
622ba12a
MM		 185/*
186 * 0: readable
187 * 1: writable
188 * 2-6: reserved
189 * 7: super page
9cf06697
SY		 190 * 8-10: available
191 * 11: snoop behavior
622ba12a
MM		 192 * 12-63: Host physcial address
193 */
194struct dma_pte {
195 u64 val;
196};
622ba12a 197
19c239ce
MM		 198static inline void dma_clear_pte(struct dma_pte *pte)
199{
200 pte->val = 0;
201}
202
203static inline void dma_set_pte_readable(struct dma_pte *pte)
204{
205 pte->val |= DMA_PTE_READ;
206}
207
208static inline void dma_set_pte_writable(struct dma_pte *pte)
209{
210 pte->val |= DMA_PTE_WRITE;
211}
212
9cf06697
SY		 213static inline void dma_set_pte_snp(struct dma_pte *pte)
214{
215 pte->val |= DMA_PTE_SNP;
216}
217
19c239ce
MM		 218static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
219{
220 pte->val = (pte->val & ~3) | (prot & 3);
221}
222
223static inline u64 dma_pte_addr(struct dma_pte *pte)
224{
225 return (pte->val & VTD_PAGE_MASK);
226}
227
dd4e8319 228static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
19c239ce 229{
dd4e8319 230 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
19c239ce
MM		 231}
232
233static inline bool dma_pte_present(struct dma_pte *pte)
234{
235 return (pte->val & 3) != 0;
236}
622ba12a 237
2c2e2c38
FY		 238/*
239 * This domain is a statically identity mapping domain.
240 * 1. This domain creats a static 1:1 mapping to all usable memory.
241 * 2. It maps to each iommu if successful.
242 * 3. Each iommu mapps to this domain if successful.
243 */
244struct dmar_domain *si_domain;
245
3b5410e7 246/* devices under the same p2p bridge are owned in one domain */
cdc7b837 247#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 248
1ce28feb
WH		 249/* domain represents a virtual machine, more than one devices
250 * across iommus may be owned in one domain, e.g. kvm guest.
251 */
252#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
253
2c2e2c38
FY		 254/* si_domain contains mulitple devices */
255#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
256
99126f7c
MM		 257struct dmar_domain {
258 int id; /* domain id */
8c11e798 259 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
99126f7c
MM		 260
261 struct list_head devices; /* all devices' list */
262 struct iova_domain iovad; /* iova's that belong to this domain */
263
264 struct dma_pte *pgd; /* virtual address */
265 spinlock_t mapping_lock; /* page table lock */
266 int gaw; /* max guest address width */
267
268 /* adjusted guest address width, 0 is level 2 30-bit */
269 int agaw;
270
3b5410e7 271 int flags; /* flags to find out type of domain */
8e604097
WH		 272
273 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 274 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d
WH		 275 int iommu_count; /* reference count of iommu */
276 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 277 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 278};
279
a647dacb
MM		 280/* PCI domain-device relationship */
281struct device_domain_info {
282 struct list_head link; /* link to domain siblings */
283 struct list_head global; /* link to global list */
276dbf99
DW		 284 int segment; /* PCI domain */
285 u8 bus; /* PCI bus number */
a647dacb
MM		 286 u8 devfn; /* PCI devfn number */
287 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
93a23a72 288 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 289 struct dmar_domain *domain; /* pointer to domain */
290};
291
5e0d2a6f 292static void flush_unmaps_timeout(unsigned long data);
293
294DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
295
80b20dd8 296#define HIGH_WATER_MARK 250
297struct deferred_flush_tables {
298 int next;
299 struct iova *iova[HIGH_WATER_MARK];
300 struct dmar_domain *domain[HIGH_WATER_MARK];
301};
302
303static struct deferred_flush_tables *deferred_flush;
304
5e0d2a6f 305/* bitmap for indexing intel_iommus */
5e0d2a6f 306static int g_num_of_iommus;
307
308static DEFINE_SPINLOCK(async_umap_flush_lock);
309static LIST_HEAD(unmaps_to_do);
310
311static int timer_on;
312static long list_size;
5e0d2a6f 313
ba395927
KA		 314static void domain_remove_dev_info(struct dmar_domain *domain);
315
0cd5c3c8
KM		 316#ifdef CONFIG_DMAR_DEFAULT_ON
317int dmar_disabled = 0;
318#else
319int dmar_disabled = 1;
320#endif /*CONFIG_DMAR_DEFAULT_ON*/
321
ba395927 322static int __initdata dmar_map_gfx = 1;
7d3b03ce 323static int dmar_forcedac;
5e0d2a6f 324static int intel_iommu_strict;
ba395927
KA		 325
326#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
327static DEFINE_SPINLOCK(device_domain_lock);
328static LIST_HEAD(device_domain_list);
329
a8bcbb0d
JR		 330static struct iommu_ops intel_iommu_ops;
331
ba395927
KA		 332static int __init intel_iommu_setup(char *str)
333{
334 if (!str)
335 return -EINVAL;
336 while (*str) {
0cd5c3c8
KM		 337 if (!strncmp(str, "on", 2)) {
338 dmar_disabled = 0;
339 printk(KERN_INFO "Intel-IOMMU: enabled\n");
340 } else if (!strncmp(str, "off", 3)) {
ba395927 341 dmar_disabled = 1;
0cd5c3c8 342 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 343 } else if (!strncmp(str, "igfx_off", 8)) {
344 dmar_map_gfx = 0;
345 printk(KERN_INFO
346 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 347 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 348 printk(KERN_INFO
7d3b03ce
KA		 349 "Intel-IOMMU: Forcing DAC for PCI devices\n");
350 dmar_forcedac = 1;
5e0d2a6f 351 } else if (!strncmp(str, "strict", 6)) {
352 printk(KERN_INFO
353 "Intel-IOMMU: disable batched IOTLB flush\n");
354 intel_iommu_strict = 1;
ba395927
KA		 355 }
356
357 str += strcspn(str, ",");
358 while (*str == ',')
359 str++;
360 }
361 return 0;
362}
363__setup("intel_iommu=", intel_iommu_setup);
364
365static struct kmem_cache *iommu_domain_cache;
366static struct kmem_cache *iommu_devinfo_cache;
367static struct kmem_cache *iommu_iova_cache;
368
eb3fa7cb
KA		 369static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
370{
371 unsigned int flags;
372 void *vaddr;
373
374 /* trying to avoid low memory issues */
375 flags = current->flags & PF_MEMALLOC;
376 current->flags |= PF_MEMALLOC;
377 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
378 current->flags &= (~PF_MEMALLOC | flags);
379 return vaddr;
380}
381
382
ba395927
KA		 383static inline void *alloc_pgtable_page(void)
384{
eb3fa7cb
KA		 385 unsigned int flags;
386 void *vaddr;
387
388 /* trying to avoid low memory issues */
389 flags = current->flags & PF_MEMALLOC;
390 current->flags |= PF_MEMALLOC;
391 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
392 current->flags &= (~PF_MEMALLOC | flags);
393 return vaddr;
ba395927
KA		 394}
395
396static inline void free_pgtable_page(void *vaddr)
397{
398 free_page((unsigned long)vaddr);
399}
400
401static inline void *alloc_domain_mem(void)
402{
eb3fa7cb 403 return iommu_kmem_cache_alloc(iommu_domain_cache);
ba395927
KA		 404}
405
38717946 406static void free_domain_mem(void *vaddr)
ba395927
KA		 407{
408 kmem_cache_free(iommu_domain_cache, vaddr);
409}
410
411static inline void * alloc_devinfo_mem(void)
412{
eb3fa7cb 413 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
ba395927
KA		 414}
415
416static inline void free_devinfo_mem(void *vaddr)
417{
418 kmem_cache_free(iommu_devinfo_cache, vaddr);
419}
420
421struct iova *alloc_iova_mem(void)
422{
eb3fa7cb 423 return iommu_kmem_cache_alloc(iommu_iova_cache);
ba395927
KA		 424}
425
426void free_iova_mem(struct iova *iova)
427{
428 kmem_cache_free(iommu_iova_cache, iova);
429}
430
1b573683
WH		 431
432static inline int width_to_agaw(int width);
433
4ed0d3e6 434static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 435{
436 unsigned long sagaw;
437 int agaw = -1;
438
439 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 440 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 441 agaw >= 0; agaw--) {
442 if (test_bit(agaw, &sagaw))
443 break;
444 }
445
446 return agaw;
447}
448
4ed0d3e6
FY		 449/*
450 * Calculate max SAGAW for each iommu.
451 */
452int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
453{
454 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
455}
456
457/*
458 * calculate agaw for each iommu.
459 * "SAGAW" may be different across iommus, use a default agaw, and
460 * get a supported less agaw for iommus that don't support the default agaw.
461 */
462int iommu_calculate_agaw(struct intel_iommu *iommu)
463{
464 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
465}
466
2c2e2c38 467/* This functionin only returns single iommu in a domain */
8c11e798
WH		 468static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
469{
470 int iommu_id;
471
2c2e2c38 472 /* si_domain and vm domain should not get here. */
1ce28feb 473 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 474 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 475
8c11e798
WH		 476 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
477 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
478 return NULL;
479
480 return g_iommus[iommu_id];
481}
482
8e604097
WH		 483static void domain_update_iommu_coherency(struct dmar_domain *domain)
484{
485 int i;
486
487 domain->iommu_coherency = 1;
488
489 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
490 for (; i < g_num_of_iommus; ) {
491 if (!ecap_coherent(g_iommus[i]->ecap)) {
492 domain->iommu_coherency = 0;
493 break;
494 }
495 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
496 }
497}
498
58c610bd
SY		 499static void domain_update_iommu_snooping(struct dmar_domain *domain)
500{
501 int i;
502
503 domain->iommu_snooping = 1;
504
505 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
506 for (; i < g_num_of_iommus; ) {
507 if (!ecap_sc_support(g_iommus[i]->ecap)) {
508 domain->iommu_snooping = 0;
509 break;
510 }
511 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
512 }
513}
514
515/* Some capabilities may be different across iommus */
516static void domain_update_iommu_cap(struct dmar_domain *domain)
517{
518 domain_update_iommu_coherency(domain);
519 domain_update_iommu_snooping(domain);
520}
521
276dbf99 522static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 523{
524 struct dmar_drhd_unit *drhd = NULL;
525 int i;
526
527 for_each_drhd_unit(drhd) {
528 if (drhd->ignored)
529 continue;
276dbf99
DW		 530 if (segment != drhd->segment)
531 continue;
c7151a8d 532
924b6231 533 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 534 if (drhd->devices[i] &&
535 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 536 drhd->devices[i]->devfn == devfn)
537 return drhd->iommu;
4958c5dc
DW		 538 if (drhd->devices[i] &&
539 drhd->devices[i]->subordinate &&
924b6231
DW		 540 drhd->devices[i]->subordinate->number <= bus &&
541 drhd->devices[i]->subordinate->subordinate >= bus)
542 return drhd->iommu;
543 }
c7151a8d
WH		 544
545 if (drhd->include_all)
546 return drhd->iommu;
547 }
548
549 return NULL;
550}
551
5331fe6f
WH		 552static void domain_flush_cache(struct dmar_domain *domain,
553 void *addr, int size)
554{
555 if (!domain->iommu_coherency)
556 clflush_cache_range(addr, size);
557}
558
ba395927
KA		 559/* Gets context entry for a given bus and devfn */
560static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
561 u8 bus, u8 devfn)
562{
563 struct root_entry *root;
564 struct context_entry *context;
565 unsigned long phy_addr;
566 unsigned long flags;
567
568 spin_lock_irqsave(&iommu->lock, flags);
569 root = &iommu->root_entry[bus];
570 context = get_context_addr_from_root(root);
571 if (!context) {
572 context = (struct context_entry *)alloc_pgtable_page();
573 if (!context) {
574 spin_unlock_irqrestore(&iommu->lock, flags);
575 return NULL;
576 }
5b6985ce 577 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 578 phy_addr = virt_to_phys((void *)context);
579 set_root_value(root, phy_addr);
580 set_root_present(root);
581 __iommu_flush_cache(iommu, root, sizeof(*root));
582 }
583 spin_unlock_irqrestore(&iommu->lock, flags);
584 return &context[devfn];
585}
586
587static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
588{
589 struct root_entry *root;
590 struct context_entry *context;
591 int ret;
592 unsigned long flags;
593
594 spin_lock_irqsave(&iommu->lock, flags);
595 root = &iommu->root_entry[bus];
596 context = get_context_addr_from_root(root);
597 if (!context) {
598 ret = 0;
599 goto out;
600 }
c07e7d21 601 ret = context_present(&context[devfn]);
ba395927
KA		 602out:
603 spin_unlock_irqrestore(&iommu->lock, flags);
604 return ret;
605}
606
607static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
608{
609 struct root_entry *root;
610 struct context_entry *context;
611 unsigned long flags;
612
613 spin_lock_irqsave(&iommu->lock, flags);
614 root = &iommu->root_entry[bus];
615 context = get_context_addr_from_root(root);
616 if (context) {
c07e7d21 617 context_clear_entry(&context[devfn]);
ba395927
KA		 618 __iommu_flush_cache(iommu, &context[devfn], \
619 sizeof(*context));
620 }
621 spin_unlock_irqrestore(&iommu->lock, flags);
622}
623
624static void free_context_table(struct intel_iommu *iommu)
625{
626 struct root_entry *root;
627 int i;
628 unsigned long flags;
629 struct context_entry *context;
630
631 spin_lock_irqsave(&iommu->lock, flags);
632 if (!iommu->root_entry) {
633 goto out;
634 }
635 for (i = 0; i < ROOT_ENTRY_NR; i++) {
636 root = &iommu->root_entry[i];
637 context = get_context_addr_from_root(root);
638 if (context)
639 free_pgtable_page(context);
640 }
641 free_pgtable_page(iommu->root_entry);
642 iommu->root_entry = NULL;
643out:
644 spin_unlock_irqrestore(&iommu->lock, flags);
645}
646
647/* page table handling */
648#define LEVEL_STRIDE (9)
649#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
650
651static inline int agaw_to_level(int agaw)
652{
653 return agaw + 2;
654}
655
656static inline int agaw_to_width(int agaw)
657{
658 return 30 + agaw * LEVEL_STRIDE;
659
660}
661
662static inline int width_to_agaw(int width)
663{
664 return (width - 30) / LEVEL_STRIDE;
665}
666
667static inline unsigned int level_to_offset_bits(int level)
668{
6660c63a 669 return (level - 1) * LEVEL_STRIDE;
ba395927
KA		 670}
671
77dfa56c 672static inline int pfn_level_offset(unsigned long pfn, int level)
ba395927 673{
6660c63a 674 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
ba395927
KA		 675}
676
6660c63a 677static inline unsigned long level_mask(int level)
ba395927 678{
6660c63a 679 return -1UL << level_to_offset_bits(level);
ba395927
KA		 680}
681
6660c63a 682static inline unsigned long level_size(int level)
ba395927 683{
6660c63a 684 return 1UL << level_to_offset_bits(level);
ba395927
KA		 685}
686
6660c63a 687static inline unsigned long align_to_level(unsigned long pfn, int level)
ba395927 688{
6660c63a 689 return (pfn + level_size(level) - 1) & level_mask(level);
ba395927
KA		 690}
691
b026fd28
DW		 692static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
693 unsigned long pfn)
ba395927 694{
b026fd28 695 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 696 struct dma_pte *parent, *pte = NULL;
697 int level = agaw_to_level(domain->agaw);
698 int offset;
699 unsigned long flags;
700
701 BUG_ON(!domain->pgd);
b026fd28 702 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
ba395927
KA		 703 parent = domain->pgd;
704
705 spin_lock_irqsave(&domain->mapping_lock, flags);
706 while (level > 0) {
707 void *tmp_page;
708
b026fd28 709 offset = pfn_level_offset(pfn, level);
ba395927
KA		 710 pte = &parent[offset];
711 if (level == 1)
712 break;
713
19c239ce 714 if (!dma_pte_present(pte)) {
ba395927
KA		 715 tmp_page = alloc_pgtable_page();
716
717 if (!tmp_page) {
718 spin_unlock_irqrestore(&domain->mapping_lock,
719 flags);
720 return NULL;
721 }
5331fe6f 722 domain_flush_cache(domain, tmp_page, PAGE_SIZE);
dd4e8319 723 dma_set_pte_pfn(pte, virt_to_dma_pfn(tmp_page));
ba395927
KA		 724 /*
725 * high level table always sets r/w, last level page
726 * table control read/write
727 */
19c239ce
MM		 728 dma_set_pte_readable(pte);
729 dma_set_pte_writable(pte);
5331fe6f 730 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927 731 }
19c239ce 732 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 733 level--;
734 }
735
736 spin_unlock_irqrestore(&domain->mapping_lock, flags);
737 return pte;
738}
739
740/* return address's pte at specific level */
90dcfb5e
DW		 741static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
742 unsigned long pfn,
743 int level)
ba395927
KA		 744{
745 struct dma_pte *parent, *pte = NULL;
746 int total = agaw_to_level(domain->agaw);
747 int offset;
748
749 parent = domain->pgd;
750 while (level <= total) {
90dcfb5e 751 offset = pfn_level_offset(pfn, total);
ba395927
KA		 752 pte = &parent[offset];
753 if (level == total)
754 return pte;
755
19c239ce 756 if (!dma_pte_present(pte))
ba395927 757 break;
19c239ce 758 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 759 total--;
760 }
761 return NULL;
762}
763
764/* clear one page's page table */
a75f7cf9 765static void dma_pte_clear_one(struct dmar_domain *domain, unsigned long pfn)
ba395927
KA		 766{
767 struct dma_pte *pte = NULL;
768
769 /* get last level pte */
a75f7cf9 770 pte = dma_pfn_level_pte(domain, pfn, 1);
ba395927
KA		 771
772 if (pte) {
19c239ce 773 dma_clear_pte(pte);
5331fe6f 774 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927
KA		 775 }
776}
777
778/* clear last level pte, a tlb flush should be followed */
595badf5
DW		 779static void dma_pte_clear_range(struct dmar_domain *domain,
780 unsigned long start_pfn,
781 unsigned long last_pfn)
ba395927 782{
04b18e65 783 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
66eae846 784
04b18e65 785 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 786 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
ba395927 787
04b18e65 788 /* we don't need lock here; nobody else touches the iova range */
595badf5 789 while (start_pfn <= last_pfn) {
04b18e65
DW		 790 dma_pte_clear_one(domain, start_pfn);
791 start_pfn++;
ba395927
KA		 792 }
793}
794
795/* free page table pages. last level pte should already be cleared */
796static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 797 unsigned long start_pfn,
798 unsigned long last_pfn)
ba395927 799{
6660c63a 800 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 801 struct dma_pte *pte;
802 int total = agaw_to_level(domain->agaw);
803 int level;
6660c63a 804 unsigned long tmp;
ba395927 805
6660c63a
DW		 806 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
807 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
ba395927
KA		 808
809 /* we don't need lock here, nobody else touches the iova range */
810 level = 2;
811 while (level <= total) {
6660c63a
DW		 812 tmp = align_to_level(start_pfn, level);
813
814 /* Only clear this pte/pmd if we're asked to clear its
815 _whole_ range */
816 if (tmp + level_size(level) - 1 > last_pfn)
ba395927
KA		 817 return;
818
6660c63a
DW		 819 while (tmp <= last_pfn) {
820 pte = dma_pfn_level_pte(domain, tmp, level);
ba395927
KA		 821 if (pte) {
822 free_pgtable_page(
19c239ce
MM		 823 phys_to_virt(dma_pte_addr(pte)));
824 dma_clear_pte(pte);
5331fe6f 825 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927
KA		 826 }
827 tmp += level_size(level);
828 }
829 level++;
830 }
831 /* free pgd */
d794dc9b 832 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 833 free_pgtable_page(domain->pgd);
834 domain->pgd = NULL;
835 }
836}
837
838/* iommu handling */
839static int iommu_alloc_root_entry(struct intel_iommu *iommu)
840{
841 struct root_entry *root;
842 unsigned long flags;
843
844 root = (struct root_entry *)alloc_pgtable_page();
845 if (!root)
846 return -ENOMEM;
847
5b6985ce 848 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 849
850 spin_lock_irqsave(&iommu->lock, flags);
851 iommu->root_entry = root;
852 spin_unlock_irqrestore(&iommu->lock, flags);
853
854 return 0;
855}
856
ba395927
KA		 857static void iommu_set_root_entry(struct intel_iommu *iommu)
858{
859 void *addr;
c416daa9 860 u32 sts;
ba395927
KA		 861 unsigned long flag;
862
863 addr = iommu->root_entry;
864
865 spin_lock_irqsave(&iommu->register_lock, flag);
866 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
867
c416daa9 868 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 869
870 /* Make sure hardware complete it */
871 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 872 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927
KA		 873
874 spin_unlock_irqrestore(&iommu->register_lock, flag);
875}
876
877static void iommu_flush_write_buffer(struct intel_iommu *iommu)
878{
879 u32 val;
880 unsigned long flag;
881
9af88143 882 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 883 return;
ba395927
KA		 884
885 spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 886 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 887
888 /* Make sure hardware complete it */
889 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 890 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927
KA		 891
892 spin_unlock_irqrestore(&iommu->register_lock, flag);
893}
894
895/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 896static void __iommu_flush_context(struct intel_iommu *iommu,
897 u16 did, u16 source_id, u8 function_mask,
898 u64 type)
ba395927
KA		 899{
900 u64 val = 0;
901 unsigned long flag;
902
ba395927
KA		 903 switch (type) {
904 case DMA_CCMD_GLOBAL_INVL:
905 val = DMA_CCMD_GLOBAL_INVL;
906 break;
907 case DMA_CCMD_DOMAIN_INVL:
908 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
909 break;
910 case DMA_CCMD_DEVICE_INVL:
911 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
912 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
913 break;
914 default:
915 BUG();
916 }
917 val |= DMA_CCMD_ICC;
918
919 spin_lock_irqsave(&iommu->register_lock, flag);
920 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
921
922 /* Make sure hardware complete it */
923 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
924 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
925
926 spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 927}
928
ba395927 929/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 930static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
931 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 932{
933 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
934 u64 val = 0, val_iva = 0;
935 unsigned long flag;
936
ba395927
KA		 937 switch (type) {
938 case DMA_TLB_GLOBAL_FLUSH:
939 /* global flush doesn't need set IVA_REG */
940 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
941 break;
942 case DMA_TLB_DSI_FLUSH:
943 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
944 break;
945 case DMA_TLB_PSI_FLUSH:
946 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
947 /* Note: always flush non-leaf currently */
948 val_iva = size_order | addr;
949 break;
950 default:
951 BUG();
952 }
953 /* Note: set drain read/write */
954#if 0
955 /*
956 * This is probably to be super secure.. Looks like we can
957 * ignore it without any impact.
958 */
959 if (cap_read_drain(iommu->cap))
960 val |= DMA_TLB_READ_DRAIN;
961#endif
962 if (cap_write_drain(iommu->cap))
963 val |= DMA_TLB_WRITE_DRAIN;
964
965 spin_lock_irqsave(&iommu->register_lock, flag);
966 /* Note: Only uses first TLB reg currently */
967 if (val_iva)
968 dmar_writeq(iommu->reg + tlb_offset, val_iva);
969 dmar_writeq(iommu->reg + tlb_offset + 8, val);
970
971 /* Make sure hardware complete it */
972 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
973 dmar_readq, (!(val & DMA_TLB_IVT)), val);
974
975 spin_unlock_irqrestore(&iommu->register_lock, flag);
976
977 /* check IOTLB invalidation granularity */
978 if (DMA_TLB_IAIG(val) == 0)
979 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
980 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
981 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 982 (unsigned long long)DMA_TLB_IIRG(type),
983 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 984}
985
93a23a72
YZ		 986static struct device_domain_info *iommu_support_dev_iotlb(
987 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
988{
989 int found = 0;
990 unsigned long flags;
991 struct device_domain_info *info;
992 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
993
994 if (!ecap_dev_iotlb_support(iommu->ecap))
995 return NULL;
996
997 if (!iommu->qi)
998 return NULL;
999
1000 spin_lock_irqsave(&device_domain_lock, flags);
1001 list_for_each_entry(info, &domain->devices, link)
1002 if (info->bus == bus && info->devfn == devfn) {
1003 found = 1;
1004 break;
1005 }
1006 spin_unlock_irqrestore(&device_domain_lock, flags);
1007
1008 if (!found || !info->dev)
1009 return NULL;
1010
1011 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1012 return NULL;
1013
1014 if (!dmar_find_matched_atsr_unit(info->dev))
1015 return NULL;
1016
1017 info->iommu = iommu;
1018
1019 return info;
1020}
1021
1022static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1023{
93a23a72
YZ		 1024 if (!info)
1025 return;
1026
1027 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1028}
1029
1030static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1031{
1032 if (!info->dev || !pci_ats_enabled(info->dev))
1033 return;
1034
1035 pci_disable_ats(info->dev);
1036}
1037
1038static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1039 u64 addr, unsigned mask)
1040{
1041 u16 sid, qdep;
1042 unsigned long flags;
1043 struct device_domain_info *info;
1044
1045 spin_lock_irqsave(&device_domain_lock, flags);
1046 list_for_each_entry(info, &domain->devices, link) {
1047 if (!info->dev || !pci_ats_enabled(info->dev))
1048 continue;
1049
1050 sid = info->bus << 8 | info->devfn;
1051 qdep = pci_ats_queue_depth(info->dev);
1052 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1053 }
1054 spin_unlock_irqrestore(&device_domain_lock, flags);
1055}
1056
1f0ef2aa 1057static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
03d6a246 1058 unsigned long pfn, unsigned int pages)
ba395927 1059{
9dd2fe89 1060 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1061 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1062
ba395927
KA		 1063 BUG_ON(pages == 0);
1064
ba395927 1065 /*
9dd2fe89
YZ		 1066 * Fallback to domain selective flush if no PSI support or the size is
1067 * too big.
ba395927
KA		 1068 * PSI requires page size to be 2 ^ x, and the base address is naturally
1069 * aligned to the size
1070 */
9dd2fe89
YZ		 1071 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1072 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1073 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1074 else
1075 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1076 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1077
1078 /*
1079 * In caching mode, domain ID 0 is reserved for non-present to present
1080 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1081 */
1082 if (!cap_caching_mode(iommu->cap) || did)
93a23a72 1083 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1084}
1085
f8bab735 1086static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1087{
1088 u32 pmen;
1089 unsigned long flags;
1090
1091 spin_lock_irqsave(&iommu->register_lock, flags);
1092 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1093 pmen &= ~DMA_PMEN_EPM;
1094 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1095
1096 /* wait for the protected region status bit to clear */
1097 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1098 readl, !(pmen & DMA_PMEN_PRS), pmen);
1099
1100 spin_unlock_irqrestore(&iommu->register_lock, flags);
1101}
1102
ba395927
KA		 1103static int iommu_enable_translation(struct intel_iommu *iommu)
1104{
1105 u32 sts;
1106 unsigned long flags;
1107
1108 spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1109 iommu->gcmd |= DMA_GCMD_TE;
1110 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1111
1112 /* Make sure hardware complete it */
1113 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1114 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1115
ba395927
KA		 1116 spin_unlock_irqrestore(&iommu->register_lock, flags);
1117 return 0;
1118}
1119
1120static int iommu_disable_translation(struct intel_iommu *iommu)
1121{
1122 u32 sts;
1123 unsigned long flag;
1124
1125 spin_lock_irqsave(&iommu->register_lock, flag);
1126 iommu->gcmd &= ~DMA_GCMD_TE;
1127 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1128
1129 /* Make sure hardware complete it */
1130 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1131 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927
KA		 1132
1133 spin_unlock_irqrestore(&iommu->register_lock, flag);
1134 return 0;
1135}
1136
3460a6d9 1137
ba395927
KA		 1138static int iommu_init_domains(struct intel_iommu *iommu)
1139{
1140 unsigned long ndomains;
1141 unsigned long nlongs;
1142
1143 ndomains = cap_ndoms(iommu->cap);
1144 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1145 nlongs = BITS_TO_LONGS(ndomains);
1146
1147 /* TBD: there might be 64K domains,
1148 * consider other allocation for future chip
1149 */
1150 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1151 if (!iommu->domain_ids) {
1152 printk(KERN_ERR "Allocating domain id array failed\n");
1153 return -ENOMEM;
1154 }
1155 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1156 GFP_KERNEL);
1157 if (!iommu->domains) {
1158 printk(KERN_ERR "Allocating domain array failed\n");
1159 kfree(iommu->domain_ids);
1160 return -ENOMEM;
1161 }
1162
e61d98d8
SS		 1163 spin_lock_init(&iommu->lock);
1164
ba395927
KA		 1165 /*
1166 * if Caching mode is set, then invalid translations are tagged
1167 * with domainid 0. Hence we need to pre-allocate it.
1168 */
1169 if (cap_caching_mode(iommu->cap))
1170 set_bit(0, iommu->domain_ids);
1171 return 0;
1172}
ba395927 1173
ba395927
KA		 1174
1175static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1176static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8
SS		 1177
1178void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1179{
1180 struct dmar_domain *domain;
1181 int i;
c7151a8d 1182 unsigned long flags;
ba395927 1183
ba395927
KA		 1184 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1185 for (; i < cap_ndoms(iommu->cap); ) {
1186 domain = iommu->domains[i];
1187 clear_bit(i, iommu->domain_ids);
c7151a8d
WH		 1188
1189 spin_lock_irqsave(&domain->iommu_lock, flags);
5e98c4b1
WH		 1190 if (--domain->iommu_count == 0) {
1191 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1192 vm_domain_exit(domain);
1193 else
1194 domain_exit(domain);
1195 }
c7151a8d
WH		 1196 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1197
ba395927
KA		 1198 i = find_next_bit(iommu->domain_ids,
1199 cap_ndoms(iommu->cap), i+1);
1200 }
1201
1202 if (iommu->gcmd & DMA_GCMD_TE)
1203 iommu_disable_translation(iommu);
1204
1205 if (iommu->irq) {
1206 set_irq_data(iommu->irq, NULL);
1207 /* This will mask the irq */
1208 free_irq(iommu->irq, iommu);
1209 destroy_irq(iommu->irq);
1210 }
1211
1212 kfree(iommu->domains);
1213 kfree(iommu->domain_ids);
1214
d9630fe9
WH		 1215 g_iommus[iommu->seq_id] = NULL;
1216
1217 /* if all iommus are freed, free g_iommus */
1218 for (i = 0; i < g_num_of_iommus; i++) {
1219 if (g_iommus[i])
1220 break;
1221 }
1222
1223 if (i == g_num_of_iommus)
1224 kfree(g_iommus);
1225
ba395927
KA		 1226 /* free context mapping */
1227 free_context_table(iommu);
ba395927
KA		 1228}
1229
2c2e2c38 1230static struct dmar_domain *alloc_domain(void)
ba395927 1231{
ba395927 1232 struct dmar_domain *domain;
ba395927
KA		 1233
1234 domain = alloc_domain_mem();
1235 if (!domain)
1236 return NULL;
1237
2c2e2c38
FY		 1238 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1239 domain->flags = 0;
1240
1241 return domain;
1242}
1243
1244static int iommu_attach_domain(struct dmar_domain *domain,
1245 struct intel_iommu *iommu)
1246{
1247 int num;
1248 unsigned long ndomains;
1249 unsigned long flags;
1250
ba395927
KA		 1251 ndomains = cap_ndoms(iommu->cap);
1252
1253 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1254
ba395927
KA		 1255 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1256 if (num >= ndomains) {
1257 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1258 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1259 return -ENOMEM;
ba395927
KA		 1260 }
1261
ba395927 1262 domain->id = num;
2c2e2c38 1263 set_bit(num, iommu->domain_ids);
8c11e798 1264 set_bit(iommu->seq_id, &domain->iommu_bmp);
ba395927
KA		 1265 iommu->domains[num] = domain;
1266 spin_unlock_irqrestore(&iommu->lock, flags);
1267
2c2e2c38 1268 return 0;
ba395927
KA		 1269}
1270
2c2e2c38
FY		 1271static void iommu_detach_domain(struct dmar_domain *domain,
1272 struct intel_iommu *iommu)
ba395927
KA		 1273{
1274 unsigned long flags;
2c2e2c38
FY		 1275 int num, ndomains;
1276 int found = 0;
ba395927 1277
8c11e798 1278 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38
FY		 1279 ndomains = cap_ndoms(iommu->cap);
1280 num = find_first_bit(iommu->domain_ids, ndomains);
1281 for (; num < ndomains; ) {
1282 if (iommu->domains[num] == domain) {
1283 found = 1;
1284 break;
1285 }
1286 num = find_next_bit(iommu->domain_ids,
1287 cap_ndoms(iommu->cap), num+1);
1288 }
1289
1290 if (found) {
1291 clear_bit(num, iommu->domain_ids);
1292 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1293 iommu->domains[num] = NULL;
1294 }
8c11e798 1295 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1296}
1297
1298static struct iova_domain reserved_iova_list;
8a443df4
MG		 1299static struct lock_class_key reserved_alloc_key;
1300static struct lock_class_key reserved_rbtree_key;
ba395927
KA		 1301
1302static void dmar_init_reserved_ranges(void)
1303{
1304 struct pci_dev *pdev = NULL;
1305 struct iova *iova;
1306 int i;
ba395927 1307
f661197e 1308 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1309
8a443df4
MG		 1310 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1311 &reserved_alloc_key);
1312 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1313 &reserved_rbtree_key);
1314
ba395927
KA		 1315 /* IOAPIC ranges shouldn't be accessed by DMA */
1316 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1317 IOVA_PFN(IOAPIC_RANGE_END));
1318 if (!iova)
1319 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1320
1321 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1322 for_each_pci_dev(pdev) {
1323 struct resource *r;
1324
1325 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1326 r = &pdev->resource[i];
1327 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1328 continue;
1a4a4551
DW		 1329 iova = reserve_iova(&reserved_iova_list,
1330 IOVA_PFN(r->start),
1331 IOVA_PFN(r->end));
ba395927
KA		 1332 if (!iova)
1333 printk(KERN_ERR "Reserve iova failed\n");
1334 }
1335 }
1336
1337}
1338
1339static void domain_reserve_special_ranges(struct dmar_domain *domain)
1340{
1341 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1342}
1343
1344static inline int guestwidth_to_adjustwidth(int gaw)
1345{
1346 int agaw;
1347 int r = (gaw - 12) % 9;
1348
1349 if (r == 0)
1350 agaw = gaw;
1351 else
1352 agaw = gaw + 9 - r;
1353 if (agaw > 64)
1354 agaw = 64;
1355 return agaw;
1356}
1357
1358static int domain_init(struct dmar_domain *domain, int guest_width)
1359{
1360 struct intel_iommu *iommu;
1361 int adjust_width, agaw;
1362 unsigned long sagaw;
1363
f661197e 1364 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
ba395927 1365 spin_lock_init(&domain->mapping_lock);
c7151a8d 1366 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1367
1368 domain_reserve_special_ranges(domain);
1369
1370 /* calculate AGAW */
8c11e798 1371 iommu = domain_get_iommu(domain);
ba395927
KA		 1372 if (guest_width > cap_mgaw(iommu->cap))
1373 guest_width = cap_mgaw(iommu->cap);
1374 domain->gaw = guest_width;
1375 adjust_width = guestwidth_to_adjustwidth(guest_width);
1376 agaw = width_to_agaw(adjust_width);
1377 sagaw = cap_sagaw(iommu->cap);
1378 if (!test_bit(agaw, &sagaw)) {
1379 /* hardware doesn't support it, choose a bigger one */
1380 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1381 agaw = find_next_bit(&sagaw, 5, agaw);
1382 if (agaw >= 5)
1383 return -ENODEV;
1384 }
1385 domain->agaw = agaw;
1386 INIT_LIST_HEAD(&domain->devices);
1387
8e604097
WH		 1388 if (ecap_coherent(iommu->ecap))
1389 domain->iommu_coherency = 1;
1390 else
1391 domain->iommu_coherency = 0;
1392
58c610bd
SY		 1393 if (ecap_sc_support(iommu->ecap))
1394 domain->iommu_snooping = 1;
1395 else
1396 domain->iommu_snooping = 0;
1397
c7151a8d
WH		 1398 domain->iommu_count = 1;
1399
ba395927
KA		 1400 /* always allocate the top pgd */
1401 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1402 if (!domain->pgd)
1403 return -ENOMEM;
5b6985ce 1404 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1405 return 0;
1406}
1407
1408static void domain_exit(struct dmar_domain *domain)
1409{
2c2e2c38
FY		 1410 struct dmar_drhd_unit *drhd;
1411 struct intel_iommu *iommu;
ba395927
KA		 1412
1413 /* Domain 0 is reserved, so dont process it */
1414 if (!domain)
1415 return;
1416
1417 domain_remove_dev_info(domain);
1418 /* destroy iovas */
1419 put_iova_domain(&domain->iovad);
ba395927
KA		 1420
1421 /* clear ptes */
595badf5 1422 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927
KA		 1423
1424 /* free page tables */
d794dc9b 1425 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1426
2c2e2c38
FY		 1427 for_each_active_iommu(iommu, drhd)
1428 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1429 iommu_detach_domain(domain, iommu);
1430
ba395927
KA		 1431 free_domain_mem(domain);
1432}
1433
4ed0d3e6
FY		 1434static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1435 u8 bus, u8 devfn, int translation)
ba395927
KA		 1436{
1437 struct context_entry *context;
ba395927 1438 unsigned long flags;
5331fe6f 1439 struct intel_iommu *iommu;
ea6606b0
WH		 1440 struct dma_pte *pgd;
1441 unsigned long num;
1442 unsigned long ndomains;
1443 int id;
1444 int agaw;
93a23a72 1445 struct device_domain_info *info = NULL;
ba395927
KA		 1446
1447 pr_debug("Set context mapping for %02x:%02x.%d\n",
1448 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1449
ba395927 1450 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1451 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1452 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1453
276dbf99 1454 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1455 if (!iommu)
1456 return -ENODEV;
1457
ba395927
KA		 1458 context = device_to_context_entry(iommu, bus, devfn);
1459 if (!context)
1460 return -ENOMEM;
1461 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1462 if (context_present(context)) {
ba395927
KA		 1463 spin_unlock_irqrestore(&iommu->lock, flags);
1464 return 0;
1465 }
1466
ea6606b0
WH		 1467 id = domain->id;
1468 pgd = domain->pgd;
1469
2c2e2c38
FY		 1470 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1471 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1472 int found = 0;
1473
1474 /* find an available domain id for this device in iommu */
1475 ndomains = cap_ndoms(iommu->cap);
1476 num = find_first_bit(iommu->domain_ids, ndomains);
1477 for (; num < ndomains; ) {
1478 if (iommu->domains[num] == domain) {
1479 id = num;
1480 found = 1;
1481 break;
1482 }
1483 num = find_next_bit(iommu->domain_ids,
1484 cap_ndoms(iommu->cap), num+1);
1485 }
1486
1487 if (found == 0) {
1488 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1489 if (num >= ndomains) {
1490 spin_unlock_irqrestore(&iommu->lock, flags);
1491 printk(KERN_ERR "IOMMU: no free domain ids\n");
1492 return -EFAULT;
1493 }
1494
1495 set_bit(num, iommu->domain_ids);
2c2e2c38 1496 set_bit(iommu->seq_id, &domain->iommu_bmp);
ea6606b0
WH		 1497 iommu->domains[num] = domain;
1498 id = num;
1499 }
1500
1501 /* Skip top levels of page tables for
1502 * iommu which has less agaw than default.
1503 */
1504 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1505 pgd = phys_to_virt(dma_pte_addr(pgd));
1506 if (!dma_pte_present(pgd)) {
1507 spin_unlock_irqrestore(&iommu->lock, flags);
1508 return -ENOMEM;
1509 }
1510 }
1511 }
1512
1513 context_set_domain_id(context, id);
4ed0d3e6 1514
93a23a72
YZ		 1515 if (translation != CONTEXT_TT_PASS_THROUGH) {
1516 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1517 translation = info ? CONTEXT_TT_DEV_IOTLB :
1518 CONTEXT_TT_MULTI_LEVEL;
1519 }
4ed0d3e6
FY		 1520 /*
1521 * In pass through mode, AW must be programmed to indicate the largest
1522 * AGAW value supported by hardware. And ASR is ignored by hardware.
1523 */
93a23a72 1524 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1525 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1526 else {
1527 context_set_address_root(context, virt_to_phys(pgd));
1528 context_set_address_width(context, iommu->agaw);
1529 }
4ed0d3e6
FY		 1530
1531 context_set_translation_type(context, translation);
c07e7d21
MM		 1532 context_set_fault_enable(context);
1533 context_set_present(context);
5331fe6f 1534 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1535
4c25a2c1
DW		 1536 /*
1537 * It's a non-present to present mapping. If hardware doesn't cache
1538 * non-present entry we only need to flush the write-buffer. If the
1539 * _does_ cache non-present entries, then it does so in the special
1540 * domain #0, which we have to flush:
1541 */
1542 if (cap_caching_mode(iommu->cap)) {
1543 iommu->flush.flush_context(iommu, 0,
1544 (((u16)bus) << 8) | devfn,
1545 DMA_CCMD_MASK_NOBIT,
1546 DMA_CCMD_DEVICE_INVL);
1f0ef2aa 1547 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1548 } else {
ba395927 1549 iommu_flush_write_buffer(iommu);
4c25a2c1 1550 }
93a23a72 1551 iommu_enable_dev_iotlb(info);
ba395927 1552 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1553
1554 spin_lock_irqsave(&domain->iommu_lock, flags);
1555 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1556 domain->iommu_count++;
58c610bd 1557 domain_update_iommu_cap(domain);
c7151a8d
WH		 1558 }
1559 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1560 return 0;
1561}
1562
1563static int
4ed0d3e6
FY		 1564domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1565 int translation)
ba395927
KA		 1566{
1567 int ret;
1568 struct pci_dev *tmp, *parent;
1569
276dbf99 1570 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1571 pdev->bus->number, pdev->devfn,
1572 translation);
ba395927
KA		 1573 if (ret)
1574 return ret;
1575
1576 /* dependent device mapping */
1577 tmp = pci_find_upstream_pcie_bridge(pdev);
1578 if (!tmp)
1579 return 0;
1580 /* Secondary interface's bus number and devfn 0 */
1581 parent = pdev->bus->self;
1582 while (parent != tmp) {
276dbf99
DW		 1583 ret = domain_context_mapping_one(domain,
1584 pci_domain_nr(parent->bus),
1585 parent->bus->number,
4ed0d3e6 1586 parent->devfn, translation);
ba395927
KA		 1587 if (ret)
1588 return ret;
1589 parent = parent->bus->self;
1590 }
1591 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1592 return domain_context_mapping_one(domain,
276dbf99 1593 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1594 tmp->subordinate->number, 0,
1595 translation);
ba395927
KA		 1596 else /* this is a legacy PCI bridge */
1597 return domain_context_mapping_one(domain,
276dbf99
DW		 1598 pci_domain_nr(tmp->bus),
1599 tmp->bus->number,
4ed0d3e6
FY		 1600 tmp->devfn,
1601 translation);
ba395927
KA		 1602}
1603
5331fe6f 1604static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1605{
1606 int ret;
1607 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1608 struct intel_iommu *iommu;
1609
276dbf99
DW		 1610 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1611 pdev->devfn);
5331fe6f
WH		 1612 if (!iommu)
1613 return -ENODEV;
ba395927 1614
276dbf99 1615 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1616 if (!ret)
1617 return ret;
1618 /* dependent device mapping */
1619 tmp = pci_find_upstream_pcie_bridge(pdev);
1620 if (!tmp)
1621 return ret;
1622 /* Secondary interface's bus number and devfn 0 */
1623 parent = pdev->bus->self;
1624 while (parent != tmp) {
8c11e798 1625 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1626 parent->devfn);
ba395927
KA		 1627 if (!ret)
1628 return ret;
1629 parent = parent->bus->self;
1630 }
1631 if (tmp->is_pcie)
276dbf99
DW		 1632 return device_context_mapped(iommu, tmp->subordinate->number,
1633 0);
ba395927 1634 else
276dbf99
DW		 1635 return device_context_mapped(iommu, tmp->bus->number,
1636 tmp->devfn);
ba395927
KA		 1637}
1638
61df7443
DW		 1639static int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1640 unsigned long phys_pfn, unsigned long nr_pages,
1641 int prot)
ba395927 1642{
ba395927 1643 struct dma_pte *pte;
1c5a46ed 1644 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
5b6985ce 1645
61df7443 1646 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
ba395927
KA		 1647
1648 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1649 return -EINVAL;
1c5a46ed 1650
61df7443
DW		 1651 while (nr_pages--) {
1652 pte = pfn_to_dma_pte(domain, iov_pfn);
ba395927
KA		 1653 if (!pte)
1654 return -ENOMEM;
1655 /* We don't need lock here, nobody else
1656 * touches the iova range
1657 */
19c239ce 1658 BUG_ON(dma_pte_addr(pte));
61df7443 1659 dma_set_pte_pfn(pte, phys_pfn);
19c239ce 1660 dma_set_pte_prot(pte, prot);
9cf06697
SY		 1661 if (prot & DMA_PTE_SNP)
1662 dma_set_pte_snp(pte);
5331fe6f 1663 domain_flush_cache(domain, pte, sizeof(*pte));
61df7443
DW		 1664 iov_pfn++;
1665 phys_pfn++;
ba395927
KA		 1666 }
1667 return 0;
1668}
1669
c7151a8d 1670static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1671{
c7151a8d
WH		 1672 if (!iommu)
1673 return;
8c11e798
WH		 1674
1675 clear_context_table(iommu, bus, devfn);
1676 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1677 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1678 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1679}
1680
1681static void domain_remove_dev_info(struct dmar_domain *domain)
1682{
1683 struct device_domain_info *info;
1684 unsigned long flags;
c7151a8d 1685 struct intel_iommu *iommu;
ba395927
KA		 1686
1687 spin_lock_irqsave(&device_domain_lock, flags);
1688 while (!list_empty(&domain->devices)) {
1689 info = list_entry(domain->devices.next,
1690 struct device_domain_info, link);
1691 list_del(&info->link);
1692 list_del(&info->global);
1693 if (info->dev)
358dd8ac 1694 info->dev->dev.archdata.iommu = NULL;
ba395927
KA		 1695 spin_unlock_irqrestore(&device_domain_lock, flags);
1696
93a23a72 1697 iommu_disable_dev_iotlb(info);
276dbf99 1698 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1699 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1700 free_devinfo_mem(info);
1701
1702 spin_lock_irqsave(&device_domain_lock, flags);
1703 }
1704 spin_unlock_irqrestore(&device_domain_lock, flags);
1705}
1706
1707/*
1708 * find_domain
358dd8ac 1709 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1710 */
38717946 1711static struct dmar_domain *
ba395927
KA		 1712find_domain(struct pci_dev *pdev)
1713{
1714 struct device_domain_info *info;
1715
1716 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1717 info = pdev->dev.archdata.iommu;
ba395927
KA		 1718 if (info)
1719 return info->domain;
1720 return NULL;
1721}
1722
ba395927
KA		 1723/* domain is initialized */
1724static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1725{
1726 struct dmar_domain *domain, *found = NULL;
1727 struct intel_iommu *iommu;
1728 struct dmar_drhd_unit *drhd;
1729 struct device_domain_info *info, *tmp;
1730 struct pci_dev *dev_tmp;
1731 unsigned long flags;
1732 int bus = 0, devfn = 0;
276dbf99 1733 int segment;
2c2e2c38 1734 int ret;
ba395927
KA		 1735
1736 domain = find_domain(pdev);
1737 if (domain)
1738 return domain;
1739
276dbf99
DW		 1740 segment = pci_domain_nr(pdev->bus);
1741
ba395927
KA		 1742 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1743 if (dev_tmp) {
1744 if (dev_tmp->is_pcie) {
1745 bus = dev_tmp->subordinate->number;
1746 devfn = 0;
1747 } else {
1748 bus = dev_tmp->bus->number;
1749 devfn = dev_tmp->devfn;
1750 }
1751 spin_lock_irqsave(&device_domain_lock, flags);
1752 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1753 if (info->segment == segment &&
1754 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1755 found = info->domain;
1756 break;
1757 }
1758 }
1759 spin_unlock_irqrestore(&device_domain_lock, flags);
1760 /* pcie-pci bridge already has a domain, uses it */
1761 if (found) {
1762 domain = found;
1763 goto found_domain;
1764 }
1765 }
1766
2c2e2c38
FY		 1767 domain = alloc_domain();
1768 if (!domain)
1769 goto error;
1770
ba395927
KA		 1771 /* Allocate new domain for the device */
1772 drhd = dmar_find_matched_drhd_unit(pdev);
1773 if (!drhd) {
1774 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1775 pci_name(pdev));
1776 return NULL;
1777 }
1778 iommu = drhd->iommu;
1779
2c2e2c38
FY		 1780 ret = iommu_attach_domain(domain, iommu);
1781 if (ret) {
1782 domain_exit(domain);
ba395927 1783 goto error;
2c2e2c38 1784 }
ba395927
KA		 1785
1786 if (domain_init(domain, gaw)) {
1787 domain_exit(domain);
1788 goto error;
1789 }
1790
1791 /* register pcie-to-pci device */
1792 if (dev_tmp) {
1793 info = alloc_devinfo_mem();
1794 if (!info) {
1795 domain_exit(domain);
1796 goto error;
1797 }
276dbf99 1798 info->segment = segment;
ba395927
KA		 1799 info->bus = bus;
1800 info->devfn = devfn;
1801 info->dev = NULL;
1802 info->domain = domain;
1803 /* This domain is shared by devices under p2p bridge */
3b5410e7 1804 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 1805
1806 /* pcie-to-pci bridge already has a domain, uses it */
1807 found = NULL;
1808 spin_lock_irqsave(&device_domain_lock, flags);
1809 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 1810 if (tmp->segment == segment &&
1811 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 1812 found = tmp->domain;
1813 break;
1814 }
1815 }
1816 if (found) {
1817 free_devinfo_mem(info);
1818 domain_exit(domain);
1819 domain = found;
1820 } else {
1821 list_add(&info->link, &domain->devices);
1822 list_add(&info->global, &device_domain_list);
1823 }
1824 spin_unlock_irqrestore(&device_domain_lock, flags);
1825 }
1826
1827found_domain:
1828 info = alloc_devinfo_mem();
1829 if (!info)
1830 goto error;
276dbf99 1831 info->segment = segment;
ba395927
KA		 1832 info->bus = pdev->bus->number;
1833 info->devfn = pdev->devfn;
1834 info->dev = pdev;
1835 info->domain = domain;
1836 spin_lock_irqsave(&device_domain_lock, flags);
1837 /* somebody is fast */
1838 found = find_domain(pdev);
1839 if (found != NULL) {
1840 spin_unlock_irqrestore(&device_domain_lock, flags);
1841 if (found != domain) {
1842 domain_exit(domain);
1843 domain = found;
1844 }
1845 free_devinfo_mem(info);
1846 return domain;
1847 }
1848 list_add(&info->link, &domain->devices);
1849 list_add(&info->global, &device_domain_list);
358dd8ac 1850 pdev->dev.archdata.iommu = info;
ba395927
KA		 1851 spin_unlock_irqrestore(&device_domain_lock, flags);
1852 return domain;
1853error:
1854 /* recheck it here, maybe others set it */
1855 return find_domain(pdev);
1856}
1857
2c2e2c38
FY		 1858static int iommu_identity_mapping;
1859
b213203e
DW		 1860static int iommu_domain_identity_map(struct dmar_domain *domain,
1861 unsigned long long start,
1862 unsigned long long end)
ba395927 1863{
c5395d5c
DW		 1864 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1865 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1866
1867 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1868 dma_to_mm_pfn(last_vpfn))) {
ba395927 1869 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 1870 return -ENOMEM;
ba395927
KA		 1871 }
1872
c5395d5c
DW		 1873 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1874 start, end, domain->id);
ba395927
KA		 1875 /*
1876 * RMRR range might have overlap with physical memory range,
1877 * clear it first
1878 */
c5395d5c 1879 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 1880
c5395d5c
DW		 1881 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1882 last_vpfn - first_vpfn + 1,
61df7443 1883 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 1884}
1885
1886static int iommu_prepare_identity_map(struct pci_dev *pdev,
1887 unsigned long long start,
1888 unsigned long long end)
1889{
1890 struct dmar_domain *domain;
1891 int ret;
1892
1893 printk(KERN_INFO
1894 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1895 pci_name(pdev), start, end);
1896
c7ab48d2 1897 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 1898 if (!domain)
1899 return -ENOMEM;
1900
1901 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 1902 if (ret)
1903 goto error;
1904
1905 /* context entry init */
4ed0d3e6 1906 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 1907 if (ret)
1908 goto error;
1909
1910 return 0;
1911
1912 error:
ba395927
KA		 1913 domain_exit(domain);
1914 return ret;
ba395927
KA		 1915}
1916
1917static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1918 struct pci_dev *pdev)
1919{
358dd8ac 1920 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 1921 return 0;
1922 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1923 rmrr->end_address + 1);
1924}
1925
49a0429e
KA		 1926#ifdef CONFIG_DMAR_FLOPPY_WA
1927static inline void iommu_prepare_isa(void)
1928{
1929 struct pci_dev *pdev;
1930 int ret;
1931
1932 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1933 if (!pdev)
1934 return;
1935
c7ab48d2 1936 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
49a0429e
KA		 1937 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1938
1939 if (ret)
c7ab48d2
DW		 1940 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
1941 "floppy might not work\n");
49a0429e
KA		 1942
1943}
1944#else
1945static inline void iommu_prepare_isa(void)
1946{
1947 return;
1948}
1949#endif /* !CONFIG_DMAR_FLPY_WA */
1950
4ed0d3e6
FY		 1951/* Initialize each context entry as pass through.*/
1952static int __init init_context_pass_through(void)
1953{
1954 struct pci_dev *pdev = NULL;
1955 struct dmar_domain *domain;
1956 int ret;
1957
1958 for_each_pci_dev(pdev) {
1959 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1960 ret = domain_context_mapping(domain, pdev,
1961 CONTEXT_TT_PASS_THROUGH);
1962 if (ret)
1963 return ret;
1964 }
1965 return 0;
1966}
1967
2c2e2c38 1968static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2
DW		 1969
1970static int __init si_domain_work_fn(unsigned long start_pfn,
1971 unsigned long end_pfn, void *datax)
1972{
1973 int *ret = datax;
1974
1975 *ret = iommu_domain_identity_map(si_domain,
1976 (uint64_t)start_pfn << PAGE_SHIFT,
1977 (uint64_t)end_pfn << PAGE_SHIFT);
1978 return *ret;
1979
1980}
1981
2c2e2c38
FY		 1982static int si_domain_init(void)
1983{
1984 struct dmar_drhd_unit *drhd;
1985 struct intel_iommu *iommu;
c7ab48d2 1986 int nid, ret = 0;
2c2e2c38
FY		 1987
1988 si_domain = alloc_domain();
1989 if (!si_domain)
1990 return -EFAULT;
1991
c7ab48d2 1992 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2c2e2c38
FY		 1993
1994 for_each_active_iommu(iommu, drhd) {
1995 ret = iommu_attach_domain(si_domain, iommu);
1996 if (ret) {
1997 domain_exit(si_domain);
1998 return -EFAULT;
1999 }
2000 }
2001
2002 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2003 domain_exit(si_domain);
2004 return -EFAULT;
2005 }
2006
2007 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2008
c7ab48d2
DW		 2009 for_each_online_node(nid) {
2010 work_with_active_regions(nid, si_domain_work_fn, &ret);
2011 if (ret)
2012 return ret;
2013 }
2014
2c2e2c38
FY		 2015 return 0;
2016}
2017
2018static void domain_remove_one_dev_info(struct dmar_domain *domain,
2019 struct pci_dev *pdev);
2020static int identity_mapping(struct pci_dev *pdev)
2021{
2022 struct device_domain_info *info;
2023
2024 if (likely(!iommu_identity_mapping))
2025 return 0;
2026
2027
2028 list_for_each_entry(info, &si_domain->devices, link)
2029 if (info->dev == pdev)
2030 return 1;
2031 return 0;
2032}
2033
2034static int domain_add_dev_info(struct dmar_domain *domain,
2035 struct pci_dev *pdev)
2036{
2037 struct device_domain_info *info;
2038 unsigned long flags;
2039
2040 info = alloc_devinfo_mem();
2041 if (!info)
2042 return -ENOMEM;
2043
2044 info->segment = pci_domain_nr(pdev->bus);
2045 info->bus = pdev->bus->number;
2046 info->devfn = pdev->devfn;
2047 info->dev = pdev;
2048 info->domain = domain;
2049
2050 spin_lock_irqsave(&device_domain_lock, flags);
2051 list_add(&info->link, &domain->devices);
2052 list_add(&info->global, &device_domain_list);
2053 pdev->dev.archdata.iommu = info;
2054 spin_unlock_irqrestore(&device_domain_lock, flags);
2055
2056 return 0;
2057}
2058
2059static int iommu_prepare_static_identity_mapping(void)
2060{
2c2e2c38
FY		 2061 struct pci_dev *pdev = NULL;
2062 int ret;
2063
2064 ret = si_domain_init();
2065 if (ret)
2066 return -EFAULT;
2067
2c2e2c38 2068 for_each_pci_dev(pdev) {
c7ab48d2
DW		 2069 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2070 pci_name(pdev));
2071
2072 ret = domain_context_mapping(si_domain, pdev,
2073 CONTEXT_TT_MULTI_LEVEL);
2074 if (ret)
2075 return ret;
2c2e2c38
FY		 2076 ret = domain_add_dev_info(si_domain, pdev);
2077 if (ret)
2078 return ret;
2079 }
2080
2081 return 0;
2082}
2083
2084int __init init_dmars(void)
ba395927
KA		 2085{
2086 struct dmar_drhd_unit *drhd;
2087 struct dmar_rmrr_unit *rmrr;
2088 struct pci_dev *pdev;
2089 struct intel_iommu *iommu;
9d783ba0 2090 int i, ret;
4ed0d3e6 2091 int pass_through = 1;
ba395927 2092
2c2e2c38
FY		 2093 /*
2094 * In case pass through can not be enabled, iommu tries to use identity
2095 * mapping.
2096 */
2097 if (iommu_pass_through)
2098 iommu_identity_mapping = 1;
2099
ba395927
KA		 2100 /*
2101 * for each drhd
2102 * allocate root
2103 * initialize and program root entry to not present
2104 * endfor
2105 */
2106 for_each_drhd_unit(drhd) {
5e0d2a6f 2107 g_num_of_iommus++;
2108 /*
2109 * lock not needed as this is only incremented in the single
2110 * threaded kernel __init code path all other access are read
2111 * only
2112 */
2113 }
2114
d9630fe9
WH		 2115 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2116 GFP_KERNEL);
2117 if (!g_iommus) {
2118 printk(KERN_ERR "Allocating global iommu array failed\n");
2119 ret = -ENOMEM;
2120 goto error;
2121 }
2122
80b20dd8 2123 deferred_flush = kzalloc(g_num_of_iommus *
2124 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2125 if (!deferred_flush) {
d9630fe9 2126 kfree(g_iommus);
5e0d2a6f 2127 ret = -ENOMEM;
2128 goto error;
2129 }
2130
5e0d2a6f 2131 for_each_drhd_unit(drhd) {
2132 if (drhd->ignored)
2133 continue;
1886e8a9
SS		 2134
2135 iommu = drhd->iommu;
d9630fe9 2136 g_iommus[iommu->seq_id] = iommu;
ba395927 2137
e61d98d8
SS		 2138 ret = iommu_init_domains(iommu);
2139 if (ret)
2140 goto error;
2141
ba395927
KA		 2142 /*
2143 * TBD:
2144 * we could share the same root & context tables
2145 * amoung all IOMMU's. Need to Split it later.
2146 */
2147 ret = iommu_alloc_root_entry(iommu);
2148 if (ret) {
2149 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2150 goto error;
2151 }
4ed0d3e6
FY		 2152 if (!ecap_pass_through(iommu->ecap))
2153 pass_through = 0;
ba395927 2154 }
4ed0d3e6
FY		 2155 if (iommu_pass_through)
2156 if (!pass_through) {
2157 printk(KERN_INFO
2158 "Pass Through is not supported by hardware.\n");
2159 iommu_pass_through = 0;
2160 }
ba395927 2161
1531a6a6
SS		 2162 /*
2163 * Start from the sane iommu hardware state.
2164 */
a77b67d4
YS		 2165 for_each_drhd_unit(drhd) {
2166 if (drhd->ignored)
2167 continue;
2168
2169 iommu = drhd->iommu;
1531a6a6
SS		 2170
2171 /*
2172 * If the queued invalidation is already initialized by us
2173 * (for example, while enabling interrupt-remapping) then
2174 * we got the things already rolling from a sane state.
2175 */
2176 if (iommu->qi)
2177 continue;
2178
2179 /*
2180 * Clear any previous faults.
2181 */
2182 dmar_fault(-1, iommu);
2183 /*
2184 * Disable queued invalidation if supported and already enabled
2185 * before OS handover.
2186 */
2187 dmar_disable_qi(iommu);
2188 }
2189
2190 for_each_drhd_unit(drhd) {
2191 if (drhd->ignored)
2192 continue;
2193
2194 iommu = drhd->iommu;
2195
a77b67d4
YS		 2196 if (dmar_enable_qi(iommu)) {
2197 /*
2198 * Queued Invalidate not enabled, use Register Based
2199 * Invalidate
2200 */
2201 iommu->flush.flush_context = __iommu_flush_context;
2202 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2203 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
b4e0f9eb
FT		 2204 "invalidation\n",
2205 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2206 } else {
2207 iommu->flush.flush_context = qi_flush_context;
2208 iommu->flush.flush_iotlb = qi_flush_iotlb;
2209 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
b4e0f9eb
FT		 2210 "invalidation\n",
2211 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2212 }
2213 }
2214
ba395927 2215 /*
4ed0d3e6
FY		 2216 * If pass through is set and enabled, context entries of all pci
2217 * devices are intialized by pass through translation type.
ba395927 2218 */
4ed0d3e6
FY		 2219 if (iommu_pass_through) {
2220 ret = init_context_pass_through();
2221 if (ret) {
2222 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2223 iommu_pass_through = 0;
ba395927
KA		 2224 }
2225 }
2226
ba395927 2227 /*
4ed0d3e6 2228 * If pass through is not set or not enabled, setup context entries for
2c2e2c38
FY		 2229 * identity mappings for rmrr, gfx, and isa and may fall back to static
2230 * identity mapping if iommu_identity_mapping is set.
ba395927 2231 */
4ed0d3e6 2232 if (!iommu_pass_through) {
2c2e2c38
FY		 2233 if (iommu_identity_mapping)
2234 iommu_prepare_static_identity_mapping();
4ed0d3e6
FY		 2235 /*
2236 * For each rmrr
2237 * for each dev attached to rmrr
2238 * do
2239 * locate drhd for dev, alloc domain for dev
2240 * allocate free domain
2241 * allocate page table entries for rmrr
2242 * if context not allocated for bus
2243 * allocate and init context
2244 * set present in root table for this bus
2245 * init context with domain, translation etc
2246 * endfor
2247 * endfor
2248 */
2c2e2c38 2249 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
4ed0d3e6
FY		 2250 for_each_rmrr_units(rmrr) {
2251 for (i = 0; i < rmrr->devices_cnt; i++) {
2252 pdev = rmrr->devices[i];
2253 /*
2254 * some BIOS lists non-exist devices in DMAR
2255 * table.
2256 */
2257 if (!pdev)
2258 continue;
2259 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2260 if (ret)
2261 printk(KERN_ERR
ba395927 2262 "IOMMU: mapping reserved region failed\n");
4ed0d3e6 2263 }
ba395927 2264 }
ba395927 2265
4ed0d3e6
FY		 2266 iommu_prepare_isa();
2267 }
49a0429e 2268
ba395927
KA		 2269 /*
2270 * for each drhd
2271 * enable fault log
2272 * global invalidate context cache
2273 * global invalidate iotlb
2274 * enable translation
2275 */
2276 for_each_drhd_unit(drhd) {
2277 if (drhd->ignored)
2278 continue;
2279 iommu = drhd->iommu;
ba395927
KA		 2280
2281 iommu_flush_write_buffer(iommu);
2282
3460a6d9
KA		 2283 ret = dmar_set_interrupt(iommu);
2284 if (ret)
2285 goto error;
2286
ba395927
KA		 2287 iommu_set_root_entry(iommu);
2288
4c25a2c1 2289 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2290 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2291 iommu_disable_protect_mem_regions(iommu);
2292
ba395927
KA		 2293 ret = iommu_enable_translation(iommu);
2294 if (ret)
2295 goto error;
2296 }
2297
2298 return 0;
2299error:
2300 for_each_drhd_unit(drhd) {
2301 if (drhd->ignored)
2302 continue;
2303 iommu = drhd->iommu;
2304 free_iommu(iommu);
2305 }
d9630fe9 2306 kfree(g_iommus);
ba395927
KA		 2307 return ret;
2308}
2309
88cb6a74
DW		 2310static inline unsigned long aligned_nrpages(unsigned long host_addr,
2311 size_t size)
ba395927 2312{
88cb6a74
DW		 2313 host_addr &= ~PAGE_MASK;
2314 host_addr += size + PAGE_SIZE - 1;
2315
2316 return host_addr >> VTD_PAGE_SHIFT;
ba395927
KA		 2317}
2318
2319struct iova *
f76aec76 2320iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
ba395927 2321{
ba395927
KA		 2322 struct iova *piova;
2323
2324 /* Make sure it's in range */
ba395927 2325 end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
f76aec76 2326 if (!size || (IOVA_START_ADDR + size > end))
ba395927
KA		 2327 return NULL;
2328
2329 piova = alloc_iova(&domain->iovad,
5b6985ce 2330 size >> PAGE_SHIFT, IOVA_PFN(end), 1);
ba395927
KA		 2331 return piova;
2332}
2333
f76aec76
KA		 2334static struct iova *
2335__intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
bb9e6d65 2336 size_t size, u64 dma_mask)
ba395927 2337{
ba395927 2338 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2339 struct iova *iova = NULL;
ba395927 2340
284901a9 2341 if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
bb9e6d65
FT		 2342 iova = iommu_alloc_iova(domain, size, dma_mask);
2343 else {
ba395927
KA		 2344 /*
2345 * First try to allocate an io virtual address in
284901a9 2346 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2347 * from higher range
ba395927 2348 */
284901a9 2349 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
ba395927 2350 if (!iova)
bb9e6d65 2351 iova = iommu_alloc_iova(domain, size, dma_mask);
ba395927
KA		 2352 }
2353
2354 if (!iova) {
2355 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
f76aec76
KA		 2356 return NULL;
2357 }
2358
2359 return iova;
2360}
2361
2362static struct dmar_domain *
2363get_valid_domain_for_dev(struct pci_dev *pdev)
2364{
2365 struct dmar_domain *domain;
2366 int ret;
2367
2368 domain = get_domain_for_dev(pdev,
2369 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2370 if (!domain) {
2371 printk(KERN_ERR
2372 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2373 return NULL;
ba395927
KA		 2374 }
2375
2376 /* make sure context mapping is ok */
5331fe6f 2377 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2378 ret = domain_context_mapping(domain, pdev,
2379 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2380 if (ret) {
2381 printk(KERN_ERR
2382 "Domain context map for %s failed",
2383 pci_name(pdev));
4fe05bbc 2384 return NULL;
f76aec76 2385 }
ba395927
KA		 2386 }
2387
f76aec76
KA		 2388 return domain;
2389}
2390
2c2e2c38
FY		 2391static int iommu_dummy(struct pci_dev *pdev)
2392{
2393 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2394}
2395
2396/* Check if the pdev needs to go through non-identity map and unmap process.*/
2397static int iommu_no_mapping(struct pci_dev *pdev)
2398{
2399 int found;
2400
2401 if (!iommu_identity_mapping)
2402 return iommu_dummy(pdev);
2403
2404 found = identity_mapping(pdev);
2405 if (found) {
2406 if (pdev->dma_mask > DMA_BIT_MASK(32))
2407 return 1;
2408 else {
2409 /*
2410 * 32 bit DMA is removed from si_domain and fall back
2411 * to non-identity mapping.
2412 */
2413 domain_remove_one_dev_info(si_domain, pdev);
2414 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2415 pci_name(pdev));
2416 return 0;
2417 }
2418 } else {
2419 /*
2420 * In case of a detached 64 bit DMA device from vm, the device
2421 * is put into si_domain for identity mapping.
2422 */
2423 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2424 int ret;
2425 ret = domain_add_dev_info(si_domain, pdev);
2426 if (!ret) {
2427 printk(KERN_INFO "64bit %s uses identity mapping\n",
2428 pci_name(pdev));
2429 return 1;
2430 }
2431 }
2432 }
2433
2434 return iommu_dummy(pdev);
2435}
2436
bb9e6d65
FT		 2437static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2438 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2439{
2440 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2441 struct dmar_domain *domain;
5b6985ce 2442 phys_addr_t start_paddr;
f76aec76
KA		 2443 struct iova *iova;
2444 int prot = 0;
6865f0d1 2445 int ret;
8c11e798 2446 struct intel_iommu *iommu;
f76aec76
KA		 2447
2448 BUG_ON(dir == DMA_NONE);
2c2e2c38
FY		 2449
2450 if (iommu_no_mapping(pdev))
6865f0d1 2451 return paddr;
f76aec76
KA		 2452
2453 domain = get_valid_domain_for_dev(pdev);
2454 if (!domain)
2455 return 0;
2456
8c11e798 2457 iommu = domain_get_iommu(domain);
88cb6a74 2458 size = aligned_nrpages(paddr, size);
f76aec76 2459
0ab36de2 2460 iova = __intel_alloc_iova(hwdev, domain, size << VTD_PAGE_SHIFT, pdev->dma_mask);
f76aec76
KA		 2461 if (!iova)
2462 goto error;
2463
ba395927
KA		 2464 /*
2465 * Check if DMAR supports zero-length reads on write only
2466 * mappings..
2467 */
2468 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2469 !cap_zlr(iommu->cap))
ba395927
KA		 2470 prot |= DMA_PTE_READ;
2471 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2472 prot |= DMA_PTE_WRITE;
2473 /*
6865f0d1 2474 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2475 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2476 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2477 * is not a big problem
2478 */
0ab36de2
DW		 2479 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2480 paddr >> VTD_PAGE_SHIFT, size, prot);
ba395927
KA		 2481 if (ret)
2482 goto error;
2483
1f0ef2aa
DW		 2484 /* it's a non-present to present mapping. Only flush if caching mode */
2485 if (cap_caching_mode(iommu->cap))
03d6a246 2486 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
1f0ef2aa 2487 else
8c11e798 2488 iommu_flush_write_buffer(iommu);
f76aec76 2489
03d6a246
DW		 2490 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2491 start_paddr += paddr & ~PAGE_MASK;
2492 return start_paddr;
ba395927 2493
ba395927 2494error:
f76aec76
KA		 2495 if (iova)
2496 __free_iova(&domain->iovad, iova);
4cf2e75d 2497 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2498 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2499 return 0;
2500}
2501
ffbbef5c
FT		 2502static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2503 unsigned long offset, size_t size,
2504 enum dma_data_direction dir,
2505 struct dma_attrs *attrs)
bb9e6d65 2506{
ffbbef5c
FT		 2507 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2508 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2509}
2510
5e0d2a6f 2511static void flush_unmaps(void)
2512{
80b20dd8 2513 int i, j;
5e0d2a6f 2514
5e0d2a6f 2515 timer_on = 0;
2516
2517 /* just flush them all */
2518 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2519 struct intel_iommu *iommu = g_iommus[i];
2520 if (!iommu)
2521 continue;
c42d9f32 2522
9dd2fe89
YZ		 2523 if (!deferred_flush[i].next)
2524 continue;
2525
2526 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2527 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2528 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2529 unsigned long mask;
2530 struct iova *iova = deferred_flush[i].iova[j];
2531
2532 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2533 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2534 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2535 iova->pfn_lo << PAGE_SHIFT, mask);
2536 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2537 }
9dd2fe89 2538 deferred_flush[i].next = 0;
5e0d2a6f 2539 }
2540
5e0d2a6f 2541 list_size = 0;
5e0d2a6f 2542}
2543
2544static void flush_unmaps_timeout(unsigned long data)
2545{
80b20dd8 2546 unsigned long flags;
2547
2548 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2549 flush_unmaps();
80b20dd8 2550 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2551}
2552
2553static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2554{
2555 unsigned long flags;
80b20dd8 2556 int next, iommu_id;
8c11e798 2557 struct intel_iommu *iommu;
5e0d2a6f 2558
2559 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2560 if (list_size == HIGH_WATER_MARK)
2561 flush_unmaps();
2562
8c11e798
WH		 2563 iommu = domain_get_iommu(dom);
2564 iommu_id = iommu->seq_id;
c42d9f32 2565
80b20dd8 2566 next = deferred_flush[iommu_id].next;
2567 deferred_flush[iommu_id].domain[next] = dom;
2568 deferred_flush[iommu_id].iova[next] = iova;
2569 deferred_flush[iommu_id].next++;
5e0d2a6f 2570
2571 if (!timer_on) {
2572 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2573 timer_on = 1;
2574 }
2575 list_size++;
2576 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2577}
2578
ffbbef5c
FT		 2579static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2580 size_t size, enum dma_data_direction dir,
2581 struct dma_attrs *attrs)
ba395927 2582{
ba395927 2583 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 2584 struct dmar_domain *domain;
d794dc9b 2585 unsigned long start_pfn, last_pfn;
ba395927 2586 struct iova *iova;
8c11e798 2587 struct intel_iommu *iommu;
ba395927 2588
2c2e2c38 2589 if (iommu_no_mapping(pdev))
f76aec76 2590 return;
2c2e2c38 2591
ba395927
KA		 2592 domain = find_domain(pdev);
2593 BUG_ON(!domain);
2594
8c11e798
WH		 2595 iommu = domain_get_iommu(domain);
2596
ba395927 2597 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
f76aec76 2598 if (!iova)
ba395927 2599 return;
ba395927 2600
d794dc9b
DW		 2601 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2602 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 2603
d794dc9b
DW		 2604 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2605 pci_name(pdev), start_pfn, last_pfn);
ba395927 2606
f76aec76 2607 /* clear the whole page */
d794dc9b
DW		 2608 dma_pte_clear_range(domain, start_pfn, last_pfn);
2609
f76aec76 2610 /* free page tables */
d794dc9b
DW		 2611 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2612
5e0d2a6f 2613 if (intel_iommu_strict) {
03d6a246 2614 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
d794dc9b 2615 last_pfn - start_pfn + 1);
5e0d2a6f 2616 /* free iova */
2617 __free_iova(&domain->iovad, iova);
2618 } else {
2619 add_unmap(domain, iova);
2620 /*
2621 * queue up the release of the unmap to save the 1/6th of the
2622 * cpu used up by the iotlb flush operation...
2623 */
5e0d2a6f 2624 }
ba395927
KA		 2625}
2626
d7ab5c46
FT		 2627static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2628 int dir)
ffbbef5c
FT		 2629{
2630 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2631}
2632
d7ab5c46
FT		 2633static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2634 dma_addr_t *dma_handle, gfp_t flags)
ba395927
KA		 2635{
2636 void *vaddr;
2637 int order;
2638
5b6985ce 2639 size = PAGE_ALIGN(size);
ba395927
KA		 2640 order = get_order(size);
2641 flags &= ~(GFP_DMA | GFP_DMA32);
2642
2643 vaddr = (void *)__get_free_pages(flags, order);
2644 if (!vaddr)
2645 return NULL;
2646 memset(vaddr, 0, size);
2647
bb9e6d65
FT		 2648 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2649 DMA_BIDIRECTIONAL,
2650 hwdev->coherent_dma_mask);
ba395927
KA		 2651 if (*dma_handle)
2652 return vaddr;
2653 free_pages((unsigned long)vaddr, order);
2654 return NULL;
2655}
2656
d7ab5c46
FT		 2657static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2658 dma_addr_t dma_handle)
ba395927
KA		 2659{
2660 int order;
2661
5b6985ce 2662 size = PAGE_ALIGN(size);
ba395927
KA		 2663 order = get_order(size);
2664
2665 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2666 free_pages((unsigned long)vaddr, order);
2667}
2668
d7ab5c46
FT		 2669static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2670 int nelems, enum dma_data_direction dir,
2671 struct dma_attrs *attrs)
ba395927 2672{
ba395927
KA		 2673 struct pci_dev *pdev = to_pci_dev(hwdev);
2674 struct dmar_domain *domain;
d794dc9b 2675 unsigned long start_pfn, last_pfn;
f76aec76 2676 struct iova *iova;
8c11e798 2677 struct intel_iommu *iommu;
ba395927 2678
2c2e2c38 2679 if (iommu_no_mapping(pdev))
ba395927
KA		 2680 return;
2681
2682 domain = find_domain(pdev);
8c11e798
WH		 2683 BUG_ON(!domain);
2684
2685 iommu = domain_get_iommu(domain);
ba395927 2686
c03ab37c 2687 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
f76aec76
KA		 2688 if (!iova)
2689 return;
f76aec76 2690
d794dc9b
DW		 2691 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2692 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76
KA		 2693
2694 /* clear the whole page */
d794dc9b
DW		 2695 dma_pte_clear_range(domain, start_pfn, last_pfn);
2696
f76aec76 2697 /* free page tables */
d794dc9b 2698 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
f76aec76 2699
03d6a246 2700 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
d794dc9b 2701 (last_pfn - start_pfn + 1));
f76aec76
KA		 2702
2703 /* free iova */
2704 __free_iova(&domain->iovad, iova);
ba395927
KA		 2705}
2706
ba395927 2707static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 2708 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 2709{
2710 int i;
c03ab37c 2711 struct scatterlist *sg;
ba395927 2712
c03ab37c 2713 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 2714 BUG_ON(!sg_page(sg));
4cf2e75d 2715 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 2716 sg->dma_length = sg->length;
ba395927
KA		 2717 }
2718 return nelems;
2719}
2720
d7ab5c46
FT		 2721static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2722 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 2723{
ba395927 2724 int i;
ba395927
KA		 2725 struct pci_dev *pdev = to_pci_dev(hwdev);
2726 struct dmar_domain *domain;
f76aec76
KA		 2727 size_t size = 0;
2728 int prot = 0;
b536d24d 2729 size_t offset_pfn = 0;
f76aec76
KA		 2730 struct iova *iova = NULL;
2731 int ret;
c03ab37c 2732 struct scatterlist *sg;
b536d24d 2733 unsigned long start_vpfn;
8c11e798 2734 struct intel_iommu *iommu;
ba395927
KA		 2735
2736 BUG_ON(dir == DMA_NONE);
2c2e2c38 2737 if (iommu_no_mapping(pdev))
c03ab37c 2738 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 2739
f76aec76
KA		 2740 domain = get_valid_domain_for_dev(pdev);
2741 if (!domain)
2742 return 0;
2743
8c11e798
WH		 2744 iommu = domain_get_iommu(domain);
2745
b536d24d 2746 for_each_sg(sglist, sg, nelems, i)
88cb6a74 2747 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 2748
88cb6a74
DW		 2749 iova = __intel_alloc_iova(hwdev, domain, size << VTD_PAGE_SHIFT,
2750 pdev->dma_mask);
f76aec76 2751 if (!iova) {
c03ab37c 2752 sglist->dma_length = 0;
f76aec76
KA		 2753 return 0;
2754 }
2755
2756 /*
2757 * Check if DMAR supports zero-length reads on write only
2758 * mappings..
2759 */
2760 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2761 !cap_zlr(iommu->cap))
f76aec76
KA		 2762 prot |= DMA_PTE_READ;
2763 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2764 prot |= DMA_PTE_WRITE;
2765
b536d24d
DW		 2766 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2767 offset_pfn = 0;
c03ab37c 2768 for_each_sg(sglist, sg, nelems, i) {
88cb6a74 2769 int nr_pages = aligned_nrpages(sg->offset, sg->length);
b536d24d
DW		 2770 ret = domain_pfn_mapping(domain, start_vpfn + offset_pfn,
2771 page_to_dma_pfn(sg_page(sg)),
2772 nr_pages, prot);
f76aec76
KA		 2773 if (ret) {
2774 /* clear the page */
b536d24d
DW		 2775 dma_pte_clear_range(domain, start_vpfn,
2776 start_vpfn + offset_pfn);
f76aec76 2777 /* free page tables */
b536d24d
DW		 2778 dma_pte_free_pagetable(domain, start_vpfn,
2779 start_vpfn + offset_pfn);
f76aec76
KA		 2780 /* free iova */
2781 __free_iova(&domain->iovad, iova);
ba395927
KA		 2782 return 0;
2783 }
b536d24d
DW		 2784 sg->dma_address = ((dma_addr_t)(start_vpfn + offset_pfn)
2785 << VTD_PAGE_SHIFT) + sg->offset;
ba395927 2786 sg->dma_length = sg->length;
b536d24d 2787 offset_pfn += nr_pages;
ba395927
KA		 2788 }
2789
1f0ef2aa
DW		 2790 /* it's a non-present to present mapping. Only flush if caching mode */
2791 if (cap_caching_mode(iommu->cap))
03d6a246 2792 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
1f0ef2aa 2793 else
8c11e798 2794 iommu_flush_write_buffer(iommu);
1f0ef2aa 2795
ba395927
KA		 2796 return nelems;
2797}
2798
dfb805e8
FT		 2799static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2800{
2801 return !dma_addr;
2802}
2803
160c1d8e 2804struct dma_map_ops intel_dma_ops = {
ba395927
KA		 2805 .alloc_coherent = intel_alloc_coherent,
2806 .free_coherent = intel_free_coherent,
ba395927
KA		 2807 .map_sg = intel_map_sg,
2808 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 2809 .map_page = intel_map_page,
2810 .unmap_page = intel_unmap_page,
dfb805e8 2811 .mapping_error = intel_mapping_error,
ba395927
KA		 2812};
2813
2814static inline int iommu_domain_cache_init(void)
2815{
2816 int ret = 0;
2817
2818 iommu_domain_cache = kmem_cache_create("iommu_domain",
2819 sizeof(struct dmar_domain),
2820 0,
2821 SLAB_HWCACHE_ALIGN,
2822
2823 NULL);
2824 if (!iommu_domain_cache) {
2825 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2826 ret = -ENOMEM;
2827 }
2828
2829 return ret;
2830}
2831
2832static inline int iommu_devinfo_cache_init(void)
2833{
2834 int ret = 0;
2835
2836 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2837 sizeof(struct device_domain_info),
2838 0,
2839 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2840 NULL);
2841 if (!iommu_devinfo_cache) {
2842 printk(KERN_ERR "Couldn't create devinfo cache\n");
2843 ret = -ENOMEM;
2844 }
2845
2846 return ret;
2847}
2848
2849static inline int iommu_iova_cache_init(void)
2850{
2851 int ret = 0;
2852
2853 iommu_iova_cache = kmem_cache_create("iommu_iova",
2854 sizeof(struct iova),
2855 0,
2856 SLAB_HWCACHE_ALIGN,
ba395927
KA		 2857 NULL);
2858 if (!iommu_iova_cache) {
2859 printk(KERN_ERR "Couldn't create iova cache\n");
2860 ret = -ENOMEM;
2861 }
2862
2863 return ret;
2864}
2865
2866static int __init iommu_init_mempool(void)
2867{
2868 int ret;
2869 ret = iommu_iova_cache_init();
2870 if (ret)
2871 return ret;
2872
2873 ret = iommu_domain_cache_init();
2874 if (ret)
2875 goto domain_error;
2876
2877 ret = iommu_devinfo_cache_init();
2878 if (!ret)
2879 return ret;
2880
2881 kmem_cache_destroy(iommu_domain_cache);
2882domain_error:
2883 kmem_cache_destroy(iommu_iova_cache);
2884
2885 return -ENOMEM;
2886}
2887
2888static void __init iommu_exit_mempool(void)
2889{
2890 kmem_cache_destroy(iommu_devinfo_cache);
2891 kmem_cache_destroy(iommu_domain_cache);
2892 kmem_cache_destroy(iommu_iova_cache);
2893
2894}
2895
ba395927
KA		 2896static void __init init_no_remapping_devices(void)
2897{
2898 struct dmar_drhd_unit *drhd;
2899
2900 for_each_drhd_unit(drhd) {
2901 if (!drhd->include_all) {
2902 int i;
2903 for (i = 0; i < drhd->devices_cnt; i++)
2904 if (drhd->devices[i] != NULL)
2905 break;
2906 /* ignore DMAR unit if no pci devices exist */
2907 if (i == drhd->devices_cnt)
2908 drhd->ignored = 1;
2909 }
2910 }
2911
2912 if (dmar_map_gfx)
2913 return;
2914
2915 for_each_drhd_unit(drhd) {
2916 int i;
2917 if (drhd->ignored || drhd->include_all)
2918 continue;
2919
2920 for (i = 0; i < drhd->devices_cnt; i++)
2921 if (drhd->devices[i] &&
2922 !IS_GFX_DEVICE(drhd->devices[i]))
2923 break;
2924
2925 if (i < drhd->devices_cnt)
2926 continue;
2927
2928 /* bypass IOMMU if it is just for gfx devices */
2929 drhd->ignored = 1;
2930 for (i = 0; i < drhd->devices_cnt; i++) {
2931 if (!drhd->devices[i])
2932 continue;
358dd8ac 2933 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 2934 }
2935 }
2936}
2937
f59c7b69
FY		 2938#ifdef CONFIG_SUSPEND
2939static int init_iommu_hw(void)
2940{
2941 struct dmar_drhd_unit *drhd;
2942 struct intel_iommu *iommu = NULL;
2943
2944 for_each_active_iommu(iommu, drhd)
2945 if (iommu->qi)
2946 dmar_reenable_qi(iommu);
2947
2948 for_each_active_iommu(iommu, drhd) {
2949 iommu_flush_write_buffer(iommu);
2950
2951 iommu_set_root_entry(iommu);
2952
2953 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 2954 DMA_CCMD_GLOBAL_INVL);
f59c7b69 2955 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 2956 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 2957 iommu_disable_protect_mem_regions(iommu);
2958 iommu_enable_translation(iommu);
2959 }
2960
2961 return 0;
2962}
2963
2964static void iommu_flush_all(void)
2965{
2966 struct dmar_drhd_unit *drhd;
2967 struct intel_iommu *iommu;
2968
2969 for_each_active_iommu(iommu, drhd) {
2970 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 2971 DMA_CCMD_GLOBAL_INVL);
f59c7b69 2972 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 2973 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 2974 }
2975}
2976
2977static int iommu_suspend(struct sys_device *dev, pm_message_t state)
2978{
2979 struct dmar_drhd_unit *drhd;
2980 struct intel_iommu *iommu = NULL;
2981 unsigned long flag;
2982
2983 for_each_active_iommu(iommu, drhd) {
2984 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
2985 GFP_ATOMIC);
2986 if (!iommu->iommu_state)
2987 goto nomem;
2988 }
2989
2990 iommu_flush_all();
2991
2992 for_each_active_iommu(iommu, drhd) {
2993 iommu_disable_translation(iommu);
2994
2995 spin_lock_irqsave(&iommu->register_lock, flag);
2996
2997 iommu->iommu_state[SR_DMAR_FECTL_REG] =
2998 readl(iommu->reg + DMAR_FECTL_REG);
2999 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3000 readl(iommu->reg + DMAR_FEDATA_REG);
3001 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3002 readl(iommu->reg + DMAR_FEADDR_REG);
3003 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3004 readl(iommu->reg + DMAR_FEUADDR_REG);
3005
3006 spin_unlock_irqrestore(&iommu->register_lock, flag);
3007 }
3008 return 0;
3009
3010nomem:
3011 for_each_active_iommu(iommu, drhd)
3012 kfree(iommu->iommu_state);
3013
3014 return -ENOMEM;
3015}
3016
3017static int iommu_resume(struct sys_device *dev)
3018{
3019 struct dmar_drhd_unit *drhd;
3020 struct intel_iommu *iommu = NULL;
3021 unsigned long flag;
3022
3023 if (init_iommu_hw()) {
3024 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3025 return -EIO;
3026 }
3027
3028 for_each_active_iommu(iommu, drhd) {
3029
3030 spin_lock_irqsave(&iommu->register_lock, flag);
3031
3032 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3033 iommu->reg + DMAR_FECTL_REG);
3034 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3035 iommu->reg + DMAR_FEDATA_REG);
3036 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3037 iommu->reg + DMAR_FEADDR_REG);
3038 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3039 iommu->reg + DMAR_FEUADDR_REG);
3040
3041 spin_unlock_irqrestore(&iommu->register_lock, flag);
3042 }
3043
3044 for_each_active_iommu(iommu, drhd)
3045 kfree(iommu->iommu_state);
3046
3047 return 0;
3048}
3049
3050static struct sysdev_class iommu_sysclass = {
3051 .name = "iommu",
3052 .resume = iommu_resume,
3053 .suspend = iommu_suspend,
3054};
3055
3056static struct sys_device device_iommu = {
3057 .cls = &iommu_sysclass,
3058};
3059
3060static int __init init_iommu_sysfs(void)
3061{
3062 int error;
3063
3064 error = sysdev_class_register(&iommu_sysclass);
3065 if (error)
3066 return error;
3067
3068 error = sysdev_register(&device_iommu);
3069 if (error)
3070 sysdev_class_unregister(&iommu_sysclass);
3071
3072 return error;
3073}
3074
3075#else
3076static int __init init_iommu_sysfs(void)
3077{
3078 return 0;
3079}
3080#endif /* CONFIG_PM */
3081
ba395927
KA		 3082int __init intel_iommu_init(void)
3083{
3084 int ret = 0;
3085
ba395927
KA		 3086 if (dmar_table_init())
3087 return -ENODEV;
3088
1886e8a9
SS		 3089 if (dmar_dev_scope_init())
3090 return -ENODEV;
3091
2ae21010
SS		 3092 /*
3093 * Check the need for DMA-remapping initialization now.
3094 * Above initialization will also be used by Interrupt-remapping.
3095 */
4ed0d3e6 3096 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
2ae21010
SS		 3097 return -ENODEV;
3098
ba395927
KA		 3099 iommu_init_mempool();
3100 dmar_init_reserved_ranges();
3101
3102 init_no_remapping_devices();
3103
3104 ret = init_dmars();
3105 if (ret) {
3106 printk(KERN_ERR "IOMMU: dmar init failed\n");
3107 put_iova_domain(&reserved_iova_list);
3108 iommu_exit_mempool();
3109 return ret;
3110 }
3111 printk(KERN_INFO
3112 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3113
5e0d2a6f 3114 init_timer(&unmap_timer);
ba395927 3115 force_iommu = 1;
4ed0d3e6
FY		 3116
3117 if (!iommu_pass_through) {
3118 printk(KERN_INFO
3119 "Multi-level page-table translation for DMAR.\n");
3120 dma_ops = &intel_dma_ops;
3121 } else
3122 printk(KERN_INFO
3123 "DMAR: Pass through translation for DMAR.\n");
3124
f59c7b69 3125 init_iommu_sysfs();
a8bcbb0d
JR		 3126
3127 register_iommu(&intel_iommu_ops);
3128
ba395927
KA		 3129 return 0;
3130}
e820482c 3131
3199aa6b
HW		 3132static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3133 struct pci_dev *pdev)
3134{
3135 struct pci_dev *tmp, *parent;
3136
3137 if (!iommu || !pdev)
3138 return;
3139
3140 /* dependent device detach */
3141 tmp = pci_find_upstream_pcie_bridge(pdev);
3142 /* Secondary interface's bus number and devfn 0 */
3143 if (tmp) {
3144 parent = pdev->bus->self;
3145 while (parent != tmp) {
3146 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3147 parent->devfn);
3199aa6b
HW		 3148 parent = parent->bus->self;
3149 }
3150 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3151 iommu_detach_dev(iommu,
3152 tmp->subordinate->number, 0);
3153 else /* this is a legacy PCI bridge */
276dbf99
DW		 3154 iommu_detach_dev(iommu, tmp->bus->number,
3155 tmp->devfn);
3199aa6b
HW		 3156 }
3157}
3158
2c2e2c38 3159static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3160 struct pci_dev *pdev)
3161{
3162 struct device_domain_info *info;
3163 struct intel_iommu *iommu;
3164 unsigned long flags;
3165 int found = 0;
3166 struct list_head *entry, *tmp;
3167
276dbf99
DW		 3168 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3169 pdev->devfn);
c7151a8d
WH		 3170 if (!iommu)
3171 return;
3172
3173 spin_lock_irqsave(&device_domain_lock, flags);
3174 list_for_each_safe(entry, tmp, &domain->devices) {
3175 info = list_entry(entry, struct device_domain_info, link);
276dbf99 3176 /* No need to compare PCI domain; it has to be the same */
c7151a8d
WH		 3177 if (info->bus == pdev->bus->number &&
3178 info->devfn == pdev->devfn) {
3179 list_del(&info->link);
3180 list_del(&info->global);
3181 if (info->dev)
3182 info->dev->dev.archdata.iommu = NULL;
3183 spin_unlock_irqrestore(&device_domain_lock, flags);
3184
93a23a72 3185 iommu_disable_dev_iotlb(info);
c7151a8d 3186 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3187 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3188 free_devinfo_mem(info);
3189
3190 spin_lock_irqsave(&device_domain_lock, flags);
3191
3192 if (found)
3193 break;
3194 else
3195 continue;
3196 }
3197
3198 /* if there is no other devices under the same iommu
3199 * owned by this domain, clear this iommu in iommu_bmp
3200 * update iommu count and coherency
3201 */
276dbf99
DW		 3202 if (iommu == device_to_iommu(info->segment, info->bus,
3203 info->devfn))
c7151a8d
WH		 3204 found = 1;
3205 }
3206
3207 if (found == 0) {
3208 unsigned long tmp_flags;
3209 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3210 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3211 domain->iommu_count--;
58c610bd 3212 domain_update_iommu_cap(domain);
c7151a8d
WH		 3213 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3214 }
3215
3216 spin_unlock_irqrestore(&device_domain_lock, flags);
3217}
3218
3219static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3220{
3221 struct device_domain_info *info;
3222 struct intel_iommu *iommu;
3223 unsigned long flags1, flags2;
3224
3225 spin_lock_irqsave(&device_domain_lock, flags1);
3226 while (!list_empty(&domain->devices)) {
3227 info = list_entry(domain->devices.next,
3228 struct device_domain_info, link);
3229 list_del(&info->link);
3230 list_del(&info->global);
3231 if (info->dev)
3232 info->dev->dev.archdata.iommu = NULL;
3233
3234 spin_unlock_irqrestore(&device_domain_lock, flags1);
3235
93a23a72 3236 iommu_disable_dev_iotlb(info);
276dbf99 3237 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3238 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3239 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3240
3241 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3242 * and capabilities
c7151a8d
WH		 3243 */
3244 spin_lock_irqsave(&domain->iommu_lock, flags2);
3245 if (test_and_clear_bit(iommu->seq_id,
3246 &domain->iommu_bmp)) {
3247 domain->iommu_count--;
58c610bd 3248 domain_update_iommu_cap(domain);
c7151a8d
WH		 3249 }
3250 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3251
3252 free_devinfo_mem(info);
3253 spin_lock_irqsave(&device_domain_lock, flags1);
3254 }
3255 spin_unlock_irqrestore(&device_domain_lock, flags1);
3256}
3257
5e98c4b1
WH		 3258/* domain id for virtual machine, it won't be set in context */
3259static unsigned long vm_domid;
3260
fe40f1e0
WH		 3261static int vm_domain_min_agaw(struct dmar_domain *domain)
3262{
3263 int i;
3264 int min_agaw = domain->agaw;
3265
3266 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3267 for (; i < g_num_of_iommus; ) {
3268 if (min_agaw > g_iommus[i]->agaw)
3269 min_agaw = g_iommus[i]->agaw;
3270
3271 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3272 }
3273
3274 return min_agaw;
3275}
3276
5e98c4b1
WH		 3277static struct dmar_domain *iommu_alloc_vm_domain(void)
3278{
3279 struct dmar_domain *domain;
3280
3281 domain = alloc_domain_mem();
3282 if (!domain)
3283 return NULL;
3284
3285 domain->id = vm_domid++;
3286 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3287 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3288
3289 return domain;
3290}
3291
2c2e2c38 3292static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3293{
3294 int adjust_width;
3295
3296 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3297 spin_lock_init(&domain->mapping_lock);
3298 spin_lock_init(&domain->iommu_lock);
3299
3300 domain_reserve_special_ranges(domain);
3301
3302 /* calculate AGAW */
3303 domain->gaw = guest_width;
3304 adjust_width = guestwidth_to_adjustwidth(guest_width);
3305 domain->agaw = width_to_agaw(adjust_width);
3306
3307 INIT_LIST_HEAD(&domain->devices);
3308
3309 domain->iommu_count = 0;
3310 domain->iommu_coherency = 0;
fe40f1e0 3311 domain->max_addr = 0;
5e98c4b1
WH		 3312
3313 /* always allocate the top pgd */
3314 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3315 if (!domain->pgd)
3316 return -ENOMEM;
3317 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3318 return 0;
3319}
3320
3321static void iommu_free_vm_domain(struct dmar_domain *domain)
3322{
3323 unsigned long flags;
3324 struct dmar_drhd_unit *drhd;
3325 struct intel_iommu *iommu;
3326 unsigned long i;
3327 unsigned long ndomains;
3328
3329 for_each_drhd_unit(drhd) {
3330 if (drhd->ignored)
3331 continue;
3332 iommu = drhd->iommu;
3333
3334 ndomains = cap_ndoms(iommu->cap);
3335 i = find_first_bit(iommu->domain_ids, ndomains);
3336 for (; i < ndomains; ) {
3337 if (iommu->domains[i] == domain) {
3338 spin_lock_irqsave(&iommu->lock, flags);
3339 clear_bit(i, iommu->domain_ids);
3340 iommu->domains[i] = NULL;
3341 spin_unlock_irqrestore(&iommu->lock, flags);
3342 break;
3343 }
3344 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3345 }
3346 }
3347}
3348
3349static void vm_domain_exit(struct dmar_domain *domain)
3350{
5e98c4b1
WH		 3351 /* Domain 0 is reserved, so dont process it */
3352 if (!domain)
3353 return;
3354
3355 vm_domain_remove_all_dev_info(domain);
3356 /* destroy iovas */
3357 put_iova_domain(&domain->iovad);
5e98c4b1
WH		 3358
3359 /* clear ptes */
595badf5 3360 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3361
3362 /* free page tables */
d794dc9b 3363 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3364
3365 iommu_free_vm_domain(domain);
3366 free_domain_mem(domain);
3367}
3368
5d450806 3369static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3370{
5d450806 3371 struct dmar_domain *dmar_domain;
38717946 3372
5d450806
JR		 3373 dmar_domain = iommu_alloc_vm_domain();
3374 if (!dmar_domain) {
38717946 3375 printk(KERN_ERR
5d450806
JR		 3376 "intel_iommu_domain_init: dmar_domain == NULL\n");
3377 return -ENOMEM;
38717946 3378 }
2c2e2c38 3379 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3380 printk(KERN_ERR
5d450806
JR		 3381 "intel_iommu_domain_init() failed\n");
3382 vm_domain_exit(dmar_domain);
3383 return -ENOMEM;
38717946 3384 }
5d450806 3385 domain->priv = dmar_domain;
faa3d6f5 3386
5d450806 3387 return 0;
38717946 3388}
38717946 3389
5d450806 3390static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3391{
5d450806
JR		 3392 struct dmar_domain *dmar_domain = domain->priv;
3393
3394 domain->priv = NULL;
3395 vm_domain_exit(dmar_domain);
38717946 3396}
38717946 3397
4c5478c9
JR		 3398static int intel_iommu_attach_device(struct iommu_domain *domain,
3399 struct device *dev)
38717946 3400{
4c5478c9
JR		 3401 struct dmar_domain *dmar_domain = domain->priv;
3402 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3403 struct intel_iommu *iommu;
3404 int addr_width;
3405 u64 end;
faa3d6f5
WH		 3406 int ret;
3407
3408 /* normally pdev is not mapped */
3409 if (unlikely(domain_context_mapped(pdev))) {
3410 struct dmar_domain *old_domain;
3411
3412 old_domain = find_domain(pdev);
3413 if (old_domain) {
2c2e2c38
FY		 3414 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3415 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3416 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 3417 else
3418 domain_remove_dev_info(old_domain);
3419 }
3420 }
3421
276dbf99
DW		 3422 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3423 pdev->devfn);
fe40f1e0
WH		 3424 if (!iommu)
3425 return -ENODEV;
3426
3427 /* check if this iommu agaw is sufficient for max mapped address */
3428 addr_width = agaw_to_width(iommu->agaw);
3429 end = DOMAIN_MAX_ADDR(addr_width);
3430 end = end & VTD_PAGE_MASK;
4c5478c9 3431 if (end < dmar_domain->max_addr) {
fe40f1e0
WH		 3432 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3433 "sufficient for the mapped address (%llx)\n",
4c5478c9 3434 __func__, iommu->agaw, dmar_domain->max_addr);
fe40f1e0
WH		 3435 return -EFAULT;
3436 }
3437
2c2e2c38 3438 ret = domain_add_dev_info(dmar_domain, pdev);
faa3d6f5
WH		 3439 if (ret)
3440 return ret;
3441
93a23a72 3442 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
faa3d6f5 3443 return ret;
38717946 3444}
38717946 3445
4c5478c9
JR		 3446static void intel_iommu_detach_device(struct iommu_domain *domain,
3447 struct device *dev)
38717946 3448{
4c5478c9
JR		 3449 struct dmar_domain *dmar_domain = domain->priv;
3450 struct pci_dev *pdev = to_pci_dev(dev);
3451
2c2e2c38 3452 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 3453}
c7151a8d 3454
dde57a21
JR		 3455static int intel_iommu_map_range(struct iommu_domain *domain,
3456 unsigned long iova, phys_addr_t hpa,
3457 size_t size, int iommu_prot)
faa3d6f5 3458{
dde57a21 3459 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0
WH		 3460 u64 max_addr;
3461 int addr_width;
dde57a21 3462 int prot = 0;
faa3d6f5 3463 int ret;
fe40f1e0 3464
dde57a21
JR		 3465 if (iommu_prot & IOMMU_READ)
3466 prot |= DMA_PTE_READ;
3467 if (iommu_prot & IOMMU_WRITE)
3468 prot |= DMA_PTE_WRITE;
9cf06697
SY		 3469 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3470 prot |= DMA_PTE_SNP;
dde57a21 3471
163cc52c 3472 max_addr = iova + size;
dde57a21 3473 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 3474 int min_agaw;
3475 u64 end;
3476
3477 /* check if minimum agaw is sufficient for mapped address */
dde57a21 3478 min_agaw = vm_domain_min_agaw(dmar_domain);
fe40f1e0
WH		 3479 addr_width = agaw_to_width(min_agaw);
3480 end = DOMAIN_MAX_ADDR(addr_width);
3481 end = end & VTD_PAGE_MASK;
3482 if (end < max_addr) {
3483 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3484 "sufficient for the mapped address (%llx)\n",
3485 __func__, min_agaw, max_addr);
3486 return -EFAULT;
3487 }
dde57a21 3488 dmar_domain->max_addr = max_addr;
fe40f1e0 3489 }
ad051221
DW		 3490 /* Round up size to next multiple of PAGE_SIZE, if it and
3491 the low bits of hpa would take us onto the next page */
88cb6a74 3492 size = aligned_nrpages(hpa, size);
ad051221
DW		 3493 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3494 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 3495 return ret;
38717946 3496}
38717946 3497
dde57a21
JR		 3498static void intel_iommu_unmap_range(struct iommu_domain *domain,
3499 unsigned long iova, size_t size)
38717946 3500{
dde57a21 3501 struct dmar_domain *dmar_domain = domain->priv;
faa3d6f5 3502
163cc52c
DW		 3503 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3504 (iova + size - 1) >> VTD_PAGE_SHIFT);
fe40f1e0 3505
163cc52c
DW		 3506 if (dmar_domain->max_addr == iova + size)
3507 dmar_domain->max_addr = iova;
38717946 3508}
38717946 3509
d14d6577
JR		 3510static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3511 unsigned long iova)
38717946 3512{
d14d6577 3513 struct dmar_domain *dmar_domain = domain->priv;
38717946 3514 struct dma_pte *pte;
faa3d6f5 3515 u64 phys = 0;
38717946 3516
b026fd28 3517 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
38717946 3518 if (pte)
faa3d6f5 3519 phys = dma_pte_addr(pte);
38717946 3520
faa3d6f5 3521 return phys;
38717946 3522}
a8bcbb0d 3523
dbb9fd86
SY		 3524static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3525 unsigned long cap)
3526{
3527 struct dmar_domain *dmar_domain = domain->priv;
3528
3529 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3530 return dmar_domain->iommu_snooping;
3531
3532 return 0;
3533}
3534
a8bcbb0d
JR		 3535static struct iommu_ops intel_iommu_ops = {
3536 .domain_init = intel_iommu_domain_init,
3537 .domain_destroy = intel_iommu_domain_destroy,
3538 .attach_dev = intel_iommu_attach_device,
3539 .detach_dev = intel_iommu_detach_device,
3540 .map = intel_iommu_map_range,
3541 .unmap = intel_iommu_unmap_range,
3542 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 3543 .domain_has_cap = intel_iommu_domain_has_cap,
a8bcbb0d 3544};
9af88143
DW		 3545
3546static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3547{
3548 /*
3549 * Mobile 4 Series Chipset neglects to set RWBF capability,
3550 * but needs it:
3551 */
3552 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3553 rwbf_quirk = 1;
3554}
3555
3556DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
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