]>
Commit | Line | Data |
---|---|---|
ba395927 KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Shaohua Li <shaohua.li@intel.com> | |
20 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
5b6985ce | 21 | * Author: Fenghua Yu <fenghua.yu@intel.com> |
ba395927 KA |
22 | */ |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/bitmap.h> | |
5e0d2a6f | 26 | #include <linux/debugfs.h> |
ba395927 KA |
27 | #include <linux/slab.h> |
28 | #include <linux/irq.h> | |
29 | #include <linux/interrupt.h> | |
ba395927 KA |
30 | #include <linux/spinlock.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/dmar.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/mempool.h> | |
5e0d2a6f | 35 | #include <linux/timer.h> |
38717946 | 36 | #include <linux/iova.h> |
5d450806 | 37 | #include <linux/iommu.h> |
38717946 | 38 | #include <linux/intel-iommu.h> |
f59c7b69 | 39 | #include <linux/sysdev.h> |
ba395927 | 40 | #include <asm/cacheflush.h> |
46a7fa27 | 41 | #include <asm/iommu.h> |
ba395927 KA |
42 | #include "pci.h" |
43 | ||
5b6985ce FY |
44 | #define ROOT_SIZE VTD_PAGE_SIZE |
45 | #define CONTEXT_SIZE VTD_PAGE_SIZE | |
46 | ||
ba395927 KA |
47 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
48 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) | |
49 | ||
50 | #define IOAPIC_RANGE_START (0xfee00000) | |
51 | #define IOAPIC_RANGE_END (0xfeefffff) | |
52 | #define IOVA_START_ADDR (0x1000) | |
53 | ||
54 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
55 | ||
4ed0d3e6 FY |
56 | #define MAX_AGAW_WIDTH 64 |
57 | ||
ba395927 | 58 | #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1) |
595badf5 | 59 | #define DOMAIN_MAX_PFN(gaw) ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
ba395927 | 60 | |
f27be03b | 61 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
284901a9 | 62 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
6a35528a | 63 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
5e0d2a6f | 64 | |
fd18de50 DW |
65 | #ifndef PHYSICAL_PAGE_MASK |
66 | #define PHYSICAL_PAGE_MASK PAGE_MASK | |
67 | #endif | |
68 | ||
dd4e8319 DW |
69 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
70 | are never going to work. */ | |
71 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) | |
72 | { | |
73 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
74 | } | |
75 | ||
76 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) | |
77 | { | |
78 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
79 | } | |
80 | static inline unsigned long page_to_dma_pfn(struct page *pg) | |
81 | { | |
82 | return mm_to_dma_pfn(page_to_pfn(pg)); | |
83 | } | |
84 | static inline unsigned long virt_to_dma_pfn(void *p) | |
85 | { | |
86 | return page_to_dma_pfn(virt_to_page(p)); | |
87 | } | |
88 | ||
d9630fe9 WH |
89 | /* global iommu list, set NULL for ignored DMAR units */ |
90 | static struct intel_iommu **g_iommus; | |
91 | ||
9af88143 DW |
92 | static int rwbf_quirk; |
93 | ||
46b08e1a MM |
94 | /* |
95 | * 0: Present | |
96 | * 1-11: Reserved | |
97 | * 12-63: Context Ptr (12 - (haw-1)) | |
98 | * 64-127: Reserved | |
99 | */ | |
100 | struct root_entry { | |
101 | u64 val; | |
102 | u64 rsvd1; | |
103 | }; | |
104 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) | |
105 | static inline bool root_present(struct root_entry *root) | |
106 | { | |
107 | return (root->val & 1); | |
108 | } | |
109 | static inline void set_root_present(struct root_entry *root) | |
110 | { | |
111 | root->val |= 1; | |
112 | } | |
113 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
114 | { | |
115 | root->val |= value & VTD_PAGE_MASK; | |
116 | } | |
117 | ||
118 | static inline struct context_entry * | |
119 | get_context_addr_from_root(struct root_entry *root) | |
120 | { | |
121 | return (struct context_entry *) | |
122 | (root_present(root)?phys_to_virt( | |
123 | root->val & VTD_PAGE_MASK) : | |
124 | NULL); | |
125 | } | |
126 | ||
7a8fc25e MM |
127 | /* |
128 | * low 64 bits: | |
129 | * 0: present | |
130 | * 1: fault processing disable | |
131 | * 2-3: translation type | |
132 | * 12-63: address space root | |
133 | * high 64 bits: | |
134 | * 0-2: address width | |
135 | * 3-6: aval | |
136 | * 8-23: domain id | |
137 | */ | |
138 | struct context_entry { | |
139 | u64 lo; | |
140 | u64 hi; | |
141 | }; | |
c07e7d21 MM |
142 | |
143 | static inline bool context_present(struct context_entry *context) | |
144 | { | |
145 | return (context->lo & 1); | |
146 | } | |
147 | static inline void context_set_present(struct context_entry *context) | |
148 | { | |
149 | context->lo |= 1; | |
150 | } | |
151 | ||
152 | static inline void context_set_fault_enable(struct context_entry *context) | |
153 | { | |
154 | context->lo &= (((u64)-1) << 2) | 1; | |
155 | } | |
156 | ||
c07e7d21 MM |
157 | static inline void context_set_translation_type(struct context_entry *context, |
158 | unsigned long value) | |
159 | { | |
160 | context->lo &= (((u64)-1) << 4) | 3; | |
161 | context->lo |= (value & 3) << 2; | |
162 | } | |
163 | ||
164 | static inline void context_set_address_root(struct context_entry *context, | |
165 | unsigned long value) | |
166 | { | |
167 | context->lo |= value & VTD_PAGE_MASK; | |
168 | } | |
169 | ||
170 | static inline void context_set_address_width(struct context_entry *context, | |
171 | unsigned long value) | |
172 | { | |
173 | context->hi |= value & 7; | |
174 | } | |
175 | ||
176 | static inline void context_set_domain_id(struct context_entry *context, | |
177 | unsigned long value) | |
178 | { | |
179 | context->hi |= (value & ((1 << 16) - 1)) << 8; | |
180 | } | |
181 | ||
182 | static inline void context_clear_entry(struct context_entry *context) | |
183 | { | |
184 | context->lo = 0; | |
185 | context->hi = 0; | |
186 | } | |
7a8fc25e | 187 | |
622ba12a MM |
188 | /* |
189 | * 0: readable | |
190 | * 1: writable | |
191 | * 2-6: reserved | |
192 | * 7: super page | |
9cf06697 SY |
193 | * 8-10: available |
194 | * 11: snoop behavior | |
622ba12a MM |
195 | * 12-63: Host physcial address |
196 | */ | |
197 | struct dma_pte { | |
198 | u64 val; | |
199 | }; | |
622ba12a | 200 | |
19c239ce MM |
201 | static inline void dma_clear_pte(struct dma_pte *pte) |
202 | { | |
203 | pte->val = 0; | |
204 | } | |
205 | ||
206 | static inline void dma_set_pte_readable(struct dma_pte *pte) | |
207 | { | |
208 | pte->val |= DMA_PTE_READ; | |
209 | } | |
210 | ||
211 | static inline void dma_set_pte_writable(struct dma_pte *pte) | |
212 | { | |
213 | pte->val |= DMA_PTE_WRITE; | |
214 | } | |
215 | ||
9cf06697 SY |
216 | static inline void dma_set_pte_snp(struct dma_pte *pte) |
217 | { | |
218 | pte->val |= DMA_PTE_SNP; | |
219 | } | |
220 | ||
19c239ce MM |
221 | static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot) |
222 | { | |
223 | pte->val = (pte->val & ~3) | (prot & 3); | |
224 | } | |
225 | ||
226 | static inline u64 dma_pte_addr(struct dma_pte *pte) | |
227 | { | |
228 | return (pte->val & VTD_PAGE_MASK); | |
229 | } | |
230 | ||
dd4e8319 | 231 | static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn) |
19c239ce | 232 | { |
dd4e8319 | 233 | pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT; |
19c239ce MM |
234 | } |
235 | ||
236 | static inline bool dma_pte_present(struct dma_pte *pte) | |
237 | { | |
238 | return (pte->val & 3) != 0; | |
239 | } | |
622ba12a | 240 | |
2c2e2c38 FY |
241 | /* |
242 | * This domain is a statically identity mapping domain. | |
243 | * 1. This domain creats a static 1:1 mapping to all usable memory. | |
244 | * 2. It maps to each iommu if successful. | |
245 | * 3. Each iommu mapps to this domain if successful. | |
246 | */ | |
247 | struct dmar_domain *si_domain; | |
248 | ||
3b5410e7 | 249 | /* devices under the same p2p bridge are owned in one domain */ |
cdc7b837 | 250 | #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0) |
3b5410e7 | 251 | |
1ce28feb WH |
252 | /* domain represents a virtual machine, more than one devices |
253 | * across iommus may be owned in one domain, e.g. kvm guest. | |
254 | */ | |
255 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1) | |
256 | ||
2c2e2c38 FY |
257 | /* si_domain contains mulitple devices */ |
258 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2) | |
259 | ||
99126f7c MM |
260 | struct dmar_domain { |
261 | int id; /* domain id */ | |
8c11e798 | 262 | unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/ |
99126f7c MM |
263 | |
264 | struct list_head devices; /* all devices' list */ | |
265 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
266 | ||
267 | struct dma_pte *pgd; /* virtual address */ | |
268 | spinlock_t mapping_lock; /* page table lock */ | |
269 | int gaw; /* max guest address width */ | |
270 | ||
271 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
272 | int agaw; | |
273 | ||
3b5410e7 | 274 | int flags; /* flags to find out type of domain */ |
8e604097 WH |
275 | |
276 | int iommu_coherency;/* indicate coherency of iommu access */ | |
58c610bd | 277 | int iommu_snooping; /* indicate snooping control feature*/ |
c7151a8d WH |
278 | int iommu_count; /* reference count of iommu */ |
279 | spinlock_t iommu_lock; /* protect iommu set in domain */ | |
fe40f1e0 | 280 | u64 max_addr; /* maximum mapped address */ |
99126f7c MM |
281 | }; |
282 | ||
a647dacb MM |
283 | /* PCI domain-device relationship */ |
284 | struct device_domain_info { | |
285 | struct list_head link; /* link to domain siblings */ | |
286 | struct list_head global; /* link to global list */ | |
276dbf99 DW |
287 | int segment; /* PCI domain */ |
288 | u8 bus; /* PCI bus number */ | |
a647dacb MM |
289 | u8 devfn; /* PCI devfn number */ |
290 | struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */ | |
93a23a72 | 291 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
a647dacb MM |
292 | struct dmar_domain *domain; /* pointer to domain */ |
293 | }; | |
294 | ||
5e0d2a6f | 295 | static void flush_unmaps_timeout(unsigned long data); |
296 | ||
297 | DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); | |
298 | ||
80b20dd8 | 299 | #define HIGH_WATER_MARK 250 |
300 | struct deferred_flush_tables { | |
301 | int next; | |
302 | struct iova *iova[HIGH_WATER_MARK]; | |
303 | struct dmar_domain *domain[HIGH_WATER_MARK]; | |
304 | }; | |
305 | ||
306 | static struct deferred_flush_tables *deferred_flush; | |
307 | ||
5e0d2a6f | 308 | /* bitmap for indexing intel_iommus */ |
5e0d2a6f | 309 | static int g_num_of_iommus; |
310 | ||
311 | static DEFINE_SPINLOCK(async_umap_flush_lock); | |
312 | static LIST_HEAD(unmaps_to_do); | |
313 | ||
314 | static int timer_on; | |
315 | static long list_size; | |
5e0d2a6f | 316 | |
ba395927 KA |
317 | static void domain_remove_dev_info(struct dmar_domain *domain); |
318 | ||
0cd5c3c8 KM |
319 | #ifdef CONFIG_DMAR_DEFAULT_ON |
320 | int dmar_disabled = 0; | |
321 | #else | |
322 | int dmar_disabled = 1; | |
323 | #endif /*CONFIG_DMAR_DEFAULT_ON*/ | |
324 | ||
ba395927 | 325 | static int __initdata dmar_map_gfx = 1; |
7d3b03ce | 326 | static int dmar_forcedac; |
5e0d2a6f | 327 | static int intel_iommu_strict; |
ba395927 KA |
328 | |
329 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) | |
330 | static DEFINE_SPINLOCK(device_domain_lock); | |
331 | static LIST_HEAD(device_domain_list); | |
332 | ||
a8bcbb0d JR |
333 | static struct iommu_ops intel_iommu_ops; |
334 | ||
ba395927 KA |
335 | static int __init intel_iommu_setup(char *str) |
336 | { | |
337 | if (!str) | |
338 | return -EINVAL; | |
339 | while (*str) { | |
0cd5c3c8 KM |
340 | if (!strncmp(str, "on", 2)) { |
341 | dmar_disabled = 0; | |
342 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); | |
343 | } else if (!strncmp(str, "off", 3)) { | |
ba395927 | 344 | dmar_disabled = 1; |
0cd5c3c8 | 345 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
ba395927 KA |
346 | } else if (!strncmp(str, "igfx_off", 8)) { |
347 | dmar_map_gfx = 0; | |
348 | printk(KERN_INFO | |
349 | "Intel-IOMMU: disable GFX device mapping\n"); | |
7d3b03ce | 350 | } else if (!strncmp(str, "forcedac", 8)) { |
5e0d2a6f | 351 | printk(KERN_INFO |
7d3b03ce KA |
352 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
353 | dmar_forcedac = 1; | |
5e0d2a6f | 354 | } else if (!strncmp(str, "strict", 6)) { |
355 | printk(KERN_INFO | |
356 | "Intel-IOMMU: disable batched IOTLB flush\n"); | |
357 | intel_iommu_strict = 1; | |
ba395927 KA |
358 | } |
359 | ||
360 | str += strcspn(str, ","); | |
361 | while (*str == ',') | |
362 | str++; | |
363 | } | |
364 | return 0; | |
365 | } | |
366 | __setup("intel_iommu=", intel_iommu_setup); | |
367 | ||
368 | static struct kmem_cache *iommu_domain_cache; | |
369 | static struct kmem_cache *iommu_devinfo_cache; | |
370 | static struct kmem_cache *iommu_iova_cache; | |
371 | ||
eb3fa7cb KA |
372 | static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep) |
373 | { | |
374 | unsigned int flags; | |
375 | void *vaddr; | |
376 | ||
377 | /* trying to avoid low memory issues */ | |
378 | flags = current->flags & PF_MEMALLOC; | |
379 | current->flags |= PF_MEMALLOC; | |
380 | vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC); | |
381 | current->flags &= (~PF_MEMALLOC | flags); | |
382 | return vaddr; | |
383 | } | |
384 | ||
385 | ||
ba395927 KA |
386 | static inline void *alloc_pgtable_page(void) |
387 | { | |
eb3fa7cb KA |
388 | unsigned int flags; |
389 | void *vaddr; | |
390 | ||
391 | /* trying to avoid low memory issues */ | |
392 | flags = current->flags & PF_MEMALLOC; | |
393 | current->flags |= PF_MEMALLOC; | |
394 | vaddr = (void *)get_zeroed_page(GFP_ATOMIC); | |
395 | current->flags &= (~PF_MEMALLOC | flags); | |
396 | return vaddr; | |
ba395927 KA |
397 | } |
398 | ||
399 | static inline void free_pgtable_page(void *vaddr) | |
400 | { | |
401 | free_page((unsigned long)vaddr); | |
402 | } | |
403 | ||
404 | static inline void *alloc_domain_mem(void) | |
405 | { | |
eb3fa7cb | 406 | return iommu_kmem_cache_alloc(iommu_domain_cache); |
ba395927 KA |
407 | } |
408 | ||
38717946 | 409 | static void free_domain_mem(void *vaddr) |
ba395927 KA |
410 | { |
411 | kmem_cache_free(iommu_domain_cache, vaddr); | |
412 | } | |
413 | ||
414 | static inline void * alloc_devinfo_mem(void) | |
415 | { | |
eb3fa7cb | 416 | return iommu_kmem_cache_alloc(iommu_devinfo_cache); |
ba395927 KA |
417 | } |
418 | ||
419 | static inline void free_devinfo_mem(void *vaddr) | |
420 | { | |
421 | kmem_cache_free(iommu_devinfo_cache, vaddr); | |
422 | } | |
423 | ||
424 | struct iova *alloc_iova_mem(void) | |
425 | { | |
eb3fa7cb | 426 | return iommu_kmem_cache_alloc(iommu_iova_cache); |
ba395927 KA |
427 | } |
428 | ||
429 | void free_iova_mem(struct iova *iova) | |
430 | { | |
431 | kmem_cache_free(iommu_iova_cache, iova); | |
432 | } | |
433 | ||
1b573683 WH |
434 | |
435 | static inline int width_to_agaw(int width); | |
436 | ||
4ed0d3e6 | 437 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
1b573683 WH |
438 | { |
439 | unsigned long sagaw; | |
440 | int agaw = -1; | |
441 | ||
442 | sagaw = cap_sagaw(iommu->cap); | |
4ed0d3e6 | 443 | for (agaw = width_to_agaw(max_gaw); |
1b573683 WH |
444 | agaw >= 0; agaw--) { |
445 | if (test_bit(agaw, &sagaw)) | |
446 | break; | |
447 | } | |
448 | ||
449 | return agaw; | |
450 | } | |
451 | ||
4ed0d3e6 FY |
452 | /* |
453 | * Calculate max SAGAW for each iommu. | |
454 | */ | |
455 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
456 | { | |
457 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); | |
458 | } | |
459 | ||
460 | /* | |
461 | * calculate agaw for each iommu. | |
462 | * "SAGAW" may be different across iommus, use a default agaw, and | |
463 | * get a supported less agaw for iommus that don't support the default agaw. | |
464 | */ | |
465 | int iommu_calculate_agaw(struct intel_iommu *iommu) | |
466 | { | |
467 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
468 | } | |
469 | ||
2c2e2c38 | 470 | /* This functionin only returns single iommu in a domain */ |
8c11e798 WH |
471 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
472 | { | |
473 | int iommu_id; | |
474 | ||
2c2e2c38 | 475 | /* si_domain and vm domain should not get here. */ |
1ce28feb | 476 | BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE); |
2c2e2c38 | 477 | BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY); |
1ce28feb | 478 | |
8c11e798 WH |
479 | iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); |
480 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) | |
481 | return NULL; | |
482 | ||
483 | return g_iommus[iommu_id]; | |
484 | } | |
485 | ||
8e604097 WH |
486 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
487 | { | |
488 | int i; | |
489 | ||
490 | domain->iommu_coherency = 1; | |
491 | ||
492 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
493 | for (; i < g_num_of_iommus; ) { | |
494 | if (!ecap_coherent(g_iommus[i]->ecap)) { | |
495 | domain->iommu_coherency = 0; | |
496 | break; | |
497 | } | |
498 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
499 | } | |
500 | } | |
501 | ||
58c610bd SY |
502 | static void domain_update_iommu_snooping(struct dmar_domain *domain) |
503 | { | |
504 | int i; | |
505 | ||
506 | domain->iommu_snooping = 1; | |
507 | ||
508 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
509 | for (; i < g_num_of_iommus; ) { | |
510 | if (!ecap_sc_support(g_iommus[i]->ecap)) { | |
511 | domain->iommu_snooping = 0; | |
512 | break; | |
513 | } | |
514 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
515 | } | |
516 | } | |
517 | ||
518 | /* Some capabilities may be different across iommus */ | |
519 | static void domain_update_iommu_cap(struct dmar_domain *domain) | |
520 | { | |
521 | domain_update_iommu_coherency(domain); | |
522 | domain_update_iommu_snooping(domain); | |
523 | } | |
524 | ||
276dbf99 | 525 | static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn) |
c7151a8d WH |
526 | { |
527 | struct dmar_drhd_unit *drhd = NULL; | |
528 | int i; | |
529 | ||
530 | for_each_drhd_unit(drhd) { | |
531 | if (drhd->ignored) | |
532 | continue; | |
276dbf99 DW |
533 | if (segment != drhd->segment) |
534 | continue; | |
c7151a8d | 535 | |
924b6231 | 536 | for (i = 0; i < drhd->devices_cnt; i++) { |
288e4877 DH |
537 | if (drhd->devices[i] && |
538 | drhd->devices[i]->bus->number == bus && | |
c7151a8d WH |
539 | drhd->devices[i]->devfn == devfn) |
540 | return drhd->iommu; | |
4958c5dc DW |
541 | if (drhd->devices[i] && |
542 | drhd->devices[i]->subordinate && | |
924b6231 DW |
543 | drhd->devices[i]->subordinate->number <= bus && |
544 | drhd->devices[i]->subordinate->subordinate >= bus) | |
545 | return drhd->iommu; | |
546 | } | |
c7151a8d WH |
547 | |
548 | if (drhd->include_all) | |
549 | return drhd->iommu; | |
550 | } | |
551 | ||
552 | return NULL; | |
553 | } | |
554 | ||
5331fe6f WH |
555 | static void domain_flush_cache(struct dmar_domain *domain, |
556 | void *addr, int size) | |
557 | { | |
558 | if (!domain->iommu_coherency) | |
559 | clflush_cache_range(addr, size); | |
560 | } | |
561 | ||
ba395927 KA |
562 | /* Gets context entry for a given bus and devfn */ |
563 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, | |
564 | u8 bus, u8 devfn) | |
565 | { | |
566 | struct root_entry *root; | |
567 | struct context_entry *context; | |
568 | unsigned long phy_addr; | |
569 | unsigned long flags; | |
570 | ||
571 | spin_lock_irqsave(&iommu->lock, flags); | |
572 | root = &iommu->root_entry[bus]; | |
573 | context = get_context_addr_from_root(root); | |
574 | if (!context) { | |
575 | context = (struct context_entry *)alloc_pgtable_page(); | |
576 | if (!context) { | |
577 | spin_unlock_irqrestore(&iommu->lock, flags); | |
578 | return NULL; | |
579 | } | |
5b6985ce | 580 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
ba395927 KA |
581 | phy_addr = virt_to_phys((void *)context); |
582 | set_root_value(root, phy_addr); | |
583 | set_root_present(root); | |
584 | __iommu_flush_cache(iommu, root, sizeof(*root)); | |
585 | } | |
586 | spin_unlock_irqrestore(&iommu->lock, flags); | |
587 | return &context[devfn]; | |
588 | } | |
589 | ||
590 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
591 | { | |
592 | struct root_entry *root; | |
593 | struct context_entry *context; | |
594 | int ret; | |
595 | unsigned long flags; | |
596 | ||
597 | spin_lock_irqsave(&iommu->lock, flags); | |
598 | root = &iommu->root_entry[bus]; | |
599 | context = get_context_addr_from_root(root); | |
600 | if (!context) { | |
601 | ret = 0; | |
602 | goto out; | |
603 | } | |
c07e7d21 | 604 | ret = context_present(&context[devfn]); |
ba395927 KA |
605 | out: |
606 | spin_unlock_irqrestore(&iommu->lock, flags); | |
607 | return ret; | |
608 | } | |
609 | ||
610 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
611 | { | |
612 | struct root_entry *root; | |
613 | struct context_entry *context; | |
614 | unsigned long flags; | |
615 | ||
616 | spin_lock_irqsave(&iommu->lock, flags); | |
617 | root = &iommu->root_entry[bus]; | |
618 | context = get_context_addr_from_root(root); | |
619 | if (context) { | |
c07e7d21 | 620 | context_clear_entry(&context[devfn]); |
ba395927 KA |
621 | __iommu_flush_cache(iommu, &context[devfn], \ |
622 | sizeof(*context)); | |
623 | } | |
624 | spin_unlock_irqrestore(&iommu->lock, flags); | |
625 | } | |
626 | ||
627 | static void free_context_table(struct intel_iommu *iommu) | |
628 | { | |
629 | struct root_entry *root; | |
630 | int i; | |
631 | unsigned long flags; | |
632 | struct context_entry *context; | |
633 | ||
634 | spin_lock_irqsave(&iommu->lock, flags); | |
635 | if (!iommu->root_entry) { | |
636 | goto out; | |
637 | } | |
638 | for (i = 0; i < ROOT_ENTRY_NR; i++) { | |
639 | root = &iommu->root_entry[i]; | |
640 | context = get_context_addr_from_root(root); | |
641 | if (context) | |
642 | free_pgtable_page(context); | |
643 | } | |
644 | free_pgtable_page(iommu->root_entry); | |
645 | iommu->root_entry = NULL; | |
646 | out: | |
647 | spin_unlock_irqrestore(&iommu->lock, flags); | |
648 | } | |
649 | ||
650 | /* page table handling */ | |
651 | #define LEVEL_STRIDE (9) | |
652 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) | |
653 | ||
654 | static inline int agaw_to_level(int agaw) | |
655 | { | |
656 | return agaw + 2; | |
657 | } | |
658 | ||
659 | static inline int agaw_to_width(int agaw) | |
660 | { | |
661 | return 30 + agaw * LEVEL_STRIDE; | |
662 | ||
663 | } | |
664 | ||
665 | static inline int width_to_agaw(int width) | |
666 | { | |
667 | return (width - 30) / LEVEL_STRIDE; | |
668 | } | |
669 | ||
670 | static inline unsigned int level_to_offset_bits(int level) | |
671 | { | |
6660c63a | 672 | return (level - 1) * LEVEL_STRIDE; |
ba395927 KA |
673 | } |
674 | ||
77dfa56c | 675 | static inline int pfn_level_offset(unsigned long pfn, int level) |
ba395927 | 676 | { |
6660c63a | 677 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; |
ba395927 KA |
678 | } |
679 | ||
6660c63a | 680 | static inline unsigned long level_mask(int level) |
ba395927 | 681 | { |
6660c63a | 682 | return -1UL << level_to_offset_bits(level); |
ba395927 KA |
683 | } |
684 | ||
6660c63a | 685 | static inline unsigned long level_size(int level) |
ba395927 | 686 | { |
6660c63a | 687 | return 1UL << level_to_offset_bits(level); |
ba395927 KA |
688 | } |
689 | ||
6660c63a | 690 | static inline unsigned long align_to_level(unsigned long pfn, int level) |
ba395927 | 691 | { |
6660c63a | 692 | return (pfn + level_size(level) - 1) & level_mask(level); |
ba395927 KA |
693 | } |
694 | ||
695 | static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr) | |
696 | { | |
697 | int addr_width = agaw_to_width(domain->agaw); | |
698 | struct dma_pte *parent, *pte = NULL; | |
699 | int level = agaw_to_level(domain->agaw); | |
700 | int offset; | |
701 | unsigned long flags; | |
702 | ||
703 | BUG_ON(!domain->pgd); | |
66eae846 | 704 | BUG_ON(addr >> addr_width); |
ba395927 KA |
705 | parent = domain->pgd; |
706 | ||
707 | spin_lock_irqsave(&domain->mapping_lock, flags); | |
708 | while (level > 0) { | |
709 | void *tmp_page; | |
710 | ||
77dfa56c | 711 | offset = pfn_level_offset(addr >> VTD_PAGE_SHIFT, level); |
ba395927 KA |
712 | pte = &parent[offset]; |
713 | if (level == 1) | |
714 | break; | |
715 | ||
19c239ce | 716 | if (!dma_pte_present(pte)) { |
ba395927 KA |
717 | tmp_page = alloc_pgtable_page(); |
718 | ||
719 | if (!tmp_page) { | |
720 | spin_unlock_irqrestore(&domain->mapping_lock, | |
721 | flags); | |
722 | return NULL; | |
723 | } | |
5331fe6f | 724 | domain_flush_cache(domain, tmp_page, PAGE_SIZE); |
dd4e8319 | 725 | dma_set_pte_pfn(pte, virt_to_dma_pfn(tmp_page)); |
ba395927 KA |
726 | /* |
727 | * high level table always sets r/w, last level page | |
728 | * table control read/write | |
729 | */ | |
19c239ce MM |
730 | dma_set_pte_readable(pte); |
731 | dma_set_pte_writable(pte); | |
5331fe6f | 732 | domain_flush_cache(domain, pte, sizeof(*pte)); |
ba395927 | 733 | } |
19c239ce | 734 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
735 | level--; |
736 | } | |
737 | ||
738 | spin_unlock_irqrestore(&domain->mapping_lock, flags); | |
739 | return pte; | |
740 | } | |
741 | ||
742 | /* return address's pte at specific level */ | |
90dcfb5e DW |
743 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
744 | unsigned long pfn, | |
745 | int level) | |
ba395927 KA |
746 | { |
747 | struct dma_pte *parent, *pte = NULL; | |
748 | int total = agaw_to_level(domain->agaw); | |
749 | int offset; | |
750 | ||
751 | parent = domain->pgd; | |
752 | while (level <= total) { | |
90dcfb5e | 753 | offset = pfn_level_offset(pfn, total); |
ba395927 KA |
754 | pte = &parent[offset]; |
755 | if (level == total) | |
756 | return pte; | |
757 | ||
19c239ce | 758 | if (!dma_pte_present(pte)) |
ba395927 | 759 | break; |
19c239ce | 760 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
761 | total--; |
762 | } | |
763 | return NULL; | |
764 | } | |
765 | ||
766 | /* clear one page's page table */ | |
a75f7cf9 | 767 | static void dma_pte_clear_one(struct dmar_domain *domain, unsigned long pfn) |
ba395927 KA |
768 | { |
769 | struct dma_pte *pte = NULL; | |
770 | ||
771 | /* get last level pte */ | |
a75f7cf9 | 772 | pte = dma_pfn_level_pte(domain, pfn, 1); |
ba395927 KA |
773 | |
774 | if (pte) { | |
19c239ce | 775 | dma_clear_pte(pte); |
5331fe6f | 776 | domain_flush_cache(domain, pte, sizeof(*pte)); |
ba395927 KA |
777 | } |
778 | } | |
779 | ||
780 | /* clear last level pte, a tlb flush should be followed */ | |
595badf5 DW |
781 | static void dma_pte_clear_range(struct dmar_domain *domain, |
782 | unsigned long start_pfn, | |
783 | unsigned long last_pfn) | |
ba395927 | 784 | { |
04b18e65 | 785 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
66eae846 | 786 | |
04b18e65 | 787 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
595badf5 | 788 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
ba395927 | 789 | |
04b18e65 | 790 | /* we don't need lock here; nobody else touches the iova range */ |
595badf5 | 791 | while (start_pfn <= last_pfn) { |
04b18e65 DW |
792 | dma_pte_clear_one(domain, start_pfn); |
793 | start_pfn++; | |
ba395927 KA |
794 | } |
795 | } | |
796 | ||
797 | /* free page table pages. last level pte should already be cleared */ | |
798 | static void dma_pte_free_pagetable(struct dmar_domain *domain, | |
d794dc9b DW |
799 | unsigned long start_pfn, |
800 | unsigned long last_pfn) | |
ba395927 | 801 | { |
6660c63a | 802 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
ba395927 KA |
803 | struct dma_pte *pte; |
804 | int total = agaw_to_level(domain->agaw); | |
805 | int level; | |
6660c63a | 806 | unsigned long tmp; |
ba395927 | 807 | |
6660c63a DW |
808 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
809 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); | |
ba395927 KA |
810 | |
811 | /* we don't need lock here, nobody else touches the iova range */ | |
812 | level = 2; | |
813 | while (level <= total) { | |
6660c63a DW |
814 | tmp = align_to_level(start_pfn, level); |
815 | ||
816 | /* Only clear this pte/pmd if we're asked to clear its | |
817 | _whole_ range */ | |
818 | if (tmp + level_size(level) - 1 > last_pfn) | |
ba395927 KA |
819 | return; |
820 | ||
6660c63a DW |
821 | while (tmp <= last_pfn) { |
822 | pte = dma_pfn_level_pte(domain, tmp, level); | |
ba395927 KA |
823 | if (pte) { |
824 | free_pgtable_page( | |
19c239ce MM |
825 | phys_to_virt(dma_pte_addr(pte))); |
826 | dma_clear_pte(pte); | |
5331fe6f | 827 | domain_flush_cache(domain, pte, sizeof(*pte)); |
ba395927 KA |
828 | } |
829 | tmp += level_size(level); | |
830 | } | |
831 | level++; | |
832 | } | |
833 | /* free pgd */ | |
d794dc9b | 834 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
ba395927 KA |
835 | free_pgtable_page(domain->pgd); |
836 | domain->pgd = NULL; | |
837 | } | |
838 | } | |
839 | ||
840 | /* iommu handling */ | |
841 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |
842 | { | |
843 | struct root_entry *root; | |
844 | unsigned long flags; | |
845 | ||
846 | root = (struct root_entry *)alloc_pgtable_page(); | |
847 | if (!root) | |
848 | return -ENOMEM; | |
849 | ||
5b6985ce | 850 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
ba395927 KA |
851 | |
852 | spin_lock_irqsave(&iommu->lock, flags); | |
853 | iommu->root_entry = root; | |
854 | spin_unlock_irqrestore(&iommu->lock, flags); | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
ba395927 KA |
859 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
860 | { | |
861 | void *addr; | |
c416daa9 | 862 | u32 sts; |
ba395927 KA |
863 | unsigned long flag; |
864 | ||
865 | addr = iommu->root_entry; | |
866 | ||
867 | spin_lock_irqsave(&iommu->register_lock, flag); | |
868 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); | |
869 | ||
c416daa9 | 870 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
871 | |
872 | /* Make sure hardware complete it */ | |
873 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 874 | readl, (sts & DMA_GSTS_RTPS), sts); |
ba395927 KA |
875 | |
876 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
877 | } | |
878 | ||
879 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |
880 | { | |
881 | u32 val; | |
882 | unsigned long flag; | |
883 | ||
9af88143 | 884 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
ba395927 | 885 | return; |
ba395927 KA |
886 | |
887 | spin_lock_irqsave(&iommu->register_lock, flag); | |
462b60f6 | 888 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
889 | |
890 | /* Make sure hardware complete it */ | |
891 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 892 | readl, (!(val & DMA_GSTS_WBFS)), val); |
ba395927 KA |
893 | |
894 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
895 | } | |
896 | ||
897 | /* return value determine if we need a write buffer flush */ | |
4c25a2c1 DW |
898 | static void __iommu_flush_context(struct intel_iommu *iommu, |
899 | u16 did, u16 source_id, u8 function_mask, | |
900 | u64 type) | |
ba395927 KA |
901 | { |
902 | u64 val = 0; | |
903 | unsigned long flag; | |
904 | ||
ba395927 KA |
905 | switch (type) { |
906 | case DMA_CCMD_GLOBAL_INVL: | |
907 | val = DMA_CCMD_GLOBAL_INVL; | |
908 | break; | |
909 | case DMA_CCMD_DOMAIN_INVL: | |
910 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); | |
911 | break; | |
912 | case DMA_CCMD_DEVICE_INVL: | |
913 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) | |
914 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); | |
915 | break; | |
916 | default: | |
917 | BUG(); | |
918 | } | |
919 | val |= DMA_CCMD_ICC; | |
920 | ||
921 | spin_lock_irqsave(&iommu->register_lock, flag); | |
922 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); | |
923 | ||
924 | /* Make sure hardware complete it */ | |
925 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, | |
926 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); | |
927 | ||
928 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
ba395927 KA |
929 | } |
930 | ||
ba395927 | 931 | /* return value determine if we need a write buffer flush */ |
1f0ef2aa DW |
932 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
933 | u64 addr, unsigned int size_order, u64 type) | |
ba395927 KA |
934 | { |
935 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); | |
936 | u64 val = 0, val_iva = 0; | |
937 | unsigned long flag; | |
938 | ||
ba395927 KA |
939 | switch (type) { |
940 | case DMA_TLB_GLOBAL_FLUSH: | |
941 | /* global flush doesn't need set IVA_REG */ | |
942 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; | |
943 | break; | |
944 | case DMA_TLB_DSI_FLUSH: | |
945 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
946 | break; | |
947 | case DMA_TLB_PSI_FLUSH: | |
948 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
949 | /* Note: always flush non-leaf currently */ | |
950 | val_iva = size_order | addr; | |
951 | break; | |
952 | default: | |
953 | BUG(); | |
954 | } | |
955 | /* Note: set drain read/write */ | |
956 | #if 0 | |
957 | /* | |
958 | * This is probably to be super secure.. Looks like we can | |
959 | * ignore it without any impact. | |
960 | */ | |
961 | if (cap_read_drain(iommu->cap)) | |
962 | val |= DMA_TLB_READ_DRAIN; | |
963 | #endif | |
964 | if (cap_write_drain(iommu->cap)) | |
965 | val |= DMA_TLB_WRITE_DRAIN; | |
966 | ||
967 | spin_lock_irqsave(&iommu->register_lock, flag); | |
968 | /* Note: Only uses first TLB reg currently */ | |
969 | if (val_iva) | |
970 | dmar_writeq(iommu->reg + tlb_offset, val_iva); | |
971 | dmar_writeq(iommu->reg + tlb_offset + 8, val); | |
972 | ||
973 | /* Make sure hardware complete it */ | |
974 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, | |
975 | dmar_readq, (!(val & DMA_TLB_IVT)), val); | |
976 | ||
977 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
978 | ||
979 | /* check IOTLB invalidation granularity */ | |
980 | if (DMA_TLB_IAIG(val) == 0) | |
981 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); | |
982 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) | |
983 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", | |
5b6985ce FY |
984 | (unsigned long long)DMA_TLB_IIRG(type), |
985 | (unsigned long long)DMA_TLB_IAIG(val)); | |
ba395927 KA |
986 | } |
987 | ||
93a23a72 YZ |
988 | static struct device_domain_info *iommu_support_dev_iotlb( |
989 | struct dmar_domain *domain, int segment, u8 bus, u8 devfn) | |
990 | { | |
991 | int found = 0; | |
992 | unsigned long flags; | |
993 | struct device_domain_info *info; | |
994 | struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn); | |
995 | ||
996 | if (!ecap_dev_iotlb_support(iommu->ecap)) | |
997 | return NULL; | |
998 | ||
999 | if (!iommu->qi) | |
1000 | return NULL; | |
1001 | ||
1002 | spin_lock_irqsave(&device_domain_lock, flags); | |
1003 | list_for_each_entry(info, &domain->devices, link) | |
1004 | if (info->bus == bus && info->devfn == devfn) { | |
1005 | found = 1; | |
1006 | break; | |
1007 | } | |
1008 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1009 | ||
1010 | if (!found || !info->dev) | |
1011 | return NULL; | |
1012 | ||
1013 | if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS)) | |
1014 | return NULL; | |
1015 | ||
1016 | if (!dmar_find_matched_atsr_unit(info->dev)) | |
1017 | return NULL; | |
1018 | ||
1019 | info->iommu = iommu; | |
1020 | ||
1021 | return info; | |
1022 | } | |
1023 | ||
1024 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) | |
ba395927 | 1025 | { |
93a23a72 YZ |
1026 | if (!info) |
1027 | return; | |
1028 | ||
1029 | pci_enable_ats(info->dev, VTD_PAGE_SHIFT); | |
1030 | } | |
1031 | ||
1032 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) | |
1033 | { | |
1034 | if (!info->dev || !pci_ats_enabled(info->dev)) | |
1035 | return; | |
1036 | ||
1037 | pci_disable_ats(info->dev); | |
1038 | } | |
1039 | ||
1040 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, | |
1041 | u64 addr, unsigned mask) | |
1042 | { | |
1043 | u16 sid, qdep; | |
1044 | unsigned long flags; | |
1045 | struct device_domain_info *info; | |
1046 | ||
1047 | spin_lock_irqsave(&device_domain_lock, flags); | |
1048 | list_for_each_entry(info, &domain->devices, link) { | |
1049 | if (!info->dev || !pci_ats_enabled(info->dev)) | |
1050 | continue; | |
1051 | ||
1052 | sid = info->bus << 8 | info->devfn; | |
1053 | qdep = pci_ats_queue_depth(info->dev); | |
1054 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); | |
1055 | } | |
1056 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1057 | } | |
1058 | ||
1f0ef2aa DW |
1059 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
1060 | u64 addr, unsigned int pages) | |
ba395927 | 1061 | { |
9dd2fe89 | 1062 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
ba395927 | 1063 | |
5b6985ce | 1064 | BUG_ON(addr & (~VTD_PAGE_MASK)); |
ba395927 KA |
1065 | BUG_ON(pages == 0); |
1066 | ||
ba395927 | 1067 | /* |
9dd2fe89 YZ |
1068 | * Fallback to domain selective flush if no PSI support or the size is |
1069 | * too big. | |
ba395927 KA |
1070 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
1071 | * aligned to the size | |
1072 | */ | |
9dd2fe89 YZ |
1073 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
1074 | iommu->flush.flush_iotlb(iommu, did, 0, 0, | |
1f0ef2aa | 1075 | DMA_TLB_DSI_FLUSH); |
9dd2fe89 YZ |
1076 | else |
1077 | iommu->flush.flush_iotlb(iommu, did, addr, mask, | |
1078 | DMA_TLB_PSI_FLUSH); | |
bf92df30 YZ |
1079 | |
1080 | /* | |
1081 | * In caching mode, domain ID 0 is reserved for non-present to present | |
1082 | * mapping flush. Device IOTLB doesn't need to be flushed in this case. | |
1083 | */ | |
1084 | if (!cap_caching_mode(iommu->cap) || did) | |
93a23a72 | 1085 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
ba395927 KA |
1086 | } |
1087 | ||
f8bab735 | 1088 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
1089 | { | |
1090 | u32 pmen; | |
1091 | unsigned long flags; | |
1092 | ||
1093 | spin_lock_irqsave(&iommu->register_lock, flags); | |
1094 | pmen = readl(iommu->reg + DMAR_PMEN_REG); | |
1095 | pmen &= ~DMA_PMEN_EPM; | |
1096 | writel(pmen, iommu->reg + DMAR_PMEN_REG); | |
1097 | ||
1098 | /* wait for the protected region status bit to clear */ | |
1099 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, | |
1100 | readl, !(pmen & DMA_PMEN_PRS), pmen); | |
1101 | ||
1102 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
1103 | } | |
1104 | ||
ba395927 KA |
1105 | static int iommu_enable_translation(struct intel_iommu *iommu) |
1106 | { | |
1107 | u32 sts; | |
1108 | unsigned long flags; | |
1109 | ||
1110 | spin_lock_irqsave(&iommu->register_lock, flags); | |
c416daa9 DW |
1111 | iommu->gcmd |= DMA_GCMD_TE; |
1112 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
ba395927 KA |
1113 | |
1114 | /* Make sure hardware complete it */ | |
1115 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1116 | readl, (sts & DMA_GSTS_TES), sts); |
ba395927 | 1117 | |
ba395927 KA |
1118 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | static int iommu_disable_translation(struct intel_iommu *iommu) | |
1123 | { | |
1124 | u32 sts; | |
1125 | unsigned long flag; | |
1126 | ||
1127 | spin_lock_irqsave(&iommu->register_lock, flag); | |
1128 | iommu->gcmd &= ~DMA_GCMD_TE; | |
1129 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
1130 | ||
1131 | /* Make sure hardware complete it */ | |
1132 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1133 | readl, (!(sts & DMA_GSTS_TES)), sts); |
ba395927 KA |
1134 | |
1135 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
1136 | return 0; | |
1137 | } | |
1138 | ||
3460a6d9 | 1139 | |
ba395927 KA |
1140 | static int iommu_init_domains(struct intel_iommu *iommu) |
1141 | { | |
1142 | unsigned long ndomains; | |
1143 | unsigned long nlongs; | |
1144 | ||
1145 | ndomains = cap_ndoms(iommu->cap); | |
1146 | pr_debug("Number of Domains supportd <%ld>\n", ndomains); | |
1147 | nlongs = BITS_TO_LONGS(ndomains); | |
1148 | ||
1149 | /* TBD: there might be 64K domains, | |
1150 | * consider other allocation for future chip | |
1151 | */ | |
1152 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); | |
1153 | if (!iommu->domain_ids) { | |
1154 | printk(KERN_ERR "Allocating domain id array failed\n"); | |
1155 | return -ENOMEM; | |
1156 | } | |
1157 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), | |
1158 | GFP_KERNEL); | |
1159 | if (!iommu->domains) { | |
1160 | printk(KERN_ERR "Allocating domain array failed\n"); | |
1161 | kfree(iommu->domain_ids); | |
1162 | return -ENOMEM; | |
1163 | } | |
1164 | ||
e61d98d8 SS |
1165 | spin_lock_init(&iommu->lock); |
1166 | ||
ba395927 KA |
1167 | /* |
1168 | * if Caching mode is set, then invalid translations are tagged | |
1169 | * with domainid 0. Hence we need to pre-allocate it. | |
1170 | */ | |
1171 | if (cap_caching_mode(iommu->cap)) | |
1172 | set_bit(0, iommu->domain_ids); | |
1173 | return 0; | |
1174 | } | |
ba395927 | 1175 | |
ba395927 KA |
1176 | |
1177 | static void domain_exit(struct dmar_domain *domain); | |
5e98c4b1 | 1178 | static void vm_domain_exit(struct dmar_domain *domain); |
e61d98d8 SS |
1179 | |
1180 | void free_dmar_iommu(struct intel_iommu *iommu) | |
ba395927 KA |
1181 | { |
1182 | struct dmar_domain *domain; | |
1183 | int i; | |
c7151a8d | 1184 | unsigned long flags; |
ba395927 | 1185 | |
ba395927 KA |
1186 | i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap)); |
1187 | for (; i < cap_ndoms(iommu->cap); ) { | |
1188 | domain = iommu->domains[i]; | |
1189 | clear_bit(i, iommu->domain_ids); | |
c7151a8d WH |
1190 | |
1191 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
5e98c4b1 WH |
1192 | if (--domain->iommu_count == 0) { |
1193 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) | |
1194 | vm_domain_exit(domain); | |
1195 | else | |
1196 | domain_exit(domain); | |
1197 | } | |
c7151a8d WH |
1198 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
1199 | ||
ba395927 KA |
1200 | i = find_next_bit(iommu->domain_ids, |
1201 | cap_ndoms(iommu->cap), i+1); | |
1202 | } | |
1203 | ||
1204 | if (iommu->gcmd & DMA_GCMD_TE) | |
1205 | iommu_disable_translation(iommu); | |
1206 | ||
1207 | if (iommu->irq) { | |
1208 | set_irq_data(iommu->irq, NULL); | |
1209 | /* This will mask the irq */ | |
1210 | free_irq(iommu->irq, iommu); | |
1211 | destroy_irq(iommu->irq); | |
1212 | } | |
1213 | ||
1214 | kfree(iommu->domains); | |
1215 | kfree(iommu->domain_ids); | |
1216 | ||
d9630fe9 WH |
1217 | g_iommus[iommu->seq_id] = NULL; |
1218 | ||
1219 | /* if all iommus are freed, free g_iommus */ | |
1220 | for (i = 0; i < g_num_of_iommus; i++) { | |
1221 | if (g_iommus[i]) | |
1222 | break; | |
1223 | } | |
1224 | ||
1225 | if (i == g_num_of_iommus) | |
1226 | kfree(g_iommus); | |
1227 | ||
ba395927 KA |
1228 | /* free context mapping */ |
1229 | free_context_table(iommu); | |
ba395927 KA |
1230 | } |
1231 | ||
2c2e2c38 | 1232 | static struct dmar_domain *alloc_domain(void) |
ba395927 | 1233 | { |
ba395927 | 1234 | struct dmar_domain *domain; |
ba395927 KA |
1235 | |
1236 | domain = alloc_domain_mem(); | |
1237 | if (!domain) | |
1238 | return NULL; | |
1239 | ||
2c2e2c38 FY |
1240 | memset(&domain->iommu_bmp, 0, sizeof(unsigned long)); |
1241 | domain->flags = 0; | |
1242 | ||
1243 | return domain; | |
1244 | } | |
1245 | ||
1246 | static int iommu_attach_domain(struct dmar_domain *domain, | |
1247 | struct intel_iommu *iommu) | |
1248 | { | |
1249 | int num; | |
1250 | unsigned long ndomains; | |
1251 | unsigned long flags; | |
1252 | ||
ba395927 KA |
1253 | ndomains = cap_ndoms(iommu->cap); |
1254 | ||
1255 | spin_lock_irqsave(&iommu->lock, flags); | |
2c2e2c38 | 1256 | |
ba395927 KA |
1257 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
1258 | if (num >= ndomains) { | |
1259 | spin_unlock_irqrestore(&iommu->lock, flags); | |
ba395927 | 1260 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
2c2e2c38 | 1261 | return -ENOMEM; |
ba395927 KA |
1262 | } |
1263 | ||
ba395927 | 1264 | domain->id = num; |
2c2e2c38 | 1265 | set_bit(num, iommu->domain_ids); |
8c11e798 | 1266 | set_bit(iommu->seq_id, &domain->iommu_bmp); |
ba395927 KA |
1267 | iommu->domains[num] = domain; |
1268 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1269 | ||
2c2e2c38 | 1270 | return 0; |
ba395927 KA |
1271 | } |
1272 | ||
2c2e2c38 FY |
1273 | static void iommu_detach_domain(struct dmar_domain *domain, |
1274 | struct intel_iommu *iommu) | |
ba395927 KA |
1275 | { |
1276 | unsigned long flags; | |
2c2e2c38 FY |
1277 | int num, ndomains; |
1278 | int found = 0; | |
ba395927 | 1279 | |
8c11e798 | 1280 | spin_lock_irqsave(&iommu->lock, flags); |
2c2e2c38 FY |
1281 | ndomains = cap_ndoms(iommu->cap); |
1282 | num = find_first_bit(iommu->domain_ids, ndomains); | |
1283 | for (; num < ndomains; ) { | |
1284 | if (iommu->domains[num] == domain) { | |
1285 | found = 1; | |
1286 | break; | |
1287 | } | |
1288 | num = find_next_bit(iommu->domain_ids, | |
1289 | cap_ndoms(iommu->cap), num+1); | |
1290 | } | |
1291 | ||
1292 | if (found) { | |
1293 | clear_bit(num, iommu->domain_ids); | |
1294 | clear_bit(iommu->seq_id, &domain->iommu_bmp); | |
1295 | iommu->domains[num] = NULL; | |
1296 | } | |
8c11e798 | 1297 | spin_unlock_irqrestore(&iommu->lock, flags); |
ba395927 KA |
1298 | } |
1299 | ||
1300 | static struct iova_domain reserved_iova_list; | |
8a443df4 MG |
1301 | static struct lock_class_key reserved_alloc_key; |
1302 | static struct lock_class_key reserved_rbtree_key; | |
ba395927 KA |
1303 | |
1304 | static void dmar_init_reserved_ranges(void) | |
1305 | { | |
1306 | struct pci_dev *pdev = NULL; | |
1307 | struct iova *iova; | |
1308 | int i; | |
1309 | u64 addr, size; | |
1310 | ||
f661197e | 1311 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
ba395927 | 1312 | |
8a443df4 MG |
1313 | lockdep_set_class(&reserved_iova_list.iova_alloc_lock, |
1314 | &reserved_alloc_key); | |
1315 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, | |
1316 | &reserved_rbtree_key); | |
1317 | ||
ba395927 KA |
1318 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
1319 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), | |
1320 | IOVA_PFN(IOAPIC_RANGE_END)); | |
1321 | if (!iova) | |
1322 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); | |
1323 | ||
1324 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ | |
1325 | for_each_pci_dev(pdev) { | |
1326 | struct resource *r; | |
1327 | ||
1328 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1329 | r = &pdev->resource[i]; | |
1330 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) | |
1331 | continue; | |
1332 | addr = r->start; | |
fd18de50 | 1333 | addr &= PHYSICAL_PAGE_MASK; |
ba395927 | 1334 | size = r->end - addr; |
5b6985ce | 1335 | size = PAGE_ALIGN(size); |
ba395927 KA |
1336 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr), |
1337 | IOVA_PFN(size + addr) - 1); | |
1338 | if (!iova) | |
1339 | printk(KERN_ERR "Reserve iova failed\n"); | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | } | |
1344 | ||
1345 | static void domain_reserve_special_ranges(struct dmar_domain *domain) | |
1346 | { | |
1347 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); | |
1348 | } | |
1349 | ||
1350 | static inline int guestwidth_to_adjustwidth(int gaw) | |
1351 | { | |
1352 | int agaw; | |
1353 | int r = (gaw - 12) % 9; | |
1354 | ||
1355 | if (r == 0) | |
1356 | agaw = gaw; | |
1357 | else | |
1358 | agaw = gaw + 9 - r; | |
1359 | if (agaw > 64) | |
1360 | agaw = 64; | |
1361 | return agaw; | |
1362 | } | |
1363 | ||
1364 | static int domain_init(struct dmar_domain *domain, int guest_width) | |
1365 | { | |
1366 | struct intel_iommu *iommu; | |
1367 | int adjust_width, agaw; | |
1368 | unsigned long sagaw; | |
1369 | ||
f661197e | 1370 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
ba395927 | 1371 | spin_lock_init(&domain->mapping_lock); |
c7151a8d | 1372 | spin_lock_init(&domain->iommu_lock); |
ba395927 KA |
1373 | |
1374 | domain_reserve_special_ranges(domain); | |
1375 | ||
1376 | /* calculate AGAW */ | |
8c11e798 | 1377 | iommu = domain_get_iommu(domain); |
ba395927 KA |
1378 | if (guest_width > cap_mgaw(iommu->cap)) |
1379 | guest_width = cap_mgaw(iommu->cap); | |
1380 | domain->gaw = guest_width; | |
1381 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
1382 | agaw = width_to_agaw(adjust_width); | |
1383 | sagaw = cap_sagaw(iommu->cap); | |
1384 | if (!test_bit(agaw, &sagaw)) { | |
1385 | /* hardware doesn't support it, choose a bigger one */ | |
1386 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); | |
1387 | agaw = find_next_bit(&sagaw, 5, agaw); | |
1388 | if (agaw >= 5) | |
1389 | return -ENODEV; | |
1390 | } | |
1391 | domain->agaw = agaw; | |
1392 | INIT_LIST_HEAD(&domain->devices); | |
1393 | ||
8e604097 WH |
1394 | if (ecap_coherent(iommu->ecap)) |
1395 | domain->iommu_coherency = 1; | |
1396 | else | |
1397 | domain->iommu_coherency = 0; | |
1398 | ||
58c610bd SY |
1399 | if (ecap_sc_support(iommu->ecap)) |
1400 | domain->iommu_snooping = 1; | |
1401 | else | |
1402 | domain->iommu_snooping = 0; | |
1403 | ||
c7151a8d WH |
1404 | domain->iommu_count = 1; |
1405 | ||
ba395927 KA |
1406 | /* always allocate the top pgd */ |
1407 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(); | |
1408 | if (!domain->pgd) | |
1409 | return -ENOMEM; | |
5b6985ce | 1410 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
ba395927 KA |
1411 | return 0; |
1412 | } | |
1413 | ||
1414 | static void domain_exit(struct dmar_domain *domain) | |
1415 | { | |
2c2e2c38 FY |
1416 | struct dmar_drhd_unit *drhd; |
1417 | struct intel_iommu *iommu; | |
ba395927 KA |
1418 | |
1419 | /* Domain 0 is reserved, so dont process it */ | |
1420 | if (!domain) | |
1421 | return; | |
1422 | ||
1423 | domain_remove_dev_info(domain); | |
1424 | /* destroy iovas */ | |
1425 | put_iova_domain(&domain->iovad); | |
ba395927 KA |
1426 | |
1427 | /* clear ptes */ | |
595badf5 | 1428 | dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 KA |
1429 | |
1430 | /* free page tables */ | |
d794dc9b | 1431 | dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 | 1432 | |
2c2e2c38 FY |
1433 | for_each_active_iommu(iommu, drhd) |
1434 | if (test_bit(iommu->seq_id, &domain->iommu_bmp)) | |
1435 | iommu_detach_domain(domain, iommu); | |
1436 | ||
ba395927 KA |
1437 | free_domain_mem(domain); |
1438 | } | |
1439 | ||
4ed0d3e6 FY |
1440 | static int domain_context_mapping_one(struct dmar_domain *domain, int segment, |
1441 | u8 bus, u8 devfn, int translation) | |
ba395927 KA |
1442 | { |
1443 | struct context_entry *context; | |
ba395927 | 1444 | unsigned long flags; |
5331fe6f | 1445 | struct intel_iommu *iommu; |
ea6606b0 WH |
1446 | struct dma_pte *pgd; |
1447 | unsigned long num; | |
1448 | unsigned long ndomains; | |
1449 | int id; | |
1450 | int agaw; | |
93a23a72 | 1451 | struct device_domain_info *info = NULL; |
ba395927 KA |
1452 | |
1453 | pr_debug("Set context mapping for %02x:%02x.%d\n", | |
1454 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
4ed0d3e6 | 1455 | |
ba395927 | 1456 | BUG_ON(!domain->pgd); |
4ed0d3e6 FY |
1457 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
1458 | translation != CONTEXT_TT_MULTI_LEVEL); | |
5331fe6f | 1459 | |
276dbf99 | 1460 | iommu = device_to_iommu(segment, bus, devfn); |
5331fe6f WH |
1461 | if (!iommu) |
1462 | return -ENODEV; | |
1463 | ||
ba395927 KA |
1464 | context = device_to_context_entry(iommu, bus, devfn); |
1465 | if (!context) | |
1466 | return -ENOMEM; | |
1467 | spin_lock_irqsave(&iommu->lock, flags); | |
c07e7d21 | 1468 | if (context_present(context)) { |
ba395927 KA |
1469 | spin_unlock_irqrestore(&iommu->lock, flags); |
1470 | return 0; | |
1471 | } | |
1472 | ||
ea6606b0 WH |
1473 | id = domain->id; |
1474 | pgd = domain->pgd; | |
1475 | ||
2c2e2c38 FY |
1476 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
1477 | domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) { | |
ea6606b0 WH |
1478 | int found = 0; |
1479 | ||
1480 | /* find an available domain id for this device in iommu */ | |
1481 | ndomains = cap_ndoms(iommu->cap); | |
1482 | num = find_first_bit(iommu->domain_ids, ndomains); | |
1483 | for (; num < ndomains; ) { | |
1484 | if (iommu->domains[num] == domain) { | |
1485 | id = num; | |
1486 | found = 1; | |
1487 | break; | |
1488 | } | |
1489 | num = find_next_bit(iommu->domain_ids, | |
1490 | cap_ndoms(iommu->cap), num+1); | |
1491 | } | |
1492 | ||
1493 | if (found == 0) { | |
1494 | num = find_first_zero_bit(iommu->domain_ids, ndomains); | |
1495 | if (num >= ndomains) { | |
1496 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1497 | printk(KERN_ERR "IOMMU: no free domain ids\n"); | |
1498 | return -EFAULT; | |
1499 | } | |
1500 | ||
1501 | set_bit(num, iommu->domain_ids); | |
2c2e2c38 | 1502 | set_bit(iommu->seq_id, &domain->iommu_bmp); |
ea6606b0 WH |
1503 | iommu->domains[num] = domain; |
1504 | id = num; | |
1505 | } | |
1506 | ||
1507 | /* Skip top levels of page tables for | |
1508 | * iommu which has less agaw than default. | |
1509 | */ | |
1510 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { | |
1511 | pgd = phys_to_virt(dma_pte_addr(pgd)); | |
1512 | if (!dma_pte_present(pgd)) { | |
1513 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1514 | return -ENOMEM; | |
1515 | } | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | context_set_domain_id(context, id); | |
4ed0d3e6 | 1520 | |
93a23a72 YZ |
1521 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
1522 | info = iommu_support_dev_iotlb(domain, segment, bus, devfn); | |
1523 | translation = info ? CONTEXT_TT_DEV_IOTLB : | |
1524 | CONTEXT_TT_MULTI_LEVEL; | |
1525 | } | |
4ed0d3e6 FY |
1526 | /* |
1527 | * In pass through mode, AW must be programmed to indicate the largest | |
1528 | * AGAW value supported by hardware. And ASR is ignored by hardware. | |
1529 | */ | |
93a23a72 | 1530 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
4ed0d3e6 | 1531 | context_set_address_width(context, iommu->msagaw); |
93a23a72 YZ |
1532 | else { |
1533 | context_set_address_root(context, virt_to_phys(pgd)); | |
1534 | context_set_address_width(context, iommu->agaw); | |
1535 | } | |
4ed0d3e6 FY |
1536 | |
1537 | context_set_translation_type(context, translation); | |
c07e7d21 MM |
1538 | context_set_fault_enable(context); |
1539 | context_set_present(context); | |
5331fe6f | 1540 | domain_flush_cache(domain, context, sizeof(*context)); |
ba395927 | 1541 | |
4c25a2c1 DW |
1542 | /* |
1543 | * It's a non-present to present mapping. If hardware doesn't cache | |
1544 | * non-present entry we only need to flush the write-buffer. If the | |
1545 | * _does_ cache non-present entries, then it does so in the special | |
1546 | * domain #0, which we have to flush: | |
1547 | */ | |
1548 | if (cap_caching_mode(iommu->cap)) { | |
1549 | iommu->flush.flush_context(iommu, 0, | |
1550 | (((u16)bus) << 8) | devfn, | |
1551 | DMA_CCMD_MASK_NOBIT, | |
1552 | DMA_CCMD_DEVICE_INVL); | |
1f0ef2aa | 1553 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH); |
4c25a2c1 | 1554 | } else { |
ba395927 | 1555 | iommu_flush_write_buffer(iommu); |
4c25a2c1 | 1556 | } |
93a23a72 | 1557 | iommu_enable_dev_iotlb(info); |
ba395927 | 1558 | spin_unlock_irqrestore(&iommu->lock, flags); |
c7151a8d WH |
1559 | |
1560 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
1561 | if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) { | |
1562 | domain->iommu_count++; | |
58c610bd | 1563 | domain_update_iommu_cap(domain); |
c7151a8d WH |
1564 | } |
1565 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
ba395927 KA |
1566 | return 0; |
1567 | } | |
1568 | ||
1569 | static int | |
4ed0d3e6 FY |
1570 | domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev, |
1571 | int translation) | |
ba395927 KA |
1572 | { |
1573 | int ret; | |
1574 | struct pci_dev *tmp, *parent; | |
1575 | ||
276dbf99 | 1576 | ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus), |
4ed0d3e6 FY |
1577 | pdev->bus->number, pdev->devfn, |
1578 | translation); | |
ba395927 KA |
1579 | if (ret) |
1580 | return ret; | |
1581 | ||
1582 | /* dependent device mapping */ | |
1583 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
1584 | if (!tmp) | |
1585 | return 0; | |
1586 | /* Secondary interface's bus number and devfn 0 */ | |
1587 | parent = pdev->bus->self; | |
1588 | while (parent != tmp) { | |
276dbf99 DW |
1589 | ret = domain_context_mapping_one(domain, |
1590 | pci_domain_nr(parent->bus), | |
1591 | parent->bus->number, | |
4ed0d3e6 | 1592 | parent->devfn, translation); |
ba395927 KA |
1593 | if (ret) |
1594 | return ret; | |
1595 | parent = parent->bus->self; | |
1596 | } | |
1597 | if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */ | |
1598 | return domain_context_mapping_one(domain, | |
276dbf99 | 1599 | pci_domain_nr(tmp->subordinate), |
4ed0d3e6 FY |
1600 | tmp->subordinate->number, 0, |
1601 | translation); | |
ba395927 KA |
1602 | else /* this is a legacy PCI bridge */ |
1603 | return domain_context_mapping_one(domain, | |
276dbf99 DW |
1604 | pci_domain_nr(tmp->bus), |
1605 | tmp->bus->number, | |
4ed0d3e6 FY |
1606 | tmp->devfn, |
1607 | translation); | |
ba395927 KA |
1608 | } |
1609 | ||
5331fe6f | 1610 | static int domain_context_mapped(struct pci_dev *pdev) |
ba395927 KA |
1611 | { |
1612 | int ret; | |
1613 | struct pci_dev *tmp, *parent; | |
5331fe6f WH |
1614 | struct intel_iommu *iommu; |
1615 | ||
276dbf99 DW |
1616 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
1617 | pdev->devfn); | |
5331fe6f WH |
1618 | if (!iommu) |
1619 | return -ENODEV; | |
ba395927 | 1620 | |
276dbf99 | 1621 | ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn); |
ba395927 KA |
1622 | if (!ret) |
1623 | return ret; | |
1624 | /* dependent device mapping */ | |
1625 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
1626 | if (!tmp) | |
1627 | return ret; | |
1628 | /* Secondary interface's bus number and devfn 0 */ | |
1629 | parent = pdev->bus->self; | |
1630 | while (parent != tmp) { | |
8c11e798 | 1631 | ret = device_context_mapped(iommu, parent->bus->number, |
276dbf99 | 1632 | parent->devfn); |
ba395927 KA |
1633 | if (!ret) |
1634 | return ret; | |
1635 | parent = parent->bus->self; | |
1636 | } | |
1637 | if (tmp->is_pcie) | |
276dbf99 DW |
1638 | return device_context_mapped(iommu, tmp->subordinate->number, |
1639 | 0); | |
ba395927 | 1640 | else |
276dbf99 DW |
1641 | return device_context_mapped(iommu, tmp->bus->number, |
1642 | tmp->devfn); | |
ba395927 KA |
1643 | } |
1644 | ||
1645 | static int | |
1646 | domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova, | |
1647 | u64 hpa, size_t size, int prot) | |
1648 | { | |
1649 | u64 start_pfn, end_pfn; | |
1650 | struct dma_pte *pte; | |
1651 | int index; | |
5b6985ce FY |
1652 | int addr_width = agaw_to_width(domain->agaw); |
1653 | ||
66eae846 | 1654 | BUG_ON(hpa >> addr_width); |
ba395927 KA |
1655 | |
1656 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | |
1657 | return -EINVAL; | |
5b6985ce FY |
1658 | iova &= PAGE_MASK; |
1659 | start_pfn = ((u64)hpa) >> VTD_PAGE_SHIFT; | |
1660 | end_pfn = (VTD_PAGE_ALIGN(((u64)hpa) + size)) >> VTD_PAGE_SHIFT; | |
ba395927 KA |
1661 | index = 0; |
1662 | while (start_pfn < end_pfn) { | |
5b6985ce | 1663 | pte = addr_to_dma_pte(domain, iova + VTD_PAGE_SIZE * index); |
ba395927 KA |
1664 | if (!pte) |
1665 | return -ENOMEM; | |
1666 | /* We don't need lock here, nobody else | |
1667 | * touches the iova range | |
1668 | */ | |
19c239ce | 1669 | BUG_ON(dma_pte_addr(pte)); |
dd4e8319 | 1670 | dma_set_pte_pfn(pte, start_pfn); |
19c239ce | 1671 | dma_set_pte_prot(pte, prot); |
9cf06697 SY |
1672 | if (prot & DMA_PTE_SNP) |
1673 | dma_set_pte_snp(pte); | |
5331fe6f | 1674 | domain_flush_cache(domain, pte, sizeof(*pte)); |
ba395927 KA |
1675 | start_pfn++; |
1676 | index++; | |
1677 | } | |
1678 | return 0; | |
1679 | } | |
1680 | ||
c7151a8d | 1681 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
ba395927 | 1682 | { |
c7151a8d WH |
1683 | if (!iommu) |
1684 | return; | |
8c11e798 WH |
1685 | |
1686 | clear_context_table(iommu, bus, devfn); | |
1687 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
4c25a2c1 | 1688 | DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 1689 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
ba395927 KA |
1690 | } |
1691 | ||
1692 | static void domain_remove_dev_info(struct dmar_domain *domain) | |
1693 | { | |
1694 | struct device_domain_info *info; | |
1695 | unsigned long flags; | |
c7151a8d | 1696 | struct intel_iommu *iommu; |
ba395927 KA |
1697 | |
1698 | spin_lock_irqsave(&device_domain_lock, flags); | |
1699 | while (!list_empty(&domain->devices)) { | |
1700 | info = list_entry(domain->devices.next, | |
1701 | struct device_domain_info, link); | |
1702 | list_del(&info->link); | |
1703 | list_del(&info->global); | |
1704 | if (info->dev) | |
358dd8ac | 1705 | info->dev->dev.archdata.iommu = NULL; |
ba395927 KA |
1706 | spin_unlock_irqrestore(&device_domain_lock, flags); |
1707 | ||
93a23a72 | 1708 | iommu_disable_dev_iotlb(info); |
276dbf99 | 1709 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
c7151a8d | 1710 | iommu_detach_dev(iommu, info->bus, info->devfn); |
ba395927 KA |
1711 | free_devinfo_mem(info); |
1712 | ||
1713 | spin_lock_irqsave(&device_domain_lock, flags); | |
1714 | } | |
1715 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1716 | } | |
1717 | ||
1718 | /* | |
1719 | * find_domain | |
358dd8ac | 1720 | * Note: we use struct pci_dev->dev.archdata.iommu stores the info |
ba395927 | 1721 | */ |
38717946 | 1722 | static struct dmar_domain * |
ba395927 KA |
1723 | find_domain(struct pci_dev *pdev) |
1724 | { | |
1725 | struct device_domain_info *info; | |
1726 | ||
1727 | /* No lock here, assumes no domain exit in normal case */ | |
358dd8ac | 1728 | info = pdev->dev.archdata.iommu; |
ba395927 KA |
1729 | if (info) |
1730 | return info->domain; | |
1731 | return NULL; | |
1732 | } | |
1733 | ||
ba395927 KA |
1734 | /* domain is initialized */ |
1735 | static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw) | |
1736 | { | |
1737 | struct dmar_domain *domain, *found = NULL; | |
1738 | struct intel_iommu *iommu; | |
1739 | struct dmar_drhd_unit *drhd; | |
1740 | struct device_domain_info *info, *tmp; | |
1741 | struct pci_dev *dev_tmp; | |
1742 | unsigned long flags; | |
1743 | int bus = 0, devfn = 0; | |
276dbf99 | 1744 | int segment; |
2c2e2c38 | 1745 | int ret; |
ba395927 KA |
1746 | |
1747 | domain = find_domain(pdev); | |
1748 | if (domain) | |
1749 | return domain; | |
1750 | ||
276dbf99 DW |
1751 | segment = pci_domain_nr(pdev->bus); |
1752 | ||
ba395927 KA |
1753 | dev_tmp = pci_find_upstream_pcie_bridge(pdev); |
1754 | if (dev_tmp) { | |
1755 | if (dev_tmp->is_pcie) { | |
1756 | bus = dev_tmp->subordinate->number; | |
1757 | devfn = 0; | |
1758 | } else { | |
1759 | bus = dev_tmp->bus->number; | |
1760 | devfn = dev_tmp->devfn; | |
1761 | } | |
1762 | spin_lock_irqsave(&device_domain_lock, flags); | |
1763 | list_for_each_entry(info, &device_domain_list, global) { | |
276dbf99 DW |
1764 | if (info->segment == segment && |
1765 | info->bus == bus && info->devfn == devfn) { | |
ba395927 KA |
1766 | found = info->domain; |
1767 | break; | |
1768 | } | |
1769 | } | |
1770 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1771 | /* pcie-pci bridge already has a domain, uses it */ | |
1772 | if (found) { | |
1773 | domain = found; | |
1774 | goto found_domain; | |
1775 | } | |
1776 | } | |
1777 | ||
2c2e2c38 FY |
1778 | domain = alloc_domain(); |
1779 | if (!domain) | |
1780 | goto error; | |
1781 | ||
ba395927 KA |
1782 | /* Allocate new domain for the device */ |
1783 | drhd = dmar_find_matched_drhd_unit(pdev); | |
1784 | if (!drhd) { | |
1785 | printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n", | |
1786 | pci_name(pdev)); | |
1787 | return NULL; | |
1788 | } | |
1789 | iommu = drhd->iommu; | |
1790 | ||
2c2e2c38 FY |
1791 | ret = iommu_attach_domain(domain, iommu); |
1792 | if (ret) { | |
1793 | domain_exit(domain); | |
ba395927 | 1794 | goto error; |
2c2e2c38 | 1795 | } |
ba395927 KA |
1796 | |
1797 | if (domain_init(domain, gaw)) { | |
1798 | domain_exit(domain); | |
1799 | goto error; | |
1800 | } | |
1801 | ||
1802 | /* register pcie-to-pci device */ | |
1803 | if (dev_tmp) { | |
1804 | info = alloc_devinfo_mem(); | |
1805 | if (!info) { | |
1806 | domain_exit(domain); | |
1807 | goto error; | |
1808 | } | |
276dbf99 | 1809 | info->segment = segment; |
ba395927 KA |
1810 | info->bus = bus; |
1811 | info->devfn = devfn; | |
1812 | info->dev = NULL; | |
1813 | info->domain = domain; | |
1814 | /* This domain is shared by devices under p2p bridge */ | |
3b5410e7 | 1815 | domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES; |
ba395927 KA |
1816 | |
1817 | /* pcie-to-pci bridge already has a domain, uses it */ | |
1818 | found = NULL; | |
1819 | spin_lock_irqsave(&device_domain_lock, flags); | |
1820 | list_for_each_entry(tmp, &device_domain_list, global) { | |
276dbf99 DW |
1821 | if (tmp->segment == segment && |
1822 | tmp->bus == bus && tmp->devfn == devfn) { | |
ba395927 KA |
1823 | found = tmp->domain; |
1824 | break; | |
1825 | } | |
1826 | } | |
1827 | if (found) { | |
1828 | free_devinfo_mem(info); | |
1829 | domain_exit(domain); | |
1830 | domain = found; | |
1831 | } else { | |
1832 | list_add(&info->link, &domain->devices); | |
1833 | list_add(&info->global, &device_domain_list); | |
1834 | } | |
1835 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1836 | } | |
1837 | ||
1838 | found_domain: | |
1839 | info = alloc_devinfo_mem(); | |
1840 | if (!info) | |
1841 | goto error; | |
276dbf99 | 1842 | info->segment = segment; |
ba395927 KA |
1843 | info->bus = pdev->bus->number; |
1844 | info->devfn = pdev->devfn; | |
1845 | info->dev = pdev; | |
1846 | info->domain = domain; | |
1847 | spin_lock_irqsave(&device_domain_lock, flags); | |
1848 | /* somebody is fast */ | |
1849 | found = find_domain(pdev); | |
1850 | if (found != NULL) { | |
1851 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1852 | if (found != domain) { | |
1853 | domain_exit(domain); | |
1854 | domain = found; | |
1855 | } | |
1856 | free_devinfo_mem(info); | |
1857 | return domain; | |
1858 | } | |
1859 | list_add(&info->link, &domain->devices); | |
1860 | list_add(&info->global, &device_domain_list); | |
358dd8ac | 1861 | pdev->dev.archdata.iommu = info; |
ba395927 KA |
1862 | spin_unlock_irqrestore(&device_domain_lock, flags); |
1863 | return domain; | |
1864 | error: | |
1865 | /* recheck it here, maybe others set it */ | |
1866 | return find_domain(pdev); | |
1867 | } | |
1868 | ||
2c2e2c38 FY |
1869 | static int iommu_identity_mapping; |
1870 | ||
b213203e DW |
1871 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
1872 | unsigned long long start, | |
1873 | unsigned long long end) | |
ba395927 | 1874 | { |
ba395927 | 1875 | unsigned long size; |
5b6985ce | 1876 | unsigned long long base; |
ba395927 KA |
1877 | |
1878 | /* The address might not be aligned */ | |
5b6985ce | 1879 | base = start & PAGE_MASK; |
ba395927 | 1880 | size = end - base; |
5b6985ce | 1881 | size = PAGE_ALIGN(size); |
ba395927 KA |
1882 | if (!reserve_iova(&domain->iovad, IOVA_PFN(base), |
1883 | IOVA_PFN(base + size) - 1)) { | |
1884 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); | |
b213203e | 1885 | return -ENOMEM; |
ba395927 KA |
1886 | } |
1887 | ||
b213203e DW |
1888 | pr_debug("Mapping reserved region %lx@%llx for domain %d\n", |
1889 | size, base, domain->id); | |
ba395927 KA |
1890 | /* |
1891 | * RMRR range might have overlap with physical memory range, | |
1892 | * clear it first | |
1893 | */ | |
595badf5 DW |
1894 | dma_pte_clear_range(domain, base >> VTD_PAGE_SHIFT, |
1895 | (base + size - 1) >> VTD_PAGE_SHIFT); | |
ba395927 | 1896 | |
b213203e DW |
1897 | return domain_page_mapping(domain, base, base, size, |
1898 | DMA_PTE_READ|DMA_PTE_WRITE); | |
1899 | } | |
1900 | ||
1901 | static int iommu_prepare_identity_map(struct pci_dev *pdev, | |
1902 | unsigned long long start, | |
1903 | unsigned long long end) | |
1904 | { | |
1905 | struct dmar_domain *domain; | |
1906 | int ret; | |
1907 | ||
1908 | printk(KERN_INFO | |
1909 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", | |
1910 | pci_name(pdev), start, end); | |
1911 | ||
c7ab48d2 | 1912 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
b213203e DW |
1913 | if (!domain) |
1914 | return -ENOMEM; | |
1915 | ||
1916 | ret = iommu_domain_identity_map(domain, start, end); | |
ba395927 KA |
1917 | if (ret) |
1918 | goto error; | |
1919 | ||
1920 | /* context entry init */ | |
4ed0d3e6 | 1921 | ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
b213203e DW |
1922 | if (ret) |
1923 | goto error; | |
1924 | ||
1925 | return 0; | |
1926 | ||
1927 | error: | |
ba395927 KA |
1928 | domain_exit(domain); |
1929 | return ret; | |
ba395927 KA |
1930 | } |
1931 | ||
1932 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, | |
1933 | struct pci_dev *pdev) | |
1934 | { | |
358dd8ac | 1935 | if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
ba395927 KA |
1936 | return 0; |
1937 | return iommu_prepare_identity_map(pdev, rmrr->base_address, | |
1938 | rmrr->end_address + 1); | |
1939 | } | |
1940 | ||
49a0429e KA |
1941 | #ifdef CONFIG_DMAR_FLOPPY_WA |
1942 | static inline void iommu_prepare_isa(void) | |
1943 | { | |
1944 | struct pci_dev *pdev; | |
1945 | int ret; | |
1946 | ||
1947 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
1948 | if (!pdev) | |
1949 | return; | |
1950 | ||
c7ab48d2 | 1951 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
49a0429e KA |
1952 | ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024); |
1953 | ||
1954 | if (ret) | |
c7ab48d2 DW |
1955 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
1956 | "floppy might not work\n"); | |
49a0429e KA |
1957 | |
1958 | } | |
1959 | #else | |
1960 | static inline void iommu_prepare_isa(void) | |
1961 | { | |
1962 | return; | |
1963 | } | |
1964 | #endif /* !CONFIG_DMAR_FLPY_WA */ | |
1965 | ||
4ed0d3e6 FY |
1966 | /* Initialize each context entry as pass through.*/ |
1967 | static int __init init_context_pass_through(void) | |
1968 | { | |
1969 | struct pci_dev *pdev = NULL; | |
1970 | struct dmar_domain *domain; | |
1971 | int ret; | |
1972 | ||
1973 | for_each_pci_dev(pdev) { | |
1974 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
1975 | ret = domain_context_mapping(domain, pdev, | |
1976 | CONTEXT_TT_PASS_THROUGH); | |
1977 | if (ret) | |
1978 | return ret; | |
1979 | } | |
1980 | return 0; | |
1981 | } | |
1982 | ||
2c2e2c38 | 1983 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
c7ab48d2 DW |
1984 | |
1985 | static int __init si_domain_work_fn(unsigned long start_pfn, | |
1986 | unsigned long end_pfn, void *datax) | |
1987 | { | |
1988 | int *ret = datax; | |
1989 | ||
1990 | *ret = iommu_domain_identity_map(si_domain, | |
1991 | (uint64_t)start_pfn << PAGE_SHIFT, | |
1992 | (uint64_t)end_pfn << PAGE_SHIFT); | |
1993 | return *ret; | |
1994 | ||
1995 | } | |
1996 | ||
2c2e2c38 FY |
1997 | static int si_domain_init(void) |
1998 | { | |
1999 | struct dmar_drhd_unit *drhd; | |
2000 | struct intel_iommu *iommu; | |
c7ab48d2 | 2001 | int nid, ret = 0; |
2c2e2c38 FY |
2002 | |
2003 | si_domain = alloc_domain(); | |
2004 | if (!si_domain) | |
2005 | return -EFAULT; | |
2006 | ||
c7ab48d2 | 2007 | pr_debug("Identity mapping domain is domain %d\n", si_domain->id); |
2c2e2c38 FY |
2008 | |
2009 | for_each_active_iommu(iommu, drhd) { | |
2010 | ret = iommu_attach_domain(si_domain, iommu); | |
2011 | if (ret) { | |
2012 | domain_exit(si_domain); | |
2013 | return -EFAULT; | |
2014 | } | |
2015 | } | |
2016 | ||
2017 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { | |
2018 | domain_exit(si_domain); | |
2019 | return -EFAULT; | |
2020 | } | |
2021 | ||
2022 | si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY; | |
2023 | ||
c7ab48d2 DW |
2024 | for_each_online_node(nid) { |
2025 | work_with_active_regions(nid, si_domain_work_fn, &ret); | |
2026 | if (ret) | |
2027 | return ret; | |
2028 | } | |
2029 | ||
2c2e2c38 FY |
2030 | return 0; |
2031 | } | |
2032 | ||
2033 | static void domain_remove_one_dev_info(struct dmar_domain *domain, | |
2034 | struct pci_dev *pdev); | |
2035 | static int identity_mapping(struct pci_dev *pdev) | |
2036 | { | |
2037 | struct device_domain_info *info; | |
2038 | ||
2039 | if (likely(!iommu_identity_mapping)) | |
2040 | return 0; | |
2041 | ||
2042 | ||
2043 | list_for_each_entry(info, &si_domain->devices, link) | |
2044 | if (info->dev == pdev) | |
2045 | return 1; | |
2046 | return 0; | |
2047 | } | |
2048 | ||
2049 | static int domain_add_dev_info(struct dmar_domain *domain, | |
2050 | struct pci_dev *pdev) | |
2051 | { | |
2052 | struct device_domain_info *info; | |
2053 | unsigned long flags; | |
2054 | ||
2055 | info = alloc_devinfo_mem(); | |
2056 | if (!info) | |
2057 | return -ENOMEM; | |
2058 | ||
2059 | info->segment = pci_domain_nr(pdev->bus); | |
2060 | info->bus = pdev->bus->number; | |
2061 | info->devfn = pdev->devfn; | |
2062 | info->dev = pdev; | |
2063 | info->domain = domain; | |
2064 | ||
2065 | spin_lock_irqsave(&device_domain_lock, flags); | |
2066 | list_add(&info->link, &domain->devices); | |
2067 | list_add(&info->global, &device_domain_list); | |
2068 | pdev->dev.archdata.iommu = info; | |
2069 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2070 | ||
2071 | return 0; | |
2072 | } | |
2073 | ||
2074 | static int iommu_prepare_static_identity_mapping(void) | |
2075 | { | |
2c2e2c38 FY |
2076 | struct pci_dev *pdev = NULL; |
2077 | int ret; | |
2078 | ||
2079 | ret = si_domain_init(); | |
2080 | if (ret) | |
2081 | return -EFAULT; | |
2082 | ||
2c2e2c38 | 2083 | for_each_pci_dev(pdev) { |
c7ab48d2 DW |
2084 | printk(KERN_INFO "IOMMU: identity mapping for device %s\n", |
2085 | pci_name(pdev)); | |
2086 | ||
2087 | ret = domain_context_mapping(si_domain, pdev, | |
2088 | CONTEXT_TT_MULTI_LEVEL); | |
2089 | if (ret) | |
2090 | return ret; | |
2c2e2c38 FY |
2091 | ret = domain_add_dev_info(si_domain, pdev); |
2092 | if (ret) | |
2093 | return ret; | |
2094 | } | |
2095 | ||
2096 | return 0; | |
2097 | } | |
2098 | ||
2099 | int __init init_dmars(void) | |
ba395927 KA |
2100 | { |
2101 | struct dmar_drhd_unit *drhd; | |
2102 | struct dmar_rmrr_unit *rmrr; | |
2103 | struct pci_dev *pdev; | |
2104 | struct intel_iommu *iommu; | |
9d783ba0 | 2105 | int i, ret; |
4ed0d3e6 | 2106 | int pass_through = 1; |
ba395927 | 2107 | |
2c2e2c38 FY |
2108 | /* |
2109 | * In case pass through can not be enabled, iommu tries to use identity | |
2110 | * mapping. | |
2111 | */ | |
2112 | if (iommu_pass_through) | |
2113 | iommu_identity_mapping = 1; | |
2114 | ||
ba395927 KA |
2115 | /* |
2116 | * for each drhd | |
2117 | * allocate root | |
2118 | * initialize and program root entry to not present | |
2119 | * endfor | |
2120 | */ | |
2121 | for_each_drhd_unit(drhd) { | |
5e0d2a6f | 2122 | g_num_of_iommus++; |
2123 | /* | |
2124 | * lock not needed as this is only incremented in the single | |
2125 | * threaded kernel __init code path all other access are read | |
2126 | * only | |
2127 | */ | |
2128 | } | |
2129 | ||
d9630fe9 WH |
2130 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
2131 | GFP_KERNEL); | |
2132 | if (!g_iommus) { | |
2133 | printk(KERN_ERR "Allocating global iommu array failed\n"); | |
2134 | ret = -ENOMEM; | |
2135 | goto error; | |
2136 | } | |
2137 | ||
80b20dd8 | 2138 | deferred_flush = kzalloc(g_num_of_iommus * |
2139 | sizeof(struct deferred_flush_tables), GFP_KERNEL); | |
2140 | if (!deferred_flush) { | |
d9630fe9 | 2141 | kfree(g_iommus); |
5e0d2a6f | 2142 | ret = -ENOMEM; |
2143 | goto error; | |
2144 | } | |
2145 | ||
5e0d2a6f | 2146 | for_each_drhd_unit(drhd) { |
2147 | if (drhd->ignored) | |
2148 | continue; | |
1886e8a9 SS |
2149 | |
2150 | iommu = drhd->iommu; | |
d9630fe9 | 2151 | g_iommus[iommu->seq_id] = iommu; |
ba395927 | 2152 | |
e61d98d8 SS |
2153 | ret = iommu_init_domains(iommu); |
2154 | if (ret) | |
2155 | goto error; | |
2156 | ||
ba395927 KA |
2157 | /* |
2158 | * TBD: | |
2159 | * we could share the same root & context tables | |
2160 | * amoung all IOMMU's. Need to Split it later. | |
2161 | */ | |
2162 | ret = iommu_alloc_root_entry(iommu); | |
2163 | if (ret) { | |
2164 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); | |
2165 | goto error; | |
2166 | } | |
4ed0d3e6 FY |
2167 | if (!ecap_pass_through(iommu->ecap)) |
2168 | pass_through = 0; | |
ba395927 | 2169 | } |
4ed0d3e6 FY |
2170 | if (iommu_pass_through) |
2171 | if (!pass_through) { | |
2172 | printk(KERN_INFO | |
2173 | "Pass Through is not supported by hardware.\n"); | |
2174 | iommu_pass_through = 0; | |
2175 | } | |
ba395927 | 2176 | |
1531a6a6 SS |
2177 | /* |
2178 | * Start from the sane iommu hardware state. | |
2179 | */ | |
a77b67d4 YS |
2180 | for_each_drhd_unit(drhd) { |
2181 | if (drhd->ignored) | |
2182 | continue; | |
2183 | ||
2184 | iommu = drhd->iommu; | |
1531a6a6 SS |
2185 | |
2186 | /* | |
2187 | * If the queued invalidation is already initialized by us | |
2188 | * (for example, while enabling interrupt-remapping) then | |
2189 | * we got the things already rolling from a sane state. | |
2190 | */ | |
2191 | if (iommu->qi) | |
2192 | continue; | |
2193 | ||
2194 | /* | |
2195 | * Clear any previous faults. | |
2196 | */ | |
2197 | dmar_fault(-1, iommu); | |
2198 | /* | |
2199 | * Disable queued invalidation if supported and already enabled | |
2200 | * before OS handover. | |
2201 | */ | |
2202 | dmar_disable_qi(iommu); | |
2203 | } | |
2204 | ||
2205 | for_each_drhd_unit(drhd) { | |
2206 | if (drhd->ignored) | |
2207 | continue; | |
2208 | ||
2209 | iommu = drhd->iommu; | |
2210 | ||
a77b67d4 YS |
2211 | if (dmar_enable_qi(iommu)) { |
2212 | /* | |
2213 | * Queued Invalidate not enabled, use Register Based | |
2214 | * Invalidate | |
2215 | */ | |
2216 | iommu->flush.flush_context = __iommu_flush_context; | |
2217 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; | |
2218 | printk(KERN_INFO "IOMMU 0x%Lx: using Register based " | |
b4e0f9eb FT |
2219 | "invalidation\n", |
2220 | (unsigned long long)drhd->reg_base_addr); | |
a77b67d4 YS |
2221 | } else { |
2222 | iommu->flush.flush_context = qi_flush_context; | |
2223 | iommu->flush.flush_iotlb = qi_flush_iotlb; | |
2224 | printk(KERN_INFO "IOMMU 0x%Lx: using Queued " | |
b4e0f9eb FT |
2225 | "invalidation\n", |
2226 | (unsigned long long)drhd->reg_base_addr); | |
a77b67d4 YS |
2227 | } |
2228 | } | |
2229 | ||
ba395927 | 2230 | /* |
4ed0d3e6 FY |
2231 | * If pass through is set and enabled, context entries of all pci |
2232 | * devices are intialized by pass through translation type. | |
ba395927 | 2233 | */ |
4ed0d3e6 FY |
2234 | if (iommu_pass_through) { |
2235 | ret = init_context_pass_through(); | |
2236 | if (ret) { | |
2237 | printk(KERN_ERR "IOMMU: Pass through init failed.\n"); | |
2238 | iommu_pass_through = 0; | |
ba395927 KA |
2239 | } |
2240 | } | |
2241 | ||
ba395927 | 2242 | /* |
4ed0d3e6 | 2243 | * If pass through is not set or not enabled, setup context entries for |
2c2e2c38 FY |
2244 | * identity mappings for rmrr, gfx, and isa and may fall back to static |
2245 | * identity mapping if iommu_identity_mapping is set. | |
ba395927 | 2246 | */ |
4ed0d3e6 | 2247 | if (!iommu_pass_through) { |
2c2e2c38 FY |
2248 | if (iommu_identity_mapping) |
2249 | iommu_prepare_static_identity_mapping(); | |
4ed0d3e6 FY |
2250 | /* |
2251 | * For each rmrr | |
2252 | * for each dev attached to rmrr | |
2253 | * do | |
2254 | * locate drhd for dev, alloc domain for dev | |
2255 | * allocate free domain | |
2256 | * allocate page table entries for rmrr | |
2257 | * if context not allocated for bus | |
2258 | * allocate and init context | |
2259 | * set present in root table for this bus | |
2260 | * init context with domain, translation etc | |
2261 | * endfor | |
2262 | * endfor | |
2263 | */ | |
2c2e2c38 | 2264 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
4ed0d3e6 FY |
2265 | for_each_rmrr_units(rmrr) { |
2266 | for (i = 0; i < rmrr->devices_cnt; i++) { | |
2267 | pdev = rmrr->devices[i]; | |
2268 | /* | |
2269 | * some BIOS lists non-exist devices in DMAR | |
2270 | * table. | |
2271 | */ | |
2272 | if (!pdev) | |
2273 | continue; | |
2274 | ret = iommu_prepare_rmrr_dev(rmrr, pdev); | |
2275 | if (ret) | |
2276 | printk(KERN_ERR | |
ba395927 | 2277 | "IOMMU: mapping reserved region failed\n"); |
4ed0d3e6 | 2278 | } |
ba395927 | 2279 | } |
ba395927 | 2280 | |
4ed0d3e6 FY |
2281 | iommu_prepare_isa(); |
2282 | } | |
49a0429e | 2283 | |
ba395927 KA |
2284 | /* |
2285 | * for each drhd | |
2286 | * enable fault log | |
2287 | * global invalidate context cache | |
2288 | * global invalidate iotlb | |
2289 | * enable translation | |
2290 | */ | |
2291 | for_each_drhd_unit(drhd) { | |
2292 | if (drhd->ignored) | |
2293 | continue; | |
2294 | iommu = drhd->iommu; | |
ba395927 KA |
2295 | |
2296 | iommu_flush_write_buffer(iommu); | |
2297 | ||
3460a6d9 KA |
2298 | ret = dmar_set_interrupt(iommu); |
2299 | if (ret) | |
2300 | goto error; | |
2301 | ||
ba395927 KA |
2302 | iommu_set_root_entry(iommu); |
2303 | ||
4c25a2c1 | 2304 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2305 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
f8bab735 | 2306 | iommu_disable_protect_mem_regions(iommu); |
2307 | ||
ba395927 KA |
2308 | ret = iommu_enable_translation(iommu); |
2309 | if (ret) | |
2310 | goto error; | |
2311 | } | |
2312 | ||
2313 | return 0; | |
2314 | error: | |
2315 | for_each_drhd_unit(drhd) { | |
2316 | if (drhd->ignored) | |
2317 | continue; | |
2318 | iommu = drhd->iommu; | |
2319 | free_iommu(iommu); | |
2320 | } | |
d9630fe9 | 2321 | kfree(g_iommus); |
ba395927 KA |
2322 | return ret; |
2323 | } | |
2324 | ||
2325 | static inline u64 aligned_size(u64 host_addr, size_t size) | |
2326 | { | |
2327 | u64 addr; | |
5b6985ce FY |
2328 | addr = (host_addr & (~PAGE_MASK)) + size; |
2329 | return PAGE_ALIGN(addr); | |
ba395927 KA |
2330 | } |
2331 | ||
2332 | struct iova * | |
f76aec76 | 2333 | iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end) |
ba395927 | 2334 | { |
ba395927 KA |
2335 | struct iova *piova; |
2336 | ||
2337 | /* Make sure it's in range */ | |
ba395927 | 2338 | end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end); |
f76aec76 | 2339 | if (!size || (IOVA_START_ADDR + size > end)) |
ba395927 KA |
2340 | return NULL; |
2341 | ||
2342 | piova = alloc_iova(&domain->iovad, | |
5b6985ce | 2343 | size >> PAGE_SHIFT, IOVA_PFN(end), 1); |
ba395927 KA |
2344 | return piova; |
2345 | } | |
2346 | ||
f76aec76 KA |
2347 | static struct iova * |
2348 | __intel_alloc_iova(struct device *dev, struct dmar_domain *domain, | |
bb9e6d65 | 2349 | size_t size, u64 dma_mask) |
ba395927 | 2350 | { |
ba395927 | 2351 | struct pci_dev *pdev = to_pci_dev(dev); |
ba395927 | 2352 | struct iova *iova = NULL; |
ba395927 | 2353 | |
284901a9 | 2354 | if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac) |
bb9e6d65 FT |
2355 | iova = iommu_alloc_iova(domain, size, dma_mask); |
2356 | else { | |
ba395927 KA |
2357 | /* |
2358 | * First try to allocate an io virtual address in | |
284901a9 | 2359 | * DMA_BIT_MASK(32) and if that fails then try allocating |
3609801e | 2360 | * from higher range |
ba395927 | 2361 | */ |
284901a9 | 2362 | iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32)); |
ba395927 | 2363 | if (!iova) |
bb9e6d65 | 2364 | iova = iommu_alloc_iova(domain, size, dma_mask); |
ba395927 KA |
2365 | } |
2366 | ||
2367 | if (!iova) { | |
2368 | printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev)); | |
f76aec76 KA |
2369 | return NULL; |
2370 | } | |
2371 | ||
2372 | return iova; | |
2373 | } | |
2374 | ||
2375 | static struct dmar_domain * | |
2376 | get_valid_domain_for_dev(struct pci_dev *pdev) | |
2377 | { | |
2378 | struct dmar_domain *domain; | |
2379 | int ret; | |
2380 | ||
2381 | domain = get_domain_for_dev(pdev, | |
2382 | DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
2383 | if (!domain) { | |
2384 | printk(KERN_ERR | |
2385 | "Allocating domain for %s failed", pci_name(pdev)); | |
4fe05bbc | 2386 | return NULL; |
ba395927 KA |
2387 | } |
2388 | ||
2389 | /* make sure context mapping is ok */ | |
5331fe6f | 2390 | if (unlikely(!domain_context_mapped(pdev))) { |
4ed0d3e6 FY |
2391 | ret = domain_context_mapping(domain, pdev, |
2392 | CONTEXT_TT_MULTI_LEVEL); | |
f76aec76 KA |
2393 | if (ret) { |
2394 | printk(KERN_ERR | |
2395 | "Domain context map for %s failed", | |
2396 | pci_name(pdev)); | |
4fe05bbc | 2397 | return NULL; |
f76aec76 | 2398 | } |
ba395927 KA |
2399 | } |
2400 | ||
f76aec76 KA |
2401 | return domain; |
2402 | } | |
2403 | ||
2c2e2c38 FY |
2404 | static int iommu_dummy(struct pci_dev *pdev) |
2405 | { | |
2406 | return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; | |
2407 | } | |
2408 | ||
2409 | /* Check if the pdev needs to go through non-identity map and unmap process.*/ | |
2410 | static int iommu_no_mapping(struct pci_dev *pdev) | |
2411 | { | |
2412 | int found; | |
2413 | ||
2414 | if (!iommu_identity_mapping) | |
2415 | return iommu_dummy(pdev); | |
2416 | ||
2417 | found = identity_mapping(pdev); | |
2418 | if (found) { | |
2419 | if (pdev->dma_mask > DMA_BIT_MASK(32)) | |
2420 | return 1; | |
2421 | else { | |
2422 | /* | |
2423 | * 32 bit DMA is removed from si_domain and fall back | |
2424 | * to non-identity mapping. | |
2425 | */ | |
2426 | domain_remove_one_dev_info(si_domain, pdev); | |
2427 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", | |
2428 | pci_name(pdev)); | |
2429 | return 0; | |
2430 | } | |
2431 | } else { | |
2432 | /* | |
2433 | * In case of a detached 64 bit DMA device from vm, the device | |
2434 | * is put into si_domain for identity mapping. | |
2435 | */ | |
2436 | if (pdev->dma_mask > DMA_BIT_MASK(32)) { | |
2437 | int ret; | |
2438 | ret = domain_add_dev_info(si_domain, pdev); | |
2439 | if (!ret) { | |
2440 | printk(KERN_INFO "64bit %s uses identity mapping\n", | |
2441 | pci_name(pdev)); | |
2442 | return 1; | |
2443 | } | |
2444 | } | |
2445 | } | |
2446 | ||
2447 | return iommu_dummy(pdev); | |
2448 | } | |
2449 | ||
bb9e6d65 FT |
2450 | static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr, |
2451 | size_t size, int dir, u64 dma_mask) | |
f76aec76 KA |
2452 | { |
2453 | struct pci_dev *pdev = to_pci_dev(hwdev); | |
f76aec76 | 2454 | struct dmar_domain *domain; |
5b6985ce | 2455 | phys_addr_t start_paddr; |
f76aec76 KA |
2456 | struct iova *iova; |
2457 | int prot = 0; | |
6865f0d1 | 2458 | int ret; |
8c11e798 | 2459 | struct intel_iommu *iommu; |
f76aec76 KA |
2460 | |
2461 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 FY |
2462 | |
2463 | if (iommu_no_mapping(pdev)) | |
6865f0d1 | 2464 | return paddr; |
f76aec76 KA |
2465 | |
2466 | domain = get_valid_domain_for_dev(pdev); | |
2467 | if (!domain) | |
2468 | return 0; | |
2469 | ||
8c11e798 | 2470 | iommu = domain_get_iommu(domain); |
6865f0d1 | 2471 | size = aligned_size((u64)paddr, size); |
f76aec76 | 2472 | |
bb9e6d65 | 2473 | iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask); |
f76aec76 KA |
2474 | if (!iova) |
2475 | goto error; | |
2476 | ||
5b6985ce | 2477 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
f76aec76 | 2478 | |
ba395927 KA |
2479 | /* |
2480 | * Check if DMAR supports zero-length reads on write only | |
2481 | * mappings.. | |
2482 | */ | |
2483 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 2484 | !cap_zlr(iommu->cap)) |
ba395927 KA |
2485 | prot |= DMA_PTE_READ; |
2486 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
2487 | prot |= DMA_PTE_WRITE; | |
2488 | /* | |
6865f0d1 | 2489 | * paddr - (paddr + size) might be partial page, we should map the whole |
ba395927 | 2490 | * page. Note: if two part of one page are separately mapped, we |
6865f0d1 | 2491 | * might have two guest_addr mapping to the same host paddr, but this |
ba395927 KA |
2492 | * is not a big problem |
2493 | */ | |
6865f0d1 | 2494 | ret = domain_page_mapping(domain, start_paddr, |
fd18de50 DW |
2495 | ((u64)paddr) & PHYSICAL_PAGE_MASK, |
2496 | size, prot); | |
ba395927 KA |
2497 | if (ret) |
2498 | goto error; | |
2499 | ||
1f0ef2aa DW |
2500 | /* it's a non-present to present mapping. Only flush if caching mode */ |
2501 | if (cap_caching_mode(iommu->cap)) | |
2502 | iommu_flush_iotlb_psi(iommu, 0, start_paddr, | |
2503 | size >> VTD_PAGE_SHIFT); | |
2504 | else | |
8c11e798 | 2505 | iommu_flush_write_buffer(iommu); |
f76aec76 | 2506 | |
5b6985ce | 2507 | return start_paddr + ((u64)paddr & (~PAGE_MASK)); |
ba395927 | 2508 | |
ba395927 | 2509 | error: |
f76aec76 KA |
2510 | if (iova) |
2511 | __free_iova(&domain->iovad, iova); | |
4cf2e75d | 2512 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
5b6985ce | 2513 | pci_name(pdev), size, (unsigned long long)paddr, dir); |
ba395927 KA |
2514 | return 0; |
2515 | } | |
2516 | ||
ffbbef5c FT |
2517 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
2518 | unsigned long offset, size_t size, | |
2519 | enum dma_data_direction dir, | |
2520 | struct dma_attrs *attrs) | |
bb9e6d65 | 2521 | { |
ffbbef5c FT |
2522 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
2523 | dir, to_pci_dev(dev)->dma_mask); | |
bb9e6d65 FT |
2524 | } |
2525 | ||
5e0d2a6f | 2526 | static void flush_unmaps(void) |
2527 | { | |
80b20dd8 | 2528 | int i, j; |
5e0d2a6f | 2529 | |
5e0d2a6f | 2530 | timer_on = 0; |
2531 | ||
2532 | /* just flush them all */ | |
2533 | for (i = 0; i < g_num_of_iommus; i++) { | |
a2bb8459 WH |
2534 | struct intel_iommu *iommu = g_iommus[i]; |
2535 | if (!iommu) | |
2536 | continue; | |
c42d9f32 | 2537 | |
9dd2fe89 YZ |
2538 | if (!deferred_flush[i].next) |
2539 | continue; | |
2540 | ||
2541 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, | |
93a23a72 | 2542 | DMA_TLB_GLOBAL_FLUSH); |
9dd2fe89 | 2543 | for (j = 0; j < deferred_flush[i].next; j++) { |
93a23a72 YZ |
2544 | unsigned long mask; |
2545 | struct iova *iova = deferred_flush[i].iova[j]; | |
2546 | ||
2547 | mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT; | |
2548 | mask = ilog2(mask >> VTD_PAGE_SHIFT); | |
2549 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], | |
2550 | iova->pfn_lo << PAGE_SHIFT, mask); | |
2551 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); | |
80b20dd8 | 2552 | } |
9dd2fe89 | 2553 | deferred_flush[i].next = 0; |
5e0d2a6f | 2554 | } |
2555 | ||
5e0d2a6f | 2556 | list_size = 0; |
5e0d2a6f | 2557 | } |
2558 | ||
2559 | static void flush_unmaps_timeout(unsigned long data) | |
2560 | { | |
80b20dd8 | 2561 | unsigned long flags; |
2562 | ||
2563 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
5e0d2a6f | 2564 | flush_unmaps(); |
80b20dd8 | 2565 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
5e0d2a6f | 2566 | } |
2567 | ||
2568 | static void add_unmap(struct dmar_domain *dom, struct iova *iova) | |
2569 | { | |
2570 | unsigned long flags; | |
80b20dd8 | 2571 | int next, iommu_id; |
8c11e798 | 2572 | struct intel_iommu *iommu; |
5e0d2a6f | 2573 | |
2574 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
80b20dd8 | 2575 | if (list_size == HIGH_WATER_MARK) |
2576 | flush_unmaps(); | |
2577 | ||
8c11e798 WH |
2578 | iommu = domain_get_iommu(dom); |
2579 | iommu_id = iommu->seq_id; | |
c42d9f32 | 2580 | |
80b20dd8 | 2581 | next = deferred_flush[iommu_id].next; |
2582 | deferred_flush[iommu_id].domain[next] = dom; | |
2583 | deferred_flush[iommu_id].iova[next] = iova; | |
2584 | deferred_flush[iommu_id].next++; | |
5e0d2a6f | 2585 | |
2586 | if (!timer_on) { | |
2587 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); | |
2588 | timer_on = 1; | |
2589 | } | |
2590 | list_size++; | |
2591 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); | |
2592 | } | |
2593 | ||
ffbbef5c FT |
2594 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
2595 | size_t size, enum dma_data_direction dir, | |
2596 | struct dma_attrs *attrs) | |
ba395927 | 2597 | { |
ba395927 | 2598 | struct pci_dev *pdev = to_pci_dev(dev); |
f76aec76 | 2599 | struct dmar_domain *domain; |
d794dc9b | 2600 | unsigned long start_pfn, last_pfn; |
ba395927 | 2601 | struct iova *iova; |
8c11e798 | 2602 | struct intel_iommu *iommu; |
ba395927 | 2603 | |
2c2e2c38 | 2604 | if (iommu_no_mapping(pdev)) |
f76aec76 | 2605 | return; |
2c2e2c38 | 2606 | |
ba395927 KA |
2607 | domain = find_domain(pdev); |
2608 | BUG_ON(!domain); | |
2609 | ||
8c11e798 WH |
2610 | iommu = domain_get_iommu(domain); |
2611 | ||
ba395927 | 2612 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
f76aec76 | 2613 | if (!iova) |
ba395927 | 2614 | return; |
ba395927 | 2615 | |
d794dc9b DW |
2616 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
2617 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
ba395927 | 2618 | |
d794dc9b DW |
2619 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
2620 | pci_name(pdev), start_pfn, last_pfn); | |
ba395927 | 2621 | |
f76aec76 | 2622 | /* clear the whole page */ |
d794dc9b DW |
2623 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
2624 | ||
f76aec76 | 2625 | /* free page tables */ |
d794dc9b DW |
2626 | dma_pte_free_pagetable(domain, start_pfn, last_pfn); |
2627 | ||
5e0d2a6f | 2628 | if (intel_iommu_strict) { |
d794dc9b DW |
2629 | iommu_flush_iotlb_psi(iommu, domain->id, |
2630 | start_pfn << VTD_PAGE_SHIFT, | |
2631 | last_pfn - start_pfn + 1); | |
5e0d2a6f | 2632 | /* free iova */ |
2633 | __free_iova(&domain->iovad, iova); | |
2634 | } else { | |
2635 | add_unmap(domain, iova); | |
2636 | /* | |
2637 | * queue up the release of the unmap to save the 1/6th of the | |
2638 | * cpu used up by the iotlb flush operation... | |
2639 | */ | |
5e0d2a6f | 2640 | } |
ba395927 KA |
2641 | } |
2642 | ||
d7ab5c46 FT |
2643 | static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size, |
2644 | int dir) | |
ffbbef5c FT |
2645 | { |
2646 | intel_unmap_page(dev, dev_addr, size, dir, NULL); | |
2647 | } | |
2648 | ||
d7ab5c46 FT |
2649 | static void *intel_alloc_coherent(struct device *hwdev, size_t size, |
2650 | dma_addr_t *dma_handle, gfp_t flags) | |
ba395927 KA |
2651 | { |
2652 | void *vaddr; | |
2653 | int order; | |
2654 | ||
5b6985ce | 2655 | size = PAGE_ALIGN(size); |
ba395927 KA |
2656 | order = get_order(size); |
2657 | flags &= ~(GFP_DMA | GFP_DMA32); | |
2658 | ||
2659 | vaddr = (void *)__get_free_pages(flags, order); | |
2660 | if (!vaddr) | |
2661 | return NULL; | |
2662 | memset(vaddr, 0, size); | |
2663 | ||
bb9e6d65 FT |
2664 | *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size, |
2665 | DMA_BIDIRECTIONAL, | |
2666 | hwdev->coherent_dma_mask); | |
ba395927 KA |
2667 | if (*dma_handle) |
2668 | return vaddr; | |
2669 | free_pages((unsigned long)vaddr, order); | |
2670 | return NULL; | |
2671 | } | |
2672 | ||
d7ab5c46 FT |
2673 | static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr, |
2674 | dma_addr_t dma_handle) | |
ba395927 KA |
2675 | { |
2676 | int order; | |
2677 | ||
5b6985ce | 2678 | size = PAGE_ALIGN(size); |
ba395927 KA |
2679 | order = get_order(size); |
2680 | ||
2681 | intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL); | |
2682 | free_pages((unsigned long)vaddr, order); | |
2683 | } | |
2684 | ||
d7ab5c46 FT |
2685 | static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist, |
2686 | int nelems, enum dma_data_direction dir, | |
2687 | struct dma_attrs *attrs) | |
ba395927 | 2688 | { |
ba395927 KA |
2689 | struct pci_dev *pdev = to_pci_dev(hwdev); |
2690 | struct dmar_domain *domain; | |
d794dc9b | 2691 | unsigned long start_pfn, last_pfn; |
f76aec76 | 2692 | struct iova *iova; |
8c11e798 | 2693 | struct intel_iommu *iommu; |
ba395927 | 2694 | |
2c2e2c38 | 2695 | if (iommu_no_mapping(pdev)) |
ba395927 KA |
2696 | return; |
2697 | ||
2698 | domain = find_domain(pdev); | |
8c11e798 WH |
2699 | BUG_ON(!domain); |
2700 | ||
2701 | iommu = domain_get_iommu(domain); | |
ba395927 | 2702 | |
c03ab37c | 2703 | iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address)); |
f76aec76 KA |
2704 | if (!iova) |
2705 | return; | |
f76aec76 | 2706 | |
d794dc9b DW |
2707 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
2708 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
f76aec76 KA |
2709 | |
2710 | /* clear the whole page */ | |
d794dc9b DW |
2711 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
2712 | ||
f76aec76 | 2713 | /* free page tables */ |
d794dc9b | 2714 | dma_pte_free_pagetable(domain, start_pfn, last_pfn); |
f76aec76 | 2715 | |
d794dc9b DW |
2716 | iommu_flush_iotlb_psi(iommu, domain->id, |
2717 | start_pfn << VTD_PAGE_SHIFT, | |
2718 | (last_pfn - start_pfn + 1)); | |
f76aec76 KA |
2719 | |
2720 | /* free iova */ | |
2721 | __free_iova(&domain->iovad, iova); | |
ba395927 KA |
2722 | } |
2723 | ||
ba395927 | 2724 | static int intel_nontranslate_map_sg(struct device *hddev, |
c03ab37c | 2725 | struct scatterlist *sglist, int nelems, int dir) |
ba395927 KA |
2726 | { |
2727 | int i; | |
c03ab37c | 2728 | struct scatterlist *sg; |
ba395927 | 2729 | |
c03ab37c | 2730 | for_each_sg(sglist, sg, nelems, i) { |
12d4d40e | 2731 | BUG_ON(!sg_page(sg)); |
4cf2e75d | 2732 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
c03ab37c | 2733 | sg->dma_length = sg->length; |
ba395927 KA |
2734 | } |
2735 | return nelems; | |
2736 | } | |
2737 | ||
d7ab5c46 FT |
2738 | static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems, |
2739 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
ba395927 | 2740 | { |
4cf2e75d | 2741 | phys_addr_t addr; |
ba395927 | 2742 | int i; |
ba395927 KA |
2743 | struct pci_dev *pdev = to_pci_dev(hwdev); |
2744 | struct dmar_domain *domain; | |
f76aec76 KA |
2745 | size_t size = 0; |
2746 | int prot = 0; | |
2747 | size_t offset = 0; | |
2748 | struct iova *iova = NULL; | |
2749 | int ret; | |
c03ab37c | 2750 | struct scatterlist *sg; |
f76aec76 | 2751 | unsigned long start_addr; |
8c11e798 | 2752 | struct intel_iommu *iommu; |
ba395927 KA |
2753 | |
2754 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 | 2755 | if (iommu_no_mapping(pdev)) |
c03ab37c | 2756 | return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir); |
ba395927 | 2757 | |
f76aec76 KA |
2758 | domain = get_valid_domain_for_dev(pdev); |
2759 | if (!domain) | |
2760 | return 0; | |
2761 | ||
8c11e798 WH |
2762 | iommu = domain_get_iommu(domain); |
2763 | ||
c03ab37c | 2764 | for_each_sg(sglist, sg, nelems, i) { |
4cf2e75d | 2765 | addr = page_to_phys(sg_page(sg)) + sg->offset; |
f76aec76 KA |
2766 | size += aligned_size((u64)addr, sg->length); |
2767 | } | |
2768 | ||
bb9e6d65 | 2769 | iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask); |
f76aec76 | 2770 | if (!iova) { |
c03ab37c | 2771 | sglist->dma_length = 0; |
f76aec76 KA |
2772 | return 0; |
2773 | } | |
2774 | ||
2775 | /* | |
2776 | * Check if DMAR supports zero-length reads on write only | |
2777 | * mappings.. | |
2778 | */ | |
2779 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 2780 | !cap_zlr(iommu->cap)) |
f76aec76 KA |
2781 | prot |= DMA_PTE_READ; |
2782 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
2783 | prot |= DMA_PTE_WRITE; | |
2784 | ||
5b6985ce | 2785 | start_addr = iova->pfn_lo << PAGE_SHIFT; |
f76aec76 | 2786 | offset = 0; |
c03ab37c | 2787 | for_each_sg(sglist, sg, nelems, i) { |
4cf2e75d | 2788 | addr = page_to_phys(sg_page(sg)) + sg->offset; |
f76aec76 KA |
2789 | size = aligned_size((u64)addr, sg->length); |
2790 | ret = domain_page_mapping(domain, start_addr + offset, | |
fd18de50 DW |
2791 | ((u64)addr) & PHYSICAL_PAGE_MASK, |
2792 | size, prot); | |
f76aec76 KA |
2793 | if (ret) { |
2794 | /* clear the page */ | |
595badf5 DW |
2795 | dma_pte_clear_range(domain, |
2796 | start_addr >> VTD_PAGE_SHIFT, | |
2797 | (start_addr + offset - 1) >> VTD_PAGE_SHIFT); | |
f76aec76 | 2798 | /* free page tables */ |
d794dc9b DW |
2799 | dma_pte_free_pagetable(domain, start_addr >> VTD_PAGE_SHIFT, |
2800 | (start_addr + offset - 1) >> VTD_PAGE_SHIFT); | |
f76aec76 KA |
2801 | /* free iova */ |
2802 | __free_iova(&domain->iovad, iova); | |
ba395927 KA |
2803 | return 0; |
2804 | } | |
f76aec76 | 2805 | sg->dma_address = start_addr + offset + |
5b6985ce | 2806 | ((u64)addr & (~PAGE_MASK)); |
ba395927 | 2807 | sg->dma_length = sg->length; |
f76aec76 | 2808 | offset += size; |
ba395927 KA |
2809 | } |
2810 | ||
1f0ef2aa DW |
2811 | /* it's a non-present to present mapping. Only flush if caching mode */ |
2812 | if (cap_caching_mode(iommu->cap)) | |
2813 | iommu_flush_iotlb_psi(iommu, 0, start_addr, | |
2814 | offset >> VTD_PAGE_SHIFT); | |
2815 | else | |
8c11e798 | 2816 | iommu_flush_write_buffer(iommu); |
1f0ef2aa | 2817 | |
ba395927 KA |
2818 | return nelems; |
2819 | } | |
2820 | ||
dfb805e8 FT |
2821 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
2822 | { | |
2823 | return !dma_addr; | |
2824 | } | |
2825 | ||
160c1d8e | 2826 | struct dma_map_ops intel_dma_ops = { |
ba395927 KA |
2827 | .alloc_coherent = intel_alloc_coherent, |
2828 | .free_coherent = intel_free_coherent, | |
ba395927 KA |
2829 | .map_sg = intel_map_sg, |
2830 | .unmap_sg = intel_unmap_sg, | |
ffbbef5c FT |
2831 | .map_page = intel_map_page, |
2832 | .unmap_page = intel_unmap_page, | |
dfb805e8 | 2833 | .mapping_error = intel_mapping_error, |
ba395927 KA |
2834 | }; |
2835 | ||
2836 | static inline int iommu_domain_cache_init(void) | |
2837 | { | |
2838 | int ret = 0; | |
2839 | ||
2840 | iommu_domain_cache = kmem_cache_create("iommu_domain", | |
2841 | sizeof(struct dmar_domain), | |
2842 | 0, | |
2843 | SLAB_HWCACHE_ALIGN, | |
2844 | ||
2845 | NULL); | |
2846 | if (!iommu_domain_cache) { | |
2847 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); | |
2848 | ret = -ENOMEM; | |
2849 | } | |
2850 | ||
2851 | return ret; | |
2852 | } | |
2853 | ||
2854 | static inline int iommu_devinfo_cache_init(void) | |
2855 | { | |
2856 | int ret = 0; | |
2857 | ||
2858 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", | |
2859 | sizeof(struct device_domain_info), | |
2860 | 0, | |
2861 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
2862 | NULL); |
2863 | if (!iommu_devinfo_cache) { | |
2864 | printk(KERN_ERR "Couldn't create devinfo cache\n"); | |
2865 | ret = -ENOMEM; | |
2866 | } | |
2867 | ||
2868 | return ret; | |
2869 | } | |
2870 | ||
2871 | static inline int iommu_iova_cache_init(void) | |
2872 | { | |
2873 | int ret = 0; | |
2874 | ||
2875 | iommu_iova_cache = kmem_cache_create("iommu_iova", | |
2876 | sizeof(struct iova), | |
2877 | 0, | |
2878 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
2879 | NULL); |
2880 | if (!iommu_iova_cache) { | |
2881 | printk(KERN_ERR "Couldn't create iova cache\n"); | |
2882 | ret = -ENOMEM; | |
2883 | } | |
2884 | ||
2885 | return ret; | |
2886 | } | |
2887 | ||
2888 | static int __init iommu_init_mempool(void) | |
2889 | { | |
2890 | int ret; | |
2891 | ret = iommu_iova_cache_init(); | |
2892 | if (ret) | |
2893 | return ret; | |
2894 | ||
2895 | ret = iommu_domain_cache_init(); | |
2896 | if (ret) | |
2897 | goto domain_error; | |
2898 | ||
2899 | ret = iommu_devinfo_cache_init(); | |
2900 | if (!ret) | |
2901 | return ret; | |
2902 | ||
2903 | kmem_cache_destroy(iommu_domain_cache); | |
2904 | domain_error: | |
2905 | kmem_cache_destroy(iommu_iova_cache); | |
2906 | ||
2907 | return -ENOMEM; | |
2908 | } | |
2909 | ||
2910 | static void __init iommu_exit_mempool(void) | |
2911 | { | |
2912 | kmem_cache_destroy(iommu_devinfo_cache); | |
2913 | kmem_cache_destroy(iommu_domain_cache); | |
2914 | kmem_cache_destroy(iommu_iova_cache); | |
2915 | ||
2916 | } | |
2917 | ||
ba395927 KA |
2918 | static void __init init_no_remapping_devices(void) |
2919 | { | |
2920 | struct dmar_drhd_unit *drhd; | |
2921 | ||
2922 | for_each_drhd_unit(drhd) { | |
2923 | if (!drhd->include_all) { | |
2924 | int i; | |
2925 | for (i = 0; i < drhd->devices_cnt; i++) | |
2926 | if (drhd->devices[i] != NULL) | |
2927 | break; | |
2928 | /* ignore DMAR unit if no pci devices exist */ | |
2929 | if (i == drhd->devices_cnt) | |
2930 | drhd->ignored = 1; | |
2931 | } | |
2932 | } | |
2933 | ||
2934 | if (dmar_map_gfx) | |
2935 | return; | |
2936 | ||
2937 | for_each_drhd_unit(drhd) { | |
2938 | int i; | |
2939 | if (drhd->ignored || drhd->include_all) | |
2940 | continue; | |
2941 | ||
2942 | for (i = 0; i < drhd->devices_cnt; i++) | |
2943 | if (drhd->devices[i] && | |
2944 | !IS_GFX_DEVICE(drhd->devices[i])) | |
2945 | break; | |
2946 | ||
2947 | if (i < drhd->devices_cnt) | |
2948 | continue; | |
2949 | ||
2950 | /* bypass IOMMU if it is just for gfx devices */ | |
2951 | drhd->ignored = 1; | |
2952 | for (i = 0; i < drhd->devices_cnt; i++) { | |
2953 | if (!drhd->devices[i]) | |
2954 | continue; | |
358dd8ac | 2955 | drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
ba395927 KA |
2956 | } |
2957 | } | |
2958 | } | |
2959 | ||
f59c7b69 FY |
2960 | #ifdef CONFIG_SUSPEND |
2961 | static int init_iommu_hw(void) | |
2962 | { | |
2963 | struct dmar_drhd_unit *drhd; | |
2964 | struct intel_iommu *iommu = NULL; | |
2965 | ||
2966 | for_each_active_iommu(iommu, drhd) | |
2967 | if (iommu->qi) | |
2968 | dmar_reenable_qi(iommu); | |
2969 | ||
2970 | for_each_active_iommu(iommu, drhd) { | |
2971 | iommu_flush_write_buffer(iommu); | |
2972 | ||
2973 | iommu_set_root_entry(iommu); | |
2974 | ||
2975 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 2976 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 2977 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 2978 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
2979 | iommu_disable_protect_mem_regions(iommu); |
2980 | iommu_enable_translation(iommu); | |
2981 | } | |
2982 | ||
2983 | return 0; | |
2984 | } | |
2985 | ||
2986 | static void iommu_flush_all(void) | |
2987 | { | |
2988 | struct dmar_drhd_unit *drhd; | |
2989 | struct intel_iommu *iommu; | |
2990 | ||
2991 | for_each_active_iommu(iommu, drhd) { | |
2992 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 2993 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 2994 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 2995 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
2996 | } |
2997 | } | |
2998 | ||
2999 | static int iommu_suspend(struct sys_device *dev, pm_message_t state) | |
3000 | { | |
3001 | struct dmar_drhd_unit *drhd; | |
3002 | struct intel_iommu *iommu = NULL; | |
3003 | unsigned long flag; | |
3004 | ||
3005 | for_each_active_iommu(iommu, drhd) { | |
3006 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, | |
3007 | GFP_ATOMIC); | |
3008 | if (!iommu->iommu_state) | |
3009 | goto nomem; | |
3010 | } | |
3011 | ||
3012 | iommu_flush_all(); | |
3013 | ||
3014 | for_each_active_iommu(iommu, drhd) { | |
3015 | iommu_disable_translation(iommu); | |
3016 | ||
3017 | spin_lock_irqsave(&iommu->register_lock, flag); | |
3018 | ||
3019 | iommu->iommu_state[SR_DMAR_FECTL_REG] = | |
3020 | readl(iommu->reg + DMAR_FECTL_REG); | |
3021 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = | |
3022 | readl(iommu->reg + DMAR_FEDATA_REG); | |
3023 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = | |
3024 | readl(iommu->reg + DMAR_FEADDR_REG); | |
3025 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = | |
3026 | readl(iommu->reg + DMAR_FEUADDR_REG); | |
3027 | ||
3028 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
3029 | } | |
3030 | return 0; | |
3031 | ||
3032 | nomem: | |
3033 | for_each_active_iommu(iommu, drhd) | |
3034 | kfree(iommu->iommu_state); | |
3035 | ||
3036 | return -ENOMEM; | |
3037 | } | |
3038 | ||
3039 | static int iommu_resume(struct sys_device *dev) | |
3040 | { | |
3041 | struct dmar_drhd_unit *drhd; | |
3042 | struct intel_iommu *iommu = NULL; | |
3043 | unsigned long flag; | |
3044 | ||
3045 | if (init_iommu_hw()) { | |
3046 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); | |
3047 | return -EIO; | |
3048 | } | |
3049 | ||
3050 | for_each_active_iommu(iommu, drhd) { | |
3051 | ||
3052 | spin_lock_irqsave(&iommu->register_lock, flag); | |
3053 | ||
3054 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], | |
3055 | iommu->reg + DMAR_FECTL_REG); | |
3056 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], | |
3057 | iommu->reg + DMAR_FEDATA_REG); | |
3058 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], | |
3059 | iommu->reg + DMAR_FEADDR_REG); | |
3060 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], | |
3061 | iommu->reg + DMAR_FEUADDR_REG); | |
3062 | ||
3063 | spin_unlock_irqrestore(&iommu->register_lock, flag); | |
3064 | } | |
3065 | ||
3066 | for_each_active_iommu(iommu, drhd) | |
3067 | kfree(iommu->iommu_state); | |
3068 | ||
3069 | return 0; | |
3070 | } | |
3071 | ||
3072 | static struct sysdev_class iommu_sysclass = { | |
3073 | .name = "iommu", | |
3074 | .resume = iommu_resume, | |
3075 | .suspend = iommu_suspend, | |
3076 | }; | |
3077 | ||
3078 | static struct sys_device device_iommu = { | |
3079 | .cls = &iommu_sysclass, | |
3080 | }; | |
3081 | ||
3082 | static int __init init_iommu_sysfs(void) | |
3083 | { | |
3084 | int error; | |
3085 | ||
3086 | error = sysdev_class_register(&iommu_sysclass); | |
3087 | if (error) | |
3088 | return error; | |
3089 | ||
3090 | error = sysdev_register(&device_iommu); | |
3091 | if (error) | |
3092 | sysdev_class_unregister(&iommu_sysclass); | |
3093 | ||
3094 | return error; | |
3095 | } | |
3096 | ||
3097 | #else | |
3098 | static int __init init_iommu_sysfs(void) | |
3099 | { | |
3100 | return 0; | |
3101 | } | |
3102 | #endif /* CONFIG_PM */ | |
3103 | ||
ba395927 KA |
3104 | int __init intel_iommu_init(void) |
3105 | { | |
3106 | int ret = 0; | |
3107 | ||
ba395927 KA |
3108 | if (dmar_table_init()) |
3109 | return -ENODEV; | |
3110 | ||
1886e8a9 SS |
3111 | if (dmar_dev_scope_init()) |
3112 | return -ENODEV; | |
3113 | ||
2ae21010 SS |
3114 | /* |
3115 | * Check the need for DMA-remapping initialization now. | |
3116 | * Above initialization will also be used by Interrupt-remapping. | |
3117 | */ | |
4ed0d3e6 | 3118 | if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled) |
2ae21010 SS |
3119 | return -ENODEV; |
3120 | ||
ba395927 KA |
3121 | iommu_init_mempool(); |
3122 | dmar_init_reserved_ranges(); | |
3123 | ||
3124 | init_no_remapping_devices(); | |
3125 | ||
3126 | ret = init_dmars(); | |
3127 | if (ret) { | |
3128 | printk(KERN_ERR "IOMMU: dmar init failed\n"); | |
3129 | put_iova_domain(&reserved_iova_list); | |
3130 | iommu_exit_mempool(); | |
3131 | return ret; | |
3132 | } | |
3133 | printk(KERN_INFO | |
3134 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); | |
3135 | ||
5e0d2a6f | 3136 | init_timer(&unmap_timer); |
ba395927 | 3137 | force_iommu = 1; |
4ed0d3e6 FY |
3138 | |
3139 | if (!iommu_pass_through) { | |
3140 | printk(KERN_INFO | |
3141 | "Multi-level page-table translation for DMAR.\n"); | |
3142 | dma_ops = &intel_dma_ops; | |
3143 | } else | |
3144 | printk(KERN_INFO | |
3145 | "DMAR: Pass through translation for DMAR.\n"); | |
3146 | ||
f59c7b69 | 3147 | init_iommu_sysfs(); |
a8bcbb0d JR |
3148 | |
3149 | register_iommu(&intel_iommu_ops); | |
3150 | ||
ba395927 KA |
3151 | return 0; |
3152 | } | |
e820482c | 3153 | |
3199aa6b HW |
3154 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
3155 | struct pci_dev *pdev) | |
3156 | { | |
3157 | struct pci_dev *tmp, *parent; | |
3158 | ||
3159 | if (!iommu || !pdev) | |
3160 | return; | |
3161 | ||
3162 | /* dependent device detach */ | |
3163 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
3164 | /* Secondary interface's bus number and devfn 0 */ | |
3165 | if (tmp) { | |
3166 | parent = pdev->bus->self; | |
3167 | while (parent != tmp) { | |
3168 | iommu_detach_dev(iommu, parent->bus->number, | |
276dbf99 | 3169 | parent->devfn); |
3199aa6b HW |
3170 | parent = parent->bus->self; |
3171 | } | |
3172 | if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */ | |
3173 | iommu_detach_dev(iommu, | |
3174 | tmp->subordinate->number, 0); | |
3175 | else /* this is a legacy PCI bridge */ | |
276dbf99 DW |
3176 | iommu_detach_dev(iommu, tmp->bus->number, |
3177 | tmp->devfn); | |
3199aa6b HW |
3178 | } |
3179 | } | |
3180 | ||
2c2e2c38 | 3181 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
c7151a8d WH |
3182 | struct pci_dev *pdev) |
3183 | { | |
3184 | struct device_domain_info *info; | |
3185 | struct intel_iommu *iommu; | |
3186 | unsigned long flags; | |
3187 | int found = 0; | |
3188 | struct list_head *entry, *tmp; | |
3189 | ||
276dbf99 DW |
3190 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
3191 | pdev->devfn); | |
c7151a8d WH |
3192 | if (!iommu) |
3193 | return; | |
3194 | ||
3195 | spin_lock_irqsave(&device_domain_lock, flags); | |
3196 | list_for_each_safe(entry, tmp, &domain->devices) { | |
3197 | info = list_entry(entry, struct device_domain_info, link); | |
276dbf99 | 3198 | /* No need to compare PCI domain; it has to be the same */ |
c7151a8d WH |
3199 | if (info->bus == pdev->bus->number && |
3200 | info->devfn == pdev->devfn) { | |
3201 | list_del(&info->link); | |
3202 | list_del(&info->global); | |
3203 | if (info->dev) | |
3204 | info->dev->dev.archdata.iommu = NULL; | |
3205 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
3206 | ||
93a23a72 | 3207 | iommu_disable_dev_iotlb(info); |
c7151a8d | 3208 | iommu_detach_dev(iommu, info->bus, info->devfn); |
3199aa6b | 3209 | iommu_detach_dependent_devices(iommu, pdev); |
c7151a8d WH |
3210 | free_devinfo_mem(info); |
3211 | ||
3212 | spin_lock_irqsave(&device_domain_lock, flags); | |
3213 | ||
3214 | if (found) | |
3215 | break; | |
3216 | else | |
3217 | continue; | |
3218 | } | |
3219 | ||
3220 | /* if there is no other devices under the same iommu | |
3221 | * owned by this domain, clear this iommu in iommu_bmp | |
3222 | * update iommu count and coherency | |
3223 | */ | |
276dbf99 DW |
3224 | if (iommu == device_to_iommu(info->segment, info->bus, |
3225 | info->devfn)) | |
c7151a8d WH |
3226 | found = 1; |
3227 | } | |
3228 | ||
3229 | if (found == 0) { | |
3230 | unsigned long tmp_flags; | |
3231 | spin_lock_irqsave(&domain->iommu_lock, tmp_flags); | |
3232 | clear_bit(iommu->seq_id, &domain->iommu_bmp); | |
3233 | domain->iommu_count--; | |
58c610bd | 3234 | domain_update_iommu_cap(domain); |
c7151a8d WH |
3235 | spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags); |
3236 | } | |
3237 | ||
3238 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
3239 | } | |
3240 | ||
3241 | static void vm_domain_remove_all_dev_info(struct dmar_domain *domain) | |
3242 | { | |
3243 | struct device_domain_info *info; | |
3244 | struct intel_iommu *iommu; | |
3245 | unsigned long flags1, flags2; | |
3246 | ||
3247 | spin_lock_irqsave(&device_domain_lock, flags1); | |
3248 | while (!list_empty(&domain->devices)) { | |
3249 | info = list_entry(domain->devices.next, | |
3250 | struct device_domain_info, link); | |
3251 | list_del(&info->link); | |
3252 | list_del(&info->global); | |
3253 | if (info->dev) | |
3254 | info->dev->dev.archdata.iommu = NULL; | |
3255 | ||
3256 | spin_unlock_irqrestore(&device_domain_lock, flags1); | |
3257 | ||
93a23a72 | 3258 | iommu_disable_dev_iotlb(info); |
276dbf99 | 3259 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
c7151a8d | 3260 | iommu_detach_dev(iommu, info->bus, info->devfn); |
3199aa6b | 3261 | iommu_detach_dependent_devices(iommu, info->dev); |
c7151a8d WH |
3262 | |
3263 | /* clear this iommu in iommu_bmp, update iommu count | |
58c610bd | 3264 | * and capabilities |
c7151a8d WH |
3265 | */ |
3266 | spin_lock_irqsave(&domain->iommu_lock, flags2); | |
3267 | if (test_and_clear_bit(iommu->seq_id, | |
3268 | &domain->iommu_bmp)) { | |
3269 | domain->iommu_count--; | |
58c610bd | 3270 | domain_update_iommu_cap(domain); |
c7151a8d WH |
3271 | } |
3272 | spin_unlock_irqrestore(&domain->iommu_lock, flags2); | |
3273 | ||
3274 | free_devinfo_mem(info); | |
3275 | spin_lock_irqsave(&device_domain_lock, flags1); | |
3276 | } | |
3277 | spin_unlock_irqrestore(&device_domain_lock, flags1); | |
3278 | } | |
3279 | ||
5e98c4b1 WH |
3280 | /* domain id for virtual machine, it won't be set in context */ |
3281 | static unsigned long vm_domid; | |
3282 | ||
fe40f1e0 WH |
3283 | static int vm_domain_min_agaw(struct dmar_domain *domain) |
3284 | { | |
3285 | int i; | |
3286 | int min_agaw = domain->agaw; | |
3287 | ||
3288 | i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus); | |
3289 | for (; i < g_num_of_iommus; ) { | |
3290 | if (min_agaw > g_iommus[i]->agaw) | |
3291 | min_agaw = g_iommus[i]->agaw; | |
3292 | ||
3293 | i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1); | |
3294 | } | |
3295 | ||
3296 | return min_agaw; | |
3297 | } | |
3298 | ||
5e98c4b1 WH |
3299 | static struct dmar_domain *iommu_alloc_vm_domain(void) |
3300 | { | |
3301 | struct dmar_domain *domain; | |
3302 | ||
3303 | domain = alloc_domain_mem(); | |
3304 | if (!domain) | |
3305 | return NULL; | |
3306 | ||
3307 | domain->id = vm_domid++; | |
3308 | memset(&domain->iommu_bmp, 0, sizeof(unsigned long)); | |
3309 | domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE; | |
3310 | ||
3311 | return domain; | |
3312 | } | |
3313 | ||
2c2e2c38 | 3314 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
5e98c4b1 WH |
3315 | { |
3316 | int adjust_width; | |
3317 | ||
3318 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); | |
3319 | spin_lock_init(&domain->mapping_lock); | |
3320 | spin_lock_init(&domain->iommu_lock); | |
3321 | ||
3322 | domain_reserve_special_ranges(domain); | |
3323 | ||
3324 | /* calculate AGAW */ | |
3325 | domain->gaw = guest_width; | |
3326 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
3327 | domain->agaw = width_to_agaw(adjust_width); | |
3328 | ||
3329 | INIT_LIST_HEAD(&domain->devices); | |
3330 | ||
3331 | domain->iommu_count = 0; | |
3332 | domain->iommu_coherency = 0; | |
fe40f1e0 | 3333 | domain->max_addr = 0; |
5e98c4b1 WH |
3334 | |
3335 | /* always allocate the top pgd */ | |
3336 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(); | |
3337 | if (!domain->pgd) | |
3338 | return -ENOMEM; | |
3339 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); | |
3340 | return 0; | |
3341 | } | |
3342 | ||
3343 | static void iommu_free_vm_domain(struct dmar_domain *domain) | |
3344 | { | |
3345 | unsigned long flags; | |
3346 | struct dmar_drhd_unit *drhd; | |
3347 | struct intel_iommu *iommu; | |
3348 | unsigned long i; | |
3349 | unsigned long ndomains; | |
3350 | ||
3351 | for_each_drhd_unit(drhd) { | |
3352 | if (drhd->ignored) | |
3353 | continue; | |
3354 | iommu = drhd->iommu; | |
3355 | ||
3356 | ndomains = cap_ndoms(iommu->cap); | |
3357 | i = find_first_bit(iommu->domain_ids, ndomains); | |
3358 | for (; i < ndomains; ) { | |
3359 | if (iommu->domains[i] == domain) { | |
3360 | spin_lock_irqsave(&iommu->lock, flags); | |
3361 | clear_bit(i, iommu->domain_ids); | |
3362 | iommu->domains[i] = NULL; | |
3363 | spin_unlock_irqrestore(&iommu->lock, flags); | |
3364 | break; | |
3365 | } | |
3366 | i = find_next_bit(iommu->domain_ids, ndomains, i+1); | |
3367 | } | |
3368 | } | |
3369 | } | |
3370 | ||
3371 | static void vm_domain_exit(struct dmar_domain *domain) | |
3372 | { | |
5e98c4b1 WH |
3373 | /* Domain 0 is reserved, so dont process it */ |
3374 | if (!domain) | |
3375 | return; | |
3376 | ||
3377 | vm_domain_remove_all_dev_info(domain); | |
3378 | /* destroy iovas */ | |
3379 | put_iova_domain(&domain->iovad); | |
5e98c4b1 WH |
3380 | |
3381 | /* clear ptes */ | |
595badf5 | 3382 | dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
5e98c4b1 WH |
3383 | |
3384 | /* free page tables */ | |
d794dc9b | 3385 | dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
5e98c4b1 WH |
3386 | |
3387 | iommu_free_vm_domain(domain); | |
3388 | free_domain_mem(domain); | |
3389 | } | |
3390 | ||
5d450806 | 3391 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
38717946 | 3392 | { |
5d450806 | 3393 | struct dmar_domain *dmar_domain; |
38717946 | 3394 | |
5d450806 JR |
3395 | dmar_domain = iommu_alloc_vm_domain(); |
3396 | if (!dmar_domain) { | |
38717946 | 3397 | printk(KERN_ERR |
5d450806 JR |
3398 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
3399 | return -ENOMEM; | |
38717946 | 3400 | } |
2c2e2c38 | 3401 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
38717946 | 3402 | printk(KERN_ERR |
5d450806 JR |
3403 | "intel_iommu_domain_init() failed\n"); |
3404 | vm_domain_exit(dmar_domain); | |
3405 | return -ENOMEM; | |
38717946 | 3406 | } |
5d450806 | 3407 | domain->priv = dmar_domain; |
faa3d6f5 | 3408 | |
5d450806 | 3409 | return 0; |
38717946 | 3410 | } |
38717946 | 3411 | |
5d450806 | 3412 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
38717946 | 3413 | { |
5d450806 JR |
3414 | struct dmar_domain *dmar_domain = domain->priv; |
3415 | ||
3416 | domain->priv = NULL; | |
3417 | vm_domain_exit(dmar_domain); | |
38717946 | 3418 | } |
38717946 | 3419 | |
4c5478c9 JR |
3420 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
3421 | struct device *dev) | |
38717946 | 3422 | { |
4c5478c9 JR |
3423 | struct dmar_domain *dmar_domain = domain->priv; |
3424 | struct pci_dev *pdev = to_pci_dev(dev); | |
fe40f1e0 WH |
3425 | struct intel_iommu *iommu; |
3426 | int addr_width; | |
3427 | u64 end; | |
faa3d6f5 WH |
3428 | int ret; |
3429 | ||
3430 | /* normally pdev is not mapped */ | |
3431 | if (unlikely(domain_context_mapped(pdev))) { | |
3432 | struct dmar_domain *old_domain; | |
3433 | ||
3434 | old_domain = find_domain(pdev); | |
3435 | if (old_domain) { | |
2c2e2c38 FY |
3436 | if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
3437 | dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) | |
3438 | domain_remove_one_dev_info(old_domain, pdev); | |
faa3d6f5 WH |
3439 | else |
3440 | domain_remove_dev_info(old_domain); | |
3441 | } | |
3442 | } | |
3443 | ||
276dbf99 DW |
3444 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
3445 | pdev->devfn); | |
fe40f1e0 WH |
3446 | if (!iommu) |
3447 | return -ENODEV; | |
3448 | ||
3449 | /* check if this iommu agaw is sufficient for max mapped address */ | |
3450 | addr_width = agaw_to_width(iommu->agaw); | |
3451 | end = DOMAIN_MAX_ADDR(addr_width); | |
3452 | end = end & VTD_PAGE_MASK; | |
4c5478c9 | 3453 | if (end < dmar_domain->max_addr) { |
fe40f1e0 WH |
3454 | printk(KERN_ERR "%s: iommu agaw (%d) is not " |
3455 | "sufficient for the mapped address (%llx)\n", | |
4c5478c9 | 3456 | __func__, iommu->agaw, dmar_domain->max_addr); |
fe40f1e0 WH |
3457 | return -EFAULT; |
3458 | } | |
3459 | ||
2c2e2c38 | 3460 | ret = domain_add_dev_info(dmar_domain, pdev); |
faa3d6f5 WH |
3461 | if (ret) |
3462 | return ret; | |
3463 | ||
93a23a72 | 3464 | ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
faa3d6f5 | 3465 | return ret; |
38717946 | 3466 | } |
38717946 | 3467 | |
4c5478c9 JR |
3468 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
3469 | struct device *dev) | |
38717946 | 3470 | { |
4c5478c9 JR |
3471 | struct dmar_domain *dmar_domain = domain->priv; |
3472 | struct pci_dev *pdev = to_pci_dev(dev); | |
3473 | ||
2c2e2c38 | 3474 | domain_remove_one_dev_info(dmar_domain, pdev); |
faa3d6f5 | 3475 | } |
c7151a8d | 3476 | |
dde57a21 JR |
3477 | static int intel_iommu_map_range(struct iommu_domain *domain, |
3478 | unsigned long iova, phys_addr_t hpa, | |
3479 | size_t size, int iommu_prot) | |
faa3d6f5 | 3480 | { |
dde57a21 | 3481 | struct dmar_domain *dmar_domain = domain->priv; |
fe40f1e0 WH |
3482 | u64 max_addr; |
3483 | int addr_width; | |
dde57a21 | 3484 | int prot = 0; |
faa3d6f5 | 3485 | int ret; |
fe40f1e0 | 3486 | |
dde57a21 JR |
3487 | if (iommu_prot & IOMMU_READ) |
3488 | prot |= DMA_PTE_READ; | |
3489 | if (iommu_prot & IOMMU_WRITE) | |
3490 | prot |= DMA_PTE_WRITE; | |
9cf06697 SY |
3491 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
3492 | prot |= DMA_PTE_SNP; | |
dde57a21 | 3493 | |
fe40f1e0 | 3494 | max_addr = (iova & VTD_PAGE_MASK) + VTD_PAGE_ALIGN(size); |
dde57a21 | 3495 | if (dmar_domain->max_addr < max_addr) { |
fe40f1e0 WH |
3496 | int min_agaw; |
3497 | u64 end; | |
3498 | ||
3499 | /* check if minimum agaw is sufficient for mapped address */ | |
dde57a21 | 3500 | min_agaw = vm_domain_min_agaw(dmar_domain); |
fe40f1e0 WH |
3501 | addr_width = agaw_to_width(min_agaw); |
3502 | end = DOMAIN_MAX_ADDR(addr_width); | |
3503 | end = end & VTD_PAGE_MASK; | |
3504 | if (end < max_addr) { | |
3505 | printk(KERN_ERR "%s: iommu agaw (%d) is not " | |
3506 | "sufficient for the mapped address (%llx)\n", | |
3507 | __func__, min_agaw, max_addr); | |
3508 | return -EFAULT; | |
3509 | } | |
dde57a21 | 3510 | dmar_domain->max_addr = max_addr; |
fe40f1e0 WH |
3511 | } |
3512 | ||
dde57a21 | 3513 | ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot); |
faa3d6f5 | 3514 | return ret; |
38717946 | 3515 | } |
38717946 | 3516 | |
dde57a21 JR |
3517 | static void intel_iommu_unmap_range(struct iommu_domain *domain, |
3518 | unsigned long iova, size_t size) | |
38717946 | 3519 | { |
dde57a21 | 3520 | struct dmar_domain *dmar_domain = domain->priv; |
faa3d6f5 WH |
3521 | dma_addr_t base; |
3522 | ||
3523 | /* The address might not be aligned */ | |
3524 | base = iova & VTD_PAGE_MASK; | |
3525 | size = VTD_PAGE_ALIGN(size); | |
595badf5 DW |
3526 | dma_pte_clear_range(dmar_domain, base >> VTD_PAGE_SHIFT, |
3527 | (base + size - 1) >> VTD_PAGE_SHIFT); | |
fe40f1e0 | 3528 | |
dde57a21 JR |
3529 | if (dmar_domain->max_addr == base + size) |
3530 | dmar_domain->max_addr = base; | |
38717946 | 3531 | } |
38717946 | 3532 | |
d14d6577 JR |
3533 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
3534 | unsigned long iova) | |
38717946 | 3535 | { |
d14d6577 | 3536 | struct dmar_domain *dmar_domain = domain->priv; |
38717946 | 3537 | struct dma_pte *pte; |
faa3d6f5 | 3538 | u64 phys = 0; |
38717946 | 3539 | |
d14d6577 | 3540 | pte = addr_to_dma_pte(dmar_domain, iova); |
38717946 | 3541 | if (pte) |
faa3d6f5 | 3542 | phys = dma_pte_addr(pte); |
38717946 | 3543 | |
faa3d6f5 | 3544 | return phys; |
38717946 | 3545 | } |
a8bcbb0d | 3546 | |
dbb9fd86 SY |
3547 | static int intel_iommu_domain_has_cap(struct iommu_domain *domain, |
3548 | unsigned long cap) | |
3549 | { | |
3550 | struct dmar_domain *dmar_domain = domain->priv; | |
3551 | ||
3552 | if (cap == IOMMU_CAP_CACHE_COHERENCY) | |
3553 | return dmar_domain->iommu_snooping; | |
3554 | ||
3555 | return 0; | |
3556 | } | |
3557 | ||
a8bcbb0d JR |
3558 | static struct iommu_ops intel_iommu_ops = { |
3559 | .domain_init = intel_iommu_domain_init, | |
3560 | .domain_destroy = intel_iommu_domain_destroy, | |
3561 | .attach_dev = intel_iommu_attach_device, | |
3562 | .detach_dev = intel_iommu_detach_device, | |
3563 | .map = intel_iommu_map_range, | |
3564 | .unmap = intel_iommu_unmap_range, | |
3565 | .iova_to_phys = intel_iommu_iova_to_phys, | |
dbb9fd86 | 3566 | .domain_has_cap = intel_iommu_domain_has_cap, |
a8bcbb0d | 3567 | }; |
9af88143 DW |
3568 | |
3569 | static void __devinit quirk_iommu_rwbf(struct pci_dev *dev) | |
3570 | { | |
3571 | /* | |
3572 | * Mobile 4 Series Chipset neglects to set RWBF capability, | |
3573 | * but needs it: | |
3574 | */ | |
3575 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); | |
3576 | rwbf_quirk = 1; | |
3577 | } | |
3578 | ||
3579 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |