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ba395927 KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
ba395927 KA |
20 | */ |
21 | ||
22 | #ifndef _INTEL_IOMMU_H_ | |
23 | #define _INTEL_IOMMU_H_ | |
24 | ||
25 | #include <linux/types.h> | |
26 | #include <linux/msi.h> | |
f661197e | 27 | #include <linux/sysdev.h> |
ba395927 KA |
28 | #include "iova.h" |
29 | #include <linux/io.h> | |
fe962e90 | 30 | #include <asm/cacheflush.h> |
e61d98d8 | 31 | #include "dma_remapping.h" |
f661197e | 32 | |
ba395927 KA |
33 | /* |
34 | * Intel IOMMU register specification per version 1.0 public spec. | |
35 | */ | |
36 | ||
37 | #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ | |
38 | #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ | |
39 | #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ | |
40 | #define DMAR_GCMD_REG 0x18 /* Global command register */ | |
41 | #define DMAR_GSTS_REG 0x1c /* Global status register */ | |
42 | #define DMAR_RTADDR_REG 0x20 /* Root entry table */ | |
43 | #define DMAR_CCMD_REG 0x28 /* Context command reg */ | |
44 | #define DMAR_FSTS_REG 0x34 /* Fault Status register */ | |
45 | #define DMAR_FECTL_REG 0x38 /* Fault control register */ | |
46 | #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ | |
47 | #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ | |
48 | #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ | |
49 | #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ | |
50 | #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ | |
51 | #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ | |
52 | #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ | |
53 | #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ | |
54 | #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ | |
fe962e90 SS |
55 | #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */ |
56 | #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ | |
57 | #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ | |
58 | #define DMAR_ICS_REG 0x98 /* Invalidation complete status register */ | |
ba395927 KA |
59 | |
60 | #define OFFSET_STRIDE (9) | |
61 | /* | |
62 | #define dmar_readl(dmar, reg) readl(dmar + reg) | |
63 | #define dmar_readq(dmar, reg) ({ \ | |
64 | u32 lo, hi; \ | |
65 | lo = readl(dmar + reg); \ | |
66 | hi = readl(dmar + reg + 4); \ | |
67 | (((u64) hi) << 32) + lo; }) | |
68 | */ | |
4fe05bbc | 69 | static inline u64 dmar_readq(void __iomem *addr) |
ba395927 KA |
70 | { |
71 | u32 lo, hi; | |
72 | lo = readl(addr); | |
73 | hi = readl(addr + 4); | |
74 | return (((u64) hi) << 32) + lo; | |
75 | } | |
76 | ||
77 | static inline void dmar_writeq(void __iomem *addr, u64 val) | |
78 | { | |
79 | writel((u32)val, addr); | |
80 | writel((u32)(val >> 32), addr + 4); | |
81 | } | |
82 | ||
83 | #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) | |
84 | #define DMAR_VER_MINOR(v) ((v) & 0x0f) | |
85 | ||
86 | /* | |
87 | * Decoding Capability Register | |
88 | */ | |
89 | #define cap_read_drain(c) (((c) >> 55) & 1) | |
90 | #define cap_write_drain(c) (((c) >> 54) & 1) | |
91 | #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) | |
92 | #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) | |
93 | #define cap_pgsel_inv(c) (((c) >> 39) & 1) | |
94 | ||
95 | #define cap_super_page_val(c) (((c) >> 34) & 0xf) | |
96 | #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ | |
97 | * OFFSET_STRIDE) + 21) | |
98 | ||
99 | #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) | |
100 | #define cap_max_fault_reg_offset(c) \ | |
101 | (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) | |
102 | ||
103 | #define cap_zlr(c) (((c) >> 22) & 1) | |
104 | #define cap_isoch(c) (((c) >> 23) & 1) | |
105 | #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) | |
106 | #define cap_sagaw(c) (((c) >> 8) & 0x1f) | |
107 | #define cap_caching_mode(c) (((c) >> 7) & 1) | |
108 | #define cap_phmr(c) (((c) >> 6) & 1) | |
109 | #define cap_plmr(c) (((c) >> 5) & 1) | |
110 | #define cap_rwbf(c) (((c) >> 4) & 1) | |
111 | #define cap_afl(c) (((c) >> 3) & 1) | |
112 | #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) | |
113 | /* | |
114 | * Extended Capability Register | |
115 | */ | |
116 | ||
117 | #define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1) | |
118 | #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) | |
119 | #define ecap_max_iotlb_offset(e) \ | |
120 | (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16) | |
121 | #define ecap_coherent(e) ((e) & 0x1) | |
fe962e90 | 122 | #define ecap_qis(e) ((e) & 0x2) |
ad3ad3f6 SS |
123 | #define ecap_eim_support(e) ((e >> 4) & 0x1) |
124 | #define ecap_ir_support(e) ((e >> 3) & 0x1) | |
ba395927 KA |
125 | |
126 | ||
127 | /* IOTLB_REG */ | |
128 | #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) | |
129 | #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) | |
130 | #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) | |
131 | #define DMA_TLB_IIRG(type) ((type >> 60) & 7) | |
132 | #define DMA_TLB_IAIG(val) (((val) >> 57) & 7) | |
133 | #define DMA_TLB_READ_DRAIN (((u64)1) << 49) | |
134 | #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) | |
135 | #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) | |
136 | #define DMA_TLB_IVT (((u64)1) << 63) | |
137 | #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) | |
138 | #define DMA_TLB_MAX_SIZE (0x3f) | |
139 | ||
fe962e90 SS |
140 | /* INVALID_DESC */ |
141 | #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3) | |
142 | #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3) | |
143 | #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3) | |
144 | #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) | |
145 | #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) | |
146 | #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) | |
147 | #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6) | |
148 | #define DMA_ID_TLB_ADDR(addr) (addr) | |
149 | #define DMA_ID_TLB_ADDR_MASK(mask) (mask) | |
150 | ||
f8bab735 | 151 | /* PMEN_REG */ |
152 | #define DMA_PMEN_EPM (((u32)1)<<31) | |
153 | #define DMA_PMEN_PRS (((u32)1)<<0) | |
154 | ||
ba395927 KA |
155 | /* GCMD_REG */ |
156 | #define DMA_GCMD_TE (((u32)1) << 31) | |
157 | #define DMA_GCMD_SRTP (((u32)1) << 30) | |
158 | #define DMA_GCMD_SFL (((u32)1) << 29) | |
159 | #define DMA_GCMD_EAFL (((u32)1) << 28) | |
fe962e90 | 160 | #define DMA_GCMD_QIE (((u32)1) << 26) |
ba395927 KA |
161 | #define DMA_GCMD_WBF (((u32)1) << 27) |
162 | ||
163 | /* GSTS_REG */ | |
164 | #define DMA_GSTS_TES (((u32)1) << 31) | |
165 | #define DMA_GSTS_RTPS (((u32)1) << 30) | |
166 | #define DMA_GSTS_FLS (((u32)1) << 29) | |
167 | #define DMA_GSTS_AFLS (((u32)1) << 28) | |
fe962e90 | 168 | #define DMA_GSTS_QIES (((u32)1) << 26) |
ba395927 KA |
169 | #define DMA_GSTS_WBFS (((u32)1) << 27) |
170 | ||
171 | /* CCMD_REG */ | |
172 | #define DMA_CCMD_ICC (((u64)1) << 63) | |
173 | #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) | |
174 | #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) | |
175 | #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) | |
176 | #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) | |
177 | #define DMA_CCMD_MASK_NOBIT 0 | |
178 | #define DMA_CCMD_MASK_1BIT 1 | |
179 | #define DMA_CCMD_MASK_2BIT 2 | |
180 | #define DMA_CCMD_MASK_3BIT 3 | |
181 | #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) | |
182 | #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) | |
183 | ||
184 | /* FECTL_REG */ | |
185 | #define DMA_FECTL_IM (((u32)1) << 31) | |
186 | ||
187 | /* FSTS_REG */ | |
188 | #define DMA_FSTS_PPF ((u32)2) | |
189 | #define DMA_FSTS_PFO ((u32)1) | |
190 | #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) | |
191 | ||
192 | /* FRCD_REG, 32 bits access */ | |
193 | #define DMA_FRCD_F (((u32)1) << 31) | |
194 | #define dma_frcd_type(d) ((d >> 30) & 1) | |
195 | #define dma_frcd_fault_reason(c) (c & 0xff) | |
196 | #define dma_frcd_source_id(c) (c & 0xffff) | |
197 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */ | |
198 | ||
cf1337f0 SS |
199 | #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */ |
200 | ||
201 | #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ | |
202 | {\ | |
203 | cycles_t start_time = get_cycles();\ | |
204 | while (1) {\ | |
205 | sts = op (iommu->reg + offset);\ | |
206 | if (cond)\ | |
207 | break;\ | |
208 | if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ | |
209 | panic("DMAR hardware is malfunctioning\n");\ | |
210 | cpu_relax();\ | |
211 | }\ | |
212 | } | |
213 | ||
fe962e90 SS |
214 | #define QI_LENGTH 256 /* queue length */ |
215 | ||
216 | enum { | |
217 | QI_FREE, | |
218 | QI_IN_USE, | |
219 | QI_DONE | |
220 | }; | |
221 | ||
222 | #define QI_CC_TYPE 0x1 | |
223 | #define QI_IOTLB_TYPE 0x2 | |
224 | #define QI_DIOTLB_TYPE 0x3 | |
225 | #define QI_IEC_TYPE 0x4 | |
226 | #define QI_IWD_TYPE 0x5 | |
227 | ||
228 | #define QI_IEC_SELECTIVE (((u64)1) << 4) | |
229 | #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32)) | |
230 | #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27)) | |
231 | ||
232 | #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32) | |
233 | #define QI_IWD_STATUS_WRITE (((u64)1) << 5) | |
234 | ||
235 | struct qi_desc { | |
236 | u64 low, high; | |
237 | }; | |
238 | ||
239 | struct q_inval { | |
240 | spinlock_t q_lock; | |
241 | struct qi_desc *desc; /* invalidation queue */ | |
242 | int *desc_status; /* desc status */ | |
243 | int free_head; /* first free entry */ | |
244 | int free_tail; /* last free entry */ | |
245 | int free_cnt; | |
246 | }; | |
247 | ||
ba395927 KA |
248 | struct intel_iommu { |
249 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
250 | u64 cap; | |
251 | u64 ecap; | |
ba395927 KA |
252 | int seg; |
253 | u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ | |
ba395927 | 254 | spinlock_t register_lock; /* protect register handling */ |
c42d9f32 | 255 | int seq_id; /* sequence id of the iommu */ |
e61d98d8 SS |
256 | |
257 | #ifdef CONFIG_DMAR | |
258 | unsigned long *domain_ids; /* bitmap of domains */ | |
259 | struct dmar_domain **domains; /* ptr to domains */ | |
260 | spinlock_t lock; /* protect context, domain ids */ | |
ba395927 KA |
261 | struct root_entry *root_entry; /* virtual address */ |
262 | ||
263 | unsigned int irq; | |
264 | unsigned char name[7]; /* Device Name */ | |
265 | struct msi_msg saved_msg; | |
266 | struct sys_device sysdev; | |
e61d98d8 | 267 | #endif |
fe962e90 | 268 | struct q_inval *qi; /* Queued invalidation info */ |
ba395927 KA |
269 | }; |
270 | ||
fe962e90 SS |
271 | static inline void __iommu_flush_cache( |
272 | struct intel_iommu *iommu, void *addr, int size) | |
273 | { | |
274 | if (!ecap_coherent(iommu->ecap)) | |
275 | clflush_cache_range(addr, size); | |
276 | } | |
277 | ||
e61d98d8 SS |
278 | extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev); |
279 | ||
1886e8a9 | 280 | extern int alloc_iommu(struct dmar_drhd_unit *drhd); |
e61d98d8 | 281 | extern void free_iommu(struct intel_iommu *iommu); |
e820482c | 282 | |
ba395927 | 283 | #endif |