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Commit | Line | Data |
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5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 SS |
3 | #include <linux/spinlock.h> |
4 | #include <linux/jiffies.h> | |
5 | #include <linux/pci.h> | |
b6fcb33a | 6 | #include <linux/irq.h> |
ad3ad3f6 | 7 | #include <asm/io_apic.h> |
17483a1f | 8 | #include <asm/smp.h> |
6d652ea1 | 9 | #include <asm/cpu.h> |
38717946 | 10 | #include <linux/intel-iommu.h> |
ad3ad3f6 SS |
11 | #include "intr_remapping.h" |
12 | ||
13 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; | |
14 | static int ir_ioapic_num; | |
2ae21010 SS |
15 | int intr_remapping_enabled; |
16 | ||
5aeecaf4 | 17 | struct irq_2_iommu { |
b6fcb33a SS |
18 | struct intel_iommu *iommu; |
19 | u16 irte_index; | |
20 | u16 sub_handle; | |
21 | u8 irte_mask; | |
5aeecaf4 YL |
22 | }; |
23 | ||
0b8f1efa YL |
24 | #ifdef CONFIG_SPARSE_IRQ |
25 | static struct irq_2_iommu *get_one_free_irq_2_iommu(int cpu) | |
26 | { | |
27 | struct irq_2_iommu *iommu; | |
28 | int node; | |
29 | ||
30 | node = cpu_to_node(cpu); | |
31 | ||
32 | iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node); | |
33 | printk(KERN_DEBUG "alloc irq_2_iommu on cpu %d node %d\n", cpu, node); | |
34 | ||
35 | return iommu; | |
36 | } | |
e420dfb4 YL |
37 | |
38 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) | |
39 | { | |
0b8f1efa YL |
40 | struct irq_desc *desc; |
41 | ||
42 | desc = irq_to_desc(irq); | |
43 | ||
44 | if (WARN_ON_ONCE(!desc)) | |
45 | return NULL; | |
46 | ||
47 | return desc->irq_2_iommu; | |
48 | } | |
49 | ||
50 | static struct irq_2_iommu *irq_2_iommu_alloc_cpu(unsigned int irq, int cpu) | |
51 | { | |
52 | struct irq_desc *desc; | |
53 | struct irq_2_iommu *irq_iommu; | |
54 | ||
55 | /* | |
56 | * alloc irq desc if not allocated already. | |
57 | */ | |
58 | desc = irq_to_desc_alloc_cpu(irq, cpu); | |
59 | if (!desc) { | |
60 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
61 | return NULL; | |
62 | } | |
63 | ||
64 | irq_iommu = desc->irq_2_iommu; | |
65 | ||
66 | if (!irq_iommu) | |
67 | desc->irq_2_iommu = get_one_free_irq_2_iommu(cpu); | |
68 | ||
69 | return desc->irq_2_iommu; | |
70 | } | |
71 | ||
72 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) | |
73 | { | |
74 | return irq_2_iommu_alloc_cpu(irq, boot_cpu_id); | |
e420dfb4 | 75 | } |
d6c88a50 | 76 | |
0b8f1efa YL |
77 | #else /* !CONFIG_SPARSE_IRQ */ |
78 | ||
79 | static struct irq_2_iommu irq_2_iommuX[NR_IRQS]; | |
80 | ||
81 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) | |
82 | { | |
83 | if (irq < nr_irqs) | |
84 | return &irq_2_iommuX[irq]; | |
85 | ||
86 | return NULL; | |
87 | } | |
e420dfb4 YL |
88 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) |
89 | { | |
90 | return irq_2_iommu(irq); | |
91 | } | |
0b8f1efa | 92 | #endif |
b6fcb33a SS |
93 | |
94 | static DEFINE_SPINLOCK(irq_2_ir_lock); | |
95 | ||
e420dfb4 | 96 | static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq) |
b6fcb33a | 97 | { |
e420dfb4 YL |
98 | struct irq_2_iommu *irq_iommu; |
99 | ||
100 | irq_iommu = irq_2_iommu(irq); | |
b6fcb33a | 101 | |
e420dfb4 YL |
102 | if (!irq_iommu) |
103 | return NULL; | |
b6fcb33a | 104 | |
e420dfb4 YL |
105 | if (!irq_iommu->iommu) |
106 | return NULL; | |
b6fcb33a | 107 | |
e420dfb4 YL |
108 | return irq_iommu; |
109 | } | |
b6fcb33a | 110 | |
e420dfb4 YL |
111 | int irq_remapped(int irq) |
112 | { | |
113 | return valid_irq_2_iommu(irq) != NULL; | |
b6fcb33a SS |
114 | } |
115 | ||
116 | int get_irte(int irq, struct irte *entry) | |
117 | { | |
118 | int index; | |
e420dfb4 | 119 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 120 | unsigned long flags; |
b6fcb33a | 121 | |
e420dfb4 | 122 | if (!entry) |
b6fcb33a SS |
123 | return -1; |
124 | ||
4c5502b1 | 125 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
126 | irq_iommu = valid_irq_2_iommu(irq); |
127 | if (!irq_iommu) { | |
4c5502b1 | 128 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
129 | return -1; |
130 | } | |
131 | ||
e420dfb4 YL |
132 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
133 | *entry = *(irq_iommu->iommu->ir_table->base + index); | |
b6fcb33a | 134 | |
4c5502b1 | 135 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
136 | return 0; |
137 | } | |
138 | ||
139 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) | |
140 | { | |
141 | struct ir_table *table = iommu->ir_table; | |
e420dfb4 | 142 | struct irq_2_iommu *irq_iommu; |
b6fcb33a SS |
143 | u16 index, start_index; |
144 | unsigned int mask = 0; | |
4c5502b1 | 145 | unsigned long flags; |
b6fcb33a SS |
146 | int i; |
147 | ||
148 | if (!count) | |
149 | return -1; | |
150 | ||
0b8f1efa | 151 | #ifndef CONFIG_SPARSE_IRQ |
e420dfb4 YL |
152 | /* protect irq_2_iommu_alloc later */ |
153 | if (irq >= nr_irqs) | |
154 | return -1; | |
0b8f1efa | 155 | #endif |
e420dfb4 | 156 | |
b6fcb33a SS |
157 | /* |
158 | * start the IRTE search from index 0. | |
159 | */ | |
160 | index = start_index = 0; | |
161 | ||
162 | if (count > 1) { | |
163 | count = __roundup_pow_of_two(count); | |
164 | mask = ilog2(count); | |
165 | } | |
166 | ||
167 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
168 | printk(KERN_ERR | |
169 | "Requested mask %x exceeds the max invalidation handle" | |
170 | " mask value %Lx\n", mask, | |
171 | ecap_max_handle_mask(iommu->ecap)); | |
172 | return -1; | |
173 | } | |
174 | ||
4c5502b1 | 175 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a SS |
176 | do { |
177 | for (i = index; i < index + count; i++) | |
178 | if (table->base[i].present) | |
179 | break; | |
180 | /* empty index found */ | |
181 | if (i == index + count) | |
182 | break; | |
183 | ||
184 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; | |
185 | ||
186 | if (index == start_index) { | |
4c5502b1 | 187 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
188 | printk(KERN_ERR "can't allocate an IRTE\n"); |
189 | return -1; | |
190 | } | |
191 | } while (1); | |
192 | ||
193 | for (i = index; i < index + count; i++) | |
194 | table->base[i].present = 1; | |
195 | ||
e420dfb4 | 196 | irq_iommu = irq_2_iommu_alloc(irq); |
0b8f1efa | 197 | if (!irq_iommu) { |
4c5502b1 | 198 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
0b8f1efa YL |
199 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); |
200 | return -1; | |
201 | } | |
202 | ||
e420dfb4 YL |
203 | irq_iommu->iommu = iommu; |
204 | irq_iommu->irte_index = index; | |
205 | irq_iommu->sub_handle = 0; | |
206 | irq_iommu->irte_mask = mask; | |
b6fcb33a | 207 | |
4c5502b1 | 208 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
209 | |
210 | return index; | |
211 | } | |
212 | ||
704126ad | 213 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
214 | { |
215 | struct qi_desc desc; | |
216 | ||
217 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
218 | | QI_IEC_SELECTIVE; | |
219 | desc.high = 0; | |
220 | ||
704126ad | 221 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
222 | } |
223 | ||
224 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |
225 | { | |
226 | int index; | |
e420dfb4 | 227 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 228 | unsigned long flags; |
b6fcb33a | 229 | |
4c5502b1 | 230 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
231 | irq_iommu = valid_irq_2_iommu(irq); |
232 | if (!irq_iommu) { | |
4c5502b1 | 233 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
234 | return -1; |
235 | } | |
236 | ||
e420dfb4 YL |
237 | *sub_handle = irq_iommu->sub_handle; |
238 | index = irq_iommu->irte_index; | |
4c5502b1 | 239 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
240 | return index; |
241 | } | |
242 | ||
243 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) | |
244 | { | |
e420dfb4 | 245 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 246 | unsigned long flags; |
e420dfb4 | 247 | |
4c5502b1 | 248 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 249 | |
7ddfb650 | 250 | irq_iommu = irq_2_iommu_alloc(irq); |
b6fcb33a | 251 | |
0b8f1efa | 252 | if (!irq_iommu) { |
4c5502b1 | 253 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
0b8f1efa YL |
254 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); |
255 | return -1; | |
256 | } | |
257 | ||
e420dfb4 YL |
258 | irq_iommu->iommu = iommu; |
259 | irq_iommu->irte_index = index; | |
260 | irq_iommu->sub_handle = subhandle; | |
261 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 262 | |
4c5502b1 | 263 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
264 | |
265 | return 0; | |
266 | } | |
267 | ||
268 | int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index) | |
269 | { | |
e420dfb4 | 270 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 271 | unsigned long flags; |
e420dfb4 | 272 | |
4c5502b1 | 273 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
274 | irq_iommu = valid_irq_2_iommu(irq); |
275 | if (!irq_iommu) { | |
4c5502b1 | 276 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
277 | return -1; |
278 | } | |
279 | ||
e420dfb4 YL |
280 | irq_iommu->iommu = NULL; |
281 | irq_iommu->irte_index = 0; | |
282 | irq_iommu->sub_handle = 0; | |
283 | irq_2_iommu(irq)->irte_mask = 0; | |
b6fcb33a | 284 | |
4c5502b1 | 285 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
286 | |
287 | return 0; | |
288 | } | |
289 | ||
290 | int modify_irte(int irq, struct irte *irte_modified) | |
291 | { | |
704126ad | 292 | int rc; |
b6fcb33a SS |
293 | int index; |
294 | struct irte *irte; | |
295 | struct intel_iommu *iommu; | |
e420dfb4 | 296 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 297 | unsigned long flags; |
b6fcb33a | 298 | |
4c5502b1 | 299 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
300 | irq_iommu = valid_irq_2_iommu(irq); |
301 | if (!irq_iommu) { | |
4c5502b1 | 302 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
303 | return -1; |
304 | } | |
305 | ||
e420dfb4 | 306 | iommu = irq_iommu->iommu; |
b6fcb33a | 307 | |
e420dfb4 | 308 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
309 | irte = &iommu->ir_table->base[index]; |
310 | ||
9d783ba0 | 311 | set_64bit((unsigned long *)irte, irte_modified->low); |
b6fcb33a SS |
312 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
313 | ||
704126ad | 314 | rc = qi_flush_iec(iommu, index, 0); |
4c5502b1 | 315 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
316 | |
317 | return rc; | |
b6fcb33a SS |
318 | } |
319 | ||
320 | int flush_irte(int irq) | |
321 | { | |
704126ad | 322 | int rc; |
b6fcb33a SS |
323 | int index; |
324 | struct intel_iommu *iommu; | |
e420dfb4 | 325 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 326 | unsigned long flags; |
b6fcb33a | 327 | |
4c5502b1 | 328 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
329 | irq_iommu = valid_irq_2_iommu(irq); |
330 | if (!irq_iommu) { | |
4c5502b1 | 331 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
332 | return -1; |
333 | } | |
334 | ||
e420dfb4 | 335 | iommu = irq_iommu->iommu; |
b6fcb33a | 336 | |
e420dfb4 | 337 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a | 338 | |
704126ad | 339 | rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask); |
4c5502b1 | 340 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 341 | |
704126ad | 342 | return rc; |
b6fcb33a SS |
343 | } |
344 | ||
89027d35 SS |
345 | struct intel_iommu *map_ioapic_to_ir(int apic) |
346 | { | |
347 | int i; | |
348 | ||
349 | for (i = 0; i < MAX_IO_APICS; i++) | |
350 | if (ir_ioapic[i].id == apic) | |
351 | return ir_ioapic[i].iommu; | |
352 | return NULL; | |
353 | } | |
354 | ||
75c46fa6 SS |
355 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
356 | { | |
357 | struct dmar_drhd_unit *drhd; | |
358 | ||
359 | drhd = dmar_find_matched_drhd_unit(dev); | |
360 | if (!drhd) | |
361 | return NULL; | |
362 | ||
363 | return drhd->iommu; | |
364 | } | |
365 | ||
b6fcb33a SS |
366 | int free_irte(int irq) |
367 | { | |
704126ad | 368 | int rc = 0; |
b6fcb33a SS |
369 | int index, i; |
370 | struct irte *irte; | |
371 | struct intel_iommu *iommu; | |
e420dfb4 | 372 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 373 | unsigned long flags; |
b6fcb33a | 374 | |
4c5502b1 | 375 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
376 | irq_iommu = valid_irq_2_iommu(irq); |
377 | if (!irq_iommu) { | |
4c5502b1 | 378 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
379 | return -1; |
380 | } | |
381 | ||
e420dfb4 | 382 | iommu = irq_iommu->iommu; |
b6fcb33a | 383 | |
e420dfb4 | 384 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
385 | irte = &iommu->ir_table->base[index]; |
386 | ||
e420dfb4 YL |
387 | if (!irq_iommu->sub_handle) { |
388 | for (i = 0; i < (1 << irq_iommu->irte_mask); i++) | |
b6fcb33a | 389 | set_64bit((unsigned long *)irte, 0); |
704126ad | 390 | rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask); |
b6fcb33a SS |
391 | } |
392 | ||
e420dfb4 YL |
393 | irq_iommu->iommu = NULL; |
394 | irq_iommu->irte_index = 0; | |
395 | irq_iommu->sub_handle = 0; | |
396 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 397 | |
4c5502b1 | 398 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 399 | |
704126ad | 400 | return rc; |
b6fcb33a SS |
401 | } |
402 | ||
2ae21010 SS |
403 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
404 | { | |
405 | u64 addr; | |
406 | u32 cmd, sts; | |
407 | unsigned long flags; | |
408 | ||
409 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
410 | ||
411 | spin_lock_irqsave(&iommu->register_lock, flags); | |
412 | ||
413 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
414 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
415 | ||
416 | /* Set interrupt-remapping table pointer */ | |
417 | cmd = iommu->gcmd | DMA_GCMD_SIRTP; | |
418 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | |
419 | ||
420 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
421 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
422 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
423 | ||
424 | /* | |
425 | * global invalidation of interrupt entry cache before enabling | |
426 | * interrupt-remapping. | |
427 | */ | |
428 | qi_global_iec(iommu); | |
429 | ||
430 | spin_lock_irqsave(&iommu->register_lock, flags); | |
431 | ||
432 | /* Enable interrupt-remapping */ | |
433 | cmd = iommu->gcmd | DMA_GCMD_IRE; | |
434 | iommu->gcmd |= DMA_GCMD_IRE; | |
435 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | |
436 | ||
437 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
438 | readl, (sts & DMA_GSTS_IRES), sts); | |
439 | ||
440 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
441 | } | |
442 | ||
443 | ||
444 | static int setup_intr_remapping(struct intel_iommu *iommu, int mode) | |
445 | { | |
446 | struct ir_table *ir_table; | |
447 | struct page *pages; | |
448 | ||
449 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), | |
450 | GFP_KERNEL); | |
451 | ||
452 | if (!iommu->ir_table) | |
453 | return -ENOMEM; | |
454 | ||
455 | pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, INTR_REMAP_PAGE_ORDER); | |
456 | ||
457 | if (!pages) { | |
458 | printk(KERN_ERR "failed to allocate pages of order %d\n", | |
459 | INTR_REMAP_PAGE_ORDER); | |
460 | kfree(iommu->ir_table); | |
461 | return -ENOMEM; | |
462 | } | |
463 | ||
464 | ir_table->base = page_address(pages); | |
465 | ||
466 | iommu_set_intr_remapping(iommu, mode); | |
467 | return 0; | |
468 | } | |
469 | ||
470 | int __init enable_intr_remapping(int eim) | |
471 | { | |
472 | struct dmar_drhd_unit *drhd; | |
473 | int setup = 0; | |
474 | ||
475 | /* | |
476 | * check for the Interrupt-remapping support | |
477 | */ | |
478 | for_each_drhd_unit(drhd) { | |
479 | struct intel_iommu *iommu = drhd->iommu; | |
480 | ||
481 | if (!ecap_ir_support(iommu->ecap)) | |
482 | continue; | |
483 | ||
484 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
485 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
486 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
487 | return -1; | |
488 | } | |
489 | } | |
490 | ||
491 | /* | |
492 | * Enable queued invalidation for all the DRHD's. | |
493 | */ | |
494 | for_each_drhd_unit(drhd) { | |
495 | int ret; | |
496 | struct intel_iommu *iommu = drhd->iommu; | |
497 | ret = dmar_enable_qi(iommu); | |
498 | ||
499 | if (ret) { | |
500 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
501 | " invalidation, ecap %Lx, ret %d\n", | |
502 | drhd->reg_base_addr, iommu->ecap, ret); | |
503 | return -1; | |
504 | } | |
505 | } | |
506 | ||
507 | /* | |
508 | * Setup Interrupt-remapping for all the DRHD's now. | |
509 | */ | |
510 | for_each_drhd_unit(drhd) { | |
511 | struct intel_iommu *iommu = drhd->iommu; | |
512 | ||
513 | if (!ecap_ir_support(iommu->ecap)) | |
514 | continue; | |
515 | ||
516 | if (setup_intr_remapping(iommu, eim)) | |
517 | goto error; | |
518 | ||
519 | setup = 1; | |
520 | } | |
521 | ||
522 | if (!setup) | |
523 | goto error; | |
524 | ||
525 | intr_remapping_enabled = 1; | |
526 | ||
527 | return 0; | |
528 | ||
529 | error: | |
530 | /* | |
531 | * handle error condition gracefully here! | |
532 | */ | |
533 | return -1; | |
534 | } | |
ad3ad3f6 SS |
535 | |
536 | static int ir_parse_ioapic_scope(struct acpi_dmar_header *header, | |
537 | struct intel_iommu *iommu) | |
538 | { | |
539 | struct acpi_dmar_hardware_unit *drhd; | |
540 | struct acpi_dmar_device_scope *scope; | |
541 | void *start, *end; | |
542 | ||
543 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
544 | ||
545 | start = (void *)(drhd + 1); | |
546 | end = ((void *)drhd) + header->length; | |
547 | ||
548 | while (start < end) { | |
549 | scope = start; | |
550 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { | |
551 | if (ir_ioapic_num == MAX_IO_APICS) { | |
552 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); | |
553 | return -1; | |
554 | } | |
555 | ||
556 | printk(KERN_INFO "IOAPIC id %d under DRHD base" | |
557 | " 0x%Lx\n", scope->enumeration_id, | |
558 | drhd->address); | |
559 | ||
560 | ir_ioapic[ir_ioapic_num].iommu = iommu; | |
561 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; | |
562 | ir_ioapic_num++; | |
563 | } | |
564 | start += scope->length; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | /* | |
571 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
572 | * hardware unit. | |
573 | */ | |
574 | int __init parse_ioapics_under_ir(void) | |
575 | { | |
576 | struct dmar_drhd_unit *drhd; | |
577 | int ir_supported = 0; | |
578 | ||
579 | for_each_drhd_unit(drhd) { | |
580 | struct intel_iommu *iommu = drhd->iommu; | |
581 | ||
582 | if (ecap_ir_support(iommu->ecap)) { | |
583 | if (ir_parse_ioapic_scope(drhd->hdr, iommu)) | |
584 | return -1; | |
585 | ||
586 | ir_supported = 1; | |
587 | } | |
588 | } | |
589 | ||
590 | if (ir_supported && ir_ioapic_num != nr_ioapics) { | |
591 | printk(KERN_WARNING | |
592 | "Not all IO-APIC's listed under remapping hardware\n"); | |
593 | return -1; | |
594 | } | |
595 | ||
596 | return ir_supported; | |
597 | } |