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Commit | Line | Data |
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5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 SS |
3 | #include <linux/spinlock.h> |
4 | #include <linux/jiffies.h> | |
5 | #include <linux/pci.h> | |
b6fcb33a | 6 | #include <linux/irq.h> |
ad3ad3f6 | 7 | #include <asm/io_apic.h> |
17483a1f | 8 | #include <asm/smp.h> |
6d652ea1 | 9 | #include <asm/cpu.h> |
38717946 | 10 | #include <linux/intel-iommu.h> |
ad3ad3f6 | 11 | #include "intr_remapping.h" |
46f06b72 | 12 | #include <acpi/acpi.h> |
f007e99c WH |
13 | #include <asm/pci-direct.h> |
14 | #include "pci.h" | |
ad3ad3f6 SS |
15 | |
16 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; | |
17 | static int ir_ioapic_num; | |
2ae21010 SS |
18 | int intr_remapping_enabled; |
19 | ||
03ea8155 WH |
20 | static int disable_intremap; |
21 | static __init int setup_nointremap(char *str) | |
22 | { | |
23 | disable_intremap = 1; | |
24 | return 0; | |
25 | } | |
26 | early_param("nointremap", setup_nointremap); | |
27 | ||
5aeecaf4 | 28 | struct irq_2_iommu { |
b6fcb33a SS |
29 | struct intel_iommu *iommu; |
30 | u16 irte_index; | |
31 | u16 sub_handle; | |
32 | u8 irte_mask; | |
5aeecaf4 YL |
33 | }; |
34 | ||
d7e51e66 | 35 | #ifdef CONFIG_GENERIC_HARDIRQS |
85ac16d0 | 36 | static struct irq_2_iommu *get_one_free_irq_2_iommu(int node) |
0b8f1efa YL |
37 | { |
38 | struct irq_2_iommu *iommu; | |
0b8f1efa YL |
39 | |
40 | iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node); | |
85ac16d0 | 41 | printk(KERN_DEBUG "alloc irq_2_iommu on node %d\n", node); |
0b8f1efa YL |
42 | |
43 | return iommu; | |
44 | } | |
e420dfb4 YL |
45 | |
46 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) | |
47 | { | |
0b8f1efa YL |
48 | struct irq_desc *desc; |
49 | ||
50 | desc = irq_to_desc(irq); | |
51 | ||
52 | if (WARN_ON_ONCE(!desc)) | |
53 | return NULL; | |
54 | ||
55 | return desc->irq_2_iommu; | |
56 | } | |
57 | ||
85ac16d0 | 58 | static struct irq_2_iommu *irq_2_iommu_alloc_node(unsigned int irq, int node) |
0b8f1efa YL |
59 | { |
60 | struct irq_desc *desc; | |
61 | struct irq_2_iommu *irq_iommu; | |
62 | ||
63 | /* | |
64 | * alloc irq desc if not allocated already. | |
65 | */ | |
85ac16d0 | 66 | desc = irq_to_desc_alloc_node(irq, node); |
0b8f1efa YL |
67 | if (!desc) { |
68 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
69 | return NULL; | |
70 | } | |
71 | ||
72 | irq_iommu = desc->irq_2_iommu; | |
73 | ||
74 | if (!irq_iommu) | |
85ac16d0 | 75 | desc->irq_2_iommu = get_one_free_irq_2_iommu(node); |
0b8f1efa YL |
76 | |
77 | return desc->irq_2_iommu; | |
78 | } | |
79 | ||
80 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) | |
81 | { | |
85ac16d0 | 82 | return irq_2_iommu_alloc_node(irq, cpu_to_node(boot_cpu_id)); |
e420dfb4 | 83 | } |
d6c88a50 | 84 | |
0b8f1efa YL |
85 | #else /* !CONFIG_SPARSE_IRQ */ |
86 | ||
87 | static struct irq_2_iommu irq_2_iommuX[NR_IRQS]; | |
88 | ||
89 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) | |
90 | { | |
91 | if (irq < nr_irqs) | |
92 | return &irq_2_iommuX[irq]; | |
93 | ||
94 | return NULL; | |
95 | } | |
e420dfb4 YL |
96 | static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq) |
97 | { | |
98 | return irq_2_iommu(irq); | |
99 | } | |
0b8f1efa | 100 | #endif |
b6fcb33a SS |
101 | |
102 | static DEFINE_SPINLOCK(irq_2_ir_lock); | |
103 | ||
e420dfb4 | 104 | static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq) |
b6fcb33a | 105 | { |
e420dfb4 YL |
106 | struct irq_2_iommu *irq_iommu; |
107 | ||
108 | irq_iommu = irq_2_iommu(irq); | |
b6fcb33a | 109 | |
e420dfb4 YL |
110 | if (!irq_iommu) |
111 | return NULL; | |
b6fcb33a | 112 | |
e420dfb4 YL |
113 | if (!irq_iommu->iommu) |
114 | return NULL; | |
b6fcb33a | 115 | |
e420dfb4 YL |
116 | return irq_iommu; |
117 | } | |
b6fcb33a | 118 | |
e420dfb4 YL |
119 | int irq_remapped(int irq) |
120 | { | |
121 | return valid_irq_2_iommu(irq) != NULL; | |
b6fcb33a SS |
122 | } |
123 | ||
124 | int get_irte(int irq, struct irte *entry) | |
125 | { | |
126 | int index; | |
e420dfb4 | 127 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 128 | unsigned long flags; |
b6fcb33a | 129 | |
e420dfb4 | 130 | if (!entry) |
b6fcb33a SS |
131 | return -1; |
132 | ||
4c5502b1 | 133 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
134 | irq_iommu = valid_irq_2_iommu(irq); |
135 | if (!irq_iommu) { | |
4c5502b1 | 136 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
137 | return -1; |
138 | } | |
139 | ||
e420dfb4 YL |
140 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
141 | *entry = *(irq_iommu->iommu->ir_table->base + index); | |
b6fcb33a | 142 | |
4c5502b1 | 143 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
144 | return 0; |
145 | } | |
146 | ||
147 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) | |
148 | { | |
149 | struct ir_table *table = iommu->ir_table; | |
e420dfb4 | 150 | struct irq_2_iommu *irq_iommu; |
b6fcb33a SS |
151 | u16 index, start_index; |
152 | unsigned int mask = 0; | |
4c5502b1 | 153 | unsigned long flags; |
b6fcb33a SS |
154 | int i; |
155 | ||
156 | if (!count) | |
157 | return -1; | |
158 | ||
0b8f1efa | 159 | #ifndef CONFIG_SPARSE_IRQ |
e420dfb4 YL |
160 | /* protect irq_2_iommu_alloc later */ |
161 | if (irq >= nr_irqs) | |
162 | return -1; | |
0b8f1efa | 163 | #endif |
e420dfb4 | 164 | |
b6fcb33a SS |
165 | /* |
166 | * start the IRTE search from index 0. | |
167 | */ | |
168 | index = start_index = 0; | |
169 | ||
170 | if (count > 1) { | |
171 | count = __roundup_pow_of_two(count); | |
172 | mask = ilog2(count); | |
173 | } | |
174 | ||
175 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
176 | printk(KERN_ERR | |
177 | "Requested mask %x exceeds the max invalidation handle" | |
178 | " mask value %Lx\n", mask, | |
179 | ecap_max_handle_mask(iommu->ecap)); | |
180 | return -1; | |
181 | } | |
182 | ||
4c5502b1 | 183 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a SS |
184 | do { |
185 | for (i = index; i < index + count; i++) | |
186 | if (table->base[i].present) | |
187 | break; | |
188 | /* empty index found */ | |
189 | if (i == index + count) | |
190 | break; | |
191 | ||
192 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; | |
193 | ||
194 | if (index == start_index) { | |
4c5502b1 | 195 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
196 | printk(KERN_ERR "can't allocate an IRTE\n"); |
197 | return -1; | |
198 | } | |
199 | } while (1); | |
200 | ||
201 | for (i = index; i < index + count; i++) | |
202 | table->base[i].present = 1; | |
203 | ||
e420dfb4 | 204 | irq_iommu = irq_2_iommu_alloc(irq); |
0b8f1efa | 205 | if (!irq_iommu) { |
4c5502b1 | 206 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
0b8f1efa YL |
207 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); |
208 | return -1; | |
209 | } | |
210 | ||
e420dfb4 YL |
211 | irq_iommu->iommu = iommu; |
212 | irq_iommu->irte_index = index; | |
213 | irq_iommu->sub_handle = 0; | |
214 | irq_iommu->irte_mask = mask; | |
b6fcb33a | 215 | |
4c5502b1 | 216 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
217 | |
218 | return index; | |
219 | } | |
220 | ||
704126ad | 221 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
222 | { |
223 | struct qi_desc desc; | |
224 | ||
225 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
226 | | QI_IEC_SELECTIVE; | |
227 | desc.high = 0; | |
228 | ||
704126ad | 229 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
230 | } |
231 | ||
232 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |
233 | { | |
234 | int index; | |
e420dfb4 | 235 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 236 | unsigned long flags; |
b6fcb33a | 237 | |
4c5502b1 | 238 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
239 | irq_iommu = valid_irq_2_iommu(irq); |
240 | if (!irq_iommu) { | |
4c5502b1 | 241 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
242 | return -1; |
243 | } | |
244 | ||
e420dfb4 YL |
245 | *sub_handle = irq_iommu->sub_handle; |
246 | index = irq_iommu->irte_index; | |
4c5502b1 | 247 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
248 | return index; |
249 | } | |
250 | ||
251 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) | |
252 | { | |
e420dfb4 | 253 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 254 | unsigned long flags; |
e420dfb4 | 255 | |
4c5502b1 | 256 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 257 | |
7ddfb650 | 258 | irq_iommu = irq_2_iommu_alloc(irq); |
b6fcb33a | 259 | |
0b8f1efa | 260 | if (!irq_iommu) { |
4c5502b1 | 261 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
0b8f1efa YL |
262 | printk(KERN_ERR "can't allocate irq_2_iommu\n"); |
263 | return -1; | |
264 | } | |
265 | ||
e420dfb4 YL |
266 | irq_iommu->iommu = iommu; |
267 | irq_iommu->irte_index = index; | |
268 | irq_iommu->sub_handle = subhandle; | |
269 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 270 | |
4c5502b1 | 271 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
272 | |
273 | return 0; | |
274 | } | |
275 | ||
276 | int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index) | |
277 | { | |
e420dfb4 | 278 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 279 | unsigned long flags; |
e420dfb4 | 280 | |
4c5502b1 | 281 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
282 | irq_iommu = valid_irq_2_iommu(irq); |
283 | if (!irq_iommu) { | |
4c5502b1 | 284 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
285 | return -1; |
286 | } | |
287 | ||
e420dfb4 YL |
288 | irq_iommu->iommu = NULL; |
289 | irq_iommu->irte_index = 0; | |
290 | irq_iommu->sub_handle = 0; | |
291 | irq_2_iommu(irq)->irte_mask = 0; | |
b6fcb33a | 292 | |
4c5502b1 | 293 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
298 | int modify_irte(int irq, struct irte *irte_modified) | |
299 | { | |
704126ad | 300 | int rc; |
b6fcb33a SS |
301 | int index; |
302 | struct irte *irte; | |
303 | struct intel_iommu *iommu; | |
e420dfb4 | 304 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 305 | unsigned long flags; |
b6fcb33a | 306 | |
4c5502b1 | 307 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
308 | irq_iommu = valid_irq_2_iommu(irq); |
309 | if (!irq_iommu) { | |
4c5502b1 | 310 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
311 | return -1; |
312 | } | |
313 | ||
e420dfb4 | 314 | iommu = irq_iommu->iommu; |
b6fcb33a | 315 | |
e420dfb4 | 316 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
317 | irte = &iommu->ir_table->base[index]; |
318 | ||
c4658b4e WH |
319 | set_64bit((unsigned long *)&irte->low, irte_modified->low); |
320 | set_64bit((unsigned long *)&irte->high, irte_modified->high); | |
b6fcb33a SS |
321 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
322 | ||
704126ad | 323 | rc = qi_flush_iec(iommu, index, 0); |
4c5502b1 | 324 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
325 | |
326 | return rc; | |
b6fcb33a SS |
327 | } |
328 | ||
329 | int flush_irte(int irq) | |
330 | { | |
704126ad | 331 | int rc; |
b6fcb33a SS |
332 | int index; |
333 | struct intel_iommu *iommu; | |
e420dfb4 | 334 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 335 | unsigned long flags; |
b6fcb33a | 336 | |
4c5502b1 | 337 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
338 | irq_iommu = valid_irq_2_iommu(irq); |
339 | if (!irq_iommu) { | |
4c5502b1 | 340 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
341 | return -1; |
342 | } | |
343 | ||
e420dfb4 | 344 | iommu = irq_iommu->iommu; |
b6fcb33a | 345 | |
e420dfb4 | 346 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a | 347 | |
704126ad | 348 | rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask); |
4c5502b1 | 349 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 350 | |
704126ad | 351 | return rc; |
b6fcb33a SS |
352 | } |
353 | ||
89027d35 SS |
354 | struct intel_iommu *map_ioapic_to_ir(int apic) |
355 | { | |
356 | int i; | |
357 | ||
358 | for (i = 0; i < MAX_IO_APICS; i++) | |
359 | if (ir_ioapic[i].id == apic) | |
360 | return ir_ioapic[i].iommu; | |
361 | return NULL; | |
362 | } | |
363 | ||
75c46fa6 SS |
364 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
365 | { | |
366 | struct dmar_drhd_unit *drhd; | |
367 | ||
368 | drhd = dmar_find_matched_drhd_unit(dev); | |
369 | if (!drhd) | |
370 | return NULL; | |
371 | ||
372 | return drhd->iommu; | |
373 | } | |
374 | ||
c4658b4e WH |
375 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
376 | { | |
377 | struct irte *start, *entry, *end; | |
378 | struct intel_iommu *iommu; | |
379 | int index; | |
380 | ||
381 | if (irq_iommu->sub_handle) | |
382 | return 0; | |
383 | ||
384 | iommu = irq_iommu->iommu; | |
385 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | |
386 | ||
387 | start = iommu->ir_table->base + index; | |
388 | end = start + (1 << irq_iommu->irte_mask); | |
389 | ||
390 | for (entry = start; entry < end; entry++) { | |
391 | set_64bit((unsigned long *)&entry->low, 0); | |
392 | set_64bit((unsigned long *)&entry->high, 0); | |
393 | } | |
394 | ||
395 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
396 | } | |
397 | ||
b6fcb33a SS |
398 | int free_irte(int irq) |
399 | { | |
704126ad | 400 | int rc = 0; |
e420dfb4 | 401 | struct irq_2_iommu *irq_iommu; |
4c5502b1 | 402 | unsigned long flags; |
b6fcb33a | 403 | |
4c5502b1 | 404 | spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
405 | irq_iommu = valid_irq_2_iommu(irq); |
406 | if (!irq_iommu) { | |
4c5502b1 | 407 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
408 | return -1; |
409 | } | |
410 | ||
c4658b4e | 411 | rc = clear_entries(irq_iommu); |
b6fcb33a | 412 | |
e420dfb4 YL |
413 | irq_iommu->iommu = NULL; |
414 | irq_iommu->irte_index = 0; | |
415 | irq_iommu->sub_handle = 0; | |
416 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 417 | |
4c5502b1 | 418 | spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 419 | |
704126ad | 420 | return rc; |
b6fcb33a SS |
421 | } |
422 | ||
f007e99c WH |
423 | /* |
424 | * source validation type | |
425 | */ | |
426 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
427 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fiels */ | |
428 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ | |
429 | ||
430 | /* | |
431 | * source-id qualifier | |
432 | */ | |
433 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
434 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
435 | * the third least significant bit | |
436 | */ | |
437 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
438 | * the second and third least significant bits | |
439 | */ | |
440 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
441 | * the least three significant bits | |
442 | */ | |
443 | ||
444 | /* | |
445 | * set SVT, SQ and SID fields of irte to verify | |
446 | * source ids of interrupt requests | |
447 | */ | |
448 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
449 | unsigned int sq, unsigned int sid) | |
450 | { | |
451 | irte->svt = svt; | |
452 | irte->sq = sq; | |
453 | irte->sid = sid; | |
454 | } | |
455 | ||
456 | int set_ioapic_sid(struct irte *irte, int apic) | |
457 | { | |
458 | int i; | |
459 | u16 sid = 0; | |
460 | ||
461 | if (!irte) | |
462 | return -1; | |
463 | ||
464 | for (i = 0; i < MAX_IO_APICS; i++) { | |
465 | if (ir_ioapic[i].id == apic) { | |
466 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; | |
467 | break; | |
468 | } | |
469 | } | |
470 | ||
471 | if (sid == 0) { | |
472 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); | |
473 | return -1; | |
474 | } | |
475 | ||
476 | set_irte_sid(irte, 1, 0, sid); | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
481 | int set_msi_sid(struct irte *irte, struct pci_dev *dev) | |
482 | { | |
483 | struct pci_dev *bridge; | |
484 | ||
485 | if (!irte || !dev) | |
486 | return -1; | |
487 | ||
488 | /* PCIe device or Root Complex integrated PCI device */ | |
489 | if (dev->is_pcie || !dev->bus->parent) { | |
490 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
491 | (dev->bus->number << 8) | dev->devfn); | |
492 | return 0; | |
493 | } | |
494 | ||
495 | bridge = pci_find_upstream_pcie_bridge(dev); | |
496 | if (bridge) { | |
497 | if (bridge->is_pcie) /* this is a PCIE-to-PCI/PCIX bridge */ | |
498 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, | |
499 | (bridge->bus->number << 8) | dev->bus->number); | |
500 | else /* this is a legacy PCI bridge */ | |
501 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
502 | (bridge->bus->number << 8) | bridge->devfn); | |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
2ae21010 SS |
508 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
509 | { | |
510 | u64 addr; | |
c416daa9 | 511 | u32 sts; |
2ae21010 SS |
512 | unsigned long flags; |
513 | ||
514 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
515 | ||
516 | spin_lock_irqsave(&iommu->register_lock, flags); | |
517 | ||
518 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
519 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
520 | ||
521 | /* Set interrupt-remapping table pointer */ | |
161fde08 | 522 | iommu->gcmd |= DMA_GCMD_SIRTP; |
c416daa9 | 523 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
524 | |
525 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
526 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
527 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
528 | ||
529 | /* | |
530 | * global invalidation of interrupt entry cache before enabling | |
531 | * interrupt-remapping. | |
532 | */ | |
533 | qi_global_iec(iommu); | |
534 | ||
535 | spin_lock_irqsave(&iommu->register_lock, flags); | |
536 | ||
537 | /* Enable interrupt-remapping */ | |
2ae21010 | 538 | iommu->gcmd |= DMA_GCMD_IRE; |
c416daa9 | 539 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
540 | |
541 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
542 | readl, (sts & DMA_GSTS_IRES), sts); | |
543 | ||
544 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
545 | } | |
546 | ||
547 | ||
548 | static int setup_intr_remapping(struct intel_iommu *iommu, int mode) | |
549 | { | |
550 | struct ir_table *ir_table; | |
551 | struct page *pages; | |
552 | ||
553 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), | |
fa4b57cc | 554 | GFP_ATOMIC); |
2ae21010 SS |
555 | |
556 | if (!iommu->ir_table) | |
557 | return -ENOMEM; | |
558 | ||
fa4b57cc | 559 | pages = alloc_pages(GFP_ATOMIC | __GFP_ZERO, INTR_REMAP_PAGE_ORDER); |
2ae21010 SS |
560 | |
561 | if (!pages) { | |
562 | printk(KERN_ERR "failed to allocate pages of order %d\n", | |
563 | INTR_REMAP_PAGE_ORDER); | |
564 | kfree(iommu->ir_table); | |
565 | return -ENOMEM; | |
566 | } | |
567 | ||
568 | ir_table->base = page_address(pages); | |
569 | ||
570 | iommu_set_intr_remapping(iommu, mode); | |
571 | return 0; | |
572 | } | |
573 | ||
eba67e5d SS |
574 | /* |
575 | * Disable Interrupt Remapping. | |
576 | */ | |
b24696bc | 577 | static void iommu_disable_intr_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
578 | { |
579 | unsigned long flags; | |
580 | u32 sts; | |
581 | ||
582 | if (!ecap_ir_support(iommu->ecap)) | |
583 | return; | |
584 | ||
b24696bc FY |
585 | /* |
586 | * global invalidation of interrupt entry cache before disabling | |
587 | * interrupt-remapping. | |
588 | */ | |
589 | qi_global_iec(iommu); | |
590 | ||
eba67e5d SS |
591 | spin_lock_irqsave(&iommu->register_lock, flags); |
592 | ||
593 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
594 | if (!(sts & DMA_GSTS_IRES)) | |
595 | goto end; | |
596 | ||
597 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
598 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
599 | ||
600 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
601 | readl, !(sts & DMA_GSTS_IRES), sts); | |
602 | ||
603 | end: | |
604 | spin_unlock_irqrestore(&iommu->register_lock, flags); | |
605 | } | |
606 | ||
93758238 WH |
607 | int __init intr_remapping_supported(void) |
608 | { | |
609 | struct dmar_drhd_unit *drhd; | |
610 | ||
03ea8155 WH |
611 | if (disable_intremap) |
612 | return 0; | |
613 | ||
93758238 WH |
614 | for_each_drhd_unit(drhd) { |
615 | struct intel_iommu *iommu = drhd->iommu; | |
616 | ||
617 | if (!ecap_ir_support(iommu->ecap)) | |
618 | return 0; | |
619 | } | |
620 | ||
621 | return 1; | |
622 | } | |
623 | ||
2ae21010 SS |
624 | int __init enable_intr_remapping(int eim) |
625 | { | |
626 | struct dmar_drhd_unit *drhd; | |
627 | int setup = 0; | |
628 | ||
1531a6a6 SS |
629 | for_each_drhd_unit(drhd) { |
630 | struct intel_iommu *iommu = drhd->iommu; | |
631 | ||
34aaaa94 HW |
632 | /* |
633 | * If the queued invalidation is already initialized, | |
634 | * shouldn't disable it. | |
635 | */ | |
636 | if (iommu->qi) | |
637 | continue; | |
638 | ||
1531a6a6 SS |
639 | /* |
640 | * Clear previous faults. | |
641 | */ | |
642 | dmar_fault(-1, iommu); | |
643 | ||
644 | /* | |
645 | * Disable intr remapping and queued invalidation, if already | |
646 | * enabled prior to OS handover. | |
647 | */ | |
b24696bc | 648 | iommu_disable_intr_remapping(iommu); |
1531a6a6 SS |
649 | |
650 | dmar_disable_qi(iommu); | |
651 | } | |
652 | ||
2ae21010 SS |
653 | /* |
654 | * check for the Interrupt-remapping support | |
655 | */ | |
656 | for_each_drhd_unit(drhd) { | |
657 | struct intel_iommu *iommu = drhd->iommu; | |
658 | ||
659 | if (!ecap_ir_support(iommu->ecap)) | |
660 | continue; | |
661 | ||
662 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
663 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
664 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
665 | return -1; | |
666 | } | |
667 | } | |
668 | ||
669 | /* | |
670 | * Enable queued invalidation for all the DRHD's. | |
671 | */ | |
672 | for_each_drhd_unit(drhd) { | |
673 | int ret; | |
674 | struct intel_iommu *iommu = drhd->iommu; | |
675 | ret = dmar_enable_qi(iommu); | |
676 | ||
677 | if (ret) { | |
678 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
679 | " invalidation, ecap %Lx, ret %d\n", | |
680 | drhd->reg_base_addr, iommu->ecap, ret); | |
681 | return -1; | |
682 | } | |
683 | } | |
684 | ||
685 | /* | |
686 | * Setup Interrupt-remapping for all the DRHD's now. | |
687 | */ | |
688 | for_each_drhd_unit(drhd) { | |
689 | struct intel_iommu *iommu = drhd->iommu; | |
690 | ||
691 | if (!ecap_ir_support(iommu->ecap)) | |
692 | continue; | |
693 | ||
694 | if (setup_intr_remapping(iommu, eim)) | |
695 | goto error; | |
696 | ||
697 | setup = 1; | |
698 | } | |
699 | ||
700 | if (!setup) | |
701 | goto error; | |
702 | ||
703 | intr_remapping_enabled = 1; | |
704 | ||
705 | return 0; | |
706 | ||
707 | error: | |
708 | /* | |
709 | * handle error condition gracefully here! | |
710 | */ | |
711 | return -1; | |
712 | } | |
ad3ad3f6 | 713 | |
f007e99c WH |
714 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
715 | struct intel_iommu *iommu) | |
716 | { | |
717 | struct acpi_dmar_pci_path *path; | |
718 | u8 bus; | |
719 | int count; | |
720 | ||
721 | bus = scope->bus; | |
722 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
723 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
724 | / sizeof(struct acpi_dmar_pci_path); | |
725 | ||
726 | while (--count > 0) { | |
727 | /* | |
728 | * Access PCI directly due to the PCI | |
729 | * subsystem isn't initialized yet. | |
730 | */ | |
731 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
732 | PCI_SECONDARY_BUS); | |
733 | path++; | |
734 | } | |
735 | ||
736 | ir_ioapic[ir_ioapic_num].bus = bus; | |
737 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
738 | ir_ioapic[ir_ioapic_num].iommu = iommu; | |
739 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; | |
740 | ir_ioapic_num++; | |
741 | } | |
742 | ||
ad3ad3f6 SS |
743 | static int ir_parse_ioapic_scope(struct acpi_dmar_header *header, |
744 | struct intel_iommu *iommu) | |
745 | { | |
746 | struct acpi_dmar_hardware_unit *drhd; | |
747 | struct acpi_dmar_device_scope *scope; | |
748 | void *start, *end; | |
749 | ||
750 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
751 | ||
752 | start = (void *)(drhd + 1); | |
753 | end = ((void *)drhd) + header->length; | |
754 | ||
755 | while (start < end) { | |
756 | scope = start; | |
757 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { | |
758 | if (ir_ioapic_num == MAX_IO_APICS) { | |
759 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); | |
760 | return -1; | |
761 | } | |
762 | ||
763 | printk(KERN_INFO "IOAPIC id %d under DRHD base" | |
764 | " 0x%Lx\n", scope->enumeration_id, | |
765 | drhd->address); | |
766 | ||
f007e99c | 767 | ir_parse_one_ioapic_scope(scope, iommu); |
ad3ad3f6 SS |
768 | } |
769 | start += scope->length; | |
770 | } | |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
775 | /* | |
776 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
777 | * hardware unit. | |
778 | */ | |
779 | int __init parse_ioapics_under_ir(void) | |
780 | { | |
781 | struct dmar_drhd_unit *drhd; | |
782 | int ir_supported = 0; | |
783 | ||
784 | for_each_drhd_unit(drhd) { | |
785 | struct intel_iommu *iommu = drhd->iommu; | |
786 | ||
787 | if (ecap_ir_support(iommu->ecap)) { | |
788 | if (ir_parse_ioapic_scope(drhd->hdr, iommu)) | |
789 | return -1; | |
790 | ||
791 | ir_supported = 1; | |
792 | } | |
793 | } | |
794 | ||
795 | if (ir_supported && ir_ioapic_num != nr_ioapics) { | |
796 | printk(KERN_WARNING | |
797 | "Not all IO-APIC's listed under remapping hardware\n"); | |
798 | return -1; | |
799 | } | |
800 | ||
801 | return ir_supported; | |
802 | } | |
b24696bc FY |
803 | |
804 | void disable_intr_remapping(void) | |
805 | { | |
806 | struct dmar_drhd_unit *drhd; | |
807 | struct intel_iommu *iommu = NULL; | |
808 | ||
809 | /* | |
810 | * Disable Interrupt-remapping for all the DRHD's now. | |
811 | */ | |
812 | for_each_iommu(iommu, drhd) { | |
813 | if (!ecap_ir_support(iommu->ecap)) | |
814 | continue; | |
815 | ||
816 | iommu_disable_intr_remapping(iommu); | |
817 | } | |
818 | } | |
819 | ||
820 | int reenable_intr_remapping(int eim) | |
821 | { | |
822 | struct dmar_drhd_unit *drhd; | |
823 | int setup = 0; | |
824 | struct intel_iommu *iommu = NULL; | |
825 | ||
826 | for_each_iommu(iommu, drhd) | |
827 | if (iommu->qi) | |
828 | dmar_reenable_qi(iommu); | |
829 | ||
830 | /* | |
831 | * Setup Interrupt-remapping for all the DRHD's now. | |
832 | */ | |
833 | for_each_iommu(iommu, drhd) { | |
834 | if (!ecap_ir_support(iommu->ecap)) | |
835 | continue; | |
836 | ||
837 | /* Set up interrupt remapping for iommu.*/ | |
838 | iommu_set_intr_remapping(iommu, eim); | |
839 | setup = 1; | |
840 | } | |
841 | ||
842 | if (!setup) | |
843 | goto error; | |
844 | ||
845 | return 0; | |
846 | ||
847 | error: | |
848 | /* | |
849 | * handle error condition gracefully here! | |
850 | */ | |
851 | return -1; | |
852 | } | |
853 |