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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
1da177e4 | 27 | static int pci_msi_enable = 1; |
1da177e4 | 28 | |
6a9e7f20 AB |
29 | /* Arch hooks */ |
30 | ||
11df1f05 ME |
31 | #ifndef arch_msi_check_device |
32 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
33 | { |
34 | return 0; | |
35 | } | |
11df1f05 | 36 | #endif |
6a9e7f20 | 37 | |
11df1f05 | 38 | #ifndef arch_setup_msi_irqs |
1525bf0d TG |
39 | # define arch_setup_msi_irqs default_setup_msi_irqs |
40 | # define HAVE_DEFAULT_MSI_SETUP_IRQS | |
41 | #endif | |
42 | ||
43 | #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS | |
44 | int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
45 | { |
46 | struct msi_desc *entry; | |
47 | int ret; | |
48 | ||
1c8d7b0a MW |
49 | /* |
50 | * If an architecture wants to support multiple MSI, it needs to | |
51 | * override arch_setup_msi_irqs() | |
52 | */ | |
53 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
54 | return 1; | |
55 | ||
6a9e7f20 AB |
56 | list_for_each_entry(entry, &dev->msi_list, list) { |
57 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 58 | if (ret < 0) |
6a9e7f20 | 59 | return ret; |
b5fbf533 ME |
60 | if (ret > 0) |
61 | return -ENOSPC; | |
6a9e7f20 AB |
62 | } |
63 | ||
64 | return 0; | |
65 | } | |
11df1f05 | 66 | #endif |
6a9e7f20 | 67 | |
11df1f05 | 68 | #ifndef arch_teardown_msi_irqs |
1525bf0d TG |
69 | # define arch_teardown_msi_irqs default_teardown_msi_irqs |
70 | # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
71 | #endif | |
72 | ||
73 | #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
74 | void default_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
75 | { |
76 | struct msi_desc *entry; | |
77 | ||
78 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
79 | int i, nvec; |
80 | if (entry->irq == 0) | |
81 | continue; | |
82 | nvec = 1 << entry->msi_attrib.multiple; | |
83 | for (i = 0; i < nvec; i++) | |
84 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
85 | } |
86 | } | |
11df1f05 | 87 | #endif |
6a9e7f20 | 88 | |
76ccc297 KRW |
89 | #ifndef arch_restore_msi_irqs |
90 | # define arch_restore_msi_irqs default_restore_msi_irqs | |
91 | # define HAVE_DEFAULT_MSI_RESTORE_IRQS | |
92 | #endif | |
93 | ||
94 | #ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS | |
95 | void default_restore_msi_irqs(struct pci_dev *dev, int irq) | |
96 | { | |
97 | struct msi_desc *entry; | |
98 | ||
99 | entry = NULL; | |
100 | if (dev->msix_enabled) { | |
101 | list_for_each_entry(entry, &dev->msi_list, list) { | |
102 | if (irq == entry->irq) | |
103 | break; | |
104 | } | |
105 | } else if (dev->msi_enabled) { | |
106 | entry = irq_get_msi_desc(irq); | |
107 | } | |
108 | ||
109 | if (entry) | |
110 | write_msi_msg(irq, &entry->msg); | |
111 | } | |
112 | #endif | |
113 | ||
110828c9 | 114 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 115 | { |
b1cbf4e4 EB |
116 | u16 control; |
117 | ||
110828c9 | 118 | BUG_ON(!pos); |
b1cbf4e4 | 119 | |
110828c9 MW |
120 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
121 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
122 | if (enable) | |
123 | control |= PCI_MSI_FLAGS_ENABLE; | |
124 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
125 | } |
126 | ||
b1cbf4e4 EB |
127 | static void msix_set_enable(struct pci_dev *dev, int enable) |
128 | { | |
129 | int pos; | |
130 | u16 control; | |
131 | ||
132 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
133 | if (pos) { | |
134 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
135 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
136 | if (enable) | |
137 | control |= PCI_MSIX_FLAGS_ENABLE; | |
138 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
139 | } | |
140 | } | |
141 | ||
bffac3c5 MW |
142 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
143 | { | |
0b49ec37 MW |
144 | /* Don't shift by >= width of type */ |
145 | if (x >= 5) | |
146 | return 0xffffffff; | |
147 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
148 | } |
149 | ||
f2440d9a | 150 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 151 | { |
f2440d9a MW |
152 | return msi_mask((control >> 1) & 7); |
153 | } | |
988cbb15 | 154 | |
f2440d9a MW |
155 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
156 | { | |
157 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
158 | } |
159 | ||
ce6fce42 MW |
160 | /* |
161 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
162 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
163 | * reliably as devices without an INTx disable bit will then generate a | |
164 | * level IRQ which will never be cleared. | |
ce6fce42 | 165 | */ |
12abb8ba | 166 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 167 | { |
f2440d9a | 168 | u32 mask_bits = desc->masked; |
1da177e4 | 169 | |
f2440d9a | 170 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 171 | return 0; |
f2440d9a MW |
172 | |
173 | mask_bits &= ~mask; | |
174 | mask_bits |= flag; | |
175 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
176 | |
177 | return mask_bits; | |
178 | } | |
179 | ||
180 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
181 | { | |
182 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
183 | } |
184 | ||
185 | /* | |
186 | * This internal function does not flush PCI writes to the device. | |
187 | * All users must ensure that they read from the device before either | |
188 | * assuming that the device state is up to date, or returning out of this | |
189 | * file. This saves a few milliseconds when initialising devices with lots | |
190 | * of MSI-X interrupts. | |
191 | */ | |
12abb8ba | 192 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
193 | { |
194 | u32 mask_bits = desc->masked; | |
195 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 196 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
197 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
198 | if (flag) | |
199 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 200 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
201 | |
202 | return mask_bits; | |
203 | } | |
204 | ||
205 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
206 | { | |
207 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 208 | } |
24d27553 | 209 | |
9a4da8a5 JG |
210 | #ifdef CONFIG_GENERIC_HARDIRQS |
211 | ||
1c9db525 | 212 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 213 | { |
1c9db525 | 214 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 215 | |
f2440d9a MW |
216 | if (desc->msi_attrib.is_msix) { |
217 | msix_mask_irq(desc, flag); | |
218 | readl(desc->mask_base); /* Flush write to device */ | |
219 | } else { | |
1c9db525 | 220 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 221 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 222 | } |
f2440d9a MW |
223 | } |
224 | ||
1c9db525 | 225 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 226 | { |
1c9db525 | 227 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
228 | } |
229 | ||
1c9db525 | 230 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 231 | { |
1c9db525 | 232 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
233 | } |
234 | ||
9a4da8a5 JG |
235 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
236 | ||
39431acb | 237 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 238 | { |
30da5524 BH |
239 | BUG_ON(entry->dev->current_state != PCI_D0); |
240 | ||
241 | if (entry->msi_attrib.is_msix) { | |
242 | void __iomem *base = entry->mask_base + | |
243 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
244 | ||
245 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
246 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
247 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
248 | } else { | |
249 | struct pci_dev *dev = entry->dev; | |
250 | int pos = entry->msi_attrib.pos; | |
251 | u16 data; | |
252 | ||
253 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
254 | &msg->address_lo); | |
255 | if (entry->msi_attrib.is_64) { | |
256 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
257 | &msg->address_hi); | |
258 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
259 | } else { | |
260 | msg->address_hi = 0; | |
261 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); | |
262 | } | |
263 | msg->data = data; | |
264 | } | |
265 | } | |
266 | ||
267 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
268 | { | |
dced35ae | 269 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 270 | |
39431acb | 271 | __read_msi_msg(entry, msg); |
30da5524 BH |
272 | } |
273 | ||
39431acb | 274 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 275 | { |
30da5524 | 276 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
277 | * valid messages are not all-zeroes. */ |
278 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
279 | entry->msg.data)); | |
0366f8f7 | 280 | |
fcd097f3 | 281 | *msg = entry->msg; |
0366f8f7 | 282 | } |
1da177e4 | 283 | |
30da5524 | 284 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 285 | { |
dced35ae | 286 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 287 | |
39431acb | 288 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
289 | } |
290 | ||
39431acb | 291 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 292 | { |
fcd097f3 BH |
293 | if (entry->dev->current_state != PCI_D0) { |
294 | /* Don't touch the hardware now */ | |
295 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
296 | void __iomem *base; |
297 | base = entry->mask_base + | |
298 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
299 | ||
2c21fd4b HS |
300 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
301 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
302 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 303 | } else { |
0366f8f7 EB |
304 | struct pci_dev *dev = entry->dev; |
305 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
306 | u16 msgctl; |
307 | ||
308 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
309 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
310 | msgctl |= entry->msi_attrib.multiple << 4; | |
311 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
312 | |
313 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
314 | msg->address_lo); | |
315 | if (entry->msi_attrib.is_64) { | |
316 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
317 | msg->address_hi); | |
318 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
319 | msg->data); | |
320 | } else { | |
321 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
322 | msg->data); | |
323 | } | |
1da177e4 | 324 | } |
392ee1e6 | 325 | entry->msg = *msg; |
1da177e4 | 326 | } |
0366f8f7 | 327 | |
3145e941 YL |
328 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
329 | { | |
dced35ae | 330 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 331 | |
39431acb | 332 | __write_msi_msg(entry, msg); |
3145e941 YL |
333 | } |
334 | ||
f56e4481 HS |
335 | static void free_msi_irqs(struct pci_dev *dev) |
336 | { | |
337 | struct msi_desc *entry, *tmp; | |
338 | ||
339 | list_for_each_entry(entry, &dev->msi_list, list) { | |
340 | int i, nvec; | |
341 | if (!entry->irq) | |
342 | continue; | |
343 | nvec = 1 << entry->msi_attrib.multiple; | |
9a4da8a5 | 344 | #ifdef CONFIG_GENERIC_HARDIRQS |
f56e4481 HS |
345 | for (i = 0; i < nvec; i++) |
346 | BUG_ON(irq_has_action(entry->irq + i)); | |
9a4da8a5 | 347 | #endif |
f56e4481 HS |
348 | } |
349 | ||
350 | arch_teardown_msi_irqs(dev); | |
351 | ||
352 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
353 | if (entry->msi_attrib.is_msix) { | |
354 | if (list_is_last(&entry->list, &dev->msi_list)) | |
355 | iounmap(entry->mask_base); | |
356 | } | |
424eb391 NH |
357 | |
358 | /* | |
359 | * Its possible that we get into this path | |
360 | * When populate_msi_sysfs fails, which means the entries | |
361 | * were not registered with sysfs. In that case don't | |
362 | * unregister them. | |
363 | */ | |
364 | if (entry->kobj.parent) { | |
365 | kobject_del(&entry->kobj); | |
366 | kobject_put(&entry->kobj); | |
367 | } | |
368 | ||
f56e4481 HS |
369 | list_del(&entry->list); |
370 | kfree(entry); | |
371 | } | |
372 | } | |
c54c1879 | 373 | |
379f5327 | 374 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 375 | { |
379f5327 MW |
376 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
377 | if (!desc) | |
1da177e4 LT |
378 | return NULL; |
379 | ||
379f5327 MW |
380 | INIT_LIST_HEAD(&desc->list); |
381 | desc->dev = dev; | |
1da177e4 | 382 | |
379f5327 | 383 | return desc; |
1da177e4 LT |
384 | } |
385 | ||
ba698ad4 DM |
386 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
387 | { | |
388 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
389 | pci_intx(dev, enable); | |
390 | } | |
391 | ||
8fed4b65 | 392 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 393 | { |
392ee1e6 | 394 | int pos; |
41017f0c | 395 | u16 control; |
392ee1e6 | 396 | struct msi_desc *entry; |
41017f0c | 397 | |
b1cbf4e4 EB |
398 | if (!dev->msi_enabled) |
399 | return; | |
400 | ||
dced35ae | 401 | entry = irq_get_msi_desc(dev->irq); |
392ee1e6 | 402 | pos = entry->msi_attrib.pos; |
41017f0c | 403 | |
ba698ad4 | 404 | pci_intx_for_msi(dev, 0); |
110828c9 | 405 | msi_set_enable(dev, pos, 0); |
76ccc297 | 406 | arch_restore_msi_irqs(dev, dev->irq); |
392ee1e6 EB |
407 | |
408 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 409 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 410 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 411 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 412 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
413 | } |
414 | ||
415 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 416 | { |
41017f0c | 417 | int pos; |
41017f0c | 418 | struct msi_desc *entry; |
392ee1e6 | 419 | u16 control; |
41017f0c | 420 | |
ded86d8d EB |
421 | if (!dev->msix_enabled) |
422 | return; | |
f598282f | 423 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 424 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f598282f MW |
425 | pos = entry->msi_attrib.pos; |
426 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 427 | |
41017f0c | 428 | /* route the table */ |
ba698ad4 | 429 | pci_intx_for_msi(dev, 0); |
f598282f MW |
430 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
431 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 432 | |
4aa9bc95 | 433 | list_for_each_entry(entry, &dev->msi_list, list) { |
76ccc297 | 434 | arch_restore_msi_irqs(dev, entry->irq); |
f2440d9a | 435 | msix_mask_irq(entry, entry->masked); |
41017f0c | 436 | } |
41017f0c | 437 | |
392ee1e6 | 438 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 439 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 440 | } |
8fed4b65 ME |
441 | |
442 | void pci_restore_msi_state(struct pci_dev *dev) | |
443 | { | |
444 | __pci_restore_msi_state(dev); | |
445 | __pci_restore_msix_state(dev); | |
446 | } | |
94688cf2 | 447 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 448 | |
da8d1c8b NH |
449 | |
450 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
451 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
452 | ||
453 | struct msi_attribute { | |
454 | struct attribute attr; | |
455 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
456 | char *buf); | |
457 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
458 | const char *buf, size_t count); | |
459 | }; | |
460 | ||
461 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
462 | char *buf) | |
463 | { | |
464 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
465 | } | |
466 | ||
467 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
468 | struct attribute *attr, char *buf) | |
469 | { | |
470 | struct msi_attribute *attribute = to_msi_attr(attr); | |
471 | struct msi_desc *entry = to_msi_desc(kobj); | |
472 | ||
473 | if (!attribute->show) | |
474 | return -EIO; | |
475 | ||
476 | return attribute->show(entry, attribute, buf); | |
477 | } | |
478 | ||
479 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
480 | .show = msi_irq_attr_show, | |
481 | }; | |
482 | ||
483 | static struct msi_attribute mode_attribute = | |
484 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
485 | ||
486 | ||
487 | struct attribute *msi_irq_default_attrs[] = { | |
488 | &mode_attribute.attr, | |
489 | NULL | |
490 | }; | |
491 | ||
492 | void msi_kobj_release(struct kobject *kobj) | |
493 | { | |
494 | struct msi_desc *entry = to_msi_desc(kobj); | |
495 | ||
496 | pci_dev_put(entry->dev); | |
497 | } | |
498 | ||
499 | static struct kobj_type msi_irq_ktype = { | |
500 | .release = msi_kobj_release, | |
501 | .sysfs_ops = &msi_irq_sysfs_ops, | |
502 | .default_attrs = msi_irq_default_attrs, | |
503 | }; | |
504 | ||
505 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
506 | { | |
507 | struct msi_desc *entry; | |
508 | struct kobject *kobj; | |
509 | int ret; | |
510 | int count = 0; | |
511 | ||
512 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
513 | if (!pdev->msi_kset) | |
514 | return -ENOMEM; | |
515 | ||
516 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
517 | kobj = &entry->kobj; | |
518 | kobj->kset = pdev->msi_kset; | |
519 | pci_dev_get(pdev); | |
520 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
521 | "%u", entry->irq); | |
522 | if (ret) | |
523 | goto out_unroll; | |
524 | ||
525 | count++; | |
526 | } | |
527 | ||
528 | return 0; | |
529 | ||
530 | out_unroll: | |
531 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
532 | if (!count) | |
533 | break; | |
534 | kobject_del(&entry->kobj); | |
535 | kobject_put(&entry->kobj); | |
536 | count--; | |
537 | } | |
538 | return ret; | |
539 | } | |
540 | ||
1da177e4 LT |
541 | /** |
542 | * msi_capability_init - configure device's MSI capability structure | |
543 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 544 | * @nvec: number of interrupts to allocate |
1da177e4 | 545 | * |
1c8d7b0a MW |
546 | * Setup the MSI capability structure of the device with the requested |
547 | * number of interrupts. A return value of zero indicates the successful | |
548 | * setup of an entry with the new MSI irq. A negative return value indicates | |
549 | * an error, and a positive return value indicates the number of interrupts | |
550 | * which could have been allocated. | |
551 | */ | |
552 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
553 | { |
554 | struct msi_desc *entry; | |
7fe3730d | 555 | int pos, ret; |
1da177e4 | 556 | u16 control; |
f2440d9a | 557 | unsigned mask; |
1da177e4 | 558 | |
500559a9 | 559 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
110828c9 MW |
560 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
561 | ||
1da177e4 LT |
562 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
563 | /* MSI Entry Initialization */ | |
379f5327 | 564 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
565 | if (!entry) |
566 | return -ENOMEM; | |
1ce03373 | 567 | |
500559a9 HS |
568 | entry->msi_attrib.is_msix = 0; |
569 | entry->msi_attrib.is_64 = is_64bit_address(control); | |
570 | entry->msi_attrib.entry_nr = 0; | |
571 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
572 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
573 | entry->msi_attrib.pos = pos; | |
f2440d9a | 574 | |
67b5db65 | 575 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
576 | /* All MSIs are unmasked by default, Mask them all */ |
577 | if (entry->msi_attrib.maskbit) | |
578 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
579 | mask = msi_capable_mask(control); | |
580 | msi_mask_irq(entry, mask, mask); | |
581 | ||
0dd11f9b | 582 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 583 | |
1da177e4 | 584 | /* Configure MSI capability structure */ |
1c8d7b0a | 585 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 586 | if (ret) { |
7ba1930d | 587 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 588 | free_msi_irqs(dev); |
7fe3730d | 589 | return ret; |
fd58e55f | 590 | } |
f7feaca7 | 591 | |
da8d1c8b NH |
592 | ret = populate_msi_sysfs(dev); |
593 | if (ret) { | |
594 | msi_mask_irq(entry, mask, ~mask); | |
595 | free_msi_irqs(dev); | |
596 | return ret; | |
597 | } | |
598 | ||
1da177e4 | 599 | /* Set MSI enabled bits */ |
ba698ad4 | 600 | pci_intx_for_msi(dev, 0); |
110828c9 | 601 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 602 | dev->msi_enabled = 1; |
1da177e4 | 603 | |
7fe3730d | 604 | dev->irq = entry->irq; |
1da177e4 LT |
605 | return 0; |
606 | } | |
607 | ||
5a05a9d8 HS |
608 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, |
609 | unsigned nr_entries) | |
610 | { | |
4302e0fb | 611 | resource_size_t phys_addr; |
5a05a9d8 HS |
612 | u32 table_offset; |
613 | u8 bir; | |
614 | ||
615 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
616 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
617 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; | |
618 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
619 | ||
620 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
621 | } | |
622 | ||
d9d7070e HS |
623 | static int msix_setup_entries(struct pci_dev *dev, unsigned pos, |
624 | void __iomem *base, struct msix_entry *entries, | |
625 | int nvec) | |
626 | { | |
627 | struct msi_desc *entry; | |
628 | int i; | |
629 | ||
630 | for (i = 0; i < nvec; i++) { | |
631 | entry = alloc_msi_entry(dev); | |
632 | if (!entry) { | |
633 | if (!i) | |
634 | iounmap(base); | |
635 | else | |
636 | free_msi_irqs(dev); | |
637 | /* No enough memory. Don't try again */ | |
638 | return -ENOMEM; | |
639 | } | |
640 | ||
641 | entry->msi_attrib.is_msix = 1; | |
642 | entry->msi_attrib.is_64 = 1; | |
643 | entry->msi_attrib.entry_nr = entries[i].entry; | |
644 | entry->msi_attrib.default_irq = dev->irq; | |
645 | entry->msi_attrib.pos = pos; | |
646 | entry->mask_base = base; | |
647 | ||
648 | list_add_tail(&entry->list, &dev->msi_list); | |
649 | } | |
650 | ||
651 | return 0; | |
652 | } | |
653 | ||
75cb3426 HS |
654 | static void msix_program_entries(struct pci_dev *dev, |
655 | struct msix_entry *entries) | |
656 | { | |
657 | struct msi_desc *entry; | |
658 | int i = 0; | |
659 | ||
660 | list_for_each_entry(entry, &dev->msi_list, list) { | |
661 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
662 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
663 | ||
664 | entries[i].vector = entry->irq; | |
dced35ae | 665 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
666 | entry->masked = readl(entry->mask_base + offset); |
667 | msix_mask_irq(entry, 1); | |
668 | i++; | |
669 | } | |
670 | } | |
671 | ||
1da177e4 LT |
672 | /** |
673 | * msix_capability_init - configure device's MSI-X capability | |
674 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
675 | * @entries: pointer to an array of struct msix_entry entries |
676 | * @nvec: number of @entries | |
1da177e4 | 677 | * |
eaae4b3a | 678 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
679 | * single MSI-X irq. A return of zero indicates the successful setup of |
680 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
681 | **/ |
682 | static int msix_capability_init(struct pci_dev *dev, | |
683 | struct msix_entry *entries, int nvec) | |
684 | { | |
d9d7070e | 685 | int pos, ret; |
5a05a9d8 | 686 | u16 control; |
1da177e4 LT |
687 | void __iomem *base; |
688 | ||
500559a9 | 689 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
f598282f MW |
690 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
691 | ||
692 | /* Ensure MSI-X is disabled while it is set up */ | |
693 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
694 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
695 | ||
1da177e4 | 696 | /* Request & Map MSI-X table region */ |
5a05a9d8 HS |
697 | base = msix_map_region(dev, pos, multi_msix_capable(control)); |
698 | if (!base) | |
1da177e4 LT |
699 | return -ENOMEM; |
700 | ||
d9d7070e HS |
701 | ret = msix_setup_entries(dev, pos, base, entries, nvec); |
702 | if (ret) | |
703 | return ret; | |
9c831334 ME |
704 | |
705 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
706 | if (ret) |
707 | goto error; | |
9c831334 | 708 | |
f598282f MW |
709 | /* |
710 | * Some devices require MSI-X to be enabled before we can touch the | |
711 | * MSI-X registers. We need to mask all the vectors to prevent | |
712 | * interrupts coming in before they're fully set up. | |
713 | */ | |
714 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
715 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
716 | ||
75cb3426 | 717 | msix_program_entries(dev, entries); |
f598282f | 718 | |
da8d1c8b NH |
719 | ret = populate_msi_sysfs(dev); |
720 | if (ret) { | |
721 | ret = 0; | |
722 | goto error; | |
723 | } | |
724 | ||
f598282f | 725 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 726 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 727 | dev->msix_enabled = 1; |
1da177e4 | 728 | |
f598282f MW |
729 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
730 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 731 | |
1da177e4 | 732 | return 0; |
583871d4 HS |
733 | |
734 | error: | |
735 | if (ret < 0) { | |
736 | /* | |
737 | * If we had some success, report the number of irqs | |
738 | * we succeeded in setting up. | |
739 | */ | |
d9d7070e | 740 | struct msi_desc *entry; |
583871d4 HS |
741 | int avail = 0; |
742 | ||
743 | list_for_each_entry(entry, &dev->msi_list, list) { | |
744 | if (entry->irq != 0) | |
745 | avail++; | |
746 | } | |
747 | if (avail != 0) | |
748 | ret = avail; | |
749 | } | |
750 | ||
751 | free_msi_irqs(dev); | |
752 | ||
753 | return ret; | |
1da177e4 LT |
754 | } |
755 | ||
24334a12 | 756 | /** |
17bbc12a | 757 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 758 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 759 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 760 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 761 | * |
0306ebfa | 762 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
763 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
764 | * supported return 0, else return an error code. | |
24334a12 | 765 | **/ |
500559a9 | 766 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
767 | { |
768 | struct pci_bus *bus; | |
c9953a73 | 769 | int ret; |
24334a12 | 770 | |
0306ebfa | 771 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
772 | if (!pci_msi_enable || !dev || dev->no_msi) |
773 | return -EINVAL; | |
774 | ||
314e77b3 ME |
775 | /* |
776 | * You can't ask to have 0 or less MSIs configured. | |
777 | * a) it's stupid .. | |
778 | * b) the list manipulation code assumes nvec >= 1. | |
779 | */ | |
780 | if (nvec < 1) | |
781 | return -ERANGE; | |
782 | ||
500559a9 HS |
783 | /* |
784 | * Any bridge which does NOT route MSI transactions from its | |
785 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
786 | * the secondary pci_bus. |
787 | * We expect only arch-specific PCI host bus controller driver | |
788 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
789 | */ | |
24334a12 BG |
790 | for (bus = dev->bus; bus; bus = bus->parent) |
791 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
792 | return -EINVAL; | |
793 | ||
c9953a73 ME |
794 | ret = arch_msi_check_device(dev, nvec, type); |
795 | if (ret) | |
796 | return ret; | |
797 | ||
b1e2303d ME |
798 | if (!pci_find_capability(dev, type)) |
799 | return -EINVAL; | |
800 | ||
24334a12 BG |
801 | return 0; |
802 | } | |
803 | ||
1da177e4 | 804 | /** |
1c8d7b0a MW |
805 | * pci_enable_msi_block - configure device's MSI capability structure |
806 | * @dev: device to configure | |
807 | * @nvec: number of interrupts to configure | |
1da177e4 | 808 | * |
1c8d7b0a MW |
809 | * Allocate IRQs for a device with the MSI capability. |
810 | * This function returns a negative errno if an error occurs. If it | |
811 | * is unable to allocate the number of interrupts requested, it returns | |
812 | * the number of interrupts it might be able to allocate. If it successfully | |
813 | * allocates at least the number of interrupts requested, it returns 0 and | |
814 | * updates the @dev's irq member to the lowest new interrupt number; the | |
815 | * other interrupt numbers allocated to this device are consecutive. | |
816 | */ | |
817 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 818 | { |
1c8d7b0a MW |
819 | int status, pos, maxvec; |
820 | u16 msgctl; | |
821 | ||
822 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
823 | if (!pos) | |
824 | return -EINVAL; | |
825 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
826 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
827 | if (nvec > maxvec) | |
828 | return maxvec; | |
1da177e4 | 829 | |
1c8d7b0a | 830 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
831 | if (status) |
832 | return status; | |
1da177e4 | 833 | |
ded86d8d | 834 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 835 | |
1c8d7b0a | 836 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 837 | if (dev->msix_enabled) { |
80ccba11 BH |
838 | dev_info(&dev->dev, "can't enable MSI " |
839 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 840 | return -EINVAL; |
1da177e4 | 841 | } |
1c8d7b0a MW |
842 | |
843 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
844 | return status; |
845 | } | |
1c8d7b0a | 846 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 847 | |
08261d87 AG |
848 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
849 | { | |
850 | int ret, pos, nvec; | |
851 | u16 msgctl; | |
852 | ||
853 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
854 | if (!pos) | |
855 | return -EINVAL; | |
856 | ||
857 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
858 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
859 | ||
860 | if (maxvec) | |
861 | *maxvec = ret; | |
862 | ||
863 | do { | |
864 | nvec = ret; | |
865 | ret = pci_enable_msi_block(dev, nvec); | |
866 | } while (ret > 0); | |
867 | ||
868 | if (ret < 0) | |
869 | return ret; | |
870 | return nvec; | |
871 | } | |
872 | EXPORT_SYMBOL(pci_enable_msi_block_auto); | |
873 | ||
f2440d9a | 874 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 875 | { |
f2440d9a MW |
876 | struct msi_desc *desc; |
877 | u32 mask; | |
878 | u16 ctrl; | |
110828c9 | 879 | unsigned pos; |
1da177e4 | 880 | |
128bc5fc | 881 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
882 | return; |
883 | ||
110828c9 MW |
884 | BUG_ON(list_empty(&dev->msi_list)); |
885 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
886 | pos = desc->msi_attrib.pos; | |
887 | ||
888 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 889 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 890 | dev->msi_enabled = 0; |
7bd007e4 | 891 | |
12abb8ba | 892 | /* Return the device with MSI unmasked as initial states */ |
110828c9 | 893 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 894 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
895 | /* Keep cached state to be restored */ |
896 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
897 | |
898 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 899 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 900 | } |
24d27553 | 901 | |
500559a9 | 902 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 903 | { |
d52877c7 YL |
904 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
905 | return; | |
906 | ||
907 | pci_msi_shutdown(dev); | |
f56e4481 | 908 | free_msi_irqs(dev); |
da8d1c8b NH |
909 | kset_unregister(dev->msi_kset); |
910 | dev->msi_kset = NULL; | |
1da177e4 | 911 | } |
4cc086fa | 912 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 913 | |
a52e2e35 RW |
914 | /** |
915 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
916 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
917 | */ | |
918 | int pci_msix_table_size(struct pci_dev *dev) | |
919 | { | |
920 | int pos; | |
921 | u16 control; | |
922 | ||
923 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
924 | if (!pos) | |
925 | return 0; | |
926 | ||
927 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
928 | return multi_msix_capable(control); | |
929 | } | |
930 | ||
1da177e4 LT |
931 | /** |
932 | * pci_enable_msix - configure device's MSI-X capability structure | |
933 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 934 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 935 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
936 | * |
937 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 938 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
939 | * MSI-X mode enabled on its hardware device function. A return of zero |
940 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 941 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 942 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
943 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
944 | * re-send its request. | |
1da177e4 | 945 | **/ |
500559a9 | 946 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 947 | { |
a52e2e35 | 948 | int status, nr_entries; |
ded86d8d | 949 | int i, j; |
1da177e4 | 950 | |
c9953a73 | 951 | if (!entries) |
500559a9 | 952 | return -EINVAL; |
1da177e4 | 953 | |
c9953a73 ME |
954 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
955 | if (status) | |
956 | return status; | |
957 | ||
a52e2e35 | 958 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 959 | if (nvec > nr_entries) |
57fbf52c | 960 | return nr_entries; |
1da177e4 LT |
961 | |
962 | /* Check for any invalid entries */ | |
963 | for (i = 0; i < nvec; i++) { | |
964 | if (entries[i].entry >= nr_entries) | |
965 | return -EINVAL; /* invalid entry */ | |
966 | for (j = i + 1; j < nvec; j++) { | |
967 | if (entries[i].entry == entries[j].entry) | |
968 | return -EINVAL; /* duplicate entry */ | |
969 | } | |
970 | } | |
ded86d8d | 971 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 972 | |
1ce03373 | 973 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 974 | if (dev->msi_enabled) { |
80ccba11 BH |
975 | dev_info(&dev->dev, "can't enable MSI-X " |
976 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
977 | return -EINVAL; |
978 | } | |
1da177e4 | 979 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
980 | return status; |
981 | } | |
4cc086fa | 982 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 983 | |
500559a9 | 984 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 985 | { |
12abb8ba HS |
986 | struct msi_desc *entry; |
987 | ||
128bc5fc | 988 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
989 | return; |
990 | ||
12abb8ba HS |
991 | /* Return the device with MSI-X masked as initial states */ |
992 | list_for_each_entry(entry, &dev->msi_list, list) { | |
993 | /* Keep cached states to be restored */ | |
994 | __msix_mask_irq(entry, 1); | |
995 | } | |
996 | ||
b1cbf4e4 | 997 | msix_set_enable(dev, 0); |
ba698ad4 | 998 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 999 | dev->msix_enabled = 0; |
d52877c7 | 1000 | } |
c901851f | 1001 | |
500559a9 | 1002 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1003 | { |
1004 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1005 | return; | |
1006 | ||
1007 | pci_msix_shutdown(dev); | |
f56e4481 | 1008 | free_msi_irqs(dev); |
da8d1c8b NH |
1009 | kset_unregister(dev->msi_kset); |
1010 | dev->msi_kset = NULL; | |
1da177e4 | 1011 | } |
4cc086fa | 1012 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1013 | |
1014 | /** | |
1ce03373 | 1015 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1016 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1017 | * | |
eaae4b3a | 1018 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1019 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1020 | * allocated for this device function, are reclaimed to unused state, |
1021 | * which may be used later on. | |
1022 | **/ | |
500559a9 | 1023 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1024 | { |
1da177e4 | 1025 | if (!pci_msi_enable || !dev) |
500559a9 | 1026 | return; |
1da177e4 | 1027 | |
f56e4481 HS |
1028 | if (dev->msi_enabled || dev->msix_enabled) |
1029 | free_msi_irqs(dev); | |
1da177e4 LT |
1030 | } |
1031 | ||
309e57df MW |
1032 | void pci_no_msi(void) |
1033 | { | |
1034 | pci_msi_enable = 0; | |
1035 | } | |
c9953a73 | 1036 | |
07ae95f9 AP |
1037 | /** |
1038 | * pci_msi_enabled - is MSI enabled? | |
1039 | * | |
1040 | * Returns true if MSI has not been disabled by the command-line option | |
1041 | * pci=nomsi. | |
1042 | **/ | |
1043 | int pci_msi_enabled(void) | |
d389fec6 | 1044 | { |
07ae95f9 | 1045 | return pci_msi_enable; |
d389fec6 | 1046 | } |
07ae95f9 | 1047 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1048 | |
07ae95f9 | 1049 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1050 | { |
d5dea7d9 | 1051 | int pos; |
07ae95f9 | 1052 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1053 | |
1054 | /* Disable the msi hardware to avoid screaming interrupts | |
1055 | * during boot. This is the power on reset default so | |
1056 | * usually this should be a noop. | |
1057 | */ | |
1058 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1059 | if (pos) | |
1060 | msi_set_enable(dev, pos, 0); | |
1061 | msix_set_enable(dev, 0); | |
d389fec6 | 1062 | } |