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Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Message Signaled Interrupt (MSI) |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
aff17164 | 7 | * Copyright (C) 2016 Christoph Hellwig. |
1da177e4 LT |
8 | */ |
9 | ||
1ce03373 | 10 | #include <linux/err.h> |
1da177e4 LT |
11 | #include <linux/mm.h> |
12 | #include <linux/irq.h> | |
13 | #include <linux/interrupt.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
be2021ba | 22 | #include <linux/acpi_iort.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
3878eaef | 24 | #include <linux/irqdomain.h> |
b6eec9b7 | 25 | #include <linux/of_irq.h> |
1da177e4 LT |
26 | |
27 | #include "pci.h" | |
1da177e4 | 28 | |
cbc40d5c BH |
29 | #ifdef CONFIG_PCI_MSI |
30 | ||
1da177e4 | 31 | static int pci_msi_enable = 1; |
38737d82 | 32 | int pci_msi_ignore_mask; |
1da177e4 | 33 | |
527eee29 BH |
34 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
35 | ||
8e047ada | 36 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
8e047ada JL |
37 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
38 | { | |
39 | struct irq_domain *domain; | |
40 | ||
47feb418 | 41 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 42 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 43 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); |
8e047ada JL |
44 | |
45 | return arch_setup_msi_irqs(dev, nvec, type); | |
46 | } | |
47 | ||
48 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
49 | { | |
50 | struct irq_domain *domain; | |
51 | ||
47feb418 | 52 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 53 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 54 | msi_domain_free_irqs(domain, &dev->dev); |
8e047ada JL |
55 | else |
56 | arch_teardown_msi_irqs(dev); | |
57 | } | |
58 | #else | |
59 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
60 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
61 | #endif | |
527eee29 | 62 | |
077ee78e | 63 | #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS |
6a9e7f20 | 64 | /* Arch hooks */ |
4287d824 TP |
65 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
66 | { | |
3a05d08f | 67 | return -EINVAL; |
4287d824 TP |
68 | } |
69 | ||
70 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 71 | { |
6a9e7f20 AB |
72 | } |
73 | ||
4287d824 | 74 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
75 | { |
76 | struct msi_desc *entry; | |
77 | int ret; | |
78 | ||
1c8d7b0a MW |
79 | /* |
80 | * If an architecture wants to support multiple MSI, it needs to | |
81 | * override arch_setup_msi_irqs() | |
82 | */ | |
83 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
84 | return 1; | |
85 | ||
5004e98a | 86 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 87 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 88 | if (ret < 0) |
6a9e7f20 | 89 | return ret; |
b5fbf533 ME |
90 | if (ret > 0) |
91 | return -ENOSPC; | |
6a9e7f20 AB |
92 | } |
93 | ||
94 | return 0; | |
95 | } | |
1525bf0d | 96 | |
f8bcf249 | 97 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 98 | { |
63a7b17e | 99 | int i; |
6a9e7f20 AB |
100 | struct msi_desc *entry; |
101 | ||
5004e98a | 102 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
103 | if (entry->irq) |
104 | for (i = 0; i < entry->nvec_used; i++) | |
105 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 | 106 | } |
077ee78e | 107 | #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */ |
76ccc297 | 108 | |
ac8344c4 | 109 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
110 | { |
111 | struct msi_desc *entry; | |
112 | ||
113 | entry = NULL; | |
114 | if (dev->msix_enabled) { | |
5004e98a | 115 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
116 | if (irq == entry->irq) |
117 | break; | |
118 | } | |
119 | } else if (dev->msi_enabled) { | |
120 | entry = irq_get_msi_desc(irq); | |
121 | } | |
122 | ||
123 | if (entry) | |
83a18912 | 124 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 125 | } |
4287d824 | 126 | |
ac8344c4 | 127 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 128 | { |
ac8344c4 | 129 | return default_restore_msi_irqs(dev); |
4287d824 | 130 | } |
76ccc297 | 131 | |
bffac3c5 MW |
132 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
133 | { | |
0b49ec37 MW |
134 | /* Don't shift by >= width of type */ |
135 | if (x >= 5) | |
136 | return 0xffffffff; | |
137 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
138 | } |
139 | ||
ce6fce42 MW |
140 | /* |
141 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
142 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
143 | * reliably as devices without an INTx disable bit will then generate a | |
144 | * level IRQ which will never be cleared. | |
ce6fce42 | 145 | */ |
23ed8d57 | 146 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 147 | { |
f2440d9a | 148 | u32 mask_bits = desc->masked; |
1da177e4 | 149 | |
38737d82 | 150 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 151 | return 0; |
f2440d9a MW |
152 | |
153 | mask_bits &= ~mask; | |
154 | mask_bits |= flag; | |
e39758e0 JL |
155 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
156 | mask_bits); | |
12abb8ba HS |
157 | |
158 | return mask_bits; | |
159 | } | |
160 | ||
161 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
162 | { | |
23ed8d57 | 163 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
164 | } |
165 | ||
5eb6d660 CH |
166 | static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) |
167 | { | |
d7cc609f LG |
168 | if (desc->msi_attrib.is_virtual) |
169 | return NULL; | |
170 | ||
5eb6d660 CH |
171 | return desc->mask_base + |
172 | desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
173 | } | |
174 | ||
f2440d9a MW |
175 | /* |
176 | * This internal function does not flush PCI writes to the device. | |
177 | * All users must ensure that they read from the device before either | |
178 | * assuming that the device state is up to date, or returning out of this | |
179 | * file. This saves a few milliseconds when initialising devices with lots | |
180 | * of MSI-X interrupts. | |
181 | */ | |
23ed8d57 | 182 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
183 | { |
184 | u32 mask_bits = desc->masked; | |
d7cc609f | 185 | void __iomem *desc_addr; |
38737d82 YW |
186 | |
187 | if (pci_msi_ignore_mask) | |
188 | return 0; | |
e045fa29 | 189 | |
d7cc609f LG |
190 | desc_addr = pci_msix_desc_addr(desc); |
191 | if (!desc_addr) | |
192 | return 0; | |
38737d82 | 193 | |
8d805286 | 194 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
e045fa29 | 195 | if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT) |
8d805286 | 196 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; |
d7cc609f LG |
197 | |
198 | writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL); | |
12abb8ba HS |
199 | |
200 | return mask_bits; | |
201 | } | |
202 | ||
203 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
204 | { | |
23ed8d57 | 205 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 206 | } |
24d27553 | 207 | |
1c9db525 | 208 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 209 | { |
c391f262 | 210 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
24d27553 | 211 | |
f2440d9a MW |
212 | if (desc->msi_attrib.is_msix) { |
213 | msix_mask_irq(desc, flag); | |
214 | readl(desc->mask_base); /* Flush write to device */ | |
215 | } else { | |
a281b788 | 216 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 217 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 218 | } |
f2440d9a MW |
219 | } |
220 | ||
23ed8d57 | 221 | /** |
f6b6aefe | 222 | * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts |
23ed8d57 TG |
223 | * @data: pointer to irqdata associated to that interrupt |
224 | */ | |
225 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 226 | { |
1c9db525 | 227 | msi_set_mask_bit(data, 1); |
f2440d9a | 228 | } |
a4289dc2 | 229 | EXPORT_SYMBOL_GPL(pci_msi_mask_irq); |
f2440d9a | 230 | |
23ed8d57 | 231 | /** |
f6b6aefe | 232 | * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts |
23ed8d57 TG |
233 | * @data: pointer to irqdata associated to that interrupt |
234 | */ | |
235 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 236 | { |
1c9db525 | 237 | msi_set_mask_bit(data, 0); |
1da177e4 | 238 | } |
a4289dc2 | 239 | EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); |
1da177e4 | 240 | |
ac8344c4 D |
241 | void default_restore_msi_irqs(struct pci_dev *dev) |
242 | { | |
243 | struct msi_desc *entry; | |
244 | ||
5004e98a | 245 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 246 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
247 | } |
248 | ||
891d4a48 | 249 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 250 | { |
e39758e0 JL |
251 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
252 | ||
253 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
254 | |
255 | if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 256 | void __iomem *base = pci_msix_desc_addr(entry); |
30da5524 | 257 | |
d7cc609f LG |
258 | if (!base) { |
259 | WARN_ON(1); | |
260 | return; | |
261 | } | |
262 | ||
30da5524 BH |
263 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); |
264 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
265 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
266 | } else { | |
f5322169 | 267 | int pos = dev->msi_cap; |
30da5524 BH |
268 | u16 data; |
269 | ||
9925ad0c BH |
270 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
271 | &msg->address_lo); | |
30da5524 | 272 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
273 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
274 | &msg->address_hi); | |
2f221349 | 275 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
276 | } else { |
277 | msg->address_hi = 0; | |
2f221349 | 278 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
279 | } |
280 | msg->data = data; | |
281 | } | |
282 | } | |
283 | ||
83a18912 | 284 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 285 | { |
e39758e0 JL |
286 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
287 | ||
0170591b | 288 | if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) { |
fcd097f3 BH |
289 | /* Don't touch the hardware now */ |
290 | } else if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 291 | void __iomem *base = pci_msix_desc_addr(entry); |
24d27553 | 292 | |
d7cc609f LG |
293 | if (!base) |
294 | goto skip; | |
295 | ||
2c21fd4b HS |
296 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
297 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
298 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 299 | } else { |
f5322169 | 300 | int pos = dev->msi_cap; |
1c8d7b0a MW |
301 | u16 msgctl; |
302 | ||
f84ecd28 | 303 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
304 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
305 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 306 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 307 | |
9925ad0c BH |
308 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
309 | msg->address_lo); | |
0366f8f7 | 310 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
311 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
312 | msg->address_hi); | |
2f221349 BH |
313 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
314 | msg->data); | |
0366f8f7 | 315 | } else { |
2f221349 BH |
316 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
317 | msg->data); | |
0366f8f7 | 318 | } |
1da177e4 | 319 | } |
d7cc609f LG |
320 | |
321 | skip: | |
392ee1e6 | 322 | entry->msg = *msg; |
d7cc609f LG |
323 | |
324 | if (entry->write_msi_msg) | |
325 | entry->write_msi_msg(entry, entry->write_msi_msg_data); | |
326 | ||
1da177e4 | 327 | } |
0366f8f7 | 328 | |
83a18912 | 329 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 330 | { |
dced35ae | 331 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 332 | |
83a18912 | 333 | __pci_write_msi_msg(entry, msg); |
3145e941 | 334 | } |
83a18912 | 335 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 336 | |
f56e4481 HS |
337 | static void free_msi_irqs(struct pci_dev *dev) |
338 | { | |
5004e98a | 339 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 340 | struct msi_desc *entry, *tmp; |
1c51b50c GKH |
341 | struct attribute **msi_attrs; |
342 | struct device_attribute *dev_attr; | |
63a7b17e | 343 | int i, count = 0; |
f56e4481 | 344 | |
5004e98a | 345 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
346 | if (entry->irq) |
347 | for (i = 0; i < entry->nvec_used; i++) | |
348 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 349 | |
8e047ada | 350 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 351 | |
5004e98a | 352 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 353 | if (entry->msi_attrib.is_msix) { |
5004e98a | 354 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
355 | iounmap(entry->mask_base); |
356 | } | |
424eb391 | 357 | |
f56e4481 | 358 | list_del(&entry->list); |
81efbadd | 359 | free_msi_entry(entry); |
f56e4481 | 360 | } |
1c51b50c GKH |
361 | |
362 | if (dev->msi_irq_groups) { | |
363 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
364 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 365 | while (msi_attrs[count]) { |
1c51b50c GKH |
366 | dev_attr = container_of(msi_attrs[count], |
367 | struct device_attribute, attr); | |
368 | kfree(dev_attr->attr.name); | |
369 | kfree(dev_attr); | |
370 | ++count; | |
371 | } | |
372 | kfree(msi_attrs); | |
373 | kfree(dev->msi_irq_groups[0]); | |
374 | kfree(dev->msi_irq_groups); | |
375 | dev->msi_irq_groups = NULL; | |
376 | } | |
f56e4481 | 377 | } |
c54c1879 | 378 | |
ba698ad4 DM |
379 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
380 | { | |
381 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
382 | pci_intx(dev, enable); | |
383 | } | |
384 | ||
830dfe88 BH |
385 | static void pci_msi_set_enable(struct pci_dev *dev, int enable) |
386 | { | |
387 | u16 control; | |
388 | ||
389 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
390 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
391 | if (enable) | |
392 | control |= PCI_MSI_FLAGS_ENABLE; | |
393 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
394 | } | |
395 | ||
8fed4b65 | 396 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 397 | { |
41017f0c | 398 | u16 control; |
392ee1e6 | 399 | struct msi_desc *entry; |
41017f0c | 400 | |
b1cbf4e4 EB |
401 | if (!dev->msi_enabled) |
402 | return; | |
403 | ||
dced35ae | 404 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 405 | |
ba698ad4 | 406 | pci_intx_for_msi(dev, 0); |
61b64abd | 407 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 408 | arch_restore_msi_irqs(dev); |
392ee1e6 | 409 | |
f5322169 | 410 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
411 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
412 | entry->masked); | |
abad2ec9 | 413 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 414 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 415 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
416 | } |
417 | ||
830dfe88 BH |
418 | static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
419 | { | |
420 | u16 ctrl; | |
421 | ||
422 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
423 | ctrl &= ~clear; | |
424 | ctrl |= set; | |
425 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
426 | } | |
427 | ||
8fed4b65 | 428 | static void __pci_restore_msix_state(struct pci_dev *dev) |
41017f0c | 429 | { |
41017f0c | 430 | struct msi_desc *entry; |
41017f0c | 431 | |
ded86d8d EB |
432 | if (!dev->msix_enabled) |
433 | return; | |
5004e98a | 434 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 435 | |
41017f0c | 436 | /* route the table */ |
ba698ad4 | 437 | pci_intx_for_msi(dev, 0); |
61b64abd | 438 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 439 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 440 | |
ac8344c4 | 441 | arch_restore_msi_irqs(dev); |
5004e98a | 442 | for_each_pci_msi_entry(entry, dev) |
f2440d9a | 443 | msix_mask_irq(entry, entry->masked); |
41017f0c | 444 | |
61b64abd | 445 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 446 | } |
8fed4b65 ME |
447 | |
448 | void pci_restore_msi_state(struct pci_dev *dev) | |
449 | { | |
450 | __pci_restore_msi_state(dev); | |
451 | __pci_restore_msix_state(dev); | |
452 | } | |
94688cf2 | 453 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 454 | |
1c51b50c | 455 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
456 | char *buf) |
457 | { | |
1c51b50c GKH |
458 | struct msi_desc *entry; |
459 | unsigned long irq; | |
460 | int retval; | |
da8d1c8b | 461 | |
1c51b50c GKH |
462 | retval = kstrtoul(attr->attr.name, 10, &irq); |
463 | if (retval) | |
464 | return retval; | |
da8d1c8b | 465 | |
e11ece5a YW |
466 | entry = irq_get_msi_desc(irq); |
467 | if (entry) | |
468 | return sprintf(buf, "%s\n", | |
469 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
470 | ||
1c51b50c | 471 | return -ENODEV; |
da8d1c8b NH |
472 | } |
473 | ||
da8d1c8b NH |
474 | static int populate_msi_sysfs(struct pci_dev *pdev) |
475 | { | |
1c51b50c GKH |
476 | struct attribute **msi_attrs; |
477 | struct attribute *msi_attr; | |
478 | struct device_attribute *msi_dev_attr; | |
479 | struct attribute_group *msi_irq_group; | |
480 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 481 | struct msi_desc *entry; |
1c51b50c GKH |
482 | int ret = -ENOMEM; |
483 | int num_msi = 0; | |
da8d1c8b | 484 | int count = 0; |
a8676066 | 485 | int i; |
da8d1c8b | 486 | |
1c51b50c | 487 | /* Determine how many msi entries we have */ |
5004e98a | 488 | for_each_pci_msi_entry(entry, pdev) |
a8676066 | 489 | num_msi += entry->nvec_used; |
1c51b50c GKH |
490 | if (!num_msi) |
491 | return 0; | |
da8d1c8b | 492 | |
1c51b50c | 493 | /* Dynamically create the MSI attributes for the PCI device */ |
6396bb22 | 494 | msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL); |
1c51b50c GKH |
495 | if (!msi_attrs) |
496 | return -ENOMEM; | |
5004e98a | 497 | for_each_pci_msi_entry(entry, pdev) { |
a8676066 RB |
498 | for (i = 0; i < entry->nvec_used; i++) { |
499 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); | |
500 | if (!msi_dev_attr) | |
501 | goto error_attrs; | |
502 | msi_attrs[count] = &msi_dev_attr->attr; | |
503 | ||
504 | sysfs_attr_init(&msi_dev_attr->attr); | |
505 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", | |
506 | entry->irq + i); | |
507 | if (!msi_dev_attr->attr.name) | |
508 | goto error_attrs; | |
509 | msi_dev_attr->attr.mode = S_IRUGO; | |
510 | msi_dev_attr->show = msi_mode_show; | |
511 | ++count; | |
512 | } | |
da8d1c8b NH |
513 | } |
514 | ||
1c51b50c GKH |
515 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
516 | if (!msi_irq_group) | |
517 | goto error_attrs; | |
518 | msi_irq_group->name = "msi_irqs"; | |
519 | msi_irq_group->attrs = msi_attrs; | |
520 | ||
6396bb22 | 521 | msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL); |
1c51b50c GKH |
522 | if (!msi_irq_groups) |
523 | goto error_irq_group; | |
524 | msi_irq_groups[0] = msi_irq_group; | |
525 | ||
526 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
527 | if (ret) | |
528 | goto error_irq_groups; | |
529 | pdev->msi_irq_groups = msi_irq_groups; | |
530 | ||
da8d1c8b NH |
531 | return 0; |
532 | ||
1c51b50c GKH |
533 | error_irq_groups: |
534 | kfree(msi_irq_groups); | |
535 | error_irq_group: | |
536 | kfree(msi_irq_group); | |
537 | error_attrs: | |
538 | count = 0; | |
539 | msi_attr = msi_attrs[count]; | |
540 | while (msi_attr) { | |
541 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
542 | kfree(msi_attr->name); | |
543 | kfree(msi_dev_attr); | |
544 | ++count; | |
545 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 546 | } |
29237756 | 547 | kfree(msi_attrs); |
da8d1c8b NH |
548 | return ret; |
549 | } | |
550 | ||
e75eafb9 | 551 | static struct msi_desc * |
c66d4bd1 | 552 | msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd) |
d873b4d4 | 553 | { |
bec04037 | 554 | struct irq_affinity_desc *masks = NULL; |
d873b4d4 | 555 | struct msi_desc *entry; |
e75eafb9 TG |
556 | u16 control; |
557 | ||
8e1101d2 | 558 | if (affd) |
61e1c590 | 559 | masks = irq_create_affinity_masks(nvec, affd); |
8e1101d2 | 560 | |
d873b4d4 | 561 | /* MSI Entry Initialization */ |
e75eafb9 | 562 | entry = alloc_msi_entry(&dev->dev, nvec, masks); |
d873b4d4 | 563 | if (!entry) |
e75eafb9 | 564 | goto out; |
d873b4d4 YW |
565 | |
566 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
567 | ||
568 | entry->msi_attrib.is_msix = 0; | |
569 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
d7cc609f | 570 | entry->msi_attrib.is_virtual = 0; |
d873b4d4 YW |
571 | entry->msi_attrib.entry_nr = 0; |
572 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
573 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 574 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e | 575 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
d873b4d4 YW |
576 | |
577 | if (control & PCI_MSI_FLAGS_64BIT) | |
578 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
579 | else | |
580 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
581 | ||
582 | /* Save the initial mask status */ | |
583 | if (entry->msi_attrib.maskbit) | |
584 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
585 | ||
e75eafb9 TG |
586 | out: |
587 | kfree(masks); | |
d873b4d4 YW |
588 | return entry; |
589 | } | |
590 | ||
f144d149 BH |
591 | static int msi_verify_entries(struct pci_dev *dev) |
592 | { | |
593 | struct msi_desc *entry; | |
594 | ||
5004e98a | 595 | for_each_pci_msi_entry(entry, dev) { |
2053230a VS |
596 | if (entry->msg.address_hi && dev->no_64bit_msi) { |
597 | pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n", | |
598 | entry->msg.address_hi, entry->msg.address_lo); | |
599 | return -EIO; | |
600 | } | |
f144d149 BH |
601 | } |
602 | return 0; | |
603 | } | |
604 | ||
1da177e4 LT |
605 | /** |
606 | * msi_capability_init - configure device's MSI capability structure | |
607 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 608 | * @nvec: number of interrupts to allocate |
f6b6aefe | 609 | * @affd: description of automatic IRQ affinity assignments (may be %NULL) |
1da177e4 | 610 | * |
1c8d7b0a MW |
611 | * Setup the MSI capability structure of the device with the requested |
612 | * number of interrupts. A return value of zero indicates the successful | |
f6b6aefe | 613 | * setup of an entry with the new MSI IRQ. A negative return value indicates |
1c8d7b0a MW |
614 | * an error, and a positive return value indicates the number of interrupts |
615 | * which could have been allocated. | |
616 | */ | |
61e1c590 | 617 | static int msi_capability_init(struct pci_dev *dev, int nvec, |
c66d4bd1 | 618 | struct irq_affinity *affd) |
1da177e4 LT |
619 | { |
620 | struct msi_desc *entry; | |
f465136d | 621 | int ret; |
f2440d9a | 622 | unsigned mask; |
1da177e4 | 623 | |
61b64abd | 624 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 625 | |
61e1c590 | 626 | entry = msi_setup_entry(dev, nvec, affd); |
f7feaca7 EB |
627 | if (!entry) |
628 | return -ENOMEM; | |
1ce03373 | 629 | |
f6b6aefe | 630 | /* All MSIs are unmasked by default; mask them all */ |
31ea5d4d | 631 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
632 | msi_mask_irq(entry, mask, mask); |
633 | ||
5004e98a | 634 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 635 | |
1da177e4 | 636 | /* Configure MSI capability structure */ |
8e047ada | 637 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 638 | if (ret) { |
7ba1930d | 639 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 640 | free_msi_irqs(dev); |
7fe3730d | 641 | return ret; |
fd58e55f | 642 | } |
f7feaca7 | 643 | |
f144d149 BH |
644 | ret = msi_verify_entries(dev); |
645 | if (ret) { | |
646 | msi_mask_irq(entry, mask, ~mask); | |
647 | free_msi_irqs(dev); | |
648 | return ret; | |
649 | } | |
650 | ||
da8d1c8b NH |
651 | ret = populate_msi_sysfs(dev); |
652 | if (ret) { | |
653 | msi_mask_irq(entry, mask, ~mask); | |
654 | free_msi_irqs(dev); | |
655 | return ret; | |
656 | } | |
657 | ||
f6b6aefe | 658 | /* Set MSI enabled bits */ |
ba698ad4 | 659 | pci_intx_for_msi(dev, 0); |
61b64abd | 660 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 661 | dev->msi_enabled = 1; |
1da177e4 | 662 | |
5f226991 | 663 | pcibios_free_irq(dev); |
7fe3730d | 664 | dev->irq = entry->irq; |
1da177e4 LT |
665 | return 0; |
666 | } | |
667 | ||
520fe9dc | 668 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 669 | { |
4302e0fb | 670 | resource_size_t phys_addr; |
5a05a9d8 | 671 | u32 table_offset; |
6a878e50 | 672 | unsigned long flags; |
5a05a9d8 HS |
673 | u8 bir; |
674 | ||
909094c6 BH |
675 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
676 | &table_offset); | |
4d18760c | 677 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
678 | flags = pci_resource_flags(dev, bir); |
679 | if (!flags || (flags & IORESOURCE_UNSET)) | |
680 | return NULL; | |
681 | ||
4d18760c | 682 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
683 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
684 | ||
4bdc0d67 | 685 | return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
5a05a9d8 HS |
686 | } |
687 | ||
520fe9dc | 688 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
e75eafb9 | 689 | struct msix_entry *entries, int nvec, |
c66d4bd1 | 690 | struct irq_affinity *affd) |
d9d7070e | 691 | { |
bec04037 | 692 | struct irq_affinity_desc *curmsk, *masks = NULL; |
d9d7070e | 693 | struct msi_desc *entry; |
e75eafb9 | 694 | int ret, i; |
d7cc609f | 695 | int vec_count = pci_msix_vec_count(dev); |
4ef33685 | 696 | |
8e1101d2 | 697 | if (affd) |
61e1c590 | 698 | masks = irq_create_affinity_masks(nvec, affd); |
4ef33685 | 699 | |
e75eafb9 TG |
700 | for (i = 0, curmsk = masks; i < nvec; i++) { |
701 | entry = alloc_msi_entry(&dev->dev, 1, curmsk); | |
d9d7070e HS |
702 | if (!entry) { |
703 | if (!i) | |
704 | iounmap(base); | |
705 | else | |
706 | free_msi_irqs(dev); | |
707 | /* No enough memory. Don't try again */ | |
e75eafb9 TG |
708 | ret = -ENOMEM; |
709 | goto out; | |
d9d7070e HS |
710 | } |
711 | ||
712 | entry->msi_attrib.is_msix = 1; | |
713 | entry->msi_attrib.is_64 = 1; | |
3ac020e0 CH |
714 | if (entries) |
715 | entry->msi_attrib.entry_nr = entries[i].entry; | |
716 | else | |
717 | entry->msi_attrib.entry_nr = i; | |
d7cc609f LG |
718 | |
719 | entry->msi_attrib.is_virtual = | |
720 | entry->msi_attrib.entry_nr >= vec_count; | |
721 | ||
d9d7070e | 722 | entry->msi_attrib.default_irq = dev->irq; |
d9d7070e HS |
723 | entry->mask_base = base; |
724 | ||
5004e98a | 725 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
e75eafb9 TG |
726 | if (masks) |
727 | curmsk++; | |
d9d7070e | 728 | } |
e75eafb9 TG |
729 | ret = 0; |
730 | out: | |
731 | kfree(masks); | |
3adfb572 | 732 | return ret; |
d9d7070e HS |
733 | } |
734 | ||
75cb3426 | 735 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 736 | struct msix_entry *entries) |
75cb3426 HS |
737 | { |
738 | struct msi_desc *entry; | |
739 | int i = 0; | |
d7cc609f | 740 | void __iomem *desc_addr; |
75cb3426 | 741 | |
5004e98a | 742 | for_each_pci_msi_entry(entry, dev) { |
3ac020e0 CH |
743 | if (entries) |
744 | entries[i++].vector = entry->irq; | |
d7cc609f LG |
745 | |
746 | desc_addr = pci_msix_desc_addr(entry); | |
747 | if (desc_addr) | |
748 | entry->masked = readl(desc_addr + | |
749 | PCI_MSIX_ENTRY_VECTOR_CTRL); | |
750 | else | |
751 | entry->masked = 0; | |
752 | ||
75cb3426 | 753 | msix_mask_irq(entry, 1); |
75cb3426 HS |
754 | } |
755 | } | |
756 | ||
1da177e4 LT |
757 | /** |
758 | * msix_capability_init - configure device's MSI-X capability | |
759 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
760 | * @entries: pointer to an array of struct msix_entry entries |
761 | * @nvec: number of @entries | |
f6b6aefe | 762 | * @affd: Optional pointer to enable automatic affinity assignment |
1da177e4 | 763 | * |
eaae4b3a | 764 | * Setup the MSI-X capability structure of device function with a |
f6b6aefe BH |
765 | * single MSI-X IRQ. A return of zero indicates the successful setup of |
766 | * requested MSI-X entries with allocated IRQs or non-zero for otherwise. | |
1da177e4 | 767 | **/ |
e75eafb9 | 768 | static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries, |
c66d4bd1 | 769 | int nvec, struct irq_affinity *affd) |
1da177e4 | 770 | { |
520fe9dc | 771 | int ret; |
5a05a9d8 | 772 | u16 control; |
1da177e4 LT |
773 | void __iomem *base; |
774 | ||
f598282f | 775 | /* Ensure MSI-X is disabled while it is set up */ |
61b64abd | 776 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 777 | |
66f0d0c4 | 778 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 779 | /* Request & Map MSI-X table region */ |
527eee29 | 780 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 781 | if (!base) |
1da177e4 LT |
782 | return -ENOMEM; |
783 | ||
61e1c590 | 784 | ret = msix_setup_entries(dev, base, entries, nvec, affd); |
d9d7070e HS |
785 | if (ret) |
786 | return ret; | |
9c831334 | 787 | |
8e047ada | 788 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 789 | if (ret) |
2adc7907 | 790 | goto out_avail; |
9c831334 | 791 | |
f144d149 BH |
792 | /* Check if all MSI entries honor device restrictions */ |
793 | ret = msi_verify_entries(dev); | |
794 | if (ret) | |
795 | goto out_free; | |
796 | ||
f598282f MW |
797 | /* |
798 | * Some devices require MSI-X to be enabled before we can touch the | |
799 | * MSI-X registers. We need to mask all the vectors to prevent | |
800 | * interrupts coming in before they're fully set up. | |
801 | */ | |
61b64abd | 802 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 803 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
f598282f | 804 | |
75cb3426 | 805 | msix_program_entries(dev, entries); |
f598282f | 806 | |
da8d1c8b | 807 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
808 | if (ret) |
809 | goto out_free; | |
da8d1c8b | 810 | |
f598282f | 811 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 812 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 813 | dev->msix_enabled = 1; |
61b64abd | 814 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 815 | |
5f226991 | 816 | pcibios_free_irq(dev); |
1da177e4 | 817 | return 0; |
583871d4 | 818 | |
2adc7907 | 819 | out_avail: |
583871d4 HS |
820 | if (ret < 0) { |
821 | /* | |
f6b6aefe | 822 | * If we had some success, report the number of IRQs |
583871d4 HS |
823 | * we succeeded in setting up. |
824 | */ | |
d9d7070e | 825 | struct msi_desc *entry; |
583871d4 HS |
826 | int avail = 0; |
827 | ||
5004e98a | 828 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
829 | if (entry->irq != 0) |
830 | avail++; | |
831 | } | |
832 | if (avail != 0) | |
833 | ret = avail; | |
834 | } | |
835 | ||
2adc7907 | 836 | out_free: |
583871d4 HS |
837 | free_msi_irqs(dev); |
838 | ||
839 | return ret; | |
1da177e4 LT |
840 | } |
841 | ||
24334a12 | 842 | /** |
a06cd74c | 843 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 844 | * @dev: pointer to the pci_dev data structure of MSI device function |
f6b6aefe | 845 | * @nvec: how many MSIs have been requested? |
24334a12 | 846 | * |
f7625980 | 847 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 848 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 849 | * supported return 1, else return 0. |
24334a12 | 850 | **/ |
a06cd74c | 851 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
852 | { |
853 | struct pci_bus *bus; | |
854 | ||
0306ebfa | 855 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 856 | if (!pci_msi_enable) |
a06cd74c | 857 | return 0; |
27e20603 | 858 | |
901c4ddb | 859 | if (!dev || dev->no_msi) |
a06cd74c | 860 | return 0; |
24334a12 | 861 | |
314e77b3 ME |
862 | /* |
863 | * You can't ask to have 0 or less MSIs configured. | |
864 | * a) it's stupid .. | |
865 | * b) the list manipulation code assumes nvec >= 1. | |
866 | */ | |
867 | if (nvec < 1) | |
a06cd74c | 868 | return 0; |
314e77b3 | 869 | |
500559a9 HS |
870 | /* |
871 | * Any bridge which does NOT route MSI transactions from its | |
872 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa | 873 | * the secondary pci_bus. |
61af6929 MZ |
874 | * |
875 | * The NO_MSI flag can either be set directly by: | |
876 | * - arch-specific PCI host bus controller drivers (deprecated) | |
877 | * - quirks for specific PCI bridges | |
878 | * | |
879 | * or indirectly by platform-specific PCI host bridge drivers by | |
880 | * advertising the 'msi_domain' property, which results in | |
881 | * the NO_MSI flag when no MSI domain is found for this bridge | |
882 | * at probe time. | |
0306ebfa | 883 | */ |
24334a12 BG |
884 | for (bus = dev->bus; bus; bus = bus->parent) |
885 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 886 | return 0; |
24334a12 | 887 | |
a06cd74c | 888 | return 1; |
24334a12 BG |
889 | } |
890 | ||
d1ac1d26 AG |
891 | /** |
892 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
893 | * @dev: device to report about | |
894 | * | |
895 | * This function returns the number of MSI vectors a device requested via | |
896 | * Multiple Message Capable register. It returns a negative errno if the | |
897 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
898 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
899 | * MSI specification. | |
900 | **/ | |
901 | int pci_msi_vec_count(struct pci_dev *dev) | |
902 | { | |
903 | int ret; | |
904 | u16 msgctl; | |
905 | ||
906 | if (!dev->msi_cap) | |
907 | return -EINVAL; | |
908 | ||
909 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
910 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
911 | ||
912 | return ret; | |
913 | } | |
914 | EXPORT_SYMBOL(pci_msi_vec_count); | |
915 | ||
688769f6 | 916 | static void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 917 | { |
f2440d9a MW |
918 | struct msi_desc *desc; |
919 | u32 mask; | |
1da177e4 | 920 | |
128bc5fc | 921 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
922 | return; |
923 | ||
5004e98a | 924 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 925 | desc = first_pci_msi_entry(dev); |
110828c9 | 926 | |
61b64abd | 927 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 928 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 929 | dev->msi_enabled = 0; |
7bd007e4 | 930 | |
12abb8ba | 931 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 932 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 933 | /* Keep cached state to be restored */ |
23ed8d57 | 934 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee | 935 | |
f6b6aefe | 936 | /* Restore dev->irq to its default pin-assertion IRQ */ |
f2440d9a | 937 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 938 | pcibios_alloc_irq(dev); |
d52877c7 | 939 | } |
24d27553 | 940 | |
500559a9 | 941 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 942 | { |
d52877c7 YL |
943 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
944 | return; | |
945 | ||
946 | pci_msi_shutdown(dev); | |
f56e4481 | 947 | free_msi_irqs(dev); |
1da177e4 | 948 | } |
4cc086fa | 949 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 950 | |
a52e2e35 | 951 | /** |
ff1aa430 | 952 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 953 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
954 | * This function returns the number of device's MSI-X table entries and |
955 | * therefore the number of MSI-X vectors device is capable of sending. | |
956 | * It returns a negative errno if the device is not capable of sending MSI-X | |
957 | * interrupts. | |
958 | **/ | |
959 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 960 | { |
a52e2e35 RW |
961 | u16 control; |
962 | ||
520fe9dc | 963 | if (!dev->msix_cap) |
ff1aa430 | 964 | return -EINVAL; |
a52e2e35 | 965 | |
f84ecd28 | 966 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 967 | return msix_table_size(control); |
a52e2e35 | 968 | } |
ff1aa430 | 969 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 970 | |
e75eafb9 | 971 | static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, |
d7cc609f | 972 | int nvec, struct irq_affinity *affd, int flags) |
1da177e4 | 973 | { |
5ec09405 | 974 | int nr_entries; |
ded86d8d | 975 | int i, j; |
1da177e4 | 976 | |
901c4ddb | 977 | if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0) |
a06cd74c | 978 | return -EINVAL; |
c9953a73 | 979 | |
ff1aa430 AG |
980 | nr_entries = pci_msix_vec_count(dev); |
981 | if (nr_entries < 0) | |
982 | return nr_entries; | |
d7cc609f | 983 | if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL)) |
57fbf52c | 984 | return nr_entries; |
1da177e4 | 985 | |
3ac020e0 CH |
986 | if (entries) { |
987 | /* Check for any invalid entries */ | |
988 | for (i = 0; i < nvec; i++) { | |
989 | if (entries[i].entry >= nr_entries) | |
990 | return -EINVAL; /* invalid entry */ | |
991 | for (j = i + 1; j < nvec; j++) { | |
992 | if (entries[i].entry == entries[j].entry) | |
993 | return -EINVAL; /* duplicate entry */ | |
994 | } | |
1da177e4 LT |
995 | } |
996 | } | |
7bd007e4 | 997 | |
f6b6aefe | 998 | /* Check whether driver already requested for MSI IRQ */ |
500559a9 | 999 | if (dev->msi_enabled) { |
7506dc79 | 1000 | pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
1001 | return -EINVAL; |
1002 | } | |
61e1c590 | 1003 | return msix_capability_init(dev, entries, nvec, affd); |
e75eafb9 TG |
1004 | } |
1005 | ||
688769f6 | 1006 | static void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 1007 | { |
12abb8ba HS |
1008 | struct msi_desc *entry; |
1009 | ||
128bc5fc | 1010 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1011 | return; |
1012 | ||
0170591b KB |
1013 | if (pci_dev_is_disconnected(dev)) { |
1014 | dev->msix_enabled = 0; | |
1015 | return; | |
1016 | } | |
1017 | ||
12abb8ba | 1018 | /* Return the device with MSI-X masked as initial states */ |
5004e98a | 1019 | for_each_pci_msi_entry(entry, dev) { |
12abb8ba | 1020 | /* Keep cached states to be restored */ |
23ed8d57 | 1021 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
1022 | } |
1023 | ||
61b64abd | 1024 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 1025 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1026 | dev->msix_enabled = 0; |
5f226991 | 1027 | pcibios_alloc_irq(dev); |
d52877c7 | 1028 | } |
c901851f | 1029 | |
500559a9 | 1030 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1031 | { |
1032 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1033 | return; | |
1034 | ||
1035 | pci_msix_shutdown(dev); | |
f56e4481 | 1036 | free_msi_irqs(dev); |
1da177e4 | 1037 | } |
4cc086fa | 1038 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1039 | |
309e57df MW |
1040 | void pci_no_msi(void) |
1041 | { | |
1042 | pci_msi_enable = 0; | |
1043 | } | |
c9953a73 | 1044 | |
07ae95f9 AP |
1045 | /** |
1046 | * pci_msi_enabled - is MSI enabled? | |
1047 | * | |
1048 | * Returns true if MSI has not been disabled by the command-line option | |
1049 | * pci=nomsi. | |
1050 | **/ | |
1051 | int pci_msi_enabled(void) | |
d389fec6 | 1052 | { |
07ae95f9 | 1053 | return pci_msi_enable; |
d389fec6 | 1054 | } |
07ae95f9 | 1055 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1056 | |
4ef33685 | 1057 | static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, |
c66d4bd1 | 1058 | struct irq_affinity *affd) |
302a2523 | 1059 | { |
034cd97e | 1060 | int nvec; |
302a2523 AG |
1061 | int rc; |
1062 | ||
901c4ddb | 1063 | if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0) |
a06cd74c | 1064 | return -EINVAL; |
034cd97e | 1065 | |
f6b6aefe | 1066 | /* Check whether driver already requested MSI-X IRQs */ |
034cd97e | 1067 | if (dev->msix_enabled) { |
7506dc79 | 1068 | pci_info(dev, "can't enable MSI (MSI-X already enabled)\n"); |
034cd97e AG |
1069 | return -EINVAL; |
1070 | } | |
1071 | ||
302a2523 AG |
1072 | if (maxvec < minvec) |
1073 | return -ERANGE; | |
1074 | ||
4c1ef72e TZ |
1075 | if (WARN_ON_ONCE(dev->msi_enabled)) |
1076 | return -EINVAL; | |
1077 | ||
034cd97e AG |
1078 | nvec = pci_msi_vec_count(dev); |
1079 | if (nvec < 0) | |
1080 | return nvec; | |
4ef33685 | 1081 | if (nvec < minvec) |
948b7620 | 1082 | return -ENOSPC; |
4ef33685 CH |
1083 | |
1084 | if (nvec > maxvec) | |
034cd97e AG |
1085 | nvec = maxvec; |
1086 | ||
4ef33685 | 1087 | for (;;) { |
61e1c590 | 1088 | if (affd) { |
6f9a22bc | 1089 | nvec = irq_calc_affinity_vectors(minvec, nvec, affd); |
4ef33685 CH |
1090 | if (nvec < minvec) |
1091 | return -ENOSPC; | |
1092 | } | |
1093 | ||
61e1c590 | 1094 | rc = msi_capability_init(dev, nvec, affd); |
4ef33685 CH |
1095 | if (rc == 0) |
1096 | return nvec; | |
1097 | ||
4ef33685 | 1098 | if (rc < 0) |
302a2523 | 1099 | return rc; |
4ef33685 CH |
1100 | if (rc < minvec) |
1101 | return -ENOSPC; | |
1102 | ||
1103 | nvec = rc; | |
1104 | } | |
1105 | } | |
1106 | ||
4fe03955 CH |
1107 | /* deprecated, don't use */ |
1108 | int pci_enable_msi(struct pci_dev *dev) | |
4ef33685 | 1109 | { |
4fe03955 CH |
1110 | int rc = __pci_enable_msi_range(dev, 1, 1, NULL); |
1111 | if (rc < 0) | |
1112 | return rc; | |
1113 | return 0; | |
4ef33685 | 1114 | } |
4fe03955 | 1115 | EXPORT_SYMBOL(pci_enable_msi); |
4ef33685 CH |
1116 | |
1117 | static int __pci_enable_msix_range(struct pci_dev *dev, | |
61e1c590 | 1118 | struct msix_entry *entries, int minvec, |
d7cc609f LG |
1119 | int maxvec, struct irq_affinity *affd, |
1120 | int flags) | |
4ef33685 | 1121 | { |
e75eafb9 | 1122 | int rc, nvec = maxvec; |
4ef33685 CH |
1123 | |
1124 | if (maxvec < minvec) | |
1125 | return -ERANGE; | |
1126 | ||
4c1ef72e TZ |
1127 | if (WARN_ON_ONCE(dev->msix_enabled)) |
1128 | return -EINVAL; | |
1129 | ||
4ef33685 | 1130 | for (;;) { |
61e1c590 | 1131 | if (affd) { |
6f9a22bc | 1132 | nvec = irq_calc_affinity_vectors(minvec, nvec, affd); |
4ef33685 | 1133 | if (nvec < minvec) |
302a2523 | 1134 | return -ENOSPC; |
302a2523 | 1135 | } |
302a2523 | 1136 | |
d7cc609f | 1137 | rc = __pci_enable_msix(dev, entries, nvec, affd, flags); |
4ef33685 CH |
1138 | if (rc == 0) |
1139 | return nvec; | |
1140 | ||
4ef33685 CH |
1141 | if (rc < 0) |
1142 | return rc; | |
1143 | if (rc < minvec) | |
1144 | return -ENOSPC; | |
1145 | ||
1146 | nvec = rc; | |
1147 | } | |
302a2523 | 1148 | } |
302a2523 AG |
1149 | |
1150 | /** | |
1151 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1152 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1153 | * @entries: pointer to an array of MSI-X entries | |
f6b6aefe BH |
1154 | * @minvec: minimum number of MSI-X IRQs requested |
1155 | * @maxvec: maximum number of MSI-X IRQs requested | |
302a2523 AG |
1156 | * |
1157 | * Setup the MSI-X capability structure of device function with a maximum | |
1158 | * possible number of interrupts in the range between @minvec and @maxvec | |
1159 | * upon its software driver call to request for MSI-X mode enabled on its | |
1160 | * hardware device function. It returns a negative errno if an error occurs. | |
1161 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1162 | * indicates the successful configuration of MSI-X capability structure | |
1163 | * with new allocated MSI-X interrupts. | |
1164 | **/ | |
1165 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
4ef33685 | 1166 | int minvec, int maxvec) |
302a2523 | 1167 | { |
d7cc609f | 1168 | return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0); |
302a2523 AG |
1169 | } |
1170 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1171 | |
aff17164 | 1172 | /** |
402723ad | 1173 | * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device |
aff17164 CH |
1174 | * @dev: PCI device to operate on |
1175 | * @min_vecs: minimum number of vectors required (must be >= 1) | |
1176 | * @max_vecs: maximum (desired) number of vectors | |
1177 | * @flags: flags or quirks for the allocation | |
402723ad | 1178 | * @affd: optional description of the affinity requirements |
aff17164 CH |
1179 | * |
1180 | * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI | |
1181 | * vectors if available, and fall back to a single legacy vector | |
1182 | * if neither is available. Return the number of vectors allocated, | |
1183 | * (which might be smaller than @max_vecs) if successful, or a negative | |
1184 | * error code on error. If less than @min_vecs interrupt vectors are | |
1185 | * available for @dev the function will fail with -ENOSPC. | |
1186 | * | |
1187 | * To get the Linux IRQ number used for a vector that can be passed to | |
1188 | * request_irq() use the pci_irq_vector() helper. | |
1189 | */ | |
402723ad CH |
1190 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1191 | unsigned int max_vecs, unsigned int flags, | |
c66d4bd1 | 1192 | struct irq_affinity *affd) |
aff17164 | 1193 | { |
c66d4bd1 | 1194 | struct irq_affinity msi_default_affd = {0}; |
30ff3e8c | 1195 | int nvecs = -ENOSPC; |
aff17164 | 1196 | |
402723ad CH |
1197 | if (flags & PCI_IRQ_AFFINITY) { |
1198 | if (!affd) | |
1199 | affd = &msi_default_affd; | |
1200 | } else { | |
1201 | if (WARN_ON(affd)) | |
1202 | affd = NULL; | |
1203 | } | |
61e1c590 | 1204 | |
4fe0d154 | 1205 | if (flags & PCI_IRQ_MSIX) { |
30ff3e8c PS |
1206 | nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, |
1207 | affd, flags); | |
1208 | if (nvecs > 0) | |
1209 | return nvecs; | |
aff17164 CH |
1210 | } |
1211 | ||
4fe0d154 | 1212 | if (flags & PCI_IRQ_MSI) { |
30ff3e8c PS |
1213 | nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd); |
1214 | if (nvecs > 0) | |
1215 | return nvecs; | |
aff17164 CH |
1216 | } |
1217 | ||
f6b6aefe | 1218 | /* use legacy IRQ if allowed */ |
862290f9 CH |
1219 | if (flags & PCI_IRQ_LEGACY) { |
1220 | if (min_vecs == 1 && dev->irq) { | |
c66d4bd1 ML |
1221 | /* |
1222 | * Invoke the affinity spreading logic to ensure that | |
1223 | * the device driver can adjust queue configuration | |
1224 | * for the single interrupt case. | |
1225 | */ | |
1226 | if (affd) | |
1227 | irq_create_affinity_masks(1, affd); | |
862290f9 CH |
1228 | pci_intx(dev, 1); |
1229 | return 1; | |
1230 | } | |
5d0bdf28 CH |
1231 | } |
1232 | ||
30ff3e8c | 1233 | return nvecs; |
aff17164 | 1234 | } |
402723ad | 1235 | EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); |
aff17164 CH |
1236 | |
1237 | /** | |
1238 | * pci_free_irq_vectors - free previously allocated IRQs for a device | |
1239 | * @dev: PCI device to operate on | |
1240 | * | |
1241 | * Undoes the allocations and enabling in pci_alloc_irq_vectors(). | |
1242 | */ | |
1243 | void pci_free_irq_vectors(struct pci_dev *dev) | |
1244 | { | |
1245 | pci_disable_msix(dev); | |
1246 | pci_disable_msi(dev); | |
1247 | } | |
1248 | EXPORT_SYMBOL(pci_free_irq_vectors); | |
1249 | ||
1250 | /** | |
1251 | * pci_irq_vector - return Linux IRQ number of a device vector | |
1252 | * @dev: PCI device to operate on | |
1253 | * @nr: device-relative interrupt vector index (0-based). | |
1254 | */ | |
1255 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1256 | { | |
1257 | if (dev->msix_enabled) { | |
1258 | struct msi_desc *entry; | |
1259 | int i = 0; | |
1260 | ||
1261 | for_each_pci_msi_entry(entry, dev) { | |
1262 | if (i == nr) | |
1263 | return entry->irq; | |
1264 | i++; | |
1265 | } | |
1266 | WARN_ON_ONCE(1); | |
1267 | return -EINVAL; | |
1268 | } | |
1269 | ||
1270 | if (dev->msi_enabled) { | |
1271 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1272 | ||
1273 | if (WARN_ON_ONCE(nr >= entry->nvec_used)) | |
1274 | return -EINVAL; | |
1275 | } else { | |
1276 | if (WARN_ON_ONCE(nr > 0)) | |
1277 | return -EINVAL; | |
1278 | } | |
1279 | ||
1280 | return dev->irq + nr; | |
1281 | } | |
1282 | EXPORT_SYMBOL(pci_irq_vector); | |
1283 | ||
ee8d41e5 | 1284 | /** |
f6b6aefe | 1285 | * pci_irq_get_affinity - return the affinity of a particular MSI vector |
ee8d41e5 TG |
1286 | * @dev: PCI device to operate on |
1287 | * @nr: device-relative interrupt vector index (0-based). | |
1288 | */ | |
1289 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr) | |
1290 | { | |
1291 | if (dev->msix_enabled) { | |
1292 | struct msi_desc *entry; | |
1293 | int i = 0; | |
1294 | ||
1295 | for_each_pci_msi_entry(entry, dev) { | |
1296 | if (i == nr) | |
bec04037 | 1297 | return &entry->affinity->mask; |
ee8d41e5 TG |
1298 | i++; |
1299 | } | |
1300 | WARN_ON_ONCE(1); | |
1301 | return NULL; | |
1302 | } else if (dev->msi_enabled) { | |
1303 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1304 | ||
d1d111e0 JB |
1305 | if (WARN_ON_ONCE(!entry || !entry->affinity || |
1306 | nr >= entry->nvec_used)) | |
ee8d41e5 TG |
1307 | return NULL; |
1308 | ||
bec04037 | 1309 | return &entry->affinity[nr].mask; |
ee8d41e5 TG |
1310 | } else { |
1311 | return cpu_possible_mask; | |
1312 | } | |
1313 | } | |
1314 | EXPORT_SYMBOL(pci_irq_get_affinity); | |
1315 | ||
25a98bd4 JL |
1316 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1317 | { | |
1318 | return to_pci_dev(desc->dev); | |
1319 | } | |
a4289dc2 | 1320 | EXPORT_SYMBOL(msi_desc_to_pci_dev); |
25a98bd4 | 1321 | |
c179c9b9 JL |
1322 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1323 | { | |
1324 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1325 | ||
1326 | return dev->bus->sysdata; | |
1327 | } | |
1328 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1329 | ||
3878eaef JL |
1330 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1331 | /** | |
1332 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1333 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1334 | * @msg: Pointer to the message | |
1335 | */ | |
1336 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1337 | { | |
507a883e | 1338 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1339 | |
1340 | /* | |
1341 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1342 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1343 | */ | |
1344 | if (desc->irq == irq_data->irq) | |
1345 | __pci_write_msi_msg(desc, msg); | |
1346 | } | |
1347 | ||
1348 | /** | |
1349 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
f6b6aefe | 1350 | * @desc: Pointer to the MSI descriptor |
3878eaef JL |
1351 | * |
1352 | * The ID number is only used within the irqdomain. | |
1353 | */ | |
9006c133 | 1354 | static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc) |
3878eaef | 1355 | { |
dfb9eb7c TG |
1356 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); |
1357 | ||
3878eaef | 1358 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | |
4e544bac | 1359 | pci_dev_id(dev) << 11 | |
3878eaef JL |
1360 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; |
1361 | } | |
1362 | ||
1363 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1364 | { | |
1365 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1366 | } | |
1367 | ||
1368 | /** | |
f6b6aefe BH |
1369 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities |
1370 | * for @dev | |
3878eaef JL |
1371 | * @domain: The interrupt domain to check |
1372 | * @info: The domain info for verification | |
1373 | * @dev: The device to check | |
1374 | * | |
1375 | * Returns: | |
1376 | * 0 if the functionality is supported | |
1377 | * 1 if Multi MSI is requested, but the domain does not support it | |
1378 | * -ENOTSUPP otherwise | |
1379 | */ | |
1380 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1381 | struct msi_domain_info *info, struct device *dev) | |
1382 | { | |
1383 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1384 | ||
4fe03955 | 1385 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1386 | if (pci_msi_desc_is_multi_msi(desc) && |
1387 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1388 | return 1; | |
1389 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1390 | return -ENOTSUPP; | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1396 | struct msi_desc *desc, int error) | |
1397 | { | |
4fe03955 | 1398 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1399 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) |
1400 | return 1; | |
1401 | ||
1402 | return error; | |
1403 | } | |
1404 | ||
3878eaef JL |
1405 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, |
1406 | struct msi_desc *desc) | |
1407 | { | |
1408 | arg->desc = desc; | |
dfb9eb7c | 1409 | arg->hwirq = pci_msi_domain_calc_hwirq(desc); |
3878eaef | 1410 | } |
3878eaef JL |
1411 | |
1412 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1413 | .set_desc = pci_msi_domain_set_desc, | |
1414 | .msi_check = pci_msi_domain_check_cap, | |
1415 | .handle_error = pci_msi_domain_handle_error, | |
1416 | }; | |
1417 | ||
1418 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1419 | { | |
1420 | struct msi_domain_ops *ops = info->ops; | |
1421 | ||
1422 | if (ops == NULL) { | |
1423 | info->ops = &pci_msi_domain_ops_default; | |
1424 | } else { | |
1425 | if (ops->set_desc == NULL) | |
1426 | ops->set_desc = pci_msi_domain_set_desc; | |
1427 | if (ops->msi_check == NULL) | |
1428 | ops->msi_check = pci_msi_domain_check_cap; | |
1429 | if (ops->handle_error == NULL) | |
1430 | ops->handle_error = pci_msi_domain_handle_error; | |
1431 | } | |
1432 | } | |
1433 | ||
1434 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1435 | { | |
1436 | struct irq_chip *chip = info->chip; | |
1437 | ||
1438 | BUG_ON(!chip); | |
1439 | if (!chip->irq_write_msi_msg) | |
1440 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1441 | if (!chip->irq_mask) |
1442 | chip->irq_mask = pci_msi_mask_irq; | |
1443 | if (!chip->irq_unmask) | |
1444 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1445 | } |
1446 | ||
1447 | /** | |
be5436c8 MZ |
1448 | * pci_msi_create_irq_domain - Create a MSI interrupt domain |
1449 | * @fwnode: Optional fwnode of the interrupt controller | |
3878eaef JL |
1450 | * @info: MSI domain info |
1451 | * @parent: Parent irq domain | |
1452 | * | |
1453 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1454 | * | |
1455 | * Returns: | |
1456 | * A domain pointer or NULL in case of failure. | |
1457 | */ | |
be5436c8 | 1458 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
1459 | struct msi_domain_info *info, |
1460 | struct irq_domain *parent) | |
1461 | { | |
0380839d MZ |
1462 | struct irq_domain *domain; |
1463 | ||
6988e0e0 MZ |
1464 | if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE)) |
1465 | info->flags &= ~MSI_FLAG_LEVEL_CAPABLE; | |
1466 | ||
3878eaef JL |
1467 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1468 | pci_msi_domain_update_dom_ops(info); | |
1469 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1470 | pci_msi_domain_update_chip_ops(info); | |
1471 | ||
f3b0946d | 1472 | info->flags |= MSI_FLAG_ACTIVATE_EARLY; |
25e960ef TG |
1473 | if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE)) |
1474 | info->flags |= MSI_FLAG_MUST_REACTIVATE; | |
f3b0946d | 1475 | |
923aa4c3 HK |
1476 | /* PCI-MSI is oneshot-safe */ |
1477 | info->chip->flags |= IRQCHIP_ONESHOT_SAFE; | |
1478 | ||
be5436c8 | 1479 | domain = msi_create_irq_domain(fwnode, info, parent); |
0380839d MZ |
1480 | if (!domain) |
1481 | return NULL; | |
1482 | ||
96f0d93a | 1483 | irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI); |
0380839d | 1484 | return domain; |
3878eaef | 1485 | } |
a4289dc2 | 1486 | EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); |
3878eaef | 1487 | |
235b2c77 RM |
1488 | /* |
1489 | * Users of the generic MSI infrastructure expect a device to have a single ID, | |
1490 | * so with DMA aliases we have to pick the least-worst compromise. Devices with | |
1491 | * DMA phantom functions tend to still emit MSIs from the real function number, | |
1492 | * so we ignore those and only consider topological aliases where either the | |
1493 | * alias device or RID appears on a different bus number. We also make the | |
1494 | * reasonable assumption that bridges are walked in an upstream direction (so | |
1495 | * the last one seen wins), and the much braver assumption that the most likely | |
1496 | * case is that of PCI->PCIe so we should always use the alias RID. This echoes | |
1497 | * the logic from intel_irq_remapping's set_msi_sid(), which presumably works | |
1498 | * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions | |
1499 | * for taking ownership all we can really do is close our eyes and hope... | |
1500 | */ | |
b6eec9b7 DD |
1501 | static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data) |
1502 | { | |
1503 | u32 *pa = data; | |
235b2c77 RM |
1504 | u8 bus = PCI_BUS_NUM(*pa); |
1505 | ||
1506 | if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus) | |
1507 | *pa = alias; | |
b6eec9b7 | 1508 | |
b6eec9b7 DD |
1509 | return 0; |
1510 | } | |
235b2c77 | 1511 | |
b6eec9b7 DD |
1512 | /** |
1513 | * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID) | |
1514 | * @domain: The interrupt domain | |
1515 | * @pdev: The PCI device. | |
1516 | * | |
1517 | * The RID for a device is formed from the alias, with a firmware | |
1518 | * supplied mapping applied | |
1519 | * | |
1520 | * Returns: The RID. | |
1521 | */ | |
1522 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev) | |
1523 | { | |
1524 | struct device_node *of_node; | |
4e544bac | 1525 | u32 rid = pci_dev_id(pdev); |
b6eec9b7 DD |
1526 | |
1527 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1528 | ||
1529 | of_node = irq_domain_get_of_node(domain); | |
2bcdd8f2 | 1530 | rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) : |
39c3cf56 | 1531 | iort_msi_map_id(&pdev->dev, rid); |
b6eec9b7 DD |
1532 | |
1533 | return rid; | |
1534 | } | |
54fa97ee MZ |
1535 | |
1536 | /** | |
1537 | * pci_msi_get_device_domain - Get the MSI domain for a given PCI device | |
1538 | * @pdev: The PCI device | |
1539 | * | |
1540 | * Use the firmware data to find a device-specific MSI domain | |
235b2c77 | 1541 | * (i.e. not one that is set as a default). |
54fa97ee | 1542 | * |
235b2c77 | 1543 | * Returns: The corresponding MSI domain or NULL if none has been found. |
54fa97ee MZ |
1544 | */ |
1545 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
1546 | { | |
be2021ba | 1547 | struct irq_domain *dom; |
4e544bac | 1548 | u32 rid = pci_dev_id(pdev); |
54fa97ee MZ |
1549 | |
1550 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
6f881aba | 1551 | dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI); |
be2021ba | 1552 | if (!dom) |
d1718a1b LP |
1553 | dom = iort_get_device_domain(&pdev->dev, rid, |
1554 | DOMAIN_BUS_PCI_MSI); | |
be2021ba | 1555 | return dom; |
54fa97ee | 1556 | } |
2fd60266 TG |
1557 | |
1558 | /** | |
1559 | * pci_dev_has_special_msi_domain - Check whether the device is handled by | |
1560 | * a non-standard PCI-MSI domain | |
1561 | * @pdev: The PCI device to check. | |
1562 | * | |
1563 | * Returns: True if the device irqdomain or the bus irqdomain is | |
1564 | * non-standard PCI/MSI. | |
1565 | */ | |
1566 | bool pci_dev_has_special_msi_domain(struct pci_dev *pdev) | |
1567 | { | |
1568 | struct irq_domain *dom = dev_get_msi_domain(&pdev->dev); | |
1569 | ||
1570 | if (!dom) | |
1571 | dom = dev_get_msi_domain(&pdev->bus->dev); | |
1572 | ||
1573 | if (!dom) | |
1574 | return true; | |
1575 | ||
1576 | return dom->bus_token != DOMAIN_BUS_PCI_MSI; | |
1577 | } | |
1578 | ||
3878eaef | 1579 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |
cbc40d5c BH |
1580 | #endif /* CONFIG_PCI_MSI */ |
1581 | ||
1582 | void pci_msi_init(struct pci_dev *dev) | |
1583 | { | |
1584 | u16 ctrl; | |
1585 | ||
1586 | /* | |
1587 | * Disable the MSI hardware to avoid screaming interrupts | |
1588 | * during boot. This is the power on reset default so | |
1589 | * usually this should be a noop. | |
1590 | */ | |
1591 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1592 | if (!dev->msi_cap) | |
1593 | return; | |
1594 | ||
1595 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); | |
1596 | if (ctrl & PCI_MSI_FLAGS_ENABLE) | |
1597 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, | |
1598 | ctrl & ~PCI_MSI_FLAGS_ENABLE); | |
2053230a VS |
1599 | |
1600 | if (!(ctrl & PCI_MSI_FLAGS_64BIT)) | |
1601 | dev->no_64bit_msi = 1; | |
cbc40d5c BH |
1602 | } |
1603 | ||
1604 | void pci_msix_init(struct pci_dev *dev) | |
1605 | { | |
1606 | u16 ctrl; | |
1607 | ||
1608 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1609 | if (!dev->msix_cap) | |
1610 | return; | |
1611 | ||
1612 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
1613 | if (ctrl & PCI_MSIX_FLAGS_ENABLE) | |
1614 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, | |
1615 | ctrl & ~PCI_MSIX_FLAGS_ENABLE); | |
1616 | } |