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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
527eee29 BH |
28 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
29 | ||
30 | ||
6a9e7f20 AB |
31 | /* Arch hooks */ |
32 | ||
11df1f05 ME |
33 | #ifndef arch_msi_check_device |
34 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
35 | { |
36 | return 0; | |
37 | } | |
11df1f05 | 38 | #endif |
6a9e7f20 | 39 | |
11df1f05 | 40 | #ifndef arch_setup_msi_irqs |
1525bf0d TG |
41 | # define arch_setup_msi_irqs default_setup_msi_irqs |
42 | # define HAVE_DEFAULT_MSI_SETUP_IRQS | |
43 | #endif | |
44 | ||
45 | #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS | |
46 | int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
47 | { |
48 | struct msi_desc *entry; | |
49 | int ret; | |
50 | ||
1c8d7b0a MW |
51 | /* |
52 | * If an architecture wants to support multiple MSI, it needs to | |
53 | * override arch_setup_msi_irqs() | |
54 | */ | |
55 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
56 | return 1; | |
57 | ||
6a9e7f20 AB |
58 | list_for_each_entry(entry, &dev->msi_list, list) { |
59 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 60 | if (ret < 0) |
6a9e7f20 | 61 | return ret; |
b5fbf533 ME |
62 | if (ret > 0) |
63 | return -ENOSPC; | |
6a9e7f20 AB |
64 | } |
65 | ||
66 | return 0; | |
67 | } | |
11df1f05 | 68 | #endif |
6a9e7f20 | 69 | |
11df1f05 | 70 | #ifndef arch_teardown_msi_irqs |
1525bf0d TG |
71 | # define arch_teardown_msi_irqs default_teardown_msi_irqs |
72 | # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
73 | #endif | |
74 | ||
75 | #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
76 | void default_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
77 | { |
78 | struct msi_desc *entry; | |
79 | ||
80 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
81 | int i, nvec; |
82 | if (entry->irq == 0) | |
83 | continue; | |
84 | nvec = 1 << entry->msi_attrib.multiple; | |
85 | for (i = 0; i < nvec; i++) | |
86 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
87 | } |
88 | } | |
11df1f05 | 89 | #endif |
6a9e7f20 | 90 | |
76ccc297 KRW |
91 | #ifndef arch_restore_msi_irqs |
92 | # define arch_restore_msi_irqs default_restore_msi_irqs | |
93 | # define HAVE_DEFAULT_MSI_RESTORE_IRQS | |
94 | #endif | |
95 | ||
96 | #ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS | |
97 | void default_restore_msi_irqs(struct pci_dev *dev, int irq) | |
98 | { | |
99 | struct msi_desc *entry; | |
100 | ||
101 | entry = NULL; | |
102 | if (dev->msix_enabled) { | |
103 | list_for_each_entry(entry, &dev->msi_list, list) { | |
104 | if (irq == entry->irq) | |
105 | break; | |
106 | } | |
107 | } else if (dev->msi_enabled) { | |
108 | entry = irq_get_msi_desc(irq); | |
109 | } | |
110 | ||
111 | if (entry) | |
112 | write_msi_msg(irq, &entry->msg); | |
113 | } | |
114 | #endif | |
115 | ||
e375b561 | 116 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 117 | { |
b1cbf4e4 EB |
118 | u16 control; |
119 | ||
e375b561 | 120 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
121 | control &= ~PCI_MSI_FLAGS_ENABLE; |
122 | if (enable) | |
123 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 124 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
125 | } |
126 | ||
b1cbf4e4 EB |
127 | static void msix_set_enable(struct pci_dev *dev, int enable) |
128 | { | |
b1cbf4e4 EB |
129 | u16 control; |
130 | ||
e375b561 GS |
131 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
132 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
133 | if (enable) | |
134 | control |= PCI_MSIX_FLAGS_ENABLE; | |
135 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
136 | } |
137 | ||
bffac3c5 MW |
138 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
139 | { | |
0b49ec37 MW |
140 | /* Don't shift by >= width of type */ |
141 | if (x >= 5) | |
142 | return 0xffffffff; | |
143 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
144 | } |
145 | ||
f2440d9a | 146 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 147 | { |
f2440d9a MW |
148 | return msi_mask((control >> 1) & 7); |
149 | } | |
988cbb15 | 150 | |
f2440d9a MW |
151 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
152 | { | |
153 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
154 | } |
155 | ||
ce6fce42 MW |
156 | /* |
157 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
158 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
159 | * reliably as devices without an INTx disable bit will then generate a | |
160 | * level IRQ which will never be cleared. | |
ce6fce42 | 161 | */ |
12abb8ba | 162 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 163 | { |
f2440d9a | 164 | u32 mask_bits = desc->masked; |
1da177e4 | 165 | |
f2440d9a | 166 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 167 | return 0; |
f2440d9a MW |
168 | |
169 | mask_bits &= ~mask; | |
170 | mask_bits |= flag; | |
171 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
172 | |
173 | return mask_bits; | |
174 | } | |
175 | ||
176 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
177 | { | |
178 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
179 | } |
180 | ||
181 | /* | |
182 | * This internal function does not flush PCI writes to the device. | |
183 | * All users must ensure that they read from the device before either | |
184 | * assuming that the device state is up to date, or returning out of this | |
185 | * file. This saves a few milliseconds when initialising devices with lots | |
186 | * of MSI-X interrupts. | |
187 | */ | |
12abb8ba | 188 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
189 | { |
190 | u32 mask_bits = desc->masked; | |
191 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 192 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
193 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
194 | if (flag) | |
195 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 196 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
197 | |
198 | return mask_bits; | |
199 | } | |
200 | ||
201 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
202 | { | |
203 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 204 | } |
24d27553 | 205 | |
9a4da8a5 JG |
206 | #ifdef CONFIG_GENERIC_HARDIRQS |
207 | ||
1c9db525 | 208 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 209 | { |
1c9db525 | 210 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 211 | |
f2440d9a MW |
212 | if (desc->msi_attrib.is_msix) { |
213 | msix_mask_irq(desc, flag); | |
214 | readl(desc->mask_base); /* Flush write to device */ | |
215 | } else { | |
1c9db525 | 216 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 217 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 218 | } |
f2440d9a MW |
219 | } |
220 | ||
1c9db525 | 221 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 222 | { |
1c9db525 | 223 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
224 | } |
225 | ||
1c9db525 | 226 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 227 | { |
1c9db525 | 228 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
229 | } |
230 | ||
9a4da8a5 JG |
231 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
232 | ||
39431acb | 233 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 234 | { |
30da5524 BH |
235 | BUG_ON(entry->dev->current_state != PCI_D0); |
236 | ||
237 | if (entry->msi_attrib.is_msix) { | |
238 | void __iomem *base = entry->mask_base + | |
239 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
240 | ||
241 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
242 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
243 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
244 | } else { | |
245 | struct pci_dev *dev = entry->dev; | |
f5322169 | 246 | int pos = dev->msi_cap; |
30da5524 BH |
247 | u16 data; |
248 | ||
9925ad0c BH |
249 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
250 | &msg->address_lo); | |
30da5524 | 251 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
252 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
253 | &msg->address_hi); | |
2f221349 | 254 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
255 | } else { |
256 | msg->address_hi = 0; | |
2f221349 | 257 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
258 | } |
259 | msg->data = data; | |
260 | } | |
261 | } | |
262 | ||
263 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
264 | { | |
dced35ae | 265 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 266 | |
39431acb | 267 | __read_msi_msg(entry, msg); |
30da5524 BH |
268 | } |
269 | ||
39431acb | 270 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 271 | { |
30da5524 | 272 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
273 | * valid messages are not all-zeroes. */ |
274 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
275 | entry->msg.data)); | |
0366f8f7 | 276 | |
fcd097f3 | 277 | *msg = entry->msg; |
0366f8f7 | 278 | } |
1da177e4 | 279 | |
30da5524 | 280 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 281 | { |
dced35ae | 282 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 283 | |
39431acb | 284 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
285 | } |
286 | ||
39431acb | 287 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 288 | { |
fcd097f3 BH |
289 | if (entry->dev->current_state != PCI_D0) { |
290 | /* Don't touch the hardware now */ | |
291 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
292 | void __iomem *base; |
293 | base = entry->mask_base + | |
294 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
295 | ||
2c21fd4b HS |
296 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
297 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
298 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 299 | } else { |
0366f8f7 | 300 | struct pci_dev *dev = entry->dev; |
f5322169 | 301 | int pos = dev->msi_cap; |
1c8d7b0a MW |
302 | u16 msgctl; |
303 | ||
f84ecd28 | 304 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
305 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
306 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 307 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 308 | |
9925ad0c BH |
309 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
310 | msg->address_lo); | |
0366f8f7 | 311 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
312 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
313 | msg->address_hi); | |
2f221349 BH |
314 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
315 | msg->data); | |
0366f8f7 | 316 | } else { |
2f221349 BH |
317 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
318 | msg->data); | |
0366f8f7 | 319 | } |
1da177e4 | 320 | } |
392ee1e6 | 321 | entry->msg = *msg; |
1da177e4 | 322 | } |
0366f8f7 | 323 | |
3145e941 YL |
324 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
325 | { | |
dced35ae | 326 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 327 | |
39431acb | 328 | __write_msi_msg(entry, msg); |
3145e941 YL |
329 | } |
330 | ||
f56e4481 HS |
331 | static void free_msi_irqs(struct pci_dev *dev) |
332 | { | |
333 | struct msi_desc *entry, *tmp; | |
334 | ||
335 | list_for_each_entry(entry, &dev->msi_list, list) { | |
336 | int i, nvec; | |
337 | if (!entry->irq) | |
338 | continue; | |
339 | nvec = 1 << entry->msi_attrib.multiple; | |
9a4da8a5 | 340 | #ifdef CONFIG_GENERIC_HARDIRQS |
f56e4481 HS |
341 | for (i = 0; i < nvec; i++) |
342 | BUG_ON(irq_has_action(entry->irq + i)); | |
9a4da8a5 | 343 | #endif |
f56e4481 HS |
344 | } |
345 | ||
346 | arch_teardown_msi_irqs(dev); | |
347 | ||
348 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
349 | if (entry->msi_attrib.is_msix) { | |
350 | if (list_is_last(&entry->list, &dev->msi_list)) | |
351 | iounmap(entry->mask_base); | |
352 | } | |
424eb391 NH |
353 | |
354 | /* | |
355 | * Its possible that we get into this path | |
356 | * When populate_msi_sysfs fails, which means the entries | |
357 | * were not registered with sysfs. In that case don't | |
358 | * unregister them. | |
359 | */ | |
360 | if (entry->kobj.parent) { | |
361 | kobject_del(&entry->kobj); | |
362 | kobject_put(&entry->kobj); | |
363 | } | |
364 | ||
f56e4481 HS |
365 | list_del(&entry->list); |
366 | kfree(entry); | |
367 | } | |
368 | } | |
c54c1879 | 369 | |
379f5327 | 370 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 371 | { |
379f5327 MW |
372 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
373 | if (!desc) | |
1da177e4 LT |
374 | return NULL; |
375 | ||
379f5327 MW |
376 | INIT_LIST_HEAD(&desc->list); |
377 | desc->dev = dev; | |
1da177e4 | 378 | |
379f5327 | 379 | return desc; |
1da177e4 LT |
380 | } |
381 | ||
ba698ad4 DM |
382 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
383 | { | |
384 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
385 | pci_intx(dev, enable); | |
386 | } | |
387 | ||
8fed4b65 | 388 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 389 | { |
41017f0c | 390 | u16 control; |
392ee1e6 | 391 | struct msi_desc *entry; |
41017f0c | 392 | |
b1cbf4e4 EB |
393 | if (!dev->msi_enabled) |
394 | return; | |
395 | ||
dced35ae | 396 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 397 | |
ba698ad4 | 398 | pci_intx_for_msi(dev, 0); |
e375b561 | 399 | msi_set_enable(dev, 0); |
76ccc297 | 400 | arch_restore_msi_irqs(dev, dev->irq); |
392ee1e6 | 401 | |
f5322169 | 402 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
f2440d9a | 403 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 404 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 405 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 406 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
407 | } |
408 | ||
409 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 410 | { |
41017f0c | 411 | struct msi_desc *entry; |
392ee1e6 | 412 | u16 control; |
41017f0c | 413 | |
ded86d8d EB |
414 | if (!dev->msix_enabled) |
415 | return; | |
f598282f | 416 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 417 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f5322169 | 418 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
ded86d8d | 419 | |
41017f0c | 420 | /* route the table */ |
ba698ad4 | 421 | pci_intx_for_msi(dev, 0); |
f598282f | 422 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 423 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 424 | |
4aa9bc95 | 425 | list_for_each_entry(entry, &dev->msi_list, list) { |
76ccc297 | 426 | arch_restore_msi_irqs(dev, entry->irq); |
f2440d9a | 427 | msix_mask_irq(entry, entry->masked); |
41017f0c | 428 | } |
41017f0c | 429 | |
392ee1e6 | 430 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 431 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 432 | } |
8fed4b65 ME |
433 | |
434 | void pci_restore_msi_state(struct pci_dev *dev) | |
435 | { | |
436 | __pci_restore_msi_state(dev); | |
437 | __pci_restore_msix_state(dev); | |
438 | } | |
94688cf2 | 439 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 440 | |
da8d1c8b NH |
441 | |
442 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
443 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
444 | ||
445 | struct msi_attribute { | |
446 | struct attribute attr; | |
447 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
448 | char *buf); | |
449 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
450 | const char *buf, size_t count); | |
451 | }; | |
452 | ||
453 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
454 | char *buf) | |
455 | { | |
456 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
457 | } | |
458 | ||
459 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
460 | struct attribute *attr, char *buf) | |
461 | { | |
462 | struct msi_attribute *attribute = to_msi_attr(attr); | |
463 | struct msi_desc *entry = to_msi_desc(kobj); | |
464 | ||
465 | if (!attribute->show) | |
466 | return -EIO; | |
467 | ||
468 | return attribute->show(entry, attribute, buf); | |
469 | } | |
470 | ||
471 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
472 | .show = msi_irq_attr_show, | |
473 | }; | |
474 | ||
475 | static struct msi_attribute mode_attribute = | |
476 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
477 | ||
478 | ||
9738abed | 479 | static struct attribute *msi_irq_default_attrs[] = { |
da8d1c8b NH |
480 | &mode_attribute.attr, |
481 | NULL | |
482 | }; | |
483 | ||
9738abed | 484 | static void msi_kobj_release(struct kobject *kobj) |
da8d1c8b NH |
485 | { |
486 | struct msi_desc *entry = to_msi_desc(kobj); | |
487 | ||
488 | pci_dev_put(entry->dev); | |
489 | } | |
490 | ||
491 | static struct kobj_type msi_irq_ktype = { | |
492 | .release = msi_kobj_release, | |
493 | .sysfs_ops = &msi_irq_sysfs_ops, | |
494 | .default_attrs = msi_irq_default_attrs, | |
495 | }; | |
496 | ||
497 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
498 | { | |
499 | struct msi_desc *entry; | |
500 | struct kobject *kobj; | |
501 | int ret; | |
502 | int count = 0; | |
503 | ||
504 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
505 | if (!pdev->msi_kset) | |
506 | return -ENOMEM; | |
507 | ||
508 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
509 | kobj = &entry->kobj; | |
510 | kobj->kset = pdev->msi_kset; | |
511 | pci_dev_get(pdev); | |
512 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
513 | "%u", entry->irq); | |
514 | if (ret) | |
515 | goto out_unroll; | |
516 | ||
517 | count++; | |
518 | } | |
519 | ||
520 | return 0; | |
521 | ||
522 | out_unroll: | |
523 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
524 | if (!count) | |
525 | break; | |
526 | kobject_del(&entry->kobj); | |
527 | kobject_put(&entry->kobj); | |
528 | count--; | |
529 | } | |
530 | return ret; | |
531 | } | |
532 | ||
1da177e4 LT |
533 | /** |
534 | * msi_capability_init - configure device's MSI capability structure | |
535 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 536 | * @nvec: number of interrupts to allocate |
1da177e4 | 537 | * |
1c8d7b0a MW |
538 | * Setup the MSI capability structure of the device with the requested |
539 | * number of interrupts. A return value of zero indicates the successful | |
540 | * setup of an entry with the new MSI irq. A negative return value indicates | |
541 | * an error, and a positive return value indicates the number of interrupts | |
542 | * which could have been allocated. | |
543 | */ | |
544 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
545 | { |
546 | struct msi_desc *entry; | |
f465136d | 547 | int ret; |
1da177e4 | 548 | u16 control; |
f2440d9a | 549 | unsigned mask; |
1da177e4 | 550 | |
e375b561 | 551 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 552 | |
f84ecd28 | 553 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
1da177e4 | 554 | /* MSI Entry Initialization */ |
379f5327 | 555 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
556 | if (!entry) |
557 | return -ENOMEM; | |
1ce03373 | 558 | |
500559a9 | 559 | entry->msi_attrib.is_msix = 0; |
4987ce82 | 560 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
500559a9 | 561 | entry->msi_attrib.entry_nr = 0; |
4987ce82 | 562 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
500559a9 | 563 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
f465136d | 564 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 565 | |
e5f66eaf DC |
566 | if (control & PCI_MSI_FLAGS_64BIT) |
567 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
568 | else | |
569 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
f2440d9a MW |
570 | /* All MSIs are unmasked by default, Mask them all */ |
571 | if (entry->msi_attrib.maskbit) | |
572 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
573 | mask = msi_capable_mask(control); | |
574 | msi_mask_irq(entry, mask, mask); | |
575 | ||
0dd11f9b | 576 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 577 | |
1da177e4 | 578 | /* Configure MSI capability structure */ |
1c8d7b0a | 579 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 580 | if (ret) { |
7ba1930d | 581 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 582 | free_msi_irqs(dev); |
7fe3730d | 583 | return ret; |
fd58e55f | 584 | } |
f7feaca7 | 585 | |
da8d1c8b NH |
586 | ret = populate_msi_sysfs(dev); |
587 | if (ret) { | |
588 | msi_mask_irq(entry, mask, ~mask); | |
589 | free_msi_irqs(dev); | |
590 | return ret; | |
591 | } | |
592 | ||
1da177e4 | 593 | /* Set MSI enabled bits */ |
ba698ad4 | 594 | pci_intx_for_msi(dev, 0); |
e375b561 | 595 | msi_set_enable(dev, 1); |
b1cbf4e4 | 596 | dev->msi_enabled = 1; |
1da177e4 | 597 | |
7fe3730d | 598 | dev->irq = entry->irq; |
1da177e4 LT |
599 | return 0; |
600 | } | |
601 | ||
520fe9dc | 602 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 603 | { |
4302e0fb | 604 | resource_size_t phys_addr; |
5a05a9d8 HS |
605 | u32 table_offset; |
606 | u8 bir; | |
607 | ||
909094c6 BH |
608 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
609 | &table_offset); | |
4d18760c BH |
610 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
611 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
612 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
613 | ||
614 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
615 | } | |
616 | ||
520fe9dc GS |
617 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
618 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
619 | { |
620 | struct msi_desc *entry; | |
621 | int i; | |
622 | ||
623 | for (i = 0; i < nvec; i++) { | |
624 | entry = alloc_msi_entry(dev); | |
625 | if (!entry) { | |
626 | if (!i) | |
627 | iounmap(base); | |
628 | else | |
629 | free_msi_irqs(dev); | |
630 | /* No enough memory. Don't try again */ | |
631 | return -ENOMEM; | |
632 | } | |
633 | ||
634 | entry->msi_attrib.is_msix = 1; | |
635 | entry->msi_attrib.is_64 = 1; | |
636 | entry->msi_attrib.entry_nr = entries[i].entry; | |
637 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 638 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
639 | entry->mask_base = base; |
640 | ||
641 | list_add_tail(&entry->list, &dev->msi_list); | |
642 | } | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
75cb3426 | 647 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 648 | struct msix_entry *entries) |
75cb3426 HS |
649 | { |
650 | struct msi_desc *entry; | |
651 | int i = 0; | |
652 | ||
653 | list_for_each_entry(entry, &dev->msi_list, list) { | |
654 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
655 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
656 | ||
657 | entries[i].vector = entry->irq; | |
dced35ae | 658 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
659 | entry->masked = readl(entry->mask_base + offset); |
660 | msix_mask_irq(entry, 1); | |
661 | i++; | |
662 | } | |
663 | } | |
664 | ||
1da177e4 LT |
665 | /** |
666 | * msix_capability_init - configure device's MSI-X capability | |
667 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
668 | * @entries: pointer to an array of struct msix_entry entries |
669 | * @nvec: number of @entries | |
1da177e4 | 670 | * |
eaae4b3a | 671 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
672 | * single MSI-X irq. A return of zero indicates the successful setup of |
673 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
674 | **/ |
675 | static int msix_capability_init(struct pci_dev *dev, | |
676 | struct msix_entry *entries, int nvec) | |
677 | { | |
520fe9dc | 678 | int ret; |
5a05a9d8 | 679 | u16 control; |
1da177e4 LT |
680 | void __iomem *base; |
681 | ||
520fe9dc | 682 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
f598282f MW |
683 | |
684 | /* Ensure MSI-X is disabled while it is set up */ | |
685 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 686 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 687 | |
1da177e4 | 688 | /* Request & Map MSI-X table region */ |
527eee29 | 689 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 690 | if (!base) |
1da177e4 LT |
691 | return -ENOMEM; |
692 | ||
520fe9dc | 693 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
694 | if (ret) |
695 | return ret; | |
9c831334 ME |
696 | |
697 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
698 | if (ret) |
699 | goto error; | |
9c831334 | 700 | |
f598282f MW |
701 | /* |
702 | * Some devices require MSI-X to be enabled before we can touch the | |
703 | * MSI-X registers. We need to mask all the vectors to prevent | |
704 | * interrupts coming in before they're fully set up. | |
705 | */ | |
706 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 707 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 708 | |
75cb3426 | 709 | msix_program_entries(dev, entries); |
f598282f | 710 | |
da8d1c8b NH |
711 | ret = populate_msi_sysfs(dev); |
712 | if (ret) { | |
713 | ret = 0; | |
714 | goto error; | |
715 | } | |
716 | ||
f598282f | 717 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 718 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 719 | dev->msix_enabled = 1; |
1da177e4 | 720 | |
f598282f | 721 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
520fe9dc | 722 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
8d181018 | 723 | |
1da177e4 | 724 | return 0; |
583871d4 HS |
725 | |
726 | error: | |
727 | if (ret < 0) { | |
728 | /* | |
729 | * If we had some success, report the number of irqs | |
730 | * we succeeded in setting up. | |
731 | */ | |
d9d7070e | 732 | struct msi_desc *entry; |
583871d4 HS |
733 | int avail = 0; |
734 | ||
735 | list_for_each_entry(entry, &dev->msi_list, list) { | |
736 | if (entry->irq != 0) | |
737 | avail++; | |
738 | } | |
739 | if (avail != 0) | |
740 | ret = avail; | |
741 | } | |
742 | ||
743 | free_msi_irqs(dev); | |
744 | ||
745 | return ret; | |
1da177e4 LT |
746 | } |
747 | ||
24334a12 | 748 | /** |
17bbc12a | 749 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 750 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 751 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 752 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 753 | * |
0306ebfa | 754 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
755 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
756 | * supported return 0, else return an error code. | |
24334a12 | 757 | **/ |
500559a9 | 758 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
759 | { |
760 | struct pci_bus *bus; | |
c9953a73 | 761 | int ret; |
24334a12 | 762 | |
0306ebfa | 763 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
764 | if (!pci_msi_enable || !dev || dev->no_msi) |
765 | return -EINVAL; | |
766 | ||
314e77b3 ME |
767 | /* |
768 | * You can't ask to have 0 or less MSIs configured. | |
769 | * a) it's stupid .. | |
770 | * b) the list manipulation code assumes nvec >= 1. | |
771 | */ | |
772 | if (nvec < 1) | |
773 | return -ERANGE; | |
774 | ||
500559a9 HS |
775 | /* |
776 | * Any bridge which does NOT route MSI transactions from its | |
777 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
778 | * the secondary pci_bus. |
779 | * We expect only arch-specific PCI host bus controller driver | |
780 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
781 | */ | |
24334a12 BG |
782 | for (bus = dev->bus; bus; bus = bus->parent) |
783 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
784 | return -EINVAL; | |
785 | ||
c9953a73 ME |
786 | ret = arch_msi_check_device(dev, nvec, type); |
787 | if (ret) | |
788 | return ret; | |
789 | ||
24334a12 BG |
790 | return 0; |
791 | } | |
792 | ||
1da177e4 | 793 | /** |
1c8d7b0a MW |
794 | * pci_enable_msi_block - configure device's MSI capability structure |
795 | * @dev: device to configure | |
796 | * @nvec: number of interrupts to configure | |
1da177e4 | 797 | * |
1c8d7b0a MW |
798 | * Allocate IRQs for a device with the MSI capability. |
799 | * This function returns a negative errno if an error occurs. If it | |
800 | * is unable to allocate the number of interrupts requested, it returns | |
801 | * the number of interrupts it might be able to allocate. If it successfully | |
802 | * allocates at least the number of interrupts requested, it returns 0 and | |
803 | * updates the @dev's irq member to the lowest new interrupt number; the | |
804 | * other interrupt numbers allocated to this device are consecutive. | |
805 | */ | |
806 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 807 | { |
f465136d | 808 | int status, maxvec; |
1c8d7b0a MW |
809 | u16 msgctl; |
810 | ||
f465136d | 811 | if (!dev->msi_cap) |
1c8d7b0a | 812 | return -EINVAL; |
f465136d GS |
813 | |
814 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
1c8d7b0a MW |
815 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
816 | if (nvec > maxvec) | |
817 | return maxvec; | |
1da177e4 | 818 | |
1c8d7b0a | 819 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
820 | if (status) |
821 | return status; | |
1da177e4 | 822 | |
ded86d8d | 823 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 824 | |
1c8d7b0a | 825 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 826 | if (dev->msix_enabled) { |
80ccba11 BH |
827 | dev_info(&dev->dev, "can't enable MSI " |
828 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 829 | return -EINVAL; |
1da177e4 | 830 | } |
1c8d7b0a MW |
831 | |
832 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
833 | return status; |
834 | } | |
1c8d7b0a | 835 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 836 | |
08261d87 AG |
837 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
838 | { | |
f465136d | 839 | int ret, nvec; |
08261d87 AG |
840 | u16 msgctl; |
841 | ||
f465136d | 842 | if (!dev->msi_cap) |
08261d87 AG |
843 | return -EINVAL; |
844 | ||
f465136d | 845 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); |
08261d87 AG |
846 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
847 | ||
848 | if (maxvec) | |
849 | *maxvec = ret; | |
850 | ||
851 | do { | |
852 | nvec = ret; | |
853 | ret = pci_enable_msi_block(dev, nvec); | |
854 | } while (ret > 0); | |
855 | ||
856 | if (ret < 0) | |
857 | return ret; | |
858 | return nvec; | |
859 | } | |
860 | EXPORT_SYMBOL(pci_enable_msi_block_auto); | |
861 | ||
f2440d9a | 862 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 863 | { |
f2440d9a MW |
864 | struct msi_desc *desc; |
865 | u32 mask; | |
866 | u16 ctrl; | |
1da177e4 | 867 | |
128bc5fc | 868 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
869 | return; |
870 | ||
110828c9 MW |
871 | BUG_ON(list_empty(&dev->msi_list)); |
872 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 873 | |
e375b561 | 874 | msi_set_enable(dev, 0); |
ba698ad4 | 875 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 876 | dev->msi_enabled = 0; |
7bd007e4 | 877 | |
12abb8ba | 878 | /* Return the device with MSI unmasked as initial states */ |
f5322169 | 879 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 880 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
881 | /* Keep cached state to be restored */ |
882 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
883 | |
884 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 885 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 886 | } |
24d27553 | 887 | |
500559a9 | 888 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 889 | { |
d52877c7 YL |
890 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
891 | return; | |
892 | ||
893 | pci_msi_shutdown(dev); | |
f56e4481 | 894 | free_msi_irqs(dev); |
da8d1c8b NH |
895 | kset_unregister(dev->msi_kset); |
896 | dev->msi_kset = NULL; | |
1da177e4 | 897 | } |
4cc086fa | 898 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 899 | |
a52e2e35 RW |
900 | /** |
901 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
902 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
903 | */ | |
904 | int pci_msix_table_size(struct pci_dev *dev) | |
905 | { | |
a52e2e35 RW |
906 | u16 control; |
907 | ||
520fe9dc | 908 | if (!dev->msix_cap) |
a52e2e35 RW |
909 | return 0; |
910 | ||
f84ecd28 | 911 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 912 | return msix_table_size(control); |
a52e2e35 RW |
913 | } |
914 | ||
1da177e4 LT |
915 | /** |
916 | * pci_enable_msix - configure device's MSI-X capability structure | |
917 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 918 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 919 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
920 | * |
921 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 922 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
923 | * MSI-X mode enabled on its hardware device function. A return of zero |
924 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 925 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 926 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
927 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
928 | * re-send its request. | |
1da177e4 | 929 | **/ |
500559a9 | 930 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 931 | { |
a52e2e35 | 932 | int status, nr_entries; |
ded86d8d | 933 | int i, j; |
1da177e4 | 934 | |
cdf1fd4d | 935 | if (!entries || !dev->msix_cap) |
500559a9 | 936 | return -EINVAL; |
1da177e4 | 937 | |
c9953a73 ME |
938 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
939 | if (status) | |
940 | return status; | |
941 | ||
a52e2e35 | 942 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 943 | if (nvec > nr_entries) |
57fbf52c | 944 | return nr_entries; |
1da177e4 LT |
945 | |
946 | /* Check for any invalid entries */ | |
947 | for (i = 0; i < nvec; i++) { | |
948 | if (entries[i].entry >= nr_entries) | |
949 | return -EINVAL; /* invalid entry */ | |
950 | for (j = i + 1; j < nvec; j++) { | |
951 | if (entries[i].entry == entries[j].entry) | |
952 | return -EINVAL; /* duplicate entry */ | |
953 | } | |
954 | } | |
ded86d8d | 955 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 956 | |
1ce03373 | 957 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 958 | if (dev->msi_enabled) { |
80ccba11 BH |
959 | dev_info(&dev->dev, "can't enable MSI-X " |
960 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
961 | return -EINVAL; |
962 | } | |
1da177e4 | 963 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
964 | return status; |
965 | } | |
4cc086fa | 966 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 967 | |
500559a9 | 968 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 969 | { |
12abb8ba HS |
970 | struct msi_desc *entry; |
971 | ||
128bc5fc | 972 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
973 | return; |
974 | ||
12abb8ba HS |
975 | /* Return the device with MSI-X masked as initial states */ |
976 | list_for_each_entry(entry, &dev->msi_list, list) { | |
977 | /* Keep cached states to be restored */ | |
978 | __msix_mask_irq(entry, 1); | |
979 | } | |
980 | ||
b1cbf4e4 | 981 | msix_set_enable(dev, 0); |
ba698ad4 | 982 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 983 | dev->msix_enabled = 0; |
d52877c7 | 984 | } |
c901851f | 985 | |
500559a9 | 986 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
987 | { |
988 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
989 | return; | |
990 | ||
991 | pci_msix_shutdown(dev); | |
f56e4481 | 992 | free_msi_irqs(dev); |
da8d1c8b NH |
993 | kset_unregister(dev->msi_kset); |
994 | dev->msi_kset = NULL; | |
1da177e4 | 995 | } |
4cc086fa | 996 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
997 | |
998 | /** | |
1ce03373 | 999 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1000 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1001 | * | |
eaae4b3a | 1002 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1003 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1004 | * allocated for this device function, are reclaimed to unused state, |
1005 | * which may be used later on. | |
1006 | **/ | |
500559a9 | 1007 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1008 | { |
1da177e4 | 1009 | if (!pci_msi_enable || !dev) |
500559a9 | 1010 | return; |
1da177e4 | 1011 | |
f56e4481 HS |
1012 | if (dev->msi_enabled || dev->msix_enabled) |
1013 | free_msi_irqs(dev); | |
1da177e4 LT |
1014 | } |
1015 | ||
309e57df MW |
1016 | void pci_no_msi(void) |
1017 | { | |
1018 | pci_msi_enable = 0; | |
1019 | } | |
c9953a73 | 1020 | |
07ae95f9 AP |
1021 | /** |
1022 | * pci_msi_enabled - is MSI enabled? | |
1023 | * | |
1024 | * Returns true if MSI has not been disabled by the command-line option | |
1025 | * pci=nomsi. | |
1026 | **/ | |
1027 | int pci_msi_enabled(void) | |
d389fec6 | 1028 | { |
07ae95f9 | 1029 | return pci_msi_enable; |
d389fec6 | 1030 | } |
07ae95f9 | 1031 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1032 | |
07ae95f9 | 1033 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1034 | { |
07ae95f9 | 1035 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1036 | |
1037 | /* Disable the msi hardware to avoid screaming interrupts | |
1038 | * during boot. This is the power on reset default so | |
1039 | * usually this should be a noop. | |
1040 | */ | |
e375b561 GS |
1041 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1042 | if (dev->msi_cap) | |
1043 | msi_set_enable(dev, 0); | |
1044 | ||
1045 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1046 | if (dev->msix_cap) | |
1047 | msix_set_enable(dev, 0); | |
d389fec6 | 1048 | } |