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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
11df1f05 ME |
30 | #ifndef arch_msi_check_device |
31 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
32 | { |
33 | return 0; | |
34 | } | |
11df1f05 | 35 | #endif |
6a9e7f20 | 36 | |
11df1f05 ME |
37 | #ifndef arch_setup_msi_irqs |
38 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
39 | { |
40 | struct msi_desc *entry; | |
41 | int ret; | |
42 | ||
1c8d7b0a MW |
43 | /* |
44 | * If an architecture wants to support multiple MSI, it needs to | |
45 | * override arch_setup_msi_irqs() | |
46 | */ | |
47 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
48 | return 1; | |
49 | ||
6a9e7f20 AB |
50 | list_for_each_entry(entry, &dev->msi_list, list) { |
51 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 52 | if (ret < 0) |
6a9e7f20 | 53 | return ret; |
b5fbf533 ME |
54 | if (ret > 0) |
55 | return -ENOSPC; | |
6a9e7f20 AB |
56 | } |
57 | ||
58 | return 0; | |
59 | } | |
11df1f05 | 60 | #endif |
6a9e7f20 | 61 | |
11df1f05 ME |
62 | #ifndef arch_teardown_msi_irqs |
63 | void arch_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
64 | { |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
68 | int i, nvec; |
69 | if (entry->irq == 0) | |
70 | continue; | |
71 | nvec = 1 << entry->msi_attrib.multiple; | |
72 | for (i = 0; i < nvec; i++) | |
73 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
74 | } |
75 | } | |
11df1f05 | 76 | #endif |
6a9e7f20 | 77 | |
5ca5c02f | 78 | static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 79 | { |
b1cbf4e4 EB |
80 | u16 control; |
81 | ||
b1cbf4e4 EB |
82 | if (pos) { |
83 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
84 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
85 | if (enable) | |
86 | control |= PCI_MSI_FLAGS_ENABLE; | |
87 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
88 | } | |
89 | } | |
90 | ||
5ca5c02f HS |
91 | static void msi_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); | |
94 | } | |
95 | ||
b1cbf4e4 EB |
96 | static void msix_set_enable(struct pci_dev *dev, int enable) |
97 | { | |
98 | int pos; | |
99 | u16 control; | |
100 | ||
101 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
102 | if (pos) { | |
103 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
104 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
105 | if (enable) | |
106 | control |= PCI_MSIX_FLAGS_ENABLE; | |
107 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
108 | } | |
109 | } | |
110 | ||
bffac3c5 MW |
111 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
112 | { | |
0b49ec37 MW |
113 | /* Don't shift by >= width of type */ |
114 | if (x >= 5) | |
115 | return 0xffffffff; | |
116 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
117 | } |
118 | ||
f2440d9a | 119 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 120 | { |
f2440d9a MW |
121 | return msi_mask((control >> 1) & 7); |
122 | } | |
988cbb15 | 123 | |
f2440d9a MW |
124 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
125 | { | |
126 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
127 | } |
128 | ||
ce6fce42 MW |
129 | /* |
130 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
131 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
132 | * reliably as devices without an INTx disable bit will then generate a | |
133 | * level IRQ which will never be cleared. | |
134 | * | |
135 | * Returns 1 if it succeeded in masking the interrupt and 0 if the device | |
136 | * doesn't support MSI masking. | |
137 | */ | |
f2440d9a | 138 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 139 | { |
f2440d9a | 140 | u32 mask_bits = desc->masked; |
1da177e4 | 141 | |
f2440d9a MW |
142 | if (!desc->msi_attrib.maskbit) |
143 | return; | |
144 | ||
145 | mask_bits &= ~mask; | |
146 | mask_bits |= flag; | |
147 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
148 | desc->masked = mask_bits; | |
149 | } | |
150 | ||
151 | /* | |
152 | * This internal function does not flush PCI writes to the device. | |
153 | * All users must ensure that they read from the device before either | |
154 | * assuming that the device state is up to date, or returning out of this | |
155 | * file. This saves a few milliseconds when initialising devices with lots | |
156 | * of MSI-X interrupts. | |
157 | */ | |
158 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
159 | { | |
160 | u32 mask_bits = desc->masked; | |
161 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
162 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
163 | mask_bits &= ~1; | |
164 | mask_bits |= flag; | |
165 | writel(mask_bits, desc->mask_base + offset); | |
166 | desc->masked = mask_bits; | |
167 | } | |
24d27553 | 168 | |
f2440d9a MW |
169 | static void msi_set_mask_bit(unsigned irq, u32 flag) |
170 | { | |
171 | struct msi_desc *desc = get_irq_msi(irq); | |
24d27553 | 172 | |
f2440d9a MW |
173 | if (desc->msi_attrib.is_msix) { |
174 | msix_mask_irq(desc, flag); | |
175 | readl(desc->mask_base); /* Flush write to device */ | |
176 | } else { | |
1c8d7b0a MW |
177 | unsigned offset = irq - desc->dev->irq; |
178 | msi_mask_irq(desc, 1 << offset, flag << offset); | |
1da177e4 | 179 | } |
f2440d9a MW |
180 | } |
181 | ||
182 | void mask_msi_irq(unsigned int irq) | |
183 | { | |
184 | msi_set_mask_bit(irq, 1); | |
185 | } | |
186 | ||
187 | void unmask_msi_irq(unsigned int irq) | |
188 | { | |
189 | msi_set_mask_bit(irq, 0); | |
1da177e4 LT |
190 | } |
191 | ||
3145e941 | 192 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 193 | { |
3145e941 | 194 | struct msi_desc *entry = get_irq_desc_msi(desc); |
24d27553 MW |
195 | if (entry->msi_attrib.is_msix) { |
196 | void __iomem *base = entry->mask_base + | |
197 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
198 | ||
199 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
200 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
201 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
202 | } else { | |
0366f8f7 EB |
203 | struct pci_dev *dev = entry->dev; |
204 | int pos = entry->msi_attrib.pos; | |
205 | u16 data; | |
206 | ||
207 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
208 | &msg->address_lo); | |
209 | if (entry->msi_attrib.is_64) { | |
210 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
211 | &msg->address_hi); | |
212 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
213 | } else { | |
214 | msg->address_hi = 0; | |
cbf5d9e6 | 215 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
216 | } |
217 | msg->data = data; | |
0366f8f7 EB |
218 | } |
219 | } | |
1da177e4 | 220 | |
3145e941 | 221 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 222 | { |
3145e941 YL |
223 | struct irq_desc *desc = irq_to_desc(irq); |
224 | ||
225 | read_msi_msg_desc(desc, msg); | |
226 | } | |
227 | ||
228 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
229 | { | |
230 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
24d27553 MW |
231 | if (entry->msi_attrib.is_msix) { |
232 | void __iomem *base; | |
233 | base = entry->mask_base + | |
234 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
235 | ||
236 | writel(msg->address_lo, | |
237 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
238 | writel(msg->address_hi, | |
239 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
240 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
241 | } else { | |
0366f8f7 EB |
242 | struct pci_dev *dev = entry->dev; |
243 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
244 | u16 msgctl; |
245 | ||
246 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
247 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
248 | msgctl |= entry->msi_attrib.multiple << 4; | |
249 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
250 | |
251 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
252 | msg->address_lo); | |
253 | if (entry->msi_attrib.is_64) { | |
254 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
255 | msg->address_hi); | |
256 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
257 | msg->data); | |
258 | } else { | |
259 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
260 | msg->data); | |
261 | } | |
1da177e4 | 262 | } |
392ee1e6 | 263 | entry->msg = *msg; |
1da177e4 | 264 | } |
0366f8f7 | 265 | |
3145e941 YL |
266 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
267 | { | |
268 | struct irq_desc *desc = irq_to_desc(irq); | |
269 | ||
270 | write_msi_msg_desc(desc, msg); | |
271 | } | |
272 | ||
032de8e2 | 273 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 274 | |
379f5327 | 275 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 276 | { |
379f5327 MW |
277 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
278 | if (!desc) | |
1da177e4 LT |
279 | return NULL; |
280 | ||
379f5327 MW |
281 | INIT_LIST_HEAD(&desc->list); |
282 | desc->dev = dev; | |
1da177e4 | 283 | |
379f5327 | 284 | return desc; |
1da177e4 LT |
285 | } |
286 | ||
ba698ad4 DM |
287 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
288 | { | |
289 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
290 | pci_intx(dev, enable); | |
291 | } | |
292 | ||
8fed4b65 | 293 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 294 | { |
392ee1e6 | 295 | int pos; |
41017f0c | 296 | u16 control; |
392ee1e6 | 297 | struct msi_desc *entry; |
41017f0c | 298 | |
b1cbf4e4 EB |
299 | if (!dev->msi_enabled) |
300 | return; | |
301 | ||
392ee1e6 EB |
302 | entry = get_irq_msi(dev->irq); |
303 | pos = entry->msi_attrib.pos; | |
41017f0c | 304 | |
ba698ad4 | 305 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 306 | msi_set_enable(dev, 0); |
392ee1e6 | 307 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
308 | |
309 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 310 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 311 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 312 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 313 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
314 | } |
315 | ||
316 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 317 | { |
41017f0c | 318 | int pos; |
41017f0c | 319 | struct msi_desc *entry; |
392ee1e6 | 320 | u16 control; |
41017f0c | 321 | |
ded86d8d EB |
322 | if (!dev->msix_enabled) |
323 | return; | |
324 | ||
41017f0c | 325 | /* route the table */ |
ba698ad4 | 326 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 327 | msix_set_enable(dev, 0); |
41017f0c | 328 | |
4aa9bc95 ME |
329 | list_for_each_entry(entry, &dev->msi_list, list) { |
330 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 331 | msix_mask_irq(entry, entry->masked); |
41017f0c | 332 | } |
41017f0c | 333 | |
314e77b3 ME |
334 | BUG_ON(list_empty(&dev->msi_list)); |
335 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 336 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
337 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
338 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
339 | control |= PCI_MSIX_FLAGS_ENABLE; | |
340 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 341 | } |
8fed4b65 ME |
342 | |
343 | void pci_restore_msi_state(struct pci_dev *dev) | |
344 | { | |
345 | __pci_restore_msi_state(dev); | |
346 | __pci_restore_msix_state(dev); | |
347 | } | |
94688cf2 | 348 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 349 | |
1da177e4 LT |
350 | /** |
351 | * msi_capability_init - configure device's MSI capability structure | |
352 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 353 | * @nvec: number of interrupts to allocate |
1da177e4 | 354 | * |
1c8d7b0a MW |
355 | * Setup the MSI capability structure of the device with the requested |
356 | * number of interrupts. A return value of zero indicates the successful | |
357 | * setup of an entry with the new MSI irq. A negative return value indicates | |
358 | * an error, and a positive return value indicates the number of interrupts | |
359 | * which could have been allocated. | |
360 | */ | |
361 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
362 | { |
363 | struct msi_desc *entry; | |
7fe3730d | 364 | int pos, ret; |
1da177e4 | 365 | u16 control; |
f2440d9a | 366 | unsigned mask; |
1da177e4 | 367 | |
b1cbf4e4 EB |
368 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
369 | ||
1da177e4 LT |
370 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
371 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
372 | /* MSI Entry Initialization */ | |
379f5327 | 373 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
374 | if (!entry) |
375 | return -ENOMEM; | |
1ce03373 | 376 | |
24d27553 | 377 | entry->msi_attrib.is_msix = 0; |
0366f8f7 | 378 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
379 | entry->msi_attrib.entry_nr = 0; |
380 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 381 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 382 | entry->msi_attrib.pos = pos; |
f2440d9a MW |
383 | |
384 | entry->mask_pos = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); | |
385 | /* All MSIs are unmasked by default, Mask them all */ | |
386 | if (entry->msi_attrib.maskbit) | |
387 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
388 | mask = msi_capable_mask(control); | |
389 | msi_mask_irq(entry, mask, mask); | |
390 | ||
0dd11f9b | 391 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 392 | |
1da177e4 | 393 | /* Configure MSI capability structure */ |
1c8d7b0a | 394 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 395 | if (ret) { |
032de8e2 | 396 | msi_free_irqs(dev); |
7fe3730d | 397 | return ret; |
fd58e55f | 398 | } |
f7feaca7 | 399 | |
1da177e4 | 400 | /* Set MSI enabled bits */ |
ba698ad4 | 401 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
402 | msi_set_enable(dev, 1); |
403 | dev->msi_enabled = 1; | |
1da177e4 | 404 | |
7fe3730d | 405 | dev->irq = entry->irq; |
1da177e4 LT |
406 | return 0; |
407 | } | |
408 | ||
409 | /** | |
410 | * msix_capability_init - configure device's MSI-X capability | |
411 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
412 | * @entries: pointer to an array of struct msix_entry entries |
413 | * @nvec: number of @entries | |
1da177e4 | 414 | * |
eaae4b3a | 415 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
416 | * single MSI-X irq. A return of zero indicates the successful setup of |
417 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
418 | **/ |
419 | static int msix_capability_init(struct pci_dev *dev, | |
420 | struct msix_entry *entries, int nvec) | |
421 | { | |
4aa9bc95 | 422 | struct msi_desc *entry; |
9c831334 | 423 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
424 | unsigned long phys_addr; |
425 | u32 table_offset; | |
1da177e4 LT |
426 | u16 control; |
427 | u8 bir; | |
428 | void __iomem *base; | |
429 | ||
b1cbf4e4 EB |
430 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
431 | ||
1da177e4 LT |
432 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
433 | /* Request & Map MSI-X table region */ | |
434 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
435 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
436 | |
437 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 438 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
439 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
440 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
441 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
442 | if (base == NULL) | |
443 | return -ENOMEM; | |
444 | ||
445 | /* MSI-X Table Initialization */ | |
446 | for (i = 0; i < nvec; i++) { | |
379f5327 | 447 | entry = alloc_msi_entry(dev); |
f7feaca7 | 448 | if (!entry) |
1da177e4 | 449 | break; |
1da177e4 LT |
450 | |
451 | j = entries[i].entry; | |
24d27553 | 452 | entry->msi_attrib.is_msix = 1; |
0366f8f7 | 453 | entry->msi_attrib.is_64 = 1; |
1da177e4 | 454 | entry->msi_attrib.entry_nr = j; |
1ce03373 | 455 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 456 | entry->msi_attrib.pos = pos; |
1da177e4 | 457 | entry->mask_base = base; |
f2440d9a MW |
458 | entry->masked = readl(base + j * PCI_MSIX_ENTRY_SIZE + |
459 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
460 | msix_mask_irq(entry, 1); | |
f7feaca7 | 461 | |
0dd11f9b | 462 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 463 | } |
9c831334 ME |
464 | |
465 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
b5fbf533 ME |
466 | if (ret < 0) { |
467 | /* If we had some success report the number of irqs | |
468 | * we succeeded in setting up. */ | |
9c831334 ME |
469 | int avail = 0; |
470 | list_for_each_entry(entry, &dev->msi_list, list) { | |
471 | if (entry->irq != 0) { | |
472 | avail++; | |
9c831334 | 473 | } |
1da177e4 | 474 | } |
9c831334 | 475 | |
b5fbf533 ME |
476 | if (avail != 0) |
477 | ret = avail; | |
478 | } | |
032de8e2 | 479 | |
b5fbf533 ME |
480 | if (ret) { |
481 | msi_free_irqs(dev); | |
482 | return ret; | |
1da177e4 | 483 | } |
9c831334 ME |
484 | |
485 | i = 0; | |
486 | list_for_each_entry(entry, &dev->msi_list, list) { | |
487 | entries[i].vector = entry->irq; | |
488 | set_irq_msi(entry->irq, entry); | |
489 | i++; | |
490 | } | |
1da177e4 | 491 | /* Set MSI-X enabled bits */ |
ba698ad4 | 492 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
493 | msix_set_enable(dev, 1); |
494 | dev->msix_enabled = 1; | |
1da177e4 LT |
495 | |
496 | return 0; | |
497 | } | |
498 | ||
24334a12 | 499 | /** |
17bbc12a | 500 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 501 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 502 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 503 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 504 | * |
0306ebfa | 505 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
506 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
507 | * supported return 0, else return an error code. | |
24334a12 | 508 | **/ |
c9953a73 | 509 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
510 | { |
511 | struct pci_bus *bus; | |
c9953a73 | 512 | int ret; |
24334a12 | 513 | |
0306ebfa | 514 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
515 | if (!pci_msi_enable || !dev || dev->no_msi) |
516 | return -EINVAL; | |
517 | ||
314e77b3 ME |
518 | /* |
519 | * You can't ask to have 0 or less MSIs configured. | |
520 | * a) it's stupid .. | |
521 | * b) the list manipulation code assumes nvec >= 1. | |
522 | */ | |
523 | if (nvec < 1) | |
524 | return -ERANGE; | |
525 | ||
0306ebfa BG |
526 | /* Any bridge which does NOT route MSI transactions from it's |
527 | * secondary bus to it's primary bus must set NO_MSI flag on | |
528 | * the secondary pci_bus. | |
529 | * We expect only arch-specific PCI host bus controller driver | |
530 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
531 | */ | |
24334a12 BG |
532 | for (bus = dev->bus; bus; bus = bus->parent) |
533 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
534 | return -EINVAL; | |
535 | ||
c9953a73 ME |
536 | ret = arch_msi_check_device(dev, nvec, type); |
537 | if (ret) | |
538 | return ret; | |
539 | ||
b1e2303d ME |
540 | if (!pci_find_capability(dev, type)) |
541 | return -EINVAL; | |
542 | ||
24334a12 BG |
543 | return 0; |
544 | } | |
545 | ||
1da177e4 | 546 | /** |
1c8d7b0a MW |
547 | * pci_enable_msi_block - configure device's MSI capability structure |
548 | * @dev: device to configure | |
549 | * @nvec: number of interrupts to configure | |
1da177e4 | 550 | * |
1c8d7b0a MW |
551 | * Allocate IRQs for a device with the MSI capability. |
552 | * This function returns a negative errno if an error occurs. If it | |
553 | * is unable to allocate the number of interrupts requested, it returns | |
554 | * the number of interrupts it might be able to allocate. If it successfully | |
555 | * allocates at least the number of interrupts requested, it returns 0 and | |
556 | * updates the @dev's irq member to the lowest new interrupt number; the | |
557 | * other interrupt numbers allocated to this device are consecutive. | |
558 | */ | |
559 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 560 | { |
1c8d7b0a MW |
561 | int status, pos, maxvec; |
562 | u16 msgctl; | |
563 | ||
564 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
565 | if (!pos) | |
566 | return -EINVAL; | |
567 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
568 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
569 | if (nvec > maxvec) | |
570 | return maxvec; | |
1da177e4 | 571 | |
1c8d7b0a | 572 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
573 | if (status) |
574 | return status; | |
1da177e4 | 575 | |
ded86d8d | 576 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 577 | |
1c8d7b0a | 578 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 579 | if (dev->msix_enabled) { |
80ccba11 BH |
580 | dev_info(&dev->dev, "can't enable MSI " |
581 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 582 | return -EINVAL; |
1da177e4 | 583 | } |
1c8d7b0a MW |
584 | |
585 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
586 | return status; |
587 | } | |
1c8d7b0a | 588 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 589 | |
f2440d9a | 590 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 591 | { |
f2440d9a MW |
592 | struct msi_desc *desc; |
593 | u32 mask; | |
594 | u16 ctrl; | |
1da177e4 | 595 | |
128bc5fc | 596 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
597 | return; |
598 | ||
b1cbf4e4 | 599 | msi_set_enable(dev, 0); |
ba698ad4 | 600 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 601 | dev->msi_enabled = 0; |
7bd007e4 | 602 | |
314e77b3 | 603 | BUG_ON(list_empty(&dev->msi_list)); |
f2440d9a MW |
604 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); |
605 | pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &ctrl); | |
606 | mask = msi_capable_mask(ctrl); | |
607 | msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
608 | |
609 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 610 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 611 | } |
24d27553 | 612 | |
d52877c7 YL |
613 | void pci_disable_msi(struct pci_dev* dev) |
614 | { | |
615 | struct msi_desc *entry; | |
616 | ||
617 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
618 | return; | |
619 | ||
620 | pci_msi_shutdown(dev); | |
621 | ||
622 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
379f5327 | 623 | if (entry->msi_attrib.is_msix) |
d52877c7 YL |
624 | return; |
625 | ||
626 | msi_free_irqs(dev); | |
1da177e4 | 627 | } |
4cc086fa | 628 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 629 | |
032de8e2 | 630 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 631 | { |
032de8e2 | 632 | struct msi_desc *entry, *tmp; |
7ede9c1f | 633 | |
b3b7cc7b | 634 | list_for_each_entry(entry, &dev->msi_list, list) { |
1c8d7b0a MW |
635 | int i, nvec; |
636 | if (!entry->irq) | |
637 | continue; | |
638 | nvec = 1 << entry->msi_attrib.multiple; | |
639 | for (i = 0; i < nvec; i++) | |
640 | BUG_ON(irq_has_action(entry->irq + i)); | |
b3b7cc7b | 641 | } |
1da177e4 | 642 | |
032de8e2 | 643 | arch_teardown_msi_irqs(dev); |
1da177e4 | 644 | |
032de8e2 | 645 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
24d27553 | 646 | if (entry->msi_attrib.is_msix) { |
032de8e2 ME |
647 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
648 | * PCI_MSIX_ENTRY_SIZE | |
649 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
650 | |
651 | if (list_is_last(&entry->list, &dev->msi_list)) | |
652 | iounmap(entry->mask_base); | |
032de8e2 ME |
653 | } |
654 | list_del(&entry->list); | |
655 | kfree(entry); | |
1da177e4 LT |
656 | } |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
a52e2e35 RW |
661 | /** |
662 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
663 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
664 | */ | |
665 | int pci_msix_table_size(struct pci_dev *dev) | |
666 | { | |
667 | int pos; | |
668 | u16 control; | |
669 | ||
670 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
671 | if (!pos) | |
672 | return 0; | |
673 | ||
674 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
675 | return multi_msix_capable(control); | |
676 | } | |
677 | ||
1da177e4 LT |
678 | /** |
679 | * pci_enable_msix - configure device's MSI-X capability structure | |
680 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 681 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 682 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
683 | * |
684 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 685 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
686 | * MSI-X mode enabled on its hardware device function. A return of zero |
687 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 688 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 689 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 690 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
691 | * its request. |
692 | **/ | |
693 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
694 | { | |
a52e2e35 | 695 | int status, nr_entries; |
ded86d8d | 696 | int i, j; |
1da177e4 | 697 | |
c9953a73 | 698 | if (!entries) |
1da177e4 LT |
699 | return -EINVAL; |
700 | ||
c9953a73 ME |
701 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
702 | if (status) | |
703 | return status; | |
704 | ||
a52e2e35 | 705 | nr_entries = pci_msix_table_size(dev); |
1da177e4 LT |
706 | if (nvec > nr_entries) |
707 | return -EINVAL; | |
708 | ||
709 | /* Check for any invalid entries */ | |
710 | for (i = 0; i < nvec; i++) { | |
711 | if (entries[i].entry >= nr_entries) | |
712 | return -EINVAL; /* invalid entry */ | |
713 | for (j = i + 1; j < nvec; j++) { | |
714 | if (entries[i].entry == entries[j].entry) | |
715 | return -EINVAL; /* duplicate entry */ | |
716 | } | |
717 | } | |
ded86d8d | 718 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 719 | |
1ce03373 | 720 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 721 | if (dev->msi_enabled) { |
80ccba11 BH |
722 | dev_info(&dev->dev, "can't enable MSI-X " |
723 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
724 | return -EINVAL; |
725 | } | |
1da177e4 | 726 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
727 | return status; |
728 | } | |
4cc086fa | 729 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 730 | |
fc4afc7b | 731 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 732 | { |
032de8e2 | 733 | msi_free_irqs(dev); |
fc4afc7b ME |
734 | } |
735 | ||
d52877c7 | 736 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 737 | { |
128bc5fc | 738 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
739 | return; |
740 | ||
b1cbf4e4 | 741 | msix_set_enable(dev, 0); |
ba698ad4 | 742 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 743 | dev->msix_enabled = 0; |
d52877c7 YL |
744 | } |
745 | void pci_disable_msix(struct pci_dev* dev) | |
746 | { | |
747 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
748 | return; | |
749 | ||
750 | pci_msix_shutdown(dev); | |
7bd007e4 | 751 | |
fc4afc7b | 752 | msix_free_all_irqs(dev); |
1da177e4 | 753 | } |
4cc086fa | 754 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
755 | |
756 | /** | |
1ce03373 | 757 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
758 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
759 | * | |
eaae4b3a | 760 | * Being called during hotplug remove, from which the device function |
1ce03373 | 761 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
762 | * allocated for this device function, are reclaimed to unused state, |
763 | * which may be used later on. | |
764 | **/ | |
765 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
766 | { | |
1da177e4 LT |
767 | if (!pci_msi_enable || !dev) |
768 | return; | |
769 | ||
032de8e2 ME |
770 | if (dev->msi_enabled) |
771 | msi_free_irqs(dev); | |
1da177e4 | 772 | |
fc4afc7b ME |
773 | if (dev->msix_enabled) |
774 | msix_free_all_irqs(dev); | |
1da177e4 LT |
775 | } |
776 | ||
309e57df MW |
777 | void pci_no_msi(void) |
778 | { | |
779 | pci_msi_enable = 0; | |
780 | } | |
c9953a73 | 781 | |
07ae95f9 AP |
782 | /** |
783 | * pci_msi_enabled - is MSI enabled? | |
784 | * | |
785 | * Returns true if MSI has not been disabled by the command-line option | |
786 | * pci=nomsi. | |
787 | **/ | |
788 | int pci_msi_enabled(void) | |
d389fec6 | 789 | { |
07ae95f9 | 790 | return pci_msi_enable; |
d389fec6 | 791 | } |
07ae95f9 | 792 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 793 | |
07ae95f9 | 794 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 795 | { |
07ae95f9 | 796 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 797 | } |