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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
527eee29 BH |
28 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
29 | ||
30 | ||
6a9e7f20 AB |
31 | /* Arch hooks */ |
32 | ||
4287d824 TP |
33 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
34 | { | |
0cbdcfcf TR |
35 | struct msi_chip *chip = dev->bus->msi; |
36 | int err; | |
37 | ||
38 | if (!chip || !chip->setup_irq) | |
39 | return -EINVAL; | |
40 | ||
41 | err = chip->setup_irq(chip, dev, desc); | |
42 | if (err < 0) | |
43 | return err; | |
44 | ||
45 | irq_set_chip_data(desc->irq, chip); | |
46 | ||
47 | return 0; | |
4287d824 TP |
48 | } |
49 | ||
50 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 51 | { |
0cbdcfcf TR |
52 | struct msi_chip *chip = irq_get_chip_data(irq); |
53 | ||
54 | if (!chip || !chip->teardown_irq) | |
55 | return; | |
56 | ||
57 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
58 | } |
59 | ||
4287d824 TP |
60 | int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) |
61 | { | |
0cbdcfcf TR |
62 | struct msi_chip *chip = dev->bus->msi; |
63 | ||
64 | if (!chip || !chip->check_device) | |
65 | return 0; | |
66 | ||
67 | return chip->check_device(chip, dev, nvec, type); | |
4287d824 | 68 | } |
1525bf0d | 69 | |
4287d824 | 70 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
71 | { |
72 | struct msi_desc *entry; | |
73 | int ret; | |
74 | ||
1c8d7b0a MW |
75 | /* |
76 | * If an architecture wants to support multiple MSI, it needs to | |
77 | * override arch_setup_msi_irqs() | |
78 | */ | |
79 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
80 | return 1; | |
81 | ||
6a9e7f20 AB |
82 | list_for_each_entry(entry, &dev->msi_list, list) { |
83 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 84 | if (ret < 0) |
6a9e7f20 | 85 | return ret; |
b5fbf533 ME |
86 | if (ret > 0) |
87 | return -ENOSPC; | |
6a9e7f20 AB |
88 | } |
89 | ||
90 | return 0; | |
91 | } | |
1525bf0d | 92 | |
4287d824 TP |
93 | /* |
94 | * We have a default implementation available as a separate non-weak | |
95 | * function, as it is used by the Xen x86 PCI code | |
96 | */ | |
1525bf0d | 97 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
98 | { |
99 | struct msi_desc *entry; | |
100 | ||
101 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
102 | int i, nvec; |
103 | if (entry->irq == 0) | |
104 | continue; | |
65f6ae66 AG |
105 | if (entry->nvec_used) |
106 | nvec = entry->nvec_used; | |
107 | else | |
108 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
109 | for (i = 0; i < nvec; i++) |
110 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
111 | } |
112 | } | |
113 | ||
4287d824 TP |
114 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
115 | { | |
116 | return default_teardown_msi_irqs(dev); | |
117 | } | |
76ccc297 | 118 | |
ac8344c4 | 119 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
120 | { |
121 | struct msi_desc *entry; | |
122 | ||
123 | entry = NULL; | |
124 | if (dev->msix_enabled) { | |
125 | list_for_each_entry(entry, &dev->msi_list, list) { | |
126 | if (irq == entry->irq) | |
127 | break; | |
128 | } | |
129 | } else if (dev->msi_enabled) { | |
130 | entry = irq_get_msi_desc(irq); | |
131 | } | |
132 | ||
133 | if (entry) | |
134 | write_msi_msg(irq, &entry->msg); | |
135 | } | |
4287d824 | 136 | |
ac8344c4 | 137 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 138 | { |
ac8344c4 | 139 | return default_restore_msi_irqs(dev); |
4287d824 | 140 | } |
76ccc297 | 141 | |
e375b561 | 142 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 143 | { |
b1cbf4e4 EB |
144 | u16 control; |
145 | ||
e375b561 | 146 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
147 | control &= ~PCI_MSI_FLAGS_ENABLE; |
148 | if (enable) | |
149 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 150 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
151 | } |
152 | ||
b1cbf4e4 EB |
153 | static void msix_set_enable(struct pci_dev *dev, int enable) |
154 | { | |
b1cbf4e4 EB |
155 | u16 control; |
156 | ||
e375b561 GS |
157 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
158 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
159 | if (enable) | |
160 | control |= PCI_MSIX_FLAGS_ENABLE; | |
161 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
162 | } |
163 | ||
bffac3c5 MW |
164 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
165 | { | |
0b49ec37 MW |
166 | /* Don't shift by >= width of type */ |
167 | if (x >= 5) | |
168 | return 0xffffffff; | |
169 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
170 | } |
171 | ||
f2440d9a | 172 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 173 | { |
f2440d9a MW |
174 | return msi_mask((control >> 1) & 7); |
175 | } | |
988cbb15 | 176 | |
f2440d9a MW |
177 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
178 | { | |
179 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
180 | } |
181 | ||
ce6fce42 MW |
182 | /* |
183 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
184 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
185 | * reliably as devices without an INTx disable bit will then generate a | |
186 | * level IRQ which will never be cleared. | |
ce6fce42 | 187 | */ |
0e4ccb15 | 188 | u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 189 | { |
f2440d9a | 190 | u32 mask_bits = desc->masked; |
1da177e4 | 191 | |
f2440d9a | 192 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 193 | return 0; |
f2440d9a MW |
194 | |
195 | mask_bits &= ~mask; | |
196 | mask_bits |= flag; | |
197 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
198 | |
199 | return mask_bits; | |
200 | } | |
201 | ||
0e4ccb15 KRW |
202 | __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
203 | { | |
204 | return default_msi_mask_irq(desc, mask, flag); | |
205 | } | |
206 | ||
12abb8ba HS |
207 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
208 | { | |
0e4ccb15 | 209 | desc->masked = arch_msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
210 | } |
211 | ||
212 | /* | |
213 | * This internal function does not flush PCI writes to the device. | |
214 | * All users must ensure that they read from the device before either | |
215 | * assuming that the device state is up to date, or returning out of this | |
216 | * file. This saves a few milliseconds when initialising devices with lots | |
217 | * of MSI-X interrupts. | |
218 | */ | |
0e4ccb15 | 219 | u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
220 | { |
221 | u32 mask_bits = desc->masked; | |
222 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 223 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
224 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
225 | if (flag) | |
226 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 227 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
228 | |
229 | return mask_bits; | |
230 | } | |
231 | ||
0e4ccb15 KRW |
232 | __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag) |
233 | { | |
234 | return default_msix_mask_irq(desc, flag); | |
235 | } | |
236 | ||
12abb8ba HS |
237 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
238 | { | |
0e4ccb15 | 239 | desc->masked = arch_msix_mask_irq(desc, flag); |
f2440d9a | 240 | } |
24d27553 | 241 | |
1c9db525 | 242 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 243 | { |
1c9db525 | 244 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 245 | |
f2440d9a MW |
246 | if (desc->msi_attrib.is_msix) { |
247 | msix_mask_irq(desc, flag); | |
248 | readl(desc->mask_base); /* Flush write to device */ | |
249 | } else { | |
1c9db525 | 250 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 251 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 252 | } |
f2440d9a MW |
253 | } |
254 | ||
1c9db525 | 255 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 256 | { |
1c9db525 | 257 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
258 | } |
259 | ||
1c9db525 | 260 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 261 | { |
1c9db525 | 262 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
263 | } |
264 | ||
ac8344c4 D |
265 | void default_restore_msi_irqs(struct pci_dev *dev) |
266 | { | |
267 | struct msi_desc *entry; | |
268 | ||
269 | list_for_each_entry(entry, &dev->msi_list, list) { | |
270 | default_restore_msi_irq(dev, entry->irq); | |
271 | } | |
272 | } | |
273 | ||
39431acb | 274 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 275 | { |
30da5524 BH |
276 | BUG_ON(entry->dev->current_state != PCI_D0); |
277 | ||
278 | if (entry->msi_attrib.is_msix) { | |
279 | void __iomem *base = entry->mask_base + | |
280 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
281 | ||
282 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
283 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
284 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
285 | } else { | |
286 | struct pci_dev *dev = entry->dev; | |
f5322169 | 287 | int pos = dev->msi_cap; |
30da5524 BH |
288 | u16 data; |
289 | ||
9925ad0c BH |
290 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
291 | &msg->address_lo); | |
30da5524 | 292 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
293 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
294 | &msg->address_hi); | |
2f221349 | 295 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
296 | } else { |
297 | msg->address_hi = 0; | |
2f221349 | 298 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
299 | } |
300 | msg->data = data; | |
301 | } | |
302 | } | |
303 | ||
304 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
305 | { | |
dced35ae | 306 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 307 | |
39431acb | 308 | __read_msi_msg(entry, msg); |
30da5524 BH |
309 | } |
310 | ||
39431acb | 311 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 312 | { |
30da5524 | 313 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
314 | * valid messages are not all-zeroes. */ |
315 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
316 | entry->msg.data)); | |
0366f8f7 | 317 | |
fcd097f3 | 318 | *msg = entry->msg; |
0366f8f7 | 319 | } |
1da177e4 | 320 | |
30da5524 | 321 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 322 | { |
dced35ae | 323 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 324 | |
39431acb | 325 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
326 | } |
327 | ||
39431acb | 328 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 329 | { |
fcd097f3 BH |
330 | if (entry->dev->current_state != PCI_D0) { |
331 | /* Don't touch the hardware now */ | |
332 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
333 | void __iomem *base; |
334 | base = entry->mask_base + | |
335 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
336 | ||
2c21fd4b HS |
337 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
338 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
339 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 340 | } else { |
0366f8f7 | 341 | struct pci_dev *dev = entry->dev; |
f5322169 | 342 | int pos = dev->msi_cap; |
1c8d7b0a MW |
343 | u16 msgctl; |
344 | ||
f84ecd28 | 345 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
346 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
347 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 348 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 349 | |
9925ad0c BH |
350 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
351 | msg->address_lo); | |
0366f8f7 | 352 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
353 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
354 | msg->address_hi); | |
2f221349 BH |
355 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
356 | msg->data); | |
0366f8f7 | 357 | } else { |
2f221349 BH |
358 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
359 | msg->data); | |
0366f8f7 | 360 | } |
1da177e4 | 361 | } |
392ee1e6 | 362 | entry->msg = *msg; |
1da177e4 | 363 | } |
0366f8f7 | 364 | |
3145e941 YL |
365 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
366 | { | |
dced35ae | 367 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 368 | |
39431acb | 369 | __write_msi_msg(entry, msg); |
3145e941 YL |
370 | } |
371 | ||
f56e4481 HS |
372 | static void free_msi_irqs(struct pci_dev *dev) |
373 | { | |
374 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
375 | struct attribute **msi_attrs; |
376 | struct device_attribute *dev_attr; | |
377 | int count = 0; | |
f56e4481 HS |
378 | |
379 | list_for_each_entry(entry, &dev->msi_list, list) { | |
380 | int i, nvec; | |
381 | if (!entry->irq) | |
382 | continue; | |
65f6ae66 AG |
383 | if (entry->nvec_used) |
384 | nvec = entry->nvec_used; | |
385 | else | |
386 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
387 | for (i = 0; i < nvec; i++) |
388 | BUG_ON(irq_has_action(entry->irq + i)); | |
389 | } | |
390 | ||
391 | arch_teardown_msi_irqs(dev); | |
392 | ||
393 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
394 | if (entry->msi_attrib.is_msix) { | |
395 | if (list_is_last(&entry->list, &dev->msi_list)) | |
396 | iounmap(entry->mask_base); | |
397 | } | |
424eb391 NH |
398 | |
399 | /* | |
400 | * Its possible that we get into this path | |
401 | * When populate_msi_sysfs fails, which means the entries | |
402 | * were not registered with sysfs. In that case don't | |
403 | * unregister them. | |
404 | */ | |
405 | if (entry->kobj.parent) { | |
406 | kobject_del(&entry->kobj); | |
407 | kobject_put(&entry->kobj); | |
408 | } | |
409 | ||
f56e4481 HS |
410 | list_del(&entry->list); |
411 | kfree(entry); | |
412 | } | |
1c51b50c GKH |
413 | |
414 | if (dev->msi_irq_groups) { | |
415 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
416 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
417 | list_for_each_entry(entry, &dev->msi_list, list) { | |
418 | dev_attr = container_of(msi_attrs[count], | |
419 | struct device_attribute, attr); | |
420 | kfree(dev_attr->attr.name); | |
421 | kfree(dev_attr); | |
422 | ++count; | |
423 | } | |
424 | kfree(msi_attrs); | |
425 | kfree(dev->msi_irq_groups[0]); | |
426 | kfree(dev->msi_irq_groups); | |
427 | dev->msi_irq_groups = NULL; | |
428 | } | |
f56e4481 | 429 | } |
c54c1879 | 430 | |
379f5327 | 431 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 432 | { |
379f5327 MW |
433 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
434 | if (!desc) | |
1da177e4 LT |
435 | return NULL; |
436 | ||
379f5327 MW |
437 | INIT_LIST_HEAD(&desc->list); |
438 | desc->dev = dev; | |
1da177e4 | 439 | |
379f5327 | 440 | return desc; |
1da177e4 LT |
441 | } |
442 | ||
ba698ad4 DM |
443 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
444 | { | |
445 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
446 | pci_intx(dev, enable); | |
447 | } | |
448 | ||
8fed4b65 | 449 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 450 | { |
41017f0c | 451 | u16 control; |
392ee1e6 | 452 | struct msi_desc *entry; |
41017f0c | 453 | |
b1cbf4e4 EB |
454 | if (!dev->msi_enabled) |
455 | return; | |
456 | ||
dced35ae | 457 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 458 | |
ba698ad4 | 459 | pci_intx_for_msi(dev, 0); |
e375b561 | 460 | msi_set_enable(dev, 0); |
ac8344c4 | 461 | arch_restore_msi_irqs(dev); |
392ee1e6 | 462 | |
f5322169 | 463 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
f2440d9a | 464 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 465 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 466 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 467 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
468 | } |
469 | ||
470 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 471 | { |
41017f0c | 472 | struct msi_desc *entry; |
392ee1e6 | 473 | u16 control; |
41017f0c | 474 | |
ded86d8d EB |
475 | if (!dev->msix_enabled) |
476 | return; | |
f598282f | 477 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 478 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f5322169 | 479 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
ded86d8d | 480 | |
41017f0c | 481 | /* route the table */ |
ba698ad4 | 482 | pci_intx_for_msi(dev, 0); |
f598282f | 483 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 484 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 485 | |
ac8344c4 | 486 | arch_restore_msi_irqs(dev); |
4aa9bc95 | 487 | list_for_each_entry(entry, &dev->msi_list, list) { |
f2440d9a | 488 | msix_mask_irq(entry, entry->masked); |
41017f0c | 489 | } |
41017f0c | 490 | |
392ee1e6 | 491 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 492 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 493 | } |
8fed4b65 ME |
494 | |
495 | void pci_restore_msi_state(struct pci_dev *dev) | |
496 | { | |
497 | __pci_restore_msi_state(dev); | |
498 | __pci_restore_msix_state(dev); | |
499 | } | |
94688cf2 | 500 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 501 | |
1c51b50c | 502 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
503 | char *buf) |
504 | { | |
1c51b50c GKH |
505 | struct pci_dev *pdev = to_pci_dev(dev); |
506 | struct msi_desc *entry; | |
507 | unsigned long irq; | |
508 | int retval; | |
da8d1c8b | 509 | |
1c51b50c GKH |
510 | retval = kstrtoul(attr->attr.name, 10, &irq); |
511 | if (retval) | |
512 | return retval; | |
da8d1c8b | 513 | |
1c51b50c GKH |
514 | list_for_each_entry(entry, &pdev->msi_list, list) { |
515 | if (entry->irq == irq) { | |
516 | return sprintf(buf, "%s\n", | |
517 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
518 | } | |
519 | } | |
520 | return -ENODEV; | |
da8d1c8b NH |
521 | } |
522 | ||
da8d1c8b NH |
523 | static int populate_msi_sysfs(struct pci_dev *pdev) |
524 | { | |
1c51b50c GKH |
525 | struct attribute **msi_attrs; |
526 | struct attribute *msi_attr; | |
527 | struct device_attribute *msi_dev_attr; | |
528 | struct attribute_group *msi_irq_group; | |
529 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 530 | struct msi_desc *entry; |
1c51b50c GKH |
531 | int ret = -ENOMEM; |
532 | int num_msi = 0; | |
da8d1c8b NH |
533 | int count = 0; |
534 | ||
1c51b50c GKH |
535 | /* Determine how many msi entries we have */ |
536 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
537 | ++num_msi; | |
538 | } | |
539 | if (!num_msi) | |
540 | return 0; | |
da8d1c8b | 541 | |
1c51b50c GKH |
542 | /* Dynamically create the MSI attributes for the PCI device */ |
543 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
544 | if (!msi_attrs) | |
545 | return -ENOMEM; | |
da8d1c8b | 546 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 547 | char *name = kmalloc(20, GFP_KERNEL); |
86bb4f69 GKH |
548 | if (!name) |
549 | goto error_attrs; | |
550 | ||
1c51b50c | 551 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
86bb4f69 GKH |
552 | if (!msi_dev_attr) { |
553 | kfree(name); | |
1c51b50c | 554 | goto error_attrs; |
86bb4f69 GKH |
555 | } |
556 | ||
1c51b50c GKH |
557 | sprintf(name, "%d", entry->irq); |
558 | sysfs_attr_init(&msi_dev_attr->attr); | |
559 | msi_dev_attr->attr.name = name; | |
560 | msi_dev_attr->attr.mode = S_IRUGO; | |
561 | msi_dev_attr->show = msi_mode_show; | |
562 | msi_attrs[count] = &msi_dev_attr->attr; | |
563 | ++count; | |
da8d1c8b NH |
564 | } |
565 | ||
1c51b50c GKH |
566 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
567 | if (!msi_irq_group) | |
568 | goto error_attrs; | |
569 | msi_irq_group->name = "msi_irqs"; | |
570 | msi_irq_group->attrs = msi_attrs; | |
571 | ||
572 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
573 | if (!msi_irq_groups) | |
574 | goto error_irq_group; | |
575 | msi_irq_groups[0] = msi_irq_group; | |
576 | ||
577 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
578 | if (ret) | |
579 | goto error_irq_groups; | |
580 | pdev->msi_irq_groups = msi_irq_groups; | |
581 | ||
da8d1c8b NH |
582 | return 0; |
583 | ||
1c51b50c GKH |
584 | error_irq_groups: |
585 | kfree(msi_irq_groups); | |
586 | error_irq_group: | |
587 | kfree(msi_irq_group); | |
588 | error_attrs: | |
589 | count = 0; | |
590 | msi_attr = msi_attrs[count]; | |
591 | while (msi_attr) { | |
592 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
593 | kfree(msi_attr->name); | |
594 | kfree(msi_dev_attr); | |
595 | ++count; | |
596 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 597 | } |
29237756 | 598 | kfree(msi_attrs); |
da8d1c8b NH |
599 | return ret; |
600 | } | |
601 | ||
1da177e4 LT |
602 | /** |
603 | * msi_capability_init - configure device's MSI capability structure | |
604 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 605 | * @nvec: number of interrupts to allocate |
1da177e4 | 606 | * |
1c8d7b0a MW |
607 | * Setup the MSI capability structure of the device with the requested |
608 | * number of interrupts. A return value of zero indicates the successful | |
609 | * setup of an entry with the new MSI irq. A negative return value indicates | |
610 | * an error, and a positive return value indicates the number of interrupts | |
611 | * which could have been allocated. | |
612 | */ | |
613 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
614 | { |
615 | struct msi_desc *entry; | |
f465136d | 616 | int ret; |
1da177e4 | 617 | u16 control; |
f2440d9a | 618 | unsigned mask; |
1da177e4 | 619 | |
e375b561 | 620 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 621 | |
f84ecd28 | 622 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
1da177e4 | 623 | /* MSI Entry Initialization */ |
379f5327 | 624 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
625 | if (!entry) |
626 | return -ENOMEM; | |
1ce03373 | 627 | |
500559a9 | 628 | entry->msi_attrib.is_msix = 0; |
4987ce82 | 629 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
500559a9 | 630 | entry->msi_attrib.entry_nr = 0; |
4987ce82 | 631 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
500559a9 | 632 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
f465136d | 633 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 634 | |
e5f66eaf DC |
635 | if (control & PCI_MSI_FLAGS_64BIT) |
636 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
637 | else | |
638 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
f2440d9a MW |
639 | /* All MSIs are unmasked by default, Mask them all */ |
640 | if (entry->msi_attrib.maskbit) | |
641 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
642 | mask = msi_capable_mask(control); | |
643 | msi_mask_irq(entry, mask, mask); | |
644 | ||
0dd11f9b | 645 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 646 | |
1da177e4 | 647 | /* Configure MSI capability structure */ |
1c8d7b0a | 648 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 649 | if (ret) { |
7ba1930d | 650 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 651 | free_msi_irqs(dev); |
7fe3730d | 652 | return ret; |
fd58e55f | 653 | } |
f7feaca7 | 654 | |
da8d1c8b NH |
655 | ret = populate_msi_sysfs(dev); |
656 | if (ret) { | |
657 | msi_mask_irq(entry, mask, ~mask); | |
658 | free_msi_irqs(dev); | |
659 | return ret; | |
660 | } | |
661 | ||
1da177e4 | 662 | /* Set MSI enabled bits */ |
ba698ad4 | 663 | pci_intx_for_msi(dev, 0); |
e375b561 | 664 | msi_set_enable(dev, 1); |
b1cbf4e4 | 665 | dev->msi_enabled = 1; |
1da177e4 | 666 | |
7fe3730d | 667 | dev->irq = entry->irq; |
1da177e4 LT |
668 | return 0; |
669 | } | |
670 | ||
520fe9dc | 671 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 672 | { |
4302e0fb | 673 | resource_size_t phys_addr; |
5a05a9d8 HS |
674 | u32 table_offset; |
675 | u8 bir; | |
676 | ||
909094c6 BH |
677 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
678 | &table_offset); | |
4d18760c BH |
679 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
680 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
681 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
682 | ||
683 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
684 | } | |
685 | ||
520fe9dc GS |
686 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
687 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
688 | { |
689 | struct msi_desc *entry; | |
690 | int i; | |
691 | ||
692 | for (i = 0; i < nvec; i++) { | |
693 | entry = alloc_msi_entry(dev); | |
694 | if (!entry) { | |
695 | if (!i) | |
696 | iounmap(base); | |
697 | else | |
698 | free_msi_irqs(dev); | |
699 | /* No enough memory. Don't try again */ | |
700 | return -ENOMEM; | |
701 | } | |
702 | ||
703 | entry->msi_attrib.is_msix = 1; | |
704 | entry->msi_attrib.is_64 = 1; | |
705 | entry->msi_attrib.entry_nr = entries[i].entry; | |
706 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 707 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
708 | entry->mask_base = base; |
709 | ||
710 | list_add_tail(&entry->list, &dev->msi_list); | |
711 | } | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
75cb3426 | 716 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 717 | struct msix_entry *entries) |
75cb3426 HS |
718 | { |
719 | struct msi_desc *entry; | |
720 | int i = 0; | |
721 | ||
722 | list_for_each_entry(entry, &dev->msi_list, list) { | |
723 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
724 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
725 | ||
726 | entries[i].vector = entry->irq; | |
dced35ae | 727 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
728 | entry->masked = readl(entry->mask_base + offset); |
729 | msix_mask_irq(entry, 1); | |
730 | i++; | |
731 | } | |
732 | } | |
733 | ||
1da177e4 LT |
734 | /** |
735 | * msix_capability_init - configure device's MSI-X capability | |
736 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
737 | * @entries: pointer to an array of struct msix_entry entries |
738 | * @nvec: number of @entries | |
1da177e4 | 739 | * |
eaae4b3a | 740 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
741 | * single MSI-X irq. A return of zero indicates the successful setup of |
742 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
743 | **/ |
744 | static int msix_capability_init(struct pci_dev *dev, | |
745 | struct msix_entry *entries, int nvec) | |
746 | { | |
520fe9dc | 747 | int ret; |
5a05a9d8 | 748 | u16 control; |
1da177e4 LT |
749 | void __iomem *base; |
750 | ||
520fe9dc | 751 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
f598282f MW |
752 | |
753 | /* Ensure MSI-X is disabled while it is set up */ | |
754 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 755 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 756 | |
1da177e4 | 757 | /* Request & Map MSI-X table region */ |
527eee29 | 758 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 759 | if (!base) |
1da177e4 LT |
760 | return -ENOMEM; |
761 | ||
520fe9dc | 762 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
763 | if (ret) |
764 | return ret; | |
9c831334 ME |
765 | |
766 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 | 767 | if (ret) |
2adc7907 | 768 | goto out_avail; |
9c831334 | 769 | |
f598282f MW |
770 | /* |
771 | * Some devices require MSI-X to be enabled before we can touch the | |
772 | * MSI-X registers. We need to mask all the vectors to prevent | |
773 | * interrupts coming in before they're fully set up. | |
774 | */ | |
775 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 776 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 777 | |
75cb3426 | 778 | msix_program_entries(dev, entries); |
f598282f | 779 | |
da8d1c8b | 780 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
781 | if (ret) |
782 | goto out_free; | |
da8d1c8b | 783 | |
f598282f | 784 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 785 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 786 | dev->msix_enabled = 1; |
1da177e4 | 787 | |
f598282f | 788 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
520fe9dc | 789 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
8d181018 | 790 | |
1da177e4 | 791 | return 0; |
583871d4 | 792 | |
2adc7907 | 793 | out_avail: |
583871d4 HS |
794 | if (ret < 0) { |
795 | /* | |
796 | * If we had some success, report the number of irqs | |
797 | * we succeeded in setting up. | |
798 | */ | |
d9d7070e | 799 | struct msi_desc *entry; |
583871d4 HS |
800 | int avail = 0; |
801 | ||
802 | list_for_each_entry(entry, &dev->msi_list, list) { | |
803 | if (entry->irq != 0) | |
804 | avail++; | |
805 | } | |
806 | if (avail != 0) | |
807 | ret = avail; | |
808 | } | |
809 | ||
2adc7907 | 810 | out_free: |
583871d4 HS |
811 | free_msi_irqs(dev); |
812 | ||
813 | return ret; | |
1da177e4 LT |
814 | } |
815 | ||
24334a12 | 816 | /** |
17bbc12a | 817 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 818 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 819 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 820 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 821 | * |
f7625980 | 822 | * Look at global flags, the device itself, and its parent buses |
17bbc12a ME |
823 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
824 | * supported return 0, else return an error code. | |
24334a12 | 825 | **/ |
500559a9 | 826 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
827 | { |
828 | struct pci_bus *bus; | |
c9953a73 | 829 | int ret; |
24334a12 | 830 | |
0306ebfa | 831 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
832 | if (!pci_msi_enable || !dev || dev->no_msi) |
833 | return -EINVAL; | |
834 | ||
314e77b3 ME |
835 | /* |
836 | * You can't ask to have 0 or less MSIs configured. | |
837 | * a) it's stupid .. | |
838 | * b) the list manipulation code assumes nvec >= 1. | |
839 | */ | |
840 | if (nvec < 1) | |
841 | return -ERANGE; | |
842 | ||
500559a9 HS |
843 | /* |
844 | * Any bridge which does NOT route MSI transactions from its | |
845 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
846 | * the secondary pci_bus. |
847 | * We expect only arch-specific PCI host bus controller driver | |
848 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
849 | */ | |
24334a12 BG |
850 | for (bus = dev->bus; bus; bus = bus->parent) |
851 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
852 | return -EINVAL; | |
853 | ||
c9953a73 ME |
854 | ret = arch_msi_check_device(dev, nvec, type); |
855 | if (ret) | |
856 | return ret; | |
857 | ||
24334a12 BG |
858 | return 0; |
859 | } | |
860 | ||
d1ac1d26 AG |
861 | /** |
862 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
863 | * @dev: device to report about | |
864 | * | |
865 | * This function returns the number of MSI vectors a device requested via | |
866 | * Multiple Message Capable register. It returns a negative errno if the | |
867 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
868 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
869 | * MSI specification. | |
870 | **/ | |
871 | int pci_msi_vec_count(struct pci_dev *dev) | |
872 | { | |
873 | int ret; | |
874 | u16 msgctl; | |
875 | ||
876 | if (!dev->msi_cap) | |
877 | return -EINVAL; | |
878 | ||
879 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
880 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
881 | ||
882 | return ret; | |
883 | } | |
884 | EXPORT_SYMBOL(pci_msi_vec_count); | |
885 | ||
1da177e4 | 886 | /** |
1c8d7b0a MW |
887 | * pci_enable_msi_block - configure device's MSI capability structure |
888 | * @dev: device to configure | |
889 | * @nvec: number of interrupts to configure | |
1da177e4 | 890 | * |
1c8d7b0a MW |
891 | * Allocate IRQs for a device with the MSI capability. |
892 | * This function returns a negative errno if an error occurs. If it | |
893 | * is unable to allocate the number of interrupts requested, it returns | |
894 | * the number of interrupts it might be able to allocate. If it successfully | |
895 | * allocates at least the number of interrupts requested, it returns 0 and | |
896 | * updates the @dev's irq member to the lowest new interrupt number; the | |
897 | * other interrupt numbers allocated to this device are consecutive. | |
898 | */ | |
52179dc9 | 899 | int pci_enable_msi_block(struct pci_dev *dev, int nvec) |
1da177e4 | 900 | { |
f465136d | 901 | int status, maxvec; |
1c8d7b0a | 902 | |
d1ac1d26 | 903 | if (dev->current_state != PCI_D0) |
1c8d7b0a | 904 | return -EINVAL; |
f465136d | 905 | |
d1ac1d26 AG |
906 | maxvec = pci_msi_vec_count(dev); |
907 | if (maxvec < 0) | |
908 | return maxvec; | |
1c8d7b0a MW |
909 | if (nvec > maxvec) |
910 | return maxvec; | |
1da177e4 | 911 | |
1c8d7b0a | 912 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
913 | if (status) |
914 | return status; | |
1da177e4 | 915 | |
ded86d8d | 916 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 917 | |
1c8d7b0a | 918 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 919 | if (dev->msix_enabled) { |
80ccba11 BH |
920 | dev_info(&dev->dev, "can't enable MSI " |
921 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 922 | return -EINVAL; |
1da177e4 | 923 | } |
1c8d7b0a MW |
924 | |
925 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
926 | return status; |
927 | } | |
1c8d7b0a | 928 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 929 | |
f2440d9a | 930 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 931 | { |
f2440d9a MW |
932 | struct msi_desc *desc; |
933 | u32 mask; | |
934 | u16 ctrl; | |
1da177e4 | 935 | |
128bc5fc | 936 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
937 | return; |
938 | ||
110828c9 MW |
939 | BUG_ON(list_empty(&dev->msi_list)); |
940 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 941 | |
e375b561 | 942 | msi_set_enable(dev, 0); |
ba698ad4 | 943 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 944 | dev->msi_enabled = 0; |
7bd007e4 | 945 | |
12abb8ba | 946 | /* Return the device with MSI unmasked as initial states */ |
f5322169 | 947 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 948 | mask = msi_capable_mask(ctrl); |
12abb8ba | 949 | /* Keep cached state to be restored */ |
0e4ccb15 | 950 | arch_msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
951 | |
952 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 953 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 954 | } |
24d27553 | 955 | |
500559a9 | 956 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 957 | { |
d52877c7 YL |
958 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
959 | return; | |
960 | ||
961 | pci_msi_shutdown(dev); | |
f56e4481 | 962 | free_msi_irqs(dev); |
1da177e4 | 963 | } |
4cc086fa | 964 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 965 | |
a52e2e35 | 966 | /** |
ff1aa430 | 967 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 968 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
969 | * This function returns the number of device's MSI-X table entries and |
970 | * therefore the number of MSI-X vectors device is capable of sending. | |
971 | * It returns a negative errno if the device is not capable of sending MSI-X | |
972 | * interrupts. | |
973 | **/ | |
974 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 975 | { |
a52e2e35 RW |
976 | u16 control; |
977 | ||
520fe9dc | 978 | if (!dev->msix_cap) |
ff1aa430 | 979 | return -EINVAL; |
a52e2e35 | 980 | |
f84ecd28 | 981 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 982 | return msix_table_size(control); |
a52e2e35 | 983 | } |
ff1aa430 | 984 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 985 | |
1da177e4 LT |
986 | /** |
987 | * pci_enable_msix - configure device's MSI-X capability structure | |
988 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 989 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 990 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
991 | * |
992 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 993 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
994 | * MSI-X mode enabled on its hardware device function. A return of zero |
995 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 996 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 997 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
998 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
999 | * re-send its request. | |
1da177e4 | 1000 | **/ |
500559a9 | 1001 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 1002 | { |
a52e2e35 | 1003 | int status, nr_entries; |
ded86d8d | 1004 | int i, j; |
1da177e4 | 1005 | |
869a1615 | 1006 | if (!entries || !dev->msix_cap || dev->current_state != PCI_D0) |
500559a9 | 1007 | return -EINVAL; |
1da177e4 | 1008 | |
c9953a73 ME |
1009 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
1010 | if (status) | |
1011 | return status; | |
1012 | ||
ff1aa430 AG |
1013 | nr_entries = pci_msix_vec_count(dev); |
1014 | if (nr_entries < 0) | |
1015 | return nr_entries; | |
1da177e4 | 1016 | if (nvec > nr_entries) |
57fbf52c | 1017 | return nr_entries; |
1da177e4 LT |
1018 | |
1019 | /* Check for any invalid entries */ | |
1020 | for (i = 0; i < nvec; i++) { | |
1021 | if (entries[i].entry >= nr_entries) | |
1022 | return -EINVAL; /* invalid entry */ | |
1023 | for (j = i + 1; j < nvec; j++) { | |
1024 | if (entries[i].entry == entries[j].entry) | |
1025 | return -EINVAL; /* duplicate entry */ | |
1026 | } | |
1027 | } | |
ded86d8d | 1028 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 1029 | |
1ce03373 | 1030 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 1031 | if (dev->msi_enabled) { |
80ccba11 BH |
1032 | dev_info(&dev->dev, "can't enable MSI-X " |
1033 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
1034 | return -EINVAL; |
1035 | } | |
1da177e4 | 1036 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
1037 | return status; |
1038 | } | |
4cc086fa | 1039 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 1040 | |
500559a9 | 1041 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 1042 | { |
12abb8ba HS |
1043 | struct msi_desc *entry; |
1044 | ||
128bc5fc | 1045 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1046 | return; |
1047 | ||
12abb8ba HS |
1048 | /* Return the device with MSI-X masked as initial states */ |
1049 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1050 | /* Keep cached states to be restored */ | |
0e4ccb15 | 1051 | arch_msix_mask_irq(entry, 1); |
12abb8ba HS |
1052 | } |
1053 | ||
b1cbf4e4 | 1054 | msix_set_enable(dev, 0); |
ba698ad4 | 1055 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1056 | dev->msix_enabled = 0; |
d52877c7 | 1057 | } |
c901851f | 1058 | |
500559a9 | 1059 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1060 | { |
1061 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1062 | return; | |
1063 | ||
1064 | pci_msix_shutdown(dev); | |
f56e4481 | 1065 | free_msi_irqs(dev); |
1da177e4 | 1066 | } |
4cc086fa | 1067 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1068 | |
1069 | /** | |
1ce03373 | 1070 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1071 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1072 | * | |
eaae4b3a | 1073 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1074 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1075 | * allocated for this device function, are reclaimed to unused state, |
1076 | * which may be used later on. | |
1077 | **/ | |
500559a9 | 1078 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1079 | { |
1da177e4 | 1080 | if (!pci_msi_enable || !dev) |
500559a9 | 1081 | return; |
1da177e4 | 1082 | |
f56e4481 HS |
1083 | if (dev->msi_enabled || dev->msix_enabled) |
1084 | free_msi_irqs(dev); | |
1da177e4 LT |
1085 | } |
1086 | ||
309e57df MW |
1087 | void pci_no_msi(void) |
1088 | { | |
1089 | pci_msi_enable = 0; | |
1090 | } | |
c9953a73 | 1091 | |
07ae95f9 AP |
1092 | /** |
1093 | * pci_msi_enabled - is MSI enabled? | |
1094 | * | |
1095 | * Returns true if MSI has not been disabled by the command-line option | |
1096 | * pci=nomsi. | |
1097 | **/ | |
1098 | int pci_msi_enabled(void) | |
d389fec6 | 1099 | { |
07ae95f9 | 1100 | return pci_msi_enable; |
d389fec6 | 1101 | } |
07ae95f9 | 1102 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1103 | |
07ae95f9 | 1104 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1105 | { |
07ae95f9 | 1106 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1107 | |
1108 | /* Disable the msi hardware to avoid screaming interrupts | |
1109 | * during boot. This is the power on reset default so | |
1110 | * usually this should be a noop. | |
1111 | */ | |
e375b561 GS |
1112 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1113 | if (dev->msi_cap) | |
1114 | msi_set_enable(dev, 0); | |
1115 | ||
1116 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1117 | if (dev->msix_cap) | |
1118 | msix_set_enable(dev, 0); | |
d389fec6 | 1119 | } |
302a2523 AG |
1120 | |
1121 | /** | |
1122 | * pci_enable_msi_range - configure device's MSI capability structure | |
1123 | * @dev: device to configure | |
1124 | * @minvec: minimal number of interrupts to configure | |
1125 | * @maxvec: maximum number of interrupts to configure | |
1126 | * | |
1127 | * This function tries to allocate a maximum possible number of interrupts in a | |
1128 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1129 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1130 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1131 | * the other interrupt numbers allocated to this device are consecutive. | |
1132 | **/ | |
1133 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1134 | { | |
1135 | int nvec = maxvec; | |
1136 | int rc; | |
1137 | ||
1138 | if (maxvec < minvec) | |
1139 | return -ERANGE; | |
1140 | ||
1141 | do { | |
1142 | rc = pci_enable_msi_block(dev, nvec); | |
1143 | if (rc < 0) { | |
1144 | return rc; | |
1145 | } else if (rc > 0) { | |
1146 | if (rc < minvec) | |
1147 | return -ENOSPC; | |
1148 | nvec = rc; | |
1149 | } | |
1150 | } while (rc); | |
1151 | ||
1152 | return nvec; | |
1153 | } | |
1154 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1155 | ||
1156 | /** | |
1157 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1158 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1159 | * @entries: pointer to an array of MSI-X entries | |
1160 | * @minvec: minimum number of MSI-X irqs requested | |
1161 | * @maxvec: maximum number of MSI-X irqs requested | |
1162 | * | |
1163 | * Setup the MSI-X capability structure of device function with a maximum | |
1164 | * possible number of interrupts in the range between @minvec and @maxvec | |
1165 | * upon its software driver call to request for MSI-X mode enabled on its | |
1166 | * hardware device function. It returns a negative errno if an error occurs. | |
1167 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1168 | * indicates the successful configuration of MSI-X capability structure | |
1169 | * with new allocated MSI-X interrupts. | |
1170 | **/ | |
1171 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1172 | int minvec, int maxvec) | |
1173 | { | |
1174 | int nvec = maxvec; | |
1175 | int rc; | |
1176 | ||
1177 | if (maxvec < minvec) | |
1178 | return -ERANGE; | |
1179 | ||
1180 | do { | |
1181 | rc = pci_enable_msix(dev, entries, nvec); | |
1182 | if (rc < 0) { | |
1183 | return rc; | |
1184 | } else if (rc > 0) { | |
1185 | if (rc < minvec) | |
1186 | return -ENOSPC; | |
1187 | nvec = rc; | |
1188 | } | |
1189 | } while (rc); | |
1190 | ||
1191 | return nvec; | |
1192 | } | |
1193 | EXPORT_SYMBOL(pci_enable_msix_range); |