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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
527eee29 BH |
28 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
29 | ||
30 | ||
6a9e7f20 AB |
31 | /* Arch hooks */ |
32 | ||
6a4324eb | 33 | #if defined(CONFIG_GENERIC_HARDIRQS) |
4287d824 TP |
34 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
35 | { | |
0cbdcfcf TR |
36 | struct msi_chip *chip = dev->bus->msi; |
37 | int err; | |
38 | ||
39 | if (!chip || !chip->setup_irq) | |
40 | return -EINVAL; | |
41 | ||
42 | err = chip->setup_irq(chip, dev, desc); | |
43 | if (err < 0) | |
44 | return err; | |
45 | ||
46 | irq_set_chip_data(desc->irq, chip); | |
47 | ||
48 | return 0; | |
4287d824 TP |
49 | } |
50 | ||
51 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 52 | { |
0cbdcfcf TR |
53 | struct msi_chip *chip = irq_get_chip_data(irq); |
54 | ||
55 | if (!chip || !chip->teardown_irq) | |
56 | return; | |
57 | ||
58 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
59 | } |
60 | ||
4287d824 TP |
61 | int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) |
62 | { | |
0cbdcfcf TR |
63 | struct msi_chip *chip = dev->bus->msi; |
64 | ||
65 | if (!chip || !chip->check_device) | |
66 | return 0; | |
67 | ||
68 | return chip->check_device(chip, dev, nvec, type); | |
4287d824 | 69 | } |
6a4324eb TP |
70 | #else |
71 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) | |
72 | { | |
73 | return -ENOSYS; | |
74 | } | |
75 | ||
76 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
77 | { | |
78 | } | |
79 | ||
80 | int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
81 | { | |
82 | return 0; | |
83 | } | |
84 | #endif /* CONFIG_GENERIC_HARDIRQS */ | |
1525bf0d | 85 | |
4287d824 | 86 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
87 | { |
88 | struct msi_desc *entry; | |
89 | int ret; | |
90 | ||
1c8d7b0a MW |
91 | /* |
92 | * If an architecture wants to support multiple MSI, it needs to | |
93 | * override arch_setup_msi_irqs() | |
94 | */ | |
95 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
96 | return 1; | |
97 | ||
6a9e7f20 AB |
98 | list_for_each_entry(entry, &dev->msi_list, list) { |
99 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 100 | if (ret < 0) |
6a9e7f20 | 101 | return ret; |
b5fbf533 ME |
102 | if (ret > 0) |
103 | return -ENOSPC; | |
6a9e7f20 AB |
104 | } |
105 | ||
106 | return 0; | |
107 | } | |
1525bf0d | 108 | |
4287d824 TP |
109 | /* |
110 | * We have a default implementation available as a separate non-weak | |
111 | * function, as it is used by the Xen x86 PCI code | |
112 | */ | |
1525bf0d | 113 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
114 | { |
115 | struct msi_desc *entry; | |
116 | ||
117 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
118 | int i, nvec; |
119 | if (entry->irq == 0) | |
120 | continue; | |
65f6ae66 AG |
121 | if (entry->nvec_used) |
122 | nvec = entry->nvec_used; | |
123 | else | |
124 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
125 | for (i = 0; i < nvec; i++) |
126 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
127 | } |
128 | } | |
129 | ||
4287d824 TP |
130 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
131 | { | |
132 | return default_teardown_msi_irqs(dev); | |
133 | } | |
76ccc297 | 134 | |
76ccc297 KRW |
135 | void default_restore_msi_irqs(struct pci_dev *dev, int irq) |
136 | { | |
137 | struct msi_desc *entry; | |
138 | ||
139 | entry = NULL; | |
140 | if (dev->msix_enabled) { | |
141 | list_for_each_entry(entry, &dev->msi_list, list) { | |
142 | if (irq == entry->irq) | |
143 | break; | |
144 | } | |
145 | } else if (dev->msi_enabled) { | |
146 | entry = irq_get_msi_desc(irq); | |
147 | } | |
148 | ||
149 | if (entry) | |
150 | write_msi_msg(irq, &entry->msg); | |
151 | } | |
4287d824 TP |
152 | |
153 | void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq) | |
154 | { | |
155 | return default_restore_msi_irqs(dev, irq); | |
156 | } | |
76ccc297 | 157 | |
e375b561 | 158 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 159 | { |
b1cbf4e4 EB |
160 | u16 control; |
161 | ||
e375b561 | 162 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
163 | control &= ~PCI_MSI_FLAGS_ENABLE; |
164 | if (enable) | |
165 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 166 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
167 | } |
168 | ||
b1cbf4e4 EB |
169 | static void msix_set_enable(struct pci_dev *dev, int enable) |
170 | { | |
b1cbf4e4 EB |
171 | u16 control; |
172 | ||
e375b561 GS |
173 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
174 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
175 | if (enable) | |
176 | control |= PCI_MSIX_FLAGS_ENABLE; | |
177 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
178 | } |
179 | ||
bffac3c5 MW |
180 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
181 | { | |
0b49ec37 MW |
182 | /* Don't shift by >= width of type */ |
183 | if (x >= 5) | |
184 | return 0xffffffff; | |
185 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
186 | } |
187 | ||
f2440d9a | 188 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 189 | { |
f2440d9a MW |
190 | return msi_mask((control >> 1) & 7); |
191 | } | |
988cbb15 | 192 | |
f2440d9a MW |
193 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
194 | { | |
195 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
196 | } |
197 | ||
ce6fce42 MW |
198 | /* |
199 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
200 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
201 | * reliably as devices without an INTx disable bit will then generate a | |
202 | * level IRQ which will never be cleared. | |
ce6fce42 | 203 | */ |
12abb8ba | 204 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 205 | { |
f2440d9a | 206 | u32 mask_bits = desc->masked; |
1da177e4 | 207 | |
f2440d9a | 208 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 209 | return 0; |
f2440d9a MW |
210 | |
211 | mask_bits &= ~mask; | |
212 | mask_bits |= flag; | |
213 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
214 | |
215 | return mask_bits; | |
216 | } | |
217 | ||
218 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
219 | { | |
220 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
221 | } |
222 | ||
223 | /* | |
224 | * This internal function does not flush PCI writes to the device. | |
225 | * All users must ensure that they read from the device before either | |
226 | * assuming that the device state is up to date, or returning out of this | |
227 | * file. This saves a few milliseconds when initialising devices with lots | |
228 | * of MSI-X interrupts. | |
229 | */ | |
12abb8ba | 230 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
231 | { |
232 | u32 mask_bits = desc->masked; | |
233 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 234 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
235 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
236 | if (flag) | |
237 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 238 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
239 | |
240 | return mask_bits; | |
241 | } | |
242 | ||
243 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
244 | { | |
245 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 246 | } |
24d27553 | 247 | |
9a4da8a5 JG |
248 | #ifdef CONFIG_GENERIC_HARDIRQS |
249 | ||
1c9db525 | 250 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 251 | { |
1c9db525 | 252 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 253 | |
f2440d9a MW |
254 | if (desc->msi_attrib.is_msix) { |
255 | msix_mask_irq(desc, flag); | |
256 | readl(desc->mask_base); /* Flush write to device */ | |
257 | } else { | |
1c9db525 | 258 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 259 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 260 | } |
f2440d9a MW |
261 | } |
262 | ||
1c9db525 | 263 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 264 | { |
1c9db525 | 265 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
266 | } |
267 | ||
1c9db525 | 268 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 269 | { |
1c9db525 | 270 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
271 | } |
272 | ||
9a4da8a5 JG |
273 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
274 | ||
39431acb | 275 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 276 | { |
30da5524 BH |
277 | BUG_ON(entry->dev->current_state != PCI_D0); |
278 | ||
279 | if (entry->msi_attrib.is_msix) { | |
280 | void __iomem *base = entry->mask_base + | |
281 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
282 | ||
283 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
284 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
285 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
286 | } else { | |
287 | struct pci_dev *dev = entry->dev; | |
f5322169 | 288 | int pos = dev->msi_cap; |
30da5524 BH |
289 | u16 data; |
290 | ||
9925ad0c BH |
291 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
292 | &msg->address_lo); | |
30da5524 | 293 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
294 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
295 | &msg->address_hi); | |
2f221349 | 296 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
297 | } else { |
298 | msg->address_hi = 0; | |
2f221349 | 299 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
300 | } |
301 | msg->data = data; | |
302 | } | |
303 | } | |
304 | ||
305 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
306 | { | |
dced35ae | 307 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 308 | |
39431acb | 309 | __read_msi_msg(entry, msg); |
30da5524 BH |
310 | } |
311 | ||
39431acb | 312 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 313 | { |
30da5524 | 314 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
315 | * valid messages are not all-zeroes. */ |
316 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
317 | entry->msg.data)); | |
0366f8f7 | 318 | |
fcd097f3 | 319 | *msg = entry->msg; |
0366f8f7 | 320 | } |
1da177e4 | 321 | |
30da5524 | 322 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 323 | { |
dced35ae | 324 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 325 | |
39431acb | 326 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
327 | } |
328 | ||
39431acb | 329 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 330 | { |
fcd097f3 BH |
331 | if (entry->dev->current_state != PCI_D0) { |
332 | /* Don't touch the hardware now */ | |
333 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
334 | void __iomem *base; |
335 | base = entry->mask_base + | |
336 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
337 | ||
2c21fd4b HS |
338 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
339 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
340 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 341 | } else { |
0366f8f7 | 342 | struct pci_dev *dev = entry->dev; |
f5322169 | 343 | int pos = dev->msi_cap; |
1c8d7b0a MW |
344 | u16 msgctl; |
345 | ||
f84ecd28 | 346 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
347 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
348 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 349 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 350 | |
9925ad0c BH |
351 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
352 | msg->address_lo); | |
0366f8f7 | 353 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
354 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
355 | msg->address_hi); | |
2f221349 BH |
356 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
357 | msg->data); | |
0366f8f7 | 358 | } else { |
2f221349 BH |
359 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
360 | msg->data); | |
0366f8f7 | 361 | } |
1da177e4 | 362 | } |
392ee1e6 | 363 | entry->msg = *msg; |
1da177e4 | 364 | } |
0366f8f7 | 365 | |
3145e941 YL |
366 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
367 | { | |
dced35ae | 368 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 369 | |
39431acb | 370 | __write_msi_msg(entry, msg); |
3145e941 YL |
371 | } |
372 | ||
f56e4481 HS |
373 | static void free_msi_irqs(struct pci_dev *dev) |
374 | { | |
375 | struct msi_desc *entry, *tmp; | |
376 | ||
377 | list_for_each_entry(entry, &dev->msi_list, list) { | |
378 | int i, nvec; | |
379 | if (!entry->irq) | |
380 | continue; | |
65f6ae66 AG |
381 | if (entry->nvec_used) |
382 | nvec = entry->nvec_used; | |
383 | else | |
384 | nvec = 1 << entry->msi_attrib.multiple; | |
9a4da8a5 | 385 | #ifdef CONFIG_GENERIC_HARDIRQS |
f56e4481 HS |
386 | for (i = 0; i < nvec; i++) |
387 | BUG_ON(irq_has_action(entry->irq + i)); | |
9a4da8a5 | 388 | #endif |
f56e4481 HS |
389 | } |
390 | ||
391 | arch_teardown_msi_irqs(dev); | |
392 | ||
393 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
394 | if (entry->msi_attrib.is_msix) { | |
395 | if (list_is_last(&entry->list, &dev->msi_list)) | |
396 | iounmap(entry->mask_base); | |
397 | } | |
424eb391 NH |
398 | |
399 | /* | |
400 | * Its possible that we get into this path | |
401 | * When populate_msi_sysfs fails, which means the entries | |
402 | * were not registered with sysfs. In that case don't | |
403 | * unregister them. | |
404 | */ | |
405 | if (entry->kobj.parent) { | |
406 | kobject_del(&entry->kobj); | |
407 | kobject_put(&entry->kobj); | |
408 | } | |
409 | ||
f56e4481 HS |
410 | list_del(&entry->list); |
411 | kfree(entry); | |
412 | } | |
413 | } | |
c54c1879 | 414 | |
379f5327 | 415 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 416 | { |
379f5327 MW |
417 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
418 | if (!desc) | |
1da177e4 LT |
419 | return NULL; |
420 | ||
379f5327 MW |
421 | INIT_LIST_HEAD(&desc->list); |
422 | desc->dev = dev; | |
1da177e4 | 423 | |
379f5327 | 424 | return desc; |
1da177e4 LT |
425 | } |
426 | ||
ba698ad4 DM |
427 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
428 | { | |
429 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
430 | pci_intx(dev, enable); | |
431 | } | |
432 | ||
8fed4b65 | 433 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 434 | { |
41017f0c | 435 | u16 control; |
392ee1e6 | 436 | struct msi_desc *entry; |
41017f0c | 437 | |
b1cbf4e4 EB |
438 | if (!dev->msi_enabled) |
439 | return; | |
440 | ||
dced35ae | 441 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 442 | |
ba698ad4 | 443 | pci_intx_for_msi(dev, 0); |
e375b561 | 444 | msi_set_enable(dev, 0); |
76ccc297 | 445 | arch_restore_msi_irqs(dev, dev->irq); |
392ee1e6 | 446 | |
f5322169 | 447 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
f2440d9a | 448 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 449 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 450 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 451 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
452 | } |
453 | ||
454 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 455 | { |
41017f0c | 456 | struct msi_desc *entry; |
392ee1e6 | 457 | u16 control; |
41017f0c | 458 | |
ded86d8d EB |
459 | if (!dev->msix_enabled) |
460 | return; | |
f598282f | 461 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 462 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f5322169 | 463 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
ded86d8d | 464 | |
41017f0c | 465 | /* route the table */ |
ba698ad4 | 466 | pci_intx_for_msi(dev, 0); |
f598282f | 467 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 468 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 469 | |
4aa9bc95 | 470 | list_for_each_entry(entry, &dev->msi_list, list) { |
76ccc297 | 471 | arch_restore_msi_irqs(dev, entry->irq); |
f2440d9a | 472 | msix_mask_irq(entry, entry->masked); |
41017f0c | 473 | } |
41017f0c | 474 | |
392ee1e6 | 475 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 476 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 477 | } |
8fed4b65 ME |
478 | |
479 | void pci_restore_msi_state(struct pci_dev *dev) | |
480 | { | |
481 | __pci_restore_msi_state(dev); | |
482 | __pci_restore_msix_state(dev); | |
483 | } | |
94688cf2 | 484 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 485 | |
da8d1c8b NH |
486 | |
487 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
488 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
489 | ||
490 | struct msi_attribute { | |
491 | struct attribute attr; | |
492 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
493 | char *buf); | |
494 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
495 | const char *buf, size_t count); | |
496 | }; | |
497 | ||
498 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
499 | char *buf) | |
500 | { | |
501 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
502 | } | |
503 | ||
504 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
505 | struct attribute *attr, char *buf) | |
506 | { | |
507 | struct msi_attribute *attribute = to_msi_attr(attr); | |
508 | struct msi_desc *entry = to_msi_desc(kobj); | |
509 | ||
510 | if (!attribute->show) | |
511 | return -EIO; | |
512 | ||
513 | return attribute->show(entry, attribute, buf); | |
514 | } | |
515 | ||
516 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
517 | .show = msi_irq_attr_show, | |
518 | }; | |
519 | ||
520 | static struct msi_attribute mode_attribute = | |
521 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
522 | ||
523 | ||
9738abed | 524 | static struct attribute *msi_irq_default_attrs[] = { |
da8d1c8b NH |
525 | &mode_attribute.attr, |
526 | NULL | |
527 | }; | |
528 | ||
9738abed | 529 | static void msi_kobj_release(struct kobject *kobj) |
da8d1c8b NH |
530 | { |
531 | struct msi_desc *entry = to_msi_desc(kobj); | |
532 | ||
533 | pci_dev_put(entry->dev); | |
534 | } | |
535 | ||
536 | static struct kobj_type msi_irq_ktype = { | |
537 | .release = msi_kobj_release, | |
538 | .sysfs_ops = &msi_irq_sysfs_ops, | |
539 | .default_attrs = msi_irq_default_attrs, | |
540 | }; | |
541 | ||
542 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
543 | { | |
544 | struct msi_desc *entry; | |
545 | struct kobject *kobj; | |
546 | int ret; | |
547 | int count = 0; | |
548 | ||
549 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
550 | if (!pdev->msi_kset) | |
551 | return -ENOMEM; | |
552 | ||
553 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
554 | kobj = &entry->kobj; | |
555 | kobj->kset = pdev->msi_kset; | |
556 | pci_dev_get(pdev); | |
557 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
558 | "%u", entry->irq); | |
559 | if (ret) | |
560 | goto out_unroll; | |
561 | ||
562 | count++; | |
563 | } | |
564 | ||
565 | return 0; | |
566 | ||
567 | out_unroll: | |
568 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
569 | if (!count) | |
570 | break; | |
571 | kobject_del(&entry->kobj); | |
572 | kobject_put(&entry->kobj); | |
573 | count--; | |
574 | } | |
575 | return ret; | |
576 | } | |
577 | ||
1da177e4 LT |
578 | /** |
579 | * msi_capability_init - configure device's MSI capability structure | |
580 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 581 | * @nvec: number of interrupts to allocate |
1da177e4 | 582 | * |
1c8d7b0a MW |
583 | * Setup the MSI capability structure of the device with the requested |
584 | * number of interrupts. A return value of zero indicates the successful | |
585 | * setup of an entry with the new MSI irq. A negative return value indicates | |
586 | * an error, and a positive return value indicates the number of interrupts | |
587 | * which could have been allocated. | |
588 | */ | |
589 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
590 | { |
591 | struct msi_desc *entry; | |
f465136d | 592 | int ret; |
1da177e4 | 593 | u16 control; |
f2440d9a | 594 | unsigned mask; |
1da177e4 | 595 | |
e375b561 | 596 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 597 | |
f84ecd28 | 598 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
1da177e4 | 599 | /* MSI Entry Initialization */ |
379f5327 | 600 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
601 | if (!entry) |
602 | return -ENOMEM; | |
1ce03373 | 603 | |
500559a9 | 604 | entry->msi_attrib.is_msix = 0; |
4987ce82 | 605 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
500559a9 | 606 | entry->msi_attrib.entry_nr = 0; |
4987ce82 | 607 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
500559a9 | 608 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
f465136d | 609 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 610 | |
e5f66eaf DC |
611 | if (control & PCI_MSI_FLAGS_64BIT) |
612 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
613 | else | |
614 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
f2440d9a MW |
615 | /* All MSIs are unmasked by default, Mask them all */ |
616 | if (entry->msi_attrib.maskbit) | |
617 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
618 | mask = msi_capable_mask(control); | |
619 | msi_mask_irq(entry, mask, mask); | |
620 | ||
0dd11f9b | 621 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 622 | |
1da177e4 | 623 | /* Configure MSI capability structure */ |
1c8d7b0a | 624 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 625 | if (ret) { |
7ba1930d | 626 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 627 | free_msi_irqs(dev); |
7fe3730d | 628 | return ret; |
fd58e55f | 629 | } |
f7feaca7 | 630 | |
da8d1c8b NH |
631 | ret = populate_msi_sysfs(dev); |
632 | if (ret) { | |
633 | msi_mask_irq(entry, mask, ~mask); | |
634 | free_msi_irqs(dev); | |
635 | return ret; | |
636 | } | |
637 | ||
1da177e4 | 638 | /* Set MSI enabled bits */ |
ba698ad4 | 639 | pci_intx_for_msi(dev, 0); |
e375b561 | 640 | msi_set_enable(dev, 1); |
b1cbf4e4 | 641 | dev->msi_enabled = 1; |
1da177e4 | 642 | |
7fe3730d | 643 | dev->irq = entry->irq; |
1da177e4 LT |
644 | return 0; |
645 | } | |
646 | ||
520fe9dc | 647 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 648 | { |
4302e0fb | 649 | resource_size_t phys_addr; |
5a05a9d8 HS |
650 | u32 table_offset; |
651 | u8 bir; | |
652 | ||
909094c6 BH |
653 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
654 | &table_offset); | |
4d18760c BH |
655 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
656 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
657 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
658 | ||
659 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
660 | } | |
661 | ||
520fe9dc GS |
662 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
663 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
664 | { |
665 | struct msi_desc *entry; | |
666 | int i; | |
667 | ||
668 | for (i = 0; i < nvec; i++) { | |
669 | entry = alloc_msi_entry(dev); | |
670 | if (!entry) { | |
671 | if (!i) | |
672 | iounmap(base); | |
673 | else | |
674 | free_msi_irqs(dev); | |
675 | /* No enough memory. Don't try again */ | |
676 | return -ENOMEM; | |
677 | } | |
678 | ||
679 | entry->msi_attrib.is_msix = 1; | |
680 | entry->msi_attrib.is_64 = 1; | |
681 | entry->msi_attrib.entry_nr = entries[i].entry; | |
682 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 683 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
684 | entry->mask_base = base; |
685 | ||
686 | list_add_tail(&entry->list, &dev->msi_list); | |
687 | } | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
75cb3426 | 692 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 693 | struct msix_entry *entries) |
75cb3426 HS |
694 | { |
695 | struct msi_desc *entry; | |
696 | int i = 0; | |
697 | ||
698 | list_for_each_entry(entry, &dev->msi_list, list) { | |
699 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
700 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
701 | ||
702 | entries[i].vector = entry->irq; | |
dced35ae | 703 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
704 | entry->masked = readl(entry->mask_base + offset); |
705 | msix_mask_irq(entry, 1); | |
706 | i++; | |
707 | } | |
708 | } | |
709 | ||
1da177e4 LT |
710 | /** |
711 | * msix_capability_init - configure device's MSI-X capability | |
712 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
713 | * @entries: pointer to an array of struct msix_entry entries |
714 | * @nvec: number of @entries | |
1da177e4 | 715 | * |
eaae4b3a | 716 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
717 | * single MSI-X irq. A return of zero indicates the successful setup of |
718 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
719 | **/ |
720 | static int msix_capability_init(struct pci_dev *dev, | |
721 | struct msix_entry *entries, int nvec) | |
722 | { | |
520fe9dc | 723 | int ret; |
5a05a9d8 | 724 | u16 control; |
1da177e4 LT |
725 | void __iomem *base; |
726 | ||
520fe9dc | 727 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
f598282f MW |
728 | |
729 | /* Ensure MSI-X is disabled while it is set up */ | |
730 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 731 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 732 | |
1da177e4 | 733 | /* Request & Map MSI-X table region */ |
527eee29 | 734 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 735 | if (!base) |
1da177e4 LT |
736 | return -ENOMEM; |
737 | ||
520fe9dc | 738 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
739 | if (ret) |
740 | return ret; | |
9c831334 ME |
741 | |
742 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
743 | if (ret) |
744 | goto error; | |
9c831334 | 745 | |
f598282f MW |
746 | /* |
747 | * Some devices require MSI-X to be enabled before we can touch the | |
748 | * MSI-X registers. We need to mask all the vectors to prevent | |
749 | * interrupts coming in before they're fully set up. | |
750 | */ | |
751 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 752 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 753 | |
75cb3426 | 754 | msix_program_entries(dev, entries); |
f598282f | 755 | |
da8d1c8b NH |
756 | ret = populate_msi_sysfs(dev); |
757 | if (ret) { | |
758 | ret = 0; | |
759 | goto error; | |
760 | } | |
761 | ||
f598282f | 762 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 763 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 764 | dev->msix_enabled = 1; |
1da177e4 | 765 | |
f598282f | 766 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
520fe9dc | 767 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
8d181018 | 768 | |
1da177e4 | 769 | return 0; |
583871d4 HS |
770 | |
771 | error: | |
772 | if (ret < 0) { | |
773 | /* | |
774 | * If we had some success, report the number of irqs | |
775 | * we succeeded in setting up. | |
776 | */ | |
d9d7070e | 777 | struct msi_desc *entry; |
583871d4 HS |
778 | int avail = 0; |
779 | ||
780 | list_for_each_entry(entry, &dev->msi_list, list) { | |
781 | if (entry->irq != 0) | |
782 | avail++; | |
783 | } | |
784 | if (avail != 0) | |
785 | ret = avail; | |
786 | } | |
787 | ||
788 | free_msi_irqs(dev); | |
789 | ||
790 | return ret; | |
1da177e4 LT |
791 | } |
792 | ||
24334a12 | 793 | /** |
17bbc12a | 794 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 795 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 796 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 797 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 798 | * |
0306ebfa | 799 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
800 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
801 | * supported return 0, else return an error code. | |
24334a12 | 802 | **/ |
500559a9 | 803 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
804 | { |
805 | struct pci_bus *bus; | |
c9953a73 | 806 | int ret; |
24334a12 | 807 | |
0306ebfa | 808 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
809 | if (!pci_msi_enable || !dev || dev->no_msi) |
810 | return -EINVAL; | |
811 | ||
314e77b3 ME |
812 | /* |
813 | * You can't ask to have 0 or less MSIs configured. | |
814 | * a) it's stupid .. | |
815 | * b) the list manipulation code assumes nvec >= 1. | |
816 | */ | |
817 | if (nvec < 1) | |
818 | return -ERANGE; | |
819 | ||
500559a9 HS |
820 | /* |
821 | * Any bridge which does NOT route MSI transactions from its | |
822 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
823 | * the secondary pci_bus. |
824 | * We expect only arch-specific PCI host bus controller driver | |
825 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
826 | */ | |
24334a12 BG |
827 | for (bus = dev->bus; bus; bus = bus->parent) |
828 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
829 | return -EINVAL; | |
830 | ||
c9953a73 ME |
831 | ret = arch_msi_check_device(dev, nvec, type); |
832 | if (ret) | |
833 | return ret; | |
834 | ||
24334a12 BG |
835 | return 0; |
836 | } | |
837 | ||
1da177e4 | 838 | /** |
1c8d7b0a MW |
839 | * pci_enable_msi_block - configure device's MSI capability structure |
840 | * @dev: device to configure | |
841 | * @nvec: number of interrupts to configure | |
1da177e4 | 842 | * |
1c8d7b0a MW |
843 | * Allocate IRQs for a device with the MSI capability. |
844 | * This function returns a negative errno if an error occurs. If it | |
845 | * is unable to allocate the number of interrupts requested, it returns | |
846 | * the number of interrupts it might be able to allocate. If it successfully | |
847 | * allocates at least the number of interrupts requested, it returns 0 and | |
848 | * updates the @dev's irq member to the lowest new interrupt number; the | |
849 | * other interrupt numbers allocated to this device are consecutive. | |
850 | */ | |
851 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 852 | { |
f465136d | 853 | int status, maxvec; |
1c8d7b0a MW |
854 | u16 msgctl; |
855 | ||
f465136d | 856 | if (!dev->msi_cap) |
1c8d7b0a | 857 | return -EINVAL; |
f465136d GS |
858 | |
859 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
1c8d7b0a MW |
860 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
861 | if (nvec > maxvec) | |
862 | return maxvec; | |
1da177e4 | 863 | |
1c8d7b0a | 864 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
865 | if (status) |
866 | return status; | |
1da177e4 | 867 | |
ded86d8d | 868 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 869 | |
1c8d7b0a | 870 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 871 | if (dev->msix_enabled) { |
80ccba11 BH |
872 | dev_info(&dev->dev, "can't enable MSI " |
873 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 874 | return -EINVAL; |
1da177e4 | 875 | } |
1c8d7b0a MW |
876 | |
877 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
878 | return status; |
879 | } | |
1c8d7b0a | 880 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 881 | |
08261d87 AG |
882 | int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec) |
883 | { | |
f465136d | 884 | int ret, nvec; |
08261d87 AG |
885 | u16 msgctl; |
886 | ||
f465136d | 887 | if (!dev->msi_cap) |
08261d87 AG |
888 | return -EINVAL; |
889 | ||
f465136d | 890 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); |
08261d87 AG |
891 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); |
892 | ||
893 | if (maxvec) | |
894 | *maxvec = ret; | |
895 | ||
896 | do { | |
897 | nvec = ret; | |
898 | ret = pci_enable_msi_block(dev, nvec); | |
899 | } while (ret > 0); | |
900 | ||
901 | if (ret < 0) | |
902 | return ret; | |
903 | return nvec; | |
904 | } | |
905 | EXPORT_SYMBOL(pci_enable_msi_block_auto); | |
906 | ||
f2440d9a | 907 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 908 | { |
f2440d9a MW |
909 | struct msi_desc *desc; |
910 | u32 mask; | |
911 | u16 ctrl; | |
1da177e4 | 912 | |
128bc5fc | 913 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
914 | return; |
915 | ||
110828c9 MW |
916 | BUG_ON(list_empty(&dev->msi_list)); |
917 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 918 | |
e375b561 | 919 | msi_set_enable(dev, 0); |
ba698ad4 | 920 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 921 | dev->msi_enabled = 0; |
7bd007e4 | 922 | |
12abb8ba | 923 | /* Return the device with MSI unmasked as initial states */ |
f5322169 | 924 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 925 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
926 | /* Keep cached state to be restored */ |
927 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
928 | |
929 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 930 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 931 | } |
24d27553 | 932 | |
500559a9 | 933 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 934 | { |
d52877c7 YL |
935 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
936 | return; | |
937 | ||
938 | pci_msi_shutdown(dev); | |
f56e4481 | 939 | free_msi_irqs(dev); |
da8d1c8b NH |
940 | kset_unregister(dev->msi_kset); |
941 | dev->msi_kset = NULL; | |
1da177e4 | 942 | } |
4cc086fa | 943 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 944 | |
a52e2e35 RW |
945 | /** |
946 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
947 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
948 | */ | |
949 | int pci_msix_table_size(struct pci_dev *dev) | |
950 | { | |
a52e2e35 RW |
951 | u16 control; |
952 | ||
520fe9dc | 953 | if (!dev->msix_cap) |
a52e2e35 RW |
954 | return 0; |
955 | ||
f84ecd28 | 956 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 957 | return msix_table_size(control); |
a52e2e35 RW |
958 | } |
959 | ||
1da177e4 LT |
960 | /** |
961 | * pci_enable_msix - configure device's MSI-X capability structure | |
962 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 963 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 964 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
965 | * |
966 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 967 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
968 | * MSI-X mode enabled on its hardware device function. A return of zero |
969 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 970 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 971 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
972 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
973 | * re-send its request. | |
1da177e4 | 974 | **/ |
500559a9 | 975 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 976 | { |
a52e2e35 | 977 | int status, nr_entries; |
ded86d8d | 978 | int i, j; |
1da177e4 | 979 | |
cdf1fd4d | 980 | if (!entries || !dev->msix_cap) |
500559a9 | 981 | return -EINVAL; |
1da177e4 | 982 | |
c9953a73 ME |
983 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
984 | if (status) | |
985 | return status; | |
986 | ||
a52e2e35 | 987 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 988 | if (nvec > nr_entries) |
57fbf52c | 989 | return nr_entries; |
1da177e4 LT |
990 | |
991 | /* Check for any invalid entries */ | |
992 | for (i = 0; i < nvec; i++) { | |
993 | if (entries[i].entry >= nr_entries) | |
994 | return -EINVAL; /* invalid entry */ | |
995 | for (j = i + 1; j < nvec; j++) { | |
996 | if (entries[i].entry == entries[j].entry) | |
997 | return -EINVAL; /* duplicate entry */ | |
998 | } | |
999 | } | |
ded86d8d | 1000 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 1001 | |
1ce03373 | 1002 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 1003 | if (dev->msi_enabled) { |
80ccba11 BH |
1004 | dev_info(&dev->dev, "can't enable MSI-X " |
1005 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
1006 | return -EINVAL; |
1007 | } | |
1da177e4 | 1008 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
1009 | return status; |
1010 | } | |
4cc086fa | 1011 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 1012 | |
500559a9 | 1013 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 1014 | { |
12abb8ba HS |
1015 | struct msi_desc *entry; |
1016 | ||
128bc5fc | 1017 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1018 | return; |
1019 | ||
12abb8ba HS |
1020 | /* Return the device with MSI-X masked as initial states */ |
1021 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1022 | /* Keep cached states to be restored */ | |
1023 | __msix_mask_irq(entry, 1); | |
1024 | } | |
1025 | ||
b1cbf4e4 | 1026 | msix_set_enable(dev, 0); |
ba698ad4 | 1027 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1028 | dev->msix_enabled = 0; |
d52877c7 | 1029 | } |
c901851f | 1030 | |
500559a9 | 1031 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1032 | { |
1033 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1034 | return; | |
1035 | ||
1036 | pci_msix_shutdown(dev); | |
f56e4481 | 1037 | free_msi_irqs(dev); |
da8d1c8b NH |
1038 | kset_unregister(dev->msi_kset); |
1039 | dev->msi_kset = NULL; | |
1da177e4 | 1040 | } |
4cc086fa | 1041 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1042 | |
1043 | /** | |
1ce03373 | 1044 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1045 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1046 | * | |
eaae4b3a | 1047 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1048 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1049 | * allocated for this device function, are reclaimed to unused state, |
1050 | * which may be used later on. | |
1051 | **/ | |
500559a9 | 1052 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1053 | { |
1da177e4 | 1054 | if (!pci_msi_enable || !dev) |
500559a9 | 1055 | return; |
1da177e4 | 1056 | |
f56e4481 HS |
1057 | if (dev->msi_enabled || dev->msix_enabled) |
1058 | free_msi_irqs(dev); | |
1da177e4 LT |
1059 | } |
1060 | ||
309e57df MW |
1061 | void pci_no_msi(void) |
1062 | { | |
1063 | pci_msi_enable = 0; | |
1064 | } | |
c9953a73 | 1065 | |
07ae95f9 AP |
1066 | /** |
1067 | * pci_msi_enabled - is MSI enabled? | |
1068 | * | |
1069 | * Returns true if MSI has not been disabled by the command-line option | |
1070 | * pci=nomsi. | |
1071 | **/ | |
1072 | int pci_msi_enabled(void) | |
d389fec6 | 1073 | { |
07ae95f9 | 1074 | return pci_msi_enable; |
d389fec6 | 1075 | } |
07ae95f9 | 1076 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1077 | |
07ae95f9 | 1078 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1079 | { |
07ae95f9 | 1080 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1081 | |
1082 | /* Disable the msi hardware to avoid screaming interrupts | |
1083 | * during boot. This is the power on reset default so | |
1084 | * usually this should be a noop. | |
1085 | */ | |
e375b561 GS |
1086 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1087 | if (dev->msi_cap) | |
1088 | msi_set_enable(dev, 0); | |
1089 | ||
1090 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1091 | if (dev->msix_cap) | |
1092 | msix_set_enable(dev, 0); | |
d389fec6 | 1093 | } |