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1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
9 | #include <linux/mm.h> | |
10 | #include <linux/irq.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/config.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
18 | ||
19 | #include <asm/errno.h> | |
20 | #include <asm/io.h> | |
21 | #include <asm/smp.h> | |
22 | ||
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
26 | static DEFINE_SPINLOCK(msi_lock); | |
27 | static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; | |
28 | static kmem_cache_t* msi_cachep; | |
29 | ||
30 | static int pci_msi_enable = 1; | |
70549ad9 GKH |
31 | static int last_alloc_vector; |
32 | static int nr_released_vectors; | |
1da177e4 | 33 | static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS; |
70549ad9 | 34 | static int nr_msix_devices; |
1da177e4 LT |
35 | |
36 | #ifndef CONFIG_X86_IO_APIC | |
37 | int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1}; | |
38 | u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 }; | |
39 | #endif | |
40 | ||
41 | static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags) | |
42 | { | |
43 | memset(p, 0, NR_IRQS * sizeof(struct msi_desc)); | |
44 | } | |
45 | ||
46 | static int msi_cache_init(void) | |
47 | { | |
48 | msi_cachep = kmem_cache_create("msi_cache", | |
49 | NR_IRQS * sizeof(struct msi_desc), | |
50 | 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL); | |
51 | if (!msi_cachep) | |
52 | return -ENOMEM; | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | static void msi_set_mask_bit(unsigned int vector, int flag) | |
58 | { | |
59 | struct msi_desc *entry; | |
60 | ||
61 | entry = (struct msi_desc *)msi_desc[vector]; | |
62 | if (!entry || !entry->dev || !entry->mask_base) | |
63 | return; | |
64 | switch (entry->msi_attrib.type) { | |
65 | case PCI_CAP_ID_MSI: | |
66 | { | |
67 | int pos; | |
68 | u32 mask_bits; | |
69 | ||
70 | pos = (long)entry->mask_base; | |
71 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
72 | mask_bits &= ~(1); | |
73 | mask_bits |= flag; | |
74 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
75 | break; | |
76 | } | |
77 | case PCI_CAP_ID_MSIX: | |
78 | { | |
79 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
80 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
81 | writel(flag, entry->mask_base + offset); | |
82 | break; | |
83 | } | |
84 | default: | |
85 | break; | |
86 | } | |
87 | } | |
88 | ||
89 | #ifdef CONFIG_SMP | |
90 | static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask) | |
91 | { | |
92 | struct msi_desc *entry; | |
93 | struct msg_address address; | |
94 | ||
95 | entry = (struct msi_desc *)msi_desc[vector]; | |
96 | if (!entry || !entry->dev) | |
97 | return; | |
98 | ||
99 | switch (entry->msi_attrib.type) { | |
100 | case PCI_CAP_ID_MSI: | |
101 | { | |
102 | int pos; | |
103 | ||
104 | if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI))) | |
105 | return; | |
106 | ||
107 | pci_read_config_dword(entry->dev, msi_lower_address_reg(pos), | |
108 | &address.lo_address.value); | |
109 | address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; | |
110 | address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) << | |
111 | MSI_TARGET_CPU_SHIFT); | |
112 | entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask); | |
113 | pci_write_config_dword(entry->dev, msi_lower_address_reg(pos), | |
114 | address.lo_address.value); | |
115 | break; | |
116 | } | |
117 | case PCI_CAP_ID_MSIX: | |
118 | { | |
119 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
120 | PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET; | |
121 | ||
122 | address.lo_address.value = readl(entry->mask_base + offset); | |
123 | address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK; | |
124 | address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) << | |
125 | MSI_TARGET_CPU_SHIFT); | |
126 | entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask); | |
127 | writel(address.lo_address.value, entry->mask_base + offset); | |
128 | break; | |
129 | } | |
130 | default: | |
131 | break; | |
132 | } | |
133 | } | |
134 | ||
135 | #ifdef CONFIG_IRQBALANCE | |
136 | static inline void move_msi(int vector) | |
137 | { | |
138 | if (!cpus_empty(pending_irq_balance_cpumask[vector])) { | |
139 | set_msi_affinity(vector, pending_irq_balance_cpumask[vector]); | |
140 | cpus_clear(pending_irq_balance_cpumask[vector]); | |
141 | } | |
142 | } | |
143 | #endif /* CONFIG_IRQBALANCE */ | |
144 | #endif /* CONFIG_SMP */ | |
145 | ||
146 | static void mask_MSI_irq(unsigned int vector) | |
147 | { | |
148 | msi_set_mask_bit(vector, 1); | |
149 | } | |
150 | ||
151 | static void unmask_MSI_irq(unsigned int vector) | |
152 | { | |
153 | msi_set_mask_bit(vector, 0); | |
154 | } | |
155 | ||
156 | static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector) | |
157 | { | |
158 | struct msi_desc *entry; | |
159 | unsigned long flags; | |
160 | ||
161 | spin_lock_irqsave(&msi_lock, flags); | |
162 | entry = msi_desc[vector]; | |
163 | if (!entry || !entry->dev) { | |
164 | spin_unlock_irqrestore(&msi_lock, flags); | |
165 | return 0; | |
166 | } | |
167 | entry->msi_attrib.state = 1; /* Mark it active */ | |
168 | spin_unlock_irqrestore(&msi_lock, flags); | |
169 | ||
170 | return 0; /* never anything pending */ | |
171 | } | |
172 | ||
70549ad9 | 173 | static unsigned int startup_msi_irq_w_maskbit(unsigned int vector) |
1da177e4 | 174 | { |
70549ad9 GKH |
175 | startup_msi_irq_wo_maskbit(vector); |
176 | unmask_MSI_irq(vector); | |
177 | return 0; /* never anything pending */ | |
1da177e4 LT |
178 | } |
179 | ||
70549ad9 | 180 | static void shutdown_msi_irq(unsigned int vector) |
1da177e4 LT |
181 | { |
182 | struct msi_desc *entry; | |
183 | unsigned long flags; | |
184 | ||
185 | spin_lock_irqsave(&msi_lock, flags); | |
186 | entry = msi_desc[vector]; | |
70549ad9 GKH |
187 | if (entry && entry->dev) |
188 | entry->msi_attrib.state = 0; /* Mark it not active */ | |
1da177e4 | 189 | spin_unlock_irqrestore(&msi_lock, flags); |
1da177e4 LT |
190 | } |
191 | ||
70549ad9 GKH |
192 | static void end_msi_irq_wo_maskbit(unsigned int vector) |
193 | { | |
194 | move_msi(vector); | |
195 | ack_APIC_irq(); | |
196 | } | |
1da177e4 LT |
197 | |
198 | static void end_msi_irq_w_maskbit(unsigned int vector) | |
199 | { | |
200 | move_msi(vector); | |
201 | unmask_MSI_irq(vector); | |
202 | ack_APIC_irq(); | |
203 | } | |
204 | ||
70549ad9 GKH |
205 | static void do_nothing(unsigned int vector) |
206 | { | |
207 | } | |
208 | ||
1da177e4 LT |
209 | /* |
210 | * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices, | |
211 | * which implement the MSI-X Capability Structure. | |
212 | */ | |
213 | static struct hw_interrupt_type msix_irq_type = { | |
214 | .typename = "PCI-MSI-X", | |
215 | .startup = startup_msi_irq_w_maskbit, | |
70549ad9 GKH |
216 | .shutdown = shutdown_msi_irq, |
217 | .enable = unmask_MSI_irq, | |
218 | .disable = mask_MSI_irq, | |
219 | .ack = mask_MSI_irq, | |
1da177e4 LT |
220 | .end = end_msi_irq_w_maskbit, |
221 | .set_affinity = set_msi_irq_affinity | |
222 | }; | |
223 | ||
224 | /* | |
225 | * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, | |
226 | * which implement the MSI Capability Structure with | |
227 | * Mask-and-Pending Bits. | |
228 | */ | |
229 | static struct hw_interrupt_type msi_irq_w_maskbit_type = { | |
230 | .typename = "PCI-MSI", | |
231 | .startup = startup_msi_irq_w_maskbit, | |
70549ad9 GKH |
232 | .shutdown = shutdown_msi_irq, |
233 | .enable = unmask_MSI_irq, | |
234 | .disable = mask_MSI_irq, | |
235 | .ack = mask_MSI_irq, | |
1da177e4 LT |
236 | .end = end_msi_irq_w_maskbit, |
237 | .set_affinity = set_msi_irq_affinity | |
238 | }; | |
239 | ||
240 | /* | |
241 | * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices, | |
242 | * which implement the MSI Capability Structure without | |
243 | * Mask-and-Pending Bits. | |
244 | */ | |
245 | static struct hw_interrupt_type msi_irq_wo_maskbit_type = { | |
246 | .typename = "PCI-MSI", | |
247 | .startup = startup_msi_irq_wo_maskbit, | |
70549ad9 GKH |
248 | .shutdown = shutdown_msi_irq, |
249 | .enable = do_nothing, | |
250 | .disable = do_nothing, | |
251 | .ack = do_nothing, | |
1da177e4 LT |
252 | .end = end_msi_irq_wo_maskbit, |
253 | .set_affinity = set_msi_irq_affinity | |
254 | }; | |
255 | ||
256 | static void msi_data_init(struct msg_data *msi_data, | |
257 | unsigned int vector) | |
258 | { | |
259 | memset(msi_data, 0, sizeof(struct msg_data)); | |
260 | msi_data->vector = (u8)vector; | |
261 | msi_data->delivery_mode = MSI_DELIVERY_MODE; | |
262 | msi_data->level = MSI_LEVEL_MODE; | |
263 | msi_data->trigger = MSI_TRIGGER_MODE; | |
264 | } | |
265 | ||
266 | static void msi_address_init(struct msg_address *msi_address) | |
267 | { | |
268 | unsigned int dest_id; | |
269 | ||
270 | memset(msi_address, 0, sizeof(struct msg_address)); | |
271 | msi_address->hi_address = (u32)0; | |
272 | dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT); | |
273 | msi_address->lo_address.u.dest_mode = MSI_DEST_MODE; | |
274 | msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE; | |
275 | msi_address->lo_address.u.dest_id = dest_id; | |
276 | msi_address->lo_address.value |= (MSI_TARGET_CPU << MSI_TARGET_CPU_SHIFT); | |
277 | } | |
278 | ||
279 | static int msi_free_vector(struct pci_dev* dev, int vector, int reassign); | |
280 | static int assign_msi_vector(void) | |
281 | { | |
282 | static int new_vector_avail = 1; | |
283 | int vector; | |
284 | unsigned long flags; | |
285 | ||
286 | /* | |
287 | * msi_lock is provided to ensure that successful allocation of MSI | |
288 | * vector is assigned unique among drivers. | |
289 | */ | |
290 | spin_lock_irqsave(&msi_lock, flags); | |
291 | ||
292 | if (!new_vector_avail) { | |
293 | int free_vector = 0; | |
294 | ||
295 | /* | |
296 | * vector_irq[] = -1 indicates that this specific vector is: | |
297 | * - assigned for MSI (since MSI have no associated IRQ) or | |
298 | * - assigned for legacy if less than 16, or | |
299 | * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping | |
300 | * vector_irq[] = 0 indicates that this vector, previously | |
301 | * assigned for MSI, is freed by hotplug removed operations. | |
302 | * This vector will be reused for any subsequent hotplug added | |
303 | * operations. | |
304 | * vector_irq[] > 0 indicates that this vector is assigned for | |
305 | * IOxAPIC IRQs. This vector and its value provides a 1-to-1 | |
306 | * vector-to-IOxAPIC IRQ mapping. | |
307 | */ | |
308 | for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { | |
309 | if (vector_irq[vector] != 0) | |
310 | continue; | |
311 | free_vector = vector; | |
312 | if (!msi_desc[vector]) | |
313 | break; | |
314 | else | |
315 | continue; | |
316 | } | |
317 | if (!free_vector) { | |
318 | spin_unlock_irqrestore(&msi_lock, flags); | |
319 | return -EBUSY; | |
320 | } | |
321 | vector_irq[free_vector] = -1; | |
322 | nr_released_vectors--; | |
323 | spin_unlock_irqrestore(&msi_lock, flags); | |
324 | if (msi_desc[free_vector] != NULL) { | |
325 | struct pci_dev *dev; | |
326 | int tail; | |
327 | ||
328 | /* free all linked vectors before re-assign */ | |
329 | do { | |
330 | spin_lock_irqsave(&msi_lock, flags); | |
331 | dev = msi_desc[free_vector]->dev; | |
332 | tail = msi_desc[free_vector]->link.tail; | |
333 | spin_unlock_irqrestore(&msi_lock, flags); | |
334 | msi_free_vector(dev, tail, 1); | |
335 | } while (free_vector != tail); | |
336 | } | |
337 | ||
338 | return free_vector; | |
339 | } | |
340 | vector = assign_irq_vector(AUTO_ASSIGN); | |
341 | last_alloc_vector = vector; | |
342 | if (vector == LAST_DEVICE_VECTOR) | |
343 | new_vector_avail = 0; | |
344 | ||
345 | spin_unlock_irqrestore(&msi_lock, flags); | |
346 | return vector; | |
347 | } | |
348 | ||
349 | static int get_new_vector(void) | |
350 | { | |
351 | int vector; | |
352 | ||
353 | if ((vector = assign_msi_vector()) > 0) | |
354 | set_intr_gate(vector, interrupt[vector]); | |
355 | ||
356 | return vector; | |
357 | } | |
358 | ||
359 | static int msi_init(void) | |
360 | { | |
361 | static int status = -ENOMEM; | |
362 | ||
363 | if (!status) | |
364 | return status; | |
365 | ||
366 | if (pci_msi_quirk) { | |
367 | pci_msi_enable = 0; | |
368 | printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n"); | |
369 | status = -EINVAL; | |
370 | return status; | |
371 | } | |
372 | ||
373 | if ((status = msi_cache_init()) < 0) { | |
374 | pci_msi_enable = 0; | |
375 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
376 | return status; | |
377 | } | |
378 | last_alloc_vector = assign_irq_vector(AUTO_ASSIGN); | |
379 | if (last_alloc_vector < 0) { | |
380 | pci_msi_enable = 0; | |
381 | printk(KERN_WARNING "PCI: No interrupt vectors available for MSI\n"); | |
382 | status = -EBUSY; | |
383 | return status; | |
384 | } | |
385 | vector_irq[last_alloc_vector] = 0; | |
386 | nr_released_vectors++; | |
387 | ||
388 | return status; | |
389 | } | |
390 | ||
391 | static int get_msi_vector(struct pci_dev *dev) | |
392 | { | |
393 | return get_new_vector(); | |
394 | } | |
395 | ||
396 | static struct msi_desc* alloc_msi_entry(void) | |
397 | { | |
398 | struct msi_desc *entry; | |
399 | ||
70549ad9 | 400 | entry = kmem_cache_alloc(msi_cachep, SLAB_KERNEL); |
1da177e4 LT |
401 | if (!entry) |
402 | return NULL; | |
403 | ||
404 | memset(entry, 0, sizeof(struct msi_desc)); | |
405 | entry->link.tail = entry->link.head = 0; /* single message */ | |
406 | entry->dev = NULL; | |
407 | ||
408 | return entry; | |
409 | } | |
410 | ||
411 | static void attach_msi_entry(struct msi_desc *entry, int vector) | |
412 | { | |
413 | unsigned long flags; | |
414 | ||
415 | spin_lock_irqsave(&msi_lock, flags); | |
416 | msi_desc[vector] = entry; | |
417 | spin_unlock_irqrestore(&msi_lock, flags); | |
418 | } | |
419 | ||
420 | static void irq_handler_init(int cap_id, int pos, int mask) | |
421 | { | |
422 | spin_lock(&irq_desc[pos].lock); | |
423 | if (cap_id == PCI_CAP_ID_MSIX) | |
424 | irq_desc[pos].handler = &msix_irq_type; | |
425 | else { | |
426 | if (!mask) | |
427 | irq_desc[pos].handler = &msi_irq_wo_maskbit_type; | |
428 | else | |
429 | irq_desc[pos].handler = &msi_irq_w_maskbit_type; | |
430 | } | |
431 | spin_unlock(&irq_desc[pos].lock); | |
432 | } | |
433 | ||
434 | static void enable_msi_mode(struct pci_dev *dev, int pos, int type) | |
435 | { | |
436 | u16 control; | |
437 | ||
438 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
439 | if (type == PCI_CAP_ID_MSI) { | |
440 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
441 | msi_enable(control, 1); | |
442 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
443 | } else { | |
444 | msix_enable(control); | |
445 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
446 | } | |
447 | if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { | |
448 | /* PCI Express Endpoint device detected */ | |
449 | u16 cmd; | |
450 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
451 | cmd |= PCI_COMMAND_INTX_DISABLE; | |
452 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
453 | } | |
454 | } | |
455 | ||
456 | static void disable_msi_mode(struct pci_dev *dev, int pos, int type) | |
457 | { | |
458 | u16 control; | |
459 | ||
460 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
461 | if (type == PCI_CAP_ID_MSI) { | |
462 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
463 | msi_disable(control); | |
464 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
465 | } else { | |
466 | msix_disable(control); | |
467 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
468 | } | |
469 | if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { | |
470 | /* PCI Express Endpoint device detected */ | |
471 | u16 cmd; | |
472 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
473 | cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
474 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
475 | } | |
476 | } | |
477 | ||
478 | static int msi_lookup_vector(struct pci_dev *dev, int type) | |
479 | { | |
480 | int vector; | |
481 | unsigned long flags; | |
482 | ||
483 | spin_lock_irqsave(&msi_lock, flags); | |
484 | for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) { | |
485 | if (!msi_desc[vector] || msi_desc[vector]->dev != dev || | |
486 | msi_desc[vector]->msi_attrib.type != type || | |
487 | msi_desc[vector]->msi_attrib.default_vector != dev->irq) | |
488 | continue; | |
489 | spin_unlock_irqrestore(&msi_lock, flags); | |
490 | /* This pre-assigned MSI vector for this device | |
491 | already exits. Override dev->irq with this vector */ | |
492 | dev->irq = vector; | |
493 | return 0; | |
494 | } | |
495 | spin_unlock_irqrestore(&msi_lock, flags); | |
496 | ||
497 | return -EACCES; | |
498 | } | |
499 | ||
500 | void pci_scan_msi_device(struct pci_dev *dev) | |
501 | { | |
502 | if (!dev) | |
503 | return; | |
504 | ||
505 | if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0) | |
506 | nr_msix_devices++; | |
507 | else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0) | |
508 | nr_reserved_vectors++; | |
509 | } | |
510 | ||
511 | /** | |
512 | * msi_capability_init - configure device's MSI capability structure | |
513 | * @dev: pointer to the pci_dev data structure of MSI device function | |
514 | * | |
eaae4b3a | 515 | * Setup the MSI capability structure of device function with a single |
1da177e4 LT |
516 | * MSI vector, regardless of device function is capable of handling |
517 | * multiple messages. A return of zero indicates the successful setup | |
518 | * of an entry zero with the new MSI vector or non-zero for otherwise. | |
519 | **/ | |
520 | static int msi_capability_init(struct pci_dev *dev) | |
521 | { | |
522 | struct msi_desc *entry; | |
523 | struct msg_address address; | |
524 | struct msg_data data; | |
525 | int pos, vector; | |
526 | u16 control; | |
527 | ||
528 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
529 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
530 | /* MSI Entry Initialization */ | |
531 | if (!(entry = alloc_msi_entry())) | |
532 | return -ENOMEM; | |
533 | ||
534 | if ((vector = get_msi_vector(dev)) < 0) { | |
535 | kmem_cache_free(msi_cachep, entry); | |
536 | return -EBUSY; | |
537 | } | |
538 | entry->link.head = vector; | |
539 | entry->link.tail = vector; | |
540 | entry->msi_attrib.type = PCI_CAP_ID_MSI; | |
541 | entry->msi_attrib.state = 0; /* Mark it not active */ | |
542 | entry->msi_attrib.entry_nr = 0; | |
543 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
544 | entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */ | |
545 | dev->irq = vector; | |
546 | entry->dev = dev; | |
547 | if (is_mask_bit_support(control)) { | |
548 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
549 | is_64bit_address(control)); | |
550 | } | |
551 | /* Replace with MSI handler */ | |
552 | irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit); | |
553 | /* Configure MSI capability structure */ | |
554 | msi_address_init(&address); | |
555 | msi_data_init(&data, vector); | |
556 | entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >> | |
557 | MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK); | |
558 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
559 | address.lo_address.value); | |
560 | if (is_64bit_address(control)) { | |
561 | pci_write_config_dword(dev, | |
562 | msi_upper_address_reg(pos), address.hi_address); | |
563 | pci_write_config_word(dev, | |
564 | msi_data_reg(pos, 1), *((u32*)&data)); | |
565 | } else | |
566 | pci_write_config_word(dev, | |
567 | msi_data_reg(pos, 0), *((u32*)&data)); | |
568 | if (entry->msi_attrib.maskbit) { | |
569 | unsigned int maskbits, temp; | |
570 | /* All MSIs are unmasked by default, Mask them all */ | |
571 | pci_read_config_dword(dev, | |
572 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
573 | &maskbits); | |
574 | temp = (1 << multi_msi_capable(control)); | |
575 | temp = ((temp - 1) & ~temp); | |
576 | maskbits |= temp; | |
577 | pci_write_config_dword(dev, | |
578 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
579 | maskbits); | |
580 | } | |
581 | attach_msi_entry(entry, vector); | |
582 | /* Set MSI enabled bits */ | |
583 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | /** | |
589 | * msix_capability_init - configure device's MSI-X capability | |
590 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
591 | * | |
eaae4b3a | 592 | * Setup the MSI-X capability structure of device function with a |
1da177e4 LT |
593 | * single MSI-X vector. A return of zero indicates the successful setup of |
594 | * requested MSI-X entries with allocated vectors or non-zero for otherwise. | |
595 | **/ | |
596 | static int msix_capability_init(struct pci_dev *dev, | |
597 | struct msix_entry *entries, int nvec) | |
598 | { | |
599 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
600 | struct msg_address address; | |
601 | struct msg_data data; | |
602 | int vector, pos, i, j, nr_entries, temp = 0; | |
603 | u32 phys_addr, table_offset; | |
604 | u16 control; | |
605 | u8 bir; | |
606 | void __iomem *base; | |
607 | ||
608 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
609 | /* Request & Map MSI-X table region */ | |
610 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
611 | nr_entries = multi_msix_capable(control); | |
612 | pci_read_config_dword(dev, msix_table_offset_reg(pos), | |
613 | &table_offset); | |
614 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
615 | phys_addr = pci_resource_start (dev, bir); | |
616 | phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK); | |
617 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
618 | if (base == NULL) | |
619 | return -ENOMEM; | |
620 | ||
621 | /* MSI-X Table Initialization */ | |
622 | for (i = 0; i < nvec; i++) { | |
623 | entry = alloc_msi_entry(); | |
624 | if (!entry) | |
625 | break; | |
626 | if ((vector = get_msi_vector(dev)) < 0) | |
627 | break; | |
628 | ||
629 | j = entries[i].entry; | |
630 | entries[i].vector = vector; | |
631 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; | |
632 | entry->msi_attrib.state = 0; /* Mark it not active */ | |
633 | entry->msi_attrib.entry_nr = j; | |
634 | entry->msi_attrib.maskbit = 1; | |
635 | entry->msi_attrib.default_vector = dev->irq; | |
636 | entry->dev = dev; | |
637 | entry->mask_base = base; | |
638 | if (!head) { | |
639 | entry->link.head = vector; | |
640 | entry->link.tail = vector; | |
641 | head = entry; | |
642 | } else { | |
643 | entry->link.head = temp; | |
644 | entry->link.tail = tail->link.tail; | |
645 | tail->link.tail = vector; | |
646 | head->link.head = vector; | |
647 | } | |
648 | temp = vector; | |
649 | tail = entry; | |
650 | /* Replace with MSI-X handler */ | |
651 | irq_handler_init(PCI_CAP_ID_MSIX, vector, 1); | |
652 | /* Configure MSI-X capability structure */ | |
653 | msi_address_init(&address); | |
654 | msi_data_init(&data, vector); | |
655 | entry->msi_attrib.current_cpu = | |
656 | ((address.lo_address.u.dest_id >> | |
657 | MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK); | |
658 | writel(address.lo_address.value, | |
659 | base + j * PCI_MSIX_ENTRY_SIZE + | |
660 | PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
661 | writel(address.hi_address, | |
662 | base + j * PCI_MSIX_ENTRY_SIZE + | |
663 | PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
664 | writel(*(u32*)&data, | |
665 | base + j * PCI_MSIX_ENTRY_SIZE + | |
666 | PCI_MSIX_ENTRY_DATA_OFFSET); | |
667 | attach_msi_entry(entry, vector); | |
668 | } | |
669 | if (i != nvec) { | |
670 | i--; | |
671 | for (; i >= 0; i--) { | |
672 | vector = (entries + i)->vector; | |
673 | msi_free_vector(dev, vector, 0); | |
674 | (entries + i)->vector = 0; | |
675 | } | |
676 | return -EBUSY; | |
677 | } | |
678 | /* Set MSI-X enabled bits */ | |
679 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | /** | |
685 | * pci_enable_msi - configure device's MSI capability structure | |
686 | * @dev: pointer to the pci_dev data structure of MSI device function | |
687 | * | |
688 | * Setup the MSI capability structure of device function with | |
689 | * a single MSI vector upon its software driver call to request for | |
690 | * MSI mode enabled on its hardware device function. A return of zero | |
691 | * indicates the successful setup of an entry zero with the new MSI | |
692 | * vector or non-zero for otherwise. | |
693 | **/ | |
694 | int pci_enable_msi(struct pci_dev* dev) | |
695 | { | |
696 | int pos, temp, status = -EINVAL; | |
697 | u16 control; | |
698 | ||
699 | if (!pci_msi_enable || !dev) | |
700 | return status; | |
701 | ||
702 | temp = dev->irq; | |
703 | ||
704 | if ((status = msi_init()) < 0) | |
705 | return status; | |
706 | ||
707 | if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSI))) | |
708 | return -EINVAL; | |
709 | ||
710 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
711 | if (control & PCI_MSI_FLAGS_ENABLE) | |
712 | return 0; /* Already in MSI mode */ | |
713 | ||
714 | if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { | |
715 | /* Lookup Sucess */ | |
716 | unsigned long flags; | |
717 | ||
718 | spin_lock_irqsave(&msi_lock, flags); | |
719 | if (!vector_irq[dev->irq]) { | |
720 | msi_desc[dev->irq]->msi_attrib.state = 0; | |
721 | vector_irq[dev->irq] = -1; | |
722 | nr_released_vectors--; | |
723 | spin_unlock_irqrestore(&msi_lock, flags); | |
724 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
725 | return 0; | |
726 | } | |
727 | spin_unlock_irqrestore(&msi_lock, flags); | |
728 | dev->irq = temp; | |
729 | } | |
730 | /* Check whether driver already requested for MSI-X vectors */ | |
731 | if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 && | |
732 | !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { | |
733 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " | |
734 | "Device already has MSI-X vectors assigned\n", | |
735 | pci_name(dev)); | |
736 | dev->irq = temp; | |
737 | return -EINVAL; | |
738 | } | |
739 | status = msi_capability_init(dev); | |
740 | if (!status) { | |
741 | if (!pos) | |
742 | nr_reserved_vectors--; /* Only MSI capable */ | |
743 | else if (nr_msix_devices > 0) | |
744 | nr_msix_devices--; /* Both MSI and MSI-X capable, | |
745 | but choose enabling MSI */ | |
746 | } | |
747 | ||
748 | return status; | |
749 | } | |
750 | ||
751 | void pci_disable_msi(struct pci_dev* dev) | |
752 | { | |
753 | struct msi_desc *entry; | |
754 | int pos, default_vector; | |
755 | u16 control; | |
756 | unsigned long flags; | |
757 | ||
758 | if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSI))) | |
759 | return; | |
760 | ||
761 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
762 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
763 | return; | |
764 | ||
765 | spin_lock_irqsave(&msi_lock, flags); | |
766 | entry = msi_desc[dev->irq]; | |
767 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { | |
768 | spin_unlock_irqrestore(&msi_lock, flags); | |
769 | return; | |
770 | } | |
771 | if (entry->msi_attrib.state) { | |
772 | spin_unlock_irqrestore(&msi_lock, flags); | |
773 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " | |
774 | "free_irq() on MSI vector %d\n", | |
775 | pci_name(dev), dev->irq); | |
776 | BUG_ON(entry->msi_attrib.state > 0); | |
777 | } else { | |
778 | vector_irq[dev->irq] = 0; /* free it */ | |
779 | nr_released_vectors++; | |
780 | default_vector = entry->msi_attrib.default_vector; | |
781 | spin_unlock_irqrestore(&msi_lock, flags); | |
782 | /* Restore dev->irq to its default pin-assertion vector */ | |
783 | dev->irq = default_vector; | |
784 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), | |
785 | PCI_CAP_ID_MSI); | |
786 | } | |
787 | } | |
788 | ||
1da177e4 LT |
789 | static int msi_free_vector(struct pci_dev* dev, int vector, int reassign) |
790 | { | |
791 | struct msi_desc *entry; | |
792 | int head, entry_nr, type; | |
793 | void __iomem *base; | |
794 | unsigned long flags; | |
795 | ||
796 | spin_lock_irqsave(&msi_lock, flags); | |
797 | entry = msi_desc[vector]; | |
798 | if (!entry || entry->dev != dev) { | |
799 | spin_unlock_irqrestore(&msi_lock, flags); | |
800 | return -EINVAL; | |
801 | } | |
802 | type = entry->msi_attrib.type; | |
803 | entry_nr = entry->msi_attrib.entry_nr; | |
804 | head = entry->link.head; | |
805 | base = entry->mask_base; | |
806 | msi_desc[entry->link.head]->link.tail = entry->link.tail; | |
807 | msi_desc[entry->link.tail]->link.head = entry->link.head; | |
808 | entry->dev = NULL; | |
809 | if (!reassign) { | |
810 | vector_irq[vector] = 0; | |
811 | nr_released_vectors++; | |
812 | } | |
813 | msi_desc[vector] = NULL; | |
814 | spin_unlock_irqrestore(&msi_lock, flags); | |
815 | ||
816 | kmem_cache_free(msi_cachep, entry); | |
817 | ||
818 | if (type == PCI_CAP_ID_MSIX) { | |
819 | if (!reassign) | |
820 | writel(1, base + | |
821 | entry_nr * PCI_MSIX_ENTRY_SIZE + | |
822 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
823 | ||
824 | if (head == vector) { | |
825 | /* | |
826 | * Detect last MSI-X vector to be released. | |
827 | * Release the MSI-X memory-mapped table. | |
828 | */ | |
829 | int pos, nr_entries; | |
830 | u32 phys_addr, table_offset; | |
831 | u16 control; | |
832 | u8 bir; | |
833 | ||
834 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
835 | pci_read_config_word(dev, msi_control_reg(pos), | |
836 | &control); | |
837 | nr_entries = multi_msix_capable(control); | |
838 | pci_read_config_dword(dev, msix_table_offset_reg(pos), | |
839 | &table_offset); | |
840 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
841 | phys_addr = pci_resource_start (dev, bir); | |
842 | phys_addr += (u32)(table_offset & | |
843 | ~PCI_MSIX_FLAGS_BIRMASK); | |
844 | iounmap(base); | |
845 | } | |
846 | } | |
847 | ||
848 | return 0; | |
849 | } | |
850 | ||
851 | static int reroute_msix_table(int head, struct msix_entry *entries, int *nvec) | |
852 | { | |
853 | int vector = head, tail = 0; | |
854 | int i, j = 0, nr_entries = 0; | |
855 | void __iomem *base; | |
856 | unsigned long flags; | |
857 | ||
858 | spin_lock_irqsave(&msi_lock, flags); | |
859 | while (head != tail) { | |
860 | nr_entries++; | |
861 | tail = msi_desc[vector]->link.tail; | |
862 | if (entries[0].entry == msi_desc[vector]->msi_attrib.entry_nr) | |
863 | j = vector; | |
864 | vector = tail; | |
865 | } | |
866 | if (*nvec > nr_entries) { | |
867 | spin_unlock_irqrestore(&msi_lock, flags); | |
868 | *nvec = nr_entries; | |
869 | return -EINVAL; | |
870 | } | |
871 | vector = ((j > 0) ? j : head); | |
872 | for (i = 0; i < *nvec; i++) { | |
873 | j = msi_desc[vector]->msi_attrib.entry_nr; | |
874 | msi_desc[vector]->msi_attrib.state = 0; /* Mark it not active */ | |
875 | vector_irq[vector] = -1; /* Mark it busy */ | |
876 | nr_released_vectors--; | |
877 | entries[i].vector = vector; | |
878 | if (j != (entries + i)->entry) { | |
879 | base = msi_desc[vector]->mask_base; | |
880 | msi_desc[vector]->msi_attrib.entry_nr = | |
881 | (entries + i)->entry; | |
882 | writel( readl(base + j * PCI_MSIX_ENTRY_SIZE + | |
883 | PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET), base + | |
884 | (entries + i)->entry * PCI_MSIX_ENTRY_SIZE + | |
885 | PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
886 | writel( readl(base + j * PCI_MSIX_ENTRY_SIZE + | |
887 | PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET), base + | |
888 | (entries + i)->entry * PCI_MSIX_ENTRY_SIZE + | |
889 | PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
890 | writel( (readl(base + j * PCI_MSIX_ENTRY_SIZE + | |
891 | PCI_MSIX_ENTRY_DATA_OFFSET) & 0xff00) | vector, | |
892 | base + (entries+i)->entry*PCI_MSIX_ENTRY_SIZE + | |
893 | PCI_MSIX_ENTRY_DATA_OFFSET); | |
894 | } | |
895 | vector = msi_desc[vector]->link.tail; | |
896 | } | |
897 | spin_unlock_irqrestore(&msi_lock, flags); | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
902 | /** | |
903 | * pci_enable_msix - configure device's MSI-X capability structure | |
904 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 905 | * @entries: pointer to an array of MSI-X entries |
1da177e4 LT |
906 | * @nvec: number of MSI-X vectors requested for allocation by device driver |
907 | * | |
908 | * Setup the MSI-X capability structure of device function with the number | |
909 | * of requested vectors upon its software driver call to request for | |
910 | * MSI-X mode enabled on its hardware device function. A return of zero | |
911 | * indicates the successful configuration of MSI-X capability structure | |
912 | * with new allocated MSI-X vectors. A return of < 0 indicates a failure. | |
913 | * Or a return of > 0 indicates that driver request is exceeding the number | |
914 | * of vectors available. Driver should use the returned value to re-send | |
915 | * its request. | |
916 | **/ | |
917 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
918 | { | |
919 | int status, pos, nr_entries, free_vectors; | |
920 | int i, j, temp; | |
921 | u16 control; | |
922 | unsigned long flags; | |
923 | ||
924 | if (!pci_msi_enable || !dev || !entries) | |
925 | return -EINVAL; | |
926 | ||
927 | if ((status = msi_init()) < 0) | |
928 | return status; | |
929 | ||
930 | if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX))) | |
931 | return -EINVAL; | |
932 | ||
933 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
934 | if (control & PCI_MSIX_FLAGS_ENABLE) | |
935 | return -EINVAL; /* Already in MSI-X mode */ | |
936 | ||
937 | nr_entries = multi_msix_capable(control); | |
938 | if (nvec > nr_entries) | |
939 | return -EINVAL; | |
940 | ||
941 | /* Check for any invalid entries */ | |
942 | for (i = 0; i < nvec; i++) { | |
943 | if (entries[i].entry >= nr_entries) | |
944 | return -EINVAL; /* invalid entry */ | |
945 | for (j = i + 1; j < nvec; j++) { | |
946 | if (entries[i].entry == entries[j].entry) | |
947 | return -EINVAL; /* duplicate entry */ | |
948 | } | |
949 | } | |
950 | temp = dev->irq; | |
951 | if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { | |
952 | /* Lookup Sucess */ | |
953 | nr_entries = nvec; | |
954 | /* Reroute MSI-X table */ | |
955 | if (reroute_msix_table(dev->irq, entries, &nr_entries)) { | |
956 | /* #requested > #previous-assigned */ | |
957 | dev->irq = temp; | |
958 | return nr_entries; | |
959 | } | |
960 | dev->irq = temp; | |
961 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
962 | return 0; | |
963 | } | |
964 | /* Check whether driver already requested for MSI vector */ | |
965 | if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && | |
966 | !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { | |
967 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " | |
968 | "Device already has an MSI vector assigned\n", | |
969 | pci_name(dev)); | |
970 | dev->irq = temp; | |
971 | return -EINVAL; | |
972 | } | |
973 | ||
974 | spin_lock_irqsave(&msi_lock, flags); | |
975 | /* | |
976 | * msi_lock is provided to ensure that enough vectors resources are | |
977 | * available before granting. | |
978 | */ | |
979 | free_vectors = pci_vector_resources(last_alloc_vector, | |
980 | nr_released_vectors); | |
981 | /* Ensure that each MSI/MSI-X device has one vector reserved by | |
982 | default to avoid any MSI-X driver to take all available | |
983 | resources */ | |
984 | free_vectors -= nr_reserved_vectors; | |
985 | /* Find the average of free vectors among MSI-X devices */ | |
986 | if (nr_msix_devices > 0) | |
987 | free_vectors /= nr_msix_devices; | |
988 | spin_unlock_irqrestore(&msi_lock, flags); | |
989 | ||
990 | if (nvec > free_vectors) { | |
991 | if (free_vectors > 0) | |
992 | return free_vectors; | |
993 | else | |
994 | return -EBUSY; | |
995 | } | |
996 | ||
997 | status = msix_capability_init(dev, entries, nvec); | |
998 | if (!status && nr_msix_devices > 0) | |
999 | nr_msix_devices--; | |
1000 | ||
1001 | return status; | |
1002 | } | |
1003 | ||
1004 | void pci_disable_msix(struct pci_dev* dev) | |
1005 | { | |
1006 | int pos, temp; | |
1007 | u16 control; | |
1008 | ||
1009 | if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX))) | |
1010 | return; | |
1011 | ||
1012 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1013 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
1014 | return; | |
1015 | ||
1016 | temp = dev->irq; | |
1017 | if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { | |
1018 | int state, vector, head, tail = 0, warning = 0; | |
1019 | unsigned long flags; | |
1020 | ||
1021 | vector = head = dev->irq; | |
1022 | spin_lock_irqsave(&msi_lock, flags); | |
1023 | while (head != tail) { | |
1024 | state = msi_desc[vector]->msi_attrib.state; | |
1025 | if (state) | |
1026 | warning = 1; | |
1027 | else { | |
1028 | vector_irq[vector] = 0; /* free it */ | |
1029 | nr_released_vectors++; | |
1030 | } | |
1031 | tail = msi_desc[vector]->link.tail; | |
1032 | vector = tail; | |
1033 | } | |
1034 | spin_unlock_irqrestore(&msi_lock, flags); | |
1035 | if (warning) { | |
1036 | dev->irq = temp; | |
1037 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " | |
1038 | "free_irq() on all MSI-X vectors\n", | |
1039 | pci_name(dev)); | |
1040 | BUG_ON(warning > 0); | |
1041 | } else { | |
1042 | dev->irq = temp; | |
1043 | disable_msi_mode(dev, | |
1044 | pci_find_capability(dev, PCI_CAP_ID_MSIX), | |
1045 | PCI_CAP_ID_MSIX); | |
1046 | ||
1047 | } | |
1048 | } | |
1049 | } | |
1050 | ||
1051 | /** | |
1052 | * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state | |
1053 | * @dev: pointer to the pci_dev data structure of MSI(X) device function | |
1054 | * | |
eaae4b3a | 1055 | * Being called during hotplug remove, from which the device function |
1da177e4 LT |
1056 | * is hot-removed. All previous assigned MSI/MSI-X vectors, if |
1057 | * allocated for this device function, are reclaimed to unused state, | |
1058 | * which may be used later on. | |
1059 | **/ | |
1060 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
1061 | { | |
1062 | int state, pos, temp; | |
1063 | unsigned long flags; | |
1064 | ||
1065 | if (!pci_msi_enable || !dev) | |
1066 | return; | |
1067 | ||
1068 | temp = dev->irq; /* Save IOAPIC IRQ */ | |
1069 | if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSI)) > 0 && | |
1070 | !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) { | |
1071 | spin_lock_irqsave(&msi_lock, flags); | |
1072 | state = msi_desc[dev->irq]->msi_attrib.state; | |
1073 | spin_unlock_irqrestore(&msi_lock, flags); | |
1074 | if (state) { | |
1075 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1076 | "called without free_irq() on MSI vector %d\n", | |
1077 | pci_name(dev), dev->irq); | |
1078 | BUG_ON(state > 0); | |
1079 | } else /* Release MSI vector assigned to this device */ | |
1080 | msi_free_vector(dev, dev->irq, 0); | |
1081 | dev->irq = temp; /* Restore IOAPIC IRQ */ | |
1082 | } | |
1083 | if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 && | |
1084 | !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) { | |
1085 | int vector, head, tail = 0, warning = 0; | |
1086 | void __iomem *base = NULL; | |
1087 | ||
1088 | vector = head = dev->irq; | |
1089 | while (head != tail) { | |
1090 | spin_lock_irqsave(&msi_lock, flags); | |
1091 | state = msi_desc[vector]->msi_attrib.state; | |
1092 | tail = msi_desc[vector]->link.tail; | |
1093 | base = msi_desc[vector]->mask_base; | |
1094 | spin_unlock_irqrestore(&msi_lock, flags); | |
1095 | if (state) | |
1096 | warning = 1; | |
1097 | else if (vector != head) /* Release MSI-X vector */ | |
1098 | msi_free_vector(dev, vector, 0); | |
1099 | vector = tail; | |
1100 | } | |
1101 | msi_free_vector(dev, vector, 0); | |
1102 | if (warning) { | |
1103 | /* Force to release the MSI-X memory-mapped table */ | |
1104 | u32 phys_addr, table_offset; | |
1105 | u16 control; | |
1106 | u8 bir; | |
1107 | ||
1108 | pci_read_config_word(dev, msi_control_reg(pos), | |
1109 | &control); | |
1110 | pci_read_config_dword(dev, msix_table_offset_reg(pos), | |
1111 | &table_offset); | |
1112 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
1113 | phys_addr = pci_resource_start (dev, bir); | |
1114 | phys_addr += (u32)(table_offset & | |
1115 | ~PCI_MSIX_FLAGS_BIRMASK); | |
1116 | iounmap(base); | |
1117 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1118 | "called without free_irq() on all MSI-X vectors\n", | |
1119 | pci_name(dev)); | |
1120 | BUG_ON(warning > 0); | |
1121 | } | |
1122 | dev->irq = temp; /* Restore IOAPIC IRQ */ | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | EXPORT_SYMBOL(pci_enable_msi); | |
1127 | EXPORT_SYMBOL(pci_disable_msi); | |
1128 | EXPORT_SYMBOL(pci_enable_msix); | |
1129 | EXPORT_SYMBOL(pci_disable_msix); |