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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
aff17164 | 7 | * Copyright (C) 2016 Christoph Hellwig. |
1da177e4 LT |
8 | */ |
9 | ||
1ce03373 | 10 | #include <linux/err.h> |
1da177e4 LT |
11 | #include <linux/mm.h> |
12 | #include <linux/irq.h> | |
13 | #include <linux/interrupt.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
be2021ba | 22 | #include <linux/acpi_iort.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
3878eaef | 24 | #include <linux/irqdomain.h> |
b6eec9b7 | 25 | #include <linux/of_irq.h> |
1da177e4 LT |
26 | |
27 | #include "pci.h" | |
1da177e4 | 28 | |
1da177e4 | 29 | static int pci_msi_enable = 1; |
38737d82 | 30 | int pci_msi_ignore_mask; |
1da177e4 | 31 | |
527eee29 BH |
32 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
33 | ||
8e047ada JL |
34 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
35 | static struct irq_domain *pci_msi_default_domain; | |
36 | static DEFINE_MUTEX(pci_msi_domain_lock); | |
37 | ||
38 | struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev) | |
39 | { | |
40 | return pci_msi_default_domain; | |
41 | } | |
42 | ||
020c3126 MZ |
43 | static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev) |
44 | { | |
d8a1cb75 | 45 | struct irq_domain *domain; |
020c3126 | 46 | |
d8a1cb75 MZ |
47 | domain = dev_get_msi_domain(&dev->dev); |
48 | if (domain) | |
49 | return domain; | |
020c3126 | 50 | |
d8a1cb75 | 51 | return arch_get_pci_msi_domain(dev); |
020c3126 MZ |
52 | } |
53 | ||
8e047ada JL |
54 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
55 | { | |
56 | struct irq_domain *domain; | |
57 | ||
020c3126 | 58 | domain = pci_msi_get_domain(dev); |
3845d295 | 59 | if (domain && irq_domain_is_hierarchy(domain)) |
8e047ada JL |
60 | return pci_msi_domain_alloc_irqs(domain, dev, nvec, type); |
61 | ||
62 | return arch_setup_msi_irqs(dev, nvec, type); | |
63 | } | |
64 | ||
65 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
66 | { | |
67 | struct irq_domain *domain; | |
68 | ||
020c3126 | 69 | domain = pci_msi_get_domain(dev); |
3845d295 | 70 | if (domain && irq_domain_is_hierarchy(domain)) |
8e047ada JL |
71 | pci_msi_domain_free_irqs(domain, dev); |
72 | else | |
73 | arch_teardown_msi_irqs(dev); | |
74 | } | |
75 | #else | |
76 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
77 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
78 | #endif | |
527eee29 | 79 | |
6a9e7f20 AB |
80 | /* Arch hooks */ |
81 | ||
4287d824 TP |
82 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
83 | { | |
2291ec09 | 84 | struct msi_controller *chip = dev->bus->msi; |
0cbdcfcf TR |
85 | int err; |
86 | ||
87 | if (!chip || !chip->setup_irq) | |
88 | return -EINVAL; | |
89 | ||
90 | err = chip->setup_irq(chip, dev, desc); | |
91 | if (err < 0) | |
92 | return err; | |
93 | ||
94 | irq_set_chip_data(desc->irq, chip); | |
95 | ||
96 | return 0; | |
4287d824 TP |
97 | } |
98 | ||
99 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 100 | { |
c2791b80 | 101 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
102 | |
103 | if (!chip || !chip->teardown_irq) | |
104 | return; | |
105 | ||
106 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
107 | } |
108 | ||
4287d824 | 109 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 | 110 | { |
339e5b44 | 111 | struct msi_controller *chip = dev->bus->msi; |
6a9e7f20 AB |
112 | struct msi_desc *entry; |
113 | int ret; | |
114 | ||
339e5b44 LS |
115 | if (chip && chip->setup_irqs) |
116 | return chip->setup_irqs(chip, dev, nvec, type); | |
1c8d7b0a MW |
117 | /* |
118 | * If an architecture wants to support multiple MSI, it needs to | |
119 | * override arch_setup_msi_irqs() | |
120 | */ | |
121 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
122 | return 1; | |
123 | ||
5004e98a | 124 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 125 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 126 | if (ret < 0) |
6a9e7f20 | 127 | return ret; |
b5fbf533 ME |
128 | if (ret > 0) |
129 | return -ENOSPC; | |
6a9e7f20 AB |
130 | } |
131 | ||
132 | return 0; | |
133 | } | |
1525bf0d | 134 | |
4287d824 TP |
135 | /* |
136 | * We have a default implementation available as a separate non-weak | |
137 | * function, as it is used by the Xen x86 PCI code | |
138 | */ | |
1525bf0d | 139 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 140 | { |
63a7b17e | 141 | int i; |
6a9e7f20 AB |
142 | struct msi_desc *entry; |
143 | ||
5004e98a | 144 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
145 | if (entry->irq) |
146 | for (i = 0; i < entry->nvec_used; i++) | |
147 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
148 | } |
149 | ||
4287d824 TP |
150 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
151 | { | |
152 | return default_teardown_msi_irqs(dev); | |
153 | } | |
76ccc297 | 154 | |
ac8344c4 | 155 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
156 | { |
157 | struct msi_desc *entry; | |
158 | ||
159 | entry = NULL; | |
160 | if (dev->msix_enabled) { | |
5004e98a | 161 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
162 | if (irq == entry->irq) |
163 | break; | |
164 | } | |
165 | } else if (dev->msi_enabled) { | |
166 | entry = irq_get_msi_desc(irq); | |
167 | } | |
168 | ||
169 | if (entry) | |
83a18912 | 170 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 171 | } |
4287d824 | 172 | |
ac8344c4 | 173 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 174 | { |
ac8344c4 | 175 | return default_restore_msi_irqs(dev); |
4287d824 | 176 | } |
76ccc297 | 177 | |
bffac3c5 MW |
178 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
179 | { | |
0b49ec37 MW |
180 | /* Don't shift by >= width of type */ |
181 | if (x >= 5) | |
182 | return 0xffffffff; | |
183 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
184 | } |
185 | ||
ce6fce42 MW |
186 | /* |
187 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
188 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
189 | * reliably as devices without an INTx disable bit will then generate a | |
190 | * level IRQ which will never be cleared. | |
ce6fce42 | 191 | */ |
23ed8d57 | 192 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 193 | { |
f2440d9a | 194 | u32 mask_bits = desc->masked; |
1da177e4 | 195 | |
38737d82 | 196 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 197 | return 0; |
f2440d9a MW |
198 | |
199 | mask_bits &= ~mask; | |
200 | mask_bits |= flag; | |
e39758e0 JL |
201 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
202 | mask_bits); | |
12abb8ba HS |
203 | |
204 | return mask_bits; | |
205 | } | |
206 | ||
207 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
208 | { | |
23ed8d57 | 209 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
210 | } |
211 | ||
5eb6d660 CH |
212 | static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) |
213 | { | |
214 | return desc->mask_base + | |
215 | desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
216 | } | |
217 | ||
f2440d9a MW |
218 | /* |
219 | * This internal function does not flush PCI writes to the device. | |
220 | * All users must ensure that they read from the device before either | |
221 | * assuming that the device state is up to date, or returning out of this | |
222 | * file. This saves a few milliseconds when initialising devices with lots | |
223 | * of MSI-X interrupts. | |
224 | */ | |
23ed8d57 | 225 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
226 | { |
227 | u32 mask_bits = desc->masked; | |
38737d82 YW |
228 | |
229 | if (pci_msi_ignore_mask) | |
230 | return 0; | |
231 | ||
8d805286 SY |
232 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
233 | if (flag) | |
234 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
5eb6d660 | 235 | writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL); |
12abb8ba HS |
236 | |
237 | return mask_bits; | |
238 | } | |
239 | ||
240 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
241 | { | |
23ed8d57 | 242 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 243 | } |
24d27553 | 244 | |
1c9db525 | 245 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 246 | { |
c391f262 | 247 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
24d27553 | 248 | |
f2440d9a MW |
249 | if (desc->msi_attrib.is_msix) { |
250 | msix_mask_irq(desc, flag); | |
251 | readl(desc->mask_base); /* Flush write to device */ | |
252 | } else { | |
a281b788 | 253 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 254 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 255 | } |
f2440d9a MW |
256 | } |
257 | ||
23ed8d57 TG |
258 | /** |
259 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts | |
260 | * @data: pointer to irqdata associated to that interrupt | |
261 | */ | |
262 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 263 | { |
1c9db525 | 264 | msi_set_mask_bit(data, 1); |
f2440d9a | 265 | } |
a4289dc2 | 266 | EXPORT_SYMBOL_GPL(pci_msi_mask_irq); |
f2440d9a | 267 | |
23ed8d57 TG |
268 | /** |
269 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts | |
270 | * @data: pointer to irqdata associated to that interrupt | |
271 | */ | |
272 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 273 | { |
1c9db525 | 274 | msi_set_mask_bit(data, 0); |
1da177e4 | 275 | } |
a4289dc2 | 276 | EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); |
1da177e4 | 277 | |
ac8344c4 D |
278 | void default_restore_msi_irqs(struct pci_dev *dev) |
279 | { | |
280 | struct msi_desc *entry; | |
281 | ||
5004e98a | 282 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 283 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
284 | } |
285 | ||
891d4a48 | 286 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 287 | { |
e39758e0 JL |
288 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
289 | ||
290 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
291 | |
292 | if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 293 | void __iomem *base = pci_msix_desc_addr(entry); |
30da5524 BH |
294 | |
295 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
296 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
297 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
298 | } else { | |
f5322169 | 299 | int pos = dev->msi_cap; |
30da5524 BH |
300 | u16 data; |
301 | ||
9925ad0c BH |
302 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
303 | &msg->address_lo); | |
30da5524 | 304 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
305 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
306 | &msg->address_hi); | |
2f221349 | 307 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
308 | } else { |
309 | msg->address_hi = 0; | |
2f221349 | 310 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
311 | } |
312 | msg->data = data; | |
313 | } | |
314 | } | |
315 | ||
83a18912 | 316 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 317 | { |
e39758e0 JL |
318 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
319 | ||
320 | if (dev->current_state != PCI_D0) { | |
fcd097f3 BH |
321 | /* Don't touch the hardware now */ |
322 | } else if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 323 | void __iomem *base = pci_msix_desc_addr(entry); |
24d27553 | 324 | |
2c21fd4b HS |
325 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
326 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
327 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 328 | } else { |
f5322169 | 329 | int pos = dev->msi_cap; |
1c8d7b0a MW |
330 | u16 msgctl; |
331 | ||
f84ecd28 | 332 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
333 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
334 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 335 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 336 | |
9925ad0c BH |
337 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
338 | msg->address_lo); | |
0366f8f7 | 339 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
340 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
341 | msg->address_hi); | |
2f221349 BH |
342 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
343 | msg->data); | |
0366f8f7 | 344 | } else { |
2f221349 BH |
345 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
346 | msg->data); | |
0366f8f7 | 347 | } |
1da177e4 | 348 | } |
392ee1e6 | 349 | entry->msg = *msg; |
1da177e4 | 350 | } |
0366f8f7 | 351 | |
83a18912 | 352 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 353 | { |
dced35ae | 354 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 355 | |
83a18912 | 356 | __pci_write_msi_msg(entry, msg); |
3145e941 | 357 | } |
83a18912 | 358 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 359 | |
f56e4481 HS |
360 | static void free_msi_irqs(struct pci_dev *dev) |
361 | { | |
5004e98a | 362 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 363 | struct msi_desc *entry, *tmp; |
1c51b50c GKH |
364 | struct attribute **msi_attrs; |
365 | struct device_attribute *dev_attr; | |
63a7b17e | 366 | int i, count = 0; |
f56e4481 | 367 | |
5004e98a | 368 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
369 | if (entry->irq) |
370 | for (i = 0; i < entry->nvec_used; i++) | |
371 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 372 | |
8e047ada | 373 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 374 | |
5004e98a | 375 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 376 | if (entry->msi_attrib.is_msix) { |
5004e98a | 377 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
378 | iounmap(entry->mask_base); |
379 | } | |
424eb391 | 380 | |
f56e4481 HS |
381 | list_del(&entry->list); |
382 | kfree(entry); | |
383 | } | |
1c51b50c GKH |
384 | |
385 | if (dev->msi_irq_groups) { | |
386 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
387 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 388 | while (msi_attrs[count]) { |
1c51b50c GKH |
389 | dev_attr = container_of(msi_attrs[count], |
390 | struct device_attribute, attr); | |
391 | kfree(dev_attr->attr.name); | |
392 | kfree(dev_attr); | |
393 | ++count; | |
394 | } | |
395 | kfree(msi_attrs); | |
396 | kfree(dev->msi_irq_groups[0]); | |
397 | kfree(dev->msi_irq_groups); | |
398 | dev->msi_irq_groups = NULL; | |
399 | } | |
f56e4481 | 400 | } |
c54c1879 | 401 | |
ba698ad4 DM |
402 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
403 | { | |
404 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
405 | pci_intx(dev, enable); | |
406 | } | |
407 | ||
8fed4b65 | 408 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 409 | { |
41017f0c | 410 | u16 control; |
392ee1e6 | 411 | struct msi_desc *entry; |
41017f0c | 412 | |
b1cbf4e4 EB |
413 | if (!dev->msi_enabled) |
414 | return; | |
415 | ||
dced35ae | 416 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 417 | |
ba698ad4 | 418 | pci_intx_for_msi(dev, 0); |
61b64abd | 419 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 420 | arch_restore_msi_irqs(dev); |
392ee1e6 | 421 | |
f5322169 | 422 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
423 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
424 | entry->masked); | |
abad2ec9 | 425 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 426 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 427 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
428 | } |
429 | ||
430 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 431 | { |
41017f0c | 432 | struct msi_desc *entry; |
41017f0c | 433 | |
ded86d8d EB |
434 | if (!dev->msix_enabled) |
435 | return; | |
5004e98a | 436 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 437 | |
41017f0c | 438 | /* route the table */ |
ba698ad4 | 439 | pci_intx_for_msi(dev, 0); |
61b64abd | 440 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 441 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 442 | |
ac8344c4 | 443 | arch_restore_msi_irqs(dev); |
5004e98a | 444 | for_each_pci_msi_entry(entry, dev) |
f2440d9a | 445 | msix_mask_irq(entry, entry->masked); |
41017f0c | 446 | |
61b64abd | 447 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 448 | } |
8fed4b65 ME |
449 | |
450 | void pci_restore_msi_state(struct pci_dev *dev) | |
451 | { | |
452 | __pci_restore_msi_state(dev); | |
453 | __pci_restore_msix_state(dev); | |
454 | } | |
94688cf2 | 455 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 456 | |
1c51b50c | 457 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
458 | char *buf) |
459 | { | |
1c51b50c GKH |
460 | struct msi_desc *entry; |
461 | unsigned long irq; | |
462 | int retval; | |
da8d1c8b | 463 | |
1c51b50c GKH |
464 | retval = kstrtoul(attr->attr.name, 10, &irq); |
465 | if (retval) | |
466 | return retval; | |
da8d1c8b | 467 | |
e11ece5a YW |
468 | entry = irq_get_msi_desc(irq); |
469 | if (entry) | |
470 | return sprintf(buf, "%s\n", | |
471 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
472 | ||
1c51b50c | 473 | return -ENODEV; |
da8d1c8b NH |
474 | } |
475 | ||
da8d1c8b NH |
476 | static int populate_msi_sysfs(struct pci_dev *pdev) |
477 | { | |
1c51b50c GKH |
478 | struct attribute **msi_attrs; |
479 | struct attribute *msi_attr; | |
480 | struct device_attribute *msi_dev_attr; | |
481 | struct attribute_group *msi_irq_group; | |
482 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 483 | struct msi_desc *entry; |
1c51b50c GKH |
484 | int ret = -ENOMEM; |
485 | int num_msi = 0; | |
da8d1c8b | 486 | int count = 0; |
a8676066 | 487 | int i; |
da8d1c8b | 488 | |
1c51b50c | 489 | /* Determine how many msi entries we have */ |
5004e98a | 490 | for_each_pci_msi_entry(entry, pdev) |
a8676066 | 491 | num_msi += entry->nvec_used; |
1c51b50c GKH |
492 | if (!num_msi) |
493 | return 0; | |
da8d1c8b | 494 | |
1c51b50c GKH |
495 | /* Dynamically create the MSI attributes for the PCI device */ |
496 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
497 | if (!msi_attrs) | |
498 | return -ENOMEM; | |
5004e98a | 499 | for_each_pci_msi_entry(entry, pdev) { |
a8676066 RB |
500 | for (i = 0; i < entry->nvec_used; i++) { |
501 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); | |
502 | if (!msi_dev_attr) | |
503 | goto error_attrs; | |
504 | msi_attrs[count] = &msi_dev_attr->attr; | |
505 | ||
506 | sysfs_attr_init(&msi_dev_attr->attr); | |
507 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", | |
508 | entry->irq + i); | |
509 | if (!msi_dev_attr->attr.name) | |
510 | goto error_attrs; | |
511 | msi_dev_attr->attr.mode = S_IRUGO; | |
512 | msi_dev_attr->show = msi_mode_show; | |
513 | ++count; | |
514 | } | |
da8d1c8b NH |
515 | } |
516 | ||
1c51b50c GKH |
517 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
518 | if (!msi_irq_group) | |
519 | goto error_attrs; | |
520 | msi_irq_group->name = "msi_irqs"; | |
521 | msi_irq_group->attrs = msi_attrs; | |
522 | ||
523 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
524 | if (!msi_irq_groups) | |
525 | goto error_irq_group; | |
526 | msi_irq_groups[0] = msi_irq_group; | |
527 | ||
528 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
529 | if (ret) | |
530 | goto error_irq_groups; | |
531 | pdev->msi_irq_groups = msi_irq_groups; | |
532 | ||
da8d1c8b NH |
533 | return 0; |
534 | ||
1c51b50c GKH |
535 | error_irq_groups: |
536 | kfree(msi_irq_groups); | |
537 | error_irq_group: | |
538 | kfree(msi_irq_group); | |
539 | error_attrs: | |
540 | count = 0; | |
541 | msi_attr = msi_attrs[count]; | |
542 | while (msi_attr) { | |
543 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
544 | kfree(msi_attr->name); | |
545 | kfree(msi_dev_attr); | |
546 | ++count; | |
547 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 548 | } |
29237756 | 549 | kfree(msi_attrs); |
da8d1c8b NH |
550 | return ret; |
551 | } | |
552 | ||
e75eafb9 TG |
553 | static struct msi_desc * |
554 | msi_setup_entry(struct pci_dev *dev, int nvec, bool affinity) | |
d873b4d4 | 555 | { |
e75eafb9 | 556 | struct cpumask *masks = NULL; |
d873b4d4 | 557 | struct msi_desc *entry; |
e75eafb9 TG |
558 | u16 control; |
559 | ||
560 | if (affinity) { | |
561 | masks = irq_create_affinity_masks(dev->irq_affinity, nvec); | |
562 | if (!masks) | |
563 | pr_err("Unable to allocate affinity masks, ignoring\n"); | |
564 | } | |
d873b4d4 YW |
565 | |
566 | /* MSI Entry Initialization */ | |
e75eafb9 | 567 | entry = alloc_msi_entry(&dev->dev, nvec, masks); |
d873b4d4 | 568 | if (!entry) |
e75eafb9 | 569 | goto out; |
d873b4d4 YW |
570 | |
571 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
572 | ||
573 | entry->msi_attrib.is_msix = 0; | |
574 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
575 | entry->msi_attrib.entry_nr = 0; | |
576 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
577 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 578 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e | 579 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
d873b4d4 YW |
580 | |
581 | if (control & PCI_MSI_FLAGS_64BIT) | |
582 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
583 | else | |
584 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
585 | ||
586 | /* Save the initial mask status */ | |
587 | if (entry->msi_attrib.maskbit) | |
588 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
589 | ||
e75eafb9 TG |
590 | out: |
591 | kfree(masks); | |
d873b4d4 YW |
592 | return entry; |
593 | } | |
594 | ||
f144d149 BH |
595 | static int msi_verify_entries(struct pci_dev *dev) |
596 | { | |
597 | struct msi_desc *entry; | |
598 | ||
5004e98a | 599 | for_each_pci_msi_entry(entry, dev) { |
f144d149 BH |
600 | if (!dev->no_64bit_msi || !entry->msg.address_hi) |
601 | continue; | |
602 | dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" | |
603 | " tried to assign one above 4G\n"); | |
604 | return -EIO; | |
605 | } | |
606 | return 0; | |
607 | } | |
608 | ||
1da177e4 LT |
609 | /** |
610 | * msi_capability_init - configure device's MSI capability structure | |
611 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 612 | * @nvec: number of interrupts to allocate |
1da177e4 | 613 | * |
1c8d7b0a MW |
614 | * Setup the MSI capability structure of the device with the requested |
615 | * number of interrupts. A return value of zero indicates the successful | |
616 | * setup of an entry with the new MSI irq. A negative return value indicates | |
617 | * an error, and a positive return value indicates the number of interrupts | |
618 | * which could have been allocated. | |
619 | */ | |
e75eafb9 | 620 | static int msi_capability_init(struct pci_dev *dev, int nvec, bool affinity) |
1da177e4 LT |
621 | { |
622 | struct msi_desc *entry; | |
f465136d | 623 | int ret; |
f2440d9a | 624 | unsigned mask; |
1da177e4 | 625 | |
61b64abd | 626 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 627 | |
e75eafb9 | 628 | entry = msi_setup_entry(dev, nvec, affinity); |
f7feaca7 EB |
629 | if (!entry) |
630 | return -ENOMEM; | |
1ce03373 | 631 | |
f2440d9a | 632 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 633 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
634 | msi_mask_irq(entry, mask, mask); |
635 | ||
5004e98a | 636 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 637 | |
1da177e4 | 638 | /* Configure MSI capability structure */ |
8e047ada | 639 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 640 | if (ret) { |
7ba1930d | 641 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 642 | free_msi_irqs(dev); |
7fe3730d | 643 | return ret; |
fd58e55f | 644 | } |
f7feaca7 | 645 | |
f144d149 BH |
646 | ret = msi_verify_entries(dev); |
647 | if (ret) { | |
648 | msi_mask_irq(entry, mask, ~mask); | |
649 | free_msi_irqs(dev); | |
650 | return ret; | |
651 | } | |
652 | ||
da8d1c8b NH |
653 | ret = populate_msi_sysfs(dev); |
654 | if (ret) { | |
655 | msi_mask_irq(entry, mask, ~mask); | |
656 | free_msi_irqs(dev); | |
657 | return ret; | |
658 | } | |
659 | ||
1da177e4 | 660 | /* Set MSI enabled bits */ |
ba698ad4 | 661 | pci_intx_for_msi(dev, 0); |
61b64abd | 662 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 663 | dev->msi_enabled = 1; |
1da177e4 | 664 | |
5f226991 | 665 | pcibios_free_irq(dev); |
7fe3730d | 666 | dev->irq = entry->irq; |
1da177e4 LT |
667 | return 0; |
668 | } | |
669 | ||
520fe9dc | 670 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 671 | { |
4302e0fb | 672 | resource_size_t phys_addr; |
5a05a9d8 | 673 | u32 table_offset; |
6a878e50 | 674 | unsigned long flags; |
5a05a9d8 HS |
675 | u8 bir; |
676 | ||
909094c6 BH |
677 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
678 | &table_offset); | |
4d18760c | 679 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
680 | flags = pci_resource_flags(dev, bir); |
681 | if (!flags || (flags & IORESOURCE_UNSET)) | |
682 | return NULL; | |
683 | ||
4d18760c | 684 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
685 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
686 | ||
687 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
688 | } | |
689 | ||
520fe9dc | 690 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
e75eafb9 TG |
691 | struct msix_entry *entries, int nvec, |
692 | bool affinity) | |
d9d7070e | 693 | { |
e75eafb9 | 694 | struct cpumask *curmsk, *masks = NULL; |
d9d7070e | 695 | struct msi_desc *entry; |
e75eafb9 | 696 | int ret, i; |
4ef33685 | 697 | |
e75eafb9 TG |
698 | if (affinity) { |
699 | masks = irq_create_affinity_masks(dev->irq_affinity, nvec); | |
700 | if (!masks) | |
701 | pr_err("Unable to allocate affinity masks, ignoring\n"); | |
702 | } | |
4ef33685 | 703 | |
e75eafb9 TG |
704 | for (i = 0, curmsk = masks; i < nvec; i++) { |
705 | entry = alloc_msi_entry(&dev->dev, 1, curmsk); | |
d9d7070e HS |
706 | if (!entry) { |
707 | if (!i) | |
708 | iounmap(base); | |
709 | else | |
710 | free_msi_irqs(dev); | |
711 | /* No enough memory. Don't try again */ | |
e75eafb9 TG |
712 | ret = -ENOMEM; |
713 | goto out; | |
d9d7070e HS |
714 | } |
715 | ||
716 | entry->msi_attrib.is_msix = 1; | |
717 | entry->msi_attrib.is_64 = 1; | |
3ac020e0 CH |
718 | if (entries) |
719 | entry->msi_attrib.entry_nr = entries[i].entry; | |
720 | else | |
721 | entry->msi_attrib.entry_nr = i; | |
d9d7070e | 722 | entry->msi_attrib.default_irq = dev->irq; |
d9d7070e HS |
723 | entry->mask_base = base; |
724 | ||
5004e98a | 725 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
e75eafb9 TG |
726 | if (masks) |
727 | curmsk++; | |
d9d7070e | 728 | } |
e75eafb9 TG |
729 | ret = 0; |
730 | out: | |
731 | kfree(masks); | |
d9d7070e HS |
732 | return 0; |
733 | } | |
734 | ||
75cb3426 | 735 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 736 | struct msix_entry *entries) |
75cb3426 HS |
737 | { |
738 | struct msi_desc *entry; | |
739 | int i = 0; | |
740 | ||
5004e98a | 741 | for_each_pci_msi_entry(entry, dev) { |
3ac020e0 CH |
742 | if (entries) |
743 | entries[i++].vector = entry->irq; | |
12eb21de CH |
744 | entry->masked = readl(pci_msix_desc_addr(entry) + |
745 | PCI_MSIX_ENTRY_VECTOR_CTRL); | |
75cb3426 | 746 | msix_mask_irq(entry, 1); |
75cb3426 HS |
747 | } |
748 | } | |
749 | ||
1da177e4 LT |
750 | /** |
751 | * msix_capability_init - configure device's MSI-X capability | |
752 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
753 | * @entries: pointer to an array of struct msix_entry entries |
754 | * @nvec: number of @entries | |
1da177e4 | 755 | * |
eaae4b3a | 756 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
757 | * single MSI-X irq. A return of zero indicates the successful setup of |
758 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 | 759 | **/ |
e75eafb9 TG |
760 | static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries, |
761 | int nvec, bool affinity) | |
1da177e4 | 762 | { |
520fe9dc | 763 | int ret; |
5a05a9d8 | 764 | u16 control; |
1da177e4 LT |
765 | void __iomem *base; |
766 | ||
f598282f | 767 | /* Ensure MSI-X is disabled while it is set up */ |
61b64abd | 768 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 769 | |
66f0d0c4 | 770 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 771 | /* Request & Map MSI-X table region */ |
527eee29 | 772 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 773 | if (!base) |
1da177e4 LT |
774 | return -ENOMEM; |
775 | ||
e75eafb9 | 776 | ret = msix_setup_entries(dev, base, entries, nvec, affinity); |
d9d7070e HS |
777 | if (ret) |
778 | return ret; | |
9c831334 | 779 | |
8e047ada | 780 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 781 | if (ret) |
2adc7907 | 782 | goto out_avail; |
9c831334 | 783 | |
f144d149 BH |
784 | /* Check if all MSI entries honor device restrictions */ |
785 | ret = msi_verify_entries(dev); | |
786 | if (ret) | |
787 | goto out_free; | |
788 | ||
f598282f MW |
789 | /* |
790 | * Some devices require MSI-X to be enabled before we can touch the | |
791 | * MSI-X registers. We need to mask all the vectors to prevent | |
792 | * interrupts coming in before they're fully set up. | |
793 | */ | |
61b64abd | 794 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 795 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
f598282f | 796 | |
75cb3426 | 797 | msix_program_entries(dev, entries); |
f598282f | 798 | |
da8d1c8b | 799 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
800 | if (ret) |
801 | goto out_free; | |
da8d1c8b | 802 | |
f598282f | 803 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 804 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 805 | dev->msix_enabled = 1; |
61b64abd | 806 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 807 | |
5f226991 | 808 | pcibios_free_irq(dev); |
1da177e4 | 809 | return 0; |
583871d4 | 810 | |
2adc7907 | 811 | out_avail: |
583871d4 HS |
812 | if (ret < 0) { |
813 | /* | |
814 | * If we had some success, report the number of irqs | |
815 | * we succeeded in setting up. | |
816 | */ | |
d9d7070e | 817 | struct msi_desc *entry; |
583871d4 HS |
818 | int avail = 0; |
819 | ||
5004e98a | 820 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
821 | if (entry->irq != 0) |
822 | avail++; | |
823 | } | |
824 | if (avail != 0) | |
825 | ret = avail; | |
826 | } | |
827 | ||
2adc7907 | 828 | out_free: |
583871d4 HS |
829 | free_msi_irqs(dev); |
830 | ||
831 | return ret; | |
1da177e4 LT |
832 | } |
833 | ||
24334a12 | 834 | /** |
a06cd74c | 835 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 836 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 837 | * @nvec: how many MSIs have been requested ? |
24334a12 | 838 | * |
f7625980 | 839 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 840 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 841 | * supported return 1, else return 0. |
24334a12 | 842 | **/ |
a06cd74c | 843 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
844 | { |
845 | struct pci_bus *bus; | |
846 | ||
0306ebfa | 847 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 848 | if (!pci_msi_enable) |
a06cd74c | 849 | return 0; |
27e20603 AG |
850 | |
851 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 852 | return 0; |
24334a12 | 853 | |
314e77b3 ME |
854 | /* |
855 | * You can't ask to have 0 or less MSIs configured. | |
856 | * a) it's stupid .. | |
857 | * b) the list manipulation code assumes nvec >= 1. | |
858 | */ | |
859 | if (nvec < 1) | |
a06cd74c | 860 | return 0; |
314e77b3 | 861 | |
500559a9 HS |
862 | /* |
863 | * Any bridge which does NOT route MSI transactions from its | |
864 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
865 | * the secondary pci_bus. |
866 | * We expect only arch-specific PCI host bus controller driver | |
867 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
868 | */ | |
24334a12 BG |
869 | for (bus = dev->bus; bus; bus = bus->parent) |
870 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 871 | return 0; |
24334a12 | 872 | |
a06cd74c | 873 | return 1; |
24334a12 BG |
874 | } |
875 | ||
d1ac1d26 AG |
876 | /** |
877 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
878 | * @dev: device to report about | |
879 | * | |
880 | * This function returns the number of MSI vectors a device requested via | |
881 | * Multiple Message Capable register. It returns a negative errno if the | |
882 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
883 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
884 | * MSI specification. | |
885 | **/ | |
886 | int pci_msi_vec_count(struct pci_dev *dev) | |
887 | { | |
888 | int ret; | |
889 | u16 msgctl; | |
890 | ||
891 | if (!dev->msi_cap) | |
892 | return -EINVAL; | |
893 | ||
894 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
895 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
896 | ||
897 | return ret; | |
898 | } | |
899 | EXPORT_SYMBOL(pci_msi_vec_count); | |
900 | ||
f2440d9a | 901 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 902 | { |
f2440d9a MW |
903 | struct msi_desc *desc; |
904 | u32 mask; | |
1da177e4 | 905 | |
128bc5fc | 906 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
907 | return; |
908 | ||
5004e98a | 909 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 910 | desc = first_pci_msi_entry(dev); |
110828c9 | 911 | |
61b64abd | 912 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 913 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 914 | dev->msi_enabled = 0; |
7bd007e4 | 915 | |
12abb8ba | 916 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 917 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 918 | /* Keep cached state to be restored */ |
23ed8d57 | 919 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
920 | |
921 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 922 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 923 | pcibios_alloc_irq(dev); |
d52877c7 | 924 | } |
24d27553 | 925 | |
500559a9 | 926 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 927 | { |
d52877c7 YL |
928 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
929 | return; | |
930 | ||
931 | pci_msi_shutdown(dev); | |
f56e4481 | 932 | free_msi_irqs(dev); |
1da177e4 | 933 | } |
4cc086fa | 934 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 935 | |
a52e2e35 | 936 | /** |
ff1aa430 | 937 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 938 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
939 | * This function returns the number of device's MSI-X table entries and |
940 | * therefore the number of MSI-X vectors device is capable of sending. | |
941 | * It returns a negative errno if the device is not capable of sending MSI-X | |
942 | * interrupts. | |
943 | **/ | |
944 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 945 | { |
a52e2e35 RW |
946 | u16 control; |
947 | ||
520fe9dc | 948 | if (!dev->msix_cap) |
ff1aa430 | 949 | return -EINVAL; |
a52e2e35 | 950 | |
f84ecd28 | 951 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 952 | return msix_table_size(control); |
a52e2e35 | 953 | } |
ff1aa430 | 954 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 955 | |
e75eafb9 TG |
956 | static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, |
957 | int nvec, bool affinity) | |
1da177e4 | 958 | { |
5ec09405 | 959 | int nr_entries; |
ded86d8d | 960 | int i, j; |
1da177e4 | 961 | |
a06cd74c AG |
962 | if (!pci_msi_supported(dev, nvec)) |
963 | return -EINVAL; | |
c9953a73 | 964 | |
ff1aa430 AG |
965 | nr_entries = pci_msix_vec_count(dev); |
966 | if (nr_entries < 0) | |
967 | return nr_entries; | |
1da177e4 | 968 | if (nvec > nr_entries) |
57fbf52c | 969 | return nr_entries; |
1da177e4 | 970 | |
3ac020e0 CH |
971 | if (entries) { |
972 | /* Check for any invalid entries */ | |
973 | for (i = 0; i < nvec; i++) { | |
974 | if (entries[i].entry >= nr_entries) | |
975 | return -EINVAL; /* invalid entry */ | |
976 | for (j = i + 1; j < nvec; j++) { | |
977 | if (entries[i].entry == entries[j].entry) | |
978 | return -EINVAL; /* duplicate entry */ | |
979 | } | |
1da177e4 LT |
980 | } |
981 | } | |
ded86d8d | 982 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 983 | |
1ce03373 | 984 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 985 | if (dev->msi_enabled) { |
227f0647 | 986 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
987 | return -EINVAL; |
988 | } | |
e75eafb9 TG |
989 | return msix_capability_init(dev, entries, nvec, affinity); |
990 | } | |
991 | ||
992 | /** | |
993 | * pci_enable_msix - configure device's MSI-X capability structure | |
994 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
995 | * @entries: pointer to an array of MSI-X entries (optional) | |
996 | * @nvec: number of MSI-X irqs requested for allocation by device driver | |
997 | * | |
998 | * Setup the MSI-X capability structure of device function with the number | |
999 | * of requested irqs upon its software driver call to request for | |
1000 | * MSI-X mode enabled on its hardware device function. A return of zero | |
1001 | * indicates the successful configuration of MSI-X capability structure | |
1002 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. | |
1003 | * Or a return of > 0 indicates that driver request is exceeding the number | |
1004 | * of irqs or MSI-X vectors available. Driver should use the returned value to | |
1005 | * re-send its request. | |
1006 | **/ | |
1007 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) | |
1008 | { | |
1009 | return __pci_enable_msix(dev, entries, nvec, false); | |
1da177e4 | 1010 | } |
4cc086fa | 1011 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 1012 | |
500559a9 | 1013 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 1014 | { |
12abb8ba HS |
1015 | struct msi_desc *entry; |
1016 | ||
128bc5fc | 1017 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1018 | return; |
1019 | ||
12abb8ba | 1020 | /* Return the device with MSI-X masked as initial states */ |
5004e98a | 1021 | for_each_pci_msi_entry(entry, dev) { |
12abb8ba | 1022 | /* Keep cached states to be restored */ |
23ed8d57 | 1023 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
1024 | } |
1025 | ||
61b64abd | 1026 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 1027 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1028 | dev->msix_enabled = 0; |
5f226991 | 1029 | pcibios_alloc_irq(dev); |
d52877c7 | 1030 | } |
c901851f | 1031 | |
500559a9 | 1032 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1033 | { |
1034 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1035 | return; | |
1036 | ||
1037 | pci_msix_shutdown(dev); | |
f56e4481 | 1038 | free_msi_irqs(dev); |
1da177e4 | 1039 | } |
4cc086fa | 1040 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1041 | |
309e57df MW |
1042 | void pci_no_msi(void) |
1043 | { | |
1044 | pci_msi_enable = 0; | |
1045 | } | |
c9953a73 | 1046 | |
07ae95f9 AP |
1047 | /** |
1048 | * pci_msi_enabled - is MSI enabled? | |
1049 | * | |
1050 | * Returns true if MSI has not been disabled by the command-line option | |
1051 | * pci=nomsi. | |
1052 | **/ | |
1053 | int pci_msi_enabled(void) | |
d389fec6 | 1054 | { |
07ae95f9 | 1055 | return pci_msi_enable; |
d389fec6 | 1056 | } |
07ae95f9 | 1057 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1058 | |
4ef33685 CH |
1059 | static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, |
1060 | unsigned int flags) | |
302a2523 | 1061 | { |
e75eafb9 | 1062 | bool affinity = flags & PCI_IRQ_AFFINITY; |
034cd97e | 1063 | int nvec; |
302a2523 AG |
1064 | int rc; |
1065 | ||
a06cd74c AG |
1066 | if (!pci_msi_supported(dev, minvec)) |
1067 | return -EINVAL; | |
034cd97e AG |
1068 | |
1069 | WARN_ON(!!dev->msi_enabled); | |
1070 | ||
1071 | /* Check whether driver already requested MSI-X irqs */ | |
1072 | if (dev->msix_enabled) { | |
1073 | dev_info(&dev->dev, | |
1074 | "can't enable MSI (MSI-X already enabled)\n"); | |
1075 | return -EINVAL; | |
1076 | } | |
1077 | ||
302a2523 AG |
1078 | if (maxvec < minvec) |
1079 | return -ERANGE; | |
1080 | ||
034cd97e AG |
1081 | nvec = pci_msi_vec_count(dev); |
1082 | if (nvec < 0) | |
1083 | return nvec; | |
4ef33685 | 1084 | if (nvec < minvec) |
034cd97e | 1085 | return -EINVAL; |
4ef33685 CH |
1086 | |
1087 | if (nvec > maxvec) | |
034cd97e AG |
1088 | nvec = maxvec; |
1089 | ||
4ef33685 | 1090 | for (;;) { |
e75eafb9 TG |
1091 | if (affinity) { |
1092 | nvec = irq_calc_affinity_vectors(dev->irq_affinity, | |
1093 | nvec); | |
4ef33685 CH |
1094 | if (nvec < minvec) |
1095 | return -ENOSPC; | |
1096 | } | |
1097 | ||
e75eafb9 | 1098 | rc = msi_capability_init(dev, nvec, affinity); |
4ef33685 CH |
1099 | if (rc == 0) |
1100 | return nvec; | |
1101 | ||
4ef33685 | 1102 | if (rc < 0) |
302a2523 | 1103 | return rc; |
4ef33685 CH |
1104 | if (rc < minvec) |
1105 | return -ENOSPC; | |
1106 | ||
1107 | nvec = rc; | |
1108 | } | |
1109 | } | |
1110 | ||
1111 | /** | |
1112 | * pci_enable_msi_range - configure device's MSI capability structure | |
1113 | * @dev: device to configure | |
1114 | * @minvec: minimal number of interrupts to configure | |
1115 | * @maxvec: maximum number of interrupts to configure | |
1116 | * | |
1117 | * This function tries to allocate a maximum possible number of interrupts in a | |
1118 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1119 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1120 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1121 | * the other interrupt numbers allocated to this device are consecutive. | |
1122 | **/ | |
1123 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1124 | { | |
4fe0d154 | 1125 | return __pci_enable_msi_range(dev, minvec, maxvec, 0); |
4ef33685 CH |
1126 | } |
1127 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1128 | ||
1129 | static int __pci_enable_msix_range(struct pci_dev *dev, | |
1130 | struct msix_entry *entries, int minvec, int maxvec, | |
1131 | unsigned int flags) | |
1132 | { | |
e75eafb9 TG |
1133 | bool affinity = flags & PCI_IRQ_AFFINITY; |
1134 | int rc, nvec = maxvec; | |
4ef33685 CH |
1135 | |
1136 | if (maxvec < minvec) | |
1137 | return -ERANGE; | |
1138 | ||
1139 | for (;;) { | |
e75eafb9 TG |
1140 | if (affinity) { |
1141 | nvec = irq_calc_affinity_vectors(dev->irq_affinity, | |
1142 | nvec); | |
4ef33685 | 1143 | if (nvec < minvec) |
302a2523 | 1144 | return -ENOSPC; |
302a2523 | 1145 | } |
302a2523 | 1146 | |
e75eafb9 | 1147 | rc = __pci_enable_msix(dev, entries, nvec, affinity); |
4ef33685 CH |
1148 | if (rc == 0) |
1149 | return nvec; | |
1150 | ||
4ef33685 CH |
1151 | if (rc < 0) |
1152 | return rc; | |
1153 | if (rc < minvec) | |
1154 | return -ENOSPC; | |
1155 | ||
1156 | nvec = rc; | |
1157 | } | |
302a2523 | 1158 | } |
302a2523 AG |
1159 | |
1160 | /** | |
1161 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1162 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1163 | * @entries: pointer to an array of MSI-X entries | |
1164 | * @minvec: minimum number of MSI-X irqs requested | |
1165 | * @maxvec: maximum number of MSI-X irqs requested | |
1166 | * | |
1167 | * Setup the MSI-X capability structure of device function with a maximum | |
1168 | * possible number of interrupts in the range between @minvec and @maxvec | |
1169 | * upon its software driver call to request for MSI-X mode enabled on its | |
1170 | * hardware device function. It returns a negative errno if an error occurs. | |
1171 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1172 | * indicates the successful configuration of MSI-X capability structure | |
1173 | * with new allocated MSI-X interrupts. | |
1174 | **/ | |
1175 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
4ef33685 | 1176 | int minvec, int maxvec) |
302a2523 | 1177 | { |
4fe0d154 | 1178 | return __pci_enable_msix_range(dev, entries, minvec, maxvec, 0); |
302a2523 AG |
1179 | } |
1180 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1181 | |
aff17164 CH |
1182 | /** |
1183 | * pci_alloc_irq_vectors - allocate multiple IRQs for a device | |
1184 | * @dev: PCI device to operate on | |
1185 | * @min_vecs: minimum number of vectors required (must be >= 1) | |
1186 | * @max_vecs: maximum (desired) number of vectors | |
1187 | * @flags: flags or quirks for the allocation | |
1188 | * | |
1189 | * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI | |
1190 | * vectors if available, and fall back to a single legacy vector | |
1191 | * if neither is available. Return the number of vectors allocated, | |
1192 | * (which might be smaller than @max_vecs) if successful, or a negative | |
1193 | * error code on error. If less than @min_vecs interrupt vectors are | |
1194 | * available for @dev the function will fail with -ENOSPC. | |
1195 | * | |
1196 | * To get the Linux IRQ number used for a vector that can be passed to | |
1197 | * request_irq() use the pci_irq_vector() helper. | |
1198 | */ | |
1199 | int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, | |
1200 | unsigned int max_vecs, unsigned int flags) | |
1201 | { | |
1202 | int vecs = -ENOSPC; | |
1203 | ||
4fe0d154 | 1204 | if (flags & PCI_IRQ_MSIX) { |
4ef33685 CH |
1205 | vecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, |
1206 | flags); | |
aff17164 CH |
1207 | if (vecs > 0) |
1208 | return vecs; | |
1209 | } | |
1210 | ||
4fe0d154 | 1211 | if (flags & PCI_IRQ_MSI) { |
4ef33685 | 1212 | vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, flags); |
aff17164 CH |
1213 | if (vecs > 0) |
1214 | return vecs; | |
1215 | } | |
1216 | ||
1217 | /* use legacy irq if allowed */ | |
5d0bdf28 CH |
1218 | if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1) { |
1219 | pci_intx(dev, 1); | |
aff17164 | 1220 | return 1; |
5d0bdf28 CH |
1221 | } |
1222 | ||
aff17164 CH |
1223 | return vecs; |
1224 | } | |
1225 | EXPORT_SYMBOL(pci_alloc_irq_vectors); | |
1226 | ||
1227 | /** | |
1228 | * pci_free_irq_vectors - free previously allocated IRQs for a device | |
1229 | * @dev: PCI device to operate on | |
1230 | * | |
1231 | * Undoes the allocations and enabling in pci_alloc_irq_vectors(). | |
1232 | */ | |
1233 | void pci_free_irq_vectors(struct pci_dev *dev) | |
1234 | { | |
1235 | pci_disable_msix(dev); | |
1236 | pci_disable_msi(dev); | |
1237 | } | |
1238 | EXPORT_SYMBOL(pci_free_irq_vectors); | |
1239 | ||
1240 | /** | |
1241 | * pci_irq_vector - return Linux IRQ number of a device vector | |
1242 | * @dev: PCI device to operate on | |
1243 | * @nr: device-relative interrupt vector index (0-based). | |
1244 | */ | |
1245 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1246 | { | |
1247 | if (dev->msix_enabled) { | |
1248 | struct msi_desc *entry; | |
1249 | int i = 0; | |
1250 | ||
1251 | for_each_pci_msi_entry(entry, dev) { | |
1252 | if (i == nr) | |
1253 | return entry->irq; | |
1254 | i++; | |
1255 | } | |
1256 | WARN_ON_ONCE(1); | |
1257 | return -EINVAL; | |
1258 | } | |
1259 | ||
1260 | if (dev->msi_enabled) { | |
1261 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1262 | ||
1263 | if (WARN_ON_ONCE(nr >= entry->nvec_used)) | |
1264 | return -EINVAL; | |
1265 | } else { | |
1266 | if (WARN_ON_ONCE(nr > 0)) | |
1267 | return -EINVAL; | |
1268 | } | |
1269 | ||
1270 | return dev->irq + nr; | |
1271 | } | |
1272 | EXPORT_SYMBOL(pci_irq_vector); | |
1273 | ||
ee8d41e5 TG |
1274 | /** |
1275 | * pci_irq_get_affinity - return the affinity of a particular msi vector | |
1276 | * @dev: PCI device to operate on | |
1277 | * @nr: device-relative interrupt vector index (0-based). | |
1278 | */ | |
1279 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr) | |
1280 | { | |
1281 | if (dev->msix_enabled) { | |
1282 | struct msi_desc *entry; | |
1283 | int i = 0; | |
1284 | ||
1285 | for_each_pci_msi_entry(entry, dev) { | |
1286 | if (i == nr) | |
1287 | return entry->affinity; | |
1288 | i++; | |
1289 | } | |
1290 | WARN_ON_ONCE(1); | |
1291 | return NULL; | |
1292 | } else if (dev->msi_enabled) { | |
1293 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1294 | ||
1295 | if (WARN_ON_ONCE(!entry || nr >= entry->nvec_used)) | |
1296 | return NULL; | |
1297 | ||
1298 | return &entry->affinity[nr]; | |
1299 | } else { | |
1300 | return cpu_possible_mask; | |
1301 | } | |
1302 | } | |
1303 | EXPORT_SYMBOL(pci_irq_get_affinity); | |
1304 | ||
25a98bd4 JL |
1305 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1306 | { | |
1307 | return to_pci_dev(desc->dev); | |
1308 | } | |
a4289dc2 | 1309 | EXPORT_SYMBOL(msi_desc_to_pci_dev); |
25a98bd4 | 1310 | |
c179c9b9 JL |
1311 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1312 | { | |
1313 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1314 | ||
1315 | return dev->bus->sysdata; | |
1316 | } | |
1317 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1318 | ||
3878eaef JL |
1319 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1320 | /** | |
1321 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1322 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1323 | * @msg: Pointer to the message | |
1324 | */ | |
1325 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1326 | { | |
507a883e | 1327 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1328 | |
1329 | /* | |
1330 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1331 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1332 | */ | |
1333 | if (desc->irq == irq_data->irq) | |
1334 | __pci_write_msi_msg(desc, msg); | |
1335 | } | |
1336 | ||
1337 | /** | |
1338 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
1339 | * @dev: Pointer to the PCI device | |
1340 | * @desc: Pointer to the msi descriptor | |
1341 | * | |
1342 | * The ID number is only used within the irqdomain. | |
1343 | */ | |
1344 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, | |
1345 | struct msi_desc *desc) | |
1346 | { | |
1347 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | | |
1348 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | | |
1349 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; | |
1350 | } | |
1351 | ||
1352 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1353 | { | |
1354 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1355 | } | |
1356 | ||
1357 | /** | |
1358 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev | |
1359 | * @domain: The interrupt domain to check | |
1360 | * @info: The domain info for verification | |
1361 | * @dev: The device to check | |
1362 | * | |
1363 | * Returns: | |
1364 | * 0 if the functionality is supported | |
1365 | * 1 if Multi MSI is requested, but the domain does not support it | |
1366 | * -ENOTSUPP otherwise | |
1367 | */ | |
1368 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1369 | struct msi_domain_info *info, struct device *dev) | |
1370 | { | |
1371 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1372 | ||
1373 | /* Special handling to support pci_enable_msi_range() */ | |
1374 | if (pci_msi_desc_is_multi_msi(desc) && | |
1375 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1376 | return 1; | |
1377 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1378 | return -ENOTSUPP; | |
1379 | ||
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1384 | struct msi_desc *desc, int error) | |
1385 | { | |
1386 | /* Special handling to support pci_enable_msi_range() */ | |
1387 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) | |
1388 | return 1; | |
1389 | ||
1390 | return error; | |
1391 | } | |
1392 | ||
1393 | #ifdef GENERIC_MSI_DOMAIN_OPS | |
1394 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, | |
1395 | struct msi_desc *desc) | |
1396 | { | |
1397 | arg->desc = desc; | |
1398 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), | |
1399 | desc); | |
1400 | } | |
1401 | #else | |
1402 | #define pci_msi_domain_set_desc NULL | |
1403 | #endif | |
1404 | ||
1405 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1406 | .set_desc = pci_msi_domain_set_desc, | |
1407 | .msi_check = pci_msi_domain_check_cap, | |
1408 | .handle_error = pci_msi_domain_handle_error, | |
1409 | }; | |
1410 | ||
1411 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1412 | { | |
1413 | struct msi_domain_ops *ops = info->ops; | |
1414 | ||
1415 | if (ops == NULL) { | |
1416 | info->ops = &pci_msi_domain_ops_default; | |
1417 | } else { | |
1418 | if (ops->set_desc == NULL) | |
1419 | ops->set_desc = pci_msi_domain_set_desc; | |
1420 | if (ops->msi_check == NULL) | |
1421 | ops->msi_check = pci_msi_domain_check_cap; | |
1422 | if (ops->handle_error == NULL) | |
1423 | ops->handle_error = pci_msi_domain_handle_error; | |
1424 | } | |
1425 | } | |
1426 | ||
1427 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1428 | { | |
1429 | struct irq_chip *chip = info->chip; | |
1430 | ||
1431 | BUG_ON(!chip); | |
1432 | if (!chip->irq_write_msi_msg) | |
1433 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1434 | if (!chip->irq_mask) |
1435 | chip->irq_mask = pci_msi_mask_irq; | |
1436 | if (!chip->irq_unmask) | |
1437 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1438 | } |
1439 | ||
1440 | /** | |
be5436c8 MZ |
1441 | * pci_msi_create_irq_domain - Create a MSI interrupt domain |
1442 | * @fwnode: Optional fwnode of the interrupt controller | |
3878eaef JL |
1443 | * @info: MSI domain info |
1444 | * @parent: Parent irq domain | |
1445 | * | |
1446 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1447 | * | |
1448 | * Returns: | |
1449 | * A domain pointer or NULL in case of failure. | |
1450 | */ | |
be5436c8 | 1451 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
1452 | struct msi_domain_info *info, |
1453 | struct irq_domain *parent) | |
1454 | { | |
0380839d MZ |
1455 | struct irq_domain *domain; |
1456 | ||
3878eaef JL |
1457 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1458 | pci_msi_domain_update_dom_ops(info); | |
1459 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1460 | pci_msi_domain_update_chip_ops(info); | |
1461 | ||
f3b0946d MZ |
1462 | info->flags |= MSI_FLAG_ACTIVATE_EARLY; |
1463 | ||
be5436c8 | 1464 | domain = msi_create_irq_domain(fwnode, info, parent); |
0380839d MZ |
1465 | if (!domain) |
1466 | return NULL; | |
1467 | ||
1468 | domain->bus_token = DOMAIN_BUS_PCI_MSI; | |
1469 | return domain; | |
3878eaef | 1470 | } |
a4289dc2 | 1471 | EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); |
3878eaef JL |
1472 | |
1473 | /** | |
1474 | * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain | |
1475 | * @domain: The interrupt domain to allocate from | |
1476 | * @dev: The device for which to allocate | |
1477 | * @nvec: The number of interrupts to allocate | |
1478 | * @type: Unused to allow simpler migration from the arch_XXX interfaces | |
1479 | * | |
1480 | * Returns: | |
1481 | * A virtual interrupt number or an error code in case of failure | |
1482 | */ | |
1483 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, | |
1484 | int nvec, int type) | |
1485 | { | |
1486 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); | |
1487 | } | |
1488 | ||
1489 | /** | |
1490 | * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain | |
1491 | * @domain: The interrupt domain | |
1492 | * @dev: The device for which to free interrupts | |
1493 | */ | |
1494 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev) | |
1495 | { | |
1496 | msi_domain_free_irqs(domain, &dev->dev); | |
1497 | } | |
8e047ada JL |
1498 | |
1499 | /** | |
1500 | * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain | |
be5436c8 | 1501 | * @fwnode: Optional fwnode of the interrupt controller |
8e047ada JL |
1502 | * @info: MSI domain info |
1503 | * @parent: Parent irq domain | |
1504 | * | |
1505 | * Returns: A domain pointer or NULL in case of failure. If successful | |
1506 | * the default PCI/MSI irqdomain pointer is updated. | |
1507 | */ | |
be5436c8 | 1508 | struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode, |
8e047ada JL |
1509 | struct msi_domain_info *info, struct irq_domain *parent) |
1510 | { | |
1511 | struct irq_domain *domain; | |
1512 | ||
1513 | mutex_lock(&pci_msi_domain_lock); | |
1514 | if (pci_msi_default_domain) { | |
1515 | pr_err("PCI: default irq domain for PCI MSI has already been created.\n"); | |
1516 | domain = NULL; | |
1517 | } else { | |
be5436c8 | 1518 | domain = pci_msi_create_irq_domain(fwnode, info, parent); |
8e047ada JL |
1519 | pci_msi_default_domain = domain; |
1520 | } | |
1521 | mutex_unlock(&pci_msi_domain_lock); | |
1522 | ||
1523 | return domain; | |
1524 | } | |
b6eec9b7 DD |
1525 | |
1526 | static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data) | |
1527 | { | |
1528 | u32 *pa = data; | |
1529 | ||
1530 | *pa = alias; | |
1531 | return 0; | |
1532 | } | |
1533 | /** | |
1534 | * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID) | |
1535 | * @domain: The interrupt domain | |
1536 | * @pdev: The PCI device. | |
1537 | * | |
1538 | * The RID for a device is formed from the alias, with a firmware | |
1539 | * supplied mapping applied | |
1540 | * | |
1541 | * Returns: The RID. | |
1542 | */ | |
1543 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev) | |
1544 | { | |
1545 | struct device_node *of_node; | |
1546 | u32 rid = 0; | |
1547 | ||
1548 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1549 | ||
1550 | of_node = irq_domain_get_of_node(domain); | |
be2021ba TN |
1551 | rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) : |
1552 | iort_msi_map_rid(&pdev->dev, rid); | |
b6eec9b7 DD |
1553 | |
1554 | return rid; | |
1555 | } | |
54fa97ee MZ |
1556 | |
1557 | /** | |
1558 | * pci_msi_get_device_domain - Get the MSI domain for a given PCI device | |
1559 | * @pdev: The PCI device | |
1560 | * | |
1561 | * Use the firmware data to find a device-specific MSI domain | |
1562 | * (i.e. not one that is ste as a default). | |
1563 | * | |
1564 | * Returns: The coresponding MSI domain or NULL if none has been found. | |
1565 | */ | |
1566 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
1567 | { | |
be2021ba | 1568 | struct irq_domain *dom; |
54fa97ee MZ |
1569 | u32 rid = 0; |
1570 | ||
1571 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
be2021ba TN |
1572 | dom = of_msi_map_get_device_domain(&pdev->dev, rid); |
1573 | if (!dom) | |
1574 | dom = iort_get_device_domain(&pdev->dev, rid); | |
1575 | return dom; | |
54fa97ee | 1576 | } |
3878eaef | 1577 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |