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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
3878eaef | 22 | #include <linux/irqdomain.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
38737d82 | 27 | int pci_msi_ignore_mask; |
1da177e4 | 28 | |
527eee29 BH |
29 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
30 | ||
8e047ada JL |
31 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
32 | static struct irq_domain *pci_msi_default_domain; | |
33 | static DEFINE_MUTEX(pci_msi_domain_lock); | |
34 | ||
35 | struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev) | |
36 | { | |
37 | return pci_msi_default_domain; | |
38 | } | |
39 | ||
020c3126 MZ |
40 | static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev) |
41 | { | |
d8a1cb75 | 42 | struct irq_domain *domain; |
020c3126 | 43 | |
d8a1cb75 MZ |
44 | domain = dev_get_msi_domain(&dev->dev); |
45 | if (domain) | |
46 | return domain; | |
020c3126 | 47 | |
d8a1cb75 | 48 | return arch_get_pci_msi_domain(dev); |
020c3126 MZ |
49 | } |
50 | ||
8e047ada JL |
51 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
52 | { | |
53 | struct irq_domain *domain; | |
54 | ||
020c3126 | 55 | domain = pci_msi_get_domain(dev); |
8e047ada JL |
56 | if (domain) |
57 | return pci_msi_domain_alloc_irqs(domain, dev, nvec, type); | |
58 | ||
59 | return arch_setup_msi_irqs(dev, nvec, type); | |
60 | } | |
61 | ||
62 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
63 | { | |
64 | struct irq_domain *domain; | |
65 | ||
020c3126 | 66 | domain = pci_msi_get_domain(dev); |
8e047ada JL |
67 | if (domain) |
68 | pci_msi_domain_free_irqs(domain, dev); | |
69 | else | |
70 | arch_teardown_msi_irqs(dev); | |
71 | } | |
72 | #else | |
73 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
74 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
75 | #endif | |
527eee29 | 76 | |
6a9e7f20 AB |
77 | /* Arch hooks */ |
78 | ||
4287d824 TP |
79 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
80 | { | |
2291ec09 | 81 | struct msi_controller *chip = dev->bus->msi; |
0cbdcfcf TR |
82 | int err; |
83 | ||
84 | if (!chip || !chip->setup_irq) | |
85 | return -EINVAL; | |
86 | ||
87 | err = chip->setup_irq(chip, dev, desc); | |
88 | if (err < 0) | |
89 | return err; | |
90 | ||
91 | irq_set_chip_data(desc->irq, chip); | |
92 | ||
93 | return 0; | |
4287d824 TP |
94 | } |
95 | ||
96 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 97 | { |
c2791b80 | 98 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
99 | |
100 | if (!chip || !chip->teardown_irq) | |
101 | return; | |
102 | ||
103 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
104 | } |
105 | ||
4287d824 | 106 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
107 | { |
108 | struct msi_desc *entry; | |
109 | int ret; | |
110 | ||
1c8d7b0a MW |
111 | /* |
112 | * If an architecture wants to support multiple MSI, it needs to | |
113 | * override arch_setup_msi_irqs() | |
114 | */ | |
115 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
116 | return 1; | |
117 | ||
5004e98a | 118 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 119 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 120 | if (ret < 0) |
6a9e7f20 | 121 | return ret; |
b5fbf533 ME |
122 | if (ret > 0) |
123 | return -ENOSPC; | |
6a9e7f20 AB |
124 | } |
125 | ||
126 | return 0; | |
127 | } | |
1525bf0d | 128 | |
4287d824 TP |
129 | /* |
130 | * We have a default implementation available as a separate non-weak | |
131 | * function, as it is used by the Xen x86 PCI code | |
132 | */ | |
1525bf0d | 133 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 134 | { |
63a7b17e | 135 | int i; |
6a9e7f20 AB |
136 | struct msi_desc *entry; |
137 | ||
5004e98a | 138 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
139 | if (entry->irq) |
140 | for (i = 0; i < entry->nvec_used; i++) | |
141 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
142 | } |
143 | ||
4287d824 TP |
144 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
145 | { | |
146 | return default_teardown_msi_irqs(dev); | |
147 | } | |
76ccc297 | 148 | |
ac8344c4 | 149 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
150 | { |
151 | struct msi_desc *entry; | |
152 | ||
153 | entry = NULL; | |
154 | if (dev->msix_enabled) { | |
5004e98a | 155 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
156 | if (irq == entry->irq) |
157 | break; | |
158 | } | |
159 | } else if (dev->msi_enabled) { | |
160 | entry = irq_get_msi_desc(irq); | |
161 | } | |
162 | ||
163 | if (entry) | |
83a18912 | 164 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 165 | } |
4287d824 | 166 | |
ac8344c4 | 167 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 168 | { |
ac8344c4 | 169 | return default_restore_msi_irqs(dev); |
4287d824 | 170 | } |
76ccc297 | 171 | |
bffac3c5 MW |
172 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
173 | { | |
0b49ec37 MW |
174 | /* Don't shift by >= width of type */ |
175 | if (x >= 5) | |
176 | return 0xffffffff; | |
177 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
178 | } |
179 | ||
ce6fce42 MW |
180 | /* |
181 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
182 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
183 | * reliably as devices without an INTx disable bit will then generate a | |
184 | * level IRQ which will never be cleared. | |
ce6fce42 | 185 | */ |
23ed8d57 | 186 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 187 | { |
f2440d9a | 188 | u32 mask_bits = desc->masked; |
1da177e4 | 189 | |
38737d82 | 190 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 191 | return 0; |
f2440d9a MW |
192 | |
193 | mask_bits &= ~mask; | |
194 | mask_bits |= flag; | |
e39758e0 JL |
195 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
196 | mask_bits); | |
12abb8ba HS |
197 | |
198 | return mask_bits; | |
199 | } | |
200 | ||
201 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
202 | { | |
23ed8d57 | 203 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
204 | } |
205 | ||
206 | /* | |
207 | * This internal function does not flush PCI writes to the device. | |
208 | * All users must ensure that they read from the device before either | |
209 | * assuming that the device state is up to date, or returning out of this | |
210 | * file. This saves a few milliseconds when initialising devices with lots | |
211 | * of MSI-X interrupts. | |
212 | */ | |
23ed8d57 | 213 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
214 | { |
215 | u32 mask_bits = desc->masked; | |
216 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 217 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
38737d82 YW |
218 | |
219 | if (pci_msi_ignore_mask) | |
220 | return 0; | |
221 | ||
8d805286 SY |
222 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
223 | if (flag) | |
224 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 225 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
226 | |
227 | return mask_bits; | |
228 | } | |
229 | ||
230 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
231 | { | |
23ed8d57 | 232 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 233 | } |
24d27553 | 234 | |
1c9db525 | 235 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 236 | { |
c391f262 | 237 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
24d27553 | 238 | |
f2440d9a MW |
239 | if (desc->msi_attrib.is_msix) { |
240 | msix_mask_irq(desc, flag); | |
241 | readl(desc->mask_base); /* Flush write to device */ | |
242 | } else { | |
a281b788 | 243 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 244 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 245 | } |
f2440d9a MW |
246 | } |
247 | ||
23ed8d57 TG |
248 | /** |
249 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts | |
250 | * @data: pointer to irqdata associated to that interrupt | |
251 | */ | |
252 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 253 | { |
1c9db525 | 254 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
255 | } |
256 | ||
23ed8d57 TG |
257 | /** |
258 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts | |
259 | * @data: pointer to irqdata associated to that interrupt | |
260 | */ | |
261 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 262 | { |
1c9db525 | 263 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
264 | } |
265 | ||
ac8344c4 D |
266 | void default_restore_msi_irqs(struct pci_dev *dev) |
267 | { | |
268 | struct msi_desc *entry; | |
269 | ||
5004e98a | 270 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 271 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
272 | } |
273 | ||
891d4a48 | 274 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 275 | { |
e39758e0 JL |
276 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
277 | ||
278 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
279 | |
280 | if (entry->msi_attrib.is_msix) { | |
281 | void __iomem *base = entry->mask_base + | |
282 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
283 | ||
284 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
285 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
286 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
287 | } else { | |
f5322169 | 288 | int pos = dev->msi_cap; |
30da5524 BH |
289 | u16 data; |
290 | ||
9925ad0c BH |
291 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
292 | &msg->address_lo); | |
30da5524 | 293 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
294 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
295 | &msg->address_hi); | |
2f221349 | 296 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
297 | } else { |
298 | msg->address_hi = 0; | |
2f221349 | 299 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
300 | } |
301 | msg->data = data; | |
302 | } | |
303 | } | |
304 | ||
83a18912 | 305 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 306 | { |
e39758e0 JL |
307 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
308 | ||
309 | if (dev->current_state != PCI_D0) { | |
fcd097f3 BH |
310 | /* Don't touch the hardware now */ |
311 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
312 | void __iomem *base; |
313 | base = entry->mask_base + | |
314 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
315 | ||
2c21fd4b HS |
316 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
317 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
318 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 319 | } else { |
f5322169 | 320 | int pos = dev->msi_cap; |
1c8d7b0a MW |
321 | u16 msgctl; |
322 | ||
f84ecd28 | 323 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
324 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
325 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 326 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 327 | |
9925ad0c BH |
328 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
329 | msg->address_lo); | |
0366f8f7 | 330 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
331 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
332 | msg->address_hi); | |
2f221349 BH |
333 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
334 | msg->data); | |
0366f8f7 | 335 | } else { |
2f221349 BH |
336 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
337 | msg->data); | |
0366f8f7 | 338 | } |
1da177e4 | 339 | } |
392ee1e6 | 340 | entry->msg = *msg; |
1da177e4 | 341 | } |
0366f8f7 | 342 | |
83a18912 | 343 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 344 | { |
dced35ae | 345 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 346 | |
83a18912 | 347 | __pci_write_msi_msg(entry, msg); |
3145e941 | 348 | } |
83a18912 | 349 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 350 | |
f56e4481 HS |
351 | static void free_msi_irqs(struct pci_dev *dev) |
352 | { | |
5004e98a | 353 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 354 | struct msi_desc *entry, *tmp; |
1c51b50c GKH |
355 | struct attribute **msi_attrs; |
356 | struct device_attribute *dev_attr; | |
63a7b17e | 357 | int i, count = 0; |
f56e4481 | 358 | |
5004e98a | 359 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
360 | if (entry->irq) |
361 | for (i = 0; i < entry->nvec_used; i++) | |
362 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 363 | |
8e047ada | 364 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 365 | |
5004e98a | 366 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 367 | if (entry->msi_attrib.is_msix) { |
5004e98a | 368 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
369 | iounmap(entry->mask_base); |
370 | } | |
424eb391 | 371 | |
f56e4481 HS |
372 | list_del(&entry->list); |
373 | kfree(entry); | |
374 | } | |
1c51b50c GKH |
375 | |
376 | if (dev->msi_irq_groups) { | |
377 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
378 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 379 | while (msi_attrs[count]) { |
1c51b50c GKH |
380 | dev_attr = container_of(msi_attrs[count], |
381 | struct device_attribute, attr); | |
382 | kfree(dev_attr->attr.name); | |
383 | kfree(dev_attr); | |
384 | ++count; | |
385 | } | |
386 | kfree(msi_attrs); | |
387 | kfree(dev->msi_irq_groups[0]); | |
388 | kfree(dev->msi_irq_groups); | |
389 | dev->msi_irq_groups = NULL; | |
390 | } | |
f56e4481 | 391 | } |
c54c1879 | 392 | |
ba698ad4 DM |
393 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
394 | { | |
395 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
396 | pci_intx(dev, enable); | |
397 | } | |
398 | ||
8fed4b65 | 399 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 400 | { |
41017f0c | 401 | u16 control; |
392ee1e6 | 402 | struct msi_desc *entry; |
41017f0c | 403 | |
b1cbf4e4 EB |
404 | if (!dev->msi_enabled) |
405 | return; | |
406 | ||
dced35ae | 407 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 408 | |
ba698ad4 | 409 | pci_intx_for_msi(dev, 0); |
61b64abd | 410 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 411 | arch_restore_msi_irqs(dev); |
392ee1e6 | 412 | |
f5322169 | 413 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
414 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
415 | entry->masked); | |
abad2ec9 | 416 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 417 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 418 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
419 | } |
420 | ||
421 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 422 | { |
41017f0c | 423 | struct msi_desc *entry; |
41017f0c | 424 | |
ded86d8d EB |
425 | if (!dev->msix_enabled) |
426 | return; | |
5004e98a | 427 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 428 | |
41017f0c | 429 | /* route the table */ |
ba698ad4 | 430 | pci_intx_for_msi(dev, 0); |
61b64abd | 431 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 432 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 433 | |
ac8344c4 | 434 | arch_restore_msi_irqs(dev); |
5004e98a | 435 | for_each_pci_msi_entry(entry, dev) |
f2440d9a | 436 | msix_mask_irq(entry, entry->masked); |
41017f0c | 437 | |
61b64abd | 438 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 439 | } |
8fed4b65 ME |
440 | |
441 | void pci_restore_msi_state(struct pci_dev *dev) | |
442 | { | |
443 | __pci_restore_msi_state(dev); | |
444 | __pci_restore_msix_state(dev); | |
445 | } | |
94688cf2 | 446 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 447 | |
1c51b50c | 448 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
449 | char *buf) |
450 | { | |
1c51b50c GKH |
451 | struct msi_desc *entry; |
452 | unsigned long irq; | |
453 | int retval; | |
da8d1c8b | 454 | |
1c51b50c GKH |
455 | retval = kstrtoul(attr->attr.name, 10, &irq); |
456 | if (retval) | |
457 | return retval; | |
da8d1c8b | 458 | |
e11ece5a YW |
459 | entry = irq_get_msi_desc(irq); |
460 | if (entry) | |
461 | return sprintf(buf, "%s\n", | |
462 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
463 | ||
1c51b50c | 464 | return -ENODEV; |
da8d1c8b NH |
465 | } |
466 | ||
da8d1c8b NH |
467 | static int populate_msi_sysfs(struct pci_dev *pdev) |
468 | { | |
1c51b50c GKH |
469 | struct attribute **msi_attrs; |
470 | struct attribute *msi_attr; | |
471 | struct device_attribute *msi_dev_attr; | |
472 | struct attribute_group *msi_irq_group; | |
473 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 474 | struct msi_desc *entry; |
1c51b50c GKH |
475 | int ret = -ENOMEM; |
476 | int num_msi = 0; | |
da8d1c8b NH |
477 | int count = 0; |
478 | ||
1c51b50c | 479 | /* Determine how many msi entries we have */ |
5004e98a | 480 | for_each_pci_msi_entry(entry, pdev) |
1c51b50c | 481 | ++num_msi; |
1c51b50c GKH |
482 | if (!num_msi) |
483 | return 0; | |
da8d1c8b | 484 | |
1c51b50c GKH |
485 | /* Dynamically create the MSI attributes for the PCI device */ |
486 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
487 | if (!msi_attrs) | |
488 | return -ENOMEM; | |
5004e98a | 489 | for_each_pci_msi_entry(entry, pdev) { |
1c51b50c | 490 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 491 | if (!msi_dev_attr) |
1c51b50c | 492 | goto error_attrs; |
1406276c | 493 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 494 | |
1c51b50c | 495 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
496 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
497 | entry->irq); | |
498 | if (!msi_dev_attr->attr.name) | |
499 | goto error_attrs; | |
1c51b50c GKH |
500 | msi_dev_attr->attr.mode = S_IRUGO; |
501 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 502 | ++count; |
da8d1c8b NH |
503 | } |
504 | ||
1c51b50c GKH |
505 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
506 | if (!msi_irq_group) | |
507 | goto error_attrs; | |
508 | msi_irq_group->name = "msi_irqs"; | |
509 | msi_irq_group->attrs = msi_attrs; | |
510 | ||
511 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
512 | if (!msi_irq_groups) | |
513 | goto error_irq_group; | |
514 | msi_irq_groups[0] = msi_irq_group; | |
515 | ||
516 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
517 | if (ret) | |
518 | goto error_irq_groups; | |
519 | pdev->msi_irq_groups = msi_irq_groups; | |
520 | ||
da8d1c8b NH |
521 | return 0; |
522 | ||
1c51b50c GKH |
523 | error_irq_groups: |
524 | kfree(msi_irq_groups); | |
525 | error_irq_group: | |
526 | kfree(msi_irq_group); | |
527 | error_attrs: | |
528 | count = 0; | |
529 | msi_attr = msi_attrs[count]; | |
530 | while (msi_attr) { | |
531 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
532 | kfree(msi_attr->name); | |
533 | kfree(msi_dev_attr); | |
534 | ++count; | |
535 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 536 | } |
29237756 | 537 | kfree(msi_attrs); |
da8d1c8b NH |
538 | return ret; |
539 | } | |
540 | ||
63a7b17e | 541 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec) |
d873b4d4 YW |
542 | { |
543 | u16 control; | |
544 | struct msi_desc *entry; | |
545 | ||
546 | /* MSI Entry Initialization */ | |
aa48b6f7 | 547 | entry = alloc_msi_entry(&dev->dev); |
d873b4d4 YW |
548 | if (!entry) |
549 | return NULL; | |
550 | ||
551 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
552 | ||
553 | entry->msi_attrib.is_msix = 0; | |
554 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
555 | entry->msi_attrib.entry_nr = 0; | |
556 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
557 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 558 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e JL |
559 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
560 | entry->nvec_used = nvec; | |
d873b4d4 YW |
561 | |
562 | if (control & PCI_MSI_FLAGS_64BIT) | |
563 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
564 | else | |
565 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
566 | ||
567 | /* Save the initial mask status */ | |
568 | if (entry->msi_attrib.maskbit) | |
569 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
570 | ||
571 | return entry; | |
572 | } | |
573 | ||
f144d149 BH |
574 | static int msi_verify_entries(struct pci_dev *dev) |
575 | { | |
576 | struct msi_desc *entry; | |
577 | ||
5004e98a | 578 | for_each_pci_msi_entry(entry, dev) { |
f144d149 BH |
579 | if (!dev->no_64bit_msi || !entry->msg.address_hi) |
580 | continue; | |
581 | dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" | |
582 | " tried to assign one above 4G\n"); | |
583 | return -EIO; | |
584 | } | |
585 | return 0; | |
586 | } | |
587 | ||
1da177e4 LT |
588 | /** |
589 | * msi_capability_init - configure device's MSI capability structure | |
590 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 591 | * @nvec: number of interrupts to allocate |
1da177e4 | 592 | * |
1c8d7b0a MW |
593 | * Setup the MSI capability structure of the device with the requested |
594 | * number of interrupts. A return value of zero indicates the successful | |
595 | * setup of an entry with the new MSI irq. A negative return value indicates | |
596 | * an error, and a positive return value indicates the number of interrupts | |
597 | * which could have been allocated. | |
598 | */ | |
599 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
600 | { |
601 | struct msi_desc *entry; | |
f465136d | 602 | int ret; |
f2440d9a | 603 | unsigned mask; |
1da177e4 | 604 | |
61b64abd | 605 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 606 | |
63a7b17e | 607 | entry = msi_setup_entry(dev, nvec); |
f7feaca7 EB |
608 | if (!entry) |
609 | return -ENOMEM; | |
1ce03373 | 610 | |
f2440d9a | 611 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 612 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
613 | msi_mask_irq(entry, mask, mask); |
614 | ||
5004e98a | 615 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 616 | |
1da177e4 | 617 | /* Configure MSI capability structure */ |
8e047ada | 618 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 619 | if (ret) { |
7ba1930d | 620 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 621 | free_msi_irqs(dev); |
7fe3730d | 622 | return ret; |
fd58e55f | 623 | } |
f7feaca7 | 624 | |
f144d149 BH |
625 | ret = msi_verify_entries(dev); |
626 | if (ret) { | |
627 | msi_mask_irq(entry, mask, ~mask); | |
628 | free_msi_irqs(dev); | |
629 | return ret; | |
630 | } | |
631 | ||
da8d1c8b NH |
632 | ret = populate_msi_sysfs(dev); |
633 | if (ret) { | |
634 | msi_mask_irq(entry, mask, ~mask); | |
635 | free_msi_irqs(dev); | |
636 | return ret; | |
637 | } | |
638 | ||
1da177e4 | 639 | /* Set MSI enabled bits */ |
ba698ad4 | 640 | pci_intx_for_msi(dev, 0); |
61b64abd | 641 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 642 | dev->msi_enabled = 1; |
1da177e4 | 643 | |
5f226991 | 644 | pcibios_free_irq(dev); |
7fe3730d | 645 | dev->irq = entry->irq; |
1da177e4 LT |
646 | return 0; |
647 | } | |
648 | ||
520fe9dc | 649 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 650 | { |
4302e0fb | 651 | resource_size_t phys_addr; |
5a05a9d8 | 652 | u32 table_offset; |
6a878e50 | 653 | unsigned long flags; |
5a05a9d8 HS |
654 | u8 bir; |
655 | ||
909094c6 BH |
656 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
657 | &table_offset); | |
4d18760c | 658 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
659 | flags = pci_resource_flags(dev, bir); |
660 | if (!flags || (flags & IORESOURCE_UNSET)) | |
661 | return NULL; | |
662 | ||
4d18760c | 663 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
664 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
665 | ||
666 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
667 | } | |
668 | ||
520fe9dc GS |
669 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
670 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
671 | { |
672 | struct msi_desc *entry; | |
673 | int i; | |
674 | ||
675 | for (i = 0; i < nvec; i++) { | |
aa48b6f7 | 676 | entry = alloc_msi_entry(&dev->dev); |
d9d7070e HS |
677 | if (!entry) { |
678 | if (!i) | |
679 | iounmap(base); | |
680 | else | |
681 | free_msi_irqs(dev); | |
682 | /* No enough memory. Don't try again */ | |
683 | return -ENOMEM; | |
684 | } | |
685 | ||
686 | entry->msi_attrib.is_msix = 1; | |
687 | entry->msi_attrib.is_64 = 1; | |
688 | entry->msi_attrib.entry_nr = entries[i].entry; | |
689 | entry->msi_attrib.default_irq = dev->irq; | |
d9d7070e | 690 | entry->mask_base = base; |
63a7b17e | 691 | entry->nvec_used = 1; |
d9d7070e | 692 | |
5004e98a | 693 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
d9d7070e HS |
694 | } |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
75cb3426 | 699 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 700 | struct msix_entry *entries) |
75cb3426 HS |
701 | { |
702 | struct msi_desc *entry; | |
703 | int i = 0; | |
704 | ||
5004e98a | 705 | for_each_pci_msi_entry(entry, dev) { |
75cb3426 HS |
706 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + |
707 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
708 | ||
709 | entries[i].vector = entry->irq; | |
75cb3426 HS |
710 | entry->masked = readl(entry->mask_base + offset); |
711 | msix_mask_irq(entry, 1); | |
712 | i++; | |
713 | } | |
714 | } | |
715 | ||
1da177e4 LT |
716 | /** |
717 | * msix_capability_init - configure device's MSI-X capability | |
718 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
719 | * @entries: pointer to an array of struct msix_entry entries |
720 | * @nvec: number of @entries | |
1da177e4 | 721 | * |
eaae4b3a | 722 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
723 | * single MSI-X irq. A return of zero indicates the successful setup of |
724 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
725 | **/ |
726 | static int msix_capability_init(struct pci_dev *dev, | |
727 | struct msix_entry *entries, int nvec) | |
728 | { | |
520fe9dc | 729 | int ret; |
5a05a9d8 | 730 | u16 control; |
1da177e4 LT |
731 | void __iomem *base; |
732 | ||
f598282f | 733 | /* Ensure MSI-X is disabled while it is set up */ |
61b64abd | 734 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 735 | |
66f0d0c4 | 736 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 737 | /* Request & Map MSI-X table region */ |
527eee29 | 738 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 739 | if (!base) |
1da177e4 LT |
740 | return -ENOMEM; |
741 | ||
520fe9dc | 742 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
743 | if (ret) |
744 | return ret; | |
9c831334 | 745 | |
8e047ada | 746 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 747 | if (ret) |
2adc7907 | 748 | goto out_avail; |
9c831334 | 749 | |
f144d149 BH |
750 | /* Check if all MSI entries honor device restrictions */ |
751 | ret = msi_verify_entries(dev); | |
752 | if (ret) | |
753 | goto out_free; | |
754 | ||
f598282f MW |
755 | /* |
756 | * Some devices require MSI-X to be enabled before we can touch the | |
757 | * MSI-X registers. We need to mask all the vectors to prevent | |
758 | * interrupts coming in before they're fully set up. | |
759 | */ | |
61b64abd | 760 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 761 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
f598282f | 762 | |
75cb3426 | 763 | msix_program_entries(dev, entries); |
f598282f | 764 | |
da8d1c8b | 765 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
766 | if (ret) |
767 | goto out_free; | |
da8d1c8b | 768 | |
f598282f | 769 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 770 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 771 | dev->msix_enabled = 1; |
61b64abd | 772 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 773 | |
5f226991 | 774 | pcibios_free_irq(dev); |
1da177e4 | 775 | return 0; |
583871d4 | 776 | |
2adc7907 | 777 | out_avail: |
583871d4 HS |
778 | if (ret < 0) { |
779 | /* | |
780 | * If we had some success, report the number of irqs | |
781 | * we succeeded in setting up. | |
782 | */ | |
d9d7070e | 783 | struct msi_desc *entry; |
583871d4 HS |
784 | int avail = 0; |
785 | ||
5004e98a | 786 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
787 | if (entry->irq != 0) |
788 | avail++; | |
789 | } | |
790 | if (avail != 0) | |
791 | ret = avail; | |
792 | } | |
793 | ||
2adc7907 | 794 | out_free: |
583871d4 HS |
795 | free_msi_irqs(dev); |
796 | ||
797 | return ret; | |
1da177e4 LT |
798 | } |
799 | ||
24334a12 | 800 | /** |
a06cd74c | 801 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 802 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 803 | * @nvec: how many MSIs have been requested ? |
24334a12 | 804 | * |
f7625980 | 805 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 806 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 807 | * supported return 1, else return 0. |
24334a12 | 808 | **/ |
a06cd74c | 809 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
810 | { |
811 | struct pci_bus *bus; | |
812 | ||
0306ebfa | 813 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 814 | if (!pci_msi_enable) |
a06cd74c | 815 | return 0; |
27e20603 AG |
816 | |
817 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 818 | return 0; |
24334a12 | 819 | |
314e77b3 ME |
820 | /* |
821 | * You can't ask to have 0 or less MSIs configured. | |
822 | * a) it's stupid .. | |
823 | * b) the list manipulation code assumes nvec >= 1. | |
824 | */ | |
825 | if (nvec < 1) | |
a06cd74c | 826 | return 0; |
314e77b3 | 827 | |
500559a9 HS |
828 | /* |
829 | * Any bridge which does NOT route MSI transactions from its | |
830 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
831 | * the secondary pci_bus. |
832 | * We expect only arch-specific PCI host bus controller driver | |
833 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
834 | */ | |
24334a12 BG |
835 | for (bus = dev->bus; bus; bus = bus->parent) |
836 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 837 | return 0; |
24334a12 | 838 | |
a06cd74c | 839 | return 1; |
24334a12 BG |
840 | } |
841 | ||
d1ac1d26 AG |
842 | /** |
843 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
844 | * @dev: device to report about | |
845 | * | |
846 | * This function returns the number of MSI vectors a device requested via | |
847 | * Multiple Message Capable register. It returns a negative errno if the | |
848 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
849 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
850 | * MSI specification. | |
851 | **/ | |
852 | int pci_msi_vec_count(struct pci_dev *dev) | |
853 | { | |
854 | int ret; | |
855 | u16 msgctl; | |
856 | ||
857 | if (!dev->msi_cap) | |
858 | return -EINVAL; | |
859 | ||
860 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
861 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
862 | ||
863 | return ret; | |
864 | } | |
865 | EXPORT_SYMBOL(pci_msi_vec_count); | |
866 | ||
f2440d9a | 867 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 868 | { |
f2440d9a MW |
869 | struct msi_desc *desc; |
870 | u32 mask; | |
1da177e4 | 871 | |
128bc5fc | 872 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
873 | return; |
874 | ||
5004e98a | 875 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 876 | desc = first_pci_msi_entry(dev); |
110828c9 | 877 | |
61b64abd | 878 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 879 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 880 | dev->msi_enabled = 0; |
7bd007e4 | 881 | |
12abb8ba | 882 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 883 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 884 | /* Keep cached state to be restored */ |
23ed8d57 | 885 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
886 | |
887 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 888 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 889 | pcibios_alloc_irq(dev); |
d52877c7 | 890 | } |
24d27553 | 891 | |
500559a9 | 892 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 893 | { |
d52877c7 YL |
894 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
895 | return; | |
896 | ||
897 | pci_msi_shutdown(dev); | |
f56e4481 | 898 | free_msi_irqs(dev); |
1da177e4 | 899 | } |
4cc086fa | 900 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 901 | |
a52e2e35 | 902 | /** |
ff1aa430 | 903 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 904 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
905 | * This function returns the number of device's MSI-X table entries and |
906 | * therefore the number of MSI-X vectors device is capable of sending. | |
907 | * It returns a negative errno if the device is not capable of sending MSI-X | |
908 | * interrupts. | |
909 | **/ | |
910 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 911 | { |
a52e2e35 RW |
912 | u16 control; |
913 | ||
520fe9dc | 914 | if (!dev->msix_cap) |
ff1aa430 | 915 | return -EINVAL; |
a52e2e35 | 916 | |
f84ecd28 | 917 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 918 | return msix_table_size(control); |
a52e2e35 | 919 | } |
ff1aa430 | 920 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 921 | |
1da177e4 LT |
922 | /** |
923 | * pci_enable_msix - configure device's MSI-X capability structure | |
924 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 925 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 926 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
927 | * |
928 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 929 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
930 | * MSI-X mode enabled on its hardware device function. A return of zero |
931 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 932 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 933 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
934 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
935 | * re-send its request. | |
1da177e4 | 936 | **/ |
500559a9 | 937 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 938 | { |
5ec09405 | 939 | int nr_entries; |
ded86d8d | 940 | int i, j; |
1da177e4 | 941 | |
a06cd74c AG |
942 | if (!pci_msi_supported(dev, nvec)) |
943 | return -EINVAL; | |
c9953a73 | 944 | |
27e20603 AG |
945 | if (!entries) |
946 | return -EINVAL; | |
947 | ||
ff1aa430 AG |
948 | nr_entries = pci_msix_vec_count(dev); |
949 | if (nr_entries < 0) | |
950 | return nr_entries; | |
1da177e4 | 951 | if (nvec > nr_entries) |
57fbf52c | 952 | return nr_entries; |
1da177e4 LT |
953 | |
954 | /* Check for any invalid entries */ | |
955 | for (i = 0; i < nvec; i++) { | |
956 | if (entries[i].entry >= nr_entries) | |
957 | return -EINVAL; /* invalid entry */ | |
958 | for (j = i + 1; j < nvec; j++) { | |
959 | if (entries[i].entry == entries[j].entry) | |
960 | return -EINVAL; /* duplicate entry */ | |
961 | } | |
962 | } | |
ded86d8d | 963 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 964 | |
1ce03373 | 965 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 966 | if (dev->msi_enabled) { |
227f0647 | 967 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
968 | return -EINVAL; |
969 | } | |
5ec09405 | 970 | return msix_capability_init(dev, entries, nvec); |
1da177e4 | 971 | } |
4cc086fa | 972 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 973 | |
500559a9 | 974 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 975 | { |
12abb8ba HS |
976 | struct msi_desc *entry; |
977 | ||
128bc5fc | 978 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
979 | return; |
980 | ||
12abb8ba | 981 | /* Return the device with MSI-X masked as initial states */ |
5004e98a | 982 | for_each_pci_msi_entry(entry, dev) { |
12abb8ba | 983 | /* Keep cached states to be restored */ |
23ed8d57 | 984 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
985 | } |
986 | ||
61b64abd | 987 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 988 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 989 | dev->msix_enabled = 0; |
5f226991 | 990 | pcibios_alloc_irq(dev); |
d52877c7 | 991 | } |
c901851f | 992 | |
500559a9 | 993 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
994 | { |
995 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
996 | return; | |
997 | ||
998 | pci_msix_shutdown(dev); | |
f56e4481 | 999 | free_msi_irqs(dev); |
1da177e4 | 1000 | } |
4cc086fa | 1001 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1002 | |
309e57df MW |
1003 | void pci_no_msi(void) |
1004 | { | |
1005 | pci_msi_enable = 0; | |
1006 | } | |
c9953a73 | 1007 | |
07ae95f9 AP |
1008 | /** |
1009 | * pci_msi_enabled - is MSI enabled? | |
1010 | * | |
1011 | * Returns true if MSI has not been disabled by the command-line option | |
1012 | * pci=nomsi. | |
1013 | **/ | |
1014 | int pci_msi_enabled(void) | |
d389fec6 | 1015 | { |
07ae95f9 | 1016 | return pci_msi_enable; |
d389fec6 | 1017 | } |
07ae95f9 | 1018 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1019 | |
07ae95f9 | 1020 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1021 | { |
d389fec6 | 1022 | } |
302a2523 AG |
1023 | |
1024 | /** | |
1025 | * pci_enable_msi_range - configure device's MSI capability structure | |
1026 | * @dev: device to configure | |
1027 | * @minvec: minimal number of interrupts to configure | |
1028 | * @maxvec: maximum number of interrupts to configure | |
1029 | * | |
1030 | * This function tries to allocate a maximum possible number of interrupts in a | |
1031 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1032 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1033 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1034 | * the other interrupt numbers allocated to this device are consecutive. | |
1035 | **/ | |
1036 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1037 | { | |
034cd97e | 1038 | int nvec; |
302a2523 AG |
1039 | int rc; |
1040 | ||
a06cd74c AG |
1041 | if (!pci_msi_supported(dev, minvec)) |
1042 | return -EINVAL; | |
034cd97e AG |
1043 | |
1044 | WARN_ON(!!dev->msi_enabled); | |
1045 | ||
1046 | /* Check whether driver already requested MSI-X irqs */ | |
1047 | if (dev->msix_enabled) { | |
1048 | dev_info(&dev->dev, | |
1049 | "can't enable MSI (MSI-X already enabled)\n"); | |
1050 | return -EINVAL; | |
1051 | } | |
1052 | ||
302a2523 AG |
1053 | if (maxvec < minvec) |
1054 | return -ERANGE; | |
1055 | ||
034cd97e AG |
1056 | nvec = pci_msi_vec_count(dev); |
1057 | if (nvec < 0) | |
1058 | return nvec; | |
1059 | else if (nvec < minvec) | |
1060 | return -EINVAL; | |
1061 | else if (nvec > maxvec) | |
1062 | nvec = maxvec; | |
1063 | ||
302a2523 | 1064 | do { |
034cd97e | 1065 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1066 | if (rc < 0) { |
1067 | return rc; | |
1068 | } else if (rc > 0) { | |
1069 | if (rc < minvec) | |
1070 | return -ENOSPC; | |
1071 | nvec = rc; | |
1072 | } | |
1073 | } while (rc); | |
1074 | ||
1075 | return nvec; | |
1076 | } | |
1077 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1078 | ||
1079 | /** | |
1080 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1081 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1082 | * @entries: pointer to an array of MSI-X entries | |
1083 | * @minvec: minimum number of MSI-X irqs requested | |
1084 | * @maxvec: maximum number of MSI-X irqs requested | |
1085 | * | |
1086 | * Setup the MSI-X capability structure of device function with a maximum | |
1087 | * possible number of interrupts in the range between @minvec and @maxvec | |
1088 | * upon its software driver call to request for MSI-X mode enabled on its | |
1089 | * hardware device function. It returns a negative errno if an error occurs. | |
1090 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1091 | * indicates the successful configuration of MSI-X capability structure | |
1092 | * with new allocated MSI-X interrupts. | |
1093 | **/ | |
1094 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1095 | int minvec, int maxvec) | |
1096 | { | |
1097 | int nvec = maxvec; | |
1098 | int rc; | |
1099 | ||
1100 | if (maxvec < minvec) | |
1101 | return -ERANGE; | |
1102 | ||
1103 | do { | |
1104 | rc = pci_enable_msix(dev, entries, nvec); | |
1105 | if (rc < 0) { | |
1106 | return rc; | |
1107 | } else if (rc > 0) { | |
1108 | if (rc < minvec) | |
1109 | return -ENOSPC; | |
1110 | nvec = rc; | |
1111 | } | |
1112 | } while (rc); | |
1113 | ||
1114 | return nvec; | |
1115 | } | |
1116 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1117 | |
25a98bd4 JL |
1118 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1119 | { | |
1120 | return to_pci_dev(desc->dev); | |
1121 | } | |
1122 | ||
c179c9b9 JL |
1123 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1124 | { | |
1125 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1126 | ||
1127 | return dev->bus->sysdata; | |
1128 | } | |
1129 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1130 | ||
3878eaef JL |
1131 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1132 | /** | |
1133 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1134 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1135 | * @msg: Pointer to the message | |
1136 | */ | |
1137 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1138 | { | |
507a883e | 1139 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1140 | |
1141 | /* | |
1142 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1143 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1144 | */ | |
1145 | if (desc->irq == irq_data->irq) | |
1146 | __pci_write_msi_msg(desc, msg); | |
1147 | } | |
1148 | ||
1149 | /** | |
1150 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
1151 | * @dev: Pointer to the PCI device | |
1152 | * @desc: Pointer to the msi descriptor | |
1153 | * | |
1154 | * The ID number is only used within the irqdomain. | |
1155 | */ | |
1156 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, | |
1157 | struct msi_desc *desc) | |
1158 | { | |
1159 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | | |
1160 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | | |
1161 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; | |
1162 | } | |
1163 | ||
1164 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1165 | { | |
1166 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1167 | } | |
1168 | ||
1169 | /** | |
1170 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev | |
1171 | * @domain: The interrupt domain to check | |
1172 | * @info: The domain info for verification | |
1173 | * @dev: The device to check | |
1174 | * | |
1175 | * Returns: | |
1176 | * 0 if the functionality is supported | |
1177 | * 1 if Multi MSI is requested, but the domain does not support it | |
1178 | * -ENOTSUPP otherwise | |
1179 | */ | |
1180 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1181 | struct msi_domain_info *info, struct device *dev) | |
1182 | { | |
1183 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1184 | ||
1185 | /* Special handling to support pci_enable_msi_range() */ | |
1186 | if (pci_msi_desc_is_multi_msi(desc) && | |
1187 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1188 | return 1; | |
1189 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1190 | return -ENOTSUPP; | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1196 | struct msi_desc *desc, int error) | |
1197 | { | |
1198 | /* Special handling to support pci_enable_msi_range() */ | |
1199 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) | |
1200 | return 1; | |
1201 | ||
1202 | return error; | |
1203 | } | |
1204 | ||
1205 | #ifdef GENERIC_MSI_DOMAIN_OPS | |
1206 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, | |
1207 | struct msi_desc *desc) | |
1208 | { | |
1209 | arg->desc = desc; | |
1210 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), | |
1211 | desc); | |
1212 | } | |
1213 | #else | |
1214 | #define pci_msi_domain_set_desc NULL | |
1215 | #endif | |
1216 | ||
1217 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1218 | .set_desc = pci_msi_domain_set_desc, | |
1219 | .msi_check = pci_msi_domain_check_cap, | |
1220 | .handle_error = pci_msi_domain_handle_error, | |
1221 | }; | |
1222 | ||
1223 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1224 | { | |
1225 | struct msi_domain_ops *ops = info->ops; | |
1226 | ||
1227 | if (ops == NULL) { | |
1228 | info->ops = &pci_msi_domain_ops_default; | |
1229 | } else { | |
1230 | if (ops->set_desc == NULL) | |
1231 | ops->set_desc = pci_msi_domain_set_desc; | |
1232 | if (ops->msi_check == NULL) | |
1233 | ops->msi_check = pci_msi_domain_check_cap; | |
1234 | if (ops->handle_error == NULL) | |
1235 | ops->handle_error = pci_msi_domain_handle_error; | |
1236 | } | |
1237 | } | |
1238 | ||
1239 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1240 | { | |
1241 | struct irq_chip *chip = info->chip; | |
1242 | ||
1243 | BUG_ON(!chip); | |
1244 | if (!chip->irq_write_msi_msg) | |
1245 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1246 | if (!chip->irq_mask) |
1247 | chip->irq_mask = pci_msi_mask_irq; | |
1248 | if (!chip->irq_unmask) | |
1249 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1250 | } |
1251 | ||
1252 | /** | |
1253 | * pci_msi_create_irq_domain - Creat a MSI interrupt domain | |
1254 | * @node: Optional device-tree node of the interrupt controller | |
1255 | * @info: MSI domain info | |
1256 | * @parent: Parent irq domain | |
1257 | * | |
1258 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1259 | * | |
1260 | * Returns: | |
1261 | * A domain pointer or NULL in case of failure. | |
1262 | */ | |
1263 | struct irq_domain *pci_msi_create_irq_domain(struct device_node *node, | |
1264 | struct msi_domain_info *info, | |
1265 | struct irq_domain *parent) | |
1266 | { | |
0380839d MZ |
1267 | struct irq_domain *domain; |
1268 | ||
3878eaef JL |
1269 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1270 | pci_msi_domain_update_dom_ops(info); | |
1271 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1272 | pci_msi_domain_update_chip_ops(info); | |
1273 | ||
0380839d MZ |
1274 | domain = msi_create_irq_domain(node, info, parent); |
1275 | if (!domain) | |
1276 | return NULL; | |
1277 | ||
1278 | domain->bus_token = DOMAIN_BUS_PCI_MSI; | |
1279 | return domain; | |
3878eaef JL |
1280 | } |
1281 | ||
1282 | /** | |
1283 | * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain | |
1284 | * @domain: The interrupt domain to allocate from | |
1285 | * @dev: The device for which to allocate | |
1286 | * @nvec: The number of interrupts to allocate | |
1287 | * @type: Unused to allow simpler migration from the arch_XXX interfaces | |
1288 | * | |
1289 | * Returns: | |
1290 | * A virtual interrupt number or an error code in case of failure | |
1291 | */ | |
1292 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, | |
1293 | int nvec, int type) | |
1294 | { | |
1295 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); | |
1296 | } | |
1297 | ||
1298 | /** | |
1299 | * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain | |
1300 | * @domain: The interrupt domain | |
1301 | * @dev: The device for which to free interrupts | |
1302 | */ | |
1303 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev) | |
1304 | { | |
1305 | msi_domain_free_irqs(domain, &dev->dev); | |
1306 | } | |
8e047ada JL |
1307 | |
1308 | /** | |
1309 | * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain | |
1310 | * @node: Optional device-tree node of the interrupt controller | |
1311 | * @info: MSI domain info | |
1312 | * @parent: Parent irq domain | |
1313 | * | |
1314 | * Returns: A domain pointer or NULL in case of failure. If successful | |
1315 | * the default PCI/MSI irqdomain pointer is updated. | |
1316 | */ | |
1317 | struct irq_domain *pci_msi_create_default_irq_domain(struct device_node *node, | |
1318 | struct msi_domain_info *info, struct irq_domain *parent) | |
1319 | { | |
1320 | struct irq_domain *domain; | |
1321 | ||
1322 | mutex_lock(&pci_msi_domain_lock); | |
1323 | if (pci_msi_default_domain) { | |
1324 | pr_err("PCI: default irq domain for PCI MSI has already been created.\n"); | |
1325 | domain = NULL; | |
1326 | } else { | |
1327 | domain = pci_msi_create_irq_domain(node, info, parent); | |
1328 | pci_msi_default_domain = domain; | |
1329 | } | |
1330 | mutex_unlock(&pci_msi_domain_lock); | |
1331 | ||
1332 | return domain; | |
1333 | } | |
3878eaef | 1334 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |