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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
1da177e4 | 27 | static int pci_msi_enable = 1; |
1da177e4 | 28 | |
b1cbf4e4 EB |
29 | static void msi_set_enable(struct pci_dev *dev, int enable) |
30 | { | |
31 | int pos; | |
32 | u16 control; | |
33 | ||
34 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
35 | if (pos) { | |
36 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
37 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
38 | if (enable) | |
39 | control |= PCI_MSI_FLAGS_ENABLE; | |
40 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
41 | } | |
42 | } | |
43 | ||
44 | static void msix_set_enable(struct pci_dev *dev, int enable) | |
45 | { | |
46 | int pos; | |
47 | u16 control; | |
48 | ||
49 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
50 | if (pos) { | |
51 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
52 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
53 | if (enable) | |
54 | control |= PCI_MSIX_FLAGS_ENABLE; | |
55 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
56 | } | |
57 | } | |
58 | ||
988cbb15 MW |
59 | static void msix_flush_writes(unsigned int irq) |
60 | { | |
61 | struct msi_desc *entry; | |
62 | ||
63 | entry = get_irq_msi(irq); | |
64 | BUG_ON(!entry || !entry->dev); | |
65 | switch (entry->msi_attrib.type) { | |
66 | case PCI_CAP_ID_MSI: | |
67 | /* nothing to do */ | |
68 | break; | |
69 | case PCI_CAP_ID_MSIX: | |
70 | { | |
71 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
72 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
73 | readl(entry->mask_base + offset); | |
74 | break; | |
75 | } | |
76 | default: | |
77 | BUG(); | |
78 | break; | |
79 | } | |
80 | } | |
81 | ||
1ce03373 | 82 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
83 | { |
84 | struct msi_desc *entry; | |
85 | ||
5b912c10 | 86 | entry = get_irq_msi(irq); |
277bc33b | 87 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
88 | switch (entry->msi_attrib.type) { |
89 | case PCI_CAP_ID_MSI: | |
277bc33b | 90 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
91 | int pos; |
92 | u32 mask_bits; | |
277bc33b EB |
93 | |
94 | pos = (long)entry->mask_base; | |
95 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
96 | mask_bits &= ~(1); | |
97 | mask_bits |= flag; | |
98 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
58e0543e EB |
99 | } else { |
100 | msi_set_enable(entry->dev, !flag); | |
277bc33b | 101 | } |
1da177e4 | 102 | break; |
1da177e4 LT |
103 | case PCI_CAP_ID_MSIX: |
104 | { | |
105 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
106 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
107 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 108 | readl(entry->mask_base + offset); |
1da177e4 LT |
109 | break; |
110 | } | |
111 | default: | |
277bc33b | 112 | BUG(); |
1da177e4 LT |
113 | break; |
114 | } | |
392ee1e6 | 115 | entry->msi_attrib.masked = !!flag; |
1da177e4 LT |
116 | } |
117 | ||
3b7d1921 | 118 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 119 | { |
5b912c10 | 120 | struct msi_desc *entry = get_irq_msi(irq); |
0366f8f7 EB |
121 | switch(entry->msi_attrib.type) { |
122 | case PCI_CAP_ID_MSI: | |
123 | { | |
124 | struct pci_dev *dev = entry->dev; | |
125 | int pos = entry->msi_attrib.pos; | |
126 | u16 data; | |
127 | ||
128 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
129 | &msg->address_lo); | |
130 | if (entry->msi_attrib.is_64) { | |
131 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
132 | &msg->address_hi); | |
133 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
134 | } else { | |
135 | msg->address_hi = 0; | |
136 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
137 | } | |
138 | msg->data = data; | |
139 | break; | |
140 | } | |
141 | case PCI_CAP_ID_MSIX: | |
142 | { | |
143 | void __iomem *base; | |
144 | base = entry->mask_base + | |
145 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
146 | ||
147 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
148 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
149 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
150 | break; | |
151 | } | |
152 | default: | |
153 | BUG(); | |
154 | } | |
155 | } | |
1da177e4 | 156 | |
3b7d1921 | 157 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 158 | { |
5b912c10 | 159 | struct msi_desc *entry = get_irq_msi(irq); |
1da177e4 LT |
160 | switch (entry->msi_attrib.type) { |
161 | case PCI_CAP_ID_MSI: | |
162 | { | |
0366f8f7 EB |
163 | struct pci_dev *dev = entry->dev; |
164 | int pos = entry->msi_attrib.pos; | |
165 | ||
166 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
167 | msg->address_lo); | |
168 | if (entry->msi_attrib.is_64) { | |
169 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
170 | msg->address_hi); | |
171 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
172 | msg->data); | |
173 | } else { | |
174 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
175 | msg->data); | |
176 | } | |
1da177e4 LT |
177 | break; |
178 | } | |
179 | case PCI_CAP_ID_MSIX: | |
180 | { | |
0366f8f7 EB |
181 | void __iomem *base; |
182 | base = entry->mask_base + | |
183 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
184 | ||
185 | writel(msg->address_lo, | |
186 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
187 | writel(msg->address_hi, | |
188 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
189 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
190 | break; |
191 | } | |
192 | default: | |
0366f8f7 | 193 | BUG(); |
1da177e4 | 194 | } |
392ee1e6 | 195 | entry->msg = *msg; |
1da177e4 | 196 | } |
0366f8f7 | 197 | |
3b7d1921 | 198 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 199 | { |
1ce03373 | 200 | msi_set_mask_bit(irq, 1); |
988cbb15 | 201 | msix_flush_writes(irq); |
1da177e4 LT |
202 | } |
203 | ||
3b7d1921 | 204 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 205 | { |
1ce03373 | 206 | msi_set_mask_bit(irq, 0); |
988cbb15 | 207 | msix_flush_writes(irq); |
1da177e4 LT |
208 | } |
209 | ||
1ce03373 | 210 | static int msi_free_irq(struct pci_dev* dev, int irq); |
c54c1879 | 211 | |
1da177e4 | 212 | |
1da177e4 LT |
213 | static struct msi_desc* alloc_msi_entry(void) |
214 | { | |
215 | struct msi_desc *entry; | |
216 | ||
3e916c05 | 217 | entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); |
1da177e4 LT |
218 | if (!entry) |
219 | return NULL; | |
220 | ||
1da177e4 LT |
221 | entry->link.tail = entry->link.head = 0; /* single message */ |
222 | entry->dev = NULL; | |
223 | ||
224 | return entry; | |
225 | } | |
226 | ||
41017f0c | 227 | #ifdef CONFIG_PM |
8fed4b65 | 228 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 229 | { |
392ee1e6 | 230 | int pos; |
41017f0c | 231 | u16 control; |
392ee1e6 | 232 | struct msi_desc *entry; |
41017f0c | 233 | |
b1cbf4e4 EB |
234 | if (!dev->msi_enabled) |
235 | return; | |
236 | ||
392ee1e6 EB |
237 | entry = get_irq_msi(dev->irq); |
238 | pos = entry->msi_attrib.pos; | |
41017f0c | 239 | |
b1cbf4e4 | 240 | pci_intx(dev, 0); /* disable intx */ |
b1cbf4e4 | 241 | msi_set_enable(dev, 0); |
392ee1e6 EB |
242 | write_msi_msg(dev->irq, &entry->msg); |
243 | if (entry->msi_attrib.maskbit) | |
244 | msi_set_mask_bit(dev->irq, entry->msi_attrib.masked); | |
245 | ||
246 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
247 | control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); | |
248 | if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked) | |
249 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 250 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
251 | } |
252 | ||
253 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 254 | { |
41017f0c | 255 | int pos; |
1ce03373 | 256 | int irq, head, tail = 0; |
41017f0c | 257 | struct msi_desc *entry; |
392ee1e6 | 258 | u16 control; |
41017f0c | 259 | |
ded86d8d EB |
260 | if (!dev->msix_enabled) |
261 | return; | |
262 | ||
41017f0c | 263 | /* route the table */ |
b1cbf4e4 EB |
264 | pci_intx(dev, 0); /* disable intx */ |
265 | msix_set_enable(dev, 0); | |
ded86d8d | 266 | irq = head = dev->first_msi_irq; |
392ee1e6 EB |
267 | entry = get_irq_msi(irq); |
268 | pos = entry->msi_attrib.pos; | |
41017f0c | 269 | while (head != tail) { |
5b912c10 | 270 | entry = get_irq_msi(irq); |
392ee1e6 EB |
271 | write_msi_msg(irq, &entry->msg); |
272 | msi_set_mask_bit(irq, entry->msi_attrib.masked); | |
41017f0c | 273 | |
5b912c10 | 274 | tail = entry->link.tail; |
1ce03373 | 275 | irq = tail; |
41017f0c | 276 | } |
41017f0c | 277 | |
392ee1e6 EB |
278 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
279 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
280 | control |= PCI_MSIX_FLAGS_ENABLE; | |
281 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 282 | } |
8fed4b65 ME |
283 | |
284 | void pci_restore_msi_state(struct pci_dev *dev) | |
285 | { | |
286 | __pci_restore_msi_state(dev); | |
287 | __pci_restore_msix_state(dev); | |
288 | } | |
c54c1879 | 289 | #endif /* CONFIG_PM */ |
41017f0c | 290 | |
1da177e4 LT |
291 | /** |
292 | * msi_capability_init - configure device's MSI capability structure | |
293 | * @dev: pointer to the pci_dev data structure of MSI device function | |
294 | * | |
eaae4b3a | 295 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 296 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 297 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 298 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
299 | **/ |
300 | static int msi_capability_init(struct pci_dev *dev) | |
301 | { | |
302 | struct msi_desc *entry; | |
1ce03373 | 303 | int pos, irq; |
1da177e4 LT |
304 | u16 control; |
305 | ||
b1cbf4e4 EB |
306 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
307 | ||
1da177e4 LT |
308 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
309 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
310 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
311 | entry = alloc_msi_entry(); |
312 | if (!entry) | |
313 | return -ENOMEM; | |
1ce03373 | 314 | |
1da177e4 | 315 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 316 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
317 | entry->msi_attrib.entry_nr = 0; |
318 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 319 | entry->msi_attrib.masked = 1; |
1ce03373 | 320 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 321 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
322 | if (is_mask_bit_support(control)) { |
323 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
324 | is_64bit_address(control)); | |
325 | } | |
3b7d1921 EB |
326 | entry->dev = dev; |
327 | if (entry->msi_attrib.maskbit) { | |
328 | unsigned int maskbits, temp; | |
329 | /* All MSIs are unmasked by default, Mask them all */ | |
330 | pci_read_config_dword(dev, | |
331 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
332 | &maskbits); | |
333 | temp = (1 << multi_msi_capable(control)); | |
334 | temp = ((temp - 1) & ~temp); | |
335 | maskbits |= temp; | |
336 | pci_write_config_dword(dev, | |
337 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
338 | maskbits); | |
339 | } | |
1da177e4 | 340 | /* Configure MSI capability structure */ |
f7feaca7 EB |
341 | irq = arch_setup_msi_irq(dev, entry); |
342 | if (irq < 0) { | |
3e916c05 | 343 | kfree(entry); |
f7feaca7 | 344 | return irq; |
fd58e55f | 345 | } |
f7feaca7 EB |
346 | entry->link.head = irq; |
347 | entry->link.tail = irq; | |
ded86d8d | 348 | dev->first_msi_irq = irq; |
5b912c10 | 349 | set_irq_msi(irq, entry); |
f7feaca7 | 350 | |
1da177e4 | 351 | /* Set MSI enabled bits */ |
b1cbf4e4 EB |
352 | pci_intx(dev, 0); /* disable intx */ |
353 | msi_set_enable(dev, 1); | |
354 | dev->msi_enabled = 1; | |
1da177e4 | 355 | |
3b7d1921 | 356 | dev->irq = irq; |
1da177e4 LT |
357 | return 0; |
358 | } | |
359 | ||
360 | /** | |
361 | * msix_capability_init - configure device's MSI-X capability | |
362 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
363 | * @entries: pointer to an array of struct msix_entry entries |
364 | * @nvec: number of @entries | |
1da177e4 | 365 | * |
eaae4b3a | 366 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
367 | * single MSI-X irq. A return of zero indicates the successful setup of |
368 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
369 | **/ |
370 | static int msix_capability_init(struct pci_dev *dev, | |
371 | struct msix_entry *entries, int nvec) | |
372 | { | |
373 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
1ce03373 | 374 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
375 | unsigned long phys_addr; |
376 | u32 table_offset; | |
1da177e4 LT |
377 | u16 control; |
378 | u8 bir; | |
379 | void __iomem *base; | |
380 | ||
b1cbf4e4 EB |
381 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
382 | ||
1da177e4 LT |
383 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
384 | /* Request & Map MSI-X table region */ | |
385 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
386 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
387 | |
388 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 389 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
390 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
391 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
392 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
393 | if (base == NULL) | |
394 | return -ENOMEM; | |
395 | ||
396 | /* MSI-X Table Initialization */ | |
397 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
398 | entry = alloc_msi_entry(); |
399 | if (!entry) | |
1da177e4 | 400 | break; |
1da177e4 LT |
401 | |
402 | j = entries[i].entry; | |
1da177e4 | 403 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 404 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
405 | entry->msi_attrib.entry_nr = j; |
406 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 407 | entry->msi_attrib.masked = 1; |
1ce03373 | 408 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 409 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
410 | entry->dev = dev; |
411 | entry->mask_base = base; | |
f7feaca7 EB |
412 | |
413 | /* Configure MSI-X capability structure */ | |
414 | irq = arch_setup_msi_irq(dev, entry); | |
415 | if (irq < 0) { | |
3e916c05 | 416 | kfree(entry); |
f7feaca7 EB |
417 | break; |
418 | } | |
419 | entries[i].vector = irq; | |
1da177e4 | 420 | if (!head) { |
1ce03373 EB |
421 | entry->link.head = irq; |
422 | entry->link.tail = irq; | |
1da177e4 LT |
423 | head = entry; |
424 | } else { | |
425 | entry->link.head = temp; | |
426 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
427 | tail->link.tail = irq; |
428 | head->link.head = irq; | |
1da177e4 | 429 | } |
1ce03373 | 430 | temp = irq; |
1da177e4 | 431 | tail = entry; |
fd58e55f | 432 | |
5b912c10 | 433 | set_irq_msi(irq, entry); |
1da177e4 LT |
434 | } |
435 | if (i != nvec) { | |
92db6d10 | 436 | int avail = i - 1; |
1da177e4 LT |
437 | i--; |
438 | for (; i >= 0; i--) { | |
1ce03373 EB |
439 | irq = (entries + i)->vector; |
440 | msi_free_irq(dev, irq); | |
1da177e4 LT |
441 | (entries + i)->vector = 0; |
442 | } | |
92db6d10 EB |
443 | /* If we had some success report the number of irqs |
444 | * we succeeded in setting up. | |
445 | */ | |
446 | if (avail <= 0) | |
447 | avail = -EBUSY; | |
448 | return avail; | |
1da177e4 | 449 | } |
ded86d8d | 450 | dev->first_msi_irq = entries[0].vector; |
1da177e4 | 451 | /* Set MSI-X enabled bits */ |
b1cbf4e4 EB |
452 | pci_intx(dev, 0); /* disable intx */ |
453 | msix_set_enable(dev, 1); | |
454 | dev->msix_enabled = 1; | |
1da177e4 LT |
455 | |
456 | return 0; | |
457 | } | |
458 | ||
24334a12 | 459 | /** |
17bbc12a | 460 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 461 | * @dev: pointer to the pci_dev data structure of MSI device function |
b1e2303d | 462 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 463 | * |
0306ebfa | 464 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
465 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
466 | * supported return 0, else return an error code. | |
24334a12 | 467 | **/ |
17bbc12a | 468 | static int pci_msi_check_device(struct pci_dev * dev, int type) |
24334a12 BG |
469 | { |
470 | struct pci_bus *bus; | |
471 | ||
0306ebfa | 472 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
473 | if (!pci_msi_enable || !dev || dev->no_msi) |
474 | return -EINVAL; | |
475 | ||
0306ebfa BG |
476 | /* Any bridge which does NOT route MSI transactions from it's |
477 | * secondary bus to it's primary bus must set NO_MSI flag on | |
478 | * the secondary pci_bus. | |
479 | * We expect only arch-specific PCI host bus controller driver | |
480 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
481 | */ | |
24334a12 BG |
482 | for (bus = dev->bus; bus; bus = bus->parent) |
483 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
484 | return -EINVAL; | |
485 | ||
b1e2303d ME |
486 | if (!pci_find_capability(dev, type)) |
487 | return -EINVAL; | |
488 | ||
24334a12 BG |
489 | return 0; |
490 | } | |
491 | ||
1da177e4 LT |
492 | /** |
493 | * pci_enable_msi - configure device's MSI capability structure | |
494 | * @dev: pointer to the pci_dev data structure of MSI device function | |
495 | * | |
496 | * Setup the MSI capability structure of device function with | |
1ce03373 | 497 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
498 | * MSI mode enabled on its hardware device function. A return of zero |
499 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 500 | * irq or non-zero for otherwise. |
1da177e4 LT |
501 | **/ |
502 | int pci_enable_msi(struct pci_dev* dev) | |
503 | { | |
b1e2303d | 504 | int status; |
1da177e4 | 505 | |
17bbc12a | 506 | if (pci_msi_check_device(dev, PCI_CAP_ID_MSI)) |
1da177e4 LT |
507 | return -EINVAL; |
508 | ||
ded86d8d | 509 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 510 | |
1ce03373 | 511 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 EB |
512 | if (dev->msix_enabled) { |
513 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " | |
514 | "Device already has MSI-X enabled\n", | |
515 | pci_name(dev)); | |
516 | return -EINVAL; | |
1da177e4 LT |
517 | } |
518 | status = msi_capability_init(dev); | |
1da177e4 LT |
519 | return status; |
520 | } | |
4cc086fa | 521 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 LT |
522 | |
523 | void pci_disable_msi(struct pci_dev* dev) | |
524 | { | |
525 | struct msi_desc *entry; | |
b1cbf4e4 | 526 | int default_irq; |
1da177e4 | 527 | |
128bc5fc | 528 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
529 | return; |
530 | ||
b1cbf4e4 EB |
531 | msi_set_enable(dev, 0); |
532 | pci_intx(dev, 1); /* enable intx */ | |
533 | dev->msi_enabled = 0; | |
7bd007e4 | 534 | |
5b912c10 | 535 | entry = get_irq_msi(dev->first_msi_irq); |
1da177e4 | 536 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { |
1da177e4 LT |
537 | return; |
538 | } | |
e387b9ee | 539 | |
e387b9ee ME |
540 | default_irq = entry->msi_attrib.default_irq; |
541 | msi_free_irq(dev, dev->first_msi_irq); | |
542 | ||
543 | /* Restore dev->irq to its default pin-assertion irq */ | |
544 | dev->irq = default_irq; | |
545 | ||
ded86d8d | 546 | dev->first_msi_irq = 0; |
1da177e4 | 547 | } |
4cc086fa | 548 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 549 | |
1ce03373 | 550 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
551 | { |
552 | struct msi_desc *entry; | |
553 | int head, entry_nr, type; | |
554 | void __iomem *base; | |
1da177e4 | 555 | |
7ede9c1f ME |
556 | BUG_ON(irq_has_action(irq)); |
557 | ||
5b912c10 | 558 | entry = get_irq_msi(irq); |
1da177e4 | 559 | if (!entry || entry->dev != dev) { |
1da177e4 LT |
560 | return -EINVAL; |
561 | } | |
562 | type = entry->msi_attrib.type; | |
563 | entry_nr = entry->msi_attrib.entry_nr; | |
564 | head = entry->link.head; | |
565 | base = entry->mask_base; | |
5b912c10 EB |
566 | get_irq_msi(entry->link.head)->link.tail = entry->link.tail; |
567 | get_irq_msi(entry->link.tail)->link.head = entry->link.head; | |
1da177e4 | 568 | |
f7feaca7 | 569 | arch_teardown_msi_irq(irq); |
3e916c05 | 570 | kfree(entry); |
1da177e4 LT |
571 | |
572 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
573 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
574 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 575 | |
1ce03373 | 576 | if (head == irq) |
1da177e4 | 577 | iounmap(base); |
1da177e4 LT |
578 | } |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
1da177e4 LT |
583 | /** |
584 | * pci_enable_msix - configure device's MSI-X capability structure | |
585 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 586 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 587 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
588 | * |
589 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 590 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
591 | * MSI-X mode enabled on its hardware device function. A return of zero |
592 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 593 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 594 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 595 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
596 | * its request. |
597 | **/ | |
598 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
599 | { | |
92db6d10 | 600 | int status, pos, nr_entries; |
ded86d8d | 601 | int i, j; |
1da177e4 | 602 | u16 control; |
1da177e4 | 603 | |
17bbc12a | 604 | if (!entries || pci_msi_check_device(dev, PCI_CAP_ID_MSIX)) |
1da177e4 LT |
605 | return -EINVAL; |
606 | ||
b64c05e7 | 607 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1da177e4 | 608 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
1da177e4 LT |
609 | nr_entries = multi_msix_capable(control); |
610 | if (nvec > nr_entries) | |
611 | return -EINVAL; | |
612 | ||
613 | /* Check for any invalid entries */ | |
614 | for (i = 0; i < nvec; i++) { | |
615 | if (entries[i].entry >= nr_entries) | |
616 | return -EINVAL; /* invalid entry */ | |
617 | for (j = i + 1; j < nvec; j++) { | |
618 | if (entries[i].entry == entries[j].entry) | |
619 | return -EINVAL; /* duplicate entry */ | |
620 | } | |
621 | } | |
ded86d8d | 622 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 623 | |
1ce03373 | 624 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 625 | if (dev->msi_enabled) { |
1da177e4 | 626 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 627 | "Device already has an MSI irq assigned\n", |
1da177e4 | 628 | pci_name(dev)); |
1da177e4 LT |
629 | return -EINVAL; |
630 | } | |
1da177e4 | 631 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
632 | return status; |
633 | } | |
4cc086fa | 634 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 635 | |
fc4afc7b | 636 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 637 | { |
54bc6c0b | 638 | int irq, head, tail = 0; |
1da177e4 | 639 | |
fc4afc7b ME |
640 | irq = head = dev->first_msi_irq; |
641 | while (head != tail) { | |
642 | tail = get_irq_msi(irq)->link.tail; | |
643 | ||
fc4afc7b ME |
644 | if (irq != head) |
645 | msi_free_irq(dev, irq); | |
646 | irq = tail; | |
647 | } | |
648 | msi_free_irq(dev, irq); | |
649 | dev->first_msi_irq = 0; | |
650 | } | |
651 | ||
652 | void pci_disable_msix(struct pci_dev* dev) | |
653 | { | |
128bc5fc | 654 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
655 | return; |
656 | ||
b1cbf4e4 EB |
657 | msix_set_enable(dev, 0); |
658 | pci_intx(dev, 1); /* enable intx */ | |
659 | dev->msix_enabled = 0; | |
7bd007e4 | 660 | |
fc4afc7b | 661 | msix_free_all_irqs(dev); |
1da177e4 | 662 | } |
4cc086fa | 663 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
664 | |
665 | /** | |
1ce03373 | 666 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
667 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
668 | * | |
eaae4b3a | 669 | * Being called during hotplug remove, from which the device function |
1ce03373 | 670 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
671 | * allocated for this device function, are reclaimed to unused state, |
672 | * which may be used later on. | |
673 | **/ | |
674 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
675 | { | |
1da177e4 LT |
676 | if (!pci_msi_enable || !dev) |
677 | return; | |
678 | ||
7ede9c1f | 679 | if (dev->msi_enabled) |
c31af398 | 680 | msi_free_irq(dev, dev->first_msi_irq); |
1da177e4 | 681 | |
fc4afc7b ME |
682 | if (dev->msix_enabled) |
683 | msix_free_all_irqs(dev); | |
1da177e4 LT |
684 | } |
685 | ||
309e57df MW |
686 | void pci_no_msi(void) |
687 | { | |
688 | pci_msi_enable = 0; | |
689 | } |