]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
aff17164 | 7 | * Copyright (C) 2016 Christoph Hellwig. |
1da177e4 LT |
8 | */ |
9 | ||
1ce03373 | 10 | #include <linux/err.h> |
1da177e4 LT |
11 | #include <linux/mm.h> |
12 | #include <linux/irq.h> | |
13 | #include <linux/interrupt.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
be2021ba | 22 | #include <linux/acpi_iort.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
3878eaef | 24 | #include <linux/irqdomain.h> |
b6eec9b7 | 25 | #include <linux/of_irq.h> |
1da177e4 LT |
26 | |
27 | #include "pci.h" | |
1da177e4 | 28 | |
1da177e4 | 29 | static int pci_msi_enable = 1; |
38737d82 | 30 | int pci_msi_ignore_mask; |
1da177e4 | 31 | |
527eee29 BH |
32 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
33 | ||
8e047ada | 34 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
8e047ada JL |
35 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
36 | { | |
37 | struct irq_domain *domain; | |
38 | ||
47feb418 | 39 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 40 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 41 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); |
8e047ada JL |
42 | |
43 | return arch_setup_msi_irqs(dev, nvec, type); | |
44 | } | |
45 | ||
46 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
47 | { | |
48 | struct irq_domain *domain; | |
49 | ||
47feb418 | 50 | domain = dev_get_msi_domain(&dev->dev); |
3845d295 | 51 | if (domain && irq_domain_is_hierarchy(domain)) |
699c4cec | 52 | msi_domain_free_irqs(domain, &dev->dev); |
8e047ada JL |
53 | else |
54 | arch_teardown_msi_irqs(dev); | |
55 | } | |
56 | #else | |
57 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
58 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
59 | #endif | |
527eee29 | 60 | |
6a9e7f20 AB |
61 | /* Arch hooks */ |
62 | ||
4287d824 TP |
63 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
64 | { | |
2291ec09 | 65 | struct msi_controller *chip = dev->bus->msi; |
0cbdcfcf TR |
66 | int err; |
67 | ||
68 | if (!chip || !chip->setup_irq) | |
69 | return -EINVAL; | |
70 | ||
71 | err = chip->setup_irq(chip, dev, desc); | |
72 | if (err < 0) | |
73 | return err; | |
74 | ||
75 | irq_set_chip_data(desc->irq, chip); | |
76 | ||
77 | return 0; | |
4287d824 TP |
78 | } |
79 | ||
80 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 81 | { |
c2791b80 | 82 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
83 | |
84 | if (!chip || !chip->teardown_irq) | |
85 | return; | |
86 | ||
87 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
88 | } |
89 | ||
4287d824 | 90 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 | 91 | { |
339e5b44 | 92 | struct msi_controller *chip = dev->bus->msi; |
6a9e7f20 AB |
93 | struct msi_desc *entry; |
94 | int ret; | |
95 | ||
339e5b44 LS |
96 | if (chip && chip->setup_irqs) |
97 | return chip->setup_irqs(chip, dev, nvec, type); | |
1c8d7b0a MW |
98 | /* |
99 | * If an architecture wants to support multiple MSI, it needs to | |
100 | * override arch_setup_msi_irqs() | |
101 | */ | |
102 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
103 | return 1; | |
104 | ||
5004e98a | 105 | for_each_pci_msi_entry(entry, dev) { |
6a9e7f20 | 106 | ret = arch_setup_msi_irq(dev, entry); |
b5fbf533 | 107 | if (ret < 0) |
6a9e7f20 | 108 | return ret; |
b5fbf533 ME |
109 | if (ret > 0) |
110 | return -ENOSPC; | |
6a9e7f20 AB |
111 | } |
112 | ||
113 | return 0; | |
114 | } | |
1525bf0d | 115 | |
4287d824 TP |
116 | /* |
117 | * We have a default implementation available as a separate non-weak | |
118 | * function, as it is used by the Xen x86 PCI code | |
119 | */ | |
1525bf0d | 120 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 121 | { |
63a7b17e | 122 | int i; |
6a9e7f20 AB |
123 | struct msi_desc *entry; |
124 | ||
5004e98a | 125 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
126 | if (entry->irq) |
127 | for (i = 0; i < entry->nvec_used; i++) | |
128 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
129 | } |
130 | ||
4287d824 TP |
131 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
132 | { | |
133 | return default_teardown_msi_irqs(dev); | |
134 | } | |
76ccc297 | 135 | |
ac8344c4 | 136 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
137 | { |
138 | struct msi_desc *entry; | |
139 | ||
140 | entry = NULL; | |
141 | if (dev->msix_enabled) { | |
5004e98a | 142 | for_each_pci_msi_entry(entry, dev) { |
76ccc297 KRW |
143 | if (irq == entry->irq) |
144 | break; | |
145 | } | |
146 | } else if (dev->msi_enabled) { | |
147 | entry = irq_get_msi_desc(irq); | |
148 | } | |
149 | ||
150 | if (entry) | |
83a18912 | 151 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 152 | } |
4287d824 | 153 | |
ac8344c4 | 154 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 155 | { |
ac8344c4 | 156 | return default_restore_msi_irqs(dev); |
4287d824 | 157 | } |
76ccc297 | 158 | |
bffac3c5 MW |
159 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
160 | { | |
0b49ec37 MW |
161 | /* Don't shift by >= width of type */ |
162 | if (x >= 5) | |
163 | return 0xffffffff; | |
164 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
165 | } |
166 | ||
ce6fce42 MW |
167 | /* |
168 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
169 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
170 | * reliably as devices without an INTx disable bit will then generate a | |
171 | * level IRQ which will never be cleared. | |
ce6fce42 | 172 | */ |
23ed8d57 | 173 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 174 | { |
f2440d9a | 175 | u32 mask_bits = desc->masked; |
1da177e4 | 176 | |
38737d82 | 177 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 178 | return 0; |
f2440d9a MW |
179 | |
180 | mask_bits &= ~mask; | |
181 | mask_bits |= flag; | |
e39758e0 JL |
182 | pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos, |
183 | mask_bits); | |
12abb8ba HS |
184 | |
185 | return mask_bits; | |
186 | } | |
187 | ||
188 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
189 | { | |
23ed8d57 | 190 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
191 | } |
192 | ||
5eb6d660 CH |
193 | static void __iomem *pci_msix_desc_addr(struct msi_desc *desc) |
194 | { | |
195 | return desc->mask_base + | |
196 | desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
197 | } | |
198 | ||
f2440d9a MW |
199 | /* |
200 | * This internal function does not flush PCI writes to the device. | |
201 | * All users must ensure that they read from the device before either | |
202 | * assuming that the device state is up to date, or returning out of this | |
203 | * file. This saves a few milliseconds when initialising devices with lots | |
204 | * of MSI-X interrupts. | |
205 | */ | |
23ed8d57 | 206 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
207 | { |
208 | u32 mask_bits = desc->masked; | |
38737d82 YW |
209 | |
210 | if (pci_msi_ignore_mask) | |
211 | return 0; | |
212 | ||
8d805286 SY |
213 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
214 | if (flag) | |
215 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
5eb6d660 | 216 | writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL); |
12abb8ba HS |
217 | |
218 | return mask_bits; | |
219 | } | |
220 | ||
221 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
222 | { | |
23ed8d57 | 223 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 224 | } |
24d27553 | 225 | |
1c9db525 | 226 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 227 | { |
c391f262 | 228 | struct msi_desc *desc = irq_data_get_msi_desc(data); |
24d27553 | 229 | |
f2440d9a MW |
230 | if (desc->msi_attrib.is_msix) { |
231 | msix_mask_irq(desc, flag); | |
232 | readl(desc->mask_base); /* Flush write to device */ | |
233 | } else { | |
a281b788 | 234 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 235 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 236 | } |
f2440d9a MW |
237 | } |
238 | ||
23ed8d57 TG |
239 | /** |
240 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts | |
241 | * @data: pointer to irqdata associated to that interrupt | |
242 | */ | |
243 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 244 | { |
1c9db525 | 245 | msi_set_mask_bit(data, 1); |
f2440d9a | 246 | } |
a4289dc2 | 247 | EXPORT_SYMBOL_GPL(pci_msi_mask_irq); |
f2440d9a | 248 | |
23ed8d57 TG |
249 | /** |
250 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts | |
251 | * @data: pointer to irqdata associated to that interrupt | |
252 | */ | |
253 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 254 | { |
1c9db525 | 255 | msi_set_mask_bit(data, 0); |
1da177e4 | 256 | } |
a4289dc2 | 257 | EXPORT_SYMBOL_GPL(pci_msi_unmask_irq); |
1da177e4 | 258 | |
ac8344c4 D |
259 | void default_restore_msi_irqs(struct pci_dev *dev) |
260 | { | |
261 | struct msi_desc *entry; | |
262 | ||
5004e98a | 263 | for_each_pci_msi_entry(entry, dev) |
ac8344c4 | 264 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
265 | } |
266 | ||
891d4a48 | 267 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 268 | { |
e39758e0 JL |
269 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
270 | ||
271 | BUG_ON(dev->current_state != PCI_D0); | |
30da5524 BH |
272 | |
273 | if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 274 | void __iomem *base = pci_msix_desc_addr(entry); |
30da5524 BH |
275 | |
276 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
277 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
278 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
279 | } else { | |
f5322169 | 280 | int pos = dev->msi_cap; |
30da5524 BH |
281 | u16 data; |
282 | ||
9925ad0c BH |
283 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
284 | &msg->address_lo); | |
30da5524 | 285 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
286 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
287 | &msg->address_hi); | |
2f221349 | 288 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
289 | } else { |
290 | msg->address_hi = 0; | |
2f221349 | 291 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
292 | } |
293 | msg->data = data; | |
294 | } | |
295 | } | |
296 | ||
83a18912 | 297 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 298 | { |
e39758e0 JL |
299 | struct pci_dev *dev = msi_desc_to_pci_dev(entry); |
300 | ||
0170591b | 301 | if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) { |
fcd097f3 BH |
302 | /* Don't touch the hardware now */ |
303 | } else if (entry->msi_attrib.is_msix) { | |
5eb6d660 | 304 | void __iomem *base = pci_msix_desc_addr(entry); |
24d27553 | 305 | |
2c21fd4b HS |
306 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
307 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
308 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 309 | } else { |
f5322169 | 310 | int pos = dev->msi_cap; |
1c8d7b0a MW |
311 | u16 msgctl; |
312 | ||
f84ecd28 | 313 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
314 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
315 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 316 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 317 | |
9925ad0c BH |
318 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
319 | msg->address_lo); | |
0366f8f7 | 320 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
321 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
322 | msg->address_hi); | |
2f221349 BH |
323 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
324 | msg->data); | |
0366f8f7 | 325 | } else { |
2f221349 BH |
326 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
327 | msg->data); | |
0366f8f7 | 328 | } |
1da177e4 | 329 | } |
392ee1e6 | 330 | entry->msg = *msg; |
1da177e4 | 331 | } |
0366f8f7 | 332 | |
83a18912 | 333 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 334 | { |
dced35ae | 335 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 336 | |
83a18912 | 337 | __pci_write_msi_msg(entry, msg); |
3145e941 | 338 | } |
83a18912 | 339 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 340 | |
f56e4481 HS |
341 | static void free_msi_irqs(struct pci_dev *dev) |
342 | { | |
5004e98a | 343 | struct list_head *msi_list = dev_to_msi_list(&dev->dev); |
f56e4481 | 344 | struct msi_desc *entry, *tmp; |
1c51b50c GKH |
345 | struct attribute **msi_attrs; |
346 | struct device_attribute *dev_attr; | |
63a7b17e | 347 | int i, count = 0; |
f56e4481 | 348 | |
5004e98a | 349 | for_each_pci_msi_entry(entry, dev) |
63a7b17e JL |
350 | if (entry->irq) |
351 | for (i = 0; i < entry->nvec_used; i++) | |
352 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 353 | |
8e047ada | 354 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 | 355 | |
5004e98a | 356 | list_for_each_entry_safe(entry, tmp, msi_list, list) { |
f56e4481 | 357 | if (entry->msi_attrib.is_msix) { |
5004e98a | 358 | if (list_is_last(&entry->list, msi_list)) |
f56e4481 HS |
359 | iounmap(entry->mask_base); |
360 | } | |
424eb391 | 361 | |
f56e4481 | 362 | list_del(&entry->list); |
81efbadd | 363 | free_msi_entry(entry); |
f56e4481 | 364 | } |
1c51b50c GKH |
365 | |
366 | if (dev->msi_irq_groups) { | |
367 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
368 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 369 | while (msi_attrs[count]) { |
1c51b50c GKH |
370 | dev_attr = container_of(msi_attrs[count], |
371 | struct device_attribute, attr); | |
372 | kfree(dev_attr->attr.name); | |
373 | kfree(dev_attr); | |
374 | ++count; | |
375 | } | |
376 | kfree(msi_attrs); | |
377 | kfree(dev->msi_irq_groups[0]); | |
378 | kfree(dev->msi_irq_groups); | |
379 | dev->msi_irq_groups = NULL; | |
380 | } | |
f56e4481 | 381 | } |
c54c1879 | 382 | |
ba698ad4 DM |
383 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
384 | { | |
385 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
386 | pci_intx(dev, enable); | |
387 | } | |
388 | ||
8fed4b65 | 389 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 390 | { |
41017f0c | 391 | u16 control; |
392ee1e6 | 392 | struct msi_desc *entry; |
41017f0c | 393 | |
b1cbf4e4 EB |
394 | if (!dev->msi_enabled) |
395 | return; | |
396 | ||
dced35ae | 397 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 398 | |
ba698ad4 | 399 | pci_intx_for_msi(dev, 0); |
61b64abd | 400 | pci_msi_set_enable(dev, 0); |
ac8344c4 | 401 | arch_restore_msi_irqs(dev); |
392ee1e6 | 402 | |
f5322169 | 403 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
404 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
405 | entry->masked); | |
abad2ec9 | 406 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 407 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 408 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
409 | } |
410 | ||
411 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 412 | { |
41017f0c | 413 | struct msi_desc *entry; |
41017f0c | 414 | |
ded86d8d EB |
415 | if (!dev->msix_enabled) |
416 | return; | |
5004e98a | 417 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
ded86d8d | 418 | |
41017f0c | 419 | /* route the table */ |
ba698ad4 | 420 | pci_intx_for_msi(dev, 0); |
61b64abd | 421 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 422 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); |
41017f0c | 423 | |
ac8344c4 | 424 | arch_restore_msi_irqs(dev); |
5004e98a | 425 | for_each_pci_msi_entry(entry, dev) |
f2440d9a | 426 | msix_mask_irq(entry, entry->masked); |
41017f0c | 427 | |
61b64abd | 428 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 429 | } |
8fed4b65 ME |
430 | |
431 | void pci_restore_msi_state(struct pci_dev *dev) | |
432 | { | |
433 | __pci_restore_msi_state(dev); | |
434 | __pci_restore_msix_state(dev); | |
435 | } | |
94688cf2 | 436 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 437 | |
1c51b50c | 438 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
439 | char *buf) |
440 | { | |
1c51b50c GKH |
441 | struct msi_desc *entry; |
442 | unsigned long irq; | |
443 | int retval; | |
da8d1c8b | 444 | |
1c51b50c GKH |
445 | retval = kstrtoul(attr->attr.name, 10, &irq); |
446 | if (retval) | |
447 | return retval; | |
da8d1c8b | 448 | |
e11ece5a YW |
449 | entry = irq_get_msi_desc(irq); |
450 | if (entry) | |
451 | return sprintf(buf, "%s\n", | |
452 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
453 | ||
1c51b50c | 454 | return -ENODEV; |
da8d1c8b NH |
455 | } |
456 | ||
da8d1c8b NH |
457 | static int populate_msi_sysfs(struct pci_dev *pdev) |
458 | { | |
1c51b50c GKH |
459 | struct attribute **msi_attrs; |
460 | struct attribute *msi_attr; | |
461 | struct device_attribute *msi_dev_attr; | |
462 | struct attribute_group *msi_irq_group; | |
463 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 464 | struct msi_desc *entry; |
1c51b50c GKH |
465 | int ret = -ENOMEM; |
466 | int num_msi = 0; | |
da8d1c8b | 467 | int count = 0; |
a8676066 | 468 | int i; |
da8d1c8b | 469 | |
1c51b50c | 470 | /* Determine how many msi entries we have */ |
5004e98a | 471 | for_each_pci_msi_entry(entry, pdev) |
a8676066 | 472 | num_msi += entry->nvec_used; |
1c51b50c GKH |
473 | if (!num_msi) |
474 | return 0; | |
da8d1c8b | 475 | |
1c51b50c GKH |
476 | /* Dynamically create the MSI attributes for the PCI device */ |
477 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
478 | if (!msi_attrs) | |
479 | return -ENOMEM; | |
5004e98a | 480 | for_each_pci_msi_entry(entry, pdev) { |
a8676066 RB |
481 | for (i = 0; i < entry->nvec_used; i++) { |
482 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); | |
483 | if (!msi_dev_attr) | |
484 | goto error_attrs; | |
485 | msi_attrs[count] = &msi_dev_attr->attr; | |
486 | ||
487 | sysfs_attr_init(&msi_dev_attr->attr); | |
488 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", | |
489 | entry->irq + i); | |
490 | if (!msi_dev_attr->attr.name) | |
491 | goto error_attrs; | |
492 | msi_dev_attr->attr.mode = S_IRUGO; | |
493 | msi_dev_attr->show = msi_mode_show; | |
494 | ++count; | |
495 | } | |
da8d1c8b NH |
496 | } |
497 | ||
1c51b50c GKH |
498 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
499 | if (!msi_irq_group) | |
500 | goto error_attrs; | |
501 | msi_irq_group->name = "msi_irqs"; | |
502 | msi_irq_group->attrs = msi_attrs; | |
503 | ||
504 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
505 | if (!msi_irq_groups) | |
506 | goto error_irq_group; | |
507 | msi_irq_groups[0] = msi_irq_group; | |
508 | ||
509 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
510 | if (ret) | |
511 | goto error_irq_groups; | |
512 | pdev->msi_irq_groups = msi_irq_groups; | |
513 | ||
da8d1c8b NH |
514 | return 0; |
515 | ||
1c51b50c GKH |
516 | error_irq_groups: |
517 | kfree(msi_irq_groups); | |
518 | error_irq_group: | |
519 | kfree(msi_irq_group); | |
520 | error_attrs: | |
521 | count = 0; | |
522 | msi_attr = msi_attrs[count]; | |
523 | while (msi_attr) { | |
524 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
525 | kfree(msi_attr->name); | |
526 | kfree(msi_dev_attr); | |
527 | ++count; | |
528 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 529 | } |
29237756 | 530 | kfree(msi_attrs); |
da8d1c8b NH |
531 | return ret; |
532 | } | |
533 | ||
e75eafb9 | 534 | static struct msi_desc * |
61e1c590 | 535 | msi_setup_entry(struct pci_dev *dev, int nvec, const struct irq_affinity *affd) |
d873b4d4 | 536 | { |
e75eafb9 | 537 | struct cpumask *masks = NULL; |
d873b4d4 | 538 | struct msi_desc *entry; |
e75eafb9 TG |
539 | u16 control; |
540 | ||
61e1c590 CH |
541 | if (affd) { |
542 | masks = irq_create_affinity_masks(nvec, affd); | |
e75eafb9 | 543 | if (!masks) |
4bb66691 BH |
544 | dev_err(&dev->dev, "can't allocate MSI affinity masks for %d vectors\n", |
545 | nvec); | |
e75eafb9 | 546 | } |
d873b4d4 YW |
547 | |
548 | /* MSI Entry Initialization */ | |
e75eafb9 | 549 | entry = alloc_msi_entry(&dev->dev, nvec, masks); |
d873b4d4 | 550 | if (!entry) |
e75eafb9 | 551 | goto out; |
d873b4d4 YW |
552 | |
553 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
554 | ||
555 | entry->msi_attrib.is_msix = 0; | |
556 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
557 | entry->msi_attrib.entry_nr = 0; | |
558 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
559 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 560 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e | 561 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
d873b4d4 YW |
562 | |
563 | if (control & PCI_MSI_FLAGS_64BIT) | |
564 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
565 | else | |
566 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
567 | ||
568 | /* Save the initial mask status */ | |
569 | if (entry->msi_attrib.maskbit) | |
570 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
571 | ||
e75eafb9 TG |
572 | out: |
573 | kfree(masks); | |
d873b4d4 YW |
574 | return entry; |
575 | } | |
576 | ||
f144d149 BH |
577 | static int msi_verify_entries(struct pci_dev *dev) |
578 | { | |
579 | struct msi_desc *entry; | |
580 | ||
5004e98a | 581 | for_each_pci_msi_entry(entry, dev) { |
f144d149 BH |
582 | if (!dev->no_64bit_msi || !entry->msg.address_hi) |
583 | continue; | |
584 | dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" | |
585 | " tried to assign one above 4G\n"); | |
586 | return -EIO; | |
587 | } | |
588 | return 0; | |
589 | } | |
590 | ||
1da177e4 LT |
591 | /** |
592 | * msi_capability_init - configure device's MSI capability structure | |
593 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 594 | * @nvec: number of interrupts to allocate |
dadf1733 | 595 | * @affd: description of automatic irq affinity assignments (may be %NULL) |
1da177e4 | 596 | * |
1c8d7b0a MW |
597 | * Setup the MSI capability structure of the device with the requested |
598 | * number of interrupts. A return value of zero indicates the successful | |
599 | * setup of an entry with the new MSI irq. A negative return value indicates | |
600 | * an error, and a positive return value indicates the number of interrupts | |
601 | * which could have been allocated. | |
602 | */ | |
61e1c590 CH |
603 | static int msi_capability_init(struct pci_dev *dev, int nvec, |
604 | const struct irq_affinity *affd) | |
1da177e4 LT |
605 | { |
606 | struct msi_desc *entry; | |
f465136d | 607 | int ret; |
f2440d9a | 608 | unsigned mask; |
1da177e4 | 609 | |
61b64abd | 610 | pci_msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 611 | |
61e1c590 | 612 | entry = msi_setup_entry(dev, nvec, affd); |
f7feaca7 EB |
613 | if (!entry) |
614 | return -ENOMEM; | |
1ce03373 | 615 | |
f2440d9a | 616 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 617 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
618 | msi_mask_irq(entry, mask, mask); |
619 | ||
5004e98a | 620 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
9c831334 | 621 | |
1da177e4 | 622 | /* Configure MSI capability structure */ |
8e047ada | 623 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 624 | if (ret) { |
7ba1930d | 625 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 626 | free_msi_irqs(dev); |
7fe3730d | 627 | return ret; |
fd58e55f | 628 | } |
f7feaca7 | 629 | |
f144d149 BH |
630 | ret = msi_verify_entries(dev); |
631 | if (ret) { | |
632 | msi_mask_irq(entry, mask, ~mask); | |
633 | free_msi_irqs(dev); | |
634 | return ret; | |
635 | } | |
636 | ||
da8d1c8b NH |
637 | ret = populate_msi_sysfs(dev); |
638 | if (ret) { | |
639 | msi_mask_irq(entry, mask, ~mask); | |
640 | free_msi_irqs(dev); | |
641 | return ret; | |
642 | } | |
643 | ||
1da177e4 | 644 | /* Set MSI enabled bits */ |
ba698ad4 | 645 | pci_intx_for_msi(dev, 0); |
61b64abd | 646 | pci_msi_set_enable(dev, 1); |
b1cbf4e4 | 647 | dev->msi_enabled = 1; |
1da177e4 | 648 | |
5f226991 | 649 | pcibios_free_irq(dev); |
7fe3730d | 650 | dev->irq = entry->irq; |
1da177e4 LT |
651 | return 0; |
652 | } | |
653 | ||
520fe9dc | 654 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 655 | { |
4302e0fb | 656 | resource_size_t phys_addr; |
5a05a9d8 | 657 | u32 table_offset; |
6a878e50 | 658 | unsigned long flags; |
5a05a9d8 HS |
659 | u8 bir; |
660 | ||
909094c6 BH |
661 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
662 | &table_offset); | |
4d18760c | 663 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
6a878e50 YW |
664 | flags = pci_resource_flags(dev, bir); |
665 | if (!flags || (flags & IORESOURCE_UNSET)) | |
666 | return NULL; | |
667 | ||
4d18760c | 668 | table_offset &= PCI_MSIX_TABLE_OFFSET; |
5a05a9d8 HS |
669 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
670 | ||
671 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
672 | } | |
673 | ||
520fe9dc | 674 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
e75eafb9 | 675 | struct msix_entry *entries, int nvec, |
61e1c590 | 676 | const struct irq_affinity *affd) |
d9d7070e | 677 | { |
e75eafb9 | 678 | struct cpumask *curmsk, *masks = NULL; |
d9d7070e | 679 | struct msi_desc *entry; |
e75eafb9 | 680 | int ret, i; |
4ef33685 | 681 | |
61e1c590 CH |
682 | if (affd) { |
683 | masks = irq_create_affinity_masks(nvec, affd); | |
e75eafb9 | 684 | if (!masks) |
4bb66691 BH |
685 | dev_err(&dev->dev, "can't allocate MSI-X affinity masks for %d vectors\n", |
686 | nvec); | |
e75eafb9 | 687 | } |
4ef33685 | 688 | |
e75eafb9 TG |
689 | for (i = 0, curmsk = masks; i < nvec; i++) { |
690 | entry = alloc_msi_entry(&dev->dev, 1, curmsk); | |
d9d7070e HS |
691 | if (!entry) { |
692 | if (!i) | |
693 | iounmap(base); | |
694 | else | |
695 | free_msi_irqs(dev); | |
696 | /* No enough memory. Don't try again */ | |
e75eafb9 TG |
697 | ret = -ENOMEM; |
698 | goto out; | |
d9d7070e HS |
699 | } |
700 | ||
701 | entry->msi_attrib.is_msix = 1; | |
702 | entry->msi_attrib.is_64 = 1; | |
3ac020e0 CH |
703 | if (entries) |
704 | entry->msi_attrib.entry_nr = entries[i].entry; | |
705 | else | |
706 | entry->msi_attrib.entry_nr = i; | |
d9d7070e | 707 | entry->msi_attrib.default_irq = dev->irq; |
d9d7070e HS |
708 | entry->mask_base = base; |
709 | ||
5004e98a | 710 | list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); |
e75eafb9 TG |
711 | if (masks) |
712 | curmsk++; | |
d9d7070e | 713 | } |
e75eafb9 TG |
714 | ret = 0; |
715 | out: | |
716 | kfree(masks); | |
3adfb572 | 717 | return ret; |
d9d7070e HS |
718 | } |
719 | ||
75cb3426 | 720 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 721 | struct msix_entry *entries) |
75cb3426 HS |
722 | { |
723 | struct msi_desc *entry; | |
724 | int i = 0; | |
725 | ||
5004e98a | 726 | for_each_pci_msi_entry(entry, dev) { |
3ac020e0 CH |
727 | if (entries) |
728 | entries[i++].vector = entry->irq; | |
12eb21de CH |
729 | entry->masked = readl(pci_msix_desc_addr(entry) + |
730 | PCI_MSIX_ENTRY_VECTOR_CTRL); | |
75cb3426 | 731 | msix_mask_irq(entry, 1); |
75cb3426 HS |
732 | } |
733 | } | |
734 | ||
1da177e4 LT |
735 | /** |
736 | * msix_capability_init - configure device's MSI-X capability | |
737 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
738 | * @entries: pointer to an array of struct msix_entry entries |
739 | * @nvec: number of @entries | |
61e1c590 | 740 | * @affd: Optional pointer to enable automatic affinity assignement |
1da177e4 | 741 | * |
eaae4b3a | 742 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
743 | * single MSI-X irq. A return of zero indicates the successful setup of |
744 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 | 745 | **/ |
e75eafb9 | 746 | static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries, |
61e1c590 | 747 | int nvec, const struct irq_affinity *affd) |
1da177e4 | 748 | { |
520fe9dc | 749 | int ret; |
5a05a9d8 | 750 | u16 control; |
1da177e4 LT |
751 | void __iomem *base; |
752 | ||
f598282f | 753 | /* Ensure MSI-X is disabled while it is set up */ |
61b64abd | 754 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 755 | |
66f0d0c4 | 756 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 757 | /* Request & Map MSI-X table region */ |
527eee29 | 758 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 759 | if (!base) |
1da177e4 LT |
760 | return -ENOMEM; |
761 | ||
61e1c590 | 762 | ret = msix_setup_entries(dev, base, entries, nvec, affd); |
d9d7070e HS |
763 | if (ret) |
764 | return ret; | |
9c831334 | 765 | |
8e047ada | 766 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 767 | if (ret) |
2adc7907 | 768 | goto out_avail; |
9c831334 | 769 | |
f144d149 BH |
770 | /* Check if all MSI entries honor device restrictions */ |
771 | ret = msi_verify_entries(dev); | |
772 | if (ret) | |
773 | goto out_free; | |
774 | ||
f598282f MW |
775 | /* |
776 | * Some devices require MSI-X to be enabled before we can touch the | |
777 | * MSI-X registers. We need to mask all the vectors to prevent | |
778 | * interrupts coming in before they're fully set up. | |
779 | */ | |
61b64abd | 780 | pci_msix_clear_and_set_ctrl(dev, 0, |
66f0d0c4 | 781 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); |
f598282f | 782 | |
75cb3426 | 783 | msix_program_entries(dev, entries); |
f598282f | 784 | |
da8d1c8b | 785 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
786 | if (ret) |
787 | goto out_free; | |
da8d1c8b | 788 | |
f598282f | 789 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 790 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 791 | dev->msix_enabled = 1; |
61b64abd | 792 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 793 | |
5f226991 | 794 | pcibios_free_irq(dev); |
1da177e4 | 795 | return 0; |
583871d4 | 796 | |
2adc7907 | 797 | out_avail: |
583871d4 HS |
798 | if (ret < 0) { |
799 | /* | |
800 | * If we had some success, report the number of irqs | |
801 | * we succeeded in setting up. | |
802 | */ | |
d9d7070e | 803 | struct msi_desc *entry; |
583871d4 HS |
804 | int avail = 0; |
805 | ||
5004e98a | 806 | for_each_pci_msi_entry(entry, dev) { |
583871d4 HS |
807 | if (entry->irq != 0) |
808 | avail++; | |
809 | } | |
810 | if (avail != 0) | |
811 | ret = avail; | |
812 | } | |
813 | ||
2adc7907 | 814 | out_free: |
583871d4 HS |
815 | free_msi_irqs(dev); |
816 | ||
817 | return ret; | |
1da177e4 LT |
818 | } |
819 | ||
24334a12 | 820 | /** |
a06cd74c | 821 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 822 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 823 | * @nvec: how many MSIs have been requested ? |
24334a12 | 824 | * |
f7625980 | 825 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 826 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 827 | * supported return 1, else return 0. |
24334a12 | 828 | **/ |
a06cd74c | 829 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
830 | { |
831 | struct pci_bus *bus; | |
832 | ||
0306ebfa | 833 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 834 | if (!pci_msi_enable) |
a06cd74c | 835 | return 0; |
27e20603 AG |
836 | |
837 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 838 | return 0; |
24334a12 | 839 | |
314e77b3 ME |
840 | /* |
841 | * You can't ask to have 0 or less MSIs configured. | |
842 | * a) it's stupid .. | |
843 | * b) the list manipulation code assumes nvec >= 1. | |
844 | */ | |
845 | if (nvec < 1) | |
a06cd74c | 846 | return 0; |
314e77b3 | 847 | |
500559a9 HS |
848 | /* |
849 | * Any bridge which does NOT route MSI transactions from its | |
850 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
851 | * the secondary pci_bus. |
852 | * We expect only arch-specific PCI host bus controller driver | |
853 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
854 | */ | |
24334a12 BG |
855 | for (bus = dev->bus; bus; bus = bus->parent) |
856 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 857 | return 0; |
24334a12 | 858 | |
a06cd74c | 859 | return 1; |
24334a12 BG |
860 | } |
861 | ||
d1ac1d26 AG |
862 | /** |
863 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
864 | * @dev: device to report about | |
865 | * | |
866 | * This function returns the number of MSI vectors a device requested via | |
867 | * Multiple Message Capable register. It returns a negative errno if the | |
868 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
869 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
870 | * MSI specification. | |
871 | **/ | |
872 | int pci_msi_vec_count(struct pci_dev *dev) | |
873 | { | |
874 | int ret; | |
875 | u16 msgctl; | |
876 | ||
877 | if (!dev->msi_cap) | |
878 | return -EINVAL; | |
879 | ||
880 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
881 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
882 | ||
883 | return ret; | |
884 | } | |
885 | EXPORT_SYMBOL(pci_msi_vec_count); | |
886 | ||
688769f6 | 887 | static void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 888 | { |
f2440d9a MW |
889 | struct msi_desc *desc; |
890 | u32 mask; | |
1da177e4 | 891 | |
128bc5fc | 892 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
893 | return; |
894 | ||
5004e98a | 895 | BUG_ON(list_empty(dev_to_msi_list(&dev->dev))); |
4a7cc831 | 896 | desc = first_pci_msi_entry(dev); |
110828c9 | 897 | |
61b64abd | 898 | pci_msi_set_enable(dev, 0); |
ba698ad4 | 899 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 900 | dev->msi_enabled = 0; |
7bd007e4 | 901 | |
12abb8ba | 902 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 903 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 904 | /* Keep cached state to be restored */ |
23ed8d57 | 905 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
906 | |
907 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 908 | dev->irq = desc->msi_attrib.default_irq; |
5f226991 | 909 | pcibios_alloc_irq(dev); |
d52877c7 | 910 | } |
24d27553 | 911 | |
500559a9 | 912 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 913 | { |
d52877c7 YL |
914 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
915 | return; | |
916 | ||
917 | pci_msi_shutdown(dev); | |
f56e4481 | 918 | free_msi_irqs(dev); |
1da177e4 | 919 | } |
4cc086fa | 920 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 921 | |
a52e2e35 | 922 | /** |
ff1aa430 | 923 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 924 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
925 | * This function returns the number of device's MSI-X table entries and |
926 | * therefore the number of MSI-X vectors device is capable of sending. | |
927 | * It returns a negative errno if the device is not capable of sending MSI-X | |
928 | * interrupts. | |
929 | **/ | |
930 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 931 | { |
a52e2e35 RW |
932 | u16 control; |
933 | ||
520fe9dc | 934 | if (!dev->msix_cap) |
ff1aa430 | 935 | return -EINVAL; |
a52e2e35 | 936 | |
f84ecd28 | 937 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 938 | return msix_table_size(control); |
a52e2e35 | 939 | } |
ff1aa430 | 940 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 941 | |
e75eafb9 | 942 | static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, |
61e1c590 | 943 | int nvec, const struct irq_affinity *affd) |
1da177e4 | 944 | { |
5ec09405 | 945 | int nr_entries; |
ded86d8d | 946 | int i, j; |
1da177e4 | 947 | |
a06cd74c AG |
948 | if (!pci_msi_supported(dev, nvec)) |
949 | return -EINVAL; | |
c9953a73 | 950 | |
ff1aa430 AG |
951 | nr_entries = pci_msix_vec_count(dev); |
952 | if (nr_entries < 0) | |
953 | return nr_entries; | |
1da177e4 | 954 | if (nvec > nr_entries) |
57fbf52c | 955 | return nr_entries; |
1da177e4 | 956 | |
3ac020e0 CH |
957 | if (entries) { |
958 | /* Check for any invalid entries */ | |
959 | for (i = 0; i < nvec; i++) { | |
960 | if (entries[i].entry >= nr_entries) | |
961 | return -EINVAL; /* invalid entry */ | |
962 | for (j = i + 1; j < nvec; j++) { | |
963 | if (entries[i].entry == entries[j].entry) | |
964 | return -EINVAL; /* duplicate entry */ | |
965 | } | |
1da177e4 LT |
966 | } |
967 | } | |
ded86d8d | 968 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 969 | |
1ce03373 | 970 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 971 | if (dev->msi_enabled) { |
227f0647 | 972 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
973 | return -EINVAL; |
974 | } | |
61e1c590 | 975 | return msix_capability_init(dev, entries, nvec, affd); |
e75eafb9 TG |
976 | } |
977 | ||
688769f6 | 978 | static void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 979 | { |
12abb8ba HS |
980 | struct msi_desc *entry; |
981 | ||
128bc5fc | 982 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
983 | return; |
984 | ||
0170591b KB |
985 | if (pci_dev_is_disconnected(dev)) { |
986 | dev->msix_enabled = 0; | |
987 | return; | |
988 | } | |
989 | ||
12abb8ba | 990 | /* Return the device with MSI-X masked as initial states */ |
5004e98a | 991 | for_each_pci_msi_entry(entry, dev) { |
12abb8ba | 992 | /* Keep cached states to be restored */ |
23ed8d57 | 993 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
994 | } |
995 | ||
61b64abd | 996 | pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 997 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 998 | dev->msix_enabled = 0; |
5f226991 | 999 | pcibios_alloc_irq(dev); |
d52877c7 | 1000 | } |
c901851f | 1001 | |
500559a9 | 1002 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1003 | { |
1004 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1005 | return; | |
1006 | ||
1007 | pci_msix_shutdown(dev); | |
f56e4481 | 1008 | free_msi_irqs(dev); |
1da177e4 | 1009 | } |
4cc086fa | 1010 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1011 | |
309e57df MW |
1012 | void pci_no_msi(void) |
1013 | { | |
1014 | pci_msi_enable = 0; | |
1015 | } | |
c9953a73 | 1016 | |
07ae95f9 AP |
1017 | /** |
1018 | * pci_msi_enabled - is MSI enabled? | |
1019 | * | |
1020 | * Returns true if MSI has not been disabled by the command-line option | |
1021 | * pci=nomsi. | |
1022 | **/ | |
1023 | int pci_msi_enabled(void) | |
d389fec6 | 1024 | { |
07ae95f9 | 1025 | return pci_msi_enable; |
d389fec6 | 1026 | } |
07ae95f9 | 1027 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1028 | |
4ef33685 | 1029 | static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, |
61e1c590 | 1030 | const struct irq_affinity *affd) |
302a2523 | 1031 | { |
034cd97e | 1032 | int nvec; |
302a2523 AG |
1033 | int rc; |
1034 | ||
a06cd74c AG |
1035 | if (!pci_msi_supported(dev, minvec)) |
1036 | return -EINVAL; | |
034cd97e AG |
1037 | |
1038 | WARN_ON(!!dev->msi_enabled); | |
1039 | ||
1040 | /* Check whether driver already requested MSI-X irqs */ | |
1041 | if (dev->msix_enabled) { | |
1042 | dev_info(&dev->dev, | |
1043 | "can't enable MSI (MSI-X already enabled)\n"); | |
1044 | return -EINVAL; | |
1045 | } | |
1046 | ||
302a2523 AG |
1047 | if (maxvec < minvec) |
1048 | return -ERANGE; | |
1049 | ||
034cd97e AG |
1050 | nvec = pci_msi_vec_count(dev); |
1051 | if (nvec < 0) | |
1052 | return nvec; | |
4ef33685 | 1053 | if (nvec < minvec) |
948b7620 | 1054 | return -ENOSPC; |
4ef33685 CH |
1055 | |
1056 | if (nvec > maxvec) | |
034cd97e AG |
1057 | nvec = maxvec; |
1058 | ||
4ef33685 | 1059 | for (;;) { |
61e1c590 CH |
1060 | if (affd) { |
1061 | nvec = irq_calc_affinity_vectors(nvec, affd); | |
4ef33685 CH |
1062 | if (nvec < minvec) |
1063 | return -ENOSPC; | |
1064 | } | |
1065 | ||
61e1c590 | 1066 | rc = msi_capability_init(dev, nvec, affd); |
4ef33685 CH |
1067 | if (rc == 0) |
1068 | return nvec; | |
1069 | ||
4ef33685 | 1070 | if (rc < 0) |
302a2523 | 1071 | return rc; |
4ef33685 CH |
1072 | if (rc < minvec) |
1073 | return -ENOSPC; | |
1074 | ||
1075 | nvec = rc; | |
1076 | } | |
1077 | } | |
1078 | ||
4fe03955 CH |
1079 | /* deprecated, don't use */ |
1080 | int pci_enable_msi(struct pci_dev *dev) | |
4ef33685 | 1081 | { |
4fe03955 CH |
1082 | int rc = __pci_enable_msi_range(dev, 1, 1, NULL); |
1083 | if (rc < 0) | |
1084 | return rc; | |
1085 | return 0; | |
4ef33685 | 1086 | } |
4fe03955 | 1087 | EXPORT_SYMBOL(pci_enable_msi); |
4ef33685 CH |
1088 | |
1089 | static int __pci_enable_msix_range(struct pci_dev *dev, | |
61e1c590 CH |
1090 | struct msix_entry *entries, int minvec, |
1091 | int maxvec, const struct irq_affinity *affd) | |
4ef33685 | 1092 | { |
e75eafb9 | 1093 | int rc, nvec = maxvec; |
4ef33685 CH |
1094 | |
1095 | if (maxvec < minvec) | |
1096 | return -ERANGE; | |
1097 | ||
1098 | for (;;) { | |
61e1c590 CH |
1099 | if (affd) { |
1100 | nvec = irq_calc_affinity_vectors(nvec, affd); | |
4ef33685 | 1101 | if (nvec < minvec) |
302a2523 | 1102 | return -ENOSPC; |
302a2523 | 1103 | } |
302a2523 | 1104 | |
61e1c590 | 1105 | rc = __pci_enable_msix(dev, entries, nvec, affd); |
4ef33685 CH |
1106 | if (rc == 0) |
1107 | return nvec; | |
1108 | ||
4ef33685 CH |
1109 | if (rc < 0) |
1110 | return rc; | |
1111 | if (rc < minvec) | |
1112 | return -ENOSPC; | |
1113 | ||
1114 | nvec = rc; | |
1115 | } | |
302a2523 | 1116 | } |
302a2523 AG |
1117 | |
1118 | /** | |
1119 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1120 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1121 | * @entries: pointer to an array of MSI-X entries | |
1122 | * @minvec: minimum number of MSI-X irqs requested | |
1123 | * @maxvec: maximum number of MSI-X irqs requested | |
1124 | * | |
1125 | * Setup the MSI-X capability structure of device function with a maximum | |
1126 | * possible number of interrupts in the range between @minvec and @maxvec | |
1127 | * upon its software driver call to request for MSI-X mode enabled on its | |
1128 | * hardware device function. It returns a negative errno if an error occurs. | |
1129 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1130 | * indicates the successful configuration of MSI-X capability structure | |
1131 | * with new allocated MSI-X interrupts. | |
1132 | **/ | |
1133 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
4ef33685 | 1134 | int minvec, int maxvec) |
302a2523 | 1135 | { |
61e1c590 | 1136 | return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL); |
302a2523 AG |
1137 | } |
1138 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef | 1139 | |
aff17164 | 1140 | /** |
402723ad | 1141 | * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device |
aff17164 CH |
1142 | * @dev: PCI device to operate on |
1143 | * @min_vecs: minimum number of vectors required (must be >= 1) | |
1144 | * @max_vecs: maximum (desired) number of vectors | |
1145 | * @flags: flags or quirks for the allocation | |
402723ad | 1146 | * @affd: optional description of the affinity requirements |
aff17164 CH |
1147 | * |
1148 | * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI | |
1149 | * vectors if available, and fall back to a single legacy vector | |
1150 | * if neither is available. Return the number of vectors allocated, | |
1151 | * (which might be smaller than @max_vecs) if successful, or a negative | |
1152 | * error code on error. If less than @min_vecs interrupt vectors are | |
1153 | * available for @dev the function will fail with -ENOSPC. | |
1154 | * | |
1155 | * To get the Linux IRQ number used for a vector that can be passed to | |
1156 | * request_irq() use the pci_irq_vector() helper. | |
1157 | */ | |
402723ad CH |
1158 | int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, |
1159 | unsigned int max_vecs, unsigned int flags, | |
1160 | const struct irq_affinity *affd) | |
aff17164 | 1161 | { |
61e1c590 | 1162 | static const struct irq_affinity msi_default_affd; |
aff17164 CH |
1163 | int vecs = -ENOSPC; |
1164 | ||
402723ad CH |
1165 | if (flags & PCI_IRQ_AFFINITY) { |
1166 | if (!affd) | |
1167 | affd = &msi_default_affd; | |
dfef358b CH |
1168 | |
1169 | if (affd->pre_vectors + affd->post_vectors > min_vecs) | |
1170 | return -EINVAL; | |
1171 | ||
1172 | /* | |
1173 | * If there aren't any vectors left after applying the pre/post | |
1174 | * vectors don't bother with assigning affinity. | |
1175 | */ | |
1176 | if (affd->pre_vectors + affd->post_vectors == min_vecs) | |
1177 | affd = NULL; | |
402723ad CH |
1178 | } else { |
1179 | if (WARN_ON(affd)) | |
1180 | affd = NULL; | |
1181 | } | |
61e1c590 | 1182 | |
4fe0d154 | 1183 | if (flags & PCI_IRQ_MSIX) { |
4ef33685 | 1184 | vecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, |
61e1c590 | 1185 | affd); |
aff17164 CH |
1186 | if (vecs > 0) |
1187 | return vecs; | |
1188 | } | |
1189 | ||
4fe0d154 | 1190 | if (flags & PCI_IRQ_MSI) { |
61e1c590 | 1191 | vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd); |
aff17164 CH |
1192 | if (vecs > 0) |
1193 | return vecs; | |
1194 | } | |
1195 | ||
1196 | /* use legacy irq if allowed */ | |
862290f9 CH |
1197 | if (flags & PCI_IRQ_LEGACY) { |
1198 | if (min_vecs == 1 && dev->irq) { | |
1199 | pci_intx(dev, 1); | |
1200 | return 1; | |
1201 | } | |
5d0bdf28 CH |
1202 | } |
1203 | ||
aff17164 CH |
1204 | return vecs; |
1205 | } | |
402723ad | 1206 | EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); |
aff17164 CH |
1207 | |
1208 | /** | |
1209 | * pci_free_irq_vectors - free previously allocated IRQs for a device | |
1210 | * @dev: PCI device to operate on | |
1211 | * | |
1212 | * Undoes the allocations and enabling in pci_alloc_irq_vectors(). | |
1213 | */ | |
1214 | void pci_free_irq_vectors(struct pci_dev *dev) | |
1215 | { | |
1216 | pci_disable_msix(dev); | |
1217 | pci_disable_msi(dev); | |
1218 | } | |
1219 | EXPORT_SYMBOL(pci_free_irq_vectors); | |
1220 | ||
1221 | /** | |
1222 | * pci_irq_vector - return Linux IRQ number of a device vector | |
1223 | * @dev: PCI device to operate on | |
1224 | * @nr: device-relative interrupt vector index (0-based). | |
1225 | */ | |
1226 | int pci_irq_vector(struct pci_dev *dev, unsigned int nr) | |
1227 | { | |
1228 | if (dev->msix_enabled) { | |
1229 | struct msi_desc *entry; | |
1230 | int i = 0; | |
1231 | ||
1232 | for_each_pci_msi_entry(entry, dev) { | |
1233 | if (i == nr) | |
1234 | return entry->irq; | |
1235 | i++; | |
1236 | } | |
1237 | WARN_ON_ONCE(1); | |
1238 | return -EINVAL; | |
1239 | } | |
1240 | ||
1241 | if (dev->msi_enabled) { | |
1242 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1243 | ||
1244 | if (WARN_ON_ONCE(nr >= entry->nvec_used)) | |
1245 | return -EINVAL; | |
1246 | } else { | |
1247 | if (WARN_ON_ONCE(nr > 0)) | |
1248 | return -EINVAL; | |
1249 | } | |
1250 | ||
1251 | return dev->irq + nr; | |
1252 | } | |
1253 | EXPORT_SYMBOL(pci_irq_vector); | |
1254 | ||
ee8d41e5 TG |
1255 | /** |
1256 | * pci_irq_get_affinity - return the affinity of a particular msi vector | |
1257 | * @dev: PCI device to operate on | |
1258 | * @nr: device-relative interrupt vector index (0-based). | |
1259 | */ | |
1260 | const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr) | |
1261 | { | |
1262 | if (dev->msix_enabled) { | |
1263 | struct msi_desc *entry; | |
1264 | int i = 0; | |
1265 | ||
1266 | for_each_pci_msi_entry(entry, dev) { | |
1267 | if (i == nr) | |
1268 | return entry->affinity; | |
1269 | i++; | |
1270 | } | |
1271 | WARN_ON_ONCE(1); | |
1272 | return NULL; | |
1273 | } else if (dev->msi_enabled) { | |
1274 | struct msi_desc *entry = first_pci_msi_entry(dev); | |
1275 | ||
d1d111e0 JB |
1276 | if (WARN_ON_ONCE(!entry || !entry->affinity || |
1277 | nr >= entry->nvec_used)) | |
ee8d41e5 TG |
1278 | return NULL; |
1279 | ||
1280 | return &entry->affinity[nr]; | |
1281 | } else { | |
1282 | return cpu_possible_mask; | |
1283 | } | |
1284 | } | |
1285 | EXPORT_SYMBOL(pci_irq_get_affinity); | |
1286 | ||
27ddb689 SL |
1287 | /** |
1288 | * pci_irq_get_node - return the numa node of a particular msi vector | |
1289 | * @pdev: PCI device to operate on | |
1290 | * @vec: device-relative interrupt vector index (0-based). | |
1291 | */ | |
1292 | int pci_irq_get_node(struct pci_dev *pdev, int vec) | |
1293 | { | |
1294 | const struct cpumask *mask; | |
1295 | ||
1296 | mask = pci_irq_get_affinity(pdev, vec); | |
1297 | if (mask) | |
1298 | return local_memory_node(cpu_to_node(cpumask_first(mask))); | |
1299 | return dev_to_node(&pdev->dev); | |
1300 | } | |
1301 | EXPORT_SYMBOL(pci_irq_get_node); | |
1302 | ||
25a98bd4 JL |
1303 | struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc) |
1304 | { | |
1305 | return to_pci_dev(desc->dev); | |
1306 | } | |
a4289dc2 | 1307 | EXPORT_SYMBOL(msi_desc_to_pci_dev); |
25a98bd4 | 1308 | |
c179c9b9 JL |
1309 | void *msi_desc_to_pci_sysdata(struct msi_desc *desc) |
1310 | { | |
1311 | struct pci_dev *dev = msi_desc_to_pci_dev(desc); | |
1312 | ||
1313 | return dev->bus->sysdata; | |
1314 | } | |
1315 | EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata); | |
1316 | ||
3878eaef JL |
1317 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
1318 | /** | |
1319 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1320 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1321 | * @msg: Pointer to the message | |
1322 | */ | |
1323 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1324 | { | |
507a883e | 1325 | struct msi_desc *desc = irq_data_get_msi_desc(irq_data); |
3878eaef JL |
1326 | |
1327 | /* | |
1328 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1329 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1330 | */ | |
1331 | if (desc->irq == irq_data->irq) | |
1332 | __pci_write_msi_msg(desc, msg); | |
1333 | } | |
1334 | ||
1335 | /** | |
1336 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
1337 | * @dev: Pointer to the PCI device | |
1338 | * @desc: Pointer to the msi descriptor | |
1339 | * | |
1340 | * The ID number is only used within the irqdomain. | |
1341 | */ | |
1342 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, | |
1343 | struct msi_desc *desc) | |
1344 | { | |
1345 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | | |
1346 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | | |
1347 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; | |
1348 | } | |
1349 | ||
1350 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1351 | { | |
1352 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1353 | } | |
1354 | ||
1355 | /** | |
1356 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev | |
1357 | * @domain: The interrupt domain to check | |
1358 | * @info: The domain info for verification | |
1359 | * @dev: The device to check | |
1360 | * | |
1361 | * Returns: | |
1362 | * 0 if the functionality is supported | |
1363 | * 1 if Multi MSI is requested, but the domain does not support it | |
1364 | * -ENOTSUPP otherwise | |
1365 | */ | |
1366 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1367 | struct msi_domain_info *info, struct device *dev) | |
1368 | { | |
1369 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1370 | ||
4fe03955 | 1371 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1372 | if (pci_msi_desc_is_multi_msi(desc) && |
1373 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1374 | return 1; | |
1375 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1376 | return -ENOTSUPP; | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
1381 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1382 | struct msi_desc *desc, int error) | |
1383 | { | |
4fe03955 | 1384 | /* Special handling to support __pci_enable_msi_range() */ |
3878eaef JL |
1385 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) |
1386 | return 1; | |
1387 | ||
1388 | return error; | |
1389 | } | |
1390 | ||
1391 | #ifdef GENERIC_MSI_DOMAIN_OPS | |
1392 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, | |
1393 | struct msi_desc *desc) | |
1394 | { | |
1395 | arg->desc = desc; | |
1396 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), | |
1397 | desc); | |
1398 | } | |
1399 | #else | |
1400 | #define pci_msi_domain_set_desc NULL | |
1401 | #endif | |
1402 | ||
1403 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1404 | .set_desc = pci_msi_domain_set_desc, | |
1405 | .msi_check = pci_msi_domain_check_cap, | |
1406 | .handle_error = pci_msi_domain_handle_error, | |
1407 | }; | |
1408 | ||
1409 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1410 | { | |
1411 | struct msi_domain_ops *ops = info->ops; | |
1412 | ||
1413 | if (ops == NULL) { | |
1414 | info->ops = &pci_msi_domain_ops_default; | |
1415 | } else { | |
1416 | if (ops->set_desc == NULL) | |
1417 | ops->set_desc = pci_msi_domain_set_desc; | |
1418 | if (ops->msi_check == NULL) | |
1419 | ops->msi_check = pci_msi_domain_check_cap; | |
1420 | if (ops->handle_error == NULL) | |
1421 | ops->handle_error = pci_msi_domain_handle_error; | |
1422 | } | |
1423 | } | |
1424 | ||
1425 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1426 | { | |
1427 | struct irq_chip *chip = info->chip; | |
1428 | ||
1429 | BUG_ON(!chip); | |
1430 | if (!chip->irq_write_msi_msg) | |
1431 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
0701c53e MZ |
1432 | if (!chip->irq_mask) |
1433 | chip->irq_mask = pci_msi_mask_irq; | |
1434 | if (!chip->irq_unmask) | |
1435 | chip->irq_unmask = pci_msi_unmask_irq; | |
3878eaef JL |
1436 | } |
1437 | ||
1438 | /** | |
be5436c8 MZ |
1439 | * pci_msi_create_irq_domain - Create a MSI interrupt domain |
1440 | * @fwnode: Optional fwnode of the interrupt controller | |
3878eaef JL |
1441 | * @info: MSI domain info |
1442 | * @parent: Parent irq domain | |
1443 | * | |
1444 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1445 | * | |
1446 | * Returns: | |
1447 | * A domain pointer or NULL in case of failure. | |
1448 | */ | |
be5436c8 | 1449 | struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode, |
3878eaef JL |
1450 | struct msi_domain_info *info, |
1451 | struct irq_domain *parent) | |
1452 | { | |
0380839d MZ |
1453 | struct irq_domain *domain; |
1454 | ||
3878eaef JL |
1455 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
1456 | pci_msi_domain_update_dom_ops(info); | |
1457 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1458 | pci_msi_domain_update_chip_ops(info); | |
1459 | ||
f3b0946d MZ |
1460 | info->flags |= MSI_FLAG_ACTIVATE_EARLY; |
1461 | ||
be5436c8 | 1462 | domain = msi_create_irq_domain(fwnode, info, parent); |
0380839d MZ |
1463 | if (!domain) |
1464 | return NULL; | |
1465 | ||
1466 | domain->bus_token = DOMAIN_BUS_PCI_MSI; | |
1467 | return domain; | |
3878eaef | 1468 | } |
a4289dc2 | 1469 | EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain); |
3878eaef | 1470 | |
b6eec9b7 DD |
1471 | static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data) |
1472 | { | |
1473 | u32 *pa = data; | |
1474 | ||
1475 | *pa = alias; | |
1476 | return 0; | |
1477 | } | |
1478 | /** | |
1479 | * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID) | |
1480 | * @domain: The interrupt domain | |
1481 | * @pdev: The PCI device. | |
1482 | * | |
1483 | * The RID for a device is formed from the alias, with a firmware | |
1484 | * supplied mapping applied | |
1485 | * | |
1486 | * Returns: The RID. | |
1487 | */ | |
1488 | u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev) | |
1489 | { | |
1490 | struct device_node *of_node; | |
1491 | u32 rid = 0; | |
1492 | ||
1493 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
1494 | ||
1495 | of_node = irq_domain_get_of_node(domain); | |
be2021ba TN |
1496 | rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) : |
1497 | iort_msi_map_rid(&pdev->dev, rid); | |
b6eec9b7 DD |
1498 | |
1499 | return rid; | |
1500 | } | |
54fa97ee MZ |
1501 | |
1502 | /** | |
1503 | * pci_msi_get_device_domain - Get the MSI domain for a given PCI device | |
1504 | * @pdev: The PCI device | |
1505 | * | |
1506 | * Use the firmware data to find a device-specific MSI domain | |
1507 | * (i.e. not one that is ste as a default). | |
1508 | * | |
1509 | * Returns: The coresponding MSI domain or NULL if none has been found. | |
1510 | */ | |
1511 | struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) | |
1512 | { | |
be2021ba | 1513 | struct irq_domain *dom; |
54fa97ee MZ |
1514 | u32 rid = 0; |
1515 | ||
1516 | pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid); | |
be2021ba TN |
1517 | dom = of_msi_map_get_device_domain(&pdev->dev, rid); |
1518 | if (!dom) | |
1519 | dom = iort_get_device_domain(&pdev->dev, rid); | |
1520 | return dom; | |
54fa97ee | 1521 | } |
3878eaef | 1522 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |