]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
1da177e4 | 24 | |
1da177e4 | 25 | static int pci_msi_enable = 1; |
1da177e4 | 26 | |
527eee29 BH |
27 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
28 | ||
29 | ||
6a9e7f20 AB |
30 | /* Arch hooks */ |
31 | ||
4287d824 TP |
32 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
33 | { | |
0cbdcfcf TR |
34 | struct msi_chip *chip = dev->bus->msi; |
35 | int err; | |
36 | ||
37 | if (!chip || !chip->setup_irq) | |
38 | return -EINVAL; | |
39 | ||
40 | err = chip->setup_irq(chip, dev, desc); | |
41 | if (err < 0) | |
42 | return err; | |
43 | ||
44 | irq_set_chip_data(desc->irq, chip); | |
45 | ||
46 | return 0; | |
4287d824 TP |
47 | } |
48 | ||
49 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 50 | { |
0cbdcfcf TR |
51 | struct msi_chip *chip = irq_get_chip_data(irq); |
52 | ||
53 | if (!chip || !chip->teardown_irq) | |
54 | return; | |
55 | ||
56 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
57 | } |
58 | ||
4287d824 | 59 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
60 | { |
61 | struct msi_desc *entry; | |
62 | int ret; | |
63 | ||
1c8d7b0a MW |
64 | /* |
65 | * If an architecture wants to support multiple MSI, it needs to | |
66 | * override arch_setup_msi_irqs() | |
67 | */ | |
68 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
69 | return 1; | |
70 | ||
6a9e7f20 AB |
71 | list_for_each_entry(entry, &dev->msi_list, list) { |
72 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 73 | if (ret < 0) |
6a9e7f20 | 74 | return ret; |
b5fbf533 ME |
75 | if (ret > 0) |
76 | return -ENOSPC; | |
6a9e7f20 AB |
77 | } |
78 | ||
79 | return 0; | |
80 | } | |
1525bf0d | 81 | |
4287d824 TP |
82 | /* |
83 | * We have a default implementation available as a separate non-weak | |
84 | * function, as it is used by the Xen x86 PCI code | |
85 | */ | |
1525bf0d | 86 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
87 | { |
88 | struct msi_desc *entry; | |
89 | ||
90 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
91 | int i, nvec; |
92 | if (entry->irq == 0) | |
93 | continue; | |
65f6ae66 AG |
94 | if (entry->nvec_used) |
95 | nvec = entry->nvec_used; | |
96 | else | |
97 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
98 | for (i = 0; i < nvec; i++) |
99 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
100 | } |
101 | } | |
102 | ||
4287d824 TP |
103 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
104 | { | |
105 | return default_teardown_msi_irqs(dev); | |
106 | } | |
76ccc297 | 107 | |
ac8344c4 | 108 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
109 | { |
110 | struct msi_desc *entry; | |
111 | ||
112 | entry = NULL; | |
113 | if (dev->msix_enabled) { | |
114 | list_for_each_entry(entry, &dev->msi_list, list) { | |
115 | if (irq == entry->irq) | |
116 | break; | |
117 | } | |
118 | } else if (dev->msi_enabled) { | |
119 | entry = irq_get_msi_desc(irq); | |
120 | } | |
121 | ||
122 | if (entry) | |
56b72b40 | 123 | __write_msi_msg(entry, &entry->msg); |
76ccc297 | 124 | } |
4287d824 | 125 | |
ac8344c4 | 126 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 127 | { |
ac8344c4 | 128 | return default_restore_msi_irqs(dev); |
4287d824 | 129 | } |
76ccc297 | 130 | |
e375b561 | 131 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 132 | { |
b1cbf4e4 EB |
133 | u16 control; |
134 | ||
e375b561 | 135 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
136 | control &= ~PCI_MSI_FLAGS_ENABLE; |
137 | if (enable) | |
138 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 139 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
140 | } |
141 | ||
66f0d0c4 | 142 | static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
b1cbf4e4 | 143 | { |
66f0d0c4 | 144 | u16 ctrl; |
b1cbf4e4 | 145 | |
66f0d0c4 YW |
146 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); |
147 | ctrl &= ~clear; | |
148 | ctrl |= set; | |
149 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
b1cbf4e4 EB |
150 | } |
151 | ||
bffac3c5 MW |
152 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
153 | { | |
0b49ec37 MW |
154 | /* Don't shift by >= width of type */ |
155 | if (x >= 5) | |
156 | return 0xffffffff; | |
157 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
158 | } |
159 | ||
ce6fce42 MW |
160 | /* |
161 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
162 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
163 | * reliably as devices without an INTx disable bit will then generate a | |
164 | * level IRQ which will never be cleared. | |
ce6fce42 | 165 | */ |
0e4ccb15 | 166 | u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 167 | { |
f2440d9a | 168 | u32 mask_bits = desc->masked; |
1da177e4 | 169 | |
f2440d9a | 170 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 171 | return 0; |
f2440d9a MW |
172 | |
173 | mask_bits &= ~mask; | |
174 | mask_bits |= flag; | |
175 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
176 | |
177 | return mask_bits; | |
178 | } | |
179 | ||
0e4ccb15 KRW |
180 | __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
181 | { | |
182 | return default_msi_mask_irq(desc, mask, flag); | |
183 | } | |
184 | ||
12abb8ba HS |
185 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
186 | { | |
0e4ccb15 | 187 | desc->masked = arch_msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
188 | } |
189 | ||
190 | /* | |
191 | * This internal function does not flush PCI writes to the device. | |
192 | * All users must ensure that they read from the device before either | |
193 | * assuming that the device state is up to date, or returning out of this | |
194 | * file. This saves a few milliseconds when initialising devices with lots | |
195 | * of MSI-X interrupts. | |
196 | */ | |
0e4ccb15 | 197 | u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
198 | { |
199 | u32 mask_bits = desc->masked; | |
200 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 201 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
202 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
203 | if (flag) | |
204 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 205 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
206 | |
207 | return mask_bits; | |
208 | } | |
209 | ||
0e4ccb15 KRW |
210 | __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag) |
211 | { | |
212 | return default_msix_mask_irq(desc, flag); | |
213 | } | |
214 | ||
12abb8ba HS |
215 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
216 | { | |
0e4ccb15 | 217 | desc->masked = arch_msix_mask_irq(desc, flag); |
f2440d9a | 218 | } |
24d27553 | 219 | |
1c9db525 | 220 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 221 | { |
1c9db525 | 222 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 223 | |
f2440d9a MW |
224 | if (desc->msi_attrib.is_msix) { |
225 | msix_mask_irq(desc, flag); | |
226 | readl(desc->mask_base); /* Flush write to device */ | |
227 | } else { | |
a281b788 | 228 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 229 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 230 | } |
f2440d9a MW |
231 | } |
232 | ||
1c9db525 | 233 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 234 | { |
1c9db525 | 235 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
236 | } |
237 | ||
1c9db525 | 238 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 239 | { |
1c9db525 | 240 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
241 | } |
242 | ||
ac8344c4 D |
243 | void default_restore_msi_irqs(struct pci_dev *dev) |
244 | { | |
245 | struct msi_desc *entry; | |
246 | ||
247 | list_for_each_entry(entry, &dev->msi_list, list) { | |
248 | default_restore_msi_irq(dev, entry->irq); | |
249 | } | |
250 | } | |
251 | ||
39431acb | 252 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 253 | { |
30da5524 BH |
254 | BUG_ON(entry->dev->current_state != PCI_D0); |
255 | ||
256 | if (entry->msi_attrib.is_msix) { | |
257 | void __iomem *base = entry->mask_base + | |
258 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
259 | ||
260 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
261 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
262 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
263 | } else { | |
264 | struct pci_dev *dev = entry->dev; | |
f5322169 | 265 | int pos = dev->msi_cap; |
30da5524 BH |
266 | u16 data; |
267 | ||
9925ad0c BH |
268 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
269 | &msg->address_lo); | |
30da5524 | 270 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
271 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
272 | &msg->address_hi); | |
2f221349 | 273 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
274 | } else { |
275 | msg->address_hi = 0; | |
2f221349 | 276 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
277 | } |
278 | msg->data = data; | |
279 | } | |
280 | } | |
281 | ||
282 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
283 | { | |
dced35ae | 284 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 285 | |
39431acb | 286 | __read_msi_msg(entry, msg); |
30da5524 BH |
287 | } |
288 | ||
39431acb | 289 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 290 | { |
30da5524 | 291 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
292 | * valid messages are not all-zeroes. */ |
293 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
294 | entry->msg.data)); | |
0366f8f7 | 295 | |
fcd097f3 | 296 | *msg = entry->msg; |
0366f8f7 | 297 | } |
1da177e4 | 298 | |
30da5524 | 299 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 300 | { |
dced35ae | 301 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 302 | |
39431acb | 303 | __get_cached_msi_msg(entry, msg); |
3145e941 | 304 | } |
3b307ffe | 305 | EXPORT_SYMBOL_GPL(get_cached_msi_msg); |
3145e941 | 306 | |
39431acb | 307 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 308 | { |
fcd097f3 BH |
309 | if (entry->dev->current_state != PCI_D0) { |
310 | /* Don't touch the hardware now */ | |
311 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
312 | void __iomem *base; |
313 | base = entry->mask_base + | |
314 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
315 | ||
2c21fd4b HS |
316 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
317 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
318 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 319 | } else { |
0366f8f7 | 320 | struct pci_dev *dev = entry->dev; |
f5322169 | 321 | int pos = dev->msi_cap; |
1c8d7b0a MW |
322 | u16 msgctl; |
323 | ||
f84ecd28 | 324 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
325 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
326 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 327 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 328 | |
9925ad0c BH |
329 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
330 | msg->address_lo); | |
0366f8f7 | 331 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
332 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
333 | msg->address_hi); | |
2f221349 BH |
334 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
335 | msg->data); | |
0366f8f7 | 336 | } else { |
2f221349 BH |
337 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
338 | msg->data); | |
0366f8f7 | 339 | } |
1da177e4 | 340 | } |
392ee1e6 | 341 | entry->msg = *msg; |
1da177e4 | 342 | } |
0366f8f7 | 343 | |
3145e941 YL |
344 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
345 | { | |
dced35ae | 346 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 347 | |
39431acb | 348 | __write_msi_msg(entry, msg); |
3145e941 | 349 | } |
3b307ffe | 350 | EXPORT_SYMBOL_GPL(write_msi_msg); |
3145e941 | 351 | |
f56e4481 HS |
352 | static void free_msi_irqs(struct pci_dev *dev) |
353 | { | |
354 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
355 | struct attribute **msi_attrs; |
356 | struct device_attribute *dev_attr; | |
357 | int count = 0; | |
f56e4481 HS |
358 | |
359 | list_for_each_entry(entry, &dev->msi_list, list) { | |
360 | int i, nvec; | |
361 | if (!entry->irq) | |
362 | continue; | |
65f6ae66 AG |
363 | if (entry->nvec_used) |
364 | nvec = entry->nvec_used; | |
365 | else | |
366 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
367 | for (i = 0; i < nvec; i++) |
368 | BUG_ON(irq_has_action(entry->irq + i)); | |
369 | } | |
370 | ||
371 | arch_teardown_msi_irqs(dev); | |
372 | ||
373 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
374 | if (entry->msi_attrib.is_msix) { | |
375 | if (list_is_last(&entry->list, &dev->msi_list)) | |
376 | iounmap(entry->mask_base); | |
377 | } | |
424eb391 | 378 | |
f56e4481 HS |
379 | list_del(&entry->list); |
380 | kfree(entry); | |
381 | } | |
1c51b50c GKH |
382 | |
383 | if (dev->msi_irq_groups) { | |
384 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
385 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 386 | while (msi_attrs[count]) { |
1c51b50c GKH |
387 | dev_attr = container_of(msi_attrs[count], |
388 | struct device_attribute, attr); | |
389 | kfree(dev_attr->attr.name); | |
390 | kfree(dev_attr); | |
391 | ++count; | |
392 | } | |
393 | kfree(msi_attrs); | |
394 | kfree(dev->msi_irq_groups[0]); | |
395 | kfree(dev->msi_irq_groups); | |
396 | dev->msi_irq_groups = NULL; | |
397 | } | |
f56e4481 | 398 | } |
c54c1879 | 399 | |
379f5327 | 400 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 401 | { |
379f5327 MW |
402 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
403 | if (!desc) | |
1da177e4 LT |
404 | return NULL; |
405 | ||
379f5327 MW |
406 | INIT_LIST_HEAD(&desc->list); |
407 | desc->dev = dev; | |
1da177e4 | 408 | |
379f5327 | 409 | return desc; |
1da177e4 LT |
410 | } |
411 | ||
ba698ad4 DM |
412 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
413 | { | |
414 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
415 | pci_intx(dev, enable); | |
416 | } | |
417 | ||
8fed4b65 | 418 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 419 | { |
41017f0c | 420 | u16 control; |
392ee1e6 | 421 | struct msi_desc *entry; |
41017f0c | 422 | |
b1cbf4e4 EB |
423 | if (!dev->msi_enabled) |
424 | return; | |
425 | ||
dced35ae | 426 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 427 | |
ba698ad4 | 428 | pci_intx_for_msi(dev, 0); |
e375b561 | 429 | msi_set_enable(dev, 0); |
ac8344c4 | 430 | arch_restore_msi_irqs(dev); |
392ee1e6 | 431 | |
f5322169 | 432 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
433 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
434 | entry->masked); | |
abad2ec9 | 435 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 436 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 437 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
438 | } |
439 | ||
440 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 441 | { |
41017f0c | 442 | struct msi_desc *entry; |
41017f0c | 443 | |
ded86d8d EB |
444 | if (!dev->msix_enabled) |
445 | return; | |
f598282f | 446 | BUG_ON(list_empty(&dev->msi_list)); |
ded86d8d | 447 | |
41017f0c | 448 | /* route the table */ |
ba698ad4 | 449 | pci_intx_for_msi(dev, 0); |
66f0d0c4 YW |
450 | msix_clear_and_set_ctrl(dev, 0, |
451 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); | |
41017f0c | 452 | |
ac8344c4 | 453 | arch_restore_msi_irqs(dev); |
4aa9bc95 | 454 | list_for_each_entry(entry, &dev->msi_list, list) { |
f2440d9a | 455 | msix_mask_irq(entry, entry->masked); |
41017f0c | 456 | } |
41017f0c | 457 | |
66f0d0c4 | 458 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 459 | } |
8fed4b65 ME |
460 | |
461 | void pci_restore_msi_state(struct pci_dev *dev) | |
462 | { | |
463 | __pci_restore_msi_state(dev); | |
464 | __pci_restore_msix_state(dev); | |
465 | } | |
94688cf2 | 466 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 467 | |
1c51b50c | 468 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
469 | char *buf) |
470 | { | |
1c51b50c GKH |
471 | struct msi_desc *entry; |
472 | unsigned long irq; | |
473 | int retval; | |
da8d1c8b | 474 | |
1c51b50c GKH |
475 | retval = kstrtoul(attr->attr.name, 10, &irq); |
476 | if (retval) | |
477 | return retval; | |
da8d1c8b | 478 | |
e11ece5a YW |
479 | entry = irq_get_msi_desc(irq); |
480 | if (entry) | |
481 | return sprintf(buf, "%s\n", | |
482 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
483 | ||
1c51b50c | 484 | return -ENODEV; |
da8d1c8b NH |
485 | } |
486 | ||
da8d1c8b NH |
487 | static int populate_msi_sysfs(struct pci_dev *pdev) |
488 | { | |
1c51b50c GKH |
489 | struct attribute **msi_attrs; |
490 | struct attribute *msi_attr; | |
491 | struct device_attribute *msi_dev_attr; | |
492 | struct attribute_group *msi_irq_group; | |
493 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 494 | struct msi_desc *entry; |
1c51b50c GKH |
495 | int ret = -ENOMEM; |
496 | int num_msi = 0; | |
da8d1c8b NH |
497 | int count = 0; |
498 | ||
1c51b50c GKH |
499 | /* Determine how many msi entries we have */ |
500 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
501 | ++num_msi; | |
502 | } | |
503 | if (!num_msi) | |
504 | return 0; | |
da8d1c8b | 505 | |
1c51b50c GKH |
506 | /* Dynamically create the MSI attributes for the PCI device */ |
507 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
508 | if (!msi_attrs) | |
509 | return -ENOMEM; | |
da8d1c8b | 510 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 511 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 512 | if (!msi_dev_attr) |
1c51b50c | 513 | goto error_attrs; |
1406276c | 514 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 515 | |
1c51b50c | 516 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
517 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
518 | entry->irq); | |
519 | if (!msi_dev_attr->attr.name) | |
520 | goto error_attrs; | |
1c51b50c GKH |
521 | msi_dev_attr->attr.mode = S_IRUGO; |
522 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 523 | ++count; |
da8d1c8b NH |
524 | } |
525 | ||
1c51b50c GKH |
526 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
527 | if (!msi_irq_group) | |
528 | goto error_attrs; | |
529 | msi_irq_group->name = "msi_irqs"; | |
530 | msi_irq_group->attrs = msi_attrs; | |
531 | ||
532 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
533 | if (!msi_irq_groups) | |
534 | goto error_irq_group; | |
535 | msi_irq_groups[0] = msi_irq_group; | |
536 | ||
537 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
538 | if (ret) | |
539 | goto error_irq_groups; | |
540 | pdev->msi_irq_groups = msi_irq_groups; | |
541 | ||
da8d1c8b NH |
542 | return 0; |
543 | ||
1c51b50c GKH |
544 | error_irq_groups: |
545 | kfree(msi_irq_groups); | |
546 | error_irq_group: | |
547 | kfree(msi_irq_group); | |
548 | error_attrs: | |
549 | count = 0; | |
550 | msi_attr = msi_attrs[count]; | |
551 | while (msi_attr) { | |
552 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
553 | kfree(msi_attr->name); | |
554 | kfree(msi_dev_attr); | |
555 | ++count; | |
556 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 557 | } |
29237756 | 558 | kfree(msi_attrs); |
da8d1c8b NH |
559 | return ret; |
560 | } | |
561 | ||
d873b4d4 YW |
562 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev) |
563 | { | |
564 | u16 control; | |
565 | struct msi_desc *entry; | |
566 | ||
567 | /* MSI Entry Initialization */ | |
568 | entry = alloc_msi_entry(dev); | |
569 | if (!entry) | |
570 | return NULL; | |
571 | ||
572 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
573 | ||
574 | entry->msi_attrib.is_msix = 0; | |
575 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
576 | entry->msi_attrib.entry_nr = 0; | |
577 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
578 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 YW |
579 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
580 | ||
581 | if (control & PCI_MSI_FLAGS_64BIT) | |
582 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
583 | else | |
584 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
585 | ||
586 | /* Save the initial mask status */ | |
587 | if (entry->msi_attrib.maskbit) | |
588 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
589 | ||
590 | return entry; | |
591 | } | |
592 | ||
f144d149 BH |
593 | static int msi_verify_entries(struct pci_dev *dev) |
594 | { | |
595 | struct msi_desc *entry; | |
596 | ||
597 | list_for_each_entry(entry, &dev->msi_list, list) { | |
598 | if (!dev->no_64bit_msi || !entry->msg.address_hi) | |
599 | continue; | |
600 | dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" | |
601 | " tried to assign one above 4G\n"); | |
602 | return -EIO; | |
603 | } | |
604 | return 0; | |
605 | } | |
606 | ||
1da177e4 LT |
607 | /** |
608 | * msi_capability_init - configure device's MSI capability structure | |
609 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 610 | * @nvec: number of interrupts to allocate |
1da177e4 | 611 | * |
1c8d7b0a MW |
612 | * Setup the MSI capability structure of the device with the requested |
613 | * number of interrupts. A return value of zero indicates the successful | |
614 | * setup of an entry with the new MSI irq. A negative return value indicates | |
615 | * an error, and a positive return value indicates the number of interrupts | |
616 | * which could have been allocated. | |
617 | */ | |
618 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
619 | { |
620 | struct msi_desc *entry; | |
f465136d | 621 | int ret; |
f2440d9a | 622 | unsigned mask; |
1da177e4 | 623 | |
e375b561 | 624 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 625 | |
d873b4d4 | 626 | entry = msi_setup_entry(dev); |
f7feaca7 EB |
627 | if (!entry) |
628 | return -ENOMEM; | |
1ce03373 | 629 | |
f2440d9a | 630 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 631 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
632 | msi_mask_irq(entry, mask, mask); |
633 | ||
0dd11f9b | 634 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 635 | |
1da177e4 | 636 | /* Configure MSI capability structure */ |
1c8d7b0a | 637 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 638 | if (ret) { |
7ba1930d | 639 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 640 | free_msi_irqs(dev); |
7fe3730d | 641 | return ret; |
fd58e55f | 642 | } |
f7feaca7 | 643 | |
f144d149 BH |
644 | ret = msi_verify_entries(dev); |
645 | if (ret) { | |
646 | msi_mask_irq(entry, mask, ~mask); | |
647 | free_msi_irqs(dev); | |
648 | return ret; | |
649 | } | |
650 | ||
da8d1c8b NH |
651 | ret = populate_msi_sysfs(dev); |
652 | if (ret) { | |
653 | msi_mask_irq(entry, mask, ~mask); | |
654 | free_msi_irqs(dev); | |
655 | return ret; | |
656 | } | |
657 | ||
1da177e4 | 658 | /* Set MSI enabled bits */ |
ba698ad4 | 659 | pci_intx_for_msi(dev, 0); |
e375b561 | 660 | msi_set_enable(dev, 1); |
b1cbf4e4 | 661 | dev->msi_enabled = 1; |
1da177e4 | 662 | |
7fe3730d | 663 | dev->irq = entry->irq; |
1da177e4 LT |
664 | return 0; |
665 | } | |
666 | ||
520fe9dc | 667 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 668 | { |
4302e0fb | 669 | resource_size_t phys_addr; |
5a05a9d8 HS |
670 | u32 table_offset; |
671 | u8 bir; | |
672 | ||
909094c6 BH |
673 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
674 | &table_offset); | |
4d18760c BH |
675 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
676 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
677 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
678 | ||
679 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
680 | } | |
681 | ||
520fe9dc GS |
682 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
683 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
684 | { |
685 | struct msi_desc *entry; | |
686 | int i; | |
687 | ||
688 | for (i = 0; i < nvec; i++) { | |
689 | entry = alloc_msi_entry(dev); | |
690 | if (!entry) { | |
691 | if (!i) | |
692 | iounmap(base); | |
693 | else | |
694 | free_msi_irqs(dev); | |
695 | /* No enough memory. Don't try again */ | |
696 | return -ENOMEM; | |
697 | } | |
698 | ||
699 | entry->msi_attrib.is_msix = 1; | |
700 | entry->msi_attrib.is_64 = 1; | |
701 | entry->msi_attrib.entry_nr = entries[i].entry; | |
702 | entry->msi_attrib.default_irq = dev->irq; | |
d9d7070e HS |
703 | entry->mask_base = base; |
704 | ||
705 | list_add_tail(&entry->list, &dev->msi_list); | |
706 | } | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
75cb3426 | 711 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 712 | struct msix_entry *entries) |
75cb3426 HS |
713 | { |
714 | struct msi_desc *entry; | |
715 | int i = 0; | |
716 | ||
717 | list_for_each_entry(entry, &dev->msi_list, list) { | |
718 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
719 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
720 | ||
721 | entries[i].vector = entry->irq; | |
dced35ae | 722 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
723 | entry->masked = readl(entry->mask_base + offset); |
724 | msix_mask_irq(entry, 1); | |
725 | i++; | |
726 | } | |
727 | } | |
728 | ||
1da177e4 LT |
729 | /** |
730 | * msix_capability_init - configure device's MSI-X capability | |
731 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
732 | * @entries: pointer to an array of struct msix_entry entries |
733 | * @nvec: number of @entries | |
1da177e4 | 734 | * |
eaae4b3a | 735 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
736 | * single MSI-X irq. A return of zero indicates the successful setup of |
737 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
738 | **/ |
739 | static int msix_capability_init(struct pci_dev *dev, | |
740 | struct msix_entry *entries, int nvec) | |
741 | { | |
520fe9dc | 742 | int ret; |
5a05a9d8 | 743 | u16 control; |
1da177e4 LT |
744 | void __iomem *base; |
745 | ||
f598282f | 746 | /* Ensure MSI-X is disabled while it is set up */ |
66f0d0c4 | 747 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 748 | |
66f0d0c4 | 749 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 750 | /* Request & Map MSI-X table region */ |
527eee29 | 751 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 752 | if (!base) |
1da177e4 LT |
753 | return -ENOMEM; |
754 | ||
520fe9dc | 755 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
756 | if (ret) |
757 | return ret; | |
9c831334 ME |
758 | |
759 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 | 760 | if (ret) |
2adc7907 | 761 | goto out_avail; |
9c831334 | 762 | |
f144d149 BH |
763 | /* Check if all MSI entries honor device restrictions */ |
764 | ret = msi_verify_entries(dev); | |
765 | if (ret) | |
766 | goto out_free; | |
767 | ||
f598282f MW |
768 | /* |
769 | * Some devices require MSI-X to be enabled before we can touch the | |
770 | * MSI-X registers. We need to mask all the vectors to prevent | |
771 | * interrupts coming in before they're fully set up. | |
772 | */ | |
66f0d0c4 YW |
773 | msix_clear_and_set_ctrl(dev, 0, |
774 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); | |
f598282f | 775 | |
75cb3426 | 776 | msix_program_entries(dev, entries); |
f598282f | 777 | |
da8d1c8b | 778 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
779 | if (ret) |
780 | goto out_free; | |
da8d1c8b | 781 | |
f598282f | 782 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 783 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 784 | dev->msix_enabled = 1; |
1da177e4 | 785 | |
66f0d0c4 | 786 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 787 | |
1da177e4 | 788 | return 0; |
583871d4 | 789 | |
2adc7907 | 790 | out_avail: |
583871d4 HS |
791 | if (ret < 0) { |
792 | /* | |
793 | * If we had some success, report the number of irqs | |
794 | * we succeeded in setting up. | |
795 | */ | |
d9d7070e | 796 | struct msi_desc *entry; |
583871d4 HS |
797 | int avail = 0; |
798 | ||
799 | list_for_each_entry(entry, &dev->msi_list, list) { | |
800 | if (entry->irq != 0) | |
801 | avail++; | |
802 | } | |
803 | if (avail != 0) | |
804 | ret = avail; | |
805 | } | |
806 | ||
2adc7907 | 807 | out_free: |
583871d4 HS |
808 | free_msi_irqs(dev); |
809 | ||
810 | return ret; | |
1da177e4 LT |
811 | } |
812 | ||
24334a12 | 813 | /** |
a06cd74c | 814 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 815 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 816 | * @nvec: how many MSIs have been requested ? |
24334a12 | 817 | * |
f7625980 | 818 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 819 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 820 | * supported return 1, else return 0. |
24334a12 | 821 | **/ |
a06cd74c | 822 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
823 | { |
824 | struct pci_bus *bus; | |
825 | ||
0306ebfa | 826 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 827 | if (!pci_msi_enable) |
a06cd74c | 828 | return 0; |
27e20603 AG |
829 | |
830 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 831 | return 0; |
24334a12 | 832 | |
314e77b3 ME |
833 | /* |
834 | * You can't ask to have 0 or less MSIs configured. | |
835 | * a) it's stupid .. | |
836 | * b) the list manipulation code assumes nvec >= 1. | |
837 | */ | |
838 | if (nvec < 1) | |
a06cd74c | 839 | return 0; |
314e77b3 | 840 | |
500559a9 HS |
841 | /* |
842 | * Any bridge which does NOT route MSI transactions from its | |
843 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
844 | * the secondary pci_bus. |
845 | * We expect only arch-specific PCI host bus controller driver | |
846 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
847 | */ | |
24334a12 BG |
848 | for (bus = dev->bus; bus; bus = bus->parent) |
849 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 850 | return 0; |
24334a12 | 851 | |
a06cd74c | 852 | return 1; |
24334a12 BG |
853 | } |
854 | ||
d1ac1d26 AG |
855 | /** |
856 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
857 | * @dev: device to report about | |
858 | * | |
859 | * This function returns the number of MSI vectors a device requested via | |
860 | * Multiple Message Capable register. It returns a negative errno if the | |
861 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
862 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
863 | * MSI specification. | |
864 | **/ | |
865 | int pci_msi_vec_count(struct pci_dev *dev) | |
866 | { | |
867 | int ret; | |
868 | u16 msgctl; | |
869 | ||
870 | if (!dev->msi_cap) | |
871 | return -EINVAL; | |
872 | ||
873 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
874 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
875 | ||
876 | return ret; | |
877 | } | |
878 | EXPORT_SYMBOL(pci_msi_vec_count); | |
879 | ||
f2440d9a | 880 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 881 | { |
f2440d9a MW |
882 | struct msi_desc *desc; |
883 | u32 mask; | |
1da177e4 | 884 | |
128bc5fc | 885 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
886 | return; |
887 | ||
110828c9 MW |
888 | BUG_ON(list_empty(&dev->msi_list)); |
889 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 890 | |
e375b561 | 891 | msi_set_enable(dev, 0); |
ba698ad4 | 892 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 893 | dev->msi_enabled = 0; |
7bd007e4 | 894 | |
12abb8ba | 895 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 896 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 897 | /* Keep cached state to be restored */ |
0e4ccb15 | 898 | arch_msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
899 | |
900 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 901 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 902 | } |
24d27553 | 903 | |
500559a9 | 904 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 905 | { |
d52877c7 YL |
906 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
907 | return; | |
908 | ||
909 | pci_msi_shutdown(dev); | |
f56e4481 | 910 | free_msi_irqs(dev); |
1da177e4 | 911 | } |
4cc086fa | 912 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 913 | |
a52e2e35 | 914 | /** |
ff1aa430 | 915 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 916 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
917 | * This function returns the number of device's MSI-X table entries and |
918 | * therefore the number of MSI-X vectors device is capable of sending. | |
919 | * It returns a negative errno if the device is not capable of sending MSI-X | |
920 | * interrupts. | |
921 | **/ | |
922 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 923 | { |
a52e2e35 RW |
924 | u16 control; |
925 | ||
520fe9dc | 926 | if (!dev->msix_cap) |
ff1aa430 | 927 | return -EINVAL; |
a52e2e35 | 928 | |
f84ecd28 | 929 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 930 | return msix_table_size(control); |
a52e2e35 | 931 | } |
ff1aa430 | 932 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 933 | |
1da177e4 LT |
934 | /** |
935 | * pci_enable_msix - configure device's MSI-X capability structure | |
936 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 937 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 938 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
939 | * |
940 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 941 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
942 | * MSI-X mode enabled on its hardware device function. A return of zero |
943 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 944 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 945 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
946 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
947 | * re-send its request. | |
1da177e4 | 948 | **/ |
500559a9 | 949 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 950 | { |
5ec09405 | 951 | int nr_entries; |
ded86d8d | 952 | int i, j; |
1da177e4 | 953 | |
a06cd74c AG |
954 | if (!pci_msi_supported(dev, nvec)) |
955 | return -EINVAL; | |
c9953a73 | 956 | |
27e20603 AG |
957 | if (!entries) |
958 | return -EINVAL; | |
959 | ||
ff1aa430 AG |
960 | nr_entries = pci_msix_vec_count(dev); |
961 | if (nr_entries < 0) | |
962 | return nr_entries; | |
1da177e4 | 963 | if (nvec > nr_entries) |
57fbf52c | 964 | return nr_entries; |
1da177e4 LT |
965 | |
966 | /* Check for any invalid entries */ | |
967 | for (i = 0; i < nvec; i++) { | |
968 | if (entries[i].entry >= nr_entries) | |
969 | return -EINVAL; /* invalid entry */ | |
970 | for (j = i + 1; j < nvec; j++) { | |
971 | if (entries[i].entry == entries[j].entry) | |
972 | return -EINVAL; /* duplicate entry */ | |
973 | } | |
974 | } | |
ded86d8d | 975 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 976 | |
1ce03373 | 977 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 978 | if (dev->msi_enabled) { |
227f0647 | 979 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
980 | return -EINVAL; |
981 | } | |
5ec09405 | 982 | return msix_capability_init(dev, entries, nvec); |
1da177e4 | 983 | } |
4cc086fa | 984 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 985 | |
500559a9 | 986 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 987 | { |
12abb8ba HS |
988 | struct msi_desc *entry; |
989 | ||
128bc5fc | 990 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
991 | return; |
992 | ||
12abb8ba HS |
993 | /* Return the device with MSI-X masked as initial states */ |
994 | list_for_each_entry(entry, &dev->msi_list, list) { | |
995 | /* Keep cached states to be restored */ | |
0e4ccb15 | 996 | arch_msix_mask_irq(entry, 1); |
12abb8ba HS |
997 | } |
998 | ||
66f0d0c4 | 999 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 1000 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1001 | dev->msix_enabled = 0; |
d52877c7 | 1002 | } |
c901851f | 1003 | |
500559a9 | 1004 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1005 | { |
1006 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1007 | return; | |
1008 | ||
1009 | pci_msix_shutdown(dev); | |
f56e4481 | 1010 | free_msi_irqs(dev); |
1da177e4 | 1011 | } |
4cc086fa | 1012 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1013 | |
309e57df MW |
1014 | void pci_no_msi(void) |
1015 | { | |
1016 | pci_msi_enable = 0; | |
1017 | } | |
c9953a73 | 1018 | |
07ae95f9 AP |
1019 | /** |
1020 | * pci_msi_enabled - is MSI enabled? | |
1021 | * | |
1022 | * Returns true if MSI has not been disabled by the command-line option | |
1023 | * pci=nomsi. | |
1024 | **/ | |
1025 | int pci_msi_enabled(void) | |
d389fec6 | 1026 | { |
07ae95f9 | 1027 | return pci_msi_enable; |
d389fec6 | 1028 | } |
07ae95f9 | 1029 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1030 | |
07ae95f9 | 1031 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1032 | { |
07ae95f9 | 1033 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1034 | |
1035 | /* Disable the msi hardware to avoid screaming interrupts | |
1036 | * during boot. This is the power on reset default so | |
1037 | * usually this should be a noop. | |
1038 | */ | |
e375b561 GS |
1039 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1040 | if (dev->msi_cap) | |
1041 | msi_set_enable(dev, 0); | |
1042 | ||
1043 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1044 | if (dev->msix_cap) | |
66f0d0c4 | 1045 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
d389fec6 | 1046 | } |
302a2523 AG |
1047 | |
1048 | /** | |
1049 | * pci_enable_msi_range - configure device's MSI capability structure | |
1050 | * @dev: device to configure | |
1051 | * @minvec: minimal number of interrupts to configure | |
1052 | * @maxvec: maximum number of interrupts to configure | |
1053 | * | |
1054 | * This function tries to allocate a maximum possible number of interrupts in a | |
1055 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1056 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1057 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1058 | * the other interrupt numbers allocated to this device are consecutive. | |
1059 | **/ | |
1060 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1061 | { | |
034cd97e | 1062 | int nvec; |
302a2523 AG |
1063 | int rc; |
1064 | ||
a06cd74c AG |
1065 | if (!pci_msi_supported(dev, minvec)) |
1066 | return -EINVAL; | |
034cd97e AG |
1067 | |
1068 | WARN_ON(!!dev->msi_enabled); | |
1069 | ||
1070 | /* Check whether driver already requested MSI-X irqs */ | |
1071 | if (dev->msix_enabled) { | |
1072 | dev_info(&dev->dev, | |
1073 | "can't enable MSI (MSI-X already enabled)\n"); | |
1074 | return -EINVAL; | |
1075 | } | |
1076 | ||
302a2523 AG |
1077 | if (maxvec < minvec) |
1078 | return -ERANGE; | |
1079 | ||
034cd97e AG |
1080 | nvec = pci_msi_vec_count(dev); |
1081 | if (nvec < 0) | |
1082 | return nvec; | |
1083 | else if (nvec < minvec) | |
1084 | return -EINVAL; | |
1085 | else if (nvec > maxvec) | |
1086 | nvec = maxvec; | |
1087 | ||
302a2523 | 1088 | do { |
034cd97e | 1089 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1090 | if (rc < 0) { |
1091 | return rc; | |
1092 | } else if (rc > 0) { | |
1093 | if (rc < minvec) | |
1094 | return -ENOSPC; | |
1095 | nvec = rc; | |
1096 | } | |
1097 | } while (rc); | |
1098 | ||
1099 | return nvec; | |
1100 | } | |
1101 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1102 | ||
1103 | /** | |
1104 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1105 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1106 | * @entries: pointer to an array of MSI-X entries | |
1107 | * @minvec: minimum number of MSI-X irqs requested | |
1108 | * @maxvec: maximum number of MSI-X irqs requested | |
1109 | * | |
1110 | * Setup the MSI-X capability structure of device function with a maximum | |
1111 | * possible number of interrupts in the range between @minvec and @maxvec | |
1112 | * upon its software driver call to request for MSI-X mode enabled on its | |
1113 | * hardware device function. It returns a negative errno if an error occurs. | |
1114 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1115 | * indicates the successful configuration of MSI-X capability structure | |
1116 | * with new allocated MSI-X interrupts. | |
1117 | **/ | |
1118 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1119 | int minvec, int maxvec) | |
1120 | { | |
1121 | int nvec = maxvec; | |
1122 | int rc; | |
1123 | ||
1124 | if (maxvec < minvec) | |
1125 | return -ERANGE; | |
1126 | ||
1127 | do { | |
1128 | rc = pci_enable_msix(dev, entries, nvec); | |
1129 | if (rc < 0) { | |
1130 | return rc; | |
1131 | } else if (rc > 0) { | |
1132 | if (rc < minvec) | |
1133 | return -ENOSPC; | |
1134 | nvec = rc; | |
1135 | } | |
1136 | } while (rc); | |
1137 | ||
1138 | return nvec; | |
1139 | } | |
1140 | EXPORT_SYMBOL(pci_enable_msix_range); |