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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
1da177e4 | 24 | |
1da177e4 | 25 | static int pci_msi_enable = 1; |
38737d82 | 26 | int pci_msi_ignore_mask; |
1da177e4 | 27 | |
527eee29 BH |
28 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
29 | ||
30 | ||
6a9e7f20 AB |
31 | /* Arch hooks */ |
32 | ||
262a2baf YW |
33 | struct msi_controller * __weak pcibios_msi_controller(struct pci_dev *dev) |
34 | { | |
35 | return NULL; | |
36 | } | |
37 | ||
38 | static struct msi_controller *pci_msi_controller(struct pci_dev *dev) | |
39 | { | |
40 | struct msi_controller *msi_ctrl = dev->bus->msi; | |
41 | ||
42 | if (msi_ctrl) | |
43 | return msi_ctrl; | |
44 | ||
45 | return pcibios_msi_controller(dev); | |
46 | } | |
47 | ||
4287d824 TP |
48 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
49 | { | |
262a2baf | 50 | struct msi_controller *chip = pci_msi_controller(dev); |
0cbdcfcf TR |
51 | int err; |
52 | ||
53 | if (!chip || !chip->setup_irq) | |
54 | return -EINVAL; | |
55 | ||
56 | err = chip->setup_irq(chip, dev, desc); | |
57 | if (err < 0) | |
58 | return err; | |
59 | ||
60 | irq_set_chip_data(desc->irq, chip); | |
61 | ||
62 | return 0; | |
4287d824 TP |
63 | } |
64 | ||
65 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 66 | { |
c2791b80 | 67 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
68 | |
69 | if (!chip || !chip->teardown_irq) | |
70 | return; | |
71 | ||
72 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
73 | } |
74 | ||
4287d824 | 75 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
76 | { |
77 | struct msi_desc *entry; | |
78 | int ret; | |
79 | ||
1c8d7b0a MW |
80 | /* |
81 | * If an architecture wants to support multiple MSI, it needs to | |
82 | * override arch_setup_msi_irqs() | |
83 | */ | |
84 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
85 | return 1; | |
86 | ||
6a9e7f20 AB |
87 | list_for_each_entry(entry, &dev->msi_list, list) { |
88 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 89 | if (ret < 0) |
6a9e7f20 | 90 | return ret; |
b5fbf533 ME |
91 | if (ret > 0) |
92 | return -ENOSPC; | |
6a9e7f20 AB |
93 | } |
94 | ||
95 | return 0; | |
96 | } | |
1525bf0d | 97 | |
4287d824 TP |
98 | /* |
99 | * We have a default implementation available as a separate non-weak | |
100 | * function, as it is used by the Xen x86 PCI code | |
101 | */ | |
1525bf0d | 102 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
103 | { |
104 | struct msi_desc *entry; | |
105 | ||
106 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
107 | int i, nvec; |
108 | if (entry->irq == 0) | |
109 | continue; | |
65f6ae66 AG |
110 | if (entry->nvec_used) |
111 | nvec = entry->nvec_used; | |
112 | else | |
113 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
114 | for (i = 0; i < nvec; i++) |
115 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
116 | } |
117 | } | |
118 | ||
4287d824 TP |
119 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
120 | { | |
121 | return default_teardown_msi_irqs(dev); | |
122 | } | |
76ccc297 | 123 | |
ac8344c4 | 124 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
125 | { |
126 | struct msi_desc *entry; | |
127 | ||
128 | entry = NULL; | |
129 | if (dev->msix_enabled) { | |
130 | list_for_each_entry(entry, &dev->msi_list, list) { | |
131 | if (irq == entry->irq) | |
132 | break; | |
133 | } | |
134 | } else if (dev->msi_enabled) { | |
135 | entry = irq_get_msi_desc(irq); | |
136 | } | |
137 | ||
138 | if (entry) | |
56b72b40 | 139 | __write_msi_msg(entry, &entry->msg); |
76ccc297 | 140 | } |
4287d824 | 141 | |
ac8344c4 | 142 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 143 | { |
ac8344c4 | 144 | return default_restore_msi_irqs(dev); |
4287d824 | 145 | } |
76ccc297 | 146 | |
e375b561 | 147 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 148 | { |
b1cbf4e4 EB |
149 | u16 control; |
150 | ||
e375b561 | 151 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
152 | control &= ~PCI_MSI_FLAGS_ENABLE; |
153 | if (enable) | |
154 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 155 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
156 | } |
157 | ||
66f0d0c4 | 158 | static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
b1cbf4e4 | 159 | { |
66f0d0c4 | 160 | u16 ctrl; |
b1cbf4e4 | 161 | |
66f0d0c4 YW |
162 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); |
163 | ctrl &= ~clear; | |
164 | ctrl |= set; | |
165 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
b1cbf4e4 EB |
166 | } |
167 | ||
bffac3c5 MW |
168 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
169 | { | |
0b49ec37 MW |
170 | /* Don't shift by >= width of type */ |
171 | if (x >= 5) | |
172 | return 0xffffffff; | |
173 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
174 | } |
175 | ||
ce6fce42 MW |
176 | /* |
177 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
178 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
179 | * reliably as devices without an INTx disable bit will then generate a | |
180 | * level IRQ which will never be cleared. | |
ce6fce42 | 181 | */ |
03f56e42 | 182 | u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 183 | { |
f2440d9a | 184 | u32 mask_bits = desc->masked; |
1da177e4 | 185 | |
38737d82 | 186 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 187 | return 0; |
f2440d9a MW |
188 | |
189 | mask_bits &= ~mask; | |
190 | mask_bits |= flag; | |
191 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
192 | |
193 | return mask_bits; | |
194 | } | |
195 | ||
196 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
197 | { | |
03f56e42 | 198 | desc->masked = __msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
199 | } |
200 | ||
201 | /* | |
202 | * This internal function does not flush PCI writes to the device. | |
203 | * All users must ensure that they read from the device before either | |
204 | * assuming that the device state is up to date, or returning out of this | |
205 | * file. This saves a few milliseconds when initialising devices with lots | |
206 | * of MSI-X interrupts. | |
207 | */ | |
03f56e42 | 208 | u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
209 | { |
210 | u32 mask_bits = desc->masked; | |
211 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 212 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
38737d82 YW |
213 | |
214 | if (pci_msi_ignore_mask) | |
215 | return 0; | |
216 | ||
8d805286 SY |
217 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
218 | if (flag) | |
219 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 220 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
221 | |
222 | return mask_bits; | |
223 | } | |
224 | ||
225 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
226 | { | |
03f56e42 | 227 | desc->masked = __msix_mask_irq(desc, flag); |
f2440d9a | 228 | } |
24d27553 | 229 | |
1c9db525 | 230 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 231 | { |
1c9db525 | 232 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 233 | |
f2440d9a MW |
234 | if (desc->msi_attrib.is_msix) { |
235 | msix_mask_irq(desc, flag); | |
236 | readl(desc->mask_base); /* Flush write to device */ | |
237 | } else { | |
a281b788 | 238 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 239 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 240 | } |
f2440d9a MW |
241 | } |
242 | ||
1c9db525 | 243 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 244 | { |
1c9db525 | 245 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
246 | } |
247 | ||
1c9db525 | 248 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 249 | { |
1c9db525 | 250 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
251 | } |
252 | ||
ac8344c4 D |
253 | void default_restore_msi_irqs(struct pci_dev *dev) |
254 | { | |
255 | struct msi_desc *entry; | |
256 | ||
3f3cecae | 257 | list_for_each_entry(entry, &dev->msi_list, list) |
ac8344c4 | 258 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
259 | } |
260 | ||
39431acb | 261 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 262 | { |
30da5524 BH |
263 | BUG_ON(entry->dev->current_state != PCI_D0); |
264 | ||
265 | if (entry->msi_attrib.is_msix) { | |
266 | void __iomem *base = entry->mask_base + | |
267 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
268 | ||
269 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
270 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
271 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
272 | } else { | |
273 | struct pci_dev *dev = entry->dev; | |
f5322169 | 274 | int pos = dev->msi_cap; |
30da5524 BH |
275 | u16 data; |
276 | ||
9925ad0c BH |
277 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
278 | &msg->address_lo); | |
30da5524 | 279 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
280 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
281 | &msg->address_hi); | |
2f221349 | 282 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
283 | } else { |
284 | msg->address_hi = 0; | |
2f221349 | 285 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
286 | } |
287 | msg->data = data; | |
288 | } | |
289 | } | |
290 | ||
291 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
292 | { | |
dced35ae | 293 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 294 | |
39431acb | 295 | __read_msi_msg(entry, msg); |
30da5524 BH |
296 | } |
297 | ||
39431acb | 298 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 299 | { |
30da5524 | 300 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
301 | * valid messages are not all-zeroes. */ |
302 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
303 | entry->msg.data)); | |
0366f8f7 | 304 | |
fcd097f3 | 305 | *msg = entry->msg; |
0366f8f7 | 306 | } |
1da177e4 | 307 | |
30da5524 | 308 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 309 | { |
dced35ae | 310 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 311 | |
39431acb | 312 | __get_cached_msi_msg(entry, msg); |
3145e941 | 313 | } |
3b307ffe | 314 | EXPORT_SYMBOL_GPL(get_cached_msi_msg); |
3145e941 | 315 | |
39431acb | 316 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 317 | { |
fcd097f3 BH |
318 | if (entry->dev->current_state != PCI_D0) { |
319 | /* Don't touch the hardware now */ | |
320 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
321 | void __iomem *base; |
322 | base = entry->mask_base + | |
323 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
324 | ||
2c21fd4b HS |
325 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
326 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
327 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 328 | } else { |
0366f8f7 | 329 | struct pci_dev *dev = entry->dev; |
f5322169 | 330 | int pos = dev->msi_cap; |
1c8d7b0a MW |
331 | u16 msgctl; |
332 | ||
f84ecd28 | 333 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
334 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
335 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 336 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 337 | |
9925ad0c BH |
338 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
339 | msg->address_lo); | |
0366f8f7 | 340 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
341 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
342 | msg->address_hi); | |
2f221349 BH |
343 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
344 | msg->data); | |
0366f8f7 | 345 | } else { |
2f221349 BH |
346 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
347 | msg->data); | |
0366f8f7 | 348 | } |
1da177e4 | 349 | } |
392ee1e6 | 350 | entry->msg = *msg; |
1da177e4 | 351 | } |
0366f8f7 | 352 | |
3145e941 YL |
353 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
354 | { | |
dced35ae | 355 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 356 | |
39431acb | 357 | __write_msi_msg(entry, msg); |
3145e941 | 358 | } |
3b307ffe | 359 | EXPORT_SYMBOL_GPL(write_msi_msg); |
3145e941 | 360 | |
f56e4481 HS |
361 | static void free_msi_irqs(struct pci_dev *dev) |
362 | { | |
363 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
364 | struct attribute **msi_attrs; |
365 | struct device_attribute *dev_attr; | |
366 | int count = 0; | |
f56e4481 HS |
367 | |
368 | list_for_each_entry(entry, &dev->msi_list, list) { | |
369 | int i, nvec; | |
370 | if (!entry->irq) | |
371 | continue; | |
65f6ae66 AG |
372 | if (entry->nvec_used) |
373 | nvec = entry->nvec_used; | |
374 | else | |
375 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
376 | for (i = 0; i < nvec; i++) |
377 | BUG_ON(irq_has_action(entry->irq + i)); | |
378 | } | |
379 | ||
380 | arch_teardown_msi_irqs(dev); | |
381 | ||
382 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
383 | if (entry->msi_attrib.is_msix) { | |
384 | if (list_is_last(&entry->list, &dev->msi_list)) | |
385 | iounmap(entry->mask_base); | |
386 | } | |
424eb391 | 387 | |
f56e4481 HS |
388 | list_del(&entry->list); |
389 | kfree(entry); | |
390 | } | |
1c51b50c GKH |
391 | |
392 | if (dev->msi_irq_groups) { | |
393 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
394 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 395 | while (msi_attrs[count]) { |
1c51b50c GKH |
396 | dev_attr = container_of(msi_attrs[count], |
397 | struct device_attribute, attr); | |
398 | kfree(dev_attr->attr.name); | |
399 | kfree(dev_attr); | |
400 | ++count; | |
401 | } | |
402 | kfree(msi_attrs); | |
403 | kfree(dev->msi_irq_groups[0]); | |
404 | kfree(dev->msi_irq_groups); | |
405 | dev->msi_irq_groups = NULL; | |
406 | } | |
f56e4481 | 407 | } |
c54c1879 | 408 | |
379f5327 | 409 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 410 | { |
379f5327 MW |
411 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
412 | if (!desc) | |
1da177e4 LT |
413 | return NULL; |
414 | ||
379f5327 MW |
415 | INIT_LIST_HEAD(&desc->list); |
416 | desc->dev = dev; | |
1da177e4 | 417 | |
379f5327 | 418 | return desc; |
1da177e4 LT |
419 | } |
420 | ||
ba698ad4 DM |
421 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
422 | { | |
423 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
424 | pci_intx(dev, enable); | |
425 | } | |
426 | ||
8fed4b65 | 427 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 428 | { |
41017f0c | 429 | u16 control; |
392ee1e6 | 430 | struct msi_desc *entry; |
41017f0c | 431 | |
b1cbf4e4 EB |
432 | if (!dev->msi_enabled) |
433 | return; | |
434 | ||
dced35ae | 435 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 436 | |
ba698ad4 | 437 | pci_intx_for_msi(dev, 0); |
e375b561 | 438 | msi_set_enable(dev, 0); |
ac8344c4 | 439 | arch_restore_msi_irqs(dev); |
392ee1e6 | 440 | |
f5322169 | 441 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
442 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
443 | entry->masked); | |
abad2ec9 | 444 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 445 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 446 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
447 | } |
448 | ||
449 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 450 | { |
41017f0c | 451 | struct msi_desc *entry; |
41017f0c | 452 | |
ded86d8d EB |
453 | if (!dev->msix_enabled) |
454 | return; | |
f598282f | 455 | BUG_ON(list_empty(&dev->msi_list)); |
ded86d8d | 456 | |
41017f0c | 457 | /* route the table */ |
ba698ad4 | 458 | pci_intx_for_msi(dev, 0); |
66f0d0c4 YW |
459 | msix_clear_and_set_ctrl(dev, 0, |
460 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); | |
41017f0c | 461 | |
ac8344c4 | 462 | arch_restore_msi_irqs(dev); |
3f3cecae | 463 | list_for_each_entry(entry, &dev->msi_list, list) |
f2440d9a | 464 | msix_mask_irq(entry, entry->masked); |
41017f0c | 465 | |
66f0d0c4 | 466 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 467 | } |
8fed4b65 ME |
468 | |
469 | void pci_restore_msi_state(struct pci_dev *dev) | |
470 | { | |
471 | __pci_restore_msi_state(dev); | |
472 | __pci_restore_msix_state(dev); | |
473 | } | |
94688cf2 | 474 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 475 | |
1c51b50c | 476 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
477 | char *buf) |
478 | { | |
1c51b50c GKH |
479 | struct msi_desc *entry; |
480 | unsigned long irq; | |
481 | int retval; | |
da8d1c8b | 482 | |
1c51b50c GKH |
483 | retval = kstrtoul(attr->attr.name, 10, &irq); |
484 | if (retval) | |
485 | return retval; | |
da8d1c8b | 486 | |
e11ece5a YW |
487 | entry = irq_get_msi_desc(irq); |
488 | if (entry) | |
489 | return sprintf(buf, "%s\n", | |
490 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
491 | ||
1c51b50c | 492 | return -ENODEV; |
da8d1c8b NH |
493 | } |
494 | ||
da8d1c8b NH |
495 | static int populate_msi_sysfs(struct pci_dev *pdev) |
496 | { | |
1c51b50c GKH |
497 | struct attribute **msi_attrs; |
498 | struct attribute *msi_attr; | |
499 | struct device_attribute *msi_dev_attr; | |
500 | struct attribute_group *msi_irq_group; | |
501 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 502 | struct msi_desc *entry; |
1c51b50c GKH |
503 | int ret = -ENOMEM; |
504 | int num_msi = 0; | |
da8d1c8b NH |
505 | int count = 0; |
506 | ||
1c51b50c | 507 | /* Determine how many msi entries we have */ |
3f3cecae | 508 | list_for_each_entry(entry, &pdev->msi_list, list) |
1c51b50c | 509 | ++num_msi; |
1c51b50c GKH |
510 | if (!num_msi) |
511 | return 0; | |
da8d1c8b | 512 | |
1c51b50c GKH |
513 | /* Dynamically create the MSI attributes for the PCI device */ |
514 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
515 | if (!msi_attrs) | |
516 | return -ENOMEM; | |
da8d1c8b | 517 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 518 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 519 | if (!msi_dev_attr) |
1c51b50c | 520 | goto error_attrs; |
1406276c | 521 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 522 | |
1c51b50c | 523 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
524 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
525 | entry->irq); | |
526 | if (!msi_dev_attr->attr.name) | |
527 | goto error_attrs; | |
1c51b50c GKH |
528 | msi_dev_attr->attr.mode = S_IRUGO; |
529 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 530 | ++count; |
da8d1c8b NH |
531 | } |
532 | ||
1c51b50c GKH |
533 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
534 | if (!msi_irq_group) | |
535 | goto error_attrs; | |
536 | msi_irq_group->name = "msi_irqs"; | |
537 | msi_irq_group->attrs = msi_attrs; | |
538 | ||
539 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
540 | if (!msi_irq_groups) | |
541 | goto error_irq_group; | |
542 | msi_irq_groups[0] = msi_irq_group; | |
543 | ||
544 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
545 | if (ret) | |
546 | goto error_irq_groups; | |
547 | pdev->msi_irq_groups = msi_irq_groups; | |
548 | ||
da8d1c8b NH |
549 | return 0; |
550 | ||
1c51b50c GKH |
551 | error_irq_groups: |
552 | kfree(msi_irq_groups); | |
553 | error_irq_group: | |
554 | kfree(msi_irq_group); | |
555 | error_attrs: | |
556 | count = 0; | |
557 | msi_attr = msi_attrs[count]; | |
558 | while (msi_attr) { | |
559 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
560 | kfree(msi_attr->name); | |
561 | kfree(msi_dev_attr); | |
562 | ++count; | |
563 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 564 | } |
29237756 | 565 | kfree(msi_attrs); |
da8d1c8b NH |
566 | return ret; |
567 | } | |
568 | ||
d873b4d4 YW |
569 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev) |
570 | { | |
571 | u16 control; | |
572 | struct msi_desc *entry; | |
573 | ||
574 | /* MSI Entry Initialization */ | |
575 | entry = alloc_msi_entry(dev); | |
576 | if (!entry) | |
577 | return NULL; | |
578 | ||
579 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
580 | ||
581 | entry->msi_attrib.is_msix = 0; | |
582 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
583 | entry->msi_attrib.entry_nr = 0; | |
584 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
585 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 YW |
586 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
587 | ||
588 | if (control & PCI_MSI_FLAGS_64BIT) | |
589 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
590 | else | |
591 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
592 | ||
593 | /* Save the initial mask status */ | |
594 | if (entry->msi_attrib.maskbit) | |
595 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
596 | ||
597 | return entry; | |
598 | } | |
599 | ||
1da177e4 LT |
600 | /** |
601 | * msi_capability_init - configure device's MSI capability structure | |
602 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 603 | * @nvec: number of interrupts to allocate |
1da177e4 | 604 | * |
1c8d7b0a MW |
605 | * Setup the MSI capability structure of the device with the requested |
606 | * number of interrupts. A return value of zero indicates the successful | |
607 | * setup of an entry with the new MSI irq. A negative return value indicates | |
608 | * an error, and a positive return value indicates the number of interrupts | |
609 | * which could have been allocated. | |
610 | */ | |
611 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
612 | { |
613 | struct msi_desc *entry; | |
f465136d | 614 | int ret; |
f2440d9a | 615 | unsigned mask; |
1da177e4 | 616 | |
e375b561 | 617 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 618 | |
d873b4d4 | 619 | entry = msi_setup_entry(dev); |
f7feaca7 EB |
620 | if (!entry) |
621 | return -ENOMEM; | |
1ce03373 | 622 | |
f2440d9a | 623 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 624 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
625 | msi_mask_irq(entry, mask, mask); |
626 | ||
0dd11f9b | 627 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 628 | |
1da177e4 | 629 | /* Configure MSI capability structure */ |
1c8d7b0a | 630 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 631 | if (ret) { |
7ba1930d | 632 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 633 | free_msi_irqs(dev); |
7fe3730d | 634 | return ret; |
fd58e55f | 635 | } |
f7feaca7 | 636 | |
da8d1c8b NH |
637 | ret = populate_msi_sysfs(dev); |
638 | if (ret) { | |
639 | msi_mask_irq(entry, mask, ~mask); | |
640 | free_msi_irqs(dev); | |
641 | return ret; | |
642 | } | |
643 | ||
1da177e4 | 644 | /* Set MSI enabled bits */ |
ba698ad4 | 645 | pci_intx_for_msi(dev, 0); |
e375b561 | 646 | msi_set_enable(dev, 1); |
b1cbf4e4 | 647 | dev->msi_enabled = 1; |
1da177e4 | 648 | |
7fe3730d | 649 | dev->irq = entry->irq; |
1da177e4 LT |
650 | return 0; |
651 | } | |
652 | ||
520fe9dc | 653 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 654 | { |
4302e0fb | 655 | resource_size_t phys_addr; |
5a05a9d8 HS |
656 | u32 table_offset; |
657 | u8 bir; | |
658 | ||
909094c6 BH |
659 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
660 | &table_offset); | |
4d18760c BH |
661 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
662 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
663 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
664 | ||
665 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
666 | } | |
667 | ||
520fe9dc GS |
668 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
669 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
670 | { |
671 | struct msi_desc *entry; | |
672 | int i; | |
673 | ||
674 | for (i = 0; i < nvec; i++) { | |
675 | entry = alloc_msi_entry(dev); | |
676 | if (!entry) { | |
677 | if (!i) | |
678 | iounmap(base); | |
679 | else | |
680 | free_msi_irqs(dev); | |
681 | /* No enough memory. Don't try again */ | |
682 | return -ENOMEM; | |
683 | } | |
684 | ||
685 | entry->msi_attrib.is_msix = 1; | |
686 | entry->msi_attrib.is_64 = 1; | |
687 | entry->msi_attrib.entry_nr = entries[i].entry; | |
688 | entry->msi_attrib.default_irq = dev->irq; | |
d9d7070e HS |
689 | entry->mask_base = base; |
690 | ||
691 | list_add_tail(&entry->list, &dev->msi_list); | |
692 | } | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
75cb3426 | 697 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 698 | struct msix_entry *entries) |
75cb3426 HS |
699 | { |
700 | struct msi_desc *entry; | |
701 | int i = 0; | |
702 | ||
703 | list_for_each_entry(entry, &dev->msi_list, list) { | |
704 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
705 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
706 | ||
707 | entries[i].vector = entry->irq; | |
dced35ae | 708 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
709 | entry->masked = readl(entry->mask_base + offset); |
710 | msix_mask_irq(entry, 1); | |
711 | i++; | |
712 | } | |
713 | } | |
714 | ||
1da177e4 LT |
715 | /** |
716 | * msix_capability_init - configure device's MSI-X capability | |
717 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
718 | * @entries: pointer to an array of struct msix_entry entries |
719 | * @nvec: number of @entries | |
1da177e4 | 720 | * |
eaae4b3a | 721 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
722 | * single MSI-X irq. A return of zero indicates the successful setup of |
723 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
724 | **/ |
725 | static int msix_capability_init(struct pci_dev *dev, | |
726 | struct msix_entry *entries, int nvec) | |
727 | { | |
520fe9dc | 728 | int ret; |
5a05a9d8 | 729 | u16 control; |
1da177e4 LT |
730 | void __iomem *base; |
731 | ||
f598282f | 732 | /* Ensure MSI-X is disabled while it is set up */ |
66f0d0c4 | 733 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 734 | |
66f0d0c4 | 735 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 736 | /* Request & Map MSI-X table region */ |
527eee29 | 737 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 738 | if (!base) |
1da177e4 LT |
739 | return -ENOMEM; |
740 | ||
520fe9dc | 741 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
742 | if (ret) |
743 | return ret; | |
9c831334 ME |
744 | |
745 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 | 746 | if (ret) |
2adc7907 | 747 | goto out_avail; |
9c831334 | 748 | |
f598282f MW |
749 | /* |
750 | * Some devices require MSI-X to be enabled before we can touch the | |
751 | * MSI-X registers. We need to mask all the vectors to prevent | |
752 | * interrupts coming in before they're fully set up. | |
753 | */ | |
66f0d0c4 YW |
754 | msix_clear_and_set_ctrl(dev, 0, |
755 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); | |
f598282f | 756 | |
75cb3426 | 757 | msix_program_entries(dev, entries); |
f598282f | 758 | |
da8d1c8b | 759 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
760 | if (ret) |
761 | goto out_free; | |
da8d1c8b | 762 | |
f598282f | 763 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 764 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 765 | dev->msix_enabled = 1; |
1da177e4 | 766 | |
66f0d0c4 | 767 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 768 | |
1da177e4 | 769 | return 0; |
583871d4 | 770 | |
2adc7907 | 771 | out_avail: |
583871d4 HS |
772 | if (ret < 0) { |
773 | /* | |
774 | * If we had some success, report the number of irqs | |
775 | * we succeeded in setting up. | |
776 | */ | |
d9d7070e | 777 | struct msi_desc *entry; |
583871d4 HS |
778 | int avail = 0; |
779 | ||
780 | list_for_each_entry(entry, &dev->msi_list, list) { | |
781 | if (entry->irq != 0) | |
782 | avail++; | |
783 | } | |
784 | if (avail != 0) | |
785 | ret = avail; | |
786 | } | |
787 | ||
2adc7907 | 788 | out_free: |
583871d4 HS |
789 | free_msi_irqs(dev); |
790 | ||
791 | return ret; | |
1da177e4 LT |
792 | } |
793 | ||
24334a12 | 794 | /** |
a06cd74c | 795 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 796 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 797 | * @nvec: how many MSIs have been requested ? |
24334a12 | 798 | * |
f7625980 | 799 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 800 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 801 | * supported return 1, else return 0. |
24334a12 | 802 | **/ |
a06cd74c | 803 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
804 | { |
805 | struct pci_bus *bus; | |
806 | ||
0306ebfa | 807 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 808 | if (!pci_msi_enable) |
a06cd74c | 809 | return 0; |
27e20603 AG |
810 | |
811 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 812 | return 0; |
24334a12 | 813 | |
314e77b3 ME |
814 | /* |
815 | * You can't ask to have 0 or less MSIs configured. | |
816 | * a) it's stupid .. | |
817 | * b) the list manipulation code assumes nvec >= 1. | |
818 | */ | |
819 | if (nvec < 1) | |
a06cd74c | 820 | return 0; |
314e77b3 | 821 | |
500559a9 HS |
822 | /* |
823 | * Any bridge which does NOT route MSI transactions from its | |
824 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
825 | * the secondary pci_bus. |
826 | * We expect only arch-specific PCI host bus controller driver | |
827 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
828 | */ | |
24334a12 BG |
829 | for (bus = dev->bus; bus; bus = bus->parent) |
830 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 831 | return 0; |
24334a12 | 832 | |
a06cd74c | 833 | return 1; |
24334a12 BG |
834 | } |
835 | ||
d1ac1d26 AG |
836 | /** |
837 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
838 | * @dev: device to report about | |
839 | * | |
840 | * This function returns the number of MSI vectors a device requested via | |
841 | * Multiple Message Capable register. It returns a negative errno if the | |
842 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
843 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
844 | * MSI specification. | |
845 | **/ | |
846 | int pci_msi_vec_count(struct pci_dev *dev) | |
847 | { | |
848 | int ret; | |
849 | u16 msgctl; | |
850 | ||
851 | if (!dev->msi_cap) | |
852 | return -EINVAL; | |
853 | ||
854 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
855 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
856 | ||
857 | return ret; | |
858 | } | |
859 | EXPORT_SYMBOL(pci_msi_vec_count); | |
860 | ||
f2440d9a | 861 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 862 | { |
f2440d9a MW |
863 | struct msi_desc *desc; |
864 | u32 mask; | |
1da177e4 | 865 | |
128bc5fc | 866 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
867 | return; |
868 | ||
110828c9 MW |
869 | BUG_ON(list_empty(&dev->msi_list)); |
870 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 871 | |
e375b561 | 872 | msi_set_enable(dev, 0); |
ba698ad4 | 873 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 874 | dev->msi_enabled = 0; |
7bd007e4 | 875 | |
12abb8ba | 876 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 877 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 878 | /* Keep cached state to be restored */ |
03f56e42 | 879 | __msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
880 | |
881 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 882 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 883 | } |
24d27553 | 884 | |
500559a9 | 885 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 886 | { |
d52877c7 YL |
887 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
888 | return; | |
889 | ||
890 | pci_msi_shutdown(dev); | |
f56e4481 | 891 | free_msi_irqs(dev); |
1da177e4 | 892 | } |
4cc086fa | 893 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 894 | |
a52e2e35 | 895 | /** |
ff1aa430 | 896 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 897 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
898 | * This function returns the number of device's MSI-X table entries and |
899 | * therefore the number of MSI-X vectors device is capable of sending. | |
900 | * It returns a negative errno if the device is not capable of sending MSI-X | |
901 | * interrupts. | |
902 | **/ | |
903 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 904 | { |
a52e2e35 RW |
905 | u16 control; |
906 | ||
520fe9dc | 907 | if (!dev->msix_cap) |
ff1aa430 | 908 | return -EINVAL; |
a52e2e35 | 909 | |
f84ecd28 | 910 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 911 | return msix_table_size(control); |
a52e2e35 | 912 | } |
ff1aa430 | 913 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 914 | |
1da177e4 LT |
915 | /** |
916 | * pci_enable_msix - configure device's MSI-X capability structure | |
917 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 918 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 919 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
920 | * |
921 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 922 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
923 | * MSI-X mode enabled on its hardware device function. A return of zero |
924 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 925 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 926 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
927 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
928 | * re-send its request. | |
1da177e4 | 929 | **/ |
500559a9 | 930 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 931 | { |
5ec09405 | 932 | int nr_entries; |
ded86d8d | 933 | int i, j; |
1da177e4 | 934 | |
a06cd74c AG |
935 | if (!pci_msi_supported(dev, nvec)) |
936 | return -EINVAL; | |
c9953a73 | 937 | |
27e20603 AG |
938 | if (!entries) |
939 | return -EINVAL; | |
940 | ||
ff1aa430 AG |
941 | nr_entries = pci_msix_vec_count(dev); |
942 | if (nr_entries < 0) | |
943 | return nr_entries; | |
1da177e4 | 944 | if (nvec > nr_entries) |
57fbf52c | 945 | return nr_entries; |
1da177e4 LT |
946 | |
947 | /* Check for any invalid entries */ | |
948 | for (i = 0; i < nvec; i++) { | |
949 | if (entries[i].entry >= nr_entries) | |
950 | return -EINVAL; /* invalid entry */ | |
951 | for (j = i + 1; j < nvec; j++) { | |
952 | if (entries[i].entry == entries[j].entry) | |
953 | return -EINVAL; /* duplicate entry */ | |
954 | } | |
955 | } | |
ded86d8d | 956 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 957 | |
1ce03373 | 958 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 959 | if (dev->msi_enabled) { |
227f0647 | 960 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
961 | return -EINVAL; |
962 | } | |
5ec09405 | 963 | return msix_capability_init(dev, entries, nvec); |
1da177e4 | 964 | } |
4cc086fa | 965 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 966 | |
500559a9 | 967 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 968 | { |
12abb8ba HS |
969 | struct msi_desc *entry; |
970 | ||
128bc5fc | 971 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
972 | return; |
973 | ||
12abb8ba HS |
974 | /* Return the device with MSI-X masked as initial states */ |
975 | list_for_each_entry(entry, &dev->msi_list, list) { | |
976 | /* Keep cached states to be restored */ | |
03f56e42 | 977 | __msix_mask_irq(entry, 1); |
12abb8ba HS |
978 | } |
979 | ||
66f0d0c4 | 980 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 981 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 982 | dev->msix_enabled = 0; |
d52877c7 | 983 | } |
c901851f | 984 | |
500559a9 | 985 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
986 | { |
987 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
988 | return; | |
989 | ||
990 | pci_msix_shutdown(dev); | |
f56e4481 | 991 | free_msi_irqs(dev); |
1da177e4 | 992 | } |
4cc086fa | 993 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 994 | |
309e57df MW |
995 | void pci_no_msi(void) |
996 | { | |
997 | pci_msi_enable = 0; | |
998 | } | |
c9953a73 | 999 | |
07ae95f9 AP |
1000 | /** |
1001 | * pci_msi_enabled - is MSI enabled? | |
1002 | * | |
1003 | * Returns true if MSI has not been disabled by the command-line option | |
1004 | * pci=nomsi. | |
1005 | **/ | |
1006 | int pci_msi_enabled(void) | |
d389fec6 | 1007 | { |
07ae95f9 | 1008 | return pci_msi_enable; |
d389fec6 | 1009 | } |
07ae95f9 | 1010 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1011 | |
07ae95f9 | 1012 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1013 | { |
07ae95f9 | 1014 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1015 | |
1016 | /* Disable the msi hardware to avoid screaming interrupts | |
1017 | * during boot. This is the power on reset default so | |
1018 | * usually this should be a noop. | |
1019 | */ | |
e375b561 GS |
1020 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1021 | if (dev->msi_cap) | |
1022 | msi_set_enable(dev, 0); | |
1023 | ||
1024 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1025 | if (dev->msix_cap) | |
66f0d0c4 | 1026 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
d389fec6 | 1027 | } |
302a2523 AG |
1028 | |
1029 | /** | |
1030 | * pci_enable_msi_range - configure device's MSI capability structure | |
1031 | * @dev: device to configure | |
1032 | * @minvec: minimal number of interrupts to configure | |
1033 | * @maxvec: maximum number of interrupts to configure | |
1034 | * | |
1035 | * This function tries to allocate a maximum possible number of interrupts in a | |
1036 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1037 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1038 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1039 | * the other interrupt numbers allocated to this device are consecutive. | |
1040 | **/ | |
1041 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1042 | { | |
034cd97e | 1043 | int nvec; |
302a2523 AG |
1044 | int rc; |
1045 | ||
a06cd74c AG |
1046 | if (!pci_msi_supported(dev, minvec)) |
1047 | return -EINVAL; | |
034cd97e AG |
1048 | |
1049 | WARN_ON(!!dev->msi_enabled); | |
1050 | ||
1051 | /* Check whether driver already requested MSI-X irqs */ | |
1052 | if (dev->msix_enabled) { | |
1053 | dev_info(&dev->dev, | |
1054 | "can't enable MSI (MSI-X already enabled)\n"); | |
1055 | return -EINVAL; | |
1056 | } | |
1057 | ||
302a2523 AG |
1058 | if (maxvec < minvec) |
1059 | return -ERANGE; | |
1060 | ||
034cd97e AG |
1061 | nvec = pci_msi_vec_count(dev); |
1062 | if (nvec < 0) | |
1063 | return nvec; | |
1064 | else if (nvec < minvec) | |
1065 | return -EINVAL; | |
1066 | else if (nvec > maxvec) | |
1067 | nvec = maxvec; | |
1068 | ||
302a2523 | 1069 | do { |
034cd97e | 1070 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1071 | if (rc < 0) { |
1072 | return rc; | |
1073 | } else if (rc > 0) { | |
1074 | if (rc < minvec) | |
1075 | return -ENOSPC; | |
1076 | nvec = rc; | |
1077 | } | |
1078 | } while (rc); | |
1079 | ||
1080 | return nvec; | |
1081 | } | |
1082 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1083 | ||
1084 | /** | |
1085 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1086 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1087 | * @entries: pointer to an array of MSI-X entries | |
1088 | * @minvec: minimum number of MSI-X irqs requested | |
1089 | * @maxvec: maximum number of MSI-X irqs requested | |
1090 | * | |
1091 | * Setup the MSI-X capability structure of device function with a maximum | |
1092 | * possible number of interrupts in the range between @minvec and @maxvec | |
1093 | * upon its software driver call to request for MSI-X mode enabled on its | |
1094 | * hardware device function. It returns a negative errno if an error occurs. | |
1095 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1096 | * indicates the successful configuration of MSI-X capability structure | |
1097 | * with new allocated MSI-X interrupts. | |
1098 | **/ | |
1099 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1100 | int minvec, int maxvec) | |
1101 | { | |
1102 | int nvec = maxvec; | |
1103 | int rc; | |
1104 | ||
1105 | if (maxvec < minvec) | |
1106 | return -ERANGE; | |
1107 | ||
1108 | do { | |
1109 | rc = pci_enable_msix(dev, entries, nvec); | |
1110 | if (rc < 0) { | |
1111 | return rc; | |
1112 | } else if (rc > 0) { | |
1113 | if (rc < minvec) | |
1114 | return -ENOSPC; | |
1115 | nvec = rc; | |
1116 | } | |
1117 | } while (rc); | |
1118 | ||
1119 | return nvec; | |
1120 | } | |
1121 | EXPORT_SYMBOL(pci_enable_msix_range); |