]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
30 | int __attribute__ ((weak)) | |
31 | arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
32 | { | |
33 | return 0; | |
34 | } | |
35 | ||
36 | int __attribute__ ((weak)) | |
37 | arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry) | |
38 | { | |
39 | return 0; | |
40 | } | |
41 | ||
42 | int __attribute__ ((weak)) | |
43 | arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
44 | { | |
45 | struct msi_desc *entry; | |
46 | int ret; | |
47 | ||
48 | list_for_each_entry(entry, &dev->msi_list, list) { | |
49 | ret = arch_setup_msi_irq(dev, entry); | |
50 | if (ret) | |
51 | return ret; | |
52 | } | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq) | |
58 | { | |
59 | return; | |
60 | } | |
61 | ||
62 | void __attribute__ ((weak)) | |
63 | arch_teardown_msi_irqs(struct pci_dev *dev) | |
64 | { | |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
68 | if (entry->irq != 0) | |
69 | arch_teardown_msi_irq(entry->irq); | |
70 | } | |
71 | } | |
72 | ||
5ca5c02f | 73 | static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 74 | { |
b1cbf4e4 EB |
75 | u16 control; |
76 | ||
b1cbf4e4 EB |
77 | if (pos) { |
78 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
79 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
80 | if (enable) | |
81 | control |= PCI_MSI_FLAGS_ENABLE; | |
82 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
83 | } | |
84 | } | |
85 | ||
5ca5c02f HS |
86 | static void msi_set_enable(struct pci_dev *dev, int enable) |
87 | { | |
88 | __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); | |
89 | } | |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
3145e941 | 106 | static void msix_flush_writes(struct irq_desc *desc) |
988cbb15 MW |
107 | { |
108 | struct msi_desc *entry; | |
109 | ||
3145e941 | 110 | entry = get_irq_desc_msi(desc); |
988cbb15 MW |
111 | BUG_ON(!entry || !entry->dev); |
112 | switch (entry->msi_attrib.type) { | |
113 | case PCI_CAP_ID_MSI: | |
114 | /* nothing to do */ | |
115 | break; | |
116 | case PCI_CAP_ID_MSIX: | |
117 | { | |
118 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
119 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
120 | readl(entry->mask_base + offset); | |
121 | break; | |
122 | } | |
123 | default: | |
124 | BUG(); | |
125 | break; | |
126 | } | |
127 | } | |
128 | ||
ce6fce42 MW |
129 | /* |
130 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
131 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
132 | * reliably as devices without an INTx disable bit will then generate a | |
133 | * level IRQ which will never be cleared. | |
134 | * | |
135 | * Returns 1 if it succeeded in masking the interrupt and 0 if the device | |
136 | * doesn't support MSI masking. | |
137 | */ | |
3145e941 | 138 | static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag) |
1da177e4 LT |
139 | { |
140 | struct msi_desc *entry; | |
141 | ||
3145e941 | 142 | entry = get_irq_desc_msi(desc); |
277bc33b | 143 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
144 | switch (entry->msi_attrib.type) { |
145 | case PCI_CAP_ID_MSI: | |
277bc33b | 146 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
147 | int pos; |
148 | u32 mask_bits; | |
277bc33b EB |
149 | |
150 | pos = (long)entry->mask_base; | |
151 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
8e149e09 YL |
152 | mask_bits &= ~(mask); |
153 | mask_bits |= flag & mask; | |
277bc33b | 154 | pci_write_config_dword(entry->dev, pos, mask_bits); |
58e0543e | 155 | } else { |
ce6fce42 | 156 | return 0; |
277bc33b | 157 | } |
1da177e4 | 158 | break; |
1da177e4 LT |
159 | case PCI_CAP_ID_MSIX: |
160 | { | |
161 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
162 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
163 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 164 | readl(entry->mask_base + offset); |
1da177e4 LT |
165 | break; |
166 | } | |
167 | default: | |
277bc33b | 168 | BUG(); |
1da177e4 LT |
169 | break; |
170 | } | |
392ee1e6 | 171 | entry->msi_attrib.masked = !!flag; |
ce6fce42 | 172 | return 1; |
1da177e4 LT |
173 | } |
174 | ||
3145e941 | 175 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 176 | { |
3145e941 | 177 | struct msi_desc *entry = get_irq_desc_msi(desc); |
0366f8f7 EB |
178 | switch(entry->msi_attrib.type) { |
179 | case PCI_CAP_ID_MSI: | |
180 | { | |
181 | struct pci_dev *dev = entry->dev; | |
182 | int pos = entry->msi_attrib.pos; | |
183 | u16 data; | |
184 | ||
185 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
186 | &msg->address_lo); | |
187 | if (entry->msi_attrib.is_64) { | |
188 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
189 | &msg->address_hi); | |
190 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
191 | } else { | |
192 | msg->address_hi = 0; | |
cbf5d9e6 | 193 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
194 | } |
195 | msg->data = data; | |
196 | break; | |
197 | } | |
198 | case PCI_CAP_ID_MSIX: | |
199 | { | |
200 | void __iomem *base; | |
201 | base = entry->mask_base + | |
202 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
203 | ||
204 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
205 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
206 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
207 | break; | |
208 | } | |
209 | default: | |
210 | BUG(); | |
211 | } | |
212 | } | |
1da177e4 | 213 | |
3145e941 | 214 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 215 | { |
3145e941 YL |
216 | struct irq_desc *desc = irq_to_desc(irq); |
217 | ||
218 | read_msi_msg_desc(desc, msg); | |
219 | } | |
220 | ||
221 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
222 | { | |
223 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
1da177e4 LT |
224 | switch (entry->msi_attrib.type) { |
225 | case PCI_CAP_ID_MSI: | |
226 | { | |
0366f8f7 EB |
227 | struct pci_dev *dev = entry->dev; |
228 | int pos = entry->msi_attrib.pos; | |
229 | ||
230 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
231 | msg->address_lo); | |
232 | if (entry->msi_attrib.is_64) { | |
233 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
234 | msg->address_hi); | |
235 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
236 | msg->data); | |
237 | } else { | |
238 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
239 | msg->data); | |
240 | } | |
1da177e4 LT |
241 | break; |
242 | } | |
243 | case PCI_CAP_ID_MSIX: | |
244 | { | |
0366f8f7 EB |
245 | void __iomem *base; |
246 | base = entry->mask_base + | |
247 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
248 | ||
249 | writel(msg->address_lo, | |
250 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
251 | writel(msg->address_hi, | |
252 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
253 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
254 | break; |
255 | } | |
256 | default: | |
0366f8f7 | 257 | BUG(); |
1da177e4 | 258 | } |
392ee1e6 | 259 | entry->msg = *msg; |
1da177e4 | 260 | } |
0366f8f7 | 261 | |
3145e941 YL |
262 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
263 | { | |
264 | struct irq_desc *desc = irq_to_desc(irq); | |
265 | ||
266 | write_msi_msg_desc(desc, msg); | |
267 | } | |
268 | ||
3b7d1921 | 269 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 270 | { |
3145e941 YL |
271 | struct irq_desc *desc = irq_to_desc(irq); |
272 | ||
273 | msi_set_mask_bits(desc, 1, 1); | |
274 | msix_flush_writes(desc); | |
1da177e4 LT |
275 | } |
276 | ||
3b7d1921 | 277 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 278 | { |
3145e941 YL |
279 | struct irq_desc *desc = irq_to_desc(irq); |
280 | ||
281 | msi_set_mask_bits(desc, 1, 0); | |
282 | msix_flush_writes(desc); | |
1da177e4 LT |
283 | } |
284 | ||
032de8e2 | 285 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 286 | |
1da177e4 LT |
287 | static struct msi_desc* alloc_msi_entry(void) |
288 | { | |
289 | struct msi_desc *entry; | |
290 | ||
3e916c05 | 291 | entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); |
1da177e4 LT |
292 | if (!entry) |
293 | return NULL; | |
294 | ||
4aa9bc95 ME |
295 | INIT_LIST_HEAD(&entry->list); |
296 | entry->irq = 0; | |
1da177e4 LT |
297 | entry->dev = NULL; |
298 | ||
299 | return entry; | |
300 | } | |
301 | ||
ba698ad4 DM |
302 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
303 | { | |
304 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
305 | pci_intx(dev, enable); | |
306 | } | |
307 | ||
8fed4b65 | 308 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 309 | { |
392ee1e6 | 310 | int pos; |
41017f0c | 311 | u16 control; |
392ee1e6 | 312 | struct msi_desc *entry; |
41017f0c | 313 | |
b1cbf4e4 EB |
314 | if (!dev->msi_enabled) |
315 | return; | |
316 | ||
392ee1e6 EB |
317 | entry = get_irq_msi(dev->irq); |
318 | pos = entry->msi_attrib.pos; | |
41017f0c | 319 | |
ba698ad4 | 320 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 321 | msi_set_enable(dev, 0); |
392ee1e6 | 322 | write_msi_msg(dev->irq, &entry->msg); |
3145e941 YL |
323 | if (entry->msi_attrib.maskbit) { |
324 | struct irq_desc *desc = irq_to_desc(dev->irq); | |
325 | msi_set_mask_bits(desc, entry->msi_attrib.maskbits_mask, | |
8e149e09 | 326 | entry->msi_attrib.masked); |
3145e941 | 327 | } |
392ee1e6 EB |
328 | |
329 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
abad2ec9 JB |
330 | control &= ~PCI_MSI_FLAGS_QSIZE; |
331 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 332 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
333 | } |
334 | ||
335 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 336 | { |
41017f0c | 337 | int pos; |
41017f0c | 338 | struct msi_desc *entry; |
392ee1e6 | 339 | u16 control; |
41017f0c | 340 | |
ded86d8d EB |
341 | if (!dev->msix_enabled) |
342 | return; | |
343 | ||
41017f0c | 344 | /* route the table */ |
ba698ad4 | 345 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 346 | msix_set_enable(dev, 0); |
41017f0c | 347 | |
4aa9bc95 | 348 | list_for_each_entry(entry, &dev->msi_list, list) { |
3145e941 | 349 | struct irq_desc *desc = irq_to_desc(entry->irq); |
4aa9bc95 | 350 | write_msi_msg(entry->irq, &entry->msg); |
3145e941 | 351 | msi_set_mask_bits(desc, 1, entry->msi_attrib.masked); |
41017f0c | 352 | } |
41017f0c | 353 | |
314e77b3 ME |
354 | BUG_ON(list_empty(&dev->msi_list)); |
355 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 356 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
357 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
358 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
359 | control |= PCI_MSIX_FLAGS_ENABLE; | |
360 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 361 | } |
8fed4b65 ME |
362 | |
363 | void pci_restore_msi_state(struct pci_dev *dev) | |
364 | { | |
365 | __pci_restore_msi_state(dev); | |
366 | __pci_restore_msix_state(dev); | |
367 | } | |
94688cf2 | 368 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 369 | |
1da177e4 LT |
370 | /** |
371 | * msi_capability_init - configure device's MSI capability structure | |
372 | * @dev: pointer to the pci_dev data structure of MSI device function | |
373 | * | |
eaae4b3a | 374 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 375 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 376 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 377 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
378 | **/ |
379 | static int msi_capability_init(struct pci_dev *dev) | |
380 | { | |
381 | struct msi_desc *entry; | |
7fe3730d | 382 | int pos, ret; |
1da177e4 LT |
383 | u16 control; |
384 | ||
b1cbf4e4 EB |
385 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
386 | ||
1da177e4 LT |
387 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
388 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
389 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
390 | entry = alloc_msi_entry(); |
391 | if (!entry) | |
392 | return -ENOMEM; | |
1ce03373 | 393 | |
1da177e4 | 394 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 395 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
396 | entry->msi_attrib.entry_nr = 0; |
397 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 398 | entry->msi_attrib.masked = 1; |
1ce03373 | 399 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 400 | entry->msi_attrib.pos = pos; |
3b7d1921 EB |
401 | entry->dev = dev; |
402 | if (entry->msi_attrib.maskbit) { | |
0db29af1 HS |
403 | unsigned int base, maskbits, temp; |
404 | ||
405 | base = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); | |
406 | entry->mask_base = (void __iomem *)(long)base; | |
407 | ||
3b7d1921 | 408 | /* All MSIs are unmasked by default, Mask them all */ |
0db29af1 | 409 | pci_read_config_dword(dev, base, &maskbits); |
3b7d1921 EB |
410 | temp = (1 << multi_msi_capable(control)); |
411 | temp = ((temp - 1) & ~temp); | |
412 | maskbits |= temp; | |
0db29af1 | 413 | pci_write_config_dword(dev, base, maskbits); |
8e149e09 | 414 | entry->msi_attrib.maskbits_mask = temp; |
3b7d1921 | 415 | } |
0dd11f9b | 416 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 417 | |
1da177e4 | 418 | /* Configure MSI capability structure */ |
9c831334 | 419 | ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); |
7fe3730d | 420 | if (ret) { |
032de8e2 | 421 | msi_free_irqs(dev); |
7fe3730d | 422 | return ret; |
fd58e55f | 423 | } |
f7feaca7 | 424 | |
1da177e4 | 425 | /* Set MSI enabled bits */ |
ba698ad4 | 426 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
427 | msi_set_enable(dev, 1); |
428 | dev->msi_enabled = 1; | |
1da177e4 | 429 | |
7fe3730d | 430 | dev->irq = entry->irq; |
1da177e4 LT |
431 | return 0; |
432 | } | |
433 | ||
434 | /** | |
435 | * msix_capability_init - configure device's MSI-X capability | |
436 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
437 | * @entries: pointer to an array of struct msix_entry entries |
438 | * @nvec: number of @entries | |
1da177e4 | 439 | * |
eaae4b3a | 440 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
441 | * single MSI-X irq. A return of zero indicates the successful setup of |
442 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
443 | **/ |
444 | static int msix_capability_init(struct pci_dev *dev, | |
445 | struct msix_entry *entries, int nvec) | |
446 | { | |
4aa9bc95 | 447 | struct msi_desc *entry; |
9c831334 | 448 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
449 | unsigned long phys_addr; |
450 | u32 table_offset; | |
1da177e4 LT |
451 | u16 control; |
452 | u8 bir; | |
453 | void __iomem *base; | |
454 | ||
b1cbf4e4 EB |
455 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
456 | ||
1da177e4 LT |
457 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
458 | /* Request & Map MSI-X table region */ | |
459 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
460 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
461 | |
462 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 463 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
464 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
465 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
466 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
467 | if (base == NULL) | |
468 | return -ENOMEM; | |
469 | ||
470 | /* MSI-X Table Initialization */ | |
471 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
472 | entry = alloc_msi_entry(); |
473 | if (!entry) | |
1da177e4 | 474 | break; |
1da177e4 LT |
475 | |
476 | j = entries[i].entry; | |
1da177e4 | 477 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 478 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
479 | entry->msi_attrib.entry_nr = j; |
480 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 481 | entry->msi_attrib.masked = 1; |
1ce03373 | 482 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 483 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
484 | entry->dev = dev; |
485 | entry->mask_base = base; | |
f7feaca7 | 486 | |
0dd11f9b | 487 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 488 | } |
9c831334 ME |
489 | |
490 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
491 | if (ret) { | |
492 | int avail = 0; | |
493 | list_for_each_entry(entry, &dev->msi_list, list) { | |
494 | if (entry->irq != 0) { | |
495 | avail++; | |
9c831334 | 496 | } |
1da177e4 | 497 | } |
9c831334 | 498 | |
032de8e2 ME |
499 | msi_free_irqs(dev); |
500 | ||
92db6d10 EB |
501 | /* If we had some success report the number of irqs |
502 | * we succeeded in setting up. | |
503 | */ | |
9c831334 ME |
504 | if (avail == 0) |
505 | avail = ret; | |
92db6d10 | 506 | return avail; |
1da177e4 | 507 | } |
9c831334 ME |
508 | |
509 | i = 0; | |
510 | list_for_each_entry(entry, &dev->msi_list, list) { | |
511 | entries[i].vector = entry->irq; | |
512 | set_irq_msi(entry->irq, entry); | |
513 | i++; | |
514 | } | |
1da177e4 | 515 | /* Set MSI-X enabled bits */ |
ba698ad4 | 516 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
517 | msix_set_enable(dev, 1); |
518 | dev->msix_enabled = 1; | |
1da177e4 LT |
519 | |
520 | return 0; | |
521 | } | |
522 | ||
24334a12 | 523 | /** |
17bbc12a | 524 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 525 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 526 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 527 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 528 | * |
0306ebfa | 529 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
530 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
531 | * supported return 0, else return an error code. | |
24334a12 | 532 | **/ |
c9953a73 | 533 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
534 | { |
535 | struct pci_bus *bus; | |
c9953a73 | 536 | int ret; |
24334a12 | 537 | |
0306ebfa | 538 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
539 | if (!pci_msi_enable || !dev || dev->no_msi) |
540 | return -EINVAL; | |
541 | ||
314e77b3 ME |
542 | /* |
543 | * You can't ask to have 0 or less MSIs configured. | |
544 | * a) it's stupid .. | |
545 | * b) the list manipulation code assumes nvec >= 1. | |
546 | */ | |
547 | if (nvec < 1) | |
548 | return -ERANGE; | |
549 | ||
0306ebfa BG |
550 | /* Any bridge which does NOT route MSI transactions from it's |
551 | * secondary bus to it's primary bus must set NO_MSI flag on | |
552 | * the secondary pci_bus. | |
553 | * We expect only arch-specific PCI host bus controller driver | |
554 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
555 | */ | |
24334a12 BG |
556 | for (bus = dev->bus; bus; bus = bus->parent) |
557 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
558 | return -EINVAL; | |
559 | ||
c9953a73 ME |
560 | ret = arch_msi_check_device(dev, nvec, type); |
561 | if (ret) | |
562 | return ret; | |
563 | ||
b1e2303d ME |
564 | if (!pci_find_capability(dev, type)) |
565 | return -EINVAL; | |
566 | ||
24334a12 BG |
567 | return 0; |
568 | } | |
569 | ||
1da177e4 LT |
570 | /** |
571 | * pci_enable_msi - configure device's MSI capability structure | |
572 | * @dev: pointer to the pci_dev data structure of MSI device function | |
573 | * | |
574 | * Setup the MSI capability structure of device function with | |
1ce03373 | 575 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
576 | * MSI mode enabled on its hardware device function. A return of zero |
577 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 578 | * irq or non-zero for otherwise. |
1da177e4 LT |
579 | **/ |
580 | int pci_enable_msi(struct pci_dev* dev) | |
581 | { | |
b1e2303d | 582 | int status; |
1da177e4 | 583 | |
c9953a73 ME |
584 | status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); |
585 | if (status) | |
586 | return status; | |
1da177e4 | 587 | |
ded86d8d | 588 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 589 | |
1ce03373 | 590 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 | 591 | if (dev->msix_enabled) { |
80ccba11 BH |
592 | dev_info(&dev->dev, "can't enable MSI " |
593 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 594 | return -EINVAL; |
1da177e4 LT |
595 | } |
596 | status = msi_capability_init(dev); | |
1da177e4 LT |
597 | return status; |
598 | } | |
4cc086fa | 599 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 | 600 | |
d52877c7 | 601 | void pci_msi_shutdown(struct pci_dev* dev) |
1da177e4 LT |
602 | { |
603 | struct msi_desc *entry; | |
1da177e4 | 604 | |
128bc5fc | 605 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
606 | return; |
607 | ||
b1cbf4e4 | 608 | msi_set_enable(dev, 0); |
ba698ad4 | 609 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 610 | dev->msi_enabled = 0; |
7bd007e4 | 611 | |
314e77b3 ME |
612 | BUG_ON(list_empty(&dev->msi_list)); |
613 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
8e149e09 YL |
614 | /* Return the the pci reset with msi irqs unmasked */ |
615 | if (entry->msi_attrib.maskbit) { | |
616 | u32 mask = entry->msi_attrib.maskbits_mask; | |
3145e941 YL |
617 | struct irq_desc *desc = irq_to_desc(dev->irq); |
618 | msi_set_mask_bits(desc, mask, ~mask); | |
8e149e09 | 619 | } |
d52877c7 | 620 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) |
1da177e4 | 621 | return; |
e387b9ee ME |
622 | |
623 | /* Restore dev->irq to its default pin-assertion irq */ | |
d52877c7 YL |
624 | dev->irq = entry->msi_attrib.default_irq; |
625 | } | |
626 | void pci_disable_msi(struct pci_dev* dev) | |
627 | { | |
628 | struct msi_desc *entry; | |
629 | ||
630 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
631 | return; | |
632 | ||
633 | pci_msi_shutdown(dev); | |
634 | ||
635 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
636 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) | |
637 | return; | |
638 | ||
639 | msi_free_irqs(dev); | |
1da177e4 | 640 | } |
4cc086fa | 641 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 642 | |
032de8e2 | 643 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 644 | { |
032de8e2 | 645 | struct msi_desc *entry, *tmp; |
7ede9c1f | 646 | |
b3b7cc7b DM |
647 | list_for_each_entry(entry, &dev->msi_list, list) { |
648 | if (entry->irq) | |
649 | BUG_ON(irq_has_action(entry->irq)); | |
650 | } | |
1da177e4 | 651 | |
032de8e2 | 652 | arch_teardown_msi_irqs(dev); |
1da177e4 | 653 | |
032de8e2 ME |
654 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
655 | if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) { | |
032de8e2 ME |
656 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
657 | * PCI_MSIX_ENTRY_SIZE | |
658 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
659 | |
660 | if (list_is_last(&entry->list, &dev->msi_list)) | |
661 | iounmap(entry->mask_base); | |
032de8e2 ME |
662 | } |
663 | list_del(&entry->list); | |
664 | kfree(entry); | |
1da177e4 LT |
665 | } |
666 | ||
667 | return 0; | |
668 | } | |
669 | ||
1da177e4 LT |
670 | /** |
671 | * pci_enable_msix - configure device's MSI-X capability structure | |
672 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 673 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 674 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
675 | * |
676 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 677 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
678 | * MSI-X mode enabled on its hardware device function. A return of zero |
679 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 680 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 681 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 682 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
683 | * its request. |
684 | **/ | |
685 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
686 | { | |
92db6d10 | 687 | int status, pos, nr_entries; |
ded86d8d | 688 | int i, j; |
1da177e4 | 689 | u16 control; |
1da177e4 | 690 | |
c9953a73 | 691 | if (!entries) |
1da177e4 LT |
692 | return -EINVAL; |
693 | ||
c9953a73 ME |
694 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
695 | if (status) | |
696 | return status; | |
697 | ||
b64c05e7 | 698 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1da177e4 | 699 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
1da177e4 LT |
700 | nr_entries = multi_msix_capable(control); |
701 | if (nvec > nr_entries) | |
702 | return -EINVAL; | |
703 | ||
704 | /* Check for any invalid entries */ | |
705 | for (i = 0; i < nvec; i++) { | |
706 | if (entries[i].entry >= nr_entries) | |
707 | return -EINVAL; /* invalid entry */ | |
708 | for (j = i + 1; j < nvec; j++) { | |
709 | if (entries[i].entry == entries[j].entry) | |
710 | return -EINVAL; /* duplicate entry */ | |
711 | } | |
712 | } | |
ded86d8d | 713 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 714 | |
1ce03373 | 715 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 716 | if (dev->msi_enabled) { |
80ccba11 BH |
717 | dev_info(&dev->dev, "can't enable MSI-X " |
718 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
719 | return -EINVAL; |
720 | } | |
1da177e4 | 721 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
722 | return status; |
723 | } | |
4cc086fa | 724 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 725 | |
fc4afc7b | 726 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 727 | { |
032de8e2 | 728 | msi_free_irqs(dev); |
fc4afc7b ME |
729 | } |
730 | ||
d52877c7 | 731 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 732 | { |
128bc5fc | 733 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
734 | return; |
735 | ||
b1cbf4e4 | 736 | msix_set_enable(dev, 0); |
ba698ad4 | 737 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 738 | dev->msix_enabled = 0; |
d52877c7 YL |
739 | } |
740 | void pci_disable_msix(struct pci_dev* dev) | |
741 | { | |
742 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
743 | return; | |
744 | ||
745 | pci_msix_shutdown(dev); | |
7bd007e4 | 746 | |
fc4afc7b | 747 | msix_free_all_irqs(dev); |
1da177e4 | 748 | } |
4cc086fa | 749 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
750 | |
751 | /** | |
1ce03373 | 752 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
753 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
754 | * | |
eaae4b3a | 755 | * Being called during hotplug remove, from which the device function |
1ce03373 | 756 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
757 | * allocated for this device function, are reclaimed to unused state, |
758 | * which may be used later on. | |
759 | **/ | |
760 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
761 | { | |
1da177e4 LT |
762 | if (!pci_msi_enable || !dev) |
763 | return; | |
764 | ||
032de8e2 ME |
765 | if (dev->msi_enabled) |
766 | msi_free_irqs(dev); | |
1da177e4 | 767 | |
fc4afc7b ME |
768 | if (dev->msix_enabled) |
769 | msix_free_all_irqs(dev); | |
1da177e4 LT |
770 | } |
771 | ||
309e57df MW |
772 | void pci_no_msi(void) |
773 | { | |
774 | pci_msi_enable = 0; | |
775 | } | |
c9953a73 | 776 | |
07ae95f9 AP |
777 | /** |
778 | * pci_msi_enabled - is MSI enabled? | |
779 | * | |
780 | * Returns true if MSI has not been disabled by the command-line option | |
781 | * pci=nomsi. | |
782 | **/ | |
783 | int pci_msi_enabled(void) | |
d389fec6 | 784 | { |
07ae95f9 | 785 | return pci_msi_enable; |
d389fec6 | 786 | } |
07ae95f9 | 787 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 788 | |
07ae95f9 | 789 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 790 | { |
07ae95f9 | 791 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 792 | } |