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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
e18b890b | 27 | static struct kmem_cache* msi_cachep; |
1da177e4 LT |
28 | |
29 | static int pci_msi_enable = 1; | |
1da177e4 | 30 | |
1da177e4 LT |
31 | static int msi_cache_init(void) |
32 | { | |
57181784 PE |
33 | msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), |
34 | 0, SLAB_HWCACHE_ALIGN, NULL, NULL); | |
1da177e4 LT |
35 | if (!msi_cachep) |
36 | return -ENOMEM; | |
37 | ||
38 | return 0; | |
39 | } | |
40 | ||
b1cbf4e4 EB |
41 | static void msi_set_enable(struct pci_dev *dev, int enable) |
42 | { | |
43 | int pos; | |
44 | u16 control; | |
45 | ||
46 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
47 | if (pos) { | |
48 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
49 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
50 | if (enable) | |
51 | control |= PCI_MSI_FLAGS_ENABLE; | |
52 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
53 | } | |
54 | } | |
55 | ||
56 | static void msix_set_enable(struct pci_dev *dev, int enable) | |
57 | { | |
58 | int pos; | |
59 | u16 control; | |
60 | ||
61 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
62 | if (pos) { | |
63 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
64 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
65 | if (enable) | |
66 | control |= PCI_MSIX_FLAGS_ENABLE; | |
67 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
68 | } | |
69 | } | |
70 | ||
1ce03373 | 71 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
72 | { |
73 | struct msi_desc *entry; | |
74 | ||
5b912c10 | 75 | entry = get_irq_msi(irq); |
277bc33b | 76 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
77 | switch (entry->msi_attrib.type) { |
78 | case PCI_CAP_ID_MSI: | |
277bc33b | 79 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
80 | int pos; |
81 | u32 mask_bits; | |
277bc33b EB |
82 | |
83 | pos = (long)entry->mask_base; | |
84 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
85 | mask_bits &= ~(1); | |
86 | mask_bits |= flag; | |
87 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
58e0543e EB |
88 | } else { |
89 | msi_set_enable(entry->dev, !flag); | |
277bc33b | 90 | } |
1da177e4 | 91 | break; |
1da177e4 LT |
92 | case PCI_CAP_ID_MSIX: |
93 | { | |
94 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
95 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
96 | writel(flag, entry->mask_base + offset); | |
97 | break; | |
98 | } | |
99 | default: | |
277bc33b | 100 | BUG(); |
1da177e4 LT |
101 | break; |
102 | } | |
392ee1e6 | 103 | entry->msi_attrib.masked = !!flag; |
1da177e4 LT |
104 | } |
105 | ||
3b7d1921 | 106 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 107 | { |
5b912c10 | 108 | struct msi_desc *entry = get_irq_msi(irq); |
0366f8f7 EB |
109 | switch(entry->msi_attrib.type) { |
110 | case PCI_CAP_ID_MSI: | |
111 | { | |
112 | struct pci_dev *dev = entry->dev; | |
113 | int pos = entry->msi_attrib.pos; | |
114 | u16 data; | |
115 | ||
116 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
117 | &msg->address_lo); | |
118 | if (entry->msi_attrib.is_64) { | |
119 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
120 | &msg->address_hi); | |
121 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
122 | } else { | |
123 | msg->address_hi = 0; | |
124 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
125 | } | |
126 | msg->data = data; | |
127 | break; | |
128 | } | |
129 | case PCI_CAP_ID_MSIX: | |
130 | { | |
131 | void __iomem *base; | |
132 | base = entry->mask_base + | |
133 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
134 | ||
135 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
136 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
137 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
138 | break; | |
139 | } | |
140 | default: | |
141 | BUG(); | |
142 | } | |
143 | } | |
1da177e4 | 144 | |
3b7d1921 | 145 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 146 | { |
5b912c10 | 147 | struct msi_desc *entry = get_irq_msi(irq); |
1da177e4 LT |
148 | switch (entry->msi_attrib.type) { |
149 | case PCI_CAP_ID_MSI: | |
150 | { | |
0366f8f7 EB |
151 | struct pci_dev *dev = entry->dev; |
152 | int pos = entry->msi_attrib.pos; | |
153 | ||
154 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
155 | msg->address_lo); | |
156 | if (entry->msi_attrib.is_64) { | |
157 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
158 | msg->address_hi); | |
159 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
160 | msg->data); | |
161 | } else { | |
162 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
163 | msg->data); | |
164 | } | |
1da177e4 LT |
165 | break; |
166 | } | |
167 | case PCI_CAP_ID_MSIX: | |
168 | { | |
0366f8f7 EB |
169 | void __iomem *base; |
170 | base = entry->mask_base + | |
171 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
172 | ||
173 | writel(msg->address_lo, | |
174 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
175 | writel(msg->address_hi, | |
176 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
177 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
178 | break; |
179 | } | |
180 | default: | |
0366f8f7 | 181 | BUG(); |
1da177e4 | 182 | } |
392ee1e6 | 183 | entry->msg = *msg; |
1da177e4 | 184 | } |
0366f8f7 | 185 | |
3b7d1921 | 186 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 187 | { |
1ce03373 | 188 | msi_set_mask_bit(irq, 1); |
1da177e4 LT |
189 | } |
190 | ||
3b7d1921 | 191 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 192 | { |
1ce03373 | 193 | msi_set_mask_bit(irq, 0); |
1da177e4 LT |
194 | } |
195 | ||
1ce03373 | 196 | static int msi_free_irq(struct pci_dev* dev, int irq); |
c54c1879 | 197 | |
1da177e4 LT |
198 | static int msi_init(void) |
199 | { | |
200 | static int status = -ENOMEM; | |
201 | ||
202 | if (!status) | |
203 | return status; | |
204 | ||
b64c05e7 GG |
205 | status = msi_cache_init(); |
206 | if (status < 0) { | |
1da177e4 LT |
207 | pci_msi_enable = 0; |
208 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
209 | return status; | |
210 | } | |
fd58e55f | 211 | |
1da177e4 LT |
212 | return status; |
213 | } | |
214 | ||
1da177e4 LT |
215 | static struct msi_desc* alloc_msi_entry(void) |
216 | { | |
217 | struct msi_desc *entry; | |
218 | ||
57181784 | 219 | entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); |
1da177e4 LT |
220 | if (!entry) |
221 | return NULL; | |
222 | ||
1da177e4 LT |
223 | entry->link.tail = entry->link.head = 0; /* single message */ |
224 | entry->dev = NULL; | |
225 | ||
226 | return entry; | |
227 | } | |
228 | ||
41017f0c | 229 | #ifdef CONFIG_PM |
8fed4b65 | 230 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 231 | { |
392ee1e6 | 232 | int pos; |
41017f0c | 233 | u16 control; |
392ee1e6 | 234 | struct msi_desc *entry; |
41017f0c | 235 | |
b1cbf4e4 EB |
236 | if (!dev->msi_enabled) |
237 | return; | |
238 | ||
392ee1e6 EB |
239 | entry = get_irq_msi(dev->irq); |
240 | pos = entry->msi_attrib.pos; | |
41017f0c | 241 | |
b1cbf4e4 | 242 | pci_intx(dev, 0); /* disable intx */ |
b1cbf4e4 | 243 | msi_set_enable(dev, 0); |
392ee1e6 EB |
244 | write_msi_msg(dev->irq, &entry->msg); |
245 | if (entry->msi_attrib.maskbit) | |
246 | msi_set_mask_bit(dev->irq, entry->msi_attrib.masked); | |
247 | ||
248 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
249 | control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); | |
250 | if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked) | |
251 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 252 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
253 | } |
254 | ||
255 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 256 | { |
41017f0c | 257 | int pos; |
1ce03373 | 258 | int irq, head, tail = 0; |
41017f0c | 259 | struct msi_desc *entry; |
392ee1e6 | 260 | u16 control; |
41017f0c | 261 | |
ded86d8d EB |
262 | if (!dev->msix_enabled) |
263 | return; | |
264 | ||
41017f0c | 265 | /* route the table */ |
b1cbf4e4 EB |
266 | pci_intx(dev, 0); /* disable intx */ |
267 | msix_set_enable(dev, 0); | |
ded86d8d | 268 | irq = head = dev->first_msi_irq; |
392ee1e6 EB |
269 | entry = get_irq_msi(irq); |
270 | pos = entry->msi_attrib.pos; | |
41017f0c | 271 | while (head != tail) { |
5b912c10 | 272 | entry = get_irq_msi(irq); |
392ee1e6 EB |
273 | write_msi_msg(irq, &entry->msg); |
274 | msi_set_mask_bit(irq, entry->msi_attrib.masked); | |
41017f0c | 275 | |
5b912c10 | 276 | tail = entry->link.tail; |
1ce03373 | 277 | irq = tail; |
41017f0c | 278 | } |
41017f0c | 279 | |
392ee1e6 EB |
280 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
281 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
282 | control |= PCI_MSIX_FLAGS_ENABLE; | |
283 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 284 | } |
8fed4b65 ME |
285 | |
286 | void pci_restore_msi_state(struct pci_dev *dev) | |
287 | { | |
288 | __pci_restore_msi_state(dev); | |
289 | __pci_restore_msix_state(dev); | |
290 | } | |
c54c1879 | 291 | #endif /* CONFIG_PM */ |
41017f0c | 292 | |
1da177e4 LT |
293 | /** |
294 | * msi_capability_init - configure device's MSI capability structure | |
295 | * @dev: pointer to the pci_dev data structure of MSI device function | |
296 | * | |
eaae4b3a | 297 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 298 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 299 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 300 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
301 | **/ |
302 | static int msi_capability_init(struct pci_dev *dev) | |
303 | { | |
304 | struct msi_desc *entry; | |
1ce03373 | 305 | int pos, irq; |
1da177e4 LT |
306 | u16 control; |
307 | ||
b1cbf4e4 EB |
308 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
309 | ||
1da177e4 LT |
310 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
311 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
312 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
313 | entry = alloc_msi_entry(); |
314 | if (!entry) | |
315 | return -ENOMEM; | |
1ce03373 | 316 | |
1da177e4 | 317 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 318 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
319 | entry->msi_attrib.entry_nr = 0; |
320 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 321 | entry->msi_attrib.masked = 1; |
1ce03373 | 322 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 323 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
324 | if (is_mask_bit_support(control)) { |
325 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
326 | is_64bit_address(control)); | |
327 | } | |
3b7d1921 EB |
328 | entry->dev = dev; |
329 | if (entry->msi_attrib.maskbit) { | |
330 | unsigned int maskbits, temp; | |
331 | /* All MSIs are unmasked by default, Mask them all */ | |
332 | pci_read_config_dword(dev, | |
333 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
334 | &maskbits); | |
335 | temp = (1 << multi_msi_capable(control)); | |
336 | temp = ((temp - 1) & ~temp); | |
337 | maskbits |= temp; | |
338 | pci_write_config_dword(dev, | |
339 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
340 | maskbits); | |
341 | } | |
1da177e4 | 342 | /* Configure MSI capability structure */ |
f7feaca7 EB |
343 | irq = arch_setup_msi_irq(dev, entry); |
344 | if (irq < 0) { | |
345 | kmem_cache_free(msi_cachep, entry); | |
346 | return irq; | |
fd58e55f | 347 | } |
f7feaca7 EB |
348 | entry->link.head = irq; |
349 | entry->link.tail = irq; | |
ded86d8d | 350 | dev->first_msi_irq = irq; |
5b912c10 | 351 | set_irq_msi(irq, entry); |
f7feaca7 | 352 | |
1da177e4 | 353 | /* Set MSI enabled bits */ |
b1cbf4e4 EB |
354 | pci_intx(dev, 0); /* disable intx */ |
355 | msi_set_enable(dev, 1); | |
356 | dev->msi_enabled = 1; | |
1da177e4 | 357 | |
3b7d1921 | 358 | dev->irq = irq; |
1da177e4 LT |
359 | return 0; |
360 | } | |
361 | ||
362 | /** | |
363 | * msix_capability_init - configure device's MSI-X capability | |
364 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
365 | * @entries: pointer to an array of struct msix_entry entries |
366 | * @nvec: number of @entries | |
1da177e4 | 367 | * |
eaae4b3a | 368 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
369 | * single MSI-X irq. A return of zero indicates the successful setup of |
370 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
371 | **/ |
372 | static int msix_capability_init(struct pci_dev *dev, | |
373 | struct msix_entry *entries, int nvec) | |
374 | { | |
375 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
1ce03373 | 376 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
377 | unsigned long phys_addr; |
378 | u32 table_offset; | |
1da177e4 LT |
379 | u16 control; |
380 | u8 bir; | |
381 | void __iomem *base; | |
382 | ||
b1cbf4e4 EB |
383 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
384 | ||
1da177e4 LT |
385 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
386 | /* Request & Map MSI-X table region */ | |
387 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
388 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
389 | |
390 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 391 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
392 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
393 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
394 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
395 | if (base == NULL) | |
396 | return -ENOMEM; | |
397 | ||
398 | /* MSI-X Table Initialization */ | |
399 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
400 | entry = alloc_msi_entry(); |
401 | if (!entry) | |
1da177e4 | 402 | break; |
1da177e4 LT |
403 | |
404 | j = entries[i].entry; | |
1da177e4 | 405 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 406 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
407 | entry->msi_attrib.entry_nr = j; |
408 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 409 | entry->msi_attrib.masked = 1; |
1ce03373 | 410 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 411 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
412 | entry->dev = dev; |
413 | entry->mask_base = base; | |
f7feaca7 EB |
414 | |
415 | /* Configure MSI-X capability structure */ | |
416 | irq = arch_setup_msi_irq(dev, entry); | |
417 | if (irq < 0) { | |
418 | kmem_cache_free(msi_cachep, entry); | |
419 | break; | |
420 | } | |
421 | entries[i].vector = irq; | |
1da177e4 | 422 | if (!head) { |
1ce03373 EB |
423 | entry->link.head = irq; |
424 | entry->link.tail = irq; | |
1da177e4 LT |
425 | head = entry; |
426 | } else { | |
427 | entry->link.head = temp; | |
428 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
429 | tail->link.tail = irq; |
430 | head->link.head = irq; | |
1da177e4 | 431 | } |
1ce03373 | 432 | temp = irq; |
1da177e4 | 433 | tail = entry; |
fd58e55f | 434 | |
5b912c10 | 435 | set_irq_msi(irq, entry); |
1da177e4 LT |
436 | } |
437 | if (i != nvec) { | |
92db6d10 | 438 | int avail = i - 1; |
1da177e4 LT |
439 | i--; |
440 | for (; i >= 0; i--) { | |
1ce03373 EB |
441 | irq = (entries + i)->vector; |
442 | msi_free_irq(dev, irq); | |
1da177e4 LT |
443 | (entries + i)->vector = 0; |
444 | } | |
92db6d10 EB |
445 | /* If we had some success report the number of irqs |
446 | * we succeeded in setting up. | |
447 | */ | |
448 | if (avail <= 0) | |
449 | avail = -EBUSY; | |
450 | return avail; | |
1da177e4 | 451 | } |
ded86d8d | 452 | dev->first_msi_irq = entries[0].vector; |
1da177e4 | 453 | /* Set MSI-X enabled bits */ |
b1cbf4e4 EB |
454 | pci_intx(dev, 0); /* disable intx */ |
455 | msix_set_enable(dev, 1); | |
456 | dev->msix_enabled = 1; | |
1da177e4 LT |
457 | |
458 | return 0; | |
459 | } | |
460 | ||
24334a12 BG |
461 | /** |
462 | * pci_msi_supported - check whether MSI may be enabled on device | |
463 | * @dev: pointer to the pci_dev data structure of MSI device function | |
464 | * | |
0306ebfa BG |
465 | * Look at global flags, the device itself, and its parent busses |
466 | * to return 0 if MSI are supported for the device. | |
24334a12 BG |
467 | **/ |
468 | static | |
469 | int pci_msi_supported(struct pci_dev * dev) | |
470 | { | |
471 | struct pci_bus *bus; | |
472 | ||
0306ebfa | 473 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
474 | if (!pci_msi_enable || !dev || dev->no_msi) |
475 | return -EINVAL; | |
476 | ||
0306ebfa BG |
477 | /* Any bridge which does NOT route MSI transactions from it's |
478 | * secondary bus to it's primary bus must set NO_MSI flag on | |
479 | * the secondary pci_bus. | |
480 | * We expect only arch-specific PCI host bus controller driver | |
481 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
482 | */ | |
24334a12 BG |
483 | for (bus = dev->bus; bus; bus = bus->parent) |
484 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
485 | return -EINVAL; | |
486 | ||
487 | return 0; | |
488 | } | |
489 | ||
1da177e4 LT |
490 | /** |
491 | * pci_enable_msi - configure device's MSI capability structure | |
492 | * @dev: pointer to the pci_dev data structure of MSI device function | |
493 | * | |
494 | * Setup the MSI capability structure of device function with | |
1ce03373 | 495 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
496 | * MSI mode enabled on its hardware device function. A return of zero |
497 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 498 | * irq or non-zero for otherwise. |
1da177e4 LT |
499 | **/ |
500 | int pci_enable_msi(struct pci_dev* dev) | |
501 | { | |
ded86d8d | 502 | int pos, status; |
1da177e4 | 503 | |
24334a12 BG |
504 | if (pci_msi_supported(dev) < 0) |
505 | return -EINVAL; | |
6e325a62 | 506 | |
b64c05e7 GG |
507 | status = msi_init(); |
508 | if (status < 0) | |
1da177e4 LT |
509 | return status; |
510 | ||
b64c05e7 GG |
511 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
512 | if (!pos) | |
1da177e4 LT |
513 | return -EINVAL; |
514 | ||
ded86d8d | 515 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 516 | |
1ce03373 | 517 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 EB |
518 | if (dev->msix_enabled) { |
519 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " | |
520 | "Device already has MSI-X enabled\n", | |
521 | pci_name(dev)); | |
522 | return -EINVAL; | |
1da177e4 LT |
523 | } |
524 | status = msi_capability_init(dev); | |
1da177e4 LT |
525 | return status; |
526 | } | |
527 | ||
528 | void pci_disable_msi(struct pci_dev* dev) | |
529 | { | |
530 | struct msi_desc *entry; | |
b1cbf4e4 | 531 | int default_irq; |
1da177e4 | 532 | |
309e57df MW |
533 | if (!pci_msi_enable) |
534 | return; | |
b64c05e7 GG |
535 | if (!dev) |
536 | return; | |
309e57df | 537 | |
ded86d8d EB |
538 | if (!dev->msi_enabled) |
539 | return; | |
540 | ||
b1cbf4e4 EB |
541 | msi_set_enable(dev, 0); |
542 | pci_intx(dev, 1); /* enable intx */ | |
543 | dev->msi_enabled = 0; | |
7bd007e4 | 544 | |
5b912c10 | 545 | entry = get_irq_msi(dev->first_msi_irq); |
1da177e4 | 546 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { |
1da177e4 LT |
547 | return; |
548 | } | |
ded86d8d | 549 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 550 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " |
1ce03373 | 551 | "free_irq() on MSI irq %d\n", |
ded86d8d EB |
552 | pci_name(dev), dev->first_msi_irq); |
553 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1da177e4 | 554 | } else { |
1ce03373 | 555 | default_irq = entry->msi_attrib.default_irq; |
ded86d8d | 556 | msi_free_irq(dev, dev->first_msi_irq); |
7bd007e4 | 557 | |
1ce03373 EB |
558 | /* Restore dev->irq to its default pin-assertion irq */ |
559 | dev->irq = default_irq; | |
1da177e4 | 560 | } |
ded86d8d | 561 | dev->first_msi_irq = 0; |
1da177e4 LT |
562 | } |
563 | ||
1ce03373 | 564 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
565 | { |
566 | struct msi_desc *entry; | |
567 | int head, entry_nr, type; | |
568 | void __iomem *base; | |
1da177e4 | 569 | |
5b912c10 | 570 | entry = get_irq_msi(irq); |
1da177e4 | 571 | if (!entry || entry->dev != dev) { |
1da177e4 LT |
572 | return -EINVAL; |
573 | } | |
574 | type = entry->msi_attrib.type; | |
575 | entry_nr = entry->msi_attrib.entry_nr; | |
576 | head = entry->link.head; | |
577 | base = entry->mask_base; | |
5b912c10 EB |
578 | get_irq_msi(entry->link.head)->link.tail = entry->link.tail; |
579 | get_irq_msi(entry->link.tail)->link.head = entry->link.head; | |
1da177e4 | 580 | |
f7feaca7 EB |
581 | arch_teardown_msi_irq(irq); |
582 | kmem_cache_free(msi_cachep, entry); | |
1da177e4 LT |
583 | |
584 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
585 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
586 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 587 | |
1ce03373 | 588 | if (head == irq) |
1da177e4 | 589 | iounmap(base); |
1da177e4 LT |
590 | } |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
1da177e4 LT |
595 | /** |
596 | * pci_enable_msix - configure device's MSI-X capability structure | |
597 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 598 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 599 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
600 | * |
601 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 602 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
603 | * MSI-X mode enabled on its hardware device function. A return of zero |
604 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 605 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 606 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 607 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
608 | * its request. |
609 | **/ | |
610 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
611 | { | |
92db6d10 | 612 | int status, pos, nr_entries; |
ded86d8d | 613 | int i, j; |
1da177e4 | 614 | u16 control; |
1da177e4 | 615 | |
24334a12 | 616 | if (!entries || pci_msi_supported(dev) < 0) |
1da177e4 LT |
617 | return -EINVAL; |
618 | ||
b64c05e7 GG |
619 | status = msi_init(); |
620 | if (status < 0) | |
1da177e4 LT |
621 | return status; |
622 | ||
b64c05e7 GG |
623 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
624 | if (!pos) | |
1da177e4 LT |
625 | return -EINVAL; |
626 | ||
627 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1da177e4 LT |
628 | nr_entries = multi_msix_capable(control); |
629 | if (nvec > nr_entries) | |
630 | return -EINVAL; | |
631 | ||
632 | /* Check for any invalid entries */ | |
633 | for (i = 0; i < nvec; i++) { | |
634 | if (entries[i].entry >= nr_entries) | |
635 | return -EINVAL; /* invalid entry */ | |
636 | for (j = i + 1; j < nvec; j++) { | |
637 | if (entries[i].entry == entries[j].entry) | |
638 | return -EINVAL; /* duplicate entry */ | |
639 | } | |
640 | } | |
ded86d8d | 641 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 642 | |
1ce03373 | 643 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 644 | if (dev->msi_enabled) { |
1da177e4 | 645 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 646 | "Device already has an MSI irq assigned\n", |
1da177e4 | 647 | pci_name(dev)); |
1da177e4 LT |
648 | return -EINVAL; |
649 | } | |
1da177e4 | 650 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
651 | return status; |
652 | } | |
653 | ||
654 | void pci_disable_msix(struct pci_dev* dev) | |
655 | { | |
ded86d8d | 656 | int irq, head, tail = 0, warning = 0; |
1da177e4 | 657 | |
309e57df MW |
658 | if (!pci_msi_enable) |
659 | return; | |
b64c05e7 GG |
660 | if (!dev) |
661 | return; | |
662 | ||
ded86d8d EB |
663 | if (!dev->msix_enabled) |
664 | return; | |
665 | ||
b1cbf4e4 EB |
666 | msix_set_enable(dev, 0); |
667 | pci_intx(dev, 1); /* enable intx */ | |
668 | dev->msix_enabled = 0; | |
7bd007e4 | 669 | |
ded86d8d EB |
670 | irq = head = dev->first_msi_irq; |
671 | while (head != tail) { | |
5b912c10 | 672 | tail = get_irq_msi(irq)->link.tail; |
ded86d8d EB |
673 | if (irq_has_action(irq)) |
674 | warning = 1; | |
675 | else if (irq != head) /* Release MSI-X irq */ | |
676 | msi_free_irq(dev, irq); | |
677 | irq = tail; | |
678 | } | |
679 | msi_free_irq(dev, irq); | |
680 | if (warning) { | |
681 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " | |
682 | "free_irq() on all MSI-X irqs\n", | |
683 | pci_name(dev)); | |
684 | BUG_ON(warning > 0); | |
1da177e4 | 685 | } |
ded86d8d | 686 | dev->first_msi_irq = 0; |
1da177e4 LT |
687 | } |
688 | ||
689 | /** | |
1ce03373 | 690 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
691 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
692 | * | |
eaae4b3a | 693 | * Being called during hotplug remove, from which the device function |
1ce03373 | 694 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
695 | * allocated for this device function, are reclaimed to unused state, |
696 | * which may be used later on. | |
697 | **/ | |
698 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
699 | { | |
1da177e4 LT |
700 | if (!pci_msi_enable || !dev) |
701 | return; | |
702 | ||
866a8c87 | 703 | if (dev->msi_enabled) { |
ded86d8d | 704 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 705 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " |
1ce03373 | 706 | "called without free_irq() on MSI irq %d\n", |
ded86d8d EB |
707 | pci_name(dev), dev->first_msi_irq); |
708 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1ce03373 | 709 | } else /* Release MSI irq assigned to this device */ |
ded86d8d | 710 | msi_free_irq(dev, dev->first_msi_irq); |
1da177e4 | 711 | } |
866a8c87 | 712 | if (dev->msix_enabled) { |
1ce03373 | 713 | int irq, head, tail = 0, warning = 0; |
1da177e4 LT |
714 | void __iomem *base = NULL; |
715 | ||
ded86d8d | 716 | irq = head = dev->first_msi_irq; |
1da177e4 | 717 | while (head != tail) { |
5b912c10 EB |
718 | tail = get_irq_msi(irq)->link.tail; |
719 | base = get_irq_msi(irq)->mask_base; | |
1f80025e | 720 | if (irq_has_action(irq)) |
1da177e4 | 721 | warning = 1; |
1ce03373 EB |
722 | else if (irq != head) /* Release MSI-X irq */ |
723 | msi_free_irq(dev, irq); | |
724 | irq = tail; | |
1da177e4 | 725 | } |
1ce03373 | 726 | msi_free_irq(dev, irq); |
1da177e4 | 727 | if (warning) { |
1da177e4 LT |
728 | iounmap(base); |
729 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1ce03373 | 730 | "called without free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
731 | pci_name(dev)); |
732 | BUG_ON(warning > 0); | |
733 | } | |
1da177e4 LT |
734 | } |
735 | } | |
736 | ||
309e57df MW |
737 | void pci_no_msi(void) |
738 | { | |
739 | pci_msi_enable = 0; | |
740 | } | |
741 | ||
1da177e4 LT |
742 | EXPORT_SYMBOL(pci_enable_msi); |
743 | EXPORT_SYMBOL(pci_disable_msi); | |
744 | EXPORT_SYMBOL(pci_enable_msix); | |
745 | EXPORT_SYMBOL(pci_disable_msix); |