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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
1da177e4 | 24 | |
1da177e4 | 25 | static int pci_msi_enable = 1; |
1da177e4 | 26 | |
527eee29 BH |
27 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
28 | ||
29 | ||
6a9e7f20 AB |
30 | /* Arch hooks */ |
31 | ||
4287d824 TP |
32 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
33 | { | |
0cbdcfcf TR |
34 | struct msi_chip *chip = dev->bus->msi; |
35 | int err; | |
36 | ||
37 | if (!chip || !chip->setup_irq) | |
38 | return -EINVAL; | |
39 | ||
40 | err = chip->setup_irq(chip, dev, desc); | |
41 | if (err < 0) | |
42 | return err; | |
43 | ||
44 | irq_set_chip_data(desc->irq, chip); | |
45 | ||
46 | return 0; | |
4287d824 TP |
47 | } |
48 | ||
49 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 50 | { |
0cbdcfcf TR |
51 | struct msi_chip *chip = irq_get_chip_data(irq); |
52 | ||
53 | if (!chip || !chip->teardown_irq) | |
54 | return; | |
55 | ||
56 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
57 | } |
58 | ||
4287d824 TP |
59 | int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type) |
60 | { | |
0cbdcfcf TR |
61 | struct msi_chip *chip = dev->bus->msi; |
62 | ||
63 | if (!chip || !chip->check_device) | |
64 | return 0; | |
65 | ||
66 | return chip->check_device(chip, dev, nvec, type); | |
4287d824 | 67 | } |
1525bf0d | 68 | |
4287d824 | 69 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
70 | { |
71 | struct msi_desc *entry; | |
72 | int ret; | |
73 | ||
1c8d7b0a MW |
74 | /* |
75 | * If an architecture wants to support multiple MSI, it needs to | |
76 | * override arch_setup_msi_irqs() | |
77 | */ | |
78 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
79 | return 1; | |
80 | ||
6a9e7f20 AB |
81 | list_for_each_entry(entry, &dev->msi_list, list) { |
82 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 83 | if (ret < 0) |
6a9e7f20 | 84 | return ret; |
b5fbf533 ME |
85 | if (ret > 0) |
86 | return -ENOSPC; | |
6a9e7f20 AB |
87 | } |
88 | ||
89 | return 0; | |
90 | } | |
1525bf0d | 91 | |
4287d824 TP |
92 | /* |
93 | * We have a default implementation available as a separate non-weak | |
94 | * function, as it is used by the Xen x86 PCI code | |
95 | */ | |
1525bf0d | 96 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 AB |
97 | { |
98 | struct msi_desc *entry; | |
99 | ||
100 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
101 | int i, nvec; |
102 | if (entry->irq == 0) | |
103 | continue; | |
65f6ae66 AG |
104 | if (entry->nvec_used) |
105 | nvec = entry->nvec_used; | |
106 | else | |
107 | nvec = 1 << entry->msi_attrib.multiple; | |
1c8d7b0a MW |
108 | for (i = 0; i < nvec; i++) |
109 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
110 | } |
111 | } | |
112 | ||
4287d824 TP |
113 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
114 | { | |
115 | return default_teardown_msi_irqs(dev); | |
116 | } | |
76ccc297 | 117 | |
ac8344c4 | 118 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
119 | { |
120 | struct msi_desc *entry; | |
121 | ||
122 | entry = NULL; | |
123 | if (dev->msix_enabled) { | |
124 | list_for_each_entry(entry, &dev->msi_list, list) { | |
125 | if (irq == entry->irq) | |
126 | break; | |
127 | } | |
128 | } else if (dev->msi_enabled) { | |
129 | entry = irq_get_msi_desc(irq); | |
130 | } | |
131 | ||
132 | if (entry) | |
133 | write_msi_msg(irq, &entry->msg); | |
134 | } | |
4287d824 | 135 | |
ac8344c4 | 136 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 137 | { |
ac8344c4 | 138 | return default_restore_msi_irqs(dev); |
4287d824 | 139 | } |
76ccc297 | 140 | |
e375b561 | 141 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 142 | { |
b1cbf4e4 EB |
143 | u16 control; |
144 | ||
e375b561 | 145 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
146 | control &= ~PCI_MSI_FLAGS_ENABLE; |
147 | if (enable) | |
148 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 149 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
150 | } |
151 | ||
b1cbf4e4 EB |
152 | static void msix_set_enable(struct pci_dev *dev, int enable) |
153 | { | |
b1cbf4e4 EB |
154 | u16 control; |
155 | ||
e375b561 GS |
156 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
157 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
158 | if (enable) | |
159 | control |= PCI_MSIX_FLAGS_ENABLE; | |
160 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); | |
b1cbf4e4 EB |
161 | } |
162 | ||
bffac3c5 MW |
163 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
164 | { | |
0b49ec37 MW |
165 | /* Don't shift by >= width of type */ |
166 | if (x >= 5) | |
167 | return 0xffffffff; | |
168 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
169 | } |
170 | ||
f2440d9a | 171 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 172 | { |
f2440d9a MW |
173 | return msi_mask((control >> 1) & 7); |
174 | } | |
988cbb15 | 175 | |
f2440d9a MW |
176 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
177 | { | |
178 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
179 | } |
180 | ||
ce6fce42 MW |
181 | /* |
182 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
183 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
184 | * reliably as devices without an INTx disable bit will then generate a | |
185 | * level IRQ which will never be cleared. | |
ce6fce42 | 186 | */ |
0e4ccb15 | 187 | u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 188 | { |
f2440d9a | 189 | u32 mask_bits = desc->masked; |
1da177e4 | 190 | |
f2440d9a | 191 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 192 | return 0; |
f2440d9a MW |
193 | |
194 | mask_bits &= ~mask; | |
195 | mask_bits |= flag; | |
196 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
197 | |
198 | return mask_bits; | |
199 | } | |
200 | ||
0e4ccb15 KRW |
201 | __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
202 | { | |
203 | return default_msi_mask_irq(desc, mask, flag); | |
204 | } | |
205 | ||
12abb8ba HS |
206 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
207 | { | |
0e4ccb15 | 208 | desc->masked = arch_msi_mask_irq(desc, mask, flag); |
f2440d9a MW |
209 | } |
210 | ||
211 | /* | |
212 | * This internal function does not flush PCI writes to the device. | |
213 | * All users must ensure that they read from the device before either | |
214 | * assuming that the device state is up to date, or returning out of this | |
215 | * file. This saves a few milliseconds when initialising devices with lots | |
216 | * of MSI-X interrupts. | |
217 | */ | |
0e4ccb15 | 218 | u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
219 | { |
220 | u32 mask_bits = desc->masked; | |
221 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 222 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
223 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
224 | if (flag) | |
225 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 226 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
227 | |
228 | return mask_bits; | |
229 | } | |
230 | ||
0e4ccb15 KRW |
231 | __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag) |
232 | { | |
233 | return default_msix_mask_irq(desc, flag); | |
234 | } | |
235 | ||
12abb8ba HS |
236 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) |
237 | { | |
0e4ccb15 | 238 | desc->masked = arch_msix_mask_irq(desc, flag); |
f2440d9a | 239 | } |
24d27553 | 240 | |
1c9db525 | 241 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 242 | { |
1c9db525 | 243 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 244 | |
f2440d9a MW |
245 | if (desc->msi_attrib.is_msix) { |
246 | msix_mask_irq(desc, flag); | |
247 | readl(desc->mask_base); /* Flush write to device */ | |
248 | } else { | |
1c9db525 | 249 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 250 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 251 | } |
f2440d9a MW |
252 | } |
253 | ||
1c9db525 | 254 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 255 | { |
1c9db525 | 256 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
257 | } |
258 | ||
1c9db525 | 259 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 260 | { |
1c9db525 | 261 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
262 | } |
263 | ||
ac8344c4 D |
264 | void default_restore_msi_irqs(struct pci_dev *dev) |
265 | { | |
266 | struct msi_desc *entry; | |
267 | ||
268 | list_for_each_entry(entry, &dev->msi_list, list) { | |
269 | default_restore_msi_irq(dev, entry->irq); | |
270 | } | |
271 | } | |
272 | ||
39431acb | 273 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 274 | { |
30da5524 BH |
275 | BUG_ON(entry->dev->current_state != PCI_D0); |
276 | ||
277 | if (entry->msi_attrib.is_msix) { | |
278 | void __iomem *base = entry->mask_base + | |
279 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
280 | ||
281 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
282 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
283 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
284 | } else { | |
285 | struct pci_dev *dev = entry->dev; | |
f5322169 | 286 | int pos = dev->msi_cap; |
30da5524 BH |
287 | u16 data; |
288 | ||
9925ad0c BH |
289 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
290 | &msg->address_lo); | |
30da5524 | 291 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
292 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
293 | &msg->address_hi); | |
2f221349 | 294 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
295 | } else { |
296 | msg->address_hi = 0; | |
2f221349 | 297 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
298 | } |
299 | msg->data = data; | |
300 | } | |
301 | } | |
302 | ||
303 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
304 | { | |
dced35ae | 305 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 306 | |
39431acb | 307 | __read_msi_msg(entry, msg); |
30da5524 BH |
308 | } |
309 | ||
39431acb | 310 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 311 | { |
30da5524 | 312 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
313 | * valid messages are not all-zeroes. */ |
314 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
315 | entry->msg.data)); | |
0366f8f7 | 316 | |
fcd097f3 | 317 | *msg = entry->msg; |
0366f8f7 | 318 | } |
1da177e4 | 319 | |
30da5524 | 320 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 321 | { |
dced35ae | 322 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 323 | |
39431acb | 324 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
325 | } |
326 | ||
39431acb | 327 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 328 | { |
fcd097f3 BH |
329 | if (entry->dev->current_state != PCI_D0) { |
330 | /* Don't touch the hardware now */ | |
331 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
332 | void __iomem *base; |
333 | base = entry->mask_base + | |
334 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
335 | ||
2c21fd4b HS |
336 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
337 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
338 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 339 | } else { |
0366f8f7 | 340 | struct pci_dev *dev = entry->dev; |
f5322169 | 341 | int pos = dev->msi_cap; |
1c8d7b0a MW |
342 | u16 msgctl; |
343 | ||
f84ecd28 | 344 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
345 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
346 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 347 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 348 | |
9925ad0c BH |
349 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
350 | msg->address_lo); | |
0366f8f7 | 351 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
352 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
353 | msg->address_hi); | |
2f221349 BH |
354 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
355 | msg->data); | |
0366f8f7 | 356 | } else { |
2f221349 BH |
357 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
358 | msg->data); | |
0366f8f7 | 359 | } |
1da177e4 | 360 | } |
392ee1e6 | 361 | entry->msg = *msg; |
1da177e4 | 362 | } |
0366f8f7 | 363 | |
3145e941 YL |
364 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
365 | { | |
dced35ae | 366 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 367 | |
39431acb | 368 | __write_msi_msg(entry, msg); |
3145e941 YL |
369 | } |
370 | ||
f56e4481 HS |
371 | static void free_msi_irqs(struct pci_dev *dev) |
372 | { | |
373 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
374 | struct attribute **msi_attrs; |
375 | struct device_attribute *dev_attr; | |
376 | int count = 0; | |
f56e4481 HS |
377 | |
378 | list_for_each_entry(entry, &dev->msi_list, list) { | |
379 | int i, nvec; | |
380 | if (!entry->irq) | |
381 | continue; | |
65f6ae66 AG |
382 | if (entry->nvec_used) |
383 | nvec = entry->nvec_used; | |
384 | else | |
385 | nvec = 1 << entry->msi_attrib.multiple; | |
f56e4481 HS |
386 | for (i = 0; i < nvec; i++) |
387 | BUG_ON(irq_has_action(entry->irq + i)); | |
388 | } | |
389 | ||
390 | arch_teardown_msi_irqs(dev); | |
391 | ||
392 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
393 | if (entry->msi_attrib.is_msix) { | |
394 | if (list_is_last(&entry->list, &dev->msi_list)) | |
395 | iounmap(entry->mask_base); | |
396 | } | |
424eb391 NH |
397 | |
398 | /* | |
399 | * Its possible that we get into this path | |
400 | * When populate_msi_sysfs fails, which means the entries | |
401 | * were not registered with sysfs. In that case don't | |
402 | * unregister them. | |
403 | */ | |
404 | if (entry->kobj.parent) { | |
405 | kobject_del(&entry->kobj); | |
406 | kobject_put(&entry->kobj); | |
407 | } | |
408 | ||
f56e4481 HS |
409 | list_del(&entry->list); |
410 | kfree(entry); | |
411 | } | |
1c51b50c GKH |
412 | |
413 | if (dev->msi_irq_groups) { | |
414 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
415 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 416 | while (msi_attrs[count]) { |
1c51b50c GKH |
417 | dev_attr = container_of(msi_attrs[count], |
418 | struct device_attribute, attr); | |
419 | kfree(dev_attr->attr.name); | |
420 | kfree(dev_attr); | |
421 | ++count; | |
422 | } | |
423 | kfree(msi_attrs); | |
424 | kfree(dev->msi_irq_groups[0]); | |
425 | kfree(dev->msi_irq_groups); | |
426 | dev->msi_irq_groups = NULL; | |
427 | } | |
f56e4481 | 428 | } |
c54c1879 | 429 | |
379f5327 | 430 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 431 | { |
379f5327 MW |
432 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
433 | if (!desc) | |
1da177e4 LT |
434 | return NULL; |
435 | ||
379f5327 MW |
436 | INIT_LIST_HEAD(&desc->list); |
437 | desc->dev = dev; | |
1da177e4 | 438 | |
379f5327 | 439 | return desc; |
1da177e4 LT |
440 | } |
441 | ||
ba698ad4 DM |
442 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
443 | { | |
444 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
445 | pci_intx(dev, enable); | |
446 | } | |
447 | ||
8fed4b65 | 448 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 449 | { |
41017f0c | 450 | u16 control; |
392ee1e6 | 451 | struct msi_desc *entry; |
41017f0c | 452 | |
b1cbf4e4 EB |
453 | if (!dev->msi_enabled) |
454 | return; | |
455 | ||
dced35ae | 456 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 457 | |
ba698ad4 | 458 | pci_intx_for_msi(dev, 0); |
e375b561 | 459 | msi_set_enable(dev, 0); |
ac8344c4 | 460 | arch_restore_msi_irqs(dev); |
392ee1e6 | 461 | |
f5322169 | 462 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
f2440d9a | 463 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 464 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 465 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 466 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
467 | } |
468 | ||
469 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 470 | { |
41017f0c | 471 | struct msi_desc *entry; |
392ee1e6 | 472 | u16 control; |
41017f0c | 473 | |
ded86d8d EB |
474 | if (!dev->msix_enabled) |
475 | return; | |
f598282f | 476 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 477 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f5322169 | 478 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
ded86d8d | 479 | |
41017f0c | 480 | /* route the table */ |
ba698ad4 | 481 | pci_intx_for_msi(dev, 0); |
f598282f | 482 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 483 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 484 | |
ac8344c4 | 485 | arch_restore_msi_irqs(dev); |
4aa9bc95 | 486 | list_for_each_entry(entry, &dev->msi_list, list) { |
f2440d9a | 487 | msix_mask_irq(entry, entry->masked); |
41017f0c | 488 | } |
41017f0c | 489 | |
392ee1e6 | 490 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
f5322169 | 491 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
41017f0c | 492 | } |
8fed4b65 ME |
493 | |
494 | void pci_restore_msi_state(struct pci_dev *dev) | |
495 | { | |
496 | __pci_restore_msi_state(dev); | |
497 | __pci_restore_msix_state(dev); | |
498 | } | |
94688cf2 | 499 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 500 | |
1c51b50c | 501 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
502 | char *buf) |
503 | { | |
1c51b50c GKH |
504 | struct pci_dev *pdev = to_pci_dev(dev); |
505 | struct msi_desc *entry; | |
506 | unsigned long irq; | |
507 | int retval; | |
da8d1c8b | 508 | |
1c51b50c GKH |
509 | retval = kstrtoul(attr->attr.name, 10, &irq); |
510 | if (retval) | |
511 | return retval; | |
da8d1c8b | 512 | |
1c51b50c GKH |
513 | list_for_each_entry(entry, &pdev->msi_list, list) { |
514 | if (entry->irq == irq) { | |
515 | return sprintf(buf, "%s\n", | |
516 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
517 | } | |
518 | } | |
519 | return -ENODEV; | |
da8d1c8b NH |
520 | } |
521 | ||
da8d1c8b NH |
522 | static int populate_msi_sysfs(struct pci_dev *pdev) |
523 | { | |
1c51b50c GKH |
524 | struct attribute **msi_attrs; |
525 | struct attribute *msi_attr; | |
526 | struct device_attribute *msi_dev_attr; | |
527 | struct attribute_group *msi_irq_group; | |
528 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 529 | struct msi_desc *entry; |
1c51b50c GKH |
530 | int ret = -ENOMEM; |
531 | int num_msi = 0; | |
da8d1c8b NH |
532 | int count = 0; |
533 | ||
1c51b50c GKH |
534 | /* Determine how many msi entries we have */ |
535 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
536 | ++num_msi; | |
537 | } | |
538 | if (!num_msi) | |
539 | return 0; | |
da8d1c8b | 540 | |
1c51b50c GKH |
541 | /* Dynamically create the MSI attributes for the PCI device */ |
542 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
543 | if (!msi_attrs) | |
544 | return -ENOMEM; | |
da8d1c8b | 545 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 546 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 547 | if (!msi_dev_attr) |
1c51b50c | 548 | goto error_attrs; |
1406276c | 549 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 550 | |
1c51b50c | 551 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
552 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
553 | entry->irq); | |
554 | if (!msi_dev_attr->attr.name) | |
555 | goto error_attrs; | |
1c51b50c GKH |
556 | msi_dev_attr->attr.mode = S_IRUGO; |
557 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 558 | ++count; |
da8d1c8b NH |
559 | } |
560 | ||
1c51b50c GKH |
561 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
562 | if (!msi_irq_group) | |
563 | goto error_attrs; | |
564 | msi_irq_group->name = "msi_irqs"; | |
565 | msi_irq_group->attrs = msi_attrs; | |
566 | ||
567 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
568 | if (!msi_irq_groups) | |
569 | goto error_irq_group; | |
570 | msi_irq_groups[0] = msi_irq_group; | |
571 | ||
572 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
573 | if (ret) | |
574 | goto error_irq_groups; | |
575 | pdev->msi_irq_groups = msi_irq_groups; | |
576 | ||
da8d1c8b NH |
577 | return 0; |
578 | ||
1c51b50c GKH |
579 | error_irq_groups: |
580 | kfree(msi_irq_groups); | |
581 | error_irq_group: | |
582 | kfree(msi_irq_group); | |
583 | error_attrs: | |
584 | count = 0; | |
585 | msi_attr = msi_attrs[count]; | |
586 | while (msi_attr) { | |
587 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
588 | kfree(msi_attr->name); | |
589 | kfree(msi_dev_attr); | |
590 | ++count; | |
591 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 592 | } |
29237756 | 593 | kfree(msi_attrs); |
da8d1c8b NH |
594 | return ret; |
595 | } | |
596 | ||
1da177e4 LT |
597 | /** |
598 | * msi_capability_init - configure device's MSI capability structure | |
599 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 600 | * @nvec: number of interrupts to allocate |
1da177e4 | 601 | * |
1c8d7b0a MW |
602 | * Setup the MSI capability structure of the device with the requested |
603 | * number of interrupts. A return value of zero indicates the successful | |
604 | * setup of an entry with the new MSI irq. A negative return value indicates | |
605 | * an error, and a positive return value indicates the number of interrupts | |
606 | * which could have been allocated. | |
607 | */ | |
608 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
609 | { |
610 | struct msi_desc *entry; | |
f465136d | 611 | int ret; |
1da177e4 | 612 | u16 control; |
f2440d9a | 613 | unsigned mask; |
1da177e4 | 614 | |
e375b561 | 615 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 616 | |
f84ecd28 | 617 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
1da177e4 | 618 | /* MSI Entry Initialization */ |
379f5327 | 619 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
620 | if (!entry) |
621 | return -ENOMEM; | |
1ce03373 | 622 | |
500559a9 | 623 | entry->msi_attrib.is_msix = 0; |
4987ce82 | 624 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); |
500559a9 | 625 | entry->msi_attrib.entry_nr = 0; |
4987ce82 | 626 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); |
500559a9 | 627 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
f465136d | 628 | entry->msi_attrib.pos = dev->msi_cap; |
f2440d9a | 629 | |
e5f66eaf DC |
630 | if (control & PCI_MSI_FLAGS_64BIT) |
631 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
632 | else | |
633 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
f2440d9a MW |
634 | /* All MSIs are unmasked by default, Mask them all */ |
635 | if (entry->msi_attrib.maskbit) | |
636 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
637 | mask = msi_capable_mask(control); | |
638 | msi_mask_irq(entry, mask, mask); | |
639 | ||
0dd11f9b | 640 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 641 | |
1da177e4 | 642 | /* Configure MSI capability structure */ |
1c8d7b0a | 643 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 644 | if (ret) { |
7ba1930d | 645 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 646 | free_msi_irqs(dev); |
7fe3730d | 647 | return ret; |
fd58e55f | 648 | } |
f7feaca7 | 649 | |
da8d1c8b NH |
650 | ret = populate_msi_sysfs(dev); |
651 | if (ret) { | |
652 | msi_mask_irq(entry, mask, ~mask); | |
653 | free_msi_irqs(dev); | |
654 | return ret; | |
655 | } | |
656 | ||
1da177e4 | 657 | /* Set MSI enabled bits */ |
ba698ad4 | 658 | pci_intx_for_msi(dev, 0); |
e375b561 | 659 | msi_set_enable(dev, 1); |
b1cbf4e4 | 660 | dev->msi_enabled = 1; |
1da177e4 | 661 | |
7fe3730d | 662 | dev->irq = entry->irq; |
1da177e4 LT |
663 | return 0; |
664 | } | |
665 | ||
520fe9dc | 666 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 667 | { |
4302e0fb | 668 | resource_size_t phys_addr; |
5a05a9d8 HS |
669 | u32 table_offset; |
670 | u8 bir; | |
671 | ||
909094c6 BH |
672 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
673 | &table_offset); | |
4d18760c BH |
674 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
675 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
676 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
677 | ||
678 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
679 | } | |
680 | ||
520fe9dc GS |
681 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
682 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
683 | { |
684 | struct msi_desc *entry; | |
685 | int i; | |
686 | ||
687 | for (i = 0; i < nvec; i++) { | |
688 | entry = alloc_msi_entry(dev); | |
689 | if (!entry) { | |
690 | if (!i) | |
691 | iounmap(base); | |
692 | else | |
693 | free_msi_irqs(dev); | |
694 | /* No enough memory. Don't try again */ | |
695 | return -ENOMEM; | |
696 | } | |
697 | ||
698 | entry->msi_attrib.is_msix = 1; | |
699 | entry->msi_attrib.is_64 = 1; | |
700 | entry->msi_attrib.entry_nr = entries[i].entry; | |
701 | entry->msi_attrib.default_irq = dev->irq; | |
520fe9dc | 702 | entry->msi_attrib.pos = dev->msix_cap; |
d9d7070e HS |
703 | entry->mask_base = base; |
704 | ||
705 | list_add_tail(&entry->list, &dev->msi_list); | |
706 | } | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
75cb3426 | 711 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 712 | struct msix_entry *entries) |
75cb3426 HS |
713 | { |
714 | struct msi_desc *entry; | |
715 | int i = 0; | |
716 | ||
717 | list_for_each_entry(entry, &dev->msi_list, list) { | |
718 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
719 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
720 | ||
721 | entries[i].vector = entry->irq; | |
dced35ae | 722 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
723 | entry->masked = readl(entry->mask_base + offset); |
724 | msix_mask_irq(entry, 1); | |
725 | i++; | |
726 | } | |
727 | } | |
728 | ||
1da177e4 LT |
729 | /** |
730 | * msix_capability_init - configure device's MSI-X capability | |
731 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
732 | * @entries: pointer to an array of struct msix_entry entries |
733 | * @nvec: number of @entries | |
1da177e4 | 734 | * |
eaae4b3a | 735 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
736 | * single MSI-X irq. A return of zero indicates the successful setup of |
737 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
738 | **/ |
739 | static int msix_capability_init(struct pci_dev *dev, | |
740 | struct msix_entry *entries, int nvec) | |
741 | { | |
520fe9dc | 742 | int ret; |
5a05a9d8 | 743 | u16 control; |
1da177e4 LT |
744 | void __iomem *base; |
745 | ||
520fe9dc | 746 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
f598282f MW |
747 | |
748 | /* Ensure MSI-X is disabled while it is set up */ | |
749 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 750 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 751 | |
1da177e4 | 752 | /* Request & Map MSI-X table region */ |
527eee29 | 753 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 754 | if (!base) |
1da177e4 LT |
755 | return -ENOMEM; |
756 | ||
520fe9dc | 757 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
758 | if (ret) |
759 | return ret; | |
9c831334 ME |
760 | |
761 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 | 762 | if (ret) |
2adc7907 | 763 | goto out_avail; |
9c831334 | 764 | |
f598282f MW |
765 | /* |
766 | * Some devices require MSI-X to be enabled before we can touch the | |
767 | * MSI-X registers. We need to mask all the vectors to prevent | |
768 | * interrupts coming in before they're fully set up. | |
769 | */ | |
770 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
520fe9dc | 771 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
f598282f | 772 | |
75cb3426 | 773 | msix_program_entries(dev, entries); |
f598282f | 774 | |
da8d1c8b | 775 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
776 | if (ret) |
777 | goto out_free; | |
da8d1c8b | 778 | |
f598282f | 779 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 780 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 781 | dev->msix_enabled = 1; |
1da177e4 | 782 | |
f598282f | 783 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
520fe9dc | 784 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control); |
8d181018 | 785 | |
1da177e4 | 786 | return 0; |
583871d4 | 787 | |
2adc7907 | 788 | out_avail: |
583871d4 HS |
789 | if (ret < 0) { |
790 | /* | |
791 | * If we had some success, report the number of irqs | |
792 | * we succeeded in setting up. | |
793 | */ | |
d9d7070e | 794 | struct msi_desc *entry; |
583871d4 HS |
795 | int avail = 0; |
796 | ||
797 | list_for_each_entry(entry, &dev->msi_list, list) { | |
798 | if (entry->irq != 0) | |
799 | avail++; | |
800 | } | |
801 | if (avail != 0) | |
802 | ret = avail; | |
803 | } | |
804 | ||
2adc7907 | 805 | out_free: |
583871d4 HS |
806 | free_msi_irqs(dev); |
807 | ||
808 | return ret; | |
1da177e4 LT |
809 | } |
810 | ||
24334a12 | 811 | /** |
17bbc12a | 812 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 813 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 814 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 815 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 816 | * |
f7625980 | 817 | * Look at global flags, the device itself, and its parent buses |
17bbc12a ME |
818 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
819 | * supported return 0, else return an error code. | |
24334a12 | 820 | **/ |
500559a9 | 821 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
822 | { |
823 | struct pci_bus *bus; | |
c9953a73 | 824 | int ret; |
24334a12 | 825 | |
0306ebfa | 826 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
827 | if (!pci_msi_enable || !dev || dev->no_msi) |
828 | return -EINVAL; | |
829 | ||
314e77b3 ME |
830 | /* |
831 | * You can't ask to have 0 or less MSIs configured. | |
832 | * a) it's stupid .. | |
833 | * b) the list manipulation code assumes nvec >= 1. | |
834 | */ | |
835 | if (nvec < 1) | |
836 | return -ERANGE; | |
837 | ||
500559a9 HS |
838 | /* |
839 | * Any bridge which does NOT route MSI transactions from its | |
840 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
841 | * the secondary pci_bus. |
842 | * We expect only arch-specific PCI host bus controller driver | |
843 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
844 | */ | |
24334a12 BG |
845 | for (bus = dev->bus; bus; bus = bus->parent) |
846 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
847 | return -EINVAL; | |
848 | ||
c9953a73 ME |
849 | ret = arch_msi_check_device(dev, nvec, type); |
850 | if (ret) | |
851 | return ret; | |
852 | ||
24334a12 BG |
853 | return 0; |
854 | } | |
855 | ||
d1ac1d26 AG |
856 | /** |
857 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
858 | * @dev: device to report about | |
859 | * | |
860 | * This function returns the number of MSI vectors a device requested via | |
861 | * Multiple Message Capable register. It returns a negative errno if the | |
862 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
863 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
864 | * MSI specification. | |
865 | **/ | |
866 | int pci_msi_vec_count(struct pci_dev *dev) | |
867 | { | |
868 | int ret; | |
869 | u16 msgctl; | |
870 | ||
871 | if (!dev->msi_cap) | |
872 | return -EINVAL; | |
873 | ||
874 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
875 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
876 | ||
877 | return ret; | |
878 | } | |
879 | EXPORT_SYMBOL(pci_msi_vec_count); | |
880 | ||
f2440d9a | 881 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 882 | { |
f2440d9a MW |
883 | struct msi_desc *desc; |
884 | u32 mask; | |
885 | u16 ctrl; | |
1da177e4 | 886 | |
128bc5fc | 887 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
888 | return; |
889 | ||
110828c9 MW |
890 | BUG_ON(list_empty(&dev->msi_list)); |
891 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 892 | |
e375b561 | 893 | msi_set_enable(dev, 0); |
ba698ad4 | 894 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 895 | dev->msi_enabled = 0; |
7bd007e4 | 896 | |
12abb8ba | 897 | /* Return the device with MSI unmasked as initial states */ |
f5322169 | 898 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 899 | mask = msi_capable_mask(ctrl); |
12abb8ba | 900 | /* Keep cached state to be restored */ |
0e4ccb15 | 901 | arch_msi_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
902 | |
903 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 904 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 905 | } |
24d27553 | 906 | |
500559a9 | 907 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 908 | { |
d52877c7 YL |
909 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
910 | return; | |
911 | ||
912 | pci_msi_shutdown(dev); | |
f56e4481 | 913 | free_msi_irqs(dev); |
1da177e4 | 914 | } |
4cc086fa | 915 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 916 | |
a52e2e35 | 917 | /** |
ff1aa430 | 918 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 919 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
920 | * This function returns the number of device's MSI-X table entries and |
921 | * therefore the number of MSI-X vectors device is capable of sending. | |
922 | * It returns a negative errno if the device is not capable of sending MSI-X | |
923 | * interrupts. | |
924 | **/ | |
925 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 926 | { |
a52e2e35 RW |
927 | u16 control; |
928 | ||
520fe9dc | 929 | if (!dev->msix_cap) |
ff1aa430 | 930 | return -EINVAL; |
a52e2e35 | 931 | |
f84ecd28 | 932 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 933 | return msix_table_size(control); |
a52e2e35 | 934 | } |
ff1aa430 | 935 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 936 | |
1da177e4 LT |
937 | /** |
938 | * pci_enable_msix - configure device's MSI-X capability structure | |
939 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 940 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 941 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
942 | * |
943 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 944 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
945 | * MSI-X mode enabled on its hardware device function. A return of zero |
946 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 947 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 948 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
949 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
950 | * re-send its request. | |
1da177e4 | 951 | **/ |
500559a9 | 952 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 953 | { |
a52e2e35 | 954 | int status, nr_entries; |
ded86d8d | 955 | int i, j; |
1da177e4 | 956 | |
869a1615 | 957 | if (!entries || !dev->msix_cap || dev->current_state != PCI_D0) |
500559a9 | 958 | return -EINVAL; |
1da177e4 | 959 | |
c9953a73 ME |
960 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
961 | if (status) | |
962 | return status; | |
963 | ||
ff1aa430 AG |
964 | nr_entries = pci_msix_vec_count(dev); |
965 | if (nr_entries < 0) | |
966 | return nr_entries; | |
1da177e4 | 967 | if (nvec > nr_entries) |
57fbf52c | 968 | return nr_entries; |
1da177e4 LT |
969 | |
970 | /* Check for any invalid entries */ | |
971 | for (i = 0; i < nvec; i++) { | |
972 | if (entries[i].entry >= nr_entries) | |
973 | return -EINVAL; /* invalid entry */ | |
974 | for (j = i + 1; j < nvec; j++) { | |
975 | if (entries[i].entry == entries[j].entry) | |
976 | return -EINVAL; /* duplicate entry */ | |
977 | } | |
978 | } | |
ded86d8d | 979 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 980 | |
1ce03373 | 981 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 982 | if (dev->msi_enabled) { |
227f0647 | 983 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
984 | return -EINVAL; |
985 | } | |
1da177e4 | 986 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
987 | return status; |
988 | } | |
4cc086fa | 989 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 990 | |
500559a9 | 991 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 992 | { |
12abb8ba HS |
993 | struct msi_desc *entry; |
994 | ||
128bc5fc | 995 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
996 | return; |
997 | ||
12abb8ba HS |
998 | /* Return the device with MSI-X masked as initial states */ |
999 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1000 | /* Keep cached states to be restored */ | |
0e4ccb15 | 1001 | arch_msix_mask_irq(entry, 1); |
12abb8ba HS |
1002 | } |
1003 | ||
b1cbf4e4 | 1004 | msix_set_enable(dev, 0); |
ba698ad4 | 1005 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1006 | dev->msix_enabled = 0; |
d52877c7 | 1007 | } |
c901851f | 1008 | |
500559a9 | 1009 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1010 | { |
1011 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1012 | return; | |
1013 | ||
1014 | pci_msix_shutdown(dev); | |
f56e4481 | 1015 | free_msi_irqs(dev); |
1da177e4 | 1016 | } |
4cc086fa | 1017 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
1018 | |
1019 | /** | |
1ce03373 | 1020 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
1021 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
1022 | * | |
eaae4b3a | 1023 | * Being called during hotplug remove, from which the device function |
1ce03373 | 1024 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
1025 | * allocated for this device function, are reclaimed to unused state, |
1026 | * which may be used later on. | |
1027 | **/ | |
500559a9 | 1028 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 1029 | { |
1da177e4 | 1030 | if (!pci_msi_enable || !dev) |
500559a9 | 1031 | return; |
1da177e4 | 1032 | |
f56e4481 HS |
1033 | if (dev->msi_enabled || dev->msix_enabled) |
1034 | free_msi_irqs(dev); | |
1da177e4 LT |
1035 | } |
1036 | ||
309e57df MW |
1037 | void pci_no_msi(void) |
1038 | { | |
1039 | pci_msi_enable = 0; | |
1040 | } | |
c9953a73 | 1041 | |
07ae95f9 AP |
1042 | /** |
1043 | * pci_msi_enabled - is MSI enabled? | |
1044 | * | |
1045 | * Returns true if MSI has not been disabled by the command-line option | |
1046 | * pci=nomsi. | |
1047 | **/ | |
1048 | int pci_msi_enabled(void) | |
d389fec6 | 1049 | { |
07ae95f9 | 1050 | return pci_msi_enable; |
d389fec6 | 1051 | } |
07ae95f9 | 1052 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1053 | |
07ae95f9 | 1054 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1055 | { |
07ae95f9 | 1056 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1057 | |
1058 | /* Disable the msi hardware to avoid screaming interrupts | |
1059 | * during boot. This is the power on reset default so | |
1060 | * usually this should be a noop. | |
1061 | */ | |
e375b561 GS |
1062 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1063 | if (dev->msi_cap) | |
1064 | msi_set_enable(dev, 0); | |
1065 | ||
1066 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1067 | if (dev->msix_cap) | |
1068 | msix_set_enable(dev, 0); | |
d389fec6 | 1069 | } |
302a2523 AG |
1070 | |
1071 | /** | |
1072 | * pci_enable_msi_range - configure device's MSI capability structure | |
1073 | * @dev: device to configure | |
1074 | * @minvec: minimal number of interrupts to configure | |
1075 | * @maxvec: maximum number of interrupts to configure | |
1076 | * | |
1077 | * This function tries to allocate a maximum possible number of interrupts in a | |
1078 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1079 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1080 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1081 | * the other interrupt numbers allocated to this device are consecutive. | |
1082 | **/ | |
1083 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1084 | { | |
034cd97e | 1085 | int nvec; |
302a2523 AG |
1086 | int rc; |
1087 | ||
034cd97e AG |
1088 | if (dev->current_state != PCI_D0) |
1089 | return -EINVAL; | |
1090 | ||
1091 | WARN_ON(!!dev->msi_enabled); | |
1092 | ||
1093 | /* Check whether driver already requested MSI-X irqs */ | |
1094 | if (dev->msix_enabled) { | |
1095 | dev_info(&dev->dev, | |
1096 | "can't enable MSI (MSI-X already enabled)\n"); | |
1097 | return -EINVAL; | |
1098 | } | |
1099 | ||
302a2523 AG |
1100 | if (maxvec < minvec) |
1101 | return -ERANGE; | |
1102 | ||
034cd97e AG |
1103 | nvec = pci_msi_vec_count(dev); |
1104 | if (nvec < 0) | |
1105 | return nvec; | |
1106 | else if (nvec < minvec) | |
1107 | return -EINVAL; | |
1108 | else if (nvec > maxvec) | |
1109 | nvec = maxvec; | |
1110 | ||
1111 | do { | |
1112 | rc = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); | |
1113 | if (rc < 0) { | |
1114 | return rc; | |
1115 | } else if (rc > 0) { | |
1116 | if (rc < minvec) | |
1117 | return -ENOSPC; | |
1118 | nvec = rc; | |
1119 | } | |
1120 | } while (rc); | |
1121 | ||
302a2523 | 1122 | do { |
034cd97e | 1123 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1124 | if (rc < 0) { |
1125 | return rc; | |
1126 | } else if (rc > 0) { | |
1127 | if (rc < minvec) | |
1128 | return -ENOSPC; | |
1129 | nvec = rc; | |
1130 | } | |
1131 | } while (rc); | |
1132 | ||
1133 | return nvec; | |
1134 | } | |
1135 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1136 | ||
1137 | /** | |
1138 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1139 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1140 | * @entries: pointer to an array of MSI-X entries | |
1141 | * @minvec: minimum number of MSI-X irqs requested | |
1142 | * @maxvec: maximum number of MSI-X irqs requested | |
1143 | * | |
1144 | * Setup the MSI-X capability structure of device function with a maximum | |
1145 | * possible number of interrupts in the range between @minvec and @maxvec | |
1146 | * upon its software driver call to request for MSI-X mode enabled on its | |
1147 | * hardware device function. It returns a negative errno if an error occurs. | |
1148 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1149 | * indicates the successful configuration of MSI-X capability structure | |
1150 | * with new allocated MSI-X interrupts. | |
1151 | **/ | |
1152 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1153 | int minvec, int maxvec) | |
1154 | { | |
1155 | int nvec = maxvec; | |
1156 | int rc; | |
1157 | ||
1158 | if (maxvec < minvec) | |
1159 | return -ERANGE; | |
1160 | ||
1161 | do { | |
1162 | rc = pci_enable_msix(dev, entries, nvec); | |
1163 | if (rc < 0) { | |
1164 | return rc; | |
1165 | } else if (rc > 0) { | |
1166 | if (rc < minvec) | |
1167 | return -ENOSPC; | |
1168 | nvec = rc; | |
1169 | } | |
1170 | } while (rc); | |
1171 | ||
1172 | return nvec; | |
1173 | } | |
1174 | EXPORT_SYMBOL(pci_enable_msix_range); |