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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
1da177e4 | 27 | static int pci_msi_enable = 1; |
1da177e4 | 28 | |
6a9e7f20 AB |
29 | /* Arch hooks */ |
30 | ||
11df1f05 ME |
31 | #ifndef arch_msi_check_device |
32 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
33 | { |
34 | return 0; | |
35 | } | |
11df1f05 | 36 | #endif |
6a9e7f20 | 37 | |
11df1f05 | 38 | #ifndef arch_setup_msi_irqs |
1525bf0d TG |
39 | # define arch_setup_msi_irqs default_setup_msi_irqs |
40 | # define HAVE_DEFAULT_MSI_SETUP_IRQS | |
41 | #endif | |
42 | ||
43 | #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS | |
44 | int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
45 | { |
46 | struct msi_desc *entry; | |
47 | int ret; | |
48 | ||
1c8d7b0a MW |
49 | /* |
50 | * If an architecture wants to support multiple MSI, it needs to | |
51 | * override arch_setup_msi_irqs() | |
52 | */ | |
53 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
54 | return 1; | |
55 | ||
6a9e7f20 AB |
56 | list_for_each_entry(entry, &dev->msi_list, list) { |
57 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 58 | if (ret < 0) |
6a9e7f20 | 59 | return ret; |
b5fbf533 ME |
60 | if (ret > 0) |
61 | return -ENOSPC; | |
6a9e7f20 AB |
62 | } |
63 | ||
64 | return 0; | |
65 | } | |
11df1f05 | 66 | #endif |
6a9e7f20 | 67 | |
11df1f05 | 68 | #ifndef arch_teardown_msi_irqs |
1525bf0d TG |
69 | # define arch_teardown_msi_irqs default_teardown_msi_irqs |
70 | # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
71 | #endif | |
72 | ||
73 | #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
74 | void default_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
75 | { |
76 | struct msi_desc *entry; | |
77 | ||
78 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
79 | int i, nvec; |
80 | if (entry->irq == 0) | |
81 | continue; | |
82 | nvec = 1 << entry->msi_attrib.multiple; | |
83 | for (i = 0; i < nvec; i++) | |
84 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
85 | } |
86 | } | |
11df1f05 | 87 | #endif |
6a9e7f20 | 88 | |
110828c9 | 89 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 90 | { |
b1cbf4e4 EB |
91 | u16 control; |
92 | ||
110828c9 | 93 | BUG_ON(!pos); |
b1cbf4e4 | 94 | |
110828c9 MW |
95 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
96 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
97 | if (enable) | |
98 | control |= PCI_MSI_FLAGS_ENABLE; | |
99 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
100 | } |
101 | ||
b1cbf4e4 EB |
102 | static void msix_set_enable(struct pci_dev *dev, int enable) |
103 | { | |
104 | int pos; | |
105 | u16 control; | |
106 | ||
107 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
108 | if (pos) { | |
109 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
110 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
111 | if (enable) | |
112 | control |= PCI_MSIX_FLAGS_ENABLE; | |
113 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
114 | } | |
115 | } | |
116 | ||
bffac3c5 MW |
117 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
118 | { | |
0b49ec37 MW |
119 | /* Don't shift by >= width of type */ |
120 | if (x >= 5) | |
121 | return 0xffffffff; | |
122 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
123 | } |
124 | ||
f2440d9a | 125 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 126 | { |
f2440d9a MW |
127 | return msi_mask((control >> 1) & 7); |
128 | } | |
988cbb15 | 129 | |
f2440d9a MW |
130 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
131 | { | |
132 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
133 | } |
134 | ||
ce6fce42 MW |
135 | /* |
136 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
137 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
138 | * reliably as devices without an INTx disable bit will then generate a | |
139 | * level IRQ which will never be cleared. | |
ce6fce42 | 140 | */ |
12abb8ba | 141 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 142 | { |
f2440d9a | 143 | u32 mask_bits = desc->masked; |
1da177e4 | 144 | |
f2440d9a | 145 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 146 | return 0; |
f2440d9a MW |
147 | |
148 | mask_bits &= ~mask; | |
149 | mask_bits |= flag; | |
150 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
151 | |
152 | return mask_bits; | |
153 | } | |
154 | ||
155 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
156 | { | |
157 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
158 | } |
159 | ||
160 | /* | |
161 | * This internal function does not flush PCI writes to the device. | |
162 | * All users must ensure that they read from the device before either | |
163 | * assuming that the device state is up to date, or returning out of this | |
164 | * file. This saves a few milliseconds when initialising devices with lots | |
165 | * of MSI-X interrupts. | |
166 | */ | |
12abb8ba | 167 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
168 | { |
169 | u32 mask_bits = desc->masked; | |
170 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 171 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
172 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
173 | if (flag) | |
174 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 175 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
176 | |
177 | return mask_bits; | |
178 | } | |
179 | ||
180 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
181 | { | |
182 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 183 | } |
24d27553 | 184 | |
1c9db525 | 185 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 186 | { |
1c9db525 | 187 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 188 | |
f2440d9a MW |
189 | if (desc->msi_attrib.is_msix) { |
190 | msix_mask_irq(desc, flag); | |
191 | readl(desc->mask_base); /* Flush write to device */ | |
192 | } else { | |
1c9db525 | 193 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 194 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 195 | } |
f2440d9a MW |
196 | } |
197 | ||
1c9db525 | 198 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 199 | { |
1c9db525 | 200 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
201 | } |
202 | ||
1c9db525 | 203 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 204 | { |
1c9db525 | 205 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
206 | } |
207 | ||
39431acb | 208 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 209 | { |
30da5524 BH |
210 | BUG_ON(entry->dev->current_state != PCI_D0); |
211 | ||
212 | if (entry->msi_attrib.is_msix) { | |
213 | void __iomem *base = entry->mask_base + | |
214 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
215 | ||
216 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
217 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
218 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
219 | } else { | |
220 | struct pci_dev *dev = entry->dev; | |
221 | int pos = entry->msi_attrib.pos; | |
222 | u16 data; | |
223 | ||
224 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
225 | &msg->address_lo); | |
226 | if (entry->msi_attrib.is_64) { | |
227 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
228 | &msg->address_hi); | |
229 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
230 | } else { | |
231 | msg->address_hi = 0; | |
232 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); | |
233 | } | |
234 | msg->data = data; | |
235 | } | |
236 | } | |
237 | ||
238 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
239 | { | |
dced35ae | 240 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 241 | |
39431acb | 242 | __read_msi_msg(entry, msg); |
30da5524 BH |
243 | } |
244 | ||
39431acb | 245 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 246 | { |
30da5524 | 247 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
248 | * valid messages are not all-zeroes. */ |
249 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
250 | entry->msg.data)); | |
0366f8f7 | 251 | |
fcd097f3 | 252 | *msg = entry->msg; |
0366f8f7 | 253 | } |
1da177e4 | 254 | |
30da5524 | 255 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 256 | { |
dced35ae | 257 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 258 | |
39431acb | 259 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
260 | } |
261 | ||
39431acb | 262 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 263 | { |
fcd097f3 BH |
264 | if (entry->dev->current_state != PCI_D0) { |
265 | /* Don't touch the hardware now */ | |
266 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
267 | void __iomem *base; |
268 | base = entry->mask_base + | |
269 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
270 | ||
2c21fd4b HS |
271 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
272 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
273 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 274 | } else { |
0366f8f7 EB |
275 | struct pci_dev *dev = entry->dev; |
276 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
277 | u16 msgctl; |
278 | ||
279 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
280 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
281 | msgctl |= entry->msi_attrib.multiple << 4; | |
282 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
283 | |
284 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
285 | msg->address_lo); | |
286 | if (entry->msi_attrib.is_64) { | |
287 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
288 | msg->address_hi); | |
289 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
290 | msg->data); | |
291 | } else { | |
292 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
293 | msg->data); | |
294 | } | |
1da177e4 | 295 | } |
392ee1e6 | 296 | entry->msg = *msg; |
1da177e4 | 297 | } |
0366f8f7 | 298 | |
3145e941 YL |
299 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
300 | { | |
dced35ae | 301 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 302 | |
39431acb | 303 | __write_msi_msg(entry, msg); |
3145e941 YL |
304 | } |
305 | ||
f56e4481 HS |
306 | static void free_msi_irqs(struct pci_dev *dev) |
307 | { | |
308 | struct msi_desc *entry, *tmp; | |
309 | ||
310 | list_for_each_entry(entry, &dev->msi_list, list) { | |
311 | int i, nvec; | |
312 | if (!entry->irq) | |
313 | continue; | |
314 | nvec = 1 << entry->msi_attrib.multiple; | |
315 | for (i = 0; i < nvec; i++) | |
316 | BUG_ON(irq_has_action(entry->irq + i)); | |
317 | } | |
318 | ||
319 | arch_teardown_msi_irqs(dev); | |
320 | ||
321 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
322 | if (entry->msi_attrib.is_msix) { | |
323 | if (list_is_last(&entry->list, &dev->msi_list)) | |
324 | iounmap(entry->mask_base); | |
325 | } | |
326 | list_del(&entry->list); | |
327 | kfree(entry); | |
328 | } | |
329 | } | |
c54c1879 | 330 | |
379f5327 | 331 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 332 | { |
379f5327 MW |
333 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
334 | if (!desc) | |
1da177e4 LT |
335 | return NULL; |
336 | ||
379f5327 MW |
337 | INIT_LIST_HEAD(&desc->list); |
338 | desc->dev = dev; | |
1da177e4 | 339 | |
379f5327 | 340 | return desc; |
1da177e4 LT |
341 | } |
342 | ||
ba698ad4 DM |
343 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
344 | { | |
345 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
346 | pci_intx(dev, enable); | |
347 | } | |
348 | ||
8fed4b65 | 349 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 350 | { |
392ee1e6 | 351 | int pos; |
41017f0c | 352 | u16 control; |
392ee1e6 | 353 | struct msi_desc *entry; |
41017f0c | 354 | |
b1cbf4e4 EB |
355 | if (!dev->msi_enabled) |
356 | return; | |
357 | ||
dced35ae | 358 | entry = irq_get_msi_desc(dev->irq); |
392ee1e6 | 359 | pos = entry->msi_attrib.pos; |
41017f0c | 360 | |
ba698ad4 | 361 | pci_intx_for_msi(dev, 0); |
110828c9 | 362 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 363 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
364 | |
365 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 366 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 367 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 368 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 369 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
370 | } |
371 | ||
372 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 373 | { |
41017f0c | 374 | int pos; |
41017f0c | 375 | struct msi_desc *entry; |
392ee1e6 | 376 | u16 control; |
41017f0c | 377 | |
ded86d8d EB |
378 | if (!dev->msix_enabled) |
379 | return; | |
f598282f | 380 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 381 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f598282f MW |
382 | pos = entry->msi_attrib.pos; |
383 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 384 | |
41017f0c | 385 | /* route the table */ |
ba698ad4 | 386 | pci_intx_for_msi(dev, 0); |
f598282f MW |
387 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
388 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 389 | |
4aa9bc95 ME |
390 | list_for_each_entry(entry, &dev->msi_list, list) { |
391 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 392 | msix_mask_irq(entry, entry->masked); |
41017f0c | 393 | } |
41017f0c | 394 | |
392ee1e6 | 395 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 396 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 397 | } |
8fed4b65 ME |
398 | |
399 | void pci_restore_msi_state(struct pci_dev *dev) | |
400 | { | |
401 | __pci_restore_msi_state(dev); | |
402 | __pci_restore_msix_state(dev); | |
403 | } | |
94688cf2 | 404 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 405 | |
1da177e4 LT |
406 | /** |
407 | * msi_capability_init - configure device's MSI capability structure | |
408 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 409 | * @nvec: number of interrupts to allocate |
1da177e4 | 410 | * |
1c8d7b0a MW |
411 | * Setup the MSI capability structure of the device with the requested |
412 | * number of interrupts. A return value of zero indicates the successful | |
413 | * setup of an entry with the new MSI irq. A negative return value indicates | |
414 | * an error, and a positive return value indicates the number of interrupts | |
415 | * which could have been allocated. | |
416 | */ | |
417 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
418 | { |
419 | struct msi_desc *entry; | |
7fe3730d | 420 | int pos, ret; |
1da177e4 | 421 | u16 control; |
f2440d9a | 422 | unsigned mask; |
1da177e4 | 423 | |
500559a9 | 424 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
110828c9 MW |
425 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
426 | ||
1da177e4 LT |
427 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
428 | /* MSI Entry Initialization */ | |
379f5327 | 429 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
430 | if (!entry) |
431 | return -ENOMEM; | |
1ce03373 | 432 | |
500559a9 HS |
433 | entry->msi_attrib.is_msix = 0; |
434 | entry->msi_attrib.is_64 = is_64bit_address(control); | |
435 | entry->msi_attrib.entry_nr = 0; | |
436 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
437 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
438 | entry->msi_attrib.pos = pos; | |
f2440d9a | 439 | |
67b5db65 | 440 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
441 | /* All MSIs are unmasked by default, Mask them all */ |
442 | if (entry->msi_attrib.maskbit) | |
443 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
444 | mask = msi_capable_mask(control); | |
445 | msi_mask_irq(entry, mask, mask); | |
446 | ||
0dd11f9b | 447 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 448 | |
1da177e4 | 449 | /* Configure MSI capability structure */ |
1c8d7b0a | 450 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 451 | if (ret) { |
7ba1930d | 452 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 453 | free_msi_irqs(dev); |
7fe3730d | 454 | return ret; |
fd58e55f | 455 | } |
f7feaca7 | 456 | |
1da177e4 | 457 | /* Set MSI enabled bits */ |
ba698ad4 | 458 | pci_intx_for_msi(dev, 0); |
110828c9 | 459 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 460 | dev->msi_enabled = 1; |
1da177e4 | 461 | |
7fe3730d | 462 | dev->irq = entry->irq; |
1da177e4 LT |
463 | return 0; |
464 | } | |
465 | ||
5a05a9d8 HS |
466 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, |
467 | unsigned nr_entries) | |
468 | { | |
4302e0fb | 469 | resource_size_t phys_addr; |
5a05a9d8 HS |
470 | u32 table_offset; |
471 | u8 bir; | |
472 | ||
473 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
474 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
475 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; | |
476 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
477 | ||
478 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
479 | } | |
480 | ||
d9d7070e HS |
481 | static int msix_setup_entries(struct pci_dev *dev, unsigned pos, |
482 | void __iomem *base, struct msix_entry *entries, | |
483 | int nvec) | |
484 | { | |
485 | struct msi_desc *entry; | |
486 | int i; | |
487 | ||
488 | for (i = 0; i < nvec; i++) { | |
489 | entry = alloc_msi_entry(dev); | |
490 | if (!entry) { | |
491 | if (!i) | |
492 | iounmap(base); | |
493 | else | |
494 | free_msi_irqs(dev); | |
495 | /* No enough memory. Don't try again */ | |
496 | return -ENOMEM; | |
497 | } | |
498 | ||
499 | entry->msi_attrib.is_msix = 1; | |
500 | entry->msi_attrib.is_64 = 1; | |
501 | entry->msi_attrib.entry_nr = entries[i].entry; | |
502 | entry->msi_attrib.default_irq = dev->irq; | |
503 | entry->msi_attrib.pos = pos; | |
504 | entry->mask_base = base; | |
505 | ||
506 | list_add_tail(&entry->list, &dev->msi_list); | |
507 | } | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
75cb3426 HS |
512 | static void msix_program_entries(struct pci_dev *dev, |
513 | struct msix_entry *entries) | |
514 | { | |
515 | struct msi_desc *entry; | |
516 | int i = 0; | |
517 | ||
518 | list_for_each_entry(entry, &dev->msi_list, list) { | |
519 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
520 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
521 | ||
522 | entries[i].vector = entry->irq; | |
dced35ae | 523 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
524 | entry->masked = readl(entry->mask_base + offset); |
525 | msix_mask_irq(entry, 1); | |
526 | i++; | |
527 | } | |
528 | } | |
529 | ||
1da177e4 LT |
530 | /** |
531 | * msix_capability_init - configure device's MSI-X capability | |
532 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
533 | * @entries: pointer to an array of struct msix_entry entries |
534 | * @nvec: number of @entries | |
1da177e4 | 535 | * |
eaae4b3a | 536 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
537 | * single MSI-X irq. A return of zero indicates the successful setup of |
538 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
539 | **/ |
540 | static int msix_capability_init(struct pci_dev *dev, | |
541 | struct msix_entry *entries, int nvec) | |
542 | { | |
d9d7070e | 543 | int pos, ret; |
5a05a9d8 | 544 | u16 control; |
1da177e4 LT |
545 | void __iomem *base; |
546 | ||
500559a9 | 547 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
f598282f MW |
548 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
549 | ||
550 | /* Ensure MSI-X is disabled while it is set up */ | |
551 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
552 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
553 | ||
1da177e4 | 554 | /* Request & Map MSI-X table region */ |
5a05a9d8 HS |
555 | base = msix_map_region(dev, pos, multi_msix_capable(control)); |
556 | if (!base) | |
1da177e4 LT |
557 | return -ENOMEM; |
558 | ||
d9d7070e HS |
559 | ret = msix_setup_entries(dev, pos, base, entries, nvec); |
560 | if (ret) | |
561 | return ret; | |
9c831334 ME |
562 | |
563 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
564 | if (ret) |
565 | goto error; | |
9c831334 | 566 | |
f598282f MW |
567 | /* |
568 | * Some devices require MSI-X to be enabled before we can touch the | |
569 | * MSI-X registers. We need to mask all the vectors to prevent | |
570 | * interrupts coming in before they're fully set up. | |
571 | */ | |
572 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
573 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
574 | ||
75cb3426 | 575 | msix_program_entries(dev, entries); |
f598282f MW |
576 | |
577 | /* Set MSI-X enabled bits and unmask the function */ | |
ba698ad4 | 578 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 579 | dev->msix_enabled = 1; |
1da177e4 | 580 | |
f598282f MW |
581 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
582 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 583 | |
1da177e4 | 584 | return 0; |
583871d4 HS |
585 | |
586 | error: | |
587 | if (ret < 0) { | |
588 | /* | |
589 | * If we had some success, report the number of irqs | |
590 | * we succeeded in setting up. | |
591 | */ | |
d9d7070e | 592 | struct msi_desc *entry; |
583871d4 HS |
593 | int avail = 0; |
594 | ||
595 | list_for_each_entry(entry, &dev->msi_list, list) { | |
596 | if (entry->irq != 0) | |
597 | avail++; | |
598 | } | |
599 | if (avail != 0) | |
600 | ret = avail; | |
601 | } | |
602 | ||
603 | free_msi_irqs(dev); | |
604 | ||
605 | return ret; | |
1da177e4 LT |
606 | } |
607 | ||
24334a12 | 608 | /** |
17bbc12a | 609 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 610 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 611 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 612 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 613 | * |
0306ebfa | 614 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
615 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
616 | * supported return 0, else return an error code. | |
24334a12 | 617 | **/ |
500559a9 | 618 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
619 | { |
620 | struct pci_bus *bus; | |
c9953a73 | 621 | int ret; |
24334a12 | 622 | |
0306ebfa | 623 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
624 | if (!pci_msi_enable || !dev || dev->no_msi) |
625 | return -EINVAL; | |
626 | ||
314e77b3 ME |
627 | /* |
628 | * You can't ask to have 0 or less MSIs configured. | |
629 | * a) it's stupid .. | |
630 | * b) the list manipulation code assumes nvec >= 1. | |
631 | */ | |
632 | if (nvec < 1) | |
633 | return -ERANGE; | |
634 | ||
500559a9 HS |
635 | /* |
636 | * Any bridge which does NOT route MSI transactions from its | |
637 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
638 | * the secondary pci_bus. |
639 | * We expect only arch-specific PCI host bus controller driver | |
640 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
641 | */ | |
24334a12 BG |
642 | for (bus = dev->bus; bus; bus = bus->parent) |
643 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
644 | return -EINVAL; | |
645 | ||
c9953a73 ME |
646 | ret = arch_msi_check_device(dev, nvec, type); |
647 | if (ret) | |
648 | return ret; | |
649 | ||
b1e2303d ME |
650 | if (!pci_find_capability(dev, type)) |
651 | return -EINVAL; | |
652 | ||
24334a12 BG |
653 | return 0; |
654 | } | |
655 | ||
1da177e4 | 656 | /** |
1c8d7b0a MW |
657 | * pci_enable_msi_block - configure device's MSI capability structure |
658 | * @dev: device to configure | |
659 | * @nvec: number of interrupts to configure | |
1da177e4 | 660 | * |
1c8d7b0a MW |
661 | * Allocate IRQs for a device with the MSI capability. |
662 | * This function returns a negative errno if an error occurs. If it | |
663 | * is unable to allocate the number of interrupts requested, it returns | |
664 | * the number of interrupts it might be able to allocate. If it successfully | |
665 | * allocates at least the number of interrupts requested, it returns 0 and | |
666 | * updates the @dev's irq member to the lowest new interrupt number; the | |
667 | * other interrupt numbers allocated to this device are consecutive. | |
668 | */ | |
669 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 670 | { |
1c8d7b0a MW |
671 | int status, pos, maxvec; |
672 | u16 msgctl; | |
673 | ||
674 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
675 | if (!pos) | |
676 | return -EINVAL; | |
677 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
678 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
679 | if (nvec > maxvec) | |
680 | return maxvec; | |
1da177e4 | 681 | |
1c8d7b0a | 682 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
683 | if (status) |
684 | return status; | |
1da177e4 | 685 | |
ded86d8d | 686 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 687 | |
1c8d7b0a | 688 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 689 | if (dev->msix_enabled) { |
80ccba11 BH |
690 | dev_info(&dev->dev, "can't enable MSI " |
691 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 692 | return -EINVAL; |
1da177e4 | 693 | } |
1c8d7b0a MW |
694 | |
695 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
696 | return status; |
697 | } | |
1c8d7b0a | 698 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 699 | |
f2440d9a | 700 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 701 | { |
f2440d9a MW |
702 | struct msi_desc *desc; |
703 | u32 mask; | |
704 | u16 ctrl; | |
110828c9 | 705 | unsigned pos; |
1da177e4 | 706 | |
128bc5fc | 707 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
708 | return; |
709 | ||
110828c9 MW |
710 | BUG_ON(list_empty(&dev->msi_list)); |
711 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
712 | pos = desc->msi_attrib.pos; | |
713 | ||
714 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 715 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 716 | dev->msi_enabled = 0; |
7bd007e4 | 717 | |
12abb8ba | 718 | /* Return the device with MSI unmasked as initial states */ |
110828c9 | 719 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 720 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
721 | /* Keep cached state to be restored */ |
722 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
723 | |
724 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 725 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 726 | } |
24d27553 | 727 | |
500559a9 | 728 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 729 | { |
d52877c7 YL |
730 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
731 | return; | |
732 | ||
733 | pci_msi_shutdown(dev); | |
f56e4481 | 734 | free_msi_irqs(dev); |
1da177e4 | 735 | } |
4cc086fa | 736 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 737 | |
a52e2e35 RW |
738 | /** |
739 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
740 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
741 | */ | |
742 | int pci_msix_table_size(struct pci_dev *dev) | |
743 | { | |
744 | int pos; | |
745 | u16 control; | |
746 | ||
747 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
748 | if (!pos) | |
749 | return 0; | |
750 | ||
751 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
752 | return multi_msix_capable(control); | |
753 | } | |
754 | ||
1da177e4 LT |
755 | /** |
756 | * pci_enable_msix - configure device's MSI-X capability structure | |
757 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 758 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 759 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
760 | * |
761 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 762 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
763 | * MSI-X mode enabled on its hardware device function. A return of zero |
764 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 765 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 766 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
767 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
768 | * re-send its request. | |
1da177e4 | 769 | **/ |
500559a9 | 770 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 771 | { |
a52e2e35 | 772 | int status, nr_entries; |
ded86d8d | 773 | int i, j; |
1da177e4 | 774 | |
c9953a73 | 775 | if (!entries) |
500559a9 | 776 | return -EINVAL; |
1da177e4 | 777 | |
c9953a73 ME |
778 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
779 | if (status) | |
780 | return status; | |
781 | ||
a52e2e35 | 782 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 783 | if (nvec > nr_entries) |
57fbf52c | 784 | return nr_entries; |
1da177e4 LT |
785 | |
786 | /* Check for any invalid entries */ | |
787 | for (i = 0; i < nvec; i++) { | |
788 | if (entries[i].entry >= nr_entries) | |
789 | return -EINVAL; /* invalid entry */ | |
790 | for (j = i + 1; j < nvec; j++) { | |
791 | if (entries[i].entry == entries[j].entry) | |
792 | return -EINVAL; /* duplicate entry */ | |
793 | } | |
794 | } | |
ded86d8d | 795 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 796 | |
1ce03373 | 797 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 798 | if (dev->msi_enabled) { |
80ccba11 BH |
799 | dev_info(&dev->dev, "can't enable MSI-X " |
800 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
801 | return -EINVAL; |
802 | } | |
1da177e4 | 803 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
804 | return status; |
805 | } | |
4cc086fa | 806 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 807 | |
500559a9 | 808 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 809 | { |
12abb8ba HS |
810 | struct msi_desc *entry; |
811 | ||
128bc5fc | 812 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
813 | return; |
814 | ||
12abb8ba HS |
815 | /* Return the device with MSI-X masked as initial states */ |
816 | list_for_each_entry(entry, &dev->msi_list, list) { | |
817 | /* Keep cached states to be restored */ | |
818 | __msix_mask_irq(entry, 1); | |
819 | } | |
820 | ||
b1cbf4e4 | 821 | msix_set_enable(dev, 0); |
ba698ad4 | 822 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 823 | dev->msix_enabled = 0; |
d52877c7 | 824 | } |
c901851f | 825 | |
500559a9 | 826 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
827 | { |
828 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
829 | return; | |
830 | ||
831 | pci_msix_shutdown(dev); | |
f56e4481 | 832 | free_msi_irqs(dev); |
1da177e4 | 833 | } |
4cc086fa | 834 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
835 | |
836 | /** | |
1ce03373 | 837 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
838 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
839 | * | |
eaae4b3a | 840 | * Being called during hotplug remove, from which the device function |
1ce03373 | 841 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
842 | * allocated for this device function, are reclaimed to unused state, |
843 | * which may be used later on. | |
844 | **/ | |
500559a9 | 845 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 846 | { |
1da177e4 | 847 | if (!pci_msi_enable || !dev) |
500559a9 | 848 | return; |
1da177e4 | 849 | |
f56e4481 HS |
850 | if (dev->msi_enabled || dev->msix_enabled) |
851 | free_msi_irqs(dev); | |
1da177e4 LT |
852 | } |
853 | ||
309e57df MW |
854 | void pci_no_msi(void) |
855 | { | |
856 | pci_msi_enable = 0; | |
857 | } | |
c9953a73 | 858 | |
07ae95f9 AP |
859 | /** |
860 | * pci_msi_enabled - is MSI enabled? | |
861 | * | |
862 | * Returns true if MSI has not been disabled by the command-line option | |
863 | * pci=nomsi. | |
864 | **/ | |
865 | int pci_msi_enabled(void) | |
d389fec6 | 866 | { |
07ae95f9 | 867 | return pci_msi_enable; |
d389fec6 | 868 | } |
07ae95f9 | 869 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 870 | |
07ae95f9 | 871 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 872 | { |
07ae95f9 | 873 | INIT_LIST_HEAD(&dev->msi_list); |
d389fec6 | 874 | } |