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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
363c75db | 13 | #include <linux/export.h> |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
500559a9 HS |
19 | #include <linux/errno.h> |
20 | #include <linux/io.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
3878eaef | 22 | #include <linux/irqdomain.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
1da177e4 | 25 | |
1da177e4 | 26 | static int pci_msi_enable = 1; |
38737d82 | 27 | int pci_msi_ignore_mask; |
1da177e4 | 28 | |
527eee29 BH |
29 | #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) |
30 | ||
8e047ada JL |
31 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
32 | static struct irq_domain *pci_msi_default_domain; | |
33 | static DEFINE_MUTEX(pci_msi_domain_lock); | |
34 | ||
35 | struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev) | |
36 | { | |
37 | return pci_msi_default_domain; | |
38 | } | |
39 | ||
020c3126 MZ |
40 | static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev) |
41 | { | |
42 | struct irq_domain *domain = NULL; | |
43 | ||
44 | if (dev->bus->msi) | |
45 | domain = dev->bus->msi->domain; | |
46 | if (!domain) | |
47 | domain = arch_get_pci_msi_domain(dev); | |
48 | ||
49 | return domain; | |
50 | } | |
51 | ||
8e047ada JL |
52 | static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
53 | { | |
54 | struct irq_domain *domain; | |
55 | ||
020c3126 | 56 | domain = pci_msi_get_domain(dev); |
8e047ada JL |
57 | if (domain) |
58 | return pci_msi_domain_alloc_irqs(domain, dev, nvec, type); | |
59 | ||
60 | return arch_setup_msi_irqs(dev, nvec, type); | |
61 | } | |
62 | ||
63 | static void pci_msi_teardown_msi_irqs(struct pci_dev *dev) | |
64 | { | |
65 | struct irq_domain *domain; | |
66 | ||
020c3126 | 67 | domain = pci_msi_get_domain(dev); |
8e047ada JL |
68 | if (domain) |
69 | pci_msi_domain_free_irqs(domain, dev); | |
70 | else | |
71 | arch_teardown_msi_irqs(dev); | |
72 | } | |
73 | #else | |
74 | #define pci_msi_setup_msi_irqs arch_setup_msi_irqs | |
75 | #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs | |
76 | #endif | |
527eee29 | 77 | |
6a9e7f20 AB |
78 | /* Arch hooks */ |
79 | ||
262a2baf YW |
80 | struct msi_controller * __weak pcibios_msi_controller(struct pci_dev *dev) |
81 | { | |
82 | return NULL; | |
83 | } | |
84 | ||
85 | static struct msi_controller *pci_msi_controller(struct pci_dev *dev) | |
86 | { | |
87 | struct msi_controller *msi_ctrl = dev->bus->msi; | |
88 | ||
89 | if (msi_ctrl) | |
90 | return msi_ctrl; | |
91 | ||
92 | return pcibios_msi_controller(dev); | |
93 | } | |
94 | ||
4287d824 TP |
95 | int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
96 | { | |
262a2baf | 97 | struct msi_controller *chip = pci_msi_controller(dev); |
0cbdcfcf TR |
98 | int err; |
99 | ||
100 | if (!chip || !chip->setup_irq) | |
101 | return -EINVAL; | |
102 | ||
103 | err = chip->setup_irq(chip, dev, desc); | |
104 | if (err < 0) | |
105 | return err; | |
106 | ||
107 | irq_set_chip_data(desc->irq, chip); | |
108 | ||
109 | return 0; | |
4287d824 TP |
110 | } |
111 | ||
112 | void __weak arch_teardown_msi_irq(unsigned int irq) | |
6a9e7f20 | 113 | { |
c2791b80 | 114 | struct msi_controller *chip = irq_get_chip_data(irq); |
0cbdcfcf TR |
115 | |
116 | if (!chip || !chip->teardown_irq) | |
117 | return; | |
118 | ||
119 | chip->teardown_irq(chip, irq); | |
6a9e7f20 AB |
120 | } |
121 | ||
4287d824 | 122 | int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
6a9e7f20 AB |
123 | { |
124 | struct msi_desc *entry; | |
125 | int ret; | |
126 | ||
1c8d7b0a MW |
127 | /* |
128 | * If an architecture wants to support multiple MSI, it needs to | |
129 | * override arch_setup_msi_irqs() | |
130 | */ | |
131 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
132 | return 1; | |
133 | ||
6a9e7f20 AB |
134 | list_for_each_entry(entry, &dev->msi_list, list) { |
135 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 136 | if (ret < 0) |
6a9e7f20 | 137 | return ret; |
b5fbf533 ME |
138 | if (ret > 0) |
139 | return -ENOSPC; | |
6a9e7f20 AB |
140 | } |
141 | ||
142 | return 0; | |
143 | } | |
1525bf0d | 144 | |
4287d824 TP |
145 | /* |
146 | * We have a default implementation available as a separate non-weak | |
147 | * function, as it is used by the Xen x86 PCI code | |
148 | */ | |
1525bf0d | 149 | void default_teardown_msi_irqs(struct pci_dev *dev) |
6a9e7f20 | 150 | { |
63a7b17e | 151 | int i; |
6a9e7f20 AB |
152 | struct msi_desc *entry; |
153 | ||
63a7b17e JL |
154 | list_for_each_entry(entry, &dev->msi_list, list) |
155 | if (entry->irq) | |
156 | for (i = 0; i < entry->nvec_used; i++) | |
157 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
158 | } |
159 | ||
4287d824 TP |
160 | void __weak arch_teardown_msi_irqs(struct pci_dev *dev) |
161 | { | |
162 | return default_teardown_msi_irqs(dev); | |
163 | } | |
76ccc297 | 164 | |
ac8344c4 | 165 | static void default_restore_msi_irq(struct pci_dev *dev, int irq) |
76ccc297 KRW |
166 | { |
167 | struct msi_desc *entry; | |
168 | ||
169 | entry = NULL; | |
170 | if (dev->msix_enabled) { | |
171 | list_for_each_entry(entry, &dev->msi_list, list) { | |
172 | if (irq == entry->irq) | |
173 | break; | |
174 | } | |
175 | } else if (dev->msi_enabled) { | |
176 | entry = irq_get_msi_desc(irq); | |
177 | } | |
178 | ||
179 | if (entry) | |
83a18912 | 180 | __pci_write_msi_msg(entry, &entry->msg); |
76ccc297 | 181 | } |
4287d824 | 182 | |
ac8344c4 | 183 | void __weak arch_restore_msi_irqs(struct pci_dev *dev) |
4287d824 | 184 | { |
ac8344c4 | 185 | return default_restore_msi_irqs(dev); |
4287d824 | 186 | } |
76ccc297 | 187 | |
e375b561 | 188 | static void msi_set_enable(struct pci_dev *dev, int enable) |
b1cbf4e4 | 189 | { |
b1cbf4e4 EB |
190 | u16 control; |
191 | ||
e375b561 | 192 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
110828c9 MW |
193 | control &= ~PCI_MSI_FLAGS_ENABLE; |
194 | if (enable) | |
195 | control |= PCI_MSI_FLAGS_ENABLE; | |
e375b561 | 196 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
5ca5c02f HS |
197 | } |
198 | ||
66f0d0c4 | 199 | static void msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) |
b1cbf4e4 | 200 | { |
66f0d0c4 | 201 | u16 ctrl; |
b1cbf4e4 | 202 | |
66f0d0c4 YW |
203 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); |
204 | ctrl &= ~clear; | |
205 | ctrl |= set; | |
206 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
b1cbf4e4 EB |
207 | } |
208 | ||
bffac3c5 MW |
209 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
210 | { | |
0b49ec37 MW |
211 | /* Don't shift by >= width of type */ |
212 | if (x >= 5) | |
213 | return 0xffffffff; | |
214 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
215 | } |
216 | ||
ce6fce42 MW |
217 | /* |
218 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
219 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
220 | * reliably as devices without an INTx disable bit will then generate a | |
221 | * level IRQ which will never be cleared. | |
ce6fce42 | 222 | */ |
23ed8d57 | 223 | u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 224 | { |
f2440d9a | 225 | u32 mask_bits = desc->masked; |
1da177e4 | 226 | |
38737d82 | 227 | if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit) |
12abb8ba | 228 | return 0; |
f2440d9a MW |
229 | |
230 | mask_bits &= ~mask; | |
231 | mask_bits |= flag; | |
232 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
233 | |
234 | return mask_bits; | |
235 | } | |
236 | ||
237 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
238 | { | |
23ed8d57 | 239 | desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag); |
f2440d9a MW |
240 | } |
241 | ||
242 | /* | |
243 | * This internal function does not flush PCI writes to the device. | |
244 | * All users must ensure that they read from the device before either | |
245 | * assuming that the device state is up to date, or returning out of this | |
246 | * file. This saves a few milliseconds when initialising devices with lots | |
247 | * of MSI-X interrupts. | |
248 | */ | |
23ed8d57 | 249 | u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
250 | { |
251 | u32 mask_bits = desc->masked; | |
252 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 253 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
38737d82 YW |
254 | |
255 | if (pci_msi_ignore_mask) | |
256 | return 0; | |
257 | ||
8d805286 SY |
258 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
259 | if (flag) | |
260 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 261 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
262 | |
263 | return mask_bits; | |
264 | } | |
265 | ||
266 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
267 | { | |
23ed8d57 | 268 | desc->masked = __pci_msix_desc_mask_irq(desc, flag); |
f2440d9a | 269 | } |
24d27553 | 270 | |
1c9db525 | 271 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 272 | { |
1c9db525 | 273 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 274 | |
f2440d9a MW |
275 | if (desc->msi_attrib.is_msix) { |
276 | msix_mask_irq(desc, flag); | |
277 | readl(desc->mask_base); /* Flush write to device */ | |
278 | } else { | |
a281b788 | 279 | unsigned offset = data->irq - desc->irq; |
1c8d7b0a | 280 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 281 | } |
f2440d9a MW |
282 | } |
283 | ||
23ed8d57 TG |
284 | /** |
285 | * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts | |
286 | * @data: pointer to irqdata associated to that interrupt | |
287 | */ | |
288 | void pci_msi_mask_irq(struct irq_data *data) | |
f2440d9a | 289 | { |
1c9db525 | 290 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
291 | } |
292 | ||
23ed8d57 TG |
293 | /** |
294 | * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts | |
295 | * @data: pointer to irqdata associated to that interrupt | |
296 | */ | |
297 | void pci_msi_unmask_irq(struct irq_data *data) | |
f2440d9a | 298 | { |
1c9db525 | 299 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
300 | } |
301 | ||
ac8344c4 D |
302 | void default_restore_msi_irqs(struct pci_dev *dev) |
303 | { | |
304 | struct msi_desc *entry; | |
305 | ||
3f3cecae | 306 | list_for_each_entry(entry, &dev->msi_list, list) |
ac8344c4 | 307 | default_restore_msi_irq(dev, entry->irq); |
ac8344c4 D |
308 | } |
309 | ||
891d4a48 | 310 | void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 311 | { |
30da5524 BH |
312 | BUG_ON(entry->dev->current_state != PCI_D0); |
313 | ||
314 | if (entry->msi_attrib.is_msix) { | |
315 | void __iomem *base = entry->mask_base + | |
316 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
317 | ||
318 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
319 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
320 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
321 | } else { | |
322 | struct pci_dev *dev = entry->dev; | |
f5322169 | 323 | int pos = dev->msi_cap; |
30da5524 BH |
324 | u16 data; |
325 | ||
9925ad0c BH |
326 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
327 | &msg->address_lo); | |
30da5524 | 328 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
329 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
330 | &msg->address_hi); | |
2f221349 | 331 | pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data); |
30da5524 BH |
332 | } else { |
333 | msg->address_hi = 0; | |
2f221349 | 334 | pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data); |
30da5524 BH |
335 | } |
336 | msg->data = data; | |
337 | } | |
338 | } | |
339 | ||
83a18912 | 340 | void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 341 | { |
fcd097f3 BH |
342 | if (entry->dev->current_state != PCI_D0) { |
343 | /* Don't touch the hardware now */ | |
344 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
345 | void __iomem *base; |
346 | base = entry->mask_base + | |
347 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
348 | ||
2c21fd4b HS |
349 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
350 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
351 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 352 | } else { |
0366f8f7 | 353 | struct pci_dev *dev = entry->dev; |
f5322169 | 354 | int pos = dev->msi_cap; |
1c8d7b0a MW |
355 | u16 msgctl; |
356 | ||
f84ecd28 | 357 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); |
1c8d7b0a MW |
358 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; |
359 | msgctl |= entry->msi_attrib.multiple << 4; | |
f84ecd28 | 360 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl); |
0366f8f7 | 361 | |
9925ad0c BH |
362 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, |
363 | msg->address_lo); | |
0366f8f7 | 364 | if (entry->msi_attrib.is_64) { |
9925ad0c BH |
365 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, |
366 | msg->address_hi); | |
2f221349 BH |
367 | pci_write_config_word(dev, pos + PCI_MSI_DATA_64, |
368 | msg->data); | |
0366f8f7 | 369 | } else { |
2f221349 BH |
370 | pci_write_config_word(dev, pos + PCI_MSI_DATA_32, |
371 | msg->data); | |
0366f8f7 | 372 | } |
1da177e4 | 373 | } |
392ee1e6 | 374 | entry->msg = *msg; |
1da177e4 | 375 | } |
0366f8f7 | 376 | |
83a18912 | 377 | void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) |
3145e941 | 378 | { |
dced35ae | 379 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 380 | |
83a18912 | 381 | __pci_write_msi_msg(entry, msg); |
3145e941 | 382 | } |
83a18912 | 383 | EXPORT_SYMBOL_GPL(pci_write_msi_msg); |
3145e941 | 384 | |
f56e4481 HS |
385 | static void free_msi_irqs(struct pci_dev *dev) |
386 | { | |
387 | struct msi_desc *entry, *tmp; | |
1c51b50c GKH |
388 | struct attribute **msi_attrs; |
389 | struct device_attribute *dev_attr; | |
63a7b17e | 390 | int i, count = 0; |
f56e4481 | 391 | |
63a7b17e JL |
392 | list_for_each_entry(entry, &dev->msi_list, list) |
393 | if (entry->irq) | |
394 | for (i = 0; i < entry->nvec_used; i++) | |
395 | BUG_ON(irq_has_action(entry->irq + i)); | |
f56e4481 | 396 | |
8e047ada | 397 | pci_msi_teardown_msi_irqs(dev); |
f56e4481 HS |
398 | |
399 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
400 | if (entry->msi_attrib.is_msix) { | |
401 | if (list_is_last(&entry->list, &dev->msi_list)) | |
402 | iounmap(entry->mask_base); | |
403 | } | |
424eb391 | 404 | |
f56e4481 HS |
405 | list_del(&entry->list); |
406 | kfree(entry); | |
407 | } | |
1c51b50c GKH |
408 | |
409 | if (dev->msi_irq_groups) { | |
410 | sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups); | |
411 | msi_attrs = dev->msi_irq_groups[0]->attrs; | |
b701c0b1 | 412 | while (msi_attrs[count]) { |
1c51b50c GKH |
413 | dev_attr = container_of(msi_attrs[count], |
414 | struct device_attribute, attr); | |
415 | kfree(dev_attr->attr.name); | |
416 | kfree(dev_attr); | |
417 | ++count; | |
418 | } | |
419 | kfree(msi_attrs); | |
420 | kfree(dev->msi_irq_groups[0]); | |
421 | kfree(dev->msi_irq_groups); | |
422 | dev->msi_irq_groups = NULL; | |
423 | } | |
f56e4481 | 424 | } |
c54c1879 | 425 | |
379f5327 | 426 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 427 | { |
379f5327 MW |
428 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
429 | if (!desc) | |
1da177e4 LT |
430 | return NULL; |
431 | ||
379f5327 MW |
432 | INIT_LIST_HEAD(&desc->list); |
433 | desc->dev = dev; | |
1da177e4 | 434 | |
379f5327 | 435 | return desc; |
1da177e4 LT |
436 | } |
437 | ||
ba698ad4 DM |
438 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
439 | { | |
440 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
441 | pci_intx(dev, enable); | |
442 | } | |
443 | ||
8fed4b65 | 444 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 445 | { |
41017f0c | 446 | u16 control; |
392ee1e6 | 447 | struct msi_desc *entry; |
41017f0c | 448 | |
b1cbf4e4 EB |
449 | if (!dev->msi_enabled) |
450 | return; | |
451 | ||
dced35ae | 452 | entry = irq_get_msi_desc(dev->irq); |
41017f0c | 453 | |
ba698ad4 | 454 | pci_intx_for_msi(dev, 0); |
e375b561 | 455 | msi_set_enable(dev, 0); |
ac8344c4 | 456 | arch_restore_msi_irqs(dev); |
392ee1e6 | 457 | |
f5322169 | 458 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); |
31ea5d4d YW |
459 | msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), |
460 | entry->masked); | |
abad2ec9 | 461 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 462 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
f5322169 | 463 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
464 | } |
465 | ||
466 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 467 | { |
41017f0c | 468 | struct msi_desc *entry; |
41017f0c | 469 | |
ded86d8d EB |
470 | if (!dev->msix_enabled) |
471 | return; | |
f598282f | 472 | BUG_ON(list_empty(&dev->msi_list)); |
ded86d8d | 473 | |
41017f0c | 474 | /* route the table */ |
ba698ad4 | 475 | pci_intx_for_msi(dev, 0); |
66f0d0c4 YW |
476 | msix_clear_and_set_ctrl(dev, 0, |
477 | PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); | |
41017f0c | 478 | |
ac8344c4 | 479 | arch_restore_msi_irqs(dev); |
3f3cecae | 480 | list_for_each_entry(entry, &dev->msi_list, list) |
f2440d9a | 481 | msix_mask_irq(entry, entry->masked); |
41017f0c | 482 | |
66f0d0c4 | 483 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
41017f0c | 484 | } |
8fed4b65 ME |
485 | |
486 | void pci_restore_msi_state(struct pci_dev *dev) | |
487 | { | |
488 | __pci_restore_msi_state(dev); | |
489 | __pci_restore_msix_state(dev); | |
490 | } | |
94688cf2 | 491 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 492 | |
1c51b50c | 493 | static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr, |
da8d1c8b NH |
494 | char *buf) |
495 | { | |
1c51b50c GKH |
496 | struct msi_desc *entry; |
497 | unsigned long irq; | |
498 | int retval; | |
da8d1c8b | 499 | |
1c51b50c GKH |
500 | retval = kstrtoul(attr->attr.name, 10, &irq); |
501 | if (retval) | |
502 | return retval; | |
da8d1c8b | 503 | |
e11ece5a YW |
504 | entry = irq_get_msi_desc(irq); |
505 | if (entry) | |
506 | return sprintf(buf, "%s\n", | |
507 | entry->msi_attrib.is_msix ? "msix" : "msi"); | |
508 | ||
1c51b50c | 509 | return -ENODEV; |
da8d1c8b NH |
510 | } |
511 | ||
da8d1c8b NH |
512 | static int populate_msi_sysfs(struct pci_dev *pdev) |
513 | { | |
1c51b50c GKH |
514 | struct attribute **msi_attrs; |
515 | struct attribute *msi_attr; | |
516 | struct device_attribute *msi_dev_attr; | |
517 | struct attribute_group *msi_irq_group; | |
518 | const struct attribute_group **msi_irq_groups; | |
da8d1c8b | 519 | struct msi_desc *entry; |
1c51b50c GKH |
520 | int ret = -ENOMEM; |
521 | int num_msi = 0; | |
da8d1c8b NH |
522 | int count = 0; |
523 | ||
1c51b50c | 524 | /* Determine how many msi entries we have */ |
3f3cecae | 525 | list_for_each_entry(entry, &pdev->msi_list, list) |
1c51b50c | 526 | ++num_msi; |
1c51b50c GKH |
527 | if (!num_msi) |
528 | return 0; | |
da8d1c8b | 529 | |
1c51b50c GKH |
530 | /* Dynamically create the MSI attributes for the PCI device */ |
531 | msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL); | |
532 | if (!msi_attrs) | |
533 | return -ENOMEM; | |
da8d1c8b | 534 | list_for_each_entry(entry, &pdev->msi_list, list) { |
1c51b50c | 535 | msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL); |
1406276c | 536 | if (!msi_dev_attr) |
1c51b50c | 537 | goto error_attrs; |
1406276c | 538 | msi_attrs[count] = &msi_dev_attr->attr; |
86bb4f69 | 539 | |
1c51b50c | 540 | sysfs_attr_init(&msi_dev_attr->attr); |
1406276c JB |
541 | msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d", |
542 | entry->irq); | |
543 | if (!msi_dev_attr->attr.name) | |
544 | goto error_attrs; | |
1c51b50c GKH |
545 | msi_dev_attr->attr.mode = S_IRUGO; |
546 | msi_dev_attr->show = msi_mode_show; | |
1c51b50c | 547 | ++count; |
da8d1c8b NH |
548 | } |
549 | ||
1c51b50c GKH |
550 | msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL); |
551 | if (!msi_irq_group) | |
552 | goto error_attrs; | |
553 | msi_irq_group->name = "msi_irqs"; | |
554 | msi_irq_group->attrs = msi_attrs; | |
555 | ||
556 | msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL); | |
557 | if (!msi_irq_groups) | |
558 | goto error_irq_group; | |
559 | msi_irq_groups[0] = msi_irq_group; | |
560 | ||
561 | ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups); | |
562 | if (ret) | |
563 | goto error_irq_groups; | |
564 | pdev->msi_irq_groups = msi_irq_groups; | |
565 | ||
da8d1c8b NH |
566 | return 0; |
567 | ||
1c51b50c GKH |
568 | error_irq_groups: |
569 | kfree(msi_irq_groups); | |
570 | error_irq_group: | |
571 | kfree(msi_irq_group); | |
572 | error_attrs: | |
573 | count = 0; | |
574 | msi_attr = msi_attrs[count]; | |
575 | while (msi_attr) { | |
576 | msi_dev_attr = container_of(msi_attr, struct device_attribute, attr); | |
577 | kfree(msi_attr->name); | |
578 | kfree(msi_dev_attr); | |
579 | ++count; | |
580 | msi_attr = msi_attrs[count]; | |
da8d1c8b | 581 | } |
29237756 | 582 | kfree(msi_attrs); |
da8d1c8b NH |
583 | return ret; |
584 | } | |
585 | ||
63a7b17e | 586 | static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec) |
d873b4d4 YW |
587 | { |
588 | u16 control; | |
589 | struct msi_desc *entry; | |
590 | ||
591 | /* MSI Entry Initialization */ | |
592 | entry = alloc_msi_entry(dev); | |
593 | if (!entry) | |
594 | return NULL; | |
595 | ||
596 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
597 | ||
598 | entry->msi_attrib.is_msix = 0; | |
599 | entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT); | |
600 | entry->msi_attrib.entry_nr = 0; | |
601 | entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT); | |
602 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
d873b4d4 | 603 | entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1; |
63a7b17e JL |
604 | entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec)); |
605 | entry->nvec_used = nvec; | |
d873b4d4 YW |
606 | |
607 | if (control & PCI_MSI_FLAGS_64BIT) | |
608 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64; | |
609 | else | |
610 | entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32; | |
611 | ||
612 | /* Save the initial mask status */ | |
613 | if (entry->msi_attrib.maskbit) | |
614 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
615 | ||
616 | return entry; | |
617 | } | |
618 | ||
f144d149 BH |
619 | static int msi_verify_entries(struct pci_dev *dev) |
620 | { | |
621 | struct msi_desc *entry; | |
622 | ||
623 | list_for_each_entry(entry, &dev->msi_list, list) { | |
624 | if (!dev->no_64bit_msi || !entry->msg.address_hi) | |
625 | continue; | |
626 | dev_err(&dev->dev, "Device has broken 64-bit MSI but arch" | |
627 | " tried to assign one above 4G\n"); | |
628 | return -EIO; | |
629 | } | |
630 | return 0; | |
631 | } | |
632 | ||
1da177e4 LT |
633 | /** |
634 | * msi_capability_init - configure device's MSI capability structure | |
635 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 636 | * @nvec: number of interrupts to allocate |
1da177e4 | 637 | * |
1c8d7b0a MW |
638 | * Setup the MSI capability structure of the device with the requested |
639 | * number of interrupts. A return value of zero indicates the successful | |
640 | * setup of an entry with the new MSI irq. A negative return value indicates | |
641 | * an error, and a positive return value indicates the number of interrupts | |
642 | * which could have been allocated. | |
643 | */ | |
644 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
645 | { |
646 | struct msi_desc *entry; | |
f465136d | 647 | int ret; |
f2440d9a | 648 | unsigned mask; |
1da177e4 | 649 | |
e375b561 | 650 | msi_set_enable(dev, 0); /* Disable MSI during set up */ |
110828c9 | 651 | |
63a7b17e | 652 | entry = msi_setup_entry(dev, nvec); |
f7feaca7 EB |
653 | if (!entry) |
654 | return -ENOMEM; | |
1ce03373 | 655 | |
f2440d9a | 656 | /* All MSIs are unmasked by default, Mask them all */ |
31ea5d4d | 657 | mask = msi_mask(entry->msi_attrib.multi_cap); |
f2440d9a MW |
658 | msi_mask_irq(entry, mask, mask); |
659 | ||
0dd11f9b | 660 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 661 | |
1da177e4 | 662 | /* Configure MSI capability structure */ |
8e047ada | 663 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 664 | if (ret) { |
7ba1930d | 665 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 666 | free_msi_irqs(dev); |
7fe3730d | 667 | return ret; |
fd58e55f | 668 | } |
f7feaca7 | 669 | |
f144d149 BH |
670 | ret = msi_verify_entries(dev); |
671 | if (ret) { | |
672 | msi_mask_irq(entry, mask, ~mask); | |
673 | free_msi_irqs(dev); | |
674 | return ret; | |
675 | } | |
676 | ||
da8d1c8b NH |
677 | ret = populate_msi_sysfs(dev); |
678 | if (ret) { | |
679 | msi_mask_irq(entry, mask, ~mask); | |
680 | free_msi_irqs(dev); | |
681 | return ret; | |
682 | } | |
683 | ||
1da177e4 | 684 | /* Set MSI enabled bits */ |
ba698ad4 | 685 | pci_intx_for_msi(dev, 0); |
e375b561 | 686 | msi_set_enable(dev, 1); |
b1cbf4e4 | 687 | dev->msi_enabled = 1; |
1da177e4 | 688 | |
7fe3730d | 689 | dev->irq = entry->irq; |
1da177e4 LT |
690 | return 0; |
691 | } | |
692 | ||
520fe9dc | 693 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries) |
5a05a9d8 | 694 | { |
4302e0fb | 695 | resource_size_t phys_addr; |
5a05a9d8 HS |
696 | u32 table_offset; |
697 | u8 bir; | |
698 | ||
909094c6 BH |
699 | pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE, |
700 | &table_offset); | |
4d18760c BH |
701 | bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); |
702 | table_offset &= PCI_MSIX_TABLE_OFFSET; | |
5a05a9d8 HS |
703 | phys_addr = pci_resource_start(dev, bir) + table_offset; |
704 | ||
705 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
706 | } | |
707 | ||
520fe9dc GS |
708 | static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, |
709 | struct msix_entry *entries, int nvec) | |
d9d7070e HS |
710 | { |
711 | struct msi_desc *entry; | |
712 | int i; | |
713 | ||
714 | for (i = 0; i < nvec; i++) { | |
715 | entry = alloc_msi_entry(dev); | |
716 | if (!entry) { | |
717 | if (!i) | |
718 | iounmap(base); | |
719 | else | |
720 | free_msi_irqs(dev); | |
721 | /* No enough memory. Don't try again */ | |
722 | return -ENOMEM; | |
723 | } | |
724 | ||
725 | entry->msi_attrib.is_msix = 1; | |
726 | entry->msi_attrib.is_64 = 1; | |
727 | entry->msi_attrib.entry_nr = entries[i].entry; | |
728 | entry->msi_attrib.default_irq = dev->irq; | |
d9d7070e | 729 | entry->mask_base = base; |
63a7b17e | 730 | entry->nvec_used = 1; |
d9d7070e HS |
731 | |
732 | list_add_tail(&entry->list, &dev->msi_list); | |
733 | } | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
75cb3426 | 738 | static void msix_program_entries(struct pci_dev *dev, |
520fe9dc | 739 | struct msix_entry *entries) |
75cb3426 HS |
740 | { |
741 | struct msi_desc *entry; | |
742 | int i = 0; | |
743 | ||
744 | list_for_each_entry(entry, &dev->msi_list, list) { | |
745 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
746 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
747 | ||
748 | entries[i].vector = entry->irq; | |
75cb3426 HS |
749 | entry->masked = readl(entry->mask_base + offset); |
750 | msix_mask_irq(entry, 1); | |
751 | i++; | |
752 | } | |
753 | } | |
754 | ||
1da177e4 LT |
755 | /** |
756 | * msix_capability_init - configure device's MSI-X capability | |
757 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
758 | * @entries: pointer to an array of struct msix_entry entries |
759 | * @nvec: number of @entries | |
1da177e4 | 760 | * |
eaae4b3a | 761 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
762 | * single MSI-X irq. A return of zero indicates the successful setup of |
763 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
764 | **/ |
765 | static int msix_capability_init(struct pci_dev *dev, | |
766 | struct msix_entry *entries, int nvec) | |
767 | { | |
520fe9dc | 768 | int ret; |
5a05a9d8 | 769 | u16 control; |
1da177e4 LT |
770 | void __iomem *base; |
771 | ||
f598282f | 772 | /* Ensure MSI-X is disabled while it is set up */ |
66f0d0c4 | 773 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
f598282f | 774 | |
66f0d0c4 | 775 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
1da177e4 | 776 | /* Request & Map MSI-X table region */ |
527eee29 | 777 | base = msix_map_region(dev, msix_table_size(control)); |
5a05a9d8 | 778 | if (!base) |
1da177e4 LT |
779 | return -ENOMEM; |
780 | ||
520fe9dc | 781 | ret = msix_setup_entries(dev, base, entries, nvec); |
d9d7070e HS |
782 | if (ret) |
783 | return ret; | |
9c831334 | 784 | |
8e047ada | 785 | ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); |
583871d4 | 786 | if (ret) |
2adc7907 | 787 | goto out_avail; |
9c831334 | 788 | |
f144d149 BH |
789 | /* Check if all MSI entries honor device restrictions */ |
790 | ret = msi_verify_entries(dev); | |
791 | if (ret) | |
792 | goto out_free; | |
793 | ||
f598282f MW |
794 | /* |
795 | * Some devices require MSI-X to be enabled before we can touch the | |
796 | * MSI-X registers. We need to mask all the vectors to prevent | |
797 | * interrupts coming in before they're fully set up. | |
798 | */ | |
66f0d0c4 YW |
799 | msix_clear_and_set_ctrl(dev, 0, |
800 | PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE); | |
f598282f | 801 | |
75cb3426 | 802 | msix_program_entries(dev, entries); |
f598282f | 803 | |
da8d1c8b | 804 | ret = populate_msi_sysfs(dev); |
2adc7907 AG |
805 | if (ret) |
806 | goto out_free; | |
da8d1c8b | 807 | |
f598282f | 808 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 809 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 810 | dev->msix_enabled = 1; |
1da177e4 | 811 | |
66f0d0c4 | 812 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); |
8d181018 | 813 | |
1da177e4 | 814 | return 0; |
583871d4 | 815 | |
2adc7907 | 816 | out_avail: |
583871d4 HS |
817 | if (ret < 0) { |
818 | /* | |
819 | * If we had some success, report the number of irqs | |
820 | * we succeeded in setting up. | |
821 | */ | |
d9d7070e | 822 | struct msi_desc *entry; |
583871d4 HS |
823 | int avail = 0; |
824 | ||
825 | list_for_each_entry(entry, &dev->msi_list, list) { | |
826 | if (entry->irq != 0) | |
827 | avail++; | |
828 | } | |
829 | if (avail != 0) | |
830 | ret = avail; | |
831 | } | |
832 | ||
2adc7907 | 833 | out_free: |
583871d4 HS |
834 | free_msi_irqs(dev); |
835 | ||
836 | return ret; | |
1da177e4 LT |
837 | } |
838 | ||
24334a12 | 839 | /** |
a06cd74c | 840 | * pci_msi_supported - check whether MSI may be enabled on a device |
24334a12 | 841 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 842 | * @nvec: how many MSIs have been requested ? |
24334a12 | 843 | * |
f7625980 | 844 | * Look at global flags, the device itself, and its parent buses |
17bbc12a | 845 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
a06cd74c | 846 | * supported return 1, else return 0. |
24334a12 | 847 | **/ |
a06cd74c | 848 | static int pci_msi_supported(struct pci_dev *dev, int nvec) |
24334a12 BG |
849 | { |
850 | struct pci_bus *bus; | |
851 | ||
0306ebfa | 852 | /* MSI must be globally enabled and supported by the device */ |
27e20603 | 853 | if (!pci_msi_enable) |
a06cd74c | 854 | return 0; |
27e20603 AG |
855 | |
856 | if (!dev || dev->no_msi || dev->current_state != PCI_D0) | |
a06cd74c | 857 | return 0; |
24334a12 | 858 | |
314e77b3 ME |
859 | /* |
860 | * You can't ask to have 0 or less MSIs configured. | |
861 | * a) it's stupid .. | |
862 | * b) the list manipulation code assumes nvec >= 1. | |
863 | */ | |
864 | if (nvec < 1) | |
a06cd74c | 865 | return 0; |
314e77b3 | 866 | |
500559a9 HS |
867 | /* |
868 | * Any bridge which does NOT route MSI transactions from its | |
869 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
870 | * the secondary pci_bus. |
871 | * We expect only arch-specific PCI host bus controller driver | |
872 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
873 | */ | |
24334a12 BG |
874 | for (bus = dev->bus; bus; bus = bus->parent) |
875 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
a06cd74c | 876 | return 0; |
24334a12 | 877 | |
a06cd74c | 878 | return 1; |
24334a12 BG |
879 | } |
880 | ||
d1ac1d26 AG |
881 | /** |
882 | * pci_msi_vec_count - Return the number of MSI vectors a device can send | |
883 | * @dev: device to report about | |
884 | * | |
885 | * This function returns the number of MSI vectors a device requested via | |
886 | * Multiple Message Capable register. It returns a negative errno if the | |
887 | * device is not capable sending MSI interrupts. Otherwise, the call succeeds | |
888 | * and returns a power of two, up to a maximum of 2^5 (32), according to the | |
889 | * MSI specification. | |
890 | **/ | |
891 | int pci_msi_vec_count(struct pci_dev *dev) | |
892 | { | |
893 | int ret; | |
894 | u16 msgctl; | |
895 | ||
896 | if (!dev->msi_cap) | |
897 | return -EINVAL; | |
898 | ||
899 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl); | |
900 | ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
901 | ||
902 | return ret; | |
903 | } | |
904 | EXPORT_SYMBOL(pci_msi_vec_count); | |
905 | ||
f2440d9a | 906 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 907 | { |
f2440d9a MW |
908 | struct msi_desc *desc; |
909 | u32 mask; | |
1da177e4 | 910 | |
128bc5fc | 911 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
912 | return; |
913 | ||
110828c9 MW |
914 | BUG_ON(list_empty(&dev->msi_list)); |
915 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
110828c9 | 916 | |
e375b561 | 917 | msi_set_enable(dev, 0); |
ba698ad4 | 918 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 919 | dev->msi_enabled = 0; |
7bd007e4 | 920 | |
12abb8ba | 921 | /* Return the device with MSI unmasked as initial states */ |
31ea5d4d | 922 | mask = msi_mask(desc->msi_attrib.multi_cap); |
12abb8ba | 923 | /* Keep cached state to be restored */ |
23ed8d57 | 924 | __pci_msi_desc_mask_irq(desc, mask, ~mask); |
e387b9ee ME |
925 | |
926 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 927 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 928 | } |
24d27553 | 929 | |
500559a9 | 930 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 931 | { |
d52877c7 YL |
932 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
933 | return; | |
934 | ||
935 | pci_msi_shutdown(dev); | |
f56e4481 | 936 | free_msi_irqs(dev); |
1da177e4 | 937 | } |
4cc086fa | 938 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 939 | |
a52e2e35 | 940 | /** |
ff1aa430 | 941 | * pci_msix_vec_count - return the number of device's MSI-X table entries |
a52e2e35 | 942 | * @dev: pointer to the pci_dev data structure of MSI-X device function |
ff1aa430 AG |
943 | * This function returns the number of device's MSI-X table entries and |
944 | * therefore the number of MSI-X vectors device is capable of sending. | |
945 | * It returns a negative errno if the device is not capable of sending MSI-X | |
946 | * interrupts. | |
947 | **/ | |
948 | int pci_msix_vec_count(struct pci_dev *dev) | |
a52e2e35 | 949 | { |
a52e2e35 RW |
950 | u16 control; |
951 | ||
520fe9dc | 952 | if (!dev->msix_cap) |
ff1aa430 | 953 | return -EINVAL; |
a52e2e35 | 954 | |
f84ecd28 | 955 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); |
527eee29 | 956 | return msix_table_size(control); |
a52e2e35 | 957 | } |
ff1aa430 | 958 | EXPORT_SYMBOL(pci_msix_vec_count); |
a52e2e35 | 959 | |
1da177e4 LT |
960 | /** |
961 | * pci_enable_msix - configure device's MSI-X capability structure | |
962 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 963 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 964 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
965 | * |
966 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 967 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
968 | * MSI-X mode enabled on its hardware device function. A return of zero |
969 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 970 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 971 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
972 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
973 | * re-send its request. | |
1da177e4 | 974 | **/ |
500559a9 | 975 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 976 | { |
5ec09405 | 977 | int nr_entries; |
ded86d8d | 978 | int i, j; |
1da177e4 | 979 | |
a06cd74c AG |
980 | if (!pci_msi_supported(dev, nvec)) |
981 | return -EINVAL; | |
c9953a73 | 982 | |
27e20603 AG |
983 | if (!entries) |
984 | return -EINVAL; | |
985 | ||
ff1aa430 AG |
986 | nr_entries = pci_msix_vec_count(dev); |
987 | if (nr_entries < 0) | |
988 | return nr_entries; | |
1da177e4 | 989 | if (nvec > nr_entries) |
57fbf52c | 990 | return nr_entries; |
1da177e4 LT |
991 | |
992 | /* Check for any invalid entries */ | |
993 | for (i = 0; i < nvec; i++) { | |
994 | if (entries[i].entry >= nr_entries) | |
995 | return -EINVAL; /* invalid entry */ | |
996 | for (j = i + 1; j < nvec; j++) { | |
997 | if (entries[i].entry == entries[j].entry) | |
998 | return -EINVAL; /* duplicate entry */ | |
999 | } | |
1000 | } | |
ded86d8d | 1001 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 1002 | |
1ce03373 | 1003 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 1004 | if (dev->msi_enabled) { |
227f0647 | 1005 | dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n"); |
1da177e4 LT |
1006 | return -EINVAL; |
1007 | } | |
5ec09405 | 1008 | return msix_capability_init(dev, entries, nvec); |
1da177e4 | 1009 | } |
4cc086fa | 1010 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 1011 | |
500559a9 | 1012 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 1013 | { |
12abb8ba HS |
1014 | struct msi_desc *entry; |
1015 | ||
128bc5fc | 1016 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
1017 | return; |
1018 | ||
12abb8ba HS |
1019 | /* Return the device with MSI-X masked as initial states */ |
1020 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1021 | /* Keep cached states to be restored */ | |
23ed8d57 | 1022 | __pci_msix_desc_mask_irq(entry, 1); |
12abb8ba HS |
1023 | } |
1024 | ||
66f0d0c4 | 1025 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
ba698ad4 | 1026 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 1027 | dev->msix_enabled = 0; |
d52877c7 | 1028 | } |
c901851f | 1029 | |
500559a9 | 1030 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
1031 | { |
1032 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
1033 | return; | |
1034 | ||
1035 | pci_msix_shutdown(dev); | |
f56e4481 | 1036 | free_msi_irqs(dev); |
1da177e4 | 1037 | } |
4cc086fa | 1038 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 | 1039 | |
309e57df MW |
1040 | void pci_no_msi(void) |
1041 | { | |
1042 | pci_msi_enable = 0; | |
1043 | } | |
c9953a73 | 1044 | |
07ae95f9 AP |
1045 | /** |
1046 | * pci_msi_enabled - is MSI enabled? | |
1047 | * | |
1048 | * Returns true if MSI has not been disabled by the command-line option | |
1049 | * pci=nomsi. | |
1050 | **/ | |
1051 | int pci_msi_enabled(void) | |
d389fec6 | 1052 | { |
07ae95f9 | 1053 | return pci_msi_enable; |
d389fec6 | 1054 | } |
07ae95f9 | 1055 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 1056 | |
07ae95f9 | 1057 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 1058 | { |
07ae95f9 | 1059 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
1060 | |
1061 | /* Disable the msi hardware to avoid screaming interrupts | |
1062 | * during boot. This is the power on reset default so | |
1063 | * usually this should be a noop. | |
1064 | */ | |
e375b561 GS |
1065 | dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); |
1066 | if (dev->msi_cap) | |
1067 | msi_set_enable(dev, 0); | |
1068 | ||
1069 | dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1070 | if (dev->msix_cap) | |
66f0d0c4 | 1071 | msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); |
d389fec6 | 1072 | } |
302a2523 AG |
1073 | |
1074 | /** | |
1075 | * pci_enable_msi_range - configure device's MSI capability structure | |
1076 | * @dev: device to configure | |
1077 | * @minvec: minimal number of interrupts to configure | |
1078 | * @maxvec: maximum number of interrupts to configure | |
1079 | * | |
1080 | * This function tries to allocate a maximum possible number of interrupts in a | |
1081 | * range between @minvec and @maxvec. It returns a negative errno if an error | |
1082 | * occurs. If it succeeds, it returns the actual number of interrupts allocated | |
1083 | * and updates the @dev's irq member to the lowest new interrupt number; | |
1084 | * the other interrupt numbers allocated to this device are consecutive. | |
1085 | **/ | |
1086 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec) | |
1087 | { | |
034cd97e | 1088 | int nvec; |
302a2523 AG |
1089 | int rc; |
1090 | ||
a06cd74c AG |
1091 | if (!pci_msi_supported(dev, minvec)) |
1092 | return -EINVAL; | |
034cd97e AG |
1093 | |
1094 | WARN_ON(!!dev->msi_enabled); | |
1095 | ||
1096 | /* Check whether driver already requested MSI-X irqs */ | |
1097 | if (dev->msix_enabled) { | |
1098 | dev_info(&dev->dev, | |
1099 | "can't enable MSI (MSI-X already enabled)\n"); | |
1100 | return -EINVAL; | |
1101 | } | |
1102 | ||
302a2523 AG |
1103 | if (maxvec < minvec) |
1104 | return -ERANGE; | |
1105 | ||
034cd97e AG |
1106 | nvec = pci_msi_vec_count(dev); |
1107 | if (nvec < 0) | |
1108 | return nvec; | |
1109 | else if (nvec < minvec) | |
1110 | return -EINVAL; | |
1111 | else if (nvec > maxvec) | |
1112 | nvec = maxvec; | |
1113 | ||
302a2523 | 1114 | do { |
034cd97e | 1115 | rc = msi_capability_init(dev, nvec); |
302a2523 AG |
1116 | if (rc < 0) { |
1117 | return rc; | |
1118 | } else if (rc > 0) { | |
1119 | if (rc < minvec) | |
1120 | return -ENOSPC; | |
1121 | nvec = rc; | |
1122 | } | |
1123 | } while (rc); | |
1124 | ||
1125 | return nvec; | |
1126 | } | |
1127 | EXPORT_SYMBOL(pci_enable_msi_range); | |
1128 | ||
1129 | /** | |
1130 | * pci_enable_msix_range - configure device's MSI-X capability structure | |
1131 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
1132 | * @entries: pointer to an array of MSI-X entries | |
1133 | * @minvec: minimum number of MSI-X irqs requested | |
1134 | * @maxvec: maximum number of MSI-X irqs requested | |
1135 | * | |
1136 | * Setup the MSI-X capability structure of device function with a maximum | |
1137 | * possible number of interrupts in the range between @minvec and @maxvec | |
1138 | * upon its software driver call to request for MSI-X mode enabled on its | |
1139 | * hardware device function. It returns a negative errno if an error occurs. | |
1140 | * If it succeeds, it returns the actual number of interrupts allocated and | |
1141 | * indicates the successful configuration of MSI-X capability structure | |
1142 | * with new allocated MSI-X interrupts. | |
1143 | **/ | |
1144 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, | |
1145 | int minvec, int maxvec) | |
1146 | { | |
1147 | int nvec = maxvec; | |
1148 | int rc; | |
1149 | ||
1150 | if (maxvec < minvec) | |
1151 | return -ERANGE; | |
1152 | ||
1153 | do { | |
1154 | rc = pci_enable_msix(dev, entries, nvec); | |
1155 | if (rc < 0) { | |
1156 | return rc; | |
1157 | } else if (rc > 0) { | |
1158 | if (rc < minvec) | |
1159 | return -ENOSPC; | |
1160 | nvec = rc; | |
1161 | } | |
1162 | } while (rc); | |
1163 | ||
1164 | return nvec; | |
1165 | } | |
1166 | EXPORT_SYMBOL(pci_enable_msix_range); | |
3878eaef JL |
1167 | |
1168 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN | |
1169 | /** | |
1170 | * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space | |
1171 | * @irq_data: Pointer to interrupt data of the MSI interrupt | |
1172 | * @msg: Pointer to the message | |
1173 | */ | |
1174 | void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg) | |
1175 | { | |
1176 | struct msi_desc *desc = irq_data->msi_desc; | |
1177 | ||
1178 | /* | |
1179 | * For MSI-X desc->irq is always equal to irq_data->irq. For | |
1180 | * MSI only the first interrupt of MULTI MSI passes the test. | |
1181 | */ | |
1182 | if (desc->irq == irq_data->irq) | |
1183 | __pci_write_msi_msg(desc, msg); | |
1184 | } | |
1185 | ||
1186 | /** | |
1187 | * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source | |
1188 | * @dev: Pointer to the PCI device | |
1189 | * @desc: Pointer to the msi descriptor | |
1190 | * | |
1191 | * The ID number is only used within the irqdomain. | |
1192 | */ | |
1193 | irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev, | |
1194 | struct msi_desc *desc) | |
1195 | { | |
1196 | return (irq_hw_number_t)desc->msi_attrib.entry_nr | | |
1197 | PCI_DEVID(dev->bus->number, dev->devfn) << 11 | | |
1198 | (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27; | |
1199 | } | |
1200 | ||
1201 | static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc) | |
1202 | { | |
1203 | return !desc->msi_attrib.is_msix && desc->nvec_used > 1; | |
1204 | } | |
1205 | ||
1206 | /** | |
1207 | * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev | |
1208 | * @domain: The interrupt domain to check | |
1209 | * @info: The domain info for verification | |
1210 | * @dev: The device to check | |
1211 | * | |
1212 | * Returns: | |
1213 | * 0 if the functionality is supported | |
1214 | * 1 if Multi MSI is requested, but the domain does not support it | |
1215 | * -ENOTSUPP otherwise | |
1216 | */ | |
1217 | int pci_msi_domain_check_cap(struct irq_domain *domain, | |
1218 | struct msi_domain_info *info, struct device *dev) | |
1219 | { | |
1220 | struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev)); | |
1221 | ||
1222 | /* Special handling to support pci_enable_msi_range() */ | |
1223 | if (pci_msi_desc_is_multi_msi(desc) && | |
1224 | !(info->flags & MSI_FLAG_MULTI_PCI_MSI)) | |
1225 | return 1; | |
1226 | else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX)) | |
1227 | return -ENOTSUPP; | |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | static int pci_msi_domain_handle_error(struct irq_domain *domain, | |
1233 | struct msi_desc *desc, int error) | |
1234 | { | |
1235 | /* Special handling to support pci_enable_msi_range() */ | |
1236 | if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC) | |
1237 | return 1; | |
1238 | ||
1239 | return error; | |
1240 | } | |
1241 | ||
1242 | #ifdef GENERIC_MSI_DOMAIN_OPS | |
1243 | static void pci_msi_domain_set_desc(msi_alloc_info_t *arg, | |
1244 | struct msi_desc *desc) | |
1245 | { | |
1246 | arg->desc = desc; | |
1247 | arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc), | |
1248 | desc); | |
1249 | } | |
1250 | #else | |
1251 | #define pci_msi_domain_set_desc NULL | |
1252 | #endif | |
1253 | ||
1254 | static struct msi_domain_ops pci_msi_domain_ops_default = { | |
1255 | .set_desc = pci_msi_domain_set_desc, | |
1256 | .msi_check = pci_msi_domain_check_cap, | |
1257 | .handle_error = pci_msi_domain_handle_error, | |
1258 | }; | |
1259 | ||
1260 | static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info) | |
1261 | { | |
1262 | struct msi_domain_ops *ops = info->ops; | |
1263 | ||
1264 | if (ops == NULL) { | |
1265 | info->ops = &pci_msi_domain_ops_default; | |
1266 | } else { | |
1267 | if (ops->set_desc == NULL) | |
1268 | ops->set_desc = pci_msi_domain_set_desc; | |
1269 | if (ops->msi_check == NULL) | |
1270 | ops->msi_check = pci_msi_domain_check_cap; | |
1271 | if (ops->handle_error == NULL) | |
1272 | ops->handle_error = pci_msi_domain_handle_error; | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info) | |
1277 | { | |
1278 | struct irq_chip *chip = info->chip; | |
1279 | ||
1280 | BUG_ON(!chip); | |
1281 | if (!chip->irq_write_msi_msg) | |
1282 | chip->irq_write_msi_msg = pci_msi_domain_write_msg; | |
1283 | } | |
1284 | ||
1285 | /** | |
1286 | * pci_msi_create_irq_domain - Creat a MSI interrupt domain | |
1287 | * @node: Optional device-tree node of the interrupt controller | |
1288 | * @info: MSI domain info | |
1289 | * @parent: Parent irq domain | |
1290 | * | |
1291 | * Updates the domain and chip ops and creates a MSI interrupt domain. | |
1292 | * | |
1293 | * Returns: | |
1294 | * A domain pointer or NULL in case of failure. | |
1295 | */ | |
1296 | struct irq_domain *pci_msi_create_irq_domain(struct device_node *node, | |
1297 | struct msi_domain_info *info, | |
1298 | struct irq_domain *parent) | |
1299 | { | |
1300 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) | |
1301 | pci_msi_domain_update_dom_ops(info); | |
1302 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) | |
1303 | pci_msi_domain_update_chip_ops(info); | |
1304 | ||
1305 | return msi_create_irq_domain(node, info, parent); | |
1306 | } | |
1307 | ||
1308 | /** | |
1309 | * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain | |
1310 | * @domain: The interrupt domain to allocate from | |
1311 | * @dev: The device for which to allocate | |
1312 | * @nvec: The number of interrupts to allocate | |
1313 | * @type: Unused to allow simpler migration from the arch_XXX interfaces | |
1314 | * | |
1315 | * Returns: | |
1316 | * A virtual interrupt number or an error code in case of failure | |
1317 | */ | |
1318 | int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev, | |
1319 | int nvec, int type) | |
1320 | { | |
1321 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); | |
1322 | } | |
1323 | ||
1324 | /** | |
1325 | * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain | |
1326 | * @domain: The interrupt domain | |
1327 | * @dev: The device for which to free interrupts | |
1328 | */ | |
1329 | void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev) | |
1330 | { | |
1331 | msi_domain_free_irqs(domain, &dev->dev); | |
1332 | } | |
8e047ada JL |
1333 | |
1334 | /** | |
1335 | * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain | |
1336 | * @node: Optional device-tree node of the interrupt controller | |
1337 | * @info: MSI domain info | |
1338 | * @parent: Parent irq domain | |
1339 | * | |
1340 | * Returns: A domain pointer or NULL in case of failure. If successful | |
1341 | * the default PCI/MSI irqdomain pointer is updated. | |
1342 | */ | |
1343 | struct irq_domain *pci_msi_create_default_irq_domain(struct device_node *node, | |
1344 | struct msi_domain_info *info, struct irq_domain *parent) | |
1345 | { | |
1346 | struct irq_domain *domain; | |
1347 | ||
1348 | mutex_lock(&pci_msi_domain_lock); | |
1349 | if (pci_msi_default_domain) { | |
1350 | pr_err("PCI: default irq domain for PCI MSI has already been created.\n"); | |
1351 | domain = NULL; | |
1352 | } else { | |
1353 | domain = pci_msi_create_irq_domain(node, info, parent); | |
1354 | pci_msi_default_domain = domain; | |
1355 | } | |
1356 | mutex_unlock(&pci_msi_domain_lock); | |
1357 | ||
1358 | return domain; | |
1359 | } | |
3878eaef | 1360 | #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */ |