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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 LT |
14 | #include <linux/ioport.h> |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/smp.h> | |
23 | ||
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
1da177e4 | 27 | static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL }; |
e18b890b | 28 | static struct kmem_cache* msi_cachep; |
1da177e4 LT |
29 | |
30 | static int pci_msi_enable = 1; | |
1da177e4 | 31 | |
1da177e4 LT |
32 | static int msi_cache_init(void) |
33 | { | |
57181784 PE |
34 | msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc), |
35 | 0, SLAB_HWCACHE_ALIGN, NULL, NULL); | |
1da177e4 LT |
36 | if (!msi_cachep) |
37 | return -ENOMEM; | |
38 | ||
39 | return 0; | |
40 | } | |
41 | ||
1ce03373 | 42 | static void msi_set_mask_bit(unsigned int irq, int flag) |
1da177e4 LT |
43 | { |
44 | struct msi_desc *entry; | |
45 | ||
1ce03373 | 46 | entry = msi_desc[irq]; |
277bc33b | 47 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
48 | switch (entry->msi_attrib.type) { |
49 | case PCI_CAP_ID_MSI: | |
277bc33b | 50 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
51 | int pos; |
52 | u32 mask_bits; | |
277bc33b EB |
53 | |
54 | pos = (long)entry->mask_base; | |
55 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
56 | mask_bits &= ~(1); | |
57 | mask_bits |= flag; | |
58 | pci_write_config_dword(entry->dev, pos, mask_bits); | |
59 | } | |
1da177e4 | 60 | break; |
1da177e4 LT |
61 | case PCI_CAP_ID_MSIX: |
62 | { | |
63 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
64 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
65 | writel(flag, entry->mask_base + offset); | |
66 | break; | |
67 | } | |
68 | default: | |
277bc33b | 69 | BUG(); |
1da177e4 LT |
70 | break; |
71 | } | |
72 | } | |
73 | ||
3b7d1921 | 74 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
1da177e4 | 75 | { |
3b7d1921 | 76 | struct msi_desc *entry = get_irq_data(irq); |
0366f8f7 EB |
77 | switch(entry->msi_attrib.type) { |
78 | case PCI_CAP_ID_MSI: | |
79 | { | |
80 | struct pci_dev *dev = entry->dev; | |
81 | int pos = entry->msi_attrib.pos; | |
82 | u16 data; | |
83 | ||
84 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
85 | &msg->address_lo); | |
86 | if (entry->msi_attrib.is_64) { | |
87 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
88 | &msg->address_hi); | |
89 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
90 | } else { | |
91 | msg->address_hi = 0; | |
92 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
93 | } | |
94 | msg->data = data; | |
95 | break; | |
96 | } | |
97 | case PCI_CAP_ID_MSIX: | |
98 | { | |
99 | void __iomem *base; | |
100 | base = entry->mask_base + | |
101 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
102 | ||
103 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
104 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
105 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
106 | break; | |
107 | } | |
108 | default: | |
109 | BUG(); | |
110 | } | |
111 | } | |
1da177e4 | 112 | |
3b7d1921 | 113 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 114 | { |
3b7d1921 | 115 | struct msi_desc *entry = get_irq_data(irq); |
1da177e4 LT |
116 | switch (entry->msi_attrib.type) { |
117 | case PCI_CAP_ID_MSI: | |
118 | { | |
0366f8f7 EB |
119 | struct pci_dev *dev = entry->dev; |
120 | int pos = entry->msi_attrib.pos; | |
121 | ||
122 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
123 | msg->address_lo); | |
124 | if (entry->msi_attrib.is_64) { | |
125 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
126 | msg->address_hi); | |
127 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
128 | msg->data); | |
129 | } else { | |
130 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
131 | msg->data); | |
132 | } | |
1da177e4 LT |
133 | break; |
134 | } | |
135 | case PCI_CAP_ID_MSIX: | |
136 | { | |
0366f8f7 EB |
137 | void __iomem *base; |
138 | base = entry->mask_base + | |
139 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
140 | ||
141 | writel(msg->address_lo, | |
142 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
143 | writel(msg->address_hi, | |
144 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
145 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
146 | break; |
147 | } | |
148 | default: | |
0366f8f7 | 149 | BUG(); |
1da177e4 LT |
150 | } |
151 | } | |
0366f8f7 | 152 | |
3b7d1921 | 153 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 154 | { |
1ce03373 | 155 | msi_set_mask_bit(irq, 1); |
1da177e4 LT |
156 | } |
157 | ||
3b7d1921 | 158 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 159 | { |
1ce03373 | 160 | msi_set_mask_bit(irq, 0); |
1da177e4 LT |
161 | } |
162 | ||
1ce03373 | 163 | static int msi_free_irq(struct pci_dev* dev, int irq); |
c54c1879 | 164 | |
1da177e4 LT |
165 | static int msi_init(void) |
166 | { | |
167 | static int status = -ENOMEM; | |
168 | ||
169 | if (!status) | |
170 | return status; | |
171 | ||
b64c05e7 GG |
172 | status = msi_cache_init(); |
173 | if (status < 0) { | |
1da177e4 LT |
174 | pci_msi_enable = 0; |
175 | printk(KERN_WARNING "PCI: MSI cache init failed\n"); | |
176 | return status; | |
177 | } | |
fd58e55f | 178 | |
1da177e4 LT |
179 | return status; |
180 | } | |
181 | ||
1da177e4 LT |
182 | static struct msi_desc* alloc_msi_entry(void) |
183 | { | |
184 | struct msi_desc *entry; | |
185 | ||
57181784 | 186 | entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL); |
1da177e4 LT |
187 | if (!entry) |
188 | return NULL; | |
189 | ||
1da177e4 LT |
190 | entry->link.tail = entry->link.head = 0; /* single message */ |
191 | entry->dev = NULL; | |
192 | ||
193 | return entry; | |
194 | } | |
195 | ||
1ce03373 | 196 | static void attach_msi_entry(struct msi_desc *entry, int irq) |
1da177e4 | 197 | { |
1ce03373 | 198 | msi_desc[irq] = entry; |
1da177e4 LT |
199 | } |
200 | ||
3b7d1921 | 201 | static int create_msi_irq(void) |
1da177e4 | 202 | { |
1ce03373 EB |
203 | struct msi_desc *entry; |
204 | int irq; | |
205 | ||
206 | entry = alloc_msi_entry(); | |
207 | if (!entry) | |
208 | return -ENOMEM; | |
f6bc2666 | 209 | |
1ce03373 EB |
210 | irq = create_irq(); |
211 | if (irq < 0) { | |
212 | kmem_cache_free(msi_cachep, entry); | |
213 | return -EBUSY; | |
1da177e4 | 214 | } |
1ce03373 | 215 | |
1ce03373 EB |
216 | set_irq_data(irq, entry); |
217 | ||
218 | return irq; | |
219 | } | |
220 | ||
221 | static void destroy_msi_irq(unsigned int irq) | |
222 | { | |
223 | struct msi_desc *entry; | |
224 | ||
225 | entry = get_irq_data(irq); | |
226 | set_irq_chip(irq, NULL); | |
227 | set_irq_data(irq, NULL); | |
228 | destroy_irq(irq); | |
229 | kmem_cache_free(msi_cachep, entry); | |
1da177e4 LT |
230 | } |
231 | ||
232 | static void enable_msi_mode(struct pci_dev *dev, int pos, int type) | |
233 | { | |
234 | u16 control; | |
235 | ||
236 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
237 | if (type == PCI_CAP_ID_MSI) { | |
238 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
239 | msi_enable(control, 1); | |
240 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 241 | dev->msi_enabled = 1; |
1da177e4 LT |
242 | } else { |
243 | msix_enable(control); | |
244 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 245 | dev->msix_enabled = 1; |
1da177e4 | 246 | } |
1769b46a JG |
247 | |
248 | pci_intx(dev, 0); /* disable intx */ | |
1da177e4 LT |
249 | } |
250 | ||
4602b88d | 251 | void disable_msi_mode(struct pci_dev *dev, int pos, int type) |
1da177e4 LT |
252 | { |
253 | u16 control; | |
254 | ||
255 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
256 | if (type == PCI_CAP_ID_MSI) { | |
257 | /* Set enabled bits to single MSI & enable MSI_enable bit */ | |
258 | msi_disable(control); | |
259 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 260 | dev->msi_enabled = 0; |
1da177e4 LT |
261 | } else { |
262 | msix_disable(control); | |
263 | pci_write_config_word(dev, msi_control_reg(pos), control); | |
99dc804d | 264 | dev->msix_enabled = 0; |
1da177e4 | 265 | } |
1769b46a JG |
266 | |
267 | pci_intx(dev, 1); /* enable intx */ | |
1da177e4 LT |
268 | } |
269 | ||
41017f0c | 270 | #ifdef CONFIG_PM |
8fed4b65 | 271 | static int __pci_save_msi_state(struct pci_dev *dev) |
41017f0c SL |
272 | { |
273 | int pos, i = 0; | |
274 | u16 control; | |
275 | struct pci_cap_saved_state *save_state; | |
276 | u32 *cap; | |
277 | ||
278 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
279 | if (pos <= 0 || dev->no_msi) | |
280 | return 0; | |
281 | ||
282 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
283 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
284 | return 0; | |
285 | ||
286 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5, | |
287 | GFP_KERNEL); | |
288 | if (!save_state) { | |
289 | printk(KERN_ERR "Out of memory in pci_save_msi_state\n"); | |
290 | return -ENOMEM; | |
291 | } | |
292 | cap = &save_state->data[0]; | |
293 | ||
294 | pci_read_config_dword(dev, pos, &cap[i++]); | |
295 | control = cap[0] >> 16; | |
296 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]); | |
297 | if (control & PCI_MSI_FLAGS_64BIT) { | |
298 | pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]); | |
299 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]); | |
300 | } else | |
301 | pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]); | |
302 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
303 | pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]); | |
41017f0c SL |
304 | save_state->cap_nr = PCI_CAP_ID_MSI; |
305 | pci_add_saved_cap(dev, save_state); | |
306 | return 0; | |
307 | } | |
308 | ||
8fed4b65 | 309 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c SL |
310 | { |
311 | int i = 0, pos; | |
312 | u16 control; | |
313 | struct pci_cap_saved_state *save_state; | |
314 | u32 *cap; | |
315 | ||
316 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI); | |
317 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
318 | if (!save_state || pos <= 0) | |
319 | return; | |
320 | cap = &save_state->data[0]; | |
321 | ||
322 | control = cap[i++] >> 16; | |
323 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]); | |
324 | if (control & PCI_MSI_FLAGS_64BIT) { | |
325 | pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]); | |
326 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]); | |
327 | } else | |
328 | pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]); | |
329 | if (control & PCI_MSI_FLAGS_MASKBIT) | |
330 | pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]); | |
331 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
332 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
333 | pci_remove_saved_cap(save_state); | |
334 | kfree(save_state); | |
335 | } | |
336 | ||
8fed4b65 | 337 | static int __pci_save_msix_state(struct pci_dev *dev) |
41017f0c SL |
338 | { |
339 | int pos; | |
1ce03373 | 340 | int irq, head, tail = 0; |
41017f0c SL |
341 | u16 control; |
342 | struct pci_cap_saved_state *save_state; | |
343 | ||
ded86d8d EB |
344 | if (!dev->msix_enabled) |
345 | return 0; | |
346 | ||
41017f0c SL |
347 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
348 | if (pos <= 0 || dev->no_msi) | |
349 | return 0; | |
350 | ||
fd58e55f | 351 | /* save the capability */ |
41017f0c SL |
352 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
353 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
354 | return 0; | |
355 | save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16), | |
356 | GFP_KERNEL); | |
357 | if (!save_state) { | |
358 | printk(KERN_ERR "Out of memory in pci_save_msix_state\n"); | |
359 | return -ENOMEM; | |
360 | } | |
361 | *((u16 *)&save_state->data[0]) = control; | |
362 | ||
fd58e55f | 363 | /* save the table */ |
ded86d8d | 364 | irq = head = dev->first_msi_irq; |
fd58e55f | 365 | while (head != tail) { |
fd58e55f MM |
366 | struct msi_desc *entry; |
367 | ||
1ce03373 | 368 | entry = msi_desc[irq]; |
3b7d1921 | 369 | read_msi_msg(irq, &entry->msg_save); |
fd58e55f | 370 | |
1ce03373 EB |
371 | tail = msi_desc[irq]->link.tail; |
372 | irq = tail; | |
fd58e55f | 373 | } |
fd58e55f | 374 | |
41017f0c SL |
375 | save_state->cap_nr = PCI_CAP_ID_MSIX; |
376 | pci_add_saved_cap(dev, save_state); | |
377 | return 0; | |
378 | } | |
379 | ||
8fed4b65 ME |
380 | int pci_save_msi_state(struct pci_dev *dev) |
381 | { | |
382 | int rc; | |
383 | ||
384 | rc = __pci_save_msi_state(dev); | |
385 | if (rc) | |
386 | return rc; | |
387 | ||
388 | rc = __pci_save_msix_state(dev); | |
389 | ||
390 | return rc; | |
391 | } | |
392 | ||
393 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c SL |
394 | { |
395 | u16 save; | |
396 | int pos; | |
1ce03373 | 397 | int irq, head, tail = 0; |
41017f0c | 398 | struct msi_desc *entry; |
41017f0c SL |
399 | struct pci_cap_saved_state *save_state; |
400 | ||
ded86d8d EB |
401 | if (!dev->msix_enabled) |
402 | return; | |
403 | ||
41017f0c SL |
404 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX); |
405 | if (!save_state) | |
406 | return; | |
407 | save = *((u16 *)&save_state->data[0]); | |
408 | pci_remove_saved_cap(save_state); | |
409 | kfree(save_state); | |
410 | ||
411 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
412 | if (pos <= 0) | |
413 | return; | |
414 | ||
415 | /* route the table */ | |
ded86d8d | 416 | irq = head = dev->first_msi_irq; |
41017f0c | 417 | while (head != tail) { |
1ce03373 | 418 | entry = msi_desc[irq]; |
3b7d1921 | 419 | write_msi_msg(irq, &entry->msg_save); |
41017f0c | 420 | |
1ce03373 EB |
421 | tail = msi_desc[irq]->link.tail; |
422 | irq = tail; | |
41017f0c | 423 | } |
41017f0c SL |
424 | |
425 | pci_write_config_word(dev, msi_control_reg(pos), save); | |
426 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
427 | } | |
8fed4b65 ME |
428 | |
429 | void pci_restore_msi_state(struct pci_dev *dev) | |
430 | { | |
431 | __pci_restore_msi_state(dev); | |
432 | __pci_restore_msix_state(dev); | |
433 | } | |
c54c1879 | 434 | #endif /* CONFIG_PM */ |
41017f0c | 435 | |
1da177e4 LT |
436 | /** |
437 | * msi_capability_init - configure device's MSI capability structure | |
438 | * @dev: pointer to the pci_dev data structure of MSI device function | |
439 | * | |
eaae4b3a | 440 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 441 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 442 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 443 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
444 | **/ |
445 | static int msi_capability_init(struct pci_dev *dev) | |
446 | { | |
fd58e55f | 447 | int status; |
1da177e4 | 448 | struct msi_desc *entry; |
1ce03373 | 449 | int pos, irq; |
1da177e4 LT |
450 | u16 control; |
451 | ||
452 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
453 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
454 | /* MSI Entry Initialization */ | |
3b7d1921 | 455 | irq = create_msi_irq(); |
1ce03373 EB |
456 | if (irq < 0) |
457 | return irq; | |
458 | ||
459 | entry = get_irq_data(irq); | |
460 | entry->link.head = irq; | |
461 | entry->link.tail = irq; | |
1da177e4 | 462 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 463 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
464 | entry->msi_attrib.entry_nr = 0; |
465 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
1ce03373 | 466 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 467 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
468 | if (is_mask_bit_support(control)) { |
469 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, | |
470 | is_64bit_address(control)); | |
471 | } | |
3b7d1921 EB |
472 | entry->dev = dev; |
473 | if (entry->msi_attrib.maskbit) { | |
474 | unsigned int maskbits, temp; | |
475 | /* All MSIs are unmasked by default, Mask them all */ | |
476 | pci_read_config_dword(dev, | |
477 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
478 | &maskbits); | |
479 | temp = (1 << multi_msi_capable(control)); | |
480 | temp = ((temp - 1) & ~temp); | |
481 | maskbits |= temp; | |
482 | pci_write_config_dword(dev, | |
483 | msi_mask_bits_reg(pos, is_64bit_address(control)), | |
484 | maskbits); | |
485 | } | |
1da177e4 | 486 | /* Configure MSI capability structure */ |
3b7d1921 EB |
487 | status = arch_setup_msi_irq(irq, dev); |
488 | if (status < 0) { | |
1ce03373 | 489 | destroy_msi_irq(irq); |
fd58e55f MM |
490 | return status; |
491 | } | |
41017f0c | 492 | |
ded86d8d | 493 | dev->first_msi_irq = irq; |
1ce03373 | 494 | attach_msi_entry(entry, irq); |
1da177e4 LT |
495 | /* Set MSI enabled bits */ |
496 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSI); | |
497 | ||
3b7d1921 | 498 | dev->irq = irq; |
1da177e4 LT |
499 | return 0; |
500 | } | |
501 | ||
502 | /** | |
503 | * msix_capability_init - configure device's MSI-X capability | |
504 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
505 | * @entries: pointer to an array of struct msix_entry entries |
506 | * @nvec: number of @entries | |
1da177e4 | 507 | * |
eaae4b3a | 508 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
509 | * single MSI-X irq. A return of zero indicates the successful setup of |
510 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
511 | **/ |
512 | static int msix_capability_init(struct pci_dev *dev, | |
513 | struct msix_entry *entries, int nvec) | |
514 | { | |
515 | struct msi_desc *head = NULL, *tail = NULL, *entry = NULL; | |
fd58e55f | 516 | int status; |
1ce03373 | 517 | int irq, pos, i, j, nr_entries, temp = 0; |
a0454b40 GG |
518 | unsigned long phys_addr; |
519 | u32 table_offset; | |
1da177e4 LT |
520 | u16 control; |
521 | u8 bir; | |
522 | void __iomem *base; | |
523 | ||
524 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
525 | /* Request & Map MSI-X table region */ | |
526 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
527 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
528 | |
529 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 530 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
531 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
532 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
533 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
534 | if (base == NULL) | |
535 | return -ENOMEM; | |
536 | ||
537 | /* MSI-X Table Initialization */ | |
538 | for (i = 0; i < nvec; i++) { | |
3b7d1921 | 539 | irq = create_msi_irq(); |
1ce03373 | 540 | if (irq < 0) |
1da177e4 | 541 | break; |
1da177e4 | 542 | |
1ce03373 | 543 | entry = get_irq_data(irq); |
1da177e4 | 544 | j = entries[i].entry; |
1ce03373 | 545 | entries[i].vector = irq; |
1da177e4 | 546 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 547 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
548 | entry->msi_attrib.entry_nr = j; |
549 | entry->msi_attrib.maskbit = 1; | |
1ce03373 | 550 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 551 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
552 | entry->dev = dev; |
553 | entry->mask_base = base; | |
554 | if (!head) { | |
1ce03373 EB |
555 | entry->link.head = irq; |
556 | entry->link.tail = irq; | |
1da177e4 LT |
557 | head = entry; |
558 | } else { | |
559 | entry->link.head = temp; | |
560 | entry->link.tail = tail->link.tail; | |
1ce03373 EB |
561 | tail->link.tail = irq; |
562 | head->link.head = irq; | |
1da177e4 | 563 | } |
1ce03373 | 564 | temp = irq; |
1da177e4 | 565 | tail = entry; |
1da177e4 | 566 | /* Configure MSI-X capability structure */ |
3b7d1921 | 567 | status = arch_setup_msi_irq(irq, dev); |
1ce03373 EB |
568 | if (status < 0) { |
569 | destroy_msi_irq(irq); | |
fd58e55f | 570 | break; |
1ce03373 | 571 | } |
fd58e55f | 572 | |
1ce03373 | 573 | attach_msi_entry(entry, irq); |
1da177e4 LT |
574 | } |
575 | if (i != nvec) { | |
92db6d10 | 576 | int avail = i - 1; |
1da177e4 LT |
577 | i--; |
578 | for (; i >= 0; i--) { | |
1ce03373 EB |
579 | irq = (entries + i)->vector; |
580 | msi_free_irq(dev, irq); | |
1da177e4 LT |
581 | (entries + i)->vector = 0; |
582 | } | |
92db6d10 EB |
583 | /* If we had some success report the number of irqs |
584 | * we succeeded in setting up. | |
585 | */ | |
586 | if (avail <= 0) | |
587 | avail = -EBUSY; | |
588 | return avail; | |
1da177e4 | 589 | } |
ded86d8d | 590 | dev->first_msi_irq = entries[0].vector; |
1da177e4 LT |
591 | /* Set MSI-X enabled bits */ |
592 | enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
24334a12 BG |
597 | /** |
598 | * pci_msi_supported - check whether MSI may be enabled on device | |
599 | * @dev: pointer to the pci_dev data structure of MSI device function | |
600 | * | |
0306ebfa BG |
601 | * Look at global flags, the device itself, and its parent busses |
602 | * to return 0 if MSI are supported for the device. | |
24334a12 BG |
603 | **/ |
604 | static | |
605 | int pci_msi_supported(struct pci_dev * dev) | |
606 | { | |
607 | struct pci_bus *bus; | |
608 | ||
0306ebfa | 609 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
610 | if (!pci_msi_enable || !dev || dev->no_msi) |
611 | return -EINVAL; | |
612 | ||
0306ebfa BG |
613 | /* Any bridge which does NOT route MSI transactions from it's |
614 | * secondary bus to it's primary bus must set NO_MSI flag on | |
615 | * the secondary pci_bus. | |
616 | * We expect only arch-specific PCI host bus controller driver | |
617 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
618 | */ | |
24334a12 BG |
619 | for (bus = dev->bus; bus; bus = bus->parent) |
620 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
621 | return -EINVAL; | |
622 | ||
623 | return 0; | |
624 | } | |
625 | ||
1da177e4 LT |
626 | /** |
627 | * pci_enable_msi - configure device's MSI capability structure | |
628 | * @dev: pointer to the pci_dev data structure of MSI device function | |
629 | * | |
630 | * Setup the MSI capability structure of device function with | |
1ce03373 | 631 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
632 | * MSI mode enabled on its hardware device function. A return of zero |
633 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 634 | * irq or non-zero for otherwise. |
1da177e4 LT |
635 | **/ |
636 | int pci_enable_msi(struct pci_dev* dev) | |
637 | { | |
ded86d8d | 638 | int pos, status; |
1da177e4 | 639 | |
24334a12 BG |
640 | if (pci_msi_supported(dev) < 0) |
641 | return -EINVAL; | |
6e325a62 | 642 | |
b64c05e7 GG |
643 | status = msi_init(); |
644 | if (status < 0) | |
1da177e4 LT |
645 | return status; |
646 | ||
b64c05e7 GG |
647 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
648 | if (!pos) | |
1da177e4 LT |
649 | return -EINVAL; |
650 | ||
ded86d8d | 651 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 652 | |
1ce03373 | 653 | /* Check whether driver already requested for MSI-X irqs */ |
b64c05e7 | 654 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
ded86d8d | 655 | if (pos > 0 && dev->msix_enabled) { |
1da177e4 | 656 | printk(KERN_INFO "PCI: %s: Can't enable MSI. " |
ded86d8d | 657 | "Device already has MSI-X enabled\n", |
1da177e4 | 658 | pci_name(dev)); |
1da177e4 LT |
659 | return -EINVAL; |
660 | } | |
661 | status = msi_capability_init(dev); | |
1da177e4 LT |
662 | return status; |
663 | } | |
664 | ||
665 | void pci_disable_msi(struct pci_dev* dev) | |
666 | { | |
667 | struct msi_desc *entry; | |
1ce03373 | 668 | int pos, default_irq; |
1da177e4 | 669 | u16 control; |
1da177e4 | 670 | |
309e57df MW |
671 | if (!pci_msi_enable) |
672 | return; | |
b64c05e7 GG |
673 | if (!dev) |
674 | return; | |
309e57df | 675 | |
ded86d8d EB |
676 | if (!dev->msi_enabled) |
677 | return; | |
678 | ||
b64c05e7 GG |
679 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
680 | if (!pos) | |
1da177e4 LT |
681 | return; |
682 | ||
683 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
684 | if (!(control & PCI_MSI_FLAGS_ENABLE)) | |
685 | return; | |
686 | ||
ded86d8d | 687 | |
7bd007e4 EB |
688 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSI); |
689 | ||
ded86d8d | 690 | entry = msi_desc[dev->first_msi_irq]; |
1da177e4 | 691 | if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) { |
1da177e4 LT |
692 | return; |
693 | } | |
ded86d8d | 694 | if (irq_has_action(dev->first_msi_irq)) { |
1da177e4 | 695 | printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without " |
1ce03373 | 696 | "free_irq() on MSI irq %d\n", |
ded86d8d EB |
697 | pci_name(dev), dev->first_msi_irq); |
698 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1da177e4 | 699 | } else { |
1ce03373 | 700 | default_irq = entry->msi_attrib.default_irq; |
ded86d8d | 701 | msi_free_irq(dev, dev->first_msi_irq); |
7bd007e4 | 702 | |
1ce03373 EB |
703 | /* Restore dev->irq to its default pin-assertion irq */ |
704 | dev->irq = default_irq; | |
1da177e4 | 705 | } |
ded86d8d | 706 | dev->first_msi_irq = 0; |
1da177e4 LT |
707 | } |
708 | ||
1ce03373 | 709 | static int msi_free_irq(struct pci_dev* dev, int irq) |
1da177e4 LT |
710 | { |
711 | struct msi_desc *entry; | |
712 | int head, entry_nr, type; | |
713 | void __iomem *base; | |
1da177e4 | 714 | |
3b7d1921 | 715 | arch_teardown_msi_irq(irq); |
fd58e55f | 716 | |
1ce03373 | 717 | entry = msi_desc[irq]; |
1da177e4 | 718 | if (!entry || entry->dev != dev) { |
1da177e4 LT |
719 | return -EINVAL; |
720 | } | |
721 | type = entry->msi_attrib.type; | |
722 | entry_nr = entry->msi_attrib.entry_nr; | |
723 | head = entry->link.head; | |
724 | base = entry->mask_base; | |
725 | msi_desc[entry->link.head]->link.tail = entry->link.tail; | |
726 | msi_desc[entry->link.tail]->link.head = entry->link.head; | |
727 | entry->dev = NULL; | |
1ce03373 | 728 | msi_desc[irq] = NULL; |
1da177e4 | 729 | |
1ce03373 | 730 | destroy_msi_irq(irq); |
1da177e4 LT |
731 | |
732 | if (type == PCI_CAP_ID_MSIX) { | |
1ce03373 EB |
733 | writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE + |
734 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
1da177e4 | 735 | |
1ce03373 | 736 | if (head == irq) |
1da177e4 | 737 | iounmap(base); |
1da177e4 LT |
738 | } |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
1da177e4 LT |
743 | /** |
744 | * pci_enable_msix - configure device's MSI-X capability structure | |
745 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 746 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 747 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
748 | * |
749 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 750 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
751 | * MSI-X mode enabled on its hardware device function. A return of zero |
752 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 753 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 754 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 755 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
756 | * its request. |
757 | **/ | |
758 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
759 | { | |
92db6d10 | 760 | int status, pos, nr_entries; |
ded86d8d | 761 | int i, j; |
1da177e4 | 762 | u16 control; |
1da177e4 | 763 | |
24334a12 | 764 | if (!entries || pci_msi_supported(dev) < 0) |
1da177e4 LT |
765 | return -EINVAL; |
766 | ||
b64c05e7 GG |
767 | status = msi_init(); |
768 | if (status < 0) | |
1da177e4 LT |
769 | return status; |
770 | ||
b64c05e7 GG |
771 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
772 | if (!pos) | |
1da177e4 LT |
773 | return -EINVAL; |
774 | ||
775 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
1da177e4 LT |
776 | nr_entries = multi_msix_capable(control); |
777 | if (nvec > nr_entries) | |
778 | return -EINVAL; | |
779 | ||
780 | /* Check for any invalid entries */ | |
781 | for (i = 0; i < nvec; i++) { | |
782 | if (entries[i].entry >= nr_entries) | |
783 | return -EINVAL; /* invalid entry */ | |
784 | for (j = i + 1; j < nvec; j++) { | |
785 | if (entries[i].entry == entries[j].entry) | |
786 | return -EINVAL; /* duplicate entry */ | |
787 | } | |
788 | } | |
ded86d8d | 789 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 790 | |
1ce03373 | 791 | /* Check whether driver already requested for MSI irq */ |
1da177e4 | 792 | if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 && |
ded86d8d | 793 | dev->msi_enabled) { |
1da177e4 | 794 | printk(KERN_INFO "PCI: %s: Can't enable MSI-X. " |
1ce03373 | 795 | "Device already has an MSI irq assigned\n", |
1da177e4 | 796 | pci_name(dev)); |
1da177e4 LT |
797 | return -EINVAL; |
798 | } | |
1da177e4 | 799 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
800 | return status; |
801 | } | |
802 | ||
803 | void pci_disable_msix(struct pci_dev* dev) | |
804 | { | |
ded86d8d | 805 | int irq, head, tail = 0, warning = 0; |
ded86d8d | 806 | int pos; |
1da177e4 LT |
807 | u16 control; |
808 | ||
309e57df MW |
809 | if (!pci_msi_enable) |
810 | return; | |
b64c05e7 GG |
811 | if (!dev) |
812 | return; | |
813 | ||
ded86d8d EB |
814 | if (!dev->msix_enabled) |
815 | return; | |
816 | ||
b64c05e7 GG |
817 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
818 | if (!pos) | |
1da177e4 LT |
819 | return; |
820 | ||
821 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
822 | if (!(control & PCI_MSIX_FLAGS_ENABLE)) | |
823 | return; | |
824 | ||
7bd007e4 EB |
825 | disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX); |
826 | ||
ded86d8d EB |
827 | irq = head = dev->first_msi_irq; |
828 | while (head != tail) { | |
ded86d8d | 829 | tail = msi_desc[irq]->link.tail; |
ded86d8d EB |
830 | if (irq_has_action(irq)) |
831 | warning = 1; | |
832 | else if (irq != head) /* Release MSI-X irq */ | |
833 | msi_free_irq(dev, irq); | |
834 | irq = tail; | |
835 | } | |
836 | msi_free_irq(dev, irq); | |
837 | if (warning) { | |
838 | printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without " | |
839 | "free_irq() on all MSI-X irqs\n", | |
840 | pci_name(dev)); | |
841 | BUG_ON(warning > 0); | |
1da177e4 | 842 | } |
ded86d8d | 843 | dev->first_msi_irq = 0; |
1da177e4 LT |
844 | } |
845 | ||
846 | /** | |
1ce03373 | 847 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
848 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
849 | * | |
eaae4b3a | 850 | * Being called during hotplug remove, from which the device function |
1ce03373 | 851 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
852 | * allocated for this device function, are reclaimed to unused state, |
853 | * which may be used later on. | |
854 | **/ | |
855 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
856 | { | |
ded86d8d | 857 | int pos; |
1da177e4 LT |
858 | |
859 | if (!pci_msi_enable || !dev) | |
860 | return; | |
861 | ||
b64c05e7 | 862 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
ded86d8d EB |
863 | if (pos > 0 && dev->msi_enabled) { |
864 | if (irq_has_action(dev->first_msi_irq)) { | |
1da177e4 | 865 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " |
1ce03373 | 866 | "called without free_irq() on MSI irq %d\n", |
ded86d8d EB |
867 | pci_name(dev), dev->first_msi_irq); |
868 | BUG_ON(irq_has_action(dev->first_msi_irq)); | |
1ce03373 | 869 | } else /* Release MSI irq assigned to this device */ |
ded86d8d | 870 | msi_free_irq(dev, dev->first_msi_irq); |
1da177e4 | 871 | } |
b64c05e7 | 872 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
ded86d8d | 873 | if (pos > 0 && dev->msix_enabled) { |
1ce03373 | 874 | int irq, head, tail = 0, warning = 0; |
1da177e4 LT |
875 | void __iomem *base = NULL; |
876 | ||
ded86d8d | 877 | irq = head = dev->first_msi_irq; |
1da177e4 | 878 | while (head != tail) { |
1ce03373 EB |
879 | tail = msi_desc[irq]->link.tail; |
880 | base = msi_desc[irq]->mask_base; | |
1f80025e | 881 | if (irq_has_action(irq)) |
1da177e4 | 882 | warning = 1; |
1ce03373 EB |
883 | else if (irq != head) /* Release MSI-X irq */ |
884 | msi_free_irq(dev, irq); | |
885 | irq = tail; | |
1da177e4 | 886 | } |
1ce03373 | 887 | msi_free_irq(dev, irq); |
1da177e4 | 888 | if (warning) { |
1da177e4 LT |
889 | iounmap(base); |
890 | printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() " | |
1ce03373 | 891 | "called without free_irq() on all MSI-X irqs\n", |
1da177e4 LT |
892 | pci_name(dev)); |
893 | BUG_ON(warning > 0); | |
894 | } | |
1da177e4 LT |
895 | } |
896 | } | |
897 | ||
309e57df MW |
898 | void pci_no_msi(void) |
899 | { | |
900 | pci_msi_enable = 0; | |
901 | } | |
902 | ||
1da177e4 LT |
903 | EXPORT_SYMBOL(pci_enable_msi); |
904 | EXPORT_SYMBOL(pci_disable_msi); | |
905 | EXPORT_SYMBOL(pci_enable_msix); | |
906 | EXPORT_SYMBOL(pci_disable_msix); |