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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
363c75db | 14 | #include <linux/export.h> |
1da177e4 | 15 | #include <linux/ioport.h> |
1da177e4 LT |
16 | #include <linux/pci.h> |
17 | #include <linux/proc_fs.h> | |
3b7d1921 | 18 | #include <linux/msi.h> |
4fdadebc | 19 | #include <linux/smp.h> |
500559a9 HS |
20 | #include <linux/errno.h> |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include "pci.h" | |
25 | #include "msi.h" | |
26 | ||
1da177e4 | 27 | static int pci_msi_enable = 1; |
1da177e4 | 28 | |
6a9e7f20 AB |
29 | /* Arch hooks */ |
30 | ||
11df1f05 ME |
31 | #ifndef arch_msi_check_device |
32 | int arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
33 | { |
34 | return 0; | |
35 | } | |
11df1f05 | 36 | #endif |
6a9e7f20 | 37 | |
11df1f05 | 38 | #ifndef arch_setup_msi_irqs |
1525bf0d TG |
39 | # define arch_setup_msi_irqs default_setup_msi_irqs |
40 | # define HAVE_DEFAULT_MSI_SETUP_IRQS | |
41 | #endif | |
42 | ||
43 | #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS | |
44 | int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
6a9e7f20 AB |
45 | { |
46 | struct msi_desc *entry; | |
47 | int ret; | |
48 | ||
1c8d7b0a MW |
49 | /* |
50 | * If an architecture wants to support multiple MSI, it needs to | |
51 | * override arch_setup_msi_irqs() | |
52 | */ | |
53 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
54 | return 1; | |
55 | ||
6a9e7f20 AB |
56 | list_for_each_entry(entry, &dev->msi_list, list) { |
57 | ret = arch_setup_msi_irq(dev, entry); | |
b5fbf533 | 58 | if (ret < 0) |
6a9e7f20 | 59 | return ret; |
b5fbf533 ME |
60 | if (ret > 0) |
61 | return -ENOSPC; | |
6a9e7f20 AB |
62 | } |
63 | ||
64 | return 0; | |
65 | } | |
11df1f05 | 66 | #endif |
6a9e7f20 | 67 | |
11df1f05 | 68 | #ifndef arch_teardown_msi_irqs |
1525bf0d TG |
69 | # define arch_teardown_msi_irqs default_teardown_msi_irqs |
70 | # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
71 | #endif | |
72 | ||
73 | #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS | |
74 | void default_teardown_msi_irqs(struct pci_dev *dev) | |
6a9e7f20 AB |
75 | { |
76 | struct msi_desc *entry; | |
77 | ||
78 | list_for_each_entry(entry, &dev->msi_list, list) { | |
1c8d7b0a MW |
79 | int i, nvec; |
80 | if (entry->irq == 0) | |
81 | continue; | |
82 | nvec = 1 << entry->msi_attrib.multiple; | |
83 | for (i = 0; i < nvec; i++) | |
84 | arch_teardown_msi_irq(entry->irq + i); | |
6a9e7f20 AB |
85 | } |
86 | } | |
11df1f05 | 87 | #endif |
6a9e7f20 | 88 | |
110828c9 | 89 | static void msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 90 | { |
b1cbf4e4 EB |
91 | u16 control; |
92 | ||
110828c9 | 93 | BUG_ON(!pos); |
b1cbf4e4 | 94 | |
110828c9 MW |
95 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); |
96 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
97 | if (enable) | |
98 | control |= PCI_MSI_FLAGS_ENABLE; | |
99 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
5ca5c02f HS |
100 | } |
101 | ||
b1cbf4e4 EB |
102 | static void msix_set_enable(struct pci_dev *dev, int enable) |
103 | { | |
104 | int pos; | |
105 | u16 control; | |
106 | ||
107 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
108 | if (pos) { | |
109 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
110 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
111 | if (enable) | |
112 | control |= PCI_MSIX_FLAGS_ENABLE; | |
113 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
114 | } | |
115 | } | |
116 | ||
bffac3c5 MW |
117 | static inline __attribute_const__ u32 msi_mask(unsigned x) |
118 | { | |
0b49ec37 MW |
119 | /* Don't shift by >= width of type */ |
120 | if (x >= 5) | |
121 | return 0xffffffff; | |
122 | return (1 << (1 << x)) - 1; | |
bffac3c5 MW |
123 | } |
124 | ||
f2440d9a | 125 | static inline __attribute_const__ u32 msi_capable_mask(u16 control) |
988cbb15 | 126 | { |
f2440d9a MW |
127 | return msi_mask((control >> 1) & 7); |
128 | } | |
988cbb15 | 129 | |
f2440d9a MW |
130 | static inline __attribute_const__ u32 msi_enabled_mask(u16 control) |
131 | { | |
132 | return msi_mask((control >> 4) & 7); | |
988cbb15 MW |
133 | } |
134 | ||
ce6fce42 MW |
135 | /* |
136 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
137 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
138 | * reliably as devices without an INTx disable bit will then generate a | |
139 | * level IRQ which will never be cleared. | |
ce6fce42 | 140 | */ |
12abb8ba | 141 | static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) |
1da177e4 | 142 | { |
f2440d9a | 143 | u32 mask_bits = desc->masked; |
1da177e4 | 144 | |
f2440d9a | 145 | if (!desc->msi_attrib.maskbit) |
12abb8ba | 146 | return 0; |
f2440d9a MW |
147 | |
148 | mask_bits &= ~mask; | |
149 | mask_bits |= flag; | |
150 | pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits); | |
12abb8ba HS |
151 | |
152 | return mask_bits; | |
153 | } | |
154 | ||
155 | static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag) | |
156 | { | |
157 | desc->masked = __msi_mask_irq(desc, mask, flag); | |
f2440d9a MW |
158 | } |
159 | ||
160 | /* | |
161 | * This internal function does not flush PCI writes to the device. | |
162 | * All users must ensure that they read from the device before either | |
163 | * assuming that the device state is up to date, or returning out of this | |
164 | * file. This saves a few milliseconds when initialising devices with lots | |
165 | * of MSI-X interrupts. | |
166 | */ | |
12abb8ba | 167 | static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag) |
f2440d9a MW |
168 | { |
169 | u32 mask_bits = desc->masked; | |
170 | unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
2c21fd4b | 171 | PCI_MSIX_ENTRY_VECTOR_CTRL; |
8d805286 SY |
172 | mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; |
173 | if (flag) | |
174 | mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; | |
f2440d9a | 175 | writel(mask_bits, desc->mask_base + offset); |
12abb8ba HS |
176 | |
177 | return mask_bits; | |
178 | } | |
179 | ||
180 | static void msix_mask_irq(struct msi_desc *desc, u32 flag) | |
181 | { | |
182 | desc->masked = __msix_mask_irq(desc, flag); | |
f2440d9a | 183 | } |
24d27553 | 184 | |
1c9db525 | 185 | static void msi_set_mask_bit(struct irq_data *data, u32 flag) |
f2440d9a | 186 | { |
1c9db525 | 187 | struct msi_desc *desc = irq_data_get_msi(data); |
24d27553 | 188 | |
f2440d9a MW |
189 | if (desc->msi_attrib.is_msix) { |
190 | msix_mask_irq(desc, flag); | |
191 | readl(desc->mask_base); /* Flush write to device */ | |
192 | } else { | |
1c9db525 | 193 | unsigned offset = data->irq - desc->dev->irq; |
1c8d7b0a | 194 | msi_mask_irq(desc, 1 << offset, flag << offset); |
1da177e4 | 195 | } |
f2440d9a MW |
196 | } |
197 | ||
1c9db525 | 198 | void mask_msi_irq(struct irq_data *data) |
f2440d9a | 199 | { |
1c9db525 | 200 | msi_set_mask_bit(data, 1); |
f2440d9a MW |
201 | } |
202 | ||
1c9db525 | 203 | void unmask_msi_irq(struct irq_data *data) |
f2440d9a | 204 | { |
1c9db525 | 205 | msi_set_mask_bit(data, 0); |
1da177e4 LT |
206 | } |
207 | ||
39431acb | 208 | void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
1da177e4 | 209 | { |
30da5524 BH |
210 | BUG_ON(entry->dev->current_state != PCI_D0); |
211 | ||
212 | if (entry->msi_attrib.is_msix) { | |
213 | void __iomem *base = entry->mask_base + | |
214 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
215 | ||
216 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR); | |
217 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
218 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA); | |
219 | } else { | |
220 | struct pci_dev *dev = entry->dev; | |
221 | int pos = entry->msi_attrib.pos; | |
222 | u16 data; | |
223 | ||
224 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
225 | &msg->address_lo); | |
226 | if (entry->msi_attrib.is_64) { | |
227 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
228 | &msg->address_hi); | |
229 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
230 | } else { | |
231 | msg->address_hi = 0; | |
232 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); | |
233 | } | |
234 | msg->data = data; | |
235 | } | |
236 | } | |
237 | ||
238 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) | |
239 | { | |
dced35ae | 240 | struct msi_desc *entry = irq_get_msi_desc(irq); |
30da5524 | 241 | |
39431acb | 242 | __read_msi_msg(entry, msg); |
30da5524 BH |
243 | } |
244 | ||
39431acb | 245 | void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
30da5524 | 246 | { |
30da5524 | 247 | /* Assert that the cache is valid, assuming that |
fcd097f3 BH |
248 | * valid messages are not all-zeroes. */ |
249 | BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo | | |
250 | entry->msg.data)); | |
0366f8f7 | 251 | |
fcd097f3 | 252 | *msg = entry->msg; |
0366f8f7 | 253 | } |
1da177e4 | 254 | |
30da5524 | 255 | void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 256 | { |
dced35ae | 257 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 258 | |
39431acb | 259 | __get_cached_msi_msg(entry, msg); |
3145e941 YL |
260 | } |
261 | ||
39431acb | 262 | void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) |
3145e941 | 263 | { |
fcd097f3 BH |
264 | if (entry->dev->current_state != PCI_D0) { |
265 | /* Don't touch the hardware now */ | |
266 | } else if (entry->msi_attrib.is_msix) { | |
24d27553 MW |
267 | void __iomem *base; |
268 | base = entry->mask_base + | |
269 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
270 | ||
2c21fd4b HS |
271 | writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); |
272 | writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); | |
273 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA); | |
24d27553 | 274 | } else { |
0366f8f7 EB |
275 | struct pci_dev *dev = entry->dev; |
276 | int pos = entry->msi_attrib.pos; | |
1c8d7b0a MW |
277 | u16 msgctl; |
278 | ||
279 | pci_read_config_word(dev, msi_control_reg(pos), &msgctl); | |
280 | msgctl &= ~PCI_MSI_FLAGS_QSIZE; | |
281 | msgctl |= entry->msi_attrib.multiple << 4; | |
282 | pci_write_config_word(dev, msi_control_reg(pos), msgctl); | |
0366f8f7 EB |
283 | |
284 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
285 | msg->address_lo); | |
286 | if (entry->msi_attrib.is_64) { | |
287 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
288 | msg->address_hi); | |
289 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
290 | msg->data); | |
291 | } else { | |
292 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
293 | msg->data); | |
294 | } | |
1da177e4 | 295 | } |
392ee1e6 | 296 | entry->msg = *msg; |
1da177e4 | 297 | } |
0366f8f7 | 298 | |
3145e941 YL |
299 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
300 | { | |
dced35ae | 301 | struct msi_desc *entry = irq_get_msi_desc(irq); |
3145e941 | 302 | |
39431acb | 303 | __write_msi_msg(entry, msg); |
3145e941 YL |
304 | } |
305 | ||
f56e4481 HS |
306 | static void free_msi_irqs(struct pci_dev *dev) |
307 | { | |
308 | struct msi_desc *entry, *tmp; | |
309 | ||
310 | list_for_each_entry(entry, &dev->msi_list, list) { | |
311 | int i, nvec; | |
312 | if (!entry->irq) | |
313 | continue; | |
314 | nvec = 1 << entry->msi_attrib.multiple; | |
315 | for (i = 0; i < nvec; i++) | |
316 | BUG_ON(irq_has_action(entry->irq + i)); | |
317 | } | |
318 | ||
319 | arch_teardown_msi_irqs(dev); | |
320 | ||
321 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { | |
322 | if (entry->msi_attrib.is_msix) { | |
323 | if (list_is_last(&entry->list, &dev->msi_list)) | |
324 | iounmap(entry->mask_base); | |
325 | } | |
da8d1c8b NH |
326 | kobject_del(&entry->kobj); |
327 | kobject_put(&entry->kobj); | |
f56e4481 HS |
328 | list_del(&entry->list); |
329 | kfree(entry); | |
330 | } | |
331 | } | |
c54c1879 | 332 | |
379f5327 | 333 | static struct msi_desc *alloc_msi_entry(struct pci_dev *dev) |
1da177e4 | 334 | { |
379f5327 MW |
335 | struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL); |
336 | if (!desc) | |
1da177e4 LT |
337 | return NULL; |
338 | ||
379f5327 MW |
339 | INIT_LIST_HEAD(&desc->list); |
340 | desc->dev = dev; | |
1da177e4 | 341 | |
379f5327 | 342 | return desc; |
1da177e4 LT |
343 | } |
344 | ||
ba698ad4 DM |
345 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
346 | { | |
347 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
348 | pci_intx(dev, enable); | |
349 | } | |
350 | ||
8fed4b65 | 351 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 352 | { |
392ee1e6 | 353 | int pos; |
41017f0c | 354 | u16 control; |
392ee1e6 | 355 | struct msi_desc *entry; |
41017f0c | 356 | |
b1cbf4e4 EB |
357 | if (!dev->msi_enabled) |
358 | return; | |
359 | ||
dced35ae | 360 | entry = irq_get_msi_desc(dev->irq); |
392ee1e6 | 361 | pos = entry->msi_attrib.pos; |
41017f0c | 362 | |
ba698ad4 | 363 | pci_intx_for_msi(dev, 0); |
110828c9 | 364 | msi_set_enable(dev, pos, 0); |
392ee1e6 | 365 | write_msi_msg(dev->irq, &entry->msg); |
392ee1e6 EB |
366 | |
367 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
f2440d9a | 368 | msi_mask_irq(entry, msi_capable_mask(control), entry->masked); |
abad2ec9 | 369 | control &= ~PCI_MSI_FLAGS_QSIZE; |
1c8d7b0a | 370 | control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; |
41017f0c | 371 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
372 | } |
373 | ||
374 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 375 | { |
41017f0c | 376 | int pos; |
41017f0c | 377 | struct msi_desc *entry; |
392ee1e6 | 378 | u16 control; |
41017f0c | 379 | |
ded86d8d EB |
380 | if (!dev->msix_enabled) |
381 | return; | |
f598282f | 382 | BUG_ON(list_empty(&dev->msi_list)); |
9cc8d548 | 383 | entry = list_first_entry(&dev->msi_list, struct msi_desc, list); |
f598282f MW |
384 | pos = entry->msi_attrib.pos; |
385 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
ded86d8d | 386 | |
41017f0c | 387 | /* route the table */ |
ba698ad4 | 388 | pci_intx_for_msi(dev, 0); |
f598282f MW |
389 | control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL; |
390 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 391 | |
4aa9bc95 ME |
392 | list_for_each_entry(entry, &dev->msi_list, list) { |
393 | write_msi_msg(entry->irq, &entry->msg); | |
f2440d9a | 394 | msix_mask_irq(entry, entry->masked); |
41017f0c | 395 | } |
41017f0c | 396 | |
392ee1e6 | 397 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
392ee1e6 | 398 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); |
41017f0c | 399 | } |
8fed4b65 ME |
400 | |
401 | void pci_restore_msi_state(struct pci_dev *dev) | |
402 | { | |
403 | __pci_restore_msi_state(dev); | |
404 | __pci_restore_msix_state(dev); | |
405 | } | |
94688cf2 | 406 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 407 | |
da8d1c8b NH |
408 | |
409 | #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr) | |
410 | #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj) | |
411 | ||
412 | struct msi_attribute { | |
413 | struct attribute attr; | |
414 | ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr, | |
415 | char *buf); | |
416 | ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr, | |
417 | const char *buf, size_t count); | |
418 | }; | |
419 | ||
420 | static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr, | |
421 | char *buf) | |
422 | { | |
423 | return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi"); | |
424 | } | |
425 | ||
426 | static ssize_t msi_irq_attr_show(struct kobject *kobj, | |
427 | struct attribute *attr, char *buf) | |
428 | { | |
429 | struct msi_attribute *attribute = to_msi_attr(attr); | |
430 | struct msi_desc *entry = to_msi_desc(kobj); | |
431 | ||
432 | if (!attribute->show) | |
433 | return -EIO; | |
434 | ||
435 | return attribute->show(entry, attribute, buf); | |
436 | } | |
437 | ||
438 | static const struct sysfs_ops msi_irq_sysfs_ops = { | |
439 | .show = msi_irq_attr_show, | |
440 | }; | |
441 | ||
442 | static struct msi_attribute mode_attribute = | |
443 | __ATTR(mode, S_IRUGO, show_msi_mode, NULL); | |
444 | ||
445 | ||
446 | struct attribute *msi_irq_default_attrs[] = { | |
447 | &mode_attribute.attr, | |
448 | NULL | |
449 | }; | |
450 | ||
451 | void msi_kobj_release(struct kobject *kobj) | |
452 | { | |
453 | struct msi_desc *entry = to_msi_desc(kobj); | |
454 | ||
455 | pci_dev_put(entry->dev); | |
456 | } | |
457 | ||
458 | static struct kobj_type msi_irq_ktype = { | |
459 | .release = msi_kobj_release, | |
460 | .sysfs_ops = &msi_irq_sysfs_ops, | |
461 | .default_attrs = msi_irq_default_attrs, | |
462 | }; | |
463 | ||
464 | static int populate_msi_sysfs(struct pci_dev *pdev) | |
465 | { | |
466 | struct msi_desc *entry; | |
467 | struct kobject *kobj; | |
468 | int ret; | |
469 | int count = 0; | |
470 | ||
471 | pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj); | |
472 | if (!pdev->msi_kset) | |
473 | return -ENOMEM; | |
474 | ||
475 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
476 | kobj = &entry->kobj; | |
477 | kobj->kset = pdev->msi_kset; | |
478 | pci_dev_get(pdev); | |
479 | ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL, | |
480 | "%u", entry->irq); | |
481 | if (ret) | |
482 | goto out_unroll; | |
483 | ||
484 | count++; | |
485 | } | |
486 | ||
487 | return 0; | |
488 | ||
489 | out_unroll: | |
490 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
491 | if (!count) | |
492 | break; | |
493 | kobject_del(&entry->kobj); | |
494 | kobject_put(&entry->kobj); | |
495 | count--; | |
496 | } | |
497 | return ret; | |
498 | } | |
499 | ||
1da177e4 LT |
500 | /** |
501 | * msi_capability_init - configure device's MSI capability structure | |
502 | * @dev: pointer to the pci_dev data structure of MSI device function | |
1c8d7b0a | 503 | * @nvec: number of interrupts to allocate |
1da177e4 | 504 | * |
1c8d7b0a MW |
505 | * Setup the MSI capability structure of the device with the requested |
506 | * number of interrupts. A return value of zero indicates the successful | |
507 | * setup of an entry with the new MSI irq. A negative return value indicates | |
508 | * an error, and a positive return value indicates the number of interrupts | |
509 | * which could have been allocated. | |
510 | */ | |
511 | static int msi_capability_init(struct pci_dev *dev, int nvec) | |
1da177e4 LT |
512 | { |
513 | struct msi_desc *entry; | |
7fe3730d | 514 | int pos, ret; |
1da177e4 | 515 | u16 control; |
f2440d9a | 516 | unsigned mask; |
1da177e4 | 517 | |
500559a9 | 518 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
110828c9 MW |
519 | msi_set_enable(dev, pos, 0); /* Disable MSI during set up */ |
520 | ||
1da177e4 LT |
521 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
522 | /* MSI Entry Initialization */ | |
379f5327 | 523 | entry = alloc_msi_entry(dev); |
f7feaca7 EB |
524 | if (!entry) |
525 | return -ENOMEM; | |
1ce03373 | 526 | |
500559a9 HS |
527 | entry->msi_attrib.is_msix = 0; |
528 | entry->msi_attrib.is_64 = is_64bit_address(control); | |
529 | entry->msi_attrib.entry_nr = 0; | |
530 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
531 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ | |
532 | entry->msi_attrib.pos = pos; | |
f2440d9a | 533 | |
67b5db65 | 534 | entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); |
f2440d9a MW |
535 | /* All MSIs are unmasked by default, Mask them all */ |
536 | if (entry->msi_attrib.maskbit) | |
537 | pci_read_config_dword(dev, entry->mask_pos, &entry->masked); | |
538 | mask = msi_capable_mask(control); | |
539 | msi_mask_irq(entry, mask, mask); | |
540 | ||
0dd11f9b | 541 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 542 | |
1da177e4 | 543 | /* Configure MSI capability structure */ |
1c8d7b0a | 544 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI); |
7fe3730d | 545 | if (ret) { |
7ba1930d | 546 | msi_mask_irq(entry, mask, ~mask); |
f56e4481 | 547 | free_msi_irqs(dev); |
7fe3730d | 548 | return ret; |
fd58e55f | 549 | } |
f7feaca7 | 550 | |
da8d1c8b NH |
551 | ret = populate_msi_sysfs(dev); |
552 | if (ret) { | |
553 | msi_mask_irq(entry, mask, ~mask); | |
554 | free_msi_irqs(dev); | |
555 | return ret; | |
556 | } | |
557 | ||
1da177e4 | 558 | /* Set MSI enabled bits */ |
ba698ad4 | 559 | pci_intx_for_msi(dev, 0); |
110828c9 | 560 | msi_set_enable(dev, pos, 1); |
b1cbf4e4 | 561 | dev->msi_enabled = 1; |
1da177e4 | 562 | |
7fe3730d | 563 | dev->irq = entry->irq; |
1da177e4 LT |
564 | return 0; |
565 | } | |
566 | ||
5a05a9d8 HS |
567 | static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos, |
568 | unsigned nr_entries) | |
569 | { | |
4302e0fb | 570 | resource_size_t phys_addr; |
5a05a9d8 HS |
571 | u32 table_offset; |
572 | u8 bir; | |
573 | ||
574 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
575 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); | |
576 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; | |
577 | phys_addr = pci_resource_start(dev, bir) + table_offset; | |
578 | ||
579 | return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); | |
580 | } | |
581 | ||
d9d7070e HS |
582 | static int msix_setup_entries(struct pci_dev *dev, unsigned pos, |
583 | void __iomem *base, struct msix_entry *entries, | |
584 | int nvec) | |
585 | { | |
586 | struct msi_desc *entry; | |
587 | int i; | |
588 | ||
589 | for (i = 0; i < nvec; i++) { | |
590 | entry = alloc_msi_entry(dev); | |
591 | if (!entry) { | |
592 | if (!i) | |
593 | iounmap(base); | |
594 | else | |
595 | free_msi_irqs(dev); | |
596 | /* No enough memory. Don't try again */ | |
597 | return -ENOMEM; | |
598 | } | |
599 | ||
600 | entry->msi_attrib.is_msix = 1; | |
601 | entry->msi_attrib.is_64 = 1; | |
602 | entry->msi_attrib.entry_nr = entries[i].entry; | |
603 | entry->msi_attrib.default_irq = dev->irq; | |
604 | entry->msi_attrib.pos = pos; | |
605 | entry->mask_base = base; | |
606 | ||
607 | list_add_tail(&entry->list, &dev->msi_list); | |
608 | } | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
75cb3426 HS |
613 | static void msix_program_entries(struct pci_dev *dev, |
614 | struct msix_entry *entries) | |
615 | { | |
616 | struct msi_desc *entry; | |
617 | int i = 0; | |
618 | ||
619 | list_for_each_entry(entry, &dev->msi_list, list) { | |
620 | int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE + | |
621 | PCI_MSIX_ENTRY_VECTOR_CTRL; | |
622 | ||
623 | entries[i].vector = entry->irq; | |
dced35ae | 624 | irq_set_msi_desc(entry->irq, entry); |
75cb3426 HS |
625 | entry->masked = readl(entry->mask_base + offset); |
626 | msix_mask_irq(entry, 1); | |
627 | i++; | |
628 | } | |
629 | } | |
630 | ||
1da177e4 LT |
631 | /** |
632 | * msix_capability_init - configure device's MSI-X capability | |
633 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
634 | * @entries: pointer to an array of struct msix_entry entries |
635 | * @nvec: number of @entries | |
1da177e4 | 636 | * |
eaae4b3a | 637 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
638 | * single MSI-X irq. A return of zero indicates the successful setup of |
639 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
640 | **/ |
641 | static int msix_capability_init(struct pci_dev *dev, | |
642 | struct msix_entry *entries, int nvec) | |
643 | { | |
d9d7070e | 644 | int pos, ret; |
5a05a9d8 | 645 | u16 control; |
1da177e4 LT |
646 | void __iomem *base; |
647 | ||
500559a9 | 648 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
f598282f MW |
649 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
650 | ||
651 | /* Ensure MSI-X is disabled while it is set up */ | |
652 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
653 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
654 | ||
1da177e4 | 655 | /* Request & Map MSI-X table region */ |
5a05a9d8 HS |
656 | base = msix_map_region(dev, pos, multi_msix_capable(control)); |
657 | if (!base) | |
1da177e4 LT |
658 | return -ENOMEM; |
659 | ||
d9d7070e HS |
660 | ret = msix_setup_entries(dev, pos, base, entries, nvec); |
661 | if (ret) | |
662 | return ret; | |
9c831334 ME |
663 | |
664 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
583871d4 HS |
665 | if (ret) |
666 | goto error; | |
9c831334 | 667 | |
f598282f MW |
668 | /* |
669 | * Some devices require MSI-X to be enabled before we can touch the | |
670 | * MSI-X registers. We need to mask all the vectors to prevent | |
671 | * interrupts coming in before they're fully set up. | |
672 | */ | |
673 | control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE; | |
674 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
675 | ||
75cb3426 | 676 | msix_program_entries(dev, entries); |
f598282f | 677 | |
da8d1c8b NH |
678 | ret = populate_msi_sysfs(dev); |
679 | if (ret) { | |
680 | ret = 0; | |
681 | goto error; | |
682 | } | |
683 | ||
f598282f | 684 | /* Set MSI-X enabled bits and unmask the function */ |
ba698ad4 | 685 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 686 | dev->msix_enabled = 1; |
1da177e4 | 687 | |
f598282f MW |
688 | control &= ~PCI_MSIX_FLAGS_MASKALL; |
689 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
8d181018 | 690 | |
1da177e4 | 691 | return 0; |
583871d4 HS |
692 | |
693 | error: | |
694 | if (ret < 0) { | |
695 | /* | |
696 | * If we had some success, report the number of irqs | |
697 | * we succeeded in setting up. | |
698 | */ | |
d9d7070e | 699 | struct msi_desc *entry; |
583871d4 HS |
700 | int avail = 0; |
701 | ||
702 | list_for_each_entry(entry, &dev->msi_list, list) { | |
703 | if (entry->irq != 0) | |
704 | avail++; | |
705 | } | |
706 | if (avail != 0) | |
707 | ret = avail; | |
708 | } | |
709 | ||
710 | free_msi_irqs(dev); | |
711 | ||
712 | return ret; | |
1da177e4 LT |
713 | } |
714 | ||
24334a12 | 715 | /** |
17bbc12a | 716 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 717 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 718 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 719 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 720 | * |
0306ebfa | 721 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
722 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
723 | * supported return 0, else return an error code. | |
24334a12 | 724 | **/ |
500559a9 | 725 | static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type) |
24334a12 BG |
726 | { |
727 | struct pci_bus *bus; | |
c9953a73 | 728 | int ret; |
24334a12 | 729 | |
0306ebfa | 730 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
731 | if (!pci_msi_enable || !dev || dev->no_msi) |
732 | return -EINVAL; | |
733 | ||
314e77b3 ME |
734 | /* |
735 | * You can't ask to have 0 or less MSIs configured. | |
736 | * a) it's stupid .. | |
737 | * b) the list manipulation code assumes nvec >= 1. | |
738 | */ | |
739 | if (nvec < 1) | |
740 | return -ERANGE; | |
741 | ||
500559a9 HS |
742 | /* |
743 | * Any bridge which does NOT route MSI transactions from its | |
744 | * secondary bus to its primary bus must set NO_MSI flag on | |
0306ebfa BG |
745 | * the secondary pci_bus. |
746 | * We expect only arch-specific PCI host bus controller driver | |
747 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
748 | */ | |
24334a12 BG |
749 | for (bus = dev->bus; bus; bus = bus->parent) |
750 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
751 | return -EINVAL; | |
752 | ||
c9953a73 ME |
753 | ret = arch_msi_check_device(dev, nvec, type); |
754 | if (ret) | |
755 | return ret; | |
756 | ||
b1e2303d ME |
757 | if (!pci_find_capability(dev, type)) |
758 | return -EINVAL; | |
759 | ||
24334a12 BG |
760 | return 0; |
761 | } | |
762 | ||
1da177e4 | 763 | /** |
1c8d7b0a MW |
764 | * pci_enable_msi_block - configure device's MSI capability structure |
765 | * @dev: device to configure | |
766 | * @nvec: number of interrupts to configure | |
1da177e4 | 767 | * |
1c8d7b0a MW |
768 | * Allocate IRQs for a device with the MSI capability. |
769 | * This function returns a negative errno if an error occurs. If it | |
770 | * is unable to allocate the number of interrupts requested, it returns | |
771 | * the number of interrupts it might be able to allocate. If it successfully | |
772 | * allocates at least the number of interrupts requested, it returns 0 and | |
773 | * updates the @dev's irq member to the lowest new interrupt number; the | |
774 | * other interrupt numbers allocated to this device are consecutive. | |
775 | */ | |
776 | int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec) | |
1da177e4 | 777 | { |
1c8d7b0a MW |
778 | int status, pos, maxvec; |
779 | u16 msgctl; | |
780 | ||
781 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
782 | if (!pos) | |
783 | return -EINVAL; | |
784 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); | |
785 | maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1); | |
786 | if (nvec > maxvec) | |
787 | return maxvec; | |
1da177e4 | 788 | |
1c8d7b0a | 789 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI); |
c9953a73 ME |
790 | if (status) |
791 | return status; | |
1da177e4 | 792 | |
ded86d8d | 793 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 794 | |
1c8d7b0a | 795 | /* Check whether driver already requested MSI-X irqs */ |
b1cbf4e4 | 796 | if (dev->msix_enabled) { |
80ccba11 BH |
797 | dev_info(&dev->dev, "can't enable MSI " |
798 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 799 | return -EINVAL; |
1da177e4 | 800 | } |
1c8d7b0a MW |
801 | |
802 | status = msi_capability_init(dev, nvec); | |
1da177e4 LT |
803 | return status; |
804 | } | |
1c8d7b0a | 805 | EXPORT_SYMBOL(pci_enable_msi_block); |
1da177e4 | 806 | |
f2440d9a | 807 | void pci_msi_shutdown(struct pci_dev *dev) |
1da177e4 | 808 | { |
f2440d9a MW |
809 | struct msi_desc *desc; |
810 | u32 mask; | |
811 | u16 ctrl; | |
110828c9 | 812 | unsigned pos; |
1da177e4 | 813 | |
128bc5fc | 814 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
815 | return; |
816 | ||
110828c9 MW |
817 | BUG_ON(list_empty(&dev->msi_list)); |
818 | desc = list_first_entry(&dev->msi_list, struct msi_desc, list); | |
819 | pos = desc->msi_attrib.pos; | |
820 | ||
821 | msi_set_enable(dev, pos, 0); | |
ba698ad4 | 822 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 823 | dev->msi_enabled = 0; |
7bd007e4 | 824 | |
12abb8ba | 825 | /* Return the device with MSI unmasked as initial states */ |
110828c9 | 826 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl); |
f2440d9a | 827 | mask = msi_capable_mask(ctrl); |
12abb8ba HS |
828 | /* Keep cached state to be restored */ |
829 | __msi_mask_irq(desc, mask, ~mask); | |
e387b9ee ME |
830 | |
831 | /* Restore dev->irq to its default pin-assertion irq */ | |
f2440d9a | 832 | dev->irq = desc->msi_attrib.default_irq; |
d52877c7 | 833 | } |
24d27553 | 834 | |
500559a9 | 835 | void pci_disable_msi(struct pci_dev *dev) |
d52877c7 | 836 | { |
d52877c7 YL |
837 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
838 | return; | |
839 | ||
840 | pci_msi_shutdown(dev); | |
f56e4481 | 841 | free_msi_irqs(dev); |
da8d1c8b NH |
842 | kset_unregister(dev->msi_kset); |
843 | dev->msi_kset = NULL; | |
1da177e4 | 844 | } |
4cc086fa | 845 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 846 | |
a52e2e35 RW |
847 | /** |
848 | * pci_msix_table_size - return the number of device's MSI-X table entries | |
849 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
850 | */ | |
851 | int pci_msix_table_size(struct pci_dev *dev) | |
852 | { | |
853 | int pos; | |
854 | u16 control; | |
855 | ||
856 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
857 | if (!pos) | |
858 | return 0; | |
859 | ||
860 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
861 | return multi_msix_capable(control); | |
862 | } | |
863 | ||
1da177e4 LT |
864 | /** |
865 | * pci_enable_msix - configure device's MSI-X capability structure | |
866 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 867 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 868 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
869 | * |
870 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 871 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
872 | * MSI-X mode enabled on its hardware device function. A return of zero |
873 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 874 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 875 | * Or a return of > 0 indicates that driver request is exceeding the number |
57fbf52c MT |
876 | * of irqs or MSI-X vectors available. Driver should use the returned value to |
877 | * re-send its request. | |
1da177e4 | 878 | **/ |
500559a9 | 879 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec) |
1da177e4 | 880 | { |
a52e2e35 | 881 | int status, nr_entries; |
ded86d8d | 882 | int i, j; |
1da177e4 | 883 | |
c9953a73 | 884 | if (!entries) |
500559a9 | 885 | return -EINVAL; |
1da177e4 | 886 | |
c9953a73 ME |
887 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
888 | if (status) | |
889 | return status; | |
890 | ||
a52e2e35 | 891 | nr_entries = pci_msix_table_size(dev); |
1da177e4 | 892 | if (nvec > nr_entries) |
57fbf52c | 893 | return nr_entries; |
1da177e4 LT |
894 | |
895 | /* Check for any invalid entries */ | |
896 | for (i = 0; i < nvec; i++) { | |
897 | if (entries[i].entry >= nr_entries) | |
898 | return -EINVAL; /* invalid entry */ | |
899 | for (j = i + 1; j < nvec; j++) { | |
900 | if (entries[i].entry == entries[j].entry) | |
901 | return -EINVAL; /* duplicate entry */ | |
902 | } | |
903 | } | |
ded86d8d | 904 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 905 | |
1ce03373 | 906 | /* Check whether driver already requested for MSI irq */ |
500559a9 | 907 | if (dev->msi_enabled) { |
80ccba11 BH |
908 | dev_info(&dev->dev, "can't enable MSI-X " |
909 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
910 | return -EINVAL; |
911 | } | |
1da177e4 | 912 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
913 | return status; |
914 | } | |
4cc086fa | 915 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 916 | |
500559a9 | 917 | void pci_msix_shutdown(struct pci_dev *dev) |
fc4afc7b | 918 | { |
12abb8ba HS |
919 | struct msi_desc *entry; |
920 | ||
128bc5fc | 921 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
922 | return; |
923 | ||
12abb8ba HS |
924 | /* Return the device with MSI-X masked as initial states */ |
925 | list_for_each_entry(entry, &dev->msi_list, list) { | |
926 | /* Keep cached states to be restored */ | |
927 | __msix_mask_irq(entry, 1); | |
928 | } | |
929 | ||
b1cbf4e4 | 930 | msix_set_enable(dev, 0); |
ba698ad4 | 931 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 932 | dev->msix_enabled = 0; |
d52877c7 | 933 | } |
c901851f | 934 | |
500559a9 | 935 | void pci_disable_msix(struct pci_dev *dev) |
d52877c7 YL |
936 | { |
937 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
938 | return; | |
939 | ||
940 | pci_msix_shutdown(dev); | |
f56e4481 | 941 | free_msi_irqs(dev); |
da8d1c8b NH |
942 | kset_unregister(dev->msi_kset); |
943 | dev->msi_kset = NULL; | |
1da177e4 | 944 | } |
4cc086fa | 945 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
946 | |
947 | /** | |
1ce03373 | 948 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
949 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
950 | * | |
eaae4b3a | 951 | * Being called during hotplug remove, from which the device function |
1ce03373 | 952 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
953 | * allocated for this device function, are reclaimed to unused state, |
954 | * which may be used later on. | |
955 | **/ | |
500559a9 | 956 | void msi_remove_pci_irq_vectors(struct pci_dev *dev) |
1da177e4 | 957 | { |
1da177e4 | 958 | if (!pci_msi_enable || !dev) |
500559a9 | 959 | return; |
1da177e4 | 960 | |
f56e4481 HS |
961 | if (dev->msi_enabled || dev->msix_enabled) |
962 | free_msi_irqs(dev); | |
1da177e4 LT |
963 | } |
964 | ||
309e57df MW |
965 | void pci_no_msi(void) |
966 | { | |
967 | pci_msi_enable = 0; | |
968 | } | |
c9953a73 | 969 | |
07ae95f9 AP |
970 | /** |
971 | * pci_msi_enabled - is MSI enabled? | |
972 | * | |
973 | * Returns true if MSI has not been disabled by the command-line option | |
974 | * pci=nomsi. | |
975 | **/ | |
976 | int pci_msi_enabled(void) | |
d389fec6 | 977 | { |
07ae95f9 | 978 | return pci_msi_enable; |
d389fec6 | 979 | } |
07ae95f9 | 980 | EXPORT_SYMBOL(pci_msi_enabled); |
d389fec6 | 981 | |
07ae95f9 | 982 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
d389fec6 | 983 | { |
d5dea7d9 | 984 | int pos; |
07ae95f9 | 985 | INIT_LIST_HEAD(&dev->msi_list); |
d5dea7d9 EB |
986 | |
987 | /* Disable the msi hardware to avoid screaming interrupts | |
988 | * during boot. This is the power on reset default so | |
989 | * usually this should be a noop. | |
990 | */ | |
991 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
992 | if (pos) | |
993 | msi_set_enable(dev, pos, 0); | |
994 | msix_set_enable(dev, 0); | |
d389fec6 | 995 | } |