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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * File: msi.c | |
3 | * Purpose: PCI Message Signaled Interrupt (MSI) | |
4 | * | |
5 | * Copyright (C) 2003-2004 Intel | |
6 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
7 | */ | |
8 | ||
1ce03373 | 9 | #include <linux/err.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/init.h> | |
1da177e4 | 14 | #include <linux/ioport.h> |
1da177e4 LT |
15 | #include <linux/pci.h> |
16 | #include <linux/proc_fs.h> | |
3b7d1921 | 17 | #include <linux/msi.h> |
4fdadebc | 18 | #include <linux/smp.h> |
1da177e4 LT |
19 | |
20 | #include <asm/errno.h> | |
21 | #include <asm/io.h> | |
1da177e4 LT |
22 | |
23 | #include "pci.h" | |
24 | #include "msi.h" | |
25 | ||
1da177e4 | 26 | static int pci_msi_enable = 1; |
1da177e4 | 27 | |
6a9e7f20 AB |
28 | /* Arch hooks */ |
29 | ||
30 | int __attribute__ ((weak)) | |
31 | arch_msi_check_device(struct pci_dev *dev, int nvec, int type) | |
32 | { | |
33 | return 0; | |
34 | } | |
35 | ||
36 | int __attribute__ ((weak)) | |
37 | arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry) | |
38 | { | |
39 | return 0; | |
40 | } | |
41 | ||
42 | int __attribute__ ((weak)) | |
43 | arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |
44 | { | |
45 | struct msi_desc *entry; | |
46 | int ret; | |
47 | ||
48 | list_for_each_entry(entry, &dev->msi_list, list) { | |
49 | ret = arch_setup_msi_irq(dev, entry); | |
50 | if (ret) | |
51 | return ret; | |
52 | } | |
53 | ||
54 | return 0; | |
55 | } | |
56 | ||
57 | void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq) | |
58 | { | |
59 | return; | |
60 | } | |
61 | ||
62 | void __attribute__ ((weak)) | |
63 | arch_teardown_msi_irqs(struct pci_dev *dev) | |
64 | { | |
65 | struct msi_desc *entry; | |
66 | ||
67 | list_for_each_entry(entry, &dev->msi_list, list) { | |
68 | if (entry->irq != 0) | |
69 | arch_teardown_msi_irq(entry->irq); | |
70 | } | |
71 | } | |
72 | ||
5ca5c02f | 73 | static void __msi_set_enable(struct pci_dev *dev, int pos, int enable) |
b1cbf4e4 | 74 | { |
b1cbf4e4 EB |
75 | u16 control; |
76 | ||
b1cbf4e4 EB |
77 | if (pos) { |
78 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
79 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
80 | if (enable) | |
81 | control |= PCI_MSI_FLAGS_ENABLE; | |
82 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
83 | } | |
84 | } | |
85 | ||
5ca5c02f HS |
86 | static void msi_set_enable(struct pci_dev *dev, int enable) |
87 | { | |
88 | __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable); | |
89 | } | |
90 | ||
b1cbf4e4 EB |
91 | static void msix_set_enable(struct pci_dev *dev, int enable) |
92 | { | |
93 | int pos; | |
94 | u16 control; | |
95 | ||
96 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
97 | if (pos) { | |
98 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
99 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
100 | if (enable) | |
101 | control |= PCI_MSIX_FLAGS_ENABLE; | |
102 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
103 | } | |
104 | } | |
105 | ||
3145e941 | 106 | static void msix_flush_writes(struct irq_desc *desc) |
988cbb15 MW |
107 | { |
108 | struct msi_desc *entry; | |
109 | ||
3145e941 | 110 | entry = get_irq_desc_msi(desc); |
988cbb15 MW |
111 | BUG_ON(!entry || !entry->dev); |
112 | switch (entry->msi_attrib.type) { | |
113 | case PCI_CAP_ID_MSI: | |
114 | /* nothing to do */ | |
115 | break; | |
116 | case PCI_CAP_ID_MSIX: | |
117 | { | |
118 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
119 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
120 | readl(entry->mask_base + offset); | |
121 | break; | |
122 | } | |
123 | default: | |
124 | BUG(); | |
125 | break; | |
126 | } | |
127 | } | |
128 | ||
ce6fce42 MW |
129 | /* |
130 | * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to | |
131 | * mask all MSI interrupts by clearing the MSI enable bit does not work | |
132 | * reliably as devices without an INTx disable bit will then generate a | |
133 | * level IRQ which will never be cleared. | |
134 | * | |
135 | * Returns 1 if it succeeded in masking the interrupt and 0 if the device | |
136 | * doesn't support MSI masking. | |
137 | */ | |
3145e941 | 138 | static int msi_set_mask_bits(struct irq_desc *desc, u32 mask, u32 flag) |
1da177e4 LT |
139 | { |
140 | struct msi_desc *entry; | |
141 | ||
3145e941 | 142 | entry = get_irq_desc_msi(desc); |
277bc33b | 143 | BUG_ON(!entry || !entry->dev); |
1da177e4 LT |
144 | switch (entry->msi_attrib.type) { |
145 | case PCI_CAP_ID_MSI: | |
277bc33b | 146 | if (entry->msi_attrib.maskbit) { |
c54c1879 ST |
147 | int pos; |
148 | u32 mask_bits; | |
277bc33b EB |
149 | |
150 | pos = (long)entry->mask_base; | |
151 | pci_read_config_dword(entry->dev, pos, &mask_bits); | |
8e149e09 YL |
152 | mask_bits &= ~(mask); |
153 | mask_bits |= flag & mask; | |
277bc33b | 154 | pci_write_config_dword(entry->dev, pos, mask_bits); |
58e0543e | 155 | } else { |
ce6fce42 | 156 | return 0; |
277bc33b | 157 | } |
1da177e4 | 158 | break; |
1da177e4 LT |
159 | case PCI_CAP_ID_MSIX: |
160 | { | |
161 | int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + | |
162 | PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET; | |
163 | writel(flag, entry->mask_base + offset); | |
348e3fd1 | 164 | readl(entry->mask_base + offset); |
1da177e4 LT |
165 | break; |
166 | } | |
167 | default: | |
277bc33b | 168 | BUG(); |
1da177e4 LT |
169 | break; |
170 | } | |
392ee1e6 | 171 | entry->msi_attrib.masked = !!flag; |
ce6fce42 | 172 | return 1; |
1da177e4 LT |
173 | } |
174 | ||
3145e941 | 175 | void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) |
1da177e4 | 176 | { |
3145e941 | 177 | struct msi_desc *entry = get_irq_desc_msi(desc); |
0366f8f7 EB |
178 | switch(entry->msi_attrib.type) { |
179 | case PCI_CAP_ID_MSI: | |
180 | { | |
181 | struct pci_dev *dev = entry->dev; | |
182 | int pos = entry->msi_attrib.pos; | |
183 | u16 data; | |
184 | ||
185 | pci_read_config_dword(dev, msi_lower_address_reg(pos), | |
186 | &msg->address_lo); | |
187 | if (entry->msi_attrib.is_64) { | |
188 | pci_read_config_dword(dev, msi_upper_address_reg(pos), | |
189 | &msg->address_hi); | |
190 | pci_read_config_word(dev, msi_data_reg(pos, 1), &data); | |
191 | } else { | |
192 | msg->address_hi = 0; | |
cbf5d9e6 | 193 | pci_read_config_word(dev, msi_data_reg(pos, 0), &data); |
0366f8f7 EB |
194 | } |
195 | msg->data = data; | |
196 | break; | |
197 | } | |
198 | case PCI_CAP_ID_MSIX: | |
199 | { | |
200 | void __iomem *base; | |
201 | base = entry->mask_base + | |
202 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
203 | ||
204 | msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
205 | msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
206 | msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
207 | break; | |
208 | } | |
209 | default: | |
210 | BUG(); | |
211 | } | |
212 | } | |
1da177e4 | 213 | |
3145e941 | 214 | void read_msi_msg(unsigned int irq, struct msi_msg *msg) |
0366f8f7 | 215 | { |
3145e941 YL |
216 | struct irq_desc *desc = irq_to_desc(irq); |
217 | ||
218 | read_msi_msg_desc(desc, msg); | |
219 | } | |
220 | ||
221 | void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg) | |
222 | { | |
223 | struct msi_desc *entry = get_irq_desc_msi(desc); | |
1da177e4 LT |
224 | switch (entry->msi_attrib.type) { |
225 | case PCI_CAP_ID_MSI: | |
226 | { | |
0366f8f7 EB |
227 | struct pci_dev *dev = entry->dev; |
228 | int pos = entry->msi_attrib.pos; | |
229 | ||
230 | pci_write_config_dword(dev, msi_lower_address_reg(pos), | |
231 | msg->address_lo); | |
232 | if (entry->msi_attrib.is_64) { | |
233 | pci_write_config_dword(dev, msi_upper_address_reg(pos), | |
234 | msg->address_hi); | |
235 | pci_write_config_word(dev, msi_data_reg(pos, 1), | |
236 | msg->data); | |
237 | } else { | |
238 | pci_write_config_word(dev, msi_data_reg(pos, 0), | |
239 | msg->data); | |
240 | } | |
1da177e4 LT |
241 | break; |
242 | } | |
243 | case PCI_CAP_ID_MSIX: | |
244 | { | |
0366f8f7 EB |
245 | void __iomem *base; |
246 | base = entry->mask_base + | |
247 | entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; | |
248 | ||
249 | writel(msg->address_lo, | |
250 | base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET); | |
251 | writel(msg->address_hi, | |
252 | base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET); | |
253 | writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET); | |
1da177e4 LT |
254 | break; |
255 | } | |
256 | default: | |
0366f8f7 | 257 | BUG(); |
1da177e4 | 258 | } |
392ee1e6 | 259 | entry->msg = *msg; |
1da177e4 | 260 | } |
0366f8f7 | 261 | |
3145e941 YL |
262 | void write_msi_msg(unsigned int irq, struct msi_msg *msg) |
263 | { | |
264 | struct irq_desc *desc = irq_to_desc(irq); | |
265 | ||
266 | write_msi_msg_desc(desc, msg); | |
267 | } | |
268 | ||
3b7d1921 | 269 | void mask_msi_irq(unsigned int irq) |
1da177e4 | 270 | { |
3145e941 YL |
271 | struct irq_desc *desc = irq_to_desc(irq); |
272 | ||
273 | msi_set_mask_bits(desc, 1, 1); | |
274 | msix_flush_writes(desc); | |
1da177e4 LT |
275 | } |
276 | ||
3b7d1921 | 277 | void unmask_msi_irq(unsigned int irq) |
1da177e4 | 278 | { |
3145e941 YL |
279 | struct irq_desc *desc = irq_to_desc(irq); |
280 | ||
281 | msi_set_mask_bits(desc, 1, 0); | |
282 | msix_flush_writes(desc); | |
1da177e4 LT |
283 | } |
284 | ||
032de8e2 | 285 | static int msi_free_irqs(struct pci_dev* dev); |
c54c1879 | 286 | |
1da177e4 LT |
287 | static struct msi_desc* alloc_msi_entry(void) |
288 | { | |
289 | struct msi_desc *entry; | |
290 | ||
3e916c05 | 291 | entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL); |
1da177e4 LT |
292 | if (!entry) |
293 | return NULL; | |
294 | ||
4aa9bc95 ME |
295 | INIT_LIST_HEAD(&entry->list); |
296 | entry->irq = 0; | |
1da177e4 LT |
297 | entry->dev = NULL; |
298 | ||
299 | return entry; | |
300 | } | |
301 | ||
ba698ad4 DM |
302 | static void pci_intx_for_msi(struct pci_dev *dev, int enable) |
303 | { | |
304 | if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG)) | |
305 | pci_intx(dev, enable); | |
306 | } | |
307 | ||
8fed4b65 | 308 | static void __pci_restore_msi_state(struct pci_dev *dev) |
41017f0c | 309 | { |
392ee1e6 | 310 | int pos; |
41017f0c | 311 | u16 control; |
392ee1e6 | 312 | struct msi_desc *entry; |
41017f0c | 313 | |
b1cbf4e4 EB |
314 | if (!dev->msi_enabled) |
315 | return; | |
316 | ||
392ee1e6 EB |
317 | entry = get_irq_msi(dev->irq); |
318 | pos = entry->msi_attrib.pos; | |
41017f0c | 319 | |
ba698ad4 | 320 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 321 | msi_set_enable(dev, 0); |
392ee1e6 | 322 | write_msi_msg(dev->irq, &entry->msg); |
3145e941 YL |
323 | if (entry->msi_attrib.maskbit) { |
324 | struct irq_desc *desc = irq_to_desc(dev->irq); | |
325 | msi_set_mask_bits(desc, entry->msi_attrib.maskbits_mask, | |
8e149e09 | 326 | entry->msi_attrib.masked); |
3145e941 | 327 | } |
392ee1e6 EB |
328 | |
329 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
abad2ec9 JB |
330 | control &= ~PCI_MSI_FLAGS_QSIZE; |
331 | control |= PCI_MSI_FLAGS_ENABLE; | |
41017f0c | 332 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); |
8fed4b65 ME |
333 | } |
334 | ||
335 | static void __pci_restore_msix_state(struct pci_dev *dev) | |
41017f0c | 336 | { |
41017f0c | 337 | int pos; |
41017f0c | 338 | struct msi_desc *entry; |
392ee1e6 | 339 | u16 control; |
41017f0c | 340 | |
ded86d8d EB |
341 | if (!dev->msix_enabled) |
342 | return; | |
343 | ||
41017f0c | 344 | /* route the table */ |
ba698ad4 | 345 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 | 346 | msix_set_enable(dev, 0); |
41017f0c | 347 | |
4aa9bc95 | 348 | list_for_each_entry(entry, &dev->msi_list, list) { |
3145e941 | 349 | struct irq_desc *desc = irq_to_desc(entry->irq); |
4aa9bc95 | 350 | write_msi_msg(entry->irq, &entry->msg); |
3145e941 | 351 | msi_set_mask_bits(desc, 1, entry->msi_attrib.masked); |
41017f0c | 352 | } |
41017f0c | 353 | |
314e77b3 ME |
354 | BUG_ON(list_empty(&dev->msi_list)); |
355 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
4aa9bc95 | 356 | pos = entry->msi_attrib.pos; |
392ee1e6 EB |
357 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); |
358 | control &= ~PCI_MSIX_FLAGS_MASKALL; | |
359 | control |= PCI_MSIX_FLAGS_ENABLE; | |
360 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
41017f0c | 361 | } |
8fed4b65 ME |
362 | |
363 | void pci_restore_msi_state(struct pci_dev *dev) | |
364 | { | |
365 | __pci_restore_msi_state(dev); | |
366 | __pci_restore_msix_state(dev); | |
367 | } | |
94688cf2 | 368 | EXPORT_SYMBOL_GPL(pci_restore_msi_state); |
41017f0c | 369 | |
1da177e4 LT |
370 | /** |
371 | * msi_capability_init - configure device's MSI capability structure | |
372 | * @dev: pointer to the pci_dev data structure of MSI device function | |
373 | * | |
eaae4b3a | 374 | * Setup the MSI capability structure of device function with a single |
1ce03373 | 375 | * MSI irq, regardless of device function is capable of handling |
1da177e4 | 376 | * multiple messages. A return of zero indicates the successful setup |
1ce03373 | 377 | * of an entry zero with the new MSI irq or non-zero for otherwise. |
1da177e4 LT |
378 | **/ |
379 | static int msi_capability_init(struct pci_dev *dev) | |
380 | { | |
381 | struct msi_desc *entry; | |
7fe3730d | 382 | int pos, ret; |
1da177e4 LT |
383 | u16 control; |
384 | ||
b1cbf4e4 EB |
385 | msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */ |
386 | ||
1da177e4 LT |
387 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
388 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
389 | /* MSI Entry Initialization */ | |
f7feaca7 EB |
390 | entry = alloc_msi_entry(); |
391 | if (!entry) | |
392 | return -ENOMEM; | |
1ce03373 | 393 | |
1da177e4 | 394 | entry->msi_attrib.type = PCI_CAP_ID_MSI; |
0366f8f7 | 395 | entry->msi_attrib.is_64 = is_64bit_address(control); |
1da177e4 LT |
396 | entry->msi_attrib.entry_nr = 0; |
397 | entry->msi_attrib.maskbit = is_mask_bit_support(control); | |
392ee1e6 | 398 | entry->msi_attrib.masked = 1; |
1ce03373 | 399 | entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ |
0366f8f7 | 400 | entry->msi_attrib.pos = pos; |
5993760f | 401 | if (entry->msi_attrib.maskbit) { |
1da177e4 | 402 | entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos, |
5993760f | 403 | entry->msi_attrib.is_64); |
1da177e4 | 404 | } |
3b7d1921 EB |
405 | entry->dev = dev; |
406 | if (entry->msi_attrib.maskbit) { | |
407 | unsigned int maskbits, temp; | |
408 | /* All MSIs are unmasked by default, Mask them all */ | |
409 | pci_read_config_dword(dev, | |
5993760f | 410 | msi_mask_bits_reg(pos, entry->msi_attrib.is_64), |
3b7d1921 EB |
411 | &maskbits); |
412 | temp = (1 << multi_msi_capable(control)); | |
413 | temp = ((temp - 1) & ~temp); | |
414 | maskbits |= temp; | |
5993760f | 415 | pci_write_config_dword(dev, entry->msi_attrib.is_64, maskbits); |
8e149e09 | 416 | entry->msi_attrib.maskbits_mask = temp; |
3b7d1921 | 417 | } |
0dd11f9b | 418 | list_add_tail(&entry->list, &dev->msi_list); |
9c831334 | 419 | |
1da177e4 | 420 | /* Configure MSI capability structure */ |
9c831334 | 421 | ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI); |
7fe3730d | 422 | if (ret) { |
032de8e2 | 423 | msi_free_irqs(dev); |
7fe3730d | 424 | return ret; |
fd58e55f | 425 | } |
f7feaca7 | 426 | |
1da177e4 | 427 | /* Set MSI enabled bits */ |
ba698ad4 | 428 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
429 | msi_set_enable(dev, 1); |
430 | dev->msi_enabled = 1; | |
1da177e4 | 431 | |
7fe3730d | 432 | dev->irq = entry->irq; |
1da177e4 LT |
433 | return 0; |
434 | } | |
435 | ||
436 | /** | |
437 | * msix_capability_init - configure device's MSI-X capability | |
438 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
8f7020d3 RD |
439 | * @entries: pointer to an array of struct msix_entry entries |
440 | * @nvec: number of @entries | |
1da177e4 | 441 | * |
eaae4b3a | 442 | * Setup the MSI-X capability structure of device function with a |
1ce03373 EB |
443 | * single MSI-X irq. A return of zero indicates the successful setup of |
444 | * requested MSI-X entries with allocated irqs or non-zero for otherwise. | |
1da177e4 LT |
445 | **/ |
446 | static int msix_capability_init(struct pci_dev *dev, | |
447 | struct msix_entry *entries, int nvec) | |
448 | { | |
4aa9bc95 | 449 | struct msi_desc *entry; |
9c831334 | 450 | int pos, i, j, nr_entries, ret; |
a0454b40 GG |
451 | unsigned long phys_addr; |
452 | u32 table_offset; | |
1da177e4 LT |
453 | u16 control; |
454 | u8 bir; | |
455 | void __iomem *base; | |
456 | ||
b1cbf4e4 EB |
457 | msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */ |
458 | ||
1da177e4 LT |
459 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
460 | /* Request & Map MSI-X table region */ | |
461 | pci_read_config_word(dev, msi_control_reg(pos), &control); | |
462 | nr_entries = multi_msix_capable(control); | |
a0454b40 GG |
463 | |
464 | pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset); | |
1da177e4 | 465 | bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK); |
a0454b40 GG |
466 | table_offset &= ~PCI_MSIX_FLAGS_BIRMASK; |
467 | phys_addr = pci_resource_start (dev, bir) + table_offset; | |
1da177e4 LT |
468 | base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); |
469 | if (base == NULL) | |
470 | return -ENOMEM; | |
471 | ||
472 | /* MSI-X Table Initialization */ | |
473 | for (i = 0; i < nvec; i++) { | |
f7feaca7 EB |
474 | entry = alloc_msi_entry(); |
475 | if (!entry) | |
1da177e4 | 476 | break; |
1da177e4 LT |
477 | |
478 | j = entries[i].entry; | |
1da177e4 | 479 | entry->msi_attrib.type = PCI_CAP_ID_MSIX; |
0366f8f7 | 480 | entry->msi_attrib.is_64 = 1; |
1da177e4 LT |
481 | entry->msi_attrib.entry_nr = j; |
482 | entry->msi_attrib.maskbit = 1; | |
392ee1e6 | 483 | entry->msi_attrib.masked = 1; |
1ce03373 | 484 | entry->msi_attrib.default_irq = dev->irq; |
0366f8f7 | 485 | entry->msi_attrib.pos = pos; |
1da177e4 LT |
486 | entry->dev = dev; |
487 | entry->mask_base = base; | |
f7feaca7 | 488 | |
0dd11f9b | 489 | list_add_tail(&entry->list, &dev->msi_list); |
1da177e4 | 490 | } |
9c831334 ME |
491 | |
492 | ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX); | |
493 | if (ret) { | |
494 | int avail = 0; | |
495 | list_for_each_entry(entry, &dev->msi_list, list) { | |
496 | if (entry->irq != 0) { | |
497 | avail++; | |
9c831334 | 498 | } |
1da177e4 | 499 | } |
9c831334 | 500 | |
032de8e2 ME |
501 | msi_free_irqs(dev); |
502 | ||
92db6d10 EB |
503 | /* If we had some success report the number of irqs |
504 | * we succeeded in setting up. | |
505 | */ | |
9c831334 ME |
506 | if (avail == 0) |
507 | avail = ret; | |
92db6d10 | 508 | return avail; |
1da177e4 | 509 | } |
9c831334 ME |
510 | |
511 | i = 0; | |
512 | list_for_each_entry(entry, &dev->msi_list, list) { | |
513 | entries[i].vector = entry->irq; | |
514 | set_irq_msi(entry->irq, entry); | |
515 | i++; | |
516 | } | |
1da177e4 | 517 | /* Set MSI-X enabled bits */ |
ba698ad4 | 518 | pci_intx_for_msi(dev, 0); |
b1cbf4e4 EB |
519 | msix_set_enable(dev, 1); |
520 | dev->msix_enabled = 1; | |
1da177e4 LT |
521 | |
522 | return 0; | |
523 | } | |
524 | ||
24334a12 | 525 | /** |
17bbc12a | 526 | * pci_msi_check_device - check whether MSI may be enabled on a device |
24334a12 | 527 | * @dev: pointer to the pci_dev data structure of MSI device function |
c9953a73 | 528 | * @nvec: how many MSIs have been requested ? |
b1e2303d | 529 | * @type: are we checking for MSI or MSI-X ? |
24334a12 | 530 | * |
0306ebfa | 531 | * Look at global flags, the device itself, and its parent busses |
17bbc12a ME |
532 | * to determine if MSI/-X are supported for the device. If MSI/-X is |
533 | * supported return 0, else return an error code. | |
24334a12 | 534 | **/ |
c9953a73 | 535 | static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type) |
24334a12 BG |
536 | { |
537 | struct pci_bus *bus; | |
c9953a73 | 538 | int ret; |
24334a12 | 539 | |
0306ebfa | 540 | /* MSI must be globally enabled and supported by the device */ |
24334a12 BG |
541 | if (!pci_msi_enable || !dev || dev->no_msi) |
542 | return -EINVAL; | |
543 | ||
314e77b3 ME |
544 | /* |
545 | * You can't ask to have 0 or less MSIs configured. | |
546 | * a) it's stupid .. | |
547 | * b) the list manipulation code assumes nvec >= 1. | |
548 | */ | |
549 | if (nvec < 1) | |
550 | return -ERANGE; | |
551 | ||
0306ebfa BG |
552 | /* Any bridge which does NOT route MSI transactions from it's |
553 | * secondary bus to it's primary bus must set NO_MSI flag on | |
554 | * the secondary pci_bus. | |
555 | * We expect only arch-specific PCI host bus controller driver | |
556 | * or quirks for specific PCI bridges to be setting NO_MSI. | |
557 | */ | |
24334a12 BG |
558 | for (bus = dev->bus; bus; bus = bus->parent) |
559 | if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI) | |
560 | return -EINVAL; | |
561 | ||
c9953a73 ME |
562 | ret = arch_msi_check_device(dev, nvec, type); |
563 | if (ret) | |
564 | return ret; | |
565 | ||
b1e2303d ME |
566 | if (!pci_find_capability(dev, type)) |
567 | return -EINVAL; | |
568 | ||
24334a12 BG |
569 | return 0; |
570 | } | |
571 | ||
1da177e4 LT |
572 | /** |
573 | * pci_enable_msi - configure device's MSI capability structure | |
574 | * @dev: pointer to the pci_dev data structure of MSI device function | |
575 | * | |
576 | * Setup the MSI capability structure of device function with | |
1ce03373 | 577 | * a single MSI irq upon its software driver call to request for |
1da177e4 LT |
578 | * MSI mode enabled on its hardware device function. A return of zero |
579 | * indicates the successful setup of an entry zero with the new MSI | |
1ce03373 | 580 | * irq or non-zero for otherwise. |
1da177e4 LT |
581 | **/ |
582 | int pci_enable_msi(struct pci_dev* dev) | |
583 | { | |
b1e2303d | 584 | int status; |
1da177e4 | 585 | |
c9953a73 ME |
586 | status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI); |
587 | if (status) | |
588 | return status; | |
1da177e4 | 589 | |
ded86d8d | 590 | WARN_ON(!!dev->msi_enabled); |
1da177e4 | 591 | |
1ce03373 | 592 | /* Check whether driver already requested for MSI-X irqs */ |
b1cbf4e4 | 593 | if (dev->msix_enabled) { |
80ccba11 BH |
594 | dev_info(&dev->dev, "can't enable MSI " |
595 | "(MSI-X already enabled)\n"); | |
b1cbf4e4 | 596 | return -EINVAL; |
1da177e4 LT |
597 | } |
598 | status = msi_capability_init(dev); | |
1da177e4 LT |
599 | return status; |
600 | } | |
4cc086fa | 601 | EXPORT_SYMBOL(pci_enable_msi); |
1da177e4 | 602 | |
d52877c7 | 603 | void pci_msi_shutdown(struct pci_dev* dev) |
1da177e4 LT |
604 | { |
605 | struct msi_desc *entry; | |
1da177e4 | 606 | |
128bc5fc | 607 | if (!pci_msi_enable || !dev || !dev->msi_enabled) |
ded86d8d EB |
608 | return; |
609 | ||
b1cbf4e4 | 610 | msi_set_enable(dev, 0); |
ba698ad4 | 611 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 612 | dev->msi_enabled = 0; |
7bd007e4 | 613 | |
314e77b3 ME |
614 | BUG_ON(list_empty(&dev->msi_list)); |
615 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
8e149e09 YL |
616 | /* Return the the pci reset with msi irqs unmasked */ |
617 | if (entry->msi_attrib.maskbit) { | |
618 | u32 mask = entry->msi_attrib.maskbits_mask; | |
3145e941 YL |
619 | struct irq_desc *desc = irq_to_desc(dev->irq); |
620 | msi_set_mask_bits(desc, mask, ~mask); | |
8e149e09 | 621 | } |
d52877c7 | 622 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) |
1da177e4 | 623 | return; |
e387b9ee ME |
624 | |
625 | /* Restore dev->irq to its default pin-assertion irq */ | |
d52877c7 YL |
626 | dev->irq = entry->msi_attrib.default_irq; |
627 | } | |
628 | void pci_disable_msi(struct pci_dev* dev) | |
629 | { | |
630 | struct msi_desc *entry; | |
631 | ||
632 | if (!pci_msi_enable || !dev || !dev->msi_enabled) | |
633 | return; | |
634 | ||
635 | pci_msi_shutdown(dev); | |
636 | ||
637 | entry = list_entry(dev->msi_list.next, struct msi_desc, list); | |
638 | if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) | |
639 | return; | |
640 | ||
641 | msi_free_irqs(dev); | |
1da177e4 | 642 | } |
4cc086fa | 643 | EXPORT_SYMBOL(pci_disable_msi); |
1da177e4 | 644 | |
032de8e2 | 645 | static int msi_free_irqs(struct pci_dev* dev) |
1da177e4 | 646 | { |
032de8e2 | 647 | struct msi_desc *entry, *tmp; |
7ede9c1f | 648 | |
b3b7cc7b DM |
649 | list_for_each_entry(entry, &dev->msi_list, list) { |
650 | if (entry->irq) | |
651 | BUG_ON(irq_has_action(entry->irq)); | |
652 | } | |
1da177e4 | 653 | |
032de8e2 | 654 | arch_teardown_msi_irqs(dev); |
1da177e4 | 655 | |
032de8e2 ME |
656 | list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) { |
657 | if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) { | |
032de8e2 ME |
658 | writel(1, entry->mask_base + entry->msi_attrib.entry_nr |
659 | * PCI_MSIX_ENTRY_SIZE | |
660 | + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET); | |
78b7611c EB |
661 | |
662 | if (list_is_last(&entry->list, &dev->msi_list)) | |
663 | iounmap(entry->mask_base); | |
032de8e2 ME |
664 | } |
665 | list_del(&entry->list); | |
666 | kfree(entry); | |
1da177e4 LT |
667 | } |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
1da177e4 LT |
672 | /** |
673 | * pci_enable_msix - configure device's MSI-X capability structure | |
674 | * @dev: pointer to the pci_dev data structure of MSI-X device function | |
70549ad9 | 675 | * @entries: pointer to an array of MSI-X entries |
1ce03373 | 676 | * @nvec: number of MSI-X irqs requested for allocation by device driver |
1da177e4 LT |
677 | * |
678 | * Setup the MSI-X capability structure of device function with the number | |
1ce03373 | 679 | * of requested irqs upon its software driver call to request for |
1da177e4 LT |
680 | * MSI-X mode enabled on its hardware device function. A return of zero |
681 | * indicates the successful configuration of MSI-X capability structure | |
1ce03373 | 682 | * with new allocated MSI-X irqs. A return of < 0 indicates a failure. |
1da177e4 | 683 | * Or a return of > 0 indicates that driver request is exceeding the number |
1ce03373 | 684 | * of irqs available. Driver should use the returned value to re-send |
1da177e4 LT |
685 | * its request. |
686 | **/ | |
687 | int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) | |
688 | { | |
92db6d10 | 689 | int status, pos, nr_entries; |
ded86d8d | 690 | int i, j; |
1da177e4 | 691 | u16 control; |
1da177e4 | 692 | |
c9953a73 | 693 | if (!entries) |
1da177e4 LT |
694 | return -EINVAL; |
695 | ||
c9953a73 ME |
696 | status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX); |
697 | if (status) | |
698 | return status; | |
699 | ||
b64c05e7 | 700 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); |
1da177e4 | 701 | pci_read_config_word(dev, msi_control_reg(pos), &control); |
1da177e4 LT |
702 | nr_entries = multi_msix_capable(control); |
703 | if (nvec > nr_entries) | |
704 | return -EINVAL; | |
705 | ||
706 | /* Check for any invalid entries */ | |
707 | for (i = 0; i < nvec; i++) { | |
708 | if (entries[i].entry >= nr_entries) | |
709 | return -EINVAL; /* invalid entry */ | |
710 | for (j = i + 1; j < nvec; j++) { | |
711 | if (entries[i].entry == entries[j].entry) | |
712 | return -EINVAL; /* duplicate entry */ | |
713 | } | |
714 | } | |
ded86d8d | 715 | WARN_ON(!!dev->msix_enabled); |
7bd007e4 | 716 | |
1ce03373 | 717 | /* Check whether driver already requested for MSI irq */ |
b1cbf4e4 | 718 | if (dev->msi_enabled) { |
80ccba11 BH |
719 | dev_info(&dev->dev, "can't enable MSI-X " |
720 | "(MSI IRQ already assigned)\n"); | |
1da177e4 LT |
721 | return -EINVAL; |
722 | } | |
1da177e4 | 723 | status = msix_capability_init(dev, entries, nvec); |
1da177e4 LT |
724 | return status; |
725 | } | |
4cc086fa | 726 | EXPORT_SYMBOL(pci_enable_msix); |
1da177e4 | 727 | |
fc4afc7b | 728 | static void msix_free_all_irqs(struct pci_dev *dev) |
1da177e4 | 729 | { |
032de8e2 | 730 | msi_free_irqs(dev); |
fc4afc7b ME |
731 | } |
732 | ||
d52877c7 | 733 | void pci_msix_shutdown(struct pci_dev* dev) |
fc4afc7b | 734 | { |
128bc5fc | 735 | if (!pci_msi_enable || !dev || !dev->msix_enabled) |
ded86d8d EB |
736 | return; |
737 | ||
b1cbf4e4 | 738 | msix_set_enable(dev, 0); |
ba698ad4 | 739 | pci_intx_for_msi(dev, 1); |
b1cbf4e4 | 740 | dev->msix_enabled = 0; |
d52877c7 YL |
741 | } |
742 | void pci_disable_msix(struct pci_dev* dev) | |
743 | { | |
744 | if (!pci_msi_enable || !dev || !dev->msix_enabled) | |
745 | return; | |
746 | ||
747 | pci_msix_shutdown(dev); | |
7bd007e4 | 748 | |
fc4afc7b | 749 | msix_free_all_irqs(dev); |
1da177e4 | 750 | } |
4cc086fa | 751 | EXPORT_SYMBOL(pci_disable_msix); |
1da177e4 LT |
752 | |
753 | /** | |
1ce03373 | 754 | * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state |
1da177e4 LT |
755 | * @dev: pointer to the pci_dev data structure of MSI(X) device function |
756 | * | |
eaae4b3a | 757 | * Being called during hotplug remove, from which the device function |
1ce03373 | 758 | * is hot-removed. All previous assigned MSI/MSI-X irqs, if |
1da177e4 LT |
759 | * allocated for this device function, are reclaimed to unused state, |
760 | * which may be used later on. | |
761 | **/ | |
762 | void msi_remove_pci_irq_vectors(struct pci_dev* dev) | |
763 | { | |
1da177e4 LT |
764 | if (!pci_msi_enable || !dev) |
765 | return; | |
766 | ||
032de8e2 ME |
767 | if (dev->msi_enabled) |
768 | msi_free_irqs(dev); | |
1da177e4 | 769 | |
fc4afc7b ME |
770 | if (dev->msix_enabled) |
771 | msix_free_all_irqs(dev); | |
1da177e4 LT |
772 | } |
773 | ||
309e57df MW |
774 | void pci_no_msi(void) |
775 | { | |
776 | pci_msi_enable = 0; | |
777 | } | |
c9953a73 | 778 | |
4aa9bc95 ME |
779 | void pci_msi_init_pci_dev(struct pci_dev *dev) |
780 | { | |
781 | INIT_LIST_HEAD(&dev->msi_list); | |
782 | } | |
d389fec6 TI |
783 | |
784 | #ifdef CONFIG_ACPI | |
785 | #include <linux/acpi.h> | |
786 | #include <linux/pci-acpi.h> | |
787 | static void __devinit msi_acpi_init(void) | |
788 | { | |
789 | if (acpi_pci_disabled) | |
790 | return; | |
791 | pci_osc_support_set(OSC_MSI_SUPPORT); | |
792 | pcie_osc_support_set(OSC_MSI_SUPPORT); | |
793 | } | |
794 | #else | |
795 | static inline void msi_acpi_init(void) { } | |
796 | #endif /* CONFIG_ACPI */ | |
797 | ||
798 | void __devinit msi_init(void) | |
799 | { | |
800 | if (!pci_msi_enable) | |
801 | return; | |
802 | msi_acpi_init(); | |
803 | } |