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Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
1da177e4 | 4 | * |
df62ab5e BH |
5 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
6 | * David Mosberger-Tang | |
1da177e4 | 7 | * |
df62ab5e | 8 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
1da177e4 LT |
9 | */ |
10 | ||
2ab51dde | 11 | #include <linux/acpi.h> |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/delay.h> | |
9d26d3a8 | 14 | #include <linux/dmi.h> |
1da177e4 | 15 | #include <linux/init.h> |
bbd8810d | 16 | #include <linux/msi.h> |
7c674700 | 17 | #include <linux/of.h> |
1da177e4 | 18 | #include <linux/pci.h> |
075c1771 | 19 | #include <linux/pm.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/spinlock.h> | |
4e57b681 | 23 | #include <linux/string.h> |
229f5afd | 24 | #include <linux/log2.h> |
5745392e | 25 | #include <linux/logic_pio.h> |
c300bd2f | 26 | #include <linux/pm_wakeup.h> |
8dd7f803 | 27 | #include <linux/interrupt.h> |
32a9a682 | 28 | #include <linux/device.h> |
b67ea761 | 29 | #include <linux/pm_runtime.h> |
608c3881 | 30 | #include <linux/pci_hotplug.h> |
4d3f1384 | 31 | #include <linux/vmalloc.h> |
2a2aca31 | 32 | #include <asm/dma.h> |
b07461a8 | 33 | #include <linux/aer.h> |
69139244 | 34 | #include <linux/bitfield.h> |
bc56b9e0 | 35 | #include "pci.h" |
1da177e4 | 36 | |
c4eed62a KB |
37 | DEFINE_MUTEX(pci_slot_mutex); |
38 | ||
00240c38 AS |
39 | const char *pci_power_names[] = { |
40 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
41 | }; | |
42 | EXPORT_SYMBOL_GPL(pci_power_names); | |
43 | ||
93177a74 RW |
44 | int isa_dma_bridge_buggy; |
45 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
46 | ||
47 | int pci_pci_problems; | |
48 | EXPORT_SYMBOL(pci_pci_problems); | |
49 | ||
3789af9a | 50 | unsigned int pci_pm_d3hot_delay; |
1ae861e6 | 51 | |
df17e62e MG |
52 | static void pci_pme_list_scan(struct work_struct *work); |
53 | ||
54 | static LIST_HEAD(pci_pme_list); | |
55 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
56 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
57 | ||
58 | struct pci_pme_device { | |
59 | struct list_head list; | |
60 | struct pci_dev *dev; | |
61 | }; | |
62 | ||
63 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
64 | ||
1ae861e6 RW |
65 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
66 | { | |
3789af9a | 67 | unsigned int delay = dev->d3hot_delay; |
1ae861e6 | 68 | |
3789af9a KW |
69 | if (delay < pci_pm_d3hot_delay) |
70 | delay = pci_pm_d3hot_delay; | |
1ae861e6 | 71 | |
50b2b540 AH |
72 | if (delay) |
73 | msleep(delay); | |
1ae861e6 | 74 | } |
1da177e4 | 75 | |
e20afa06 AN |
76 | bool pci_reset_supported(struct pci_dev *dev) |
77 | { | |
78 | return dev->reset_methods[0] != 0; | |
79 | } | |
80 | ||
32a2eea7 JG |
81 | #ifdef CONFIG_PCI_DOMAINS |
82 | int pci_domains_supported = 1; | |
83 | #endif | |
84 | ||
4516a618 AN |
85 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
86 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
87 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
88 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
89 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
90 | ||
28760489 | 91 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
d7b8a217 NJ |
92 | #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024) |
93 | #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024) | |
94 | /* hpiosize=nn can override this */ | |
28760489 | 95 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; |
d7b8a217 NJ |
96 | /* |
97 | * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size, | |
98 | * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size; | |
99 | * pci=hpmemsize=nnM overrides both | |
100 | */ | |
101 | unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE; | |
102 | unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE; | |
28760489 | 103 | |
e16b4660 KB |
104 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
105 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
106 | ||
b0e85c3c JQ |
107 | |
108 | /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */ | |
109 | #ifdef CONFIG_PCIE_BUS_TUNE_OFF | |
110 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
111 | #elif defined CONFIG_PCIE_BUS_SAFE | |
112 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE; | |
113 | #elif defined CONFIG_PCIE_BUS_PERFORMANCE | |
114 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
115 | #elif defined CONFIG_PCIE_BUS_PEER2PEER | |
116 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER; | |
117 | #else | |
27d868b5 | 118 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b0e85c3c | 119 | #endif |
b03e7495 | 120 | |
ac1aa47b JB |
121 | /* |
122 | * The default CLS is used if arch didn't set CLS explicitly and not | |
123 | * all pci devices agree on the same value. Arch can override either | |
124 | * the dfl or actual value as it sees fit. Don't forget this is | |
125 | * measured in 32-bit words, not bytes. | |
126 | */ | |
15856ad5 | 127 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
128 | u8 pci_cache_line_size; |
129 | ||
96c55900 MS |
130 | /* |
131 | * If we set up a device for bus mastering, we need to check the latency | |
132 | * timer as certain BIOSes forget to set it properly. | |
133 | */ | |
134 | unsigned int pcibios_max_latency = 255; | |
135 | ||
6748dcc2 RW |
136 | /* If set, the PCIe ARI capability will not be used. */ |
137 | static bool pcie_ari_disabled; | |
138 | ||
cef74409 GK |
139 | /* If set, the PCIe ATS capability will not be used. */ |
140 | static bool pcie_ats_disabled; | |
141 | ||
11eb0e0e SK |
142 | /* If set, the PCI config space of each device is printed during boot. */ |
143 | bool pci_early_dump; | |
144 | ||
cef74409 GK |
145 | bool pci_ats_disabled(void) |
146 | { | |
147 | return pcie_ats_disabled; | |
148 | } | |
1a373a78 | 149 | EXPORT_SYMBOL_GPL(pci_ats_disabled); |
cef74409 | 150 | |
9d26d3a8 MW |
151 | /* Disable bridge_d3 for all PCIe ports */ |
152 | static bool pci_bridge_d3_disable; | |
153 | /* Force bridge_d3 for all PCIe ports */ | |
154 | static bool pci_bridge_d3_force; | |
155 | ||
156 | static int __init pcie_port_pm_setup(char *str) | |
157 | { | |
158 | if (!strcmp(str, "off")) | |
159 | pci_bridge_d3_disable = true; | |
160 | else if (!strcmp(str, "force")) | |
161 | pci_bridge_d3_force = true; | |
162 | return 1; | |
163 | } | |
164 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
165 | ||
a2758b6b SK |
166 | /* Time to wait after a reset for device to become responsive */ |
167 | #define PCIE_RESET_READY_POLL_MS 60000 | |
168 | ||
ad0f2ad6 CLKA |
169 | static const struct dmi_system_id aspm_fix_whitelist[] = { |
170 | { | |
171 | .ident = "LENOVO Stealth Thinkstation", | |
172 | .matches = { | |
173 | DMI_MATCH(DMI_BIOS_VERSION, "S07K"), | |
174 | }, | |
175 | }, | |
176 | { | |
177 | .ident = "Dell Inc. Precision 7960 Tower", | |
178 | .matches = { | |
179 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
180 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 7960 Tower"), | |
181 | }, | |
182 | }, | |
183 | {} | |
184 | }; | |
185 | ||
1da177e4 LT |
186 | /** |
187 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
188 | * @bus: pointer to PCI bus structure to search | |
189 | * | |
190 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
191 | * including the given PCI bus and its list of child PCI buses. | |
192 | */ | |
07656d83 | 193 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 194 | { |
94e6a9b9 | 195 | struct pci_bus *tmp; |
1da177e4 LT |
196 | unsigned char max, n; |
197 | ||
b918c62e | 198 | max = bus->busn_res.end; |
94e6a9b9 YW |
199 | list_for_each_entry(tmp, &bus->children, node) { |
200 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 201 | if (n > max) |
1da177e4 LT |
202 | max = n; |
203 | } | |
204 | return max; | |
205 | } | |
b82db5ce | 206 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 207 | |
ec5d9e87 HK |
208 | /** |
209 | * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS | |
210 | * @pdev: the PCI device | |
211 | * | |
212 | * Returns error bits set in PCI_STATUS and clears them. | |
213 | */ | |
214 | int pci_status_get_and_clear_errors(struct pci_dev *pdev) | |
215 | { | |
216 | u16 status; | |
217 | int ret; | |
218 | ||
219 | ret = pci_read_config_word(pdev, PCI_STATUS, &status); | |
220 | if (ret != PCIBIOS_SUCCESSFUL) | |
221 | return -EIO; | |
222 | ||
223 | status &= PCI_STATUS_ERROR_BITS; | |
224 | if (status) | |
225 | pci_write_config_word(pdev, PCI_STATUS, status); | |
226 | ||
227 | return status; | |
228 | } | |
229 | EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors); | |
230 | ||
1684f5dd | 231 | #ifdef CONFIG_HAS_IOMEM |
a67462fc KW |
232 | static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar, |
233 | bool write_combine) | |
1684f5dd | 234 | { |
1f7bf3bf | 235 | struct resource *res = &pdev->resource[bar]; |
a67462fc KW |
236 | resource_size_t start = res->start; |
237 | resource_size_t size = resource_size(res); | |
1f7bf3bf | 238 | |
1684f5dd AM |
239 | /* |
240 | * Make sure the BAR is actually a memory resource, not an IO resource | |
241 | */ | |
646c0282 | 242 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
a67462fc | 243 | pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
244 | return NULL; |
245 | } | |
a67462fc KW |
246 | |
247 | if (write_combine) | |
248 | return ioremap_wc(start, size); | |
249 | ||
250 | return ioremap(start, size); | |
251 | } | |
252 | ||
253 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
254 | { | |
255 | return __pci_ioremap_resource(pdev, bar, false); | |
1684f5dd AM |
256 | } |
257 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
258 | |
259 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
260 | { | |
a67462fc | 261 | return __pci_ioremap_resource(pdev, bar, true); |
c43996f4 LR |
262 | } |
263 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
264 | #endif |
265 | ||
45db3370 LG |
266 | /** |
267 | * pci_dev_str_match_path - test if a path string matches a device | |
74356add BH |
268 | * @dev: the PCI device to test |
269 | * @path: string to match the device against | |
45db3370 LG |
270 | * @endptr: pointer to the string after the match |
271 | * | |
272 | * Test if a string (typically from a kernel parameter) formatted as a | |
273 | * path of device/function addresses matches a PCI device. The string must | |
274 | * be of the form: | |
275 | * | |
276 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* | |
277 | * | |
278 | * A path for a device can be obtained using 'lspci -t'. Using a path | |
279 | * is more robust against bus renumbering than using only a single bus, | |
280 | * device and function address. | |
281 | * | |
282 | * Returns 1 if the string matches the device, 0 if it does not and | |
283 | * a negative error code if it fails to parse the string. | |
284 | */ | |
285 | static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, | |
286 | const char **endptr) | |
287 | { | |
288 | int ret; | |
289 | int seg, bus, slot, func; | |
290 | char *wpath, *p; | |
291 | char end; | |
292 | ||
293 | *endptr = strchrnul(path, ';'); | |
294 | ||
7eb6ea41 | 295 | wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); |
45db3370 LG |
296 | if (!wpath) |
297 | return -ENOMEM; | |
298 | ||
299 | while (1) { | |
300 | p = strrchr(wpath, '/'); | |
301 | if (!p) | |
302 | break; | |
303 | ret = sscanf(p, "/%x.%x%c", &slot, &func, &end); | |
304 | if (ret != 2) { | |
305 | ret = -EINVAL; | |
306 | goto free_and_exit; | |
307 | } | |
308 | ||
309 | if (dev->devfn != PCI_DEVFN(slot, func)) { | |
310 | ret = 0; | |
311 | goto free_and_exit; | |
312 | } | |
313 | ||
314 | /* | |
315 | * Note: we don't need to get a reference to the upstream | |
316 | * bridge because we hold a reference to the top level | |
317 | * device which should hold a reference to the bridge, | |
318 | * and so on. | |
319 | */ | |
320 | dev = pci_upstream_bridge(dev); | |
321 | if (!dev) { | |
322 | ret = 0; | |
323 | goto free_and_exit; | |
324 | } | |
325 | ||
326 | *p = 0; | |
327 | } | |
328 | ||
329 | ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot, | |
330 | &func, &end); | |
331 | if (ret != 4) { | |
332 | seg = 0; | |
333 | ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end); | |
334 | if (ret != 3) { | |
335 | ret = -EINVAL; | |
336 | goto free_and_exit; | |
337 | } | |
338 | } | |
339 | ||
340 | ret = (seg == pci_domain_nr(dev->bus) && | |
341 | bus == dev->bus->number && | |
342 | dev->devfn == PCI_DEVFN(slot, func)); | |
343 | ||
344 | free_and_exit: | |
345 | kfree(wpath); | |
346 | return ret; | |
347 | } | |
348 | ||
07d8d7e5 LG |
349 | /** |
350 | * pci_dev_str_match - test if a string matches a device | |
74356add BH |
351 | * @dev: the PCI device to test |
352 | * @p: string to match the device against | |
07d8d7e5 LG |
353 | * @endptr: pointer to the string after the match |
354 | * | |
355 | * Test if a string (typically from a kernel parameter) matches a specified | |
356 | * PCI device. The string may be of one of the following formats: | |
357 | * | |
45db3370 | 358 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* |
07d8d7e5 LG |
359 | * pci:<vendor>:<device>[:<subvendor>:<subdevice>] |
360 | * | |
361 | * The first format specifies a PCI bus/device/function address which | |
362 | * may change if new hardware is inserted, if motherboard firmware changes, | |
363 | * or due to changes caused in kernel parameters. If the domain is | |
45db3370 LG |
364 | * left unspecified, it is taken to be 0. In order to be robust against |
365 | * bus renumbering issues, a path of PCI device/function numbers may be used | |
366 | * to address the specific device. The path for a device can be determined | |
367 | * through the use of 'lspci -t'. | |
07d8d7e5 LG |
368 | * |
369 | * The second format matches devices using IDs in the configuration | |
370 | * space which may match multiple devices in the system. A value of 0 | |
371 | * for any field will match all devices. (Note: this differs from | |
372 | * in-kernel code that uses PCI_ANY_ID which is ~0; this is for | |
373 | * legacy reasons and convenience so users don't have to specify | |
374 | * FFFFFFFFs on the command line.) | |
375 | * | |
376 | * Returns 1 if the string matches the device, 0 if it does not and | |
377 | * a negative error code if the string cannot be parsed. | |
378 | */ | |
379 | static int pci_dev_str_match(struct pci_dev *dev, const char *p, | |
380 | const char **endptr) | |
381 | { | |
382 | int ret; | |
45db3370 | 383 | int count; |
07d8d7e5 LG |
384 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
385 | ||
386 | if (strncmp(p, "pci:", 4) == 0) { | |
387 | /* PCI vendor/device (subvendor/subdevice) IDs are specified */ | |
388 | p += 4; | |
389 | ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device, | |
390 | &subsystem_vendor, &subsystem_device, &count); | |
391 | if (ret != 4) { | |
392 | ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count); | |
393 | if (ret != 2) | |
394 | return -EINVAL; | |
395 | ||
396 | subsystem_vendor = 0; | |
397 | subsystem_device = 0; | |
398 | } | |
399 | ||
400 | p += count; | |
401 | ||
402 | if ((!vendor || vendor == dev->vendor) && | |
403 | (!device || device == dev->device) && | |
404 | (!subsystem_vendor || | |
405 | subsystem_vendor == dev->subsystem_vendor) && | |
406 | (!subsystem_device || | |
407 | subsystem_device == dev->subsystem_device)) | |
408 | goto found; | |
07d8d7e5 | 409 | } else { |
45db3370 LG |
410 | /* |
411 | * PCI Bus, Device, Function IDs are specified | |
74356add | 412 | * (optionally, may include a path of devfns following it) |
45db3370 LG |
413 | */ |
414 | ret = pci_dev_str_match_path(dev, p, &p); | |
415 | if (ret < 0) | |
416 | return ret; | |
417 | else if (ret) | |
07d8d7e5 LG |
418 | goto found; |
419 | } | |
420 | ||
421 | *endptr = p; | |
422 | return 0; | |
423 | ||
424 | found: | |
425 | *endptr = p; | |
426 | return 1; | |
427 | } | |
687d5fe3 | 428 | |
f646c2a0 PM |
429 | static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, |
430 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
431 | { |
432 | u8 id; | |
55db3208 SS |
433 | u16 ent; |
434 | ||
435 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 436 | |
687d5fe3 | 437 | while ((*ttl)--) { |
24a4e377 RD |
438 | if (pos < 0x40) |
439 | break; | |
440 | pos &= ~3; | |
55db3208 SS |
441 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
442 | ||
443 | id = ent & 0xff; | |
24a4e377 RD |
444 | if (id == 0xff) |
445 | break; | |
446 | if (id == cap) | |
447 | return pos; | |
55db3208 | 448 | pos = (ent >> 8); |
24a4e377 RD |
449 | } |
450 | return 0; | |
451 | } | |
452 | ||
f646c2a0 PM |
453 | static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
454 | u8 pos, int cap) | |
687d5fe3 ME |
455 | { |
456 | int ttl = PCI_FIND_CAP_TTL; | |
457 | ||
458 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
459 | } | |
460 | ||
f646c2a0 | 461 | u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
24a4e377 RD |
462 | { |
463 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
464 | pos + PCI_CAP_LIST_NEXT, cap); | |
465 | } | |
466 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
467 | ||
f646c2a0 | 468 | static u8 __pci_bus_find_cap_start(struct pci_bus *bus, |
d3bac118 | 469 | unsigned int devfn, u8 hdr_type) |
1da177e4 LT |
470 | { |
471 | u16 status; | |
1da177e4 LT |
472 | |
473 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
474 | if (!(status & PCI_STATUS_CAP_LIST)) | |
475 | return 0; | |
476 | ||
477 | switch (hdr_type) { | |
478 | case PCI_HEADER_TYPE_NORMAL: | |
479 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 480 | return PCI_CAPABILITY_LIST; |
1da177e4 | 481 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 482 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 483 | } |
d3bac118 ME |
484 | |
485 | return 0; | |
1da177e4 LT |
486 | } |
487 | ||
488 | /** | |
f7625980 | 489 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
490 | * @dev: PCI device to query |
491 | * @cap: capability code | |
492 | * | |
493 | * Tell if a device supports a given PCI capability. | |
494 | * Returns the address of the requested capability structure within the | |
495 | * device's PCI configuration space or 0 in case the device does not | |
74356add | 496 | * support it. Possible values for @cap include: |
1da177e4 | 497 | * |
f7625980 BH |
498 | * %PCI_CAP_ID_PM Power Management |
499 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
500 | * %PCI_CAP_ID_VPD Vital Product Data | |
501 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 502 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 503 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
504 | * %PCI_CAP_ID_PCIX PCI-X |
505 | * %PCI_CAP_ID_EXP PCI Express | |
506 | */ | |
f646c2a0 | 507 | u8 pci_find_capability(struct pci_dev *dev, int cap) |
1da177e4 | 508 | { |
f646c2a0 | 509 | u8 pos; |
d3bac118 ME |
510 | |
511 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
512 | if (pos) | |
513 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
514 | ||
515 | return pos; | |
1da177e4 | 516 | } |
b7fe9434 | 517 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
518 | |
519 | /** | |
f7625980 | 520 | * pci_bus_find_capability - query for devices' capabilities |
74356add | 521 | * @bus: the PCI bus to query |
1da177e4 | 522 | * @devfn: PCI device to query |
74356add | 523 | * @cap: capability code |
1da177e4 | 524 | * |
74356add | 525 | * Like pci_find_capability() but works for PCI devices that do not have a |
f7625980 | 526 | * pci_dev structure set up yet. |
1da177e4 LT |
527 | * |
528 | * Returns the address of the requested capability structure within the | |
529 | * device's PCI configuration space or 0 in case the device does not | |
530 | * support it. | |
531 | */ | |
f646c2a0 | 532 | u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) |
1da177e4 | 533 | { |
f646c2a0 | 534 | u8 hdr_type, pos; |
1da177e4 LT |
535 | |
536 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
537 | ||
d3bac118 ME |
538 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
539 | if (pos) | |
540 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
541 | ||
542 | return pos; | |
1da177e4 | 543 | } |
b7fe9434 | 544 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
545 | |
546 | /** | |
44a9a36f | 547 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 548 | * @dev: PCI device to query |
44a9a36f | 549 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
550 | * @cap: capability code |
551 | * | |
44a9a36f | 552 | * Returns the address of the next matching extended capability structure |
1da177e4 | 553 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
554 | * not support it. Some capabilities can occur several times, e.g., the |
555 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 556 | */ |
ee8b1c47 | 557 | u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) |
1da177e4 LT |
558 | { |
559 | u32 header; | |
557848c3 | 560 | int ttl; |
ee8b1c47 | 561 | u16 pos = PCI_CFG_SPACE_SIZE; |
1da177e4 | 562 | |
557848c3 ZY |
563 | /* minimum 8 bytes per capability */ |
564 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
565 | ||
566 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
567 | return 0; |
568 | ||
44a9a36f BH |
569 | if (start) |
570 | pos = start; | |
571 | ||
1da177e4 LT |
572 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
573 | return 0; | |
574 | ||
575 | /* | |
576 | * If we have no capabilities, this is indicated by cap ID, | |
577 | * cap version and next pointer all being 0. | |
578 | */ | |
579 | if (header == 0) | |
580 | return 0; | |
581 | ||
582 | while (ttl-- > 0) { | |
44a9a36f | 583 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
584 | return pos; |
585 | ||
586 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 587 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
588 | break; |
589 | ||
590 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
591 | break; | |
592 | } | |
593 | ||
594 | return 0; | |
595 | } | |
44a9a36f BH |
596 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
597 | ||
598 | /** | |
599 | * pci_find_ext_capability - Find an extended capability | |
600 | * @dev: PCI device to query | |
601 | * @cap: capability code | |
602 | * | |
603 | * Returns the address of the requested extended capability structure | |
604 | * within the device's PCI configuration space or 0 if the device does | |
74356add | 605 | * not support it. Possible values for @cap include: |
44a9a36f BH |
606 | * |
607 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
608 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
609 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
610 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
611 | */ | |
ee8b1c47 | 612 | u16 pci_find_ext_capability(struct pci_dev *dev, int cap) |
44a9a36f BH |
613 | { |
614 | return pci_find_next_ext_capability(dev, 0, cap); | |
615 | } | |
3a720d72 | 616 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 617 | |
70c0923b JK |
618 | /** |
619 | * pci_get_dsn - Read and return the 8-byte Device Serial Number | |
620 | * @dev: PCI device to query | |
621 | * | |
622 | * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial | |
623 | * Number. | |
624 | * | |
625 | * Returns the DSN, or zero if the capability does not exist. | |
626 | */ | |
627 | u64 pci_get_dsn(struct pci_dev *dev) | |
628 | { | |
629 | u32 dword; | |
630 | u64 dsn; | |
631 | int pos; | |
632 | ||
633 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN); | |
634 | if (!pos) | |
635 | return 0; | |
636 | ||
637 | /* | |
638 | * The Device Serial Number is two dwords offset 4 bytes from the | |
639 | * capability position. The specification says that the first dword is | |
640 | * the lower half, and the second dword is the upper half. | |
641 | */ | |
642 | pos += 4; | |
643 | pci_read_config_dword(dev, pos, &dword); | |
644 | dsn = (u64)dword; | |
645 | pci_read_config_dword(dev, pos + 4, &dword); | |
646 | dsn |= ((u64)dword) << 32; | |
647 | ||
648 | return dsn; | |
649 | } | |
650 | EXPORT_SYMBOL_GPL(pci_get_dsn); | |
651 | ||
f646c2a0 | 652 | static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) |
687d5fe3 ME |
653 | { |
654 | int rc, ttl = PCI_FIND_CAP_TTL; | |
655 | u8 cap, mask; | |
656 | ||
657 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
658 | mask = HT_3BIT_CAP_MASK; | |
659 | else | |
660 | mask = HT_5BIT_CAP_MASK; | |
661 | ||
662 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
663 | PCI_CAP_ID_HT, &ttl); | |
664 | while (pos) { | |
665 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
666 | if (rc != PCIBIOS_SUCCESSFUL) | |
667 | return 0; | |
668 | ||
669 | if ((cap & mask) == ht_cap) | |
670 | return pos; | |
671 | ||
47a4d5be BG |
672 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
673 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
674 | PCI_CAP_ID_HT, &ttl); |
675 | } | |
676 | ||
677 | return 0; | |
678 | } | |
f646c2a0 | 679 | |
687d5fe3 | 680 | /** |
f646c2a0 | 681 | * pci_find_next_ht_capability - query a device's HyperTransport capabilities |
687d5fe3 ME |
682 | * @dev: PCI device to query |
683 | * @pos: Position from which to continue searching | |
f646c2a0 | 684 | * @ht_cap: HyperTransport capability code |
687d5fe3 ME |
685 | * |
686 | * To be used in conjunction with pci_find_ht_capability() to search for | |
687 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
688 | * from pci_find_ht_capability(). | |
689 | * | |
690 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
691 | * steps to avoid an infinite loop. | |
692 | */ | |
f646c2a0 | 693 | u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap) |
687d5fe3 ME |
694 | { |
695 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
696 | } | |
697 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
698 | ||
699 | /** | |
f646c2a0 | 700 | * pci_find_ht_capability - query a device's HyperTransport capabilities |
687d5fe3 | 701 | * @dev: PCI device to query |
f646c2a0 | 702 | * @ht_cap: HyperTransport capability code |
687d5fe3 | 703 | * |
f646c2a0 | 704 | * Tell if a device supports a given HyperTransport capability. |
687d5fe3 ME |
705 | * Returns an address within the device's PCI configuration space |
706 | * or 0 in case the device does not support the request capability. | |
707 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
f646c2a0 | 708 | * which has a HyperTransport capability matching @ht_cap. |
687d5fe3 | 709 | */ |
f646c2a0 | 710 | u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap) |
687d5fe3 | 711 | { |
f646c2a0 | 712 | u8 pos; |
687d5fe3 ME |
713 | |
714 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
715 | if (pos) | |
716 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
717 | ||
718 | return pos; | |
719 | } | |
720 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
721 | ||
c124fd9a GP |
722 | /** |
723 | * pci_find_vsec_capability - Find a vendor-specific extended capability | |
724 | * @dev: PCI device to query | |
725 | * @vendor: Vendor ID for which capability is defined | |
726 | * @cap: Vendor-specific capability ID | |
727 | * | |
728 | * If @dev has Vendor ID @vendor, search for a VSEC capability with | |
729 | * VSEC ID @cap. If found, return the capability offset in | |
730 | * config space; otherwise return 0. | |
731 | */ | |
732 | u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap) | |
733 | { | |
734 | u16 vsec = 0; | |
735 | u32 header; | |
736 | ||
737 | if (vendor != dev->vendor) | |
738 | return 0; | |
739 | ||
740 | while ((vsec = pci_find_next_ext_capability(dev, vsec, | |
741 | PCI_EXT_CAP_ID_VNDR))) { | |
742 | if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, | |
743 | &header) == PCIBIOS_SUCCESSFUL && | |
744 | PCI_VNDR_HEADER_ID(header) == cap) | |
745 | return vsec; | |
746 | } | |
747 | ||
748 | return 0; | |
749 | } | |
750 | EXPORT_SYMBOL_GPL(pci_find_vsec_capability); | |
751 | ||
1da177e4 | 752 | /** |
74356add BH |
753 | * pci_find_parent_resource - return resource region of parent bus of given |
754 | * region | |
1da177e4 LT |
755 | * @dev: PCI device structure contains resources to be searched |
756 | * @res: child resource record for which parent is sought | |
757 | * | |
74356add BH |
758 | * For given resource region of given device, return the resource region of |
759 | * parent bus the given region is contained in. | |
1da177e4 | 760 | */ |
3c78bc61 RD |
761 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
762 | struct resource *res) | |
1da177e4 LT |
763 | { |
764 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 765 | struct resource *r; |
1da177e4 | 766 | int i; |
1da177e4 | 767 | |
89a74ecc | 768 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
769 | if (!r) |
770 | continue; | |
31342330 | 771 | if (resource_contains(r, res)) { |
f44116ae BH |
772 | |
773 | /* | |
774 | * If the window is prefetchable but the BAR is | |
775 | * not, the allocator made a mistake. | |
776 | */ | |
777 | if (r->flags & IORESOURCE_PREFETCH && | |
778 | !(res->flags & IORESOURCE_PREFETCH)) | |
779 | return NULL; | |
780 | ||
781 | /* | |
782 | * If we're below a transparent bridge, there may | |
783 | * be both a positively-decoded aperture and a | |
784 | * subtractively-decoded region that contain the BAR. | |
785 | * We want the positively-decoded one, so this depends | |
786 | * on pci_bus_for_each_resource() giving us those | |
787 | * first. | |
788 | */ | |
789 | return r; | |
790 | } | |
1da177e4 | 791 | } |
f44116ae | 792 | return NULL; |
1da177e4 | 793 | } |
b7fe9434 | 794 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 795 | |
afd29f90 MW |
796 | /** |
797 | * pci_find_resource - Return matching PCI device resource | |
798 | * @dev: PCI device to query | |
799 | * @res: Resource to look for | |
800 | * | |
801 | * Goes over standard PCI resources (BARs) and checks if the given resource | |
802 | * is partially or fully contained in any of them. In that case the | |
803 | * matching resource is returned, %NULL otherwise. | |
804 | */ | |
805 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) | |
806 | { | |
807 | int i; | |
808 | ||
c9c13ba4 | 809 | for (i = 0; i < PCI_STD_NUM_BARS; i++) { |
afd29f90 MW |
810 | struct resource *r = &dev->resource[i]; |
811 | ||
812 | if (r->start && resource_contains(r, res)) | |
813 | return r; | |
814 | } | |
815 | ||
816 | return NULL; | |
817 | } | |
818 | EXPORT_SYMBOL(pci_find_resource); | |
819 | ||
157e876f AW |
820 | /** |
821 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
822 | * @dev: the PCI device to operate on | |
823 | * @pos: config space offset of status word | |
824 | * @mask: mask of bit(s) to care about in status word | |
825 | * | |
826 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
827 | */ | |
828 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
829 | { | |
830 | int i; | |
831 | ||
832 | /* Wait for Transaction Pending bit clean */ | |
833 | for (i = 0; i < 4; i++) { | |
834 | u16 status; | |
835 | if (i) | |
836 | msleep((1 << (i - 1)) * 100); | |
837 | ||
838 | pci_read_config_word(dev, pos, &status); | |
839 | if (!(status & mask)) | |
840 | return 1; | |
841 | } | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
cbe42036 RJ |
846 | static int pci_acs_enable; |
847 | ||
848 | /** | |
849 | * pci_request_acs - ask for ACS to be enabled if supported | |
850 | */ | |
851 | void pci_request_acs(void) | |
852 | { | |
853 | pci_acs_enable = 1; | |
854 | } | |
855 | ||
856 | static const char *disable_acs_redir_param; | |
857 | ||
858 | /** | |
859 | * pci_disable_acs_redir - disable ACS redirect capabilities | |
860 | * @dev: the PCI device | |
861 | * | |
862 | * For only devices specified in the disable_acs_redir parameter. | |
863 | */ | |
864 | static void pci_disable_acs_redir(struct pci_dev *dev) | |
865 | { | |
866 | int ret = 0; | |
867 | const char *p; | |
868 | int pos; | |
869 | u16 ctrl; | |
870 | ||
871 | if (!disable_acs_redir_param) | |
872 | return; | |
873 | ||
874 | p = disable_acs_redir_param; | |
875 | while (*p) { | |
876 | ret = pci_dev_str_match(dev, p, &p); | |
877 | if (ret < 0) { | |
878 | pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n", | |
879 | disable_acs_redir_param); | |
880 | ||
881 | break; | |
882 | } else if (ret == 1) { | |
883 | /* Found a match */ | |
884 | break; | |
885 | } | |
886 | ||
887 | if (*p != ';' && *p != ',') { | |
888 | /* End of param or invalid format */ | |
889 | break; | |
890 | } | |
891 | p++; | |
892 | } | |
893 | ||
894 | if (ret != 1) | |
895 | return; | |
896 | ||
897 | if (!pci_dev_specific_disable_acs_redir(dev)) | |
898 | return; | |
899 | ||
52fbf5bd | 900 | pos = dev->acs_cap; |
cbe42036 RJ |
901 | if (!pos) { |
902 | pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n"); | |
903 | return; | |
904 | } | |
905 | ||
906 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
907 | ||
908 | /* P2P Request & Completion Redirect */ | |
909 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); | |
910 | ||
911 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
912 | ||
913 | pci_info(dev, "disabled ACS redirect\n"); | |
914 | } | |
915 | ||
916 | /** | |
917 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities | |
918 | * @dev: the PCI device | |
919 | */ | |
920 | static void pci_std_enable_acs(struct pci_dev *dev) | |
921 | { | |
922 | int pos; | |
923 | u16 cap; | |
924 | u16 ctrl; | |
925 | ||
52fbf5bd | 926 | pos = dev->acs_cap; |
cbe42036 RJ |
927 | if (!pos) |
928 | return; | |
929 | ||
930 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
931 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
932 | ||
933 | /* Source Validation */ | |
934 | ctrl |= (cap & PCI_ACS_SV); | |
935 | ||
936 | /* P2P Request Redirect */ | |
937 | ctrl |= (cap & PCI_ACS_RR); | |
938 | ||
939 | /* P2P Completion Redirect */ | |
940 | ctrl |= (cap & PCI_ACS_CR); | |
941 | ||
942 | /* Upstream Forwarding */ | |
943 | ctrl |= (cap & PCI_ACS_UF); | |
944 | ||
7cae7849 AW |
945 | /* Enable Translation Blocking for external devices and noats */ |
946 | if (pci_ats_disabled() || dev->external_facing || dev->untrusted) | |
76fc8e85 RJ |
947 | ctrl |= (cap & PCI_ACS_TB); |
948 | ||
cbe42036 RJ |
949 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); |
950 | } | |
951 | ||
952 | /** | |
953 | * pci_enable_acs - enable ACS if hardware support it | |
954 | * @dev: the PCI device | |
955 | */ | |
52fbf5bd | 956 | static void pci_enable_acs(struct pci_dev *dev) |
cbe42036 RJ |
957 | { |
958 | if (!pci_acs_enable) | |
959 | goto disable_acs_redir; | |
960 | ||
961 | if (!pci_dev_specific_enable_acs(dev)) | |
962 | goto disable_acs_redir; | |
963 | ||
964 | pci_std_enable_acs(dev); | |
965 | ||
966 | disable_acs_redir: | |
967 | /* | |
968 | * Note: pci_disable_acs_redir() must be called even if ACS was not | |
969 | * enabled by the kernel because it may have been enabled by | |
970 | * platform firmware. So if we are told to disable it, we should | |
971 | * always disable it after setting the kernel's default | |
972 | * preferences. | |
973 | */ | |
974 | pci_disable_acs_redir(dev); | |
975 | } | |
976 | ||
064b53db | 977 | /** |
70675e0b | 978 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
979 | * @dev: PCI device to have its BARs restored |
980 | * | |
981 | * Restore the BAR values for a given device, so as to make it | |
982 | * accessible by its driver. | |
983 | */ | |
3c78bc61 | 984 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 985 | { |
bc5f5a82 | 986 | int i; |
064b53db | 987 | |
bc5f5a82 | 988 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 989 | pci_update_resource(dev, i); |
064b53db JL |
990 | } |
991 | ||
299f2ffe | 992 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 993 | |
299f2ffe | 994 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 995 | { |
cc7cc02b | 996 | if (!ops->is_manageable || !ops->set_state || !ops->get_state || |
0847684c | 997 | !ops->choose_state || !ops->set_wakeup || !ops->need_resume) |
961d9120 RW |
998 | return -EINVAL; |
999 | pci_platform_pm = ops; | |
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
1004 | { | |
1005 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
1006 | } | |
1007 | ||
1008 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 1009 | pci_power_t t) |
961d9120 RW |
1010 | { |
1011 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
1012 | } | |
1013 | ||
cc7cc02b LW |
1014 | static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) |
1015 | { | |
1016 | return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; | |
1017 | } | |
1018 | ||
b51033e0 RW |
1019 | static inline void platform_pci_refresh_power_state(struct pci_dev *dev) |
1020 | { | |
1021 | if (pci_platform_pm && pci_platform_pm->refresh_state) | |
1022 | pci_platform_pm->refresh_state(dev); | |
1023 | } | |
1024 | ||
961d9120 RW |
1025 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
1026 | { | |
1027 | return pci_platform_pm ? | |
1028 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
1029 | } | |
8f7020d3 | 1030 | |
0847684c | 1031 | static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1032 | { |
1033 | return pci_platform_pm ? | |
0847684c | 1034 | pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; |
b67ea761 RW |
1035 | } |
1036 | ||
bac2a909 RW |
1037 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
1038 | { | |
1039 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
1040 | } | |
1041 | ||
26ad34d5 MW |
1042 | static inline bool platform_pci_bridge_d3(struct pci_dev *dev) |
1043 | { | |
c3aaf086 BH |
1044 | if (pci_platform_pm && pci_platform_pm->bridge_d3) |
1045 | return pci_platform_pm->bridge_d3(dev); | |
1046 | return false; | |
26ad34d5 MW |
1047 | } |
1048 | ||
1da177e4 | 1049 | /** |
44e4e66e | 1050 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
74356add | 1051 | * given PCI device |
44e4e66e | 1052 | * @dev: PCI device to handle. |
44e4e66e | 1053 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 1054 | * |
44e4e66e RW |
1055 | * RETURN VALUE: |
1056 | * -EINVAL if the requested state is invalid. | |
1057 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
1058 | * wrong version, or device doesn't support the requested state. | |
1059 | * 0 if device already is in the requested state. | |
1060 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 1061 | */ |
f00a20ef | 1062 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 1063 | { |
337001b6 | 1064 | u16 pmcsr; |
44e4e66e | 1065 | bool need_restore = false; |
1da177e4 | 1066 | |
4a865905 RW |
1067 | /* Check if we're already there */ |
1068 | if (dev->current_state == state) | |
1069 | return 0; | |
1070 | ||
337001b6 | 1071 | if (!dev->pm_cap) |
cca03dec AL |
1072 | return -EIO; |
1073 | ||
44e4e66e RW |
1074 | if (state < PCI_D0 || state > PCI_D3hot) |
1075 | return -EINVAL; | |
1076 | ||
74356add | 1077 | /* |
e43f15ea BH |
1078 | * Validate transition: We can enter D0 from any state, but if |
1079 | * we're already in a low-power state, we can only go deeper. E.g., | |
1080 | * we can go from D1 to D3, but we can't go directly from D3 to D1; | |
1081 | * we'd have to go from D3 to D0, then to D1. | |
1da177e4 | 1082 | */ |
4a865905 | 1083 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 1084 | && dev->current_state > state) { |
e43f15ea BH |
1085 | pci_err(dev, "invalid power transition (from %s to %s)\n", |
1086 | pci_power_name(dev->current_state), | |
1087 | pci_power_name(state)); | |
1da177e4 | 1088 | return -EINVAL; |
44e4e66e | 1089 | } |
1da177e4 | 1090 | |
74356add | 1091 | /* Check if this device supports the desired state */ |
337001b6 RW |
1092 | if ((state == PCI_D1 && !dev->d1_support) |
1093 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 1094 | return -EIO; |
1da177e4 | 1095 | |
337001b6 | 1096 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
327ccbbc BH |
1097 | if (pmcsr == (u16) ~0) { |
1098 | pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n", | |
1099 | pci_power_name(dev->current_state), | |
1100 | pci_power_name(state)); | |
1101 | return -EIO; | |
1102 | } | |
064b53db | 1103 | |
74356add BH |
1104 | /* |
1105 | * If we're (effectively) in D3, force entire word to 0. | |
1da177e4 LT |
1106 | * This doesn't affect PME_Status, disables PME_En, and |
1107 | * sets PowerState to 0. | |
1108 | */ | |
32a36585 | 1109 | switch (dev->current_state) { |
d3535fbb JL |
1110 | case PCI_D0: |
1111 | case PCI_D1: | |
1112 | case PCI_D2: | |
1113 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
1114 | pmcsr |= state; | |
1115 | break; | |
f62795f1 RW |
1116 | case PCI_D3hot: |
1117 | case PCI_D3cold: | |
32a36585 JL |
1118 | case PCI_UNKNOWN: /* Boot-up */ |
1119 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 1120 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 1121 | need_restore = true; |
df561f66 | 1122 | fallthrough; /* force to D0 */ |
32a36585 | 1123 | default: |
d3535fbb | 1124 | pmcsr = 0; |
32a36585 | 1125 | break; |
1da177e4 LT |
1126 | } |
1127 | ||
74356add | 1128 | /* Enter specified state */ |
337001b6 | 1129 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 | 1130 | |
74356add BH |
1131 | /* |
1132 | * Mandatory power management transition delays; see PCI PM 1.1 | |
1133 | * 5.6.1 table 18 | |
1134 | */ | |
1da177e4 | 1135 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
1ae861e6 | 1136 | pci_dev_d3_sleep(dev); |
1da177e4 | 1137 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
638c133e | 1138 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 1139 | |
e13cdbd7 RW |
1140 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
1141 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
7f1c62c4 | 1142 | if (dev->current_state != state) |
e43f15ea BH |
1143 | pci_info_ratelimited(dev, "refused to change power state from %s to %s\n", |
1144 | pci_power_name(dev->current_state), | |
1145 | pci_power_name(state)); | |
064b53db | 1146 | |
448bd857 HY |
1147 | /* |
1148 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
1149 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
1150 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
1151 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
1152 | * For example, at least some versions of the 3c905B and the | |
1153 | * 3c556B exhibit this behaviour. | |
1154 | * | |
1155 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
1156 | * devices in a D3hot state at boot. Consequently, we need to | |
1157 | * restore at least the BARs so that the device will be | |
1158 | * accessible to its driver. | |
1159 | */ | |
1160 | if (need_restore) | |
1161 | pci_restore_bars(dev); | |
1162 | ||
ad0f2ad6 | 1163 | if (dev->bus->self && !dmi_check_system(aspm_fix_whitelist)) |
7d715a6c SL |
1164 | pcie_aspm_pm_state_change(dev->bus->self); |
1165 | ||
1da177e4 LT |
1166 | return 0; |
1167 | } | |
1168 | ||
44e4e66e | 1169 | /** |
a6a64026 | 1170 | * pci_update_current_state - Read power state of given device and cache it |
44e4e66e | 1171 | * @dev: PCI device to handle. |
f06fc0b6 | 1172 | * @state: State to cache in case the device doesn't have the PM capability |
a6a64026 LW |
1173 | * |
1174 | * The power state is read from the PMCSR register, which however is | |
1175 | * inaccessible in D3cold. The platform firmware is therefore queried first | |
1176 | * to detect accessibility of the register. In case the platform firmware | |
1177 | * reports an incorrect state or the device isn't power manageable by the | |
1178 | * platform at all, we try to detect D3cold by testing accessibility of the | |
1179 | * vendor ID in config space. | |
44e4e66e | 1180 | */ |
73410429 | 1181 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 1182 | { |
a6a64026 LW |
1183 | if (platform_pci_get_power_state(dev) == PCI_D3cold || |
1184 | !pci_device_is_present(dev)) { | |
1185 | dev->current_state = PCI_D3cold; | |
1186 | } else if (dev->pm_cap) { | |
44e4e66e RW |
1187 | u16 pmcsr; |
1188 | ||
337001b6 | 1189 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 1190 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
1191 | } else { |
1192 | dev->current_state = state; | |
44e4e66e RW |
1193 | } |
1194 | } | |
1195 | ||
b51033e0 RW |
1196 | /** |
1197 | * pci_refresh_power_state - Refresh the given device's power state data | |
1198 | * @dev: Target PCI device. | |
1199 | * | |
1200 | * Ask the platform to refresh the devices power state information and invoke | |
1201 | * pci_update_current_state() to update its current PCI power state. | |
1202 | */ | |
1203 | void pci_refresh_power_state(struct pci_dev *dev) | |
1204 | { | |
1205 | if (platform_pci_power_manageable(dev)) | |
1206 | platform_pci_refresh_power_state(dev); | |
1207 | ||
1208 | pci_update_current_state(dev, dev->current_state); | |
1209 | } | |
1210 | ||
0e5dd46b RW |
1211 | /** |
1212 | * pci_platform_power_transition - Use platform to change device power state | |
1213 | * @dev: PCI device to handle. | |
1214 | * @state: State to put the device into. | |
1215 | */ | |
d6aa37cd | 1216 | int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) |
0e5dd46b RW |
1217 | { |
1218 | int error; | |
1219 | ||
1220 | if (platform_pci_power_manageable(dev)) { | |
1221 | error = platform_pci_set_power_state(dev, state); | |
1222 | if (!error) | |
1223 | pci_update_current_state(dev, state); | |
769ba721 | 1224 | } else |
0e5dd46b | 1225 | error = -ENODEV; |
769ba721 RW |
1226 | |
1227 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
1228 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
1229 | |
1230 | return error; | |
1231 | } | |
d6aa37cd | 1232 | EXPORT_SYMBOL_GPL(pci_platform_power_transition); |
0e5dd46b | 1233 | |
99efde6c | 1234 | static int pci_resume_one(struct pci_dev *pci_dev, void *ign) |
0b950f0f | 1235 | { |
0b950f0f SH |
1236 | pm_request_resume(&pci_dev->dev); |
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | /** | |
99efde6c | 1241 | * pci_resume_bus - Walk given bus and runtime resume devices on it |
0b950f0f SH |
1242 | * @bus: Top bus of the subtree to walk. |
1243 | */ | |
99efde6c | 1244 | void pci_resume_bus(struct pci_bus *bus) |
0b950f0f SH |
1245 | { |
1246 | if (bus) | |
99efde6c | 1247 | pci_walk_bus(bus, pci_resume_one, NULL); |
0b950f0f SH |
1248 | } |
1249 | ||
bae26849 VS |
1250 | static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) |
1251 | { | |
1252 | int delay = 1; | |
1253 | u32 id; | |
1254 | ||
1255 | /* | |
1256 | * After reset, the device should not silently discard config | |
1257 | * requests, but it may still indicate that it needs more time by | |
1258 | * responding to them with CRS completions. The Root Port will | |
1259 | * generally synthesize ~0 data to complete the read (except when | |
1260 | * CRS SV is enabled and the read was for the Vendor ID; in that | |
1261 | * case it synthesizes 0x0001 data). | |
1262 | * | |
1263 | * Wait for the device to return a non-CRS completion. Read the | |
1264 | * Command register instead of Vendor ID so we don't have to | |
1265 | * contend with the CRS SV value. | |
1266 | */ | |
1267 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
1268 | while (id == ~0) { | |
1269 | if (delay > timeout) { | |
1270 | pci_warn(dev, "not ready %dms after %s; giving up\n", | |
1271 | delay - 1, reset_type); | |
1272 | return -ENOTTY; | |
1273 | } | |
1274 | ||
1275 | if (delay > 1000) | |
1276 | pci_info(dev, "not ready %dms after %s; waiting\n", | |
1277 | delay - 1, reset_type); | |
1278 | ||
1279 | msleep(delay); | |
1280 | delay *= 2; | |
1281 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
1282 | } | |
1283 | ||
1284 | if (delay > 1000) | |
1285 | pci_info(dev, "ready %dms after %s\n", delay - 1, | |
1286 | reset_type); | |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
0e5dd46b | 1291 | /** |
dc2256b0 RW |
1292 | * pci_power_up - Put the given device into D0 |
1293 | * @dev: PCI device to power up | |
0e5dd46b | 1294 | */ |
dc2256b0 | 1295 | int pci_power_up(struct pci_dev *dev) |
0e5dd46b | 1296 | { |
dc2256b0 RW |
1297 | pci_platform_power_transition(dev, PCI_D0); |
1298 | ||
1299 | /* | |
ad9001f2 MW |
1300 | * Mandatory power management transition delays are handled in |
1301 | * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the | |
1302 | * corresponding bridge. | |
dc2256b0 RW |
1303 | */ |
1304 | if (dev->runtime_d3cold) { | |
448bd857 | 1305 | /* |
dc2256b0 RW |
1306 | * When powering on a bridge from D3cold, the whole hierarchy |
1307 | * may be powered on into D0uninitialized state, resume them to | |
1308 | * give them a chance to suspend again | |
448bd857 | 1309 | */ |
99efde6c | 1310 | pci_resume_bus(dev->subordinate); |
448bd857 | 1311 | } |
448bd857 | 1312 | |
adfac8f6 | 1313 | return pci_raw_set_power_state(dev, PCI_D0); |
448bd857 HY |
1314 | } |
1315 | ||
1316 | /** | |
1317 | * __pci_dev_set_current_state - Set current state of a PCI device | |
1318 | * @dev: Device to handle | |
1319 | * @data: pointer to state to be set | |
1320 | */ | |
1321 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
1322 | { | |
1323 | pci_power_t state = *(pci_power_t *)data; | |
1324 | ||
1325 | dev->current_state = state; | |
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | /** | |
2a4d2c42 | 1330 | * pci_bus_set_current_state - Walk given bus and set current state of devices |
448bd857 HY |
1331 | * @bus: Top bus of the subtree to walk. |
1332 | * @state: state to be set | |
1333 | */ | |
2a4d2c42 | 1334 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) |
448bd857 HY |
1335 | { |
1336 | if (bus) | |
1337 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
1338 | } |
1339 | ||
44e4e66e RW |
1340 | /** |
1341 | * pci_set_power_state - Set the power state of a PCI device | |
1342 | * @dev: PCI device to handle. | |
1343 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
1344 | * | |
877d0310 | 1345 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
1346 | * the device's PCI PM registers. |
1347 | * | |
1348 | * RETURN VALUE: | |
1349 | * -EINVAL if the requested state is invalid. | |
1350 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
1351 | * wrong version, or device doesn't support the requested state. | |
ab4b8a47 | 1352 | * 0 if the transition is to D1 or D2 but D1 and D2 are not supported. |
44e4e66e | 1353 | * 0 if device already is in the requested state. |
ab4b8a47 | 1354 | * 0 if the transition is to D3 but D3 is not supported. |
44e4e66e RW |
1355 | * 0 if device's power state has been successfully changed. |
1356 | */ | |
1357 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
1358 | { | |
337001b6 | 1359 | int error; |
44e4e66e | 1360 | |
74356add | 1361 | /* Bound the state we're entering */ |
448bd857 HY |
1362 | if (state > PCI_D3cold) |
1363 | state = PCI_D3cold; | |
44e4e66e RW |
1364 | else if (state < PCI_D0) |
1365 | state = PCI_D0; | |
1366 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
74356add | 1367 | |
44e4e66e | 1368 | /* |
74356add BH |
1369 | * If the device or the parent bridge do not support PCI |
1370 | * PM, ignore the request if we're doing anything other | |
1371 | * than putting it into D0 (which would only happen on | |
1372 | * boot). | |
44e4e66e RW |
1373 | */ |
1374 | return 0; | |
1375 | ||
db288c9c RW |
1376 | /* Check if we're already there */ |
1377 | if (dev->current_state == state) | |
1378 | return 0; | |
1379 | ||
adfac8f6 RW |
1380 | if (state == PCI_D0) |
1381 | return pci_power_up(dev); | |
0e5dd46b | 1382 | |
74356add BH |
1383 | /* |
1384 | * This device is quirked not to be put into D3, so don't put it in | |
1385 | * D3 | |
1386 | */ | |
448bd857 | 1387 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 1388 | return 0; |
44e4e66e | 1389 | |
448bd857 HY |
1390 | /* |
1391 | * To put device in D3cold, we put device into D3hot in native | |
1392 | * way, then put device into D3cold with platform ops | |
1393 | */ | |
1394 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
1395 | PCI_D3hot : state); | |
44e4e66e | 1396 | |
9c77e63b RW |
1397 | if (pci_platform_power_transition(dev, state)) |
1398 | return error; | |
44e4e66e | 1399 | |
9c77e63b RW |
1400 | /* Powering off a bridge may power off the whole hierarchy */ |
1401 | if (state == PCI_D3cold) | |
1402 | pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
44e4e66e | 1403 | |
9c77e63b | 1404 | return 0; |
45144d42 | 1405 | } |
b7fe9434 | 1406 | EXPORT_SYMBOL(pci_set_power_state); |
45144d42 | 1407 | |
1da177e4 LT |
1408 | /** |
1409 | * pci_choose_state - Choose the power state of a PCI device | |
1410 | * @dev: PCI device to be suspended | |
1411 | * @state: target sleep state for the whole system. This is the value | |
74356add | 1412 | * that is passed to suspend() function. |
1da177e4 LT |
1413 | * |
1414 | * Returns PCI power state suitable for given device and given system | |
1415 | * message. | |
1416 | */ | |
1da177e4 LT |
1417 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) |
1418 | { | |
ab826ca4 | 1419 | pci_power_t ret; |
0f64474b | 1420 | |
728cdb75 | 1421 | if (!dev->pm_cap) |
1da177e4 LT |
1422 | return PCI_D0; |
1423 | ||
961d9120 RW |
1424 | ret = platform_pci_choose_state(dev); |
1425 | if (ret != PCI_POWER_ERROR) | |
1426 | return ret; | |
ca078bae PM |
1427 | |
1428 | switch (state.event) { | |
1429 | case PM_EVENT_ON: | |
1430 | return PCI_D0; | |
1431 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
1432 | case PM_EVENT_PRETHAW: |
1433 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 1434 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 1435 | case PM_EVENT_HIBERNATE: |
ca078bae | 1436 | return PCI_D3hot; |
1da177e4 | 1437 | default: |
7506dc79 | 1438 | pci_info(dev, "unrecognized suspend event %d\n", |
80ccba11 | 1439 | state.event); |
1da177e4 LT |
1440 | BUG(); |
1441 | } | |
1442 | return PCI_D0; | |
1443 | } | |
1da177e4 LT |
1444 | EXPORT_SYMBOL(pci_choose_state); |
1445 | ||
89858517 YZ |
1446 | #define PCI_EXP_SAVE_REGS 7 |
1447 | ||
fd0f7f73 AW |
1448 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
1449 | u16 cap, bool extended) | |
34a4876e YL |
1450 | { |
1451 | struct pci_cap_saved_state *tmp; | |
34a4876e | 1452 | |
b67bfe0d | 1453 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 1454 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
1455 | return tmp; |
1456 | } | |
1457 | return NULL; | |
1458 | } | |
1459 | ||
fd0f7f73 AW |
1460 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
1461 | { | |
1462 | return _pci_find_saved_cap(dev, cap, false); | |
1463 | } | |
1464 | ||
1465 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
1466 | { | |
1467 | return _pci_find_saved_cap(dev, cap, true); | |
1468 | } | |
1469 | ||
b56a5a23 MT |
1470 | static int pci_save_pcie_state(struct pci_dev *dev) |
1471 | { | |
59875ae4 | 1472 | int i = 0; |
b56a5a23 MT |
1473 | struct pci_cap_saved_state *save_state; |
1474 | u16 *cap; | |
1475 | ||
59875ae4 | 1476 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
1477 | return 0; |
1478 | ||
9f35575d | 1479 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 1480 | if (!save_state) { |
7506dc79 | 1481 | pci_err(dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
1482 | return -ENOMEM; |
1483 | } | |
63f4898a | 1484 | |
59875ae4 JL |
1485 | cap = (u16 *)&save_state->cap.data[0]; |
1486 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
1487 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1488 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1489 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1490 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1491 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1492 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1493 | |
b56a5a23 MT |
1494 | return 0; |
1495 | } | |
1496 | ||
fa564a02 MQ |
1497 | void pci_bridge_reconfigure_ltr(struct pci_dev *dev) |
1498 | { | |
1499 | #ifdef CONFIG_PCIEASPM | |
1500 | struct pci_dev *bridge; | |
1501 | u32 ctl; | |
1502 | ||
1503 | bridge = pci_upstream_bridge(dev); | |
1504 | if (bridge && bridge->ltr_path) { | |
1505 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl); | |
1506 | if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) { | |
1507 | pci_dbg(bridge, "re-enabling LTR\n"); | |
1508 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
1509 | PCI_EXP_DEVCTL2_LTR_EN); | |
1510 | } | |
1511 | } | |
1512 | #endif | |
1513 | } | |
1514 | ||
b56a5a23 MT |
1515 | static void pci_restore_pcie_state(struct pci_dev *dev) |
1516 | { | |
59875ae4 | 1517 | int i = 0; |
b56a5a23 MT |
1518 | struct pci_cap_saved_state *save_state; |
1519 | u16 *cap; | |
1520 | ||
1521 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1522 | if (!save_state) |
9cb604ed MS |
1523 | return; |
1524 | ||
fa564a02 MQ |
1525 | /* |
1526 | * Downstream ports reset the LTR enable bit when link goes down. | |
1527 | * Check and re-configure the bit here before restoring device. | |
1528 | * PCIe r5.0, sec 7.5.3.16. | |
1529 | */ | |
1530 | pci_bridge_reconfigure_ltr(dev); | |
1531 | ||
59875ae4 JL |
1532 | cap = (u16 *)&save_state->cap.data[0]; |
1533 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1534 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1535 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1536 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1537 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1538 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1539 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1540 | } |
1541 | ||
cc692a5f SH |
1542 | static int pci_save_pcix_state(struct pci_dev *dev) |
1543 | { | |
63f4898a | 1544 | int pos; |
cc692a5f | 1545 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1546 | |
1547 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1548 | if (!pos) |
cc692a5f SH |
1549 | return 0; |
1550 | ||
f34303de | 1551 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1552 | if (!save_state) { |
7506dc79 | 1553 | pci_err(dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1554 | return -ENOMEM; |
1555 | } | |
cc692a5f | 1556 | |
24a4742f AW |
1557 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1558 | (u16 *)save_state->cap.data); | |
63f4898a | 1559 | |
cc692a5f SH |
1560 | return 0; |
1561 | } | |
1562 | ||
1563 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1564 | { | |
1565 | int i = 0, pos; | |
1566 | struct pci_cap_saved_state *save_state; | |
1567 | u16 *cap; | |
1568 | ||
1569 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1570 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1571 | if (!save_state || !pos) |
cc692a5f | 1572 | return; |
24a4742f | 1573 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1574 | |
1575 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1576 | } |
1577 | ||
dbbfadf2 BH |
1578 | static void pci_save_ltr_state(struct pci_dev *dev) |
1579 | { | |
1580 | int ltr; | |
1581 | struct pci_cap_saved_state *save_state; | |
1582 | u16 *cap; | |
1583 | ||
1584 | if (!pci_is_pcie(dev)) | |
1585 | return; | |
1586 | ||
1587 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1588 | if (!ltr) | |
1589 | return; | |
1590 | ||
1591 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1592 | if (!save_state) { | |
1593 | pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); | |
1594 | return; | |
1595 | } | |
1596 | ||
1597 | cap = (u16 *)&save_state->cap.data[0]; | |
1598 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++); | |
1599 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++); | |
1600 | } | |
1601 | ||
1602 | static void pci_restore_ltr_state(struct pci_dev *dev) | |
1603 | { | |
1604 | struct pci_cap_saved_state *save_state; | |
1605 | int ltr; | |
1606 | u16 *cap; | |
1607 | ||
1608 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1609 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1610 | if (!save_state || !ltr) | |
1611 | return; | |
1612 | ||
1613 | cap = (u16 *)&save_state->cap.data[0]; | |
1614 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++); | |
1615 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++); | |
1616 | } | |
cc692a5f | 1617 | |
1da177e4 | 1618 | /** |
74356add BH |
1619 | * pci_save_state - save the PCI configuration space of a device before |
1620 | * suspending | |
1621 | * @dev: PCI device that we're dealing with | |
1da177e4 | 1622 | */ |
3c78bc61 | 1623 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1624 | { |
1625 | int i; | |
1626 | /* XXX: 100% dword access ok here? */ | |
47b802d5 | 1627 | for (i = 0; i < 16; i++) { |
9e0b5b2c | 1628 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
47b802d5 CY |
1629 | pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n", |
1630 | i * 4, dev->saved_config_space[i]); | |
1631 | } | |
aa8c6c93 | 1632 | dev->state_saved = true; |
79e50e72 QL |
1633 | |
1634 | i = pci_save_pcie_state(dev); | |
1635 | if (i != 0) | |
b56a5a23 | 1636 | return i; |
79e50e72 QL |
1637 | |
1638 | i = pci_save_pcix_state(dev); | |
1639 | if (i != 0) | |
cc692a5f | 1640 | return i; |
79e50e72 | 1641 | |
dbbfadf2 | 1642 | pci_save_ltr_state(dev); |
ad0f2ad6 CLKA |
1643 | if (dmi_check_system(aspm_fix_whitelist)) |
1644 | pci_save_aspm_l1ss_state(dev); | |
4f802170 | 1645 | pci_save_dpc_state(dev); |
af65d1ad | 1646 | pci_save_aer_state(dev); |
39850ed5 | 1647 | pci_save_ptm_state(dev); |
754834b9 | 1648 | return pci_save_vc_state(dev); |
1da177e4 | 1649 | } |
b7fe9434 | 1650 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1651 | |
ebfc5b80 | 1652 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
08387454 | 1653 | u32 saved_val, int retry, bool force) |
ebfc5b80 RW |
1654 | { |
1655 | u32 val; | |
1656 | ||
1657 | pci_read_config_dword(pdev, offset, &val); | |
08387454 | 1658 | if (!force && val == saved_val) |
ebfc5b80 RW |
1659 | return; |
1660 | ||
1661 | for (;;) { | |
7506dc79 | 1662 | pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
227f0647 | 1663 | offset, val, saved_val); |
ebfc5b80 RW |
1664 | pci_write_config_dword(pdev, offset, saved_val); |
1665 | if (retry-- <= 0) | |
1666 | return; | |
1667 | ||
1668 | pci_read_config_dword(pdev, offset, &val); | |
1669 | if (val == saved_val) | |
1670 | return; | |
1671 | ||
1672 | mdelay(1); | |
1673 | } | |
1674 | } | |
1675 | ||
a6cb9ee7 | 1676 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
08387454 DD |
1677 | int start, int end, int retry, |
1678 | bool force) | |
ebfc5b80 RW |
1679 | { |
1680 | int index; | |
1681 | ||
1682 | for (index = end; index >= start; index--) | |
1683 | pci_restore_config_dword(pdev, 4 * index, | |
1684 | pdev->saved_config_space[index], | |
08387454 | 1685 | retry, force); |
ebfc5b80 RW |
1686 | } |
1687 | ||
a6cb9ee7 RW |
1688 | static void pci_restore_config_space(struct pci_dev *pdev) |
1689 | { | |
1690 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
08387454 | 1691 | pci_restore_config_space_range(pdev, 10, 15, 0, false); |
a6cb9ee7 | 1692 | /* Restore BARs before the command register. */ |
08387454 DD |
1693 | pci_restore_config_space_range(pdev, 4, 9, 10, false); |
1694 | pci_restore_config_space_range(pdev, 0, 3, 0, false); | |
1695 | } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1696 | pci_restore_config_space_range(pdev, 12, 15, 0, false); | |
1697 | ||
1698 | /* | |
1699 | * Force rewriting of prefetch registers to avoid S3 resume | |
1700 | * issues on Intel PCI bridges that occur when these | |
1701 | * registers are not explicitly written. | |
1702 | */ | |
1703 | pci_restore_config_space_range(pdev, 9, 11, 0, true); | |
1704 | pci_restore_config_space_range(pdev, 0, 8, 0, false); | |
a6cb9ee7 | 1705 | } else { |
08387454 | 1706 | pci_restore_config_space_range(pdev, 0, 15, 0, false); |
a6cb9ee7 RW |
1707 | } |
1708 | } | |
1709 | ||
d3252ace CK |
1710 | static void pci_restore_rebar_state(struct pci_dev *pdev) |
1711 | { | |
1712 | unsigned int pos, nbars, i; | |
1713 | u32 ctrl; | |
1714 | ||
1715 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
1716 | if (!pos) | |
1717 | return; | |
1718 | ||
1719 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1720 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
1721 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
1722 | ||
1723 | for (i = 0; i < nbars; i++, pos += 8) { | |
1724 | struct resource *res; | |
1725 | int bar_idx, size; | |
1726 | ||
1727 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1728 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
1729 | res = pdev->resource + bar_idx; | |
192f1bf7 | 1730 | size = pci_rebar_bytes_to_size(resource_size(res)); |
d3252ace | 1731 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; |
b1277a22 | 1732 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
d3252ace CK |
1733 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
1734 | } | |
1735 | } | |
1736 | ||
f7625980 | 1737 | /** |
1da177e4 | 1738 | * pci_restore_state - Restore the saved state of a PCI device |
74356add | 1739 | * @dev: PCI device that we're dealing with |
1da177e4 | 1740 | */ |
1d3c16a8 | 1741 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1742 | { |
c82f63e4 | 1743 | if (!dev->state_saved) |
1d3c16a8 | 1744 | return; |
4b77b0a2 | 1745 | |
dbbfadf2 BH |
1746 | /* |
1747 | * Restore max latencies (in the LTR capability) before enabling | |
1748 | * LTR itself (in the PCIe capability). | |
1749 | */ | |
1750 | pci_restore_ltr_state(dev); | |
ad0f2ad6 CLKA |
1751 | if (dmi_check_system(aspm_fix_whitelist)) |
1752 | pci_restore_aspm_l1ss_state(dev); | |
dbbfadf2 | 1753 | |
b56a5a23 | 1754 | pci_restore_pcie_state(dev); |
4ebeb1ec CT |
1755 | pci_restore_pasid_state(dev); |
1756 | pci_restore_pri_state(dev); | |
1900ca13 | 1757 | pci_restore_ats_state(dev); |
425c1b22 | 1758 | pci_restore_vc_state(dev); |
d3252ace | 1759 | pci_restore_rebar_state(dev); |
4f802170 | 1760 | pci_restore_dpc_state(dev); |
39850ed5 | 1761 | pci_restore_ptm_state(dev); |
b56a5a23 | 1762 | |
894020fd | 1763 | pci_aer_clear_status(dev); |
af65d1ad | 1764 | pci_restore_aer_state(dev); |
b07461a8 | 1765 | |
a6cb9ee7 | 1766 | pci_restore_config_space(dev); |
ebfc5b80 | 1767 | |
cc692a5f | 1768 | pci_restore_pcix_state(dev); |
41017f0c | 1769 | pci_restore_msi_state(dev); |
ccbc175a AD |
1770 | |
1771 | /* Restore ACS and IOV configuration state */ | |
1772 | pci_enable_acs(dev); | |
8c5cdb6a | 1773 | pci_restore_iov_state(dev); |
8fed4b65 | 1774 | |
4b77b0a2 | 1775 | dev->state_saved = false; |
1da177e4 | 1776 | } |
b7fe9434 | 1777 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1778 | |
ffbdd3f7 AW |
1779 | struct pci_saved_state { |
1780 | u32 config_space[16]; | |
914a1951 | 1781 | struct pci_cap_saved_data cap[]; |
ffbdd3f7 AW |
1782 | }; |
1783 | ||
1784 | /** | |
1785 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1786 | * the device saved state. | |
1787 | * @dev: PCI device that we're dealing with | |
1788 | * | |
f7625980 | 1789 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1790 | */ |
1791 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1792 | { | |
1793 | struct pci_saved_state *state; | |
1794 | struct pci_cap_saved_state *tmp; | |
1795 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1796 | size_t size; |
1797 | ||
1798 | if (!dev->state_saved) | |
1799 | return NULL; | |
1800 | ||
1801 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1802 | ||
b67bfe0d | 1803 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1804 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1805 | ||
1806 | state = kzalloc(size, GFP_KERNEL); | |
1807 | if (!state) | |
1808 | return NULL; | |
1809 | ||
1810 | memcpy(state->config_space, dev->saved_config_space, | |
1811 | sizeof(state->config_space)); | |
1812 | ||
1813 | cap = state->cap; | |
b67bfe0d | 1814 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1815 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1816 | memcpy(cap, &tmp->cap, len); | |
1817 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1818 | } | |
1819 | /* Empty cap_save terminates list */ | |
1820 | ||
1821 | return state; | |
1822 | } | |
1823 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1824 | ||
1825 | /** | |
1826 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1827 | * @dev: PCI device that we're dealing with | |
1828 | * @state: Saved state returned from pci_store_saved_state() | |
1829 | */ | |
98d9b271 KRW |
1830 | int pci_load_saved_state(struct pci_dev *dev, |
1831 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1832 | { |
1833 | struct pci_cap_saved_data *cap; | |
1834 | ||
1835 | dev->state_saved = false; | |
1836 | ||
1837 | if (!state) | |
1838 | return 0; | |
1839 | ||
1840 | memcpy(dev->saved_config_space, state->config_space, | |
1841 | sizeof(state->config_space)); | |
1842 | ||
1843 | cap = state->cap; | |
1844 | while (cap->size) { | |
1845 | struct pci_cap_saved_state *tmp; | |
1846 | ||
fd0f7f73 | 1847 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1848 | if (!tmp || tmp->cap.size != cap->size) |
1849 | return -EINVAL; | |
1850 | ||
1851 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1852 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1853 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1854 | } | |
1855 | ||
1856 | dev->state_saved = true; | |
1857 | return 0; | |
1858 | } | |
98d9b271 | 1859 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1860 | |
1861 | /** | |
1862 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1863 | * and free the memory allocated for it. | |
1864 | * @dev: PCI device that we're dealing with | |
1865 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1866 | */ | |
1867 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1868 | struct pci_saved_state **state) | |
1869 | { | |
1870 | int ret = pci_load_saved_state(dev, *state); | |
1871 | kfree(*state); | |
1872 | *state = NULL; | |
1873 | return ret; | |
1874 | } | |
1875 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1876 | ||
8a9d5609 BH |
1877 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1878 | { | |
1879 | return pci_enable_resources(dev, bars); | |
1880 | } | |
1881 | ||
38cc1302 HS |
1882 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1883 | { | |
1884 | int err; | |
1f6ae47e | 1885 | struct pci_dev *bridge; |
1e2571a7 BH |
1886 | u16 cmd; |
1887 | u8 pin; | |
38cc1302 HS |
1888 | |
1889 | err = pci_set_power_state(dev, PCI_D0); | |
1890 | if (err < 0 && err != -EIO) | |
1891 | return err; | |
1f6ae47e VS |
1892 | |
1893 | bridge = pci_upstream_bridge(dev); | |
1894 | if (bridge) | |
1895 | pcie_aspm_powersave_config_link(bridge); | |
1896 | ||
38cc1302 HS |
1897 | err = pcibios_enable_device(dev, bars); |
1898 | if (err < 0) | |
1899 | return err; | |
1900 | pci_fixup_device(pci_fixup_enable, dev); | |
1901 | ||
866d5417 BH |
1902 | if (dev->msi_enabled || dev->msix_enabled) |
1903 | return 0; | |
1904 | ||
1e2571a7 BH |
1905 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1906 | if (pin) { | |
1907 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1908 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1909 | pci_write_config_word(dev, PCI_COMMAND, | |
1910 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1911 | } | |
1912 | ||
38cc1302 HS |
1913 | return 0; |
1914 | } | |
1915 | ||
1916 | /** | |
0b62e13b | 1917 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1918 | * @dev: PCI device to be resumed |
1919 | * | |
74356add BH |
1920 | * NOTE: This function is a backend of pci_default_resume() and is not supposed |
1921 | * to be called by normal code, write proper resume handler and use it instead. | |
38cc1302 | 1922 | */ |
0b62e13b | 1923 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1924 | { |
296ccb08 | 1925 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1926 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1927 | return 0; | |
1928 | } | |
b7fe9434 | 1929 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1930 | |
928bea96 YL |
1931 | static void pci_enable_bridge(struct pci_dev *dev) |
1932 | { | |
79272138 | 1933 | struct pci_dev *bridge; |
928bea96 YL |
1934 | int retval; |
1935 | ||
79272138 BH |
1936 | bridge = pci_upstream_bridge(dev); |
1937 | if (bridge) | |
1938 | pci_enable_bridge(bridge); | |
928bea96 | 1939 | |
cf3e1feb | 1940 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1941 | if (!dev->is_busmaster) |
cf3e1feb | 1942 | pci_set_master(dev); |
0f50a49e | 1943 | return; |
cf3e1feb YL |
1944 | } |
1945 | ||
928bea96 YL |
1946 | retval = pci_enable_device(dev); |
1947 | if (retval) | |
7506dc79 | 1948 | pci_err(dev, "Error enabling bridge (%d), continuing\n", |
928bea96 YL |
1949 | retval); |
1950 | pci_set_master(dev); | |
1951 | } | |
1952 | ||
b4b4fbba | 1953 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1954 | { |
79272138 | 1955 | struct pci_dev *bridge; |
1da177e4 | 1956 | int err; |
b718989d | 1957 | int i, bars = 0; |
1da177e4 | 1958 | |
4d6035f9 RW |
1959 | /* |
1960 | * Power state could be unknown at this point, either due to a fresh | |
1961 | * boot or a device removal call. So get the current power state | |
1962 | * so that things like MSI message writing will behave as expected | |
1963 | * (e.g. if the device really is in D0 at enable time). | |
1964 | */ | |
14858dcc | 1965 | pci_update_current_state(dev, dev->current_state); |
9fb625c3 | 1966 | |
4d6035f9 RW |
1967 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
1968 | return 0; /* already enabled */ | |
1969 | ||
79272138 | 1970 | bridge = pci_upstream_bridge(dev); |
0f50a49e | 1971 | if (bridge) |
79272138 | 1972 | pci_enable_bridge(bridge); |
928bea96 | 1973 | |
497f16f2 YL |
1974 | /* only skip sriov related */ |
1975 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1976 | if (dev->resource[i].flags & flags) | |
1977 | bars |= (1 << i); | |
1978 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1979 | if (dev->resource[i].flags & flags) |
1980 | bars |= (1 << i); | |
1981 | ||
38cc1302 | 1982 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1983 | if (err < 0) |
38cc1302 | 1984 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1985 | return err; |
1da177e4 LT |
1986 | } |
1987 | ||
b718989d BH |
1988 | /** |
1989 | * pci_enable_device_io - Initialize a device for use with IO space | |
1990 | * @dev: PCI device to be initialized | |
1991 | * | |
74356add BH |
1992 | * Initialize device before it's used by a driver. Ask low-level code |
1993 | * to enable I/O resources. Wake up the device if it was suspended. | |
1994 | * Beware, this function can fail. | |
b718989d BH |
1995 | */ |
1996 | int pci_enable_device_io(struct pci_dev *dev) | |
1997 | { | |
b4b4fbba | 1998 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1999 | } |
b7fe9434 | 2000 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
2001 | |
2002 | /** | |
2003 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
2004 | * @dev: PCI device to be initialized | |
2005 | * | |
74356add BH |
2006 | * Initialize device before it's used by a driver. Ask low-level code |
2007 | * to enable Memory resources. Wake up the device if it was suspended. | |
2008 | * Beware, this function can fail. | |
b718989d BH |
2009 | */ |
2010 | int pci_enable_device_mem(struct pci_dev *dev) | |
2011 | { | |
b4b4fbba | 2012 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 2013 | } |
b7fe9434 | 2014 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 2015 | |
bae94d02 IPG |
2016 | /** |
2017 | * pci_enable_device - Initialize device before it's used by a driver. | |
2018 | * @dev: PCI device to be initialized | |
2019 | * | |
74356add BH |
2020 | * Initialize device before it's used by a driver. Ask low-level code |
2021 | * to enable I/O and memory. Wake up the device if it was suspended. | |
2022 | * Beware, this function can fail. | |
bae94d02 | 2023 | * |
74356add BH |
2024 | * Note we don't actually enable the device many times if we call |
2025 | * this function repeatedly (we just increment the count). | |
bae94d02 IPG |
2026 | */ |
2027 | int pci_enable_device(struct pci_dev *dev) | |
2028 | { | |
b4b4fbba | 2029 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 2030 | } |
b7fe9434 | 2031 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 2032 | |
9ac7849e | 2033 | /* |
74356add BH |
2034 | * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X |
2035 | * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so | |
9ac7849e TH |
2036 | * there's no need to track it separately. pci_devres is initialized |
2037 | * when a device is enabled using managed PCI device enable interface. | |
2038 | */ | |
2039 | struct pci_devres { | |
7f375f32 TH |
2040 | unsigned int enabled:1; |
2041 | unsigned int pinned:1; | |
9ac7849e TH |
2042 | unsigned int orig_intx:1; |
2043 | unsigned int restore_intx:1; | |
fc0f9f4d | 2044 | unsigned int mwi:1; |
9ac7849e TH |
2045 | u32 region_mask; |
2046 | }; | |
2047 | ||
2048 | static void pcim_release(struct device *gendev, void *res) | |
2049 | { | |
f3d2f165 | 2050 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
2051 | struct pci_devres *this = res; |
2052 | int i; | |
2053 | ||
2054 | if (dev->msi_enabled) | |
2055 | pci_disable_msi(dev); | |
2056 | if (dev->msix_enabled) | |
2057 | pci_disable_msix(dev); | |
2058 | ||
2059 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
2060 | if (this->region_mask & (1 << i)) | |
2061 | pci_release_region(dev, i); | |
2062 | ||
fc0f9f4d HK |
2063 | if (this->mwi) |
2064 | pci_clear_mwi(dev); | |
2065 | ||
9ac7849e TH |
2066 | if (this->restore_intx) |
2067 | pci_intx(dev, this->orig_intx); | |
2068 | ||
7f375f32 | 2069 | if (this->enabled && !this->pinned) |
9ac7849e TH |
2070 | pci_disable_device(dev); |
2071 | } | |
2072 | ||
07656d83 | 2073 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
2074 | { |
2075 | struct pci_devres *dr, *new_dr; | |
2076 | ||
2077 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
2078 | if (dr) | |
2079 | return dr; | |
2080 | ||
2081 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
2082 | if (!new_dr) | |
2083 | return NULL; | |
2084 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
2085 | } | |
2086 | ||
07656d83 | 2087 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
2088 | { |
2089 | if (pci_is_managed(pdev)) | |
2090 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
2091 | return NULL; | |
2092 | } | |
2093 | ||
2094 | /** | |
2095 | * pcim_enable_device - Managed pci_enable_device() | |
2096 | * @pdev: PCI device to be initialized | |
2097 | * | |
2098 | * Managed pci_enable_device(). | |
2099 | */ | |
2100 | int pcim_enable_device(struct pci_dev *pdev) | |
2101 | { | |
2102 | struct pci_devres *dr; | |
2103 | int rc; | |
2104 | ||
2105 | dr = get_pci_dr(pdev); | |
2106 | if (unlikely(!dr)) | |
2107 | return -ENOMEM; | |
b95d58ea TH |
2108 | if (dr->enabled) |
2109 | return 0; | |
9ac7849e TH |
2110 | |
2111 | rc = pci_enable_device(pdev); | |
2112 | if (!rc) { | |
2113 | pdev->is_managed = 1; | |
7f375f32 | 2114 | dr->enabled = 1; |
9ac7849e TH |
2115 | } |
2116 | return rc; | |
2117 | } | |
b7fe9434 | 2118 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
2119 | |
2120 | /** | |
2121 | * pcim_pin_device - Pin managed PCI device | |
2122 | * @pdev: PCI device to pin | |
2123 | * | |
2124 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
2125 | * driver detach. @pdev must have been enabled with | |
2126 | * pcim_enable_device(). | |
2127 | */ | |
2128 | void pcim_pin_device(struct pci_dev *pdev) | |
2129 | { | |
2130 | struct pci_devres *dr; | |
2131 | ||
2132 | dr = find_pci_dr(pdev); | |
7f375f32 | 2133 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 2134 | if (dr) |
7f375f32 | 2135 | dr->pinned = 1; |
9ac7849e | 2136 | } |
b7fe9434 | 2137 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 2138 | |
eca0d467 MG |
2139 | /* |
2140 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
2141 | * @dev: the PCI device being added | |
2142 | * | |
2143 | * Permits the platform to provide architecture specific functionality when | |
2144 | * devices are added. This is the default implementation. Architecture | |
2145 | * implementations can override this. | |
2146 | */ | |
3c78bc61 | 2147 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
2148 | { |
2149 | return 0; | |
2150 | } | |
2151 | ||
6ae32c53 | 2152 | /** |
74356add BH |
2153 | * pcibios_release_device - provide arch specific hooks when releasing |
2154 | * device dev | |
6ae32c53 SO |
2155 | * @dev: the PCI device being released |
2156 | * | |
2157 | * Permits the platform to provide architecture specific functionality when | |
2158 | * devices are released. This is the default implementation. Architecture | |
2159 | * implementations can override this. | |
2160 | */ | |
2161 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
2162 | ||
1da177e4 LT |
2163 | /** |
2164 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
2165 | * @dev: the PCI device to disable | |
2166 | * | |
2167 | * Disables architecture specific PCI resources for the device. This | |
2168 | * is the default implementation. Architecture implementations can | |
2169 | * override this. | |
2170 | */ | |
ff3ce480 | 2171 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 2172 | |
a43ae58c HG |
2173 | /** |
2174 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
2175 | * @irq: ISA IRQ to penalize | |
2176 | * @active: IRQ active or not | |
2177 | * | |
2178 | * Permits the platform to provide architecture-specific functionality when | |
2179 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
2180 | * implementations can override this. | |
2181 | */ | |
2182 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
2183 | ||
fa58d305 RW |
2184 | static void do_pci_disable_device(struct pci_dev *dev) |
2185 | { | |
2186 | u16 pci_command; | |
2187 | ||
2188 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
2189 | if (pci_command & PCI_COMMAND_MASTER) { | |
2190 | pci_command &= ~PCI_COMMAND_MASTER; | |
2191 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
2192 | } | |
2193 | ||
2194 | pcibios_disable_device(dev); | |
2195 | } | |
2196 | ||
2197 | /** | |
2198 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
2199 | * @dev: PCI device to disable | |
2200 | * | |
2201 | * NOTE: This function is a backend of PCI power management routines and is | |
2202 | * not supposed to be called drivers. | |
2203 | */ | |
2204 | void pci_disable_enabled_device(struct pci_dev *dev) | |
2205 | { | |
296ccb08 | 2206 | if (pci_is_enabled(dev)) |
fa58d305 RW |
2207 | do_pci_disable_device(dev); |
2208 | } | |
2209 | ||
1da177e4 LT |
2210 | /** |
2211 | * pci_disable_device - Disable PCI device after use | |
2212 | * @dev: PCI device to be disabled | |
2213 | * | |
2214 | * Signal to the system that the PCI device is not in use by the system | |
2215 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
2216 | * |
2217 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 2218 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 2219 | */ |
3c78bc61 | 2220 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 2221 | { |
9ac7849e | 2222 | struct pci_devres *dr; |
99dc804d | 2223 | |
9ac7849e TH |
2224 | dr = find_pci_dr(dev); |
2225 | if (dr) | |
7f375f32 | 2226 | dr->enabled = 0; |
9ac7849e | 2227 | |
fd6dceab KK |
2228 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
2229 | "disabling already-disabled device"); | |
2230 | ||
cc7ba39b | 2231 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
2232 | return; |
2233 | ||
fa58d305 | 2234 | do_pci_disable_device(dev); |
1da177e4 | 2235 | |
fa58d305 | 2236 | dev->is_busmaster = 0; |
1da177e4 | 2237 | } |
b7fe9434 | 2238 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 2239 | |
f7bdd12d BK |
2240 | /** |
2241 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 2242 | * @dev: the PCIe device reset |
f7bdd12d BK |
2243 | * @state: Reset state to enter into |
2244 | * | |
74356add | 2245 | * Set the PCIe reset state for the device. This is the default |
f7bdd12d BK |
2246 | * implementation. Architecture implementations can override this. |
2247 | */ | |
d6d88c83 BH |
2248 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
2249 | enum pcie_reset_state state) | |
f7bdd12d BK |
2250 | { |
2251 | return -EINVAL; | |
2252 | } | |
2253 | ||
2254 | /** | |
2255 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 2256 | * @dev: the PCIe device reset |
f7bdd12d BK |
2257 | * @state: Reset state to enter into |
2258 | * | |
f7bdd12d BK |
2259 | * Sets the PCI reset state for the device. |
2260 | */ | |
2261 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
2262 | { | |
2263 | return pcibios_set_pcie_reset_state(dev, state); | |
2264 | } | |
b7fe9434 | 2265 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 2266 | |
600a5b4f BH |
2267 | void pcie_clear_device_status(struct pci_dev *dev) |
2268 | { | |
2269 | u16 sta; | |
2270 | ||
2271 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); | |
2272 | pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); | |
2273 | } | |
2274 | ||
dcb0453d BH |
2275 | /** |
2276 | * pcie_clear_root_pme_status - Clear root port PME interrupt status. | |
2277 | * @dev: PCIe root port or event collector. | |
2278 | */ | |
2279 | void pcie_clear_root_pme_status(struct pci_dev *dev) | |
2280 | { | |
2281 | pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME); | |
2282 | } | |
2283 | ||
58ff4633 RW |
2284 | /** |
2285 | * pci_check_pme_status - Check if given device has generated PME. | |
2286 | * @dev: Device to check. | |
2287 | * | |
2288 | * Check the PME status of the device and if set, clear it and clear PME enable | |
2289 | * (if set). Return 'true' if PME status and PME enable were both set or | |
2290 | * 'false' otherwise. | |
2291 | */ | |
2292 | bool pci_check_pme_status(struct pci_dev *dev) | |
2293 | { | |
2294 | int pmcsr_pos; | |
2295 | u16 pmcsr; | |
2296 | bool ret = false; | |
2297 | ||
2298 | if (!dev->pm_cap) | |
2299 | return false; | |
2300 | ||
2301 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
2302 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
2303 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
2304 | return false; | |
2305 | ||
2306 | /* Clear PME status. */ | |
2307 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2308 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
2309 | /* Disable PME to avoid interrupt flood. */ | |
2310 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2311 | ret = true; | |
2312 | } | |
2313 | ||
2314 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
2315 | ||
2316 | return ret; | |
2317 | } | |
2318 | ||
b67ea761 RW |
2319 | /** |
2320 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
2321 | * @dev: Device to handle. | |
379021d5 | 2322 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
2323 | * |
2324 | * Check if @dev has generated PME and queue a resume request for it in that | |
2325 | * case. | |
2326 | */ | |
379021d5 | 2327 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 2328 | { |
379021d5 RW |
2329 | if (pme_poll_reset && dev->pme_poll) |
2330 | dev->pme_poll = false; | |
2331 | ||
c125e96f | 2332 | if (pci_check_pme_status(dev)) { |
c125e96f | 2333 | pci_wakeup_event(dev); |
0f953bf6 | 2334 | pm_request_resume(&dev->dev); |
c125e96f | 2335 | } |
b67ea761 RW |
2336 | return 0; |
2337 | } | |
2338 | ||
2339 | /** | |
2340 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
2341 | * @bus: Top bus of the subtree to walk. | |
2342 | */ | |
2343 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
2344 | { | |
2345 | if (bus) | |
379021d5 | 2346 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
2347 | } |
2348 | ||
448bd857 | 2349 | |
eb9d0fe4 RW |
2350 | /** |
2351 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
2352 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
2353 | * @state: PCI state from which device will issue PME#. |
2354 | */ | |
e5899e1b | 2355 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 2356 | { |
337001b6 | 2357 | if (!dev->pm_cap) |
eb9d0fe4 RW |
2358 | return false; |
2359 | ||
337001b6 | 2360 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 2361 | } |
b7fe9434 | 2362 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 2363 | |
df17e62e MG |
2364 | static void pci_pme_list_scan(struct work_struct *work) |
2365 | { | |
379021d5 | 2366 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
2367 | |
2368 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
2369 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
2370 | if (pme_dev->dev->pme_poll) { | |
2371 | struct pci_dev *bridge; | |
2372 | ||
2373 | bridge = pme_dev->dev->bus->self; | |
2374 | /* | |
2375 | * If bridge is in low power state, the | |
2376 | * configuration space of subordinate devices | |
2377 | * may be not accessible | |
2378 | */ | |
2379 | if (bridge && bridge->current_state != PCI_D0) | |
2380 | continue; | |
000dd531 MW |
2381 | /* |
2382 | * If the device is in D3cold it should not be | |
2383 | * polled either. | |
2384 | */ | |
2385 | if (pme_dev->dev->current_state == PCI_D3cold) | |
2386 | continue; | |
2387 | ||
ce300008 BH |
2388 | pci_pme_wakeup(pme_dev->dev, NULL); |
2389 | } else { | |
2390 | list_del(&pme_dev->list); | |
2391 | kfree(pme_dev); | |
379021d5 | 2392 | } |
df17e62e | 2393 | } |
ce300008 | 2394 | if (!list_empty(&pci_pme_list)) |
ea00353f LW |
2395 | queue_delayed_work(system_freezable_wq, &pci_pme_work, |
2396 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2397 | mutex_unlock(&pci_pme_list_mutex); |
2398 | } | |
2399 | ||
2cef548a | 2400 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
2401 | { |
2402 | u16 pmcsr; | |
2403 | ||
ffaddbe8 | 2404 | if (!dev->pme_support) |
eb9d0fe4 RW |
2405 | return; |
2406 | ||
337001b6 | 2407 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
2408 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
2409 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
2410 | if (!enable) | |
2411 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2412 | ||
337001b6 | 2413 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
2414 | } |
2415 | ||
0ce3fcaf RW |
2416 | /** |
2417 | * pci_pme_restore - Restore PME configuration after config space restore. | |
2418 | * @dev: PCI device to update. | |
2419 | */ | |
2420 | void pci_pme_restore(struct pci_dev *dev) | |
dc15e71e RW |
2421 | { |
2422 | u16 pmcsr; | |
2423 | ||
2424 | if (!dev->pme_support) | |
2425 | return; | |
2426 | ||
2427 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
2428 | if (dev->wakeup_prepared) { | |
2429 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
0ce3fcaf | 2430 | pmcsr &= ~PCI_PM_CTRL_PME_STATUS; |
dc15e71e RW |
2431 | } else { |
2432 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2433 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2434 | } | |
2435 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); | |
2436 | } | |
2437 | ||
2cef548a RW |
2438 | /** |
2439 | * pci_pme_active - enable or disable PCI device's PME# function | |
2440 | * @dev: PCI device to handle. | |
2441 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
2442 | * | |
2443 | * The caller must verify that the device is capable of generating PME# before | |
2444 | * calling this function with @enable equal to 'true'. | |
2445 | */ | |
2446 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
2447 | { | |
2448 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 2449 | |
6e965e0d HY |
2450 | /* |
2451 | * PCI (as opposed to PCIe) PME requires that the device have | |
2452 | * its PME# line hooked up correctly. Not all hardware vendors | |
2453 | * do this, so the PME never gets delivered and the device | |
2454 | * remains asleep. The easiest way around this is to | |
2455 | * periodically walk the list of suspended devices and check | |
2456 | * whether any have their PME flag set. The assumption is that | |
2457 | * we'll wake up often enough anyway that this won't be a huge | |
2458 | * hit, and the power savings from the devices will still be a | |
2459 | * win. | |
2460 | * | |
2461 | * Although PCIe uses in-band PME message instead of PME# line | |
2462 | * to report PME, PME does not work for some PCIe devices in | |
2463 | * reality. For example, there are devices that set their PME | |
2464 | * status bits, but don't really bother to send a PME message; | |
2465 | * there are PCI Express Root Ports that don't bother to | |
2466 | * trigger interrupts when they receive PME messages from the | |
2467 | * devices below. So PME poll is used for PCIe devices too. | |
2468 | */ | |
df17e62e | 2469 | |
379021d5 | 2470 | if (dev->pme_poll) { |
df17e62e MG |
2471 | struct pci_pme_device *pme_dev; |
2472 | if (enable) { | |
2473 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
2474 | GFP_KERNEL); | |
0394cb19 | 2475 | if (!pme_dev) { |
7506dc79 | 2476 | pci_warn(dev, "can't enable PME#\n"); |
0394cb19 BH |
2477 | return; |
2478 | } | |
df17e62e MG |
2479 | pme_dev->dev = dev; |
2480 | mutex_lock(&pci_pme_list_mutex); | |
2481 | list_add(&pme_dev->list, &pci_pme_list); | |
2482 | if (list_is_singular(&pci_pme_list)) | |
ea00353f LW |
2483 | queue_delayed_work(system_freezable_wq, |
2484 | &pci_pme_work, | |
2485 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2486 | mutex_unlock(&pci_pme_list_mutex); |
2487 | } else { | |
2488 | mutex_lock(&pci_pme_list_mutex); | |
2489 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
2490 | if (pme_dev->dev == dev) { | |
2491 | list_del(&pme_dev->list); | |
2492 | kfree(pme_dev); | |
2493 | break; | |
2494 | } | |
2495 | } | |
2496 | mutex_unlock(&pci_pme_list_mutex); | |
2497 | } | |
2498 | } | |
2499 | ||
7506dc79 | 2500 | pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 2501 | } |
b7fe9434 | 2502 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 2503 | |
1da177e4 | 2504 | /** |
cfcadfaa | 2505 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
2506 | * @dev: PCI device affected |
2507 | * @state: PCI state from which device will issue wakeup events | |
2508 | * @enable: True to enable event generation; false to disable | |
2509 | * | |
2510 | * This enables the device as a wakeup event source, or disables it. | |
2511 | * When such events involves platform-specific hooks, those hooks are | |
2512 | * called automatically by this routine. | |
2513 | * | |
2514 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 2515 | * always require such platform hooks. |
075c1771 | 2516 | * |
eb9d0fe4 RW |
2517 | * RETURN VALUE: |
2518 | * 0 is returned on success | |
2519 | * -EINVAL is returned if device is not supposed to wake up the system | |
2520 | * Error code depending on the platform is returned if both the platform and | |
2521 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 2522 | */ |
cfcadfaa | 2523 | static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1da177e4 | 2524 | { |
5bcc2fb4 | 2525 | int ret = 0; |
075c1771 | 2526 | |
baecc470 | 2527 | /* |
ac86e8ee MW |
2528 | * Bridges that are not power-manageable directly only signal |
2529 | * wakeup on behalf of subordinate devices which is set up | |
2530 | * elsewhere, so skip them. However, bridges that are | |
2531 | * power-manageable may signal wakeup for themselves (for example, | |
2532 | * on a hotplug event) and they need to be covered here. | |
baecc470 | 2533 | */ |
ac86e8ee | 2534 | if (!pci_power_manageable(dev)) |
baecc470 RW |
2535 | return 0; |
2536 | ||
0ce3fcaf RW |
2537 | /* Don't do the same thing twice in a row for one device. */ |
2538 | if (!!enable == !!dev->wakeup_prepared) | |
e80bb09d RW |
2539 | return 0; |
2540 | ||
eb9d0fe4 RW |
2541 | /* |
2542 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
2543 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
2544 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 2545 | */ |
1da177e4 | 2546 | |
5bcc2fb4 RW |
2547 | if (enable) { |
2548 | int error; | |
1da177e4 | 2549 | |
0e00392a RW |
2550 | /* |
2551 | * Enable PME signaling if the device can signal PME from | |
2552 | * D3cold regardless of whether or not it can signal PME from | |
2553 | * the current target state, because that will allow it to | |
2554 | * signal PME when the hierarchy above it goes into D3cold and | |
2555 | * the device itself ends up in D3cold as a result of that. | |
2556 | */ | |
2557 | if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold)) | |
5bcc2fb4 RW |
2558 | pci_pme_active(dev, true); |
2559 | else | |
2560 | ret = 1; | |
0847684c | 2561 | error = platform_pci_set_wakeup(dev, true); |
5bcc2fb4 RW |
2562 | if (ret) |
2563 | ret = error; | |
e80bb09d RW |
2564 | if (!ret) |
2565 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 2566 | } else { |
0847684c | 2567 | platform_pci_set_wakeup(dev, false); |
5bcc2fb4 | 2568 | pci_pme_active(dev, false); |
e80bb09d | 2569 | dev->wakeup_prepared = false; |
5bcc2fb4 | 2570 | } |
1da177e4 | 2571 | |
5bcc2fb4 | 2572 | return ret; |
eb9d0fe4 | 2573 | } |
cfcadfaa RW |
2574 | |
2575 | /** | |
2576 | * pci_enable_wake - change wakeup settings for a PCI device | |
2577 | * @pci_dev: Target device | |
2578 | * @state: PCI state from which device will issue wakeup events | |
2579 | * @enable: Whether or not to enable event generation | |
2580 | * | |
2581 | * If @enable is set, check device_may_wakeup() for the device before calling | |
2582 | * __pci_enable_wake() for it. | |
2583 | */ | |
2584 | int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) | |
2585 | { | |
2586 | if (enable && !device_may_wakeup(&pci_dev->dev)) | |
2587 | return -EINVAL; | |
2588 | ||
2589 | return __pci_enable_wake(pci_dev, state, enable); | |
2590 | } | |
0847684c | 2591 | EXPORT_SYMBOL(pci_enable_wake); |
1da177e4 | 2592 | |
0235c4fc RW |
2593 | /** |
2594 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
2595 | * @dev: PCI device to prepare | |
2596 | * @enable: True to enable wake-up event generation; false to disable | |
2597 | * | |
2598 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
2599 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
2600 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
2601 | * ordering constraints. | |
2602 | * | |
cfcadfaa RW |
2603 | * This function only returns error code if the device is not allowed to wake |
2604 | * up the system from sleep or it is not capable of generating PME# from both | |
2605 | * D3_hot and D3_cold and the platform is unable to enable wake-up power for it. | |
0235c4fc RW |
2606 | */ |
2607 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
2608 | { | |
2609 | return pci_pme_capable(dev, PCI_D3cold) ? | |
2610 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
2611 | pci_enable_wake(dev, PCI_D3hot, enable); | |
2612 | } | |
b7fe9434 | 2613 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 2614 | |
404cc2d8 | 2615 | /** |
37139074 JB |
2616 | * pci_target_state - find an appropriate low power state for a given PCI dev |
2617 | * @dev: PCI device | |
666ff6f8 | 2618 | * @wakeup: Whether or not wakeup functionality will be enabled for the device. |
37139074 JB |
2619 | * |
2620 | * Use underlying platform code to find a supported low power state for @dev. | |
2621 | * If the platform can't manage @dev, return the deepest state from which it | |
2622 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 2623 | */ |
666ff6f8 | 2624 | static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) |
404cc2d8 RW |
2625 | { |
2626 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
2627 | |
2628 | if (platform_pci_power_manageable(dev)) { | |
2629 | /* | |
60ee031a | 2630 | * Call the platform to find the target state for the device. |
404cc2d8 RW |
2631 | */ |
2632 | pci_power_t state = platform_pci_choose_state(dev); | |
2633 | ||
2634 | switch (state) { | |
2635 | case PCI_POWER_ERROR: | |
2636 | case PCI_UNKNOWN: | |
2637 | break; | |
2638 | case PCI_D1: | |
2639 | case PCI_D2: | |
2640 | if (pci_no_d1d2(dev)) | |
2641 | break; | |
df561f66 | 2642 | fallthrough; |
404cc2d8 RW |
2643 | default: |
2644 | target_state = state; | |
404cc2d8 | 2645 | } |
4132a577 LW |
2646 | |
2647 | return target_state; | |
2648 | } | |
2649 | ||
2650 | if (!dev->pm_cap) | |
d2abdf62 | 2651 | target_state = PCI_D0; |
4132a577 LW |
2652 | |
2653 | /* | |
2654 | * If the device is in D3cold even though it's not power-manageable by | |
2655 | * the platform, it may have been powered down by non-standard means. | |
2656 | * Best to let it slumber. | |
2657 | */ | |
2658 | if (dev->current_state == PCI_D3cold) | |
2659 | target_state = PCI_D3cold; | |
2660 | ||
da9f2150 RW |
2661 | if (wakeup && dev->pme_support) { |
2662 | pci_power_t state = target_state; | |
2663 | ||
404cc2d8 RW |
2664 | /* |
2665 | * Find the deepest state from which the device can generate | |
60ee031a | 2666 | * PME#. |
404cc2d8 | 2667 | */ |
da9f2150 RW |
2668 | while (state && !(dev->pme_support & (1 << state))) |
2669 | state--; | |
2670 | ||
2671 | if (state) | |
2672 | return state; | |
2673 | else if (dev->pme_support & 1) | |
2674 | return PCI_D0; | |
404cc2d8 RW |
2675 | } |
2676 | ||
e5899e1b RW |
2677 | return target_state; |
2678 | } | |
2679 | ||
2680 | /** | |
74356add BH |
2681 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition |
2682 | * into a sleep state | |
e5899e1b RW |
2683 | * @dev: Device to handle. |
2684 | * | |
2685 | * Choose the power state appropriate for the device depending on whether | |
2686 | * it can wake up the system and/or is power manageable by the platform | |
2687 | * (PCI_D3hot is the default) and put the device into that state. | |
2688 | */ | |
2689 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
2690 | { | |
666ff6f8 RW |
2691 | bool wakeup = device_may_wakeup(&dev->dev); |
2692 | pci_power_t target_state = pci_target_state(dev, wakeup); | |
e5899e1b RW |
2693 | int error; |
2694 | ||
2695 | if (target_state == PCI_POWER_ERROR) | |
2696 | return -EIO; | |
2697 | ||
666ff6f8 | 2698 | pci_enable_wake(dev, target_state, wakeup); |
c157dfa3 | 2699 | |
404cc2d8 RW |
2700 | error = pci_set_power_state(dev, target_state); |
2701 | ||
2d5c8086 | 2702 | if (error) |
404cc2d8 RW |
2703 | pci_enable_wake(dev, target_state, false); |
2704 | ||
2705 | return error; | |
2706 | } | |
b7fe9434 | 2707 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2708 | |
2709 | /** | |
74356add BH |
2710 | * pci_back_from_sleep - turn PCI device on during system-wide transition |
2711 | * into working state | |
404cc2d8 RW |
2712 | * @dev: Device to handle. |
2713 | * | |
88393161 | 2714 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2715 | */ |
2716 | int pci_back_from_sleep(struct pci_dev *dev) | |
2717 | { | |
2718 | pci_enable_wake(dev, PCI_D0, false); | |
2719 | return pci_set_power_state(dev, PCI_D0); | |
2720 | } | |
b7fe9434 | 2721 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2722 | |
6cbf8214 RW |
2723 | /** |
2724 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2725 | * @dev: PCI device being suspended. | |
2726 | * | |
2727 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2728 | * power state. | |
2729 | */ | |
2730 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2731 | { | |
666ff6f8 | 2732 | pci_power_t target_state; |
6cbf8214 RW |
2733 | int error; |
2734 | ||
666ff6f8 | 2735 | target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); |
6cbf8214 RW |
2736 | if (target_state == PCI_POWER_ERROR) |
2737 | return -EIO; | |
2738 | ||
448bd857 HY |
2739 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2740 | ||
cfcadfaa | 2741 | __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); |
6cbf8214 RW |
2742 | |
2743 | error = pci_set_power_state(dev, target_state); | |
2744 | ||
448bd857 | 2745 | if (error) { |
0847684c | 2746 | pci_enable_wake(dev, target_state, false); |
448bd857 HY |
2747 | dev->runtime_d3cold = false; |
2748 | } | |
6cbf8214 RW |
2749 | |
2750 | return error; | |
2751 | } | |
2752 | ||
b67ea761 RW |
2753 | /** |
2754 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2755 | * @dev: Device to check. | |
2756 | * | |
f7625980 | 2757 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2758 | * (through the platform or using the native PCIe PME) or if the device supports |
2759 | * PME and one of its upstream bridges can generate wake-up events. | |
2760 | */ | |
2761 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2762 | { | |
2763 | struct pci_bus *bus = dev->bus; | |
2764 | ||
b67ea761 RW |
2765 | if (!dev->pme_support) |
2766 | return false; | |
2767 | ||
666ff6f8 | 2768 | /* PME-capable in principle, but not from the target power state */ |
8feaec33 | 2769 | if (!pci_pme_capable(dev, pci_target_state(dev, true))) |
6496ebd7 AS |
2770 | return false; |
2771 | ||
8feaec33 KHF |
2772 | if (device_can_wakeup(&dev->dev)) |
2773 | return true; | |
2774 | ||
b67ea761 RW |
2775 | while (bus->parent) { |
2776 | struct pci_dev *bridge = bus->self; | |
2777 | ||
de3ef1eb | 2778 | if (device_can_wakeup(&bridge->dev)) |
b67ea761 RW |
2779 | return true; |
2780 | ||
2781 | bus = bus->parent; | |
2782 | } | |
2783 | ||
2784 | /* We have reached the root bus. */ | |
2785 | if (bus->bridge) | |
de3ef1eb | 2786 | return device_can_wakeup(bus->bridge); |
b67ea761 RW |
2787 | |
2788 | return false; | |
2789 | } | |
2790 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2791 | ||
bac2a909 | 2792 | /** |
0c7376ad | 2793 | * pci_dev_need_resume - Check if it is necessary to resume the device. |
bac2a909 RW |
2794 | * @pci_dev: Device to check. |
2795 | * | |
0c7376ad | 2796 | * Return 'true' if the device is not runtime-suspended or it has to be |
bac2a909 | 2797 | * reconfigured due to wakeup settings difference between system and runtime |
0c7376ad RW |
2798 | * suspend, or the current power state of it is not suitable for the upcoming |
2799 | * (system-wide) transition. | |
bac2a909 | 2800 | */ |
0c7376ad | 2801 | bool pci_dev_need_resume(struct pci_dev *pci_dev) |
bac2a909 RW |
2802 | { |
2803 | struct device *dev = &pci_dev->dev; | |
234f223d RW |
2804 | pci_power_t target_state; |
2805 | ||
2806 | if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev)) | |
0c7376ad | 2807 | return true; |
bac2a909 | 2808 | |
0c7376ad | 2809 | target_state = pci_target_state(pci_dev, device_may_wakeup(dev)); |
234f223d RW |
2810 | |
2811 | /* | |
2812 | * If the earlier platform check has not triggered, D3cold is just power | |
2813 | * removal on top of D3hot, so no need to resume the device in that | |
2814 | * case. | |
2815 | */ | |
0c7376ad RW |
2816 | return target_state != pci_dev->current_state && |
2817 | target_state != PCI_D3cold && | |
2818 | pci_dev->current_state != PCI_D3hot; | |
2819 | } | |
2820 | ||
2821 | /** | |
2822 | * pci_dev_adjust_pme - Adjust PME setting for a suspended device. | |
2823 | * @pci_dev: Device to check. | |
2824 | * | |
2825 | * If the device is suspended and it is not configured for system wakeup, | |
2826 | * disable PME for it to prevent it from waking up the system unnecessarily. | |
2827 | * | |
2828 | * Note that if the device's power state is D3cold and the platform check in | |
2829 | * pci_dev_need_resume() has not triggered, the device's configuration need not | |
2830 | * be changed. | |
2831 | */ | |
2832 | void pci_dev_adjust_pme(struct pci_dev *pci_dev) | |
2833 | { | |
2834 | struct device *dev = &pci_dev->dev; | |
bac2a909 | 2835 | |
2cef548a RW |
2836 | spin_lock_irq(&dev->power.lock); |
2837 | ||
0c7376ad RW |
2838 | if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) && |
2839 | pci_dev->current_state < PCI_D3cold) | |
2cef548a RW |
2840 | __pci_pme_active(pci_dev, false); |
2841 | ||
2842 | spin_unlock_irq(&dev->power.lock); | |
2cef548a RW |
2843 | } |
2844 | ||
2845 | /** | |
2846 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2847 | * @pci_dev: Device to handle. | |
2848 | * | |
2849 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2850 | * it might have been disabled during the prepare phase of system suspend if | |
2851 | * the device was not configured for system wakeup. | |
2852 | */ | |
2853 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2854 | { | |
2855 | struct device *dev = &pci_dev->dev; | |
2856 | ||
2857 | if (!pci_dev_run_wake(pci_dev)) | |
2858 | return; | |
2859 | ||
2860 | spin_lock_irq(&dev->power.lock); | |
2861 | ||
2862 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2863 | __pci_pme_active(pci_dev, true); | |
2864 | ||
2865 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2866 | } |
2867 | ||
b3c32c4f HY |
2868 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2869 | { | |
2870 | struct device *dev = &pdev->dev; | |
2871 | struct device *parent = dev->parent; | |
2872 | ||
2873 | if (parent) | |
2874 | pm_runtime_get_sync(parent); | |
2875 | pm_runtime_get_noresume(dev); | |
2876 | /* | |
2877 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2878 | * so wait until suspending completes | |
2879 | */ | |
2880 | pm_runtime_barrier(dev); | |
2881 | /* | |
2882 | * Only need to resume devices in D3cold, because config | |
2883 | * registers are still accessible for devices suspended but | |
2884 | * not in D3cold. | |
2885 | */ | |
2886 | if (pdev->current_state == PCI_D3cold) | |
2887 | pm_runtime_resume(dev); | |
2888 | } | |
2889 | ||
2890 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2891 | { | |
2892 | struct device *dev = &pdev->dev; | |
2893 | struct device *parent = dev->parent; | |
2894 | ||
2895 | pm_runtime_put(dev); | |
2896 | if (parent) | |
2897 | pm_runtime_put_sync(parent); | |
2898 | } | |
2899 | ||
85b0cae8 MW |
2900 | static const struct dmi_system_id bridge_d3_blacklist[] = { |
2901 | #ifdef CONFIG_X86 | |
2902 | { | |
2903 | /* | |
2904 | * Gigabyte X299 root port is not marked as hotplug capable | |
2905 | * which allows Linux to power manage it. However, this | |
2906 | * confuses the BIOS SMI handler so don't power manage root | |
2907 | * ports on that system. | |
2908 | */ | |
2909 | .ident = "X299 DESIGNARE EX-CF", | |
2910 | .matches = { | |
2911 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
2912 | DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"), | |
2913 | }, | |
ab1fa0fb BH |
2914 | }, |
2915 | { | |
6bc18d6a RW |
2916 | /* |
2917 | * Downstream device is not accessible after putting a root port | |
2918 | * into D3cold and back into D0 on Elo i2. | |
2919 | */ | |
2920 | .ident = "Elo i2", | |
2921 | .matches = { | |
2922 | DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"), | |
2923 | DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"), | |
2924 | DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"), | |
2925 | }, | |
85b0cae8 MW |
2926 | }, |
2927 | #endif | |
2928 | { } | |
2929 | }; | |
2930 | ||
9d26d3a8 MW |
2931 | /** |
2932 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2933 | * @bridge: Bridge to check | |
2934 | * | |
2935 | * This function checks if it is possible to move the bridge to D3. | |
47a8e237 | 2936 | * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt. |
9d26d3a8 | 2937 | */ |
c6a63307 | 2938 | bool pci_bridge_d3_possible(struct pci_dev *bridge) |
9d26d3a8 | 2939 | { |
9d26d3a8 MW |
2940 | if (!pci_is_pcie(bridge)) |
2941 | return false; | |
2942 | ||
2943 | switch (pci_pcie_type(bridge)) { | |
2944 | case PCI_EXP_TYPE_ROOT_PORT: | |
2945 | case PCI_EXP_TYPE_UPSTREAM: | |
2946 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2947 | if (pci_bridge_d3_disable) | |
2948 | return false; | |
97a90aee LW |
2949 | |
2950 | /* | |
eb3b5bf1 | 2951 | * Hotplug ports handled by firmware in System Management Mode |
97a90aee | 2952 | * may not be put into D3 by the OS (Thunderbolt on non-Macs). |
97a90aee | 2953 | */ |
eb3b5bf1 | 2954 | if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) |
97a90aee LW |
2955 | return false; |
2956 | ||
9d26d3a8 MW |
2957 | if (pci_bridge_d3_force) |
2958 | return true; | |
2959 | ||
47a8e237 LW |
2960 | /* Even the oldest 2010 Thunderbolt controller supports D3. */ |
2961 | if (bridge->is_thunderbolt) | |
2962 | return true; | |
2963 | ||
26ad34d5 MW |
2964 | /* Platform might know better if the bridge supports D3 */ |
2965 | if (platform_pci_bridge_d3(bridge)) | |
2966 | return true; | |
2967 | ||
eb3b5bf1 LW |
2968 | /* |
2969 | * Hotplug ports handled natively by the OS were not validated | |
2970 | * by vendors for runtime D3 at least until 2018 because there | |
2971 | * was no OS support. | |
2972 | */ | |
2973 | if (bridge->is_hotplug_bridge) | |
2974 | return false; | |
2975 | ||
85b0cae8 MW |
2976 | if (dmi_check_system(bridge_d3_blacklist)) |
2977 | return false; | |
2978 | ||
9d26d3a8 MW |
2979 | /* |
2980 | * It should be safe to put PCIe ports from 2015 or newer | |
2981 | * to D3. | |
2982 | */ | |
ac95090a | 2983 | if (dmi_get_bios_year() >= 2015) |
9d26d3a8 | 2984 | return true; |
9d26d3a8 MW |
2985 | break; |
2986 | } | |
2987 | ||
2988 | return false; | |
2989 | } | |
2990 | ||
2991 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2992 | { | |
2993 | bool *d3cold_ok = data; | |
9d26d3a8 | 2994 | |
718a0609 LW |
2995 | if (/* The device needs to be allowed to go D3cold ... */ |
2996 | dev->no_d3cold || !dev->d3cold_allowed || | |
2997 | ||
2998 | /* ... and if it is wakeup capable to do so from D3cold. */ | |
2999 | (device_may_wakeup(&dev->dev) && | |
3000 | !pci_pme_capable(dev, PCI_D3cold)) || | |
3001 | ||
3002 | /* If it is a bridge it must be allowed to go to D3. */ | |
d98e0929 | 3003 | !pci_power_manageable(dev)) |
9d26d3a8 | 3004 | |
718a0609 | 3005 | *d3cold_ok = false; |
9d26d3a8 | 3006 | |
718a0609 | 3007 | return !*d3cold_ok; |
9d26d3a8 MW |
3008 | } |
3009 | ||
3010 | /* | |
3011 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
3012 | * @dev: PCI device which is changed | |
9d26d3a8 MW |
3013 | * |
3014 | * Update upstream bridge PM capabilities accordingly depending on if the | |
3015 | * device PM configuration was changed or the device is being removed. The | |
3016 | * change is also propagated upstream. | |
3017 | */ | |
1ed276a7 | 3018 | void pci_bridge_d3_update(struct pci_dev *dev) |
9d26d3a8 | 3019 | { |
1ed276a7 | 3020 | bool remove = !device_is_registered(&dev->dev); |
9d26d3a8 MW |
3021 | struct pci_dev *bridge; |
3022 | bool d3cold_ok = true; | |
3023 | ||
3024 | bridge = pci_upstream_bridge(dev); | |
3025 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
3026 | return; | |
3027 | ||
9d26d3a8 | 3028 | /* |
e8559b71 LW |
3029 | * If D3 is currently allowed for the bridge, removing one of its |
3030 | * children won't change that. | |
3031 | */ | |
3032 | if (remove && bridge->bridge_d3) | |
3033 | return; | |
3034 | ||
3035 | /* | |
3036 | * If D3 is currently allowed for the bridge and a child is added or | |
3037 | * changed, disallowance of D3 can only be caused by that child, so | |
3038 | * we only need to check that single device, not any of its siblings. | |
3039 | * | |
3040 | * If D3 is currently not allowed for the bridge, checking the device | |
3041 | * first may allow us to skip checking its siblings. | |
9d26d3a8 MW |
3042 | */ |
3043 | if (!remove) | |
3044 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
3045 | ||
e8559b71 LW |
3046 | /* |
3047 | * If D3 is currently not allowed for the bridge, this may be caused | |
3048 | * either by the device being changed/removed or any of its siblings, | |
3049 | * so we need to go through all children to find out if one of them | |
3050 | * continues to block D3. | |
3051 | */ | |
3052 | if (d3cold_ok && !bridge->bridge_d3) | |
9d26d3a8 MW |
3053 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, |
3054 | &d3cold_ok); | |
9d26d3a8 MW |
3055 | |
3056 | if (bridge->bridge_d3 != d3cold_ok) { | |
3057 | bridge->bridge_d3 = d3cold_ok; | |
3058 | /* Propagate change to upstream bridges */ | |
1ed276a7 | 3059 | pci_bridge_d3_update(bridge); |
9d26d3a8 | 3060 | } |
9d26d3a8 MW |
3061 | } |
3062 | ||
9d26d3a8 MW |
3063 | /** |
3064 | * pci_d3cold_enable - Enable D3cold for device | |
3065 | * @dev: PCI device to handle | |
3066 | * | |
3067 | * This function can be used in drivers to enable D3cold from the device | |
3068 | * they handle. It also updates upstream PCI bridge PM capabilities | |
3069 | * accordingly. | |
3070 | */ | |
3071 | void pci_d3cold_enable(struct pci_dev *dev) | |
3072 | { | |
3073 | if (dev->no_d3cold) { | |
3074 | dev->no_d3cold = false; | |
1ed276a7 | 3075 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
3076 | } |
3077 | } | |
3078 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
3079 | ||
3080 | /** | |
3081 | * pci_d3cold_disable - Disable D3cold for device | |
3082 | * @dev: PCI device to handle | |
3083 | * | |
3084 | * This function can be used in drivers to disable D3cold from the device | |
3085 | * they handle. It also updates upstream PCI bridge PM capabilities | |
3086 | * accordingly. | |
3087 | */ | |
3088 | void pci_d3cold_disable(struct pci_dev *dev) | |
3089 | { | |
3090 | if (!dev->no_d3cold) { | |
3091 | dev->no_d3cold = true; | |
1ed276a7 | 3092 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
3093 | } |
3094 | } | |
3095 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
3096 | ||
eb9d0fe4 RW |
3097 | /** |
3098 | * pci_pm_init - Initialize PM functions of given PCI device | |
3099 | * @dev: PCI device to handle. | |
3100 | */ | |
3101 | void pci_pm_init(struct pci_dev *dev) | |
3102 | { | |
3103 | int pm; | |
d6112f8d | 3104 | u16 status; |
eb9d0fe4 | 3105 | u16 pmc; |
1da177e4 | 3106 | |
bb910a70 | 3107 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
3108 | pm_runtime_set_active(&dev->dev); |
3109 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 3110 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 3111 | dev->wakeup_prepared = false; |
bb910a70 | 3112 | |
337001b6 | 3113 | dev->pm_cap = 0; |
ffaddbe8 | 3114 | dev->pme_support = 0; |
337001b6 | 3115 | |
eb9d0fe4 RW |
3116 | /* find PCI PM capability in list */ |
3117 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
3118 | if (!pm) | |
50246dd4 | 3119 | return; |
eb9d0fe4 RW |
3120 | /* Check device's ability to generate PME# */ |
3121 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 3122 | |
eb9d0fe4 | 3123 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
7506dc79 | 3124 | pci_err(dev, "unsupported PM cap regs version (%u)\n", |
eb9d0fe4 | 3125 | pmc & PCI_PM_CAP_VER_MASK); |
50246dd4 | 3126 | return; |
eb9d0fe4 RW |
3127 | } |
3128 | ||
337001b6 | 3129 | dev->pm_cap = pm; |
3789af9a | 3130 | dev->d3hot_delay = PCI_PM_D3HOT_WAIT; |
448bd857 | 3131 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 3132 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 3133 | dev->d3cold_allowed = true; |
337001b6 RW |
3134 | |
3135 | dev->d1_support = false; | |
3136 | dev->d2_support = false; | |
3137 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 3138 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 3139 | dev->d1_support = true; |
c9ed77ee | 3140 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 3141 | dev->d2_support = true; |
c9ed77ee BH |
3142 | |
3143 | if (dev->d1_support || dev->d2_support) | |
34c6b710 | 3144 | pci_info(dev, "supports%s%s\n", |
ec84f126 JB |
3145 | dev->d1_support ? " D1" : "", |
3146 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
3147 | } |
3148 | ||
3149 | pmc &= PCI_PM_CAP_PME_MASK; | |
3150 | if (pmc) { | |
34c6b710 | 3151 | pci_info(dev, "PME# supported from%s%s%s%s%s\n", |
c9ed77ee BH |
3152 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
3153 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
3154 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
3789af9a | 3155 | (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "", |
c9ed77ee | 3156 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); |
337001b6 | 3157 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 3158 | dev->pme_poll = true; |
eb9d0fe4 RW |
3159 | /* |
3160 | * Make device's PM flags reflect the wake-up capability, but | |
3161 | * let the user space enable it to wake up the system as needed. | |
3162 | */ | |
3163 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 3164 | /* Disable the PME# generation functionality */ |
337001b6 | 3165 | pci_pme_active(dev, false); |
eb9d0fe4 | 3166 | } |
d6112f8d FB |
3167 | |
3168 | pci_read_config_word(dev, PCI_STATUS, &status); | |
3169 | if (status & PCI_STATUS_IMM_READY) | |
3170 | dev->imm_ready = 1; | |
1da177e4 LT |
3171 | } |
3172 | ||
938174e5 SS |
3173 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
3174 | { | |
92efb1bd | 3175 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
3176 | |
3177 | switch (prop) { | |
3178 | case PCI_EA_P_MEM: | |
3179 | case PCI_EA_P_VF_MEM: | |
3180 | flags |= IORESOURCE_MEM; | |
3181 | break; | |
3182 | case PCI_EA_P_MEM_PREFETCH: | |
3183 | case PCI_EA_P_VF_MEM_PREFETCH: | |
3184 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
3185 | break; | |
3186 | case PCI_EA_P_IO: | |
3187 | flags |= IORESOURCE_IO; | |
3188 | break; | |
3189 | default: | |
3190 | return 0; | |
3191 | } | |
3192 | ||
3193 | return flags; | |
3194 | } | |
3195 | ||
3196 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
3197 | u8 prop) | |
3198 | { | |
3199 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
3200 | return &dev->resource[bei]; | |
11183991 DD |
3201 | #ifdef CONFIG_PCI_IOV |
3202 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
3203 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
3204 | return &dev->resource[PCI_IOV_RESOURCES + | |
3205 | bei - PCI_EA_BEI_VF_BAR0]; | |
3206 | #endif | |
938174e5 SS |
3207 | else if (bei == PCI_EA_BEI_ROM) |
3208 | return &dev->resource[PCI_ROM_RESOURCE]; | |
3209 | else | |
3210 | return NULL; | |
3211 | } | |
3212 | ||
3213 | /* Read an Enhanced Allocation (EA) entry */ | |
3214 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
3215 | { | |
3216 | struct resource *res; | |
3217 | int ent_size, ent_offset = offset; | |
3218 | resource_size_t start, end; | |
3219 | unsigned long flags; | |
26635112 | 3220 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
3221 | u8 prop; |
3222 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
3223 | ||
3224 | pci_read_config_dword(dev, ent_offset, &dw0); | |
3225 | ent_offset += 4; | |
3226 | ||
3227 | /* Entry size field indicates DWORDs after 1st */ | |
3228 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
3229 | ||
3230 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
3231 | goto out; | |
3232 | ||
26635112 BH |
3233 | bei = (dw0 & PCI_EA_BEI) >> 4; |
3234 | prop = (dw0 & PCI_EA_PP) >> 8; | |
3235 | ||
938174e5 SS |
3236 | /* |
3237 | * If the Property is in the reserved range, try the Secondary | |
3238 | * Property instead. | |
3239 | */ | |
3240 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 3241 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
3242 | if (prop > PCI_EA_P_BRIDGE_IO) |
3243 | goto out; | |
3244 | ||
26635112 | 3245 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 3246 | if (!res) { |
7506dc79 | 3247 | pci_err(dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
3248 | goto out; |
3249 | } | |
3250 | ||
3251 | flags = pci_ea_flags(dev, prop); | |
3252 | if (!flags) { | |
7506dc79 | 3253 | pci_err(dev, "Unsupported EA properties: %#x\n", prop); |
938174e5 SS |
3254 | goto out; |
3255 | } | |
3256 | ||
3257 | /* Read Base */ | |
3258 | pci_read_config_dword(dev, ent_offset, &base); | |
3259 | start = (base & PCI_EA_FIELD_MASK); | |
3260 | ent_offset += 4; | |
3261 | ||
3262 | /* Read MaxOffset */ | |
3263 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
3264 | ent_offset += 4; | |
3265 | ||
3266 | /* Read Base MSBs (if 64-bit entry) */ | |
3267 | if (base & PCI_EA_IS_64) { | |
3268 | u32 base_upper; | |
3269 | ||
3270 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
3271 | ent_offset += 4; | |
3272 | ||
3273 | flags |= IORESOURCE_MEM_64; | |
3274 | ||
3275 | /* entry starts above 32-bit boundary, can't use */ | |
3276 | if (!support_64 && base_upper) | |
3277 | goto out; | |
3278 | ||
3279 | if (support_64) | |
3280 | start |= ((u64)base_upper << 32); | |
3281 | } | |
3282 | ||
3283 | end = start + (max_offset | 0x03); | |
3284 | ||
3285 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
3286 | if (max_offset & PCI_EA_IS_64) { | |
3287 | u32 max_offset_upper; | |
3288 | ||
3289 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
3290 | ent_offset += 4; | |
3291 | ||
3292 | flags |= IORESOURCE_MEM_64; | |
3293 | ||
3294 | /* entry too big, can't use */ | |
3295 | if (!support_64 && max_offset_upper) | |
3296 | goto out; | |
3297 | ||
3298 | if (support_64) | |
3299 | end += ((u64)max_offset_upper << 32); | |
3300 | } | |
3301 | ||
3302 | if (end < start) { | |
7506dc79 | 3303 | pci_err(dev, "EA Entry crosses address boundary\n"); |
938174e5 SS |
3304 | goto out; |
3305 | } | |
3306 | ||
3307 | if (ent_size != ent_offset - offset) { | |
7506dc79 | 3308 | pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", |
938174e5 SS |
3309 | ent_size, ent_offset - offset); |
3310 | goto out; | |
3311 | } | |
3312 | ||
3313 | res->name = pci_name(dev); | |
3314 | res->start = start; | |
3315 | res->end = end; | |
3316 | res->flags = flags; | |
597becb4 BH |
3317 | |
3318 | if (bei <= PCI_EA_BEI_BAR5) | |
34c6b710 | 3319 | pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3320 | bei, res, prop); |
3321 | else if (bei == PCI_EA_BEI_ROM) | |
34c6b710 | 3322 | pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3323 | res, prop); |
3324 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
34c6b710 | 3325 | pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3326 | bei - PCI_EA_BEI_VF_BAR0, res, prop); |
3327 | else | |
34c6b710 | 3328 | pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3329 | bei, res, prop); |
3330 | ||
938174e5 SS |
3331 | out: |
3332 | return offset + ent_size; | |
3333 | } | |
3334 | ||
dcbb408a | 3335 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
3336 | void pci_ea_init(struct pci_dev *dev) |
3337 | { | |
3338 | int ea; | |
3339 | u8 num_ent; | |
3340 | int offset; | |
3341 | int i; | |
3342 | ||
3343 | /* find PCI EA capability in list */ | |
3344 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
3345 | if (!ea) | |
3346 | return; | |
3347 | ||
3348 | /* determine the number of entries */ | |
3349 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
3350 | &num_ent); | |
3351 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
3352 | ||
3353 | offset = ea + PCI_EA_FIRST_ENT; | |
3354 | ||
3355 | /* Skip DWORD 2 for type 1 functions */ | |
3356 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
3357 | offset += 4; | |
3358 | ||
3359 | /* parse each EA entry */ | |
3360 | for (i = 0; i < num_ent; ++i) | |
3361 | offset = pci_ea_read(dev, offset); | |
3362 | } | |
3363 | ||
34a4876e YL |
3364 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
3365 | struct pci_cap_saved_state *new_cap) | |
3366 | { | |
3367 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
3368 | } | |
3369 | ||
63f4898a | 3370 | /** |
fd0f7f73 | 3371 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
74356add | 3372 | * capability registers |
63f4898a RW |
3373 | * @dev: the PCI device |
3374 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 3375 | * @extended: Standard or Extended capability ID |
63f4898a RW |
3376 | * @size: requested size of the buffer |
3377 | */ | |
fd0f7f73 AW |
3378 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
3379 | bool extended, unsigned int size) | |
63f4898a RW |
3380 | { |
3381 | int pos; | |
3382 | struct pci_cap_saved_state *save_state; | |
3383 | ||
fd0f7f73 AW |
3384 | if (extended) |
3385 | pos = pci_find_ext_capability(dev, cap); | |
3386 | else | |
3387 | pos = pci_find_capability(dev, cap); | |
3388 | ||
0a1a9b49 | 3389 | if (!pos) |
63f4898a RW |
3390 | return 0; |
3391 | ||
3392 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
3393 | if (!save_state) | |
3394 | return -ENOMEM; | |
3395 | ||
24a4742f | 3396 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 3397 | save_state->cap.cap_extended = extended; |
24a4742f | 3398 | save_state->cap.size = size; |
63f4898a RW |
3399 | pci_add_saved_cap(dev, save_state); |
3400 | ||
3401 | return 0; | |
3402 | } | |
3403 | ||
fd0f7f73 AW |
3404 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
3405 | { | |
3406 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
3407 | } | |
3408 | ||
3409 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
3410 | { | |
3411 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
3412 | } | |
3413 | ||
63f4898a RW |
3414 | /** |
3415 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
3416 | * @dev: the PCI device | |
3417 | */ | |
3418 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
3419 | { | |
3420 | int error; | |
3421 | ||
89858517 YZ |
3422 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
3423 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a | 3424 | if (error) |
7506dc79 | 3425 | pci_err(dev, "unable to preallocate PCI Express save buffer\n"); |
63f4898a RW |
3426 | |
3427 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
3428 | if (error) | |
7506dc79 | 3429 | pci_err(dev, "unable to preallocate PCI-X save buffer\n"); |
425c1b22 | 3430 | |
dbbfadf2 BH |
3431 | error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR, |
3432 | 2 * sizeof(u16)); | |
3433 | if (error) | |
3434 | pci_err(dev, "unable to allocate suspend buffer for LTR\n"); | |
3435 | ||
ad0f2ad6 CLKA |
3436 | if (dmi_check_system(aspm_fix_whitelist)) { |
3437 | error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS, | |
3438 | 2 * sizeof(u32)); | |
3439 | if (error) | |
3440 | pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n"); | |
3441 | } | |
218afb81 | 3442 | |
425c1b22 | 3443 | pci_allocate_vc_save_buffers(dev); |
63f4898a RW |
3444 | } |
3445 | ||
f796841e YL |
3446 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
3447 | { | |
3448 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 3449 | struct hlist_node *n; |
f796841e | 3450 | |
b67bfe0d | 3451 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
3452 | kfree(tmp); |
3453 | } | |
3454 | ||
58c3a727 | 3455 | /** |
31ab2476 | 3456 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 3457 | * @dev: the PCI device |
b0cc6020 YW |
3458 | * |
3459 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
3460 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 3461 | */ |
31ab2476 | 3462 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 3463 | { |
58c3a727 | 3464 | u32 cap; |
8113587c | 3465 | struct pci_dev *bridge; |
58c3a727 | 3466 | |
6748dcc2 | 3467 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
3468 | return; |
3469 | ||
8113587c | 3470 | bridge = dev->bus->self; |
cb97ae34 | 3471 | if (!bridge) |
8113587c ZY |
3472 | return; |
3473 | ||
59875ae4 | 3474 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
3475 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
3476 | return; | |
3477 | ||
b0cc6020 YW |
3478 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
3479 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
3480 | PCI_EXP_DEVCTL2_ARI); | |
3481 | bridge->ari_enabled = 1; | |
3482 | } else { | |
3483 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
3484 | PCI_EXP_DEVCTL2_ARI); | |
3485 | bridge->ari_enabled = 0; | |
3486 | } | |
58c3a727 YZ |
3487 | } |
3488 | ||
0a67119f AW |
3489 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
3490 | { | |
3491 | int pos; | |
83db7e0b | 3492 | u16 cap, ctrl; |
0a67119f | 3493 | |
52fbf5bd | 3494 | pos = pdev->acs_cap; |
0a67119f AW |
3495 | if (!pos) |
3496 | return false; | |
3497 | ||
83db7e0b AW |
3498 | /* |
3499 | * Except for egress control, capabilities are either required | |
3500 | * or only required if controllable. Features missing from the | |
3501 | * capability field can therefore be assumed as hard-wired enabled. | |
3502 | */ | |
3503 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
3504 | acs_flags &= (cap | PCI_ACS_EC); | |
3505 | ||
0a67119f AW |
3506 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
3507 | return (ctrl & acs_flags) == acs_flags; | |
3508 | } | |
3509 | ||
ad805758 AW |
3510 | /** |
3511 | * pci_acs_enabled - test ACS against required flags for a given device | |
3512 | * @pdev: device to test | |
3513 | * @acs_flags: required PCI ACS flags | |
3514 | * | |
3515 | * Return true if the device supports the provided flags. Automatically | |
3516 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
3517 | * |
3518 | * Note that this interface checks the effective ACS capabilities of the | |
3519 | * device rather than the actual capabilities. For instance, most single | |
3520 | * function endpoints are not required to support ACS because they have no | |
3521 | * opportunity for peer-to-peer access. We therefore return 'true' | |
3522 | * regardless of whether the device exposes an ACS capability. This makes | |
3523 | * it much easier for callers of this function to ignore the actual type | |
3524 | * or topology of the device when testing ACS support. | |
ad805758 AW |
3525 | */ |
3526 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
3527 | { | |
0a67119f | 3528 | int ret; |
ad805758 AW |
3529 | |
3530 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
3531 | if (ret >= 0) | |
3532 | return ret > 0; | |
3533 | ||
0a67119f AW |
3534 | /* |
3535 | * Conventional PCI and PCI-X devices never support ACS, either | |
3536 | * effectively or actually. The shared bus topology implies that | |
3537 | * any device on the bus can receive or snoop DMA. | |
3538 | */ | |
ad805758 AW |
3539 | if (!pci_is_pcie(pdev)) |
3540 | return false; | |
3541 | ||
0a67119f AW |
3542 | switch (pci_pcie_type(pdev)) { |
3543 | /* | |
3544 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 3545 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
3546 | * handle them as we would a non-PCIe device. |
3547 | */ | |
3548 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
3549 | /* | |
3550 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
3551 | * applicable... must never implement an ACS Extended Capability...". | |
3552 | * This seems arbitrary, but we take a conservative interpretation | |
3553 | * of this statement. | |
3554 | */ | |
3555 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
3556 | case PCI_EXP_TYPE_RC_EC: | |
3557 | return false; | |
3558 | /* | |
3559 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
3560 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
3561 | * regardless of whether they are single- or multi-function devices. | |
3562 | */ | |
3563 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3564 | case PCI_EXP_TYPE_ROOT_PORT: | |
3565 | return pci_acs_flags_enabled(pdev, acs_flags); | |
3566 | /* | |
3567 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
3568 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 3569 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
3570 | * device. The footnote for section 6.12 indicates the specific |
3571 | * PCIe types included here. | |
3572 | */ | |
3573 | case PCI_EXP_TYPE_ENDPOINT: | |
3574 | case PCI_EXP_TYPE_UPSTREAM: | |
3575 | case PCI_EXP_TYPE_LEG_END: | |
3576 | case PCI_EXP_TYPE_RC_END: | |
3577 | if (!pdev->multifunction) | |
3578 | break; | |
3579 | ||
0a67119f | 3580 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
3581 | } |
3582 | ||
0a67119f | 3583 | /* |
f7625980 | 3584 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
3585 | * to single function devices with the exception of downstream ports. |
3586 | */ | |
ad805758 AW |
3587 | return true; |
3588 | } | |
3589 | ||
3590 | /** | |
2f0cd59c | 3591 | * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy |
ad805758 AW |
3592 | * @start: starting downstream device |
3593 | * @end: ending upstream device or NULL to search to the root bus | |
3594 | * @acs_flags: required flags | |
3595 | * | |
3596 | * Walk up a device tree from start to end testing PCI ACS support. If | |
3597 | * any step along the way does not support the required flags, return false. | |
3598 | */ | |
3599 | bool pci_acs_path_enabled(struct pci_dev *start, | |
3600 | struct pci_dev *end, u16 acs_flags) | |
3601 | { | |
3602 | struct pci_dev *pdev, *parent = start; | |
3603 | ||
3604 | do { | |
3605 | pdev = parent; | |
3606 | ||
3607 | if (!pci_acs_enabled(pdev, acs_flags)) | |
3608 | return false; | |
3609 | ||
3610 | if (pci_is_root_bus(pdev->bus)) | |
3611 | return (end == NULL); | |
3612 | ||
3613 | parent = pdev->bus->self; | |
3614 | } while (pdev != end); | |
3615 | ||
3616 | return true; | |
3617 | } | |
3618 | ||
52fbf5bd RJ |
3619 | /** |
3620 | * pci_acs_init - Initialize ACS if hardware supports it | |
3621 | * @dev: the PCI device | |
3622 | */ | |
3623 | void pci_acs_init(struct pci_dev *dev) | |
3624 | { | |
3625 | dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
3626 | ||
462b58fb RJ |
3627 | /* |
3628 | * Attempt to enable ACS regardless of capability because some Root | |
3629 | * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have | |
3630 | * the standard ACS capability but still support ACS via those | |
3631 | * quirks. | |
3632 | */ | |
3633 | pci_enable_acs(dev); | |
52fbf5bd RJ |
3634 | } |
3635 | ||
276b738d CK |
3636 | /** |
3637 | * pci_rebar_find_pos - find position of resize ctrl reg for BAR | |
3638 | * @pdev: PCI device | |
3639 | * @bar: BAR to find | |
3640 | * | |
3641 | * Helper to find the position of the ctrl register for a BAR. | |
3642 | * Returns -ENOTSUPP if resizable BARs are not supported at all. | |
3643 | * Returns -ENOENT if no ctrl register for the BAR could be found. | |
3644 | */ | |
3645 | static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) | |
3646 | { | |
3647 | unsigned int pos, nbars, i; | |
3648 | u32 ctrl; | |
3649 | ||
3650 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
3651 | if (!pos) | |
3652 | return -ENOTSUPP; | |
3653 | ||
3654 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3655 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
3656 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
3657 | ||
3658 | for (i = 0; i < nbars; i++, pos += 8) { | |
3659 | int bar_idx; | |
3660 | ||
3661 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3662 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
3663 | if (bar_idx == bar) | |
3664 | return pos; | |
3665 | } | |
3666 | ||
3667 | return -ENOENT; | |
3668 | } | |
3669 | ||
3670 | /** | |
3671 | * pci_rebar_get_possible_sizes - get possible sizes for BAR | |
3672 | * @pdev: PCI device | |
3673 | * @bar: BAR to query | |
3674 | * | |
3675 | * Get the possible sizes of a resizable BAR as bitmask defined in the spec | |
3676 | * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable. | |
3677 | */ | |
3678 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) | |
3679 | { | |
3680 | int pos; | |
3681 | u32 cap; | |
3682 | ||
3683 | pos = pci_rebar_find_pos(pdev, bar); | |
3684 | if (pos < 0) | |
3685 | return 0; | |
3686 | ||
3687 | pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); | |
907830b0 ND |
3688 | cap &= PCI_REBAR_CAP_SIZES; |
3689 | ||
3690 | /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ | |
3691 | if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && | |
3692 | bar == 0 && cap == 0x7000) | |
3693 | cap = 0x3f000; | |
3694 | ||
3695 | return cap >> 4; | |
276b738d | 3696 | } |
8fbdbb66 | 3697 | EXPORT_SYMBOL(pci_rebar_get_possible_sizes); |
276b738d CK |
3698 | |
3699 | /** | |
3700 | * pci_rebar_get_current_size - get the current size of a BAR | |
3701 | * @pdev: PCI device | |
3702 | * @bar: BAR to set size to | |
3703 | * | |
3704 | * Read the size of a BAR from the resizable BAR config. | |
3705 | * Returns size if found or negative error code. | |
3706 | */ | |
3707 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) | |
3708 | { | |
3709 | int pos; | |
3710 | u32 ctrl; | |
3711 | ||
3712 | pos = pci_rebar_find_pos(pdev, bar); | |
3713 | if (pos < 0) | |
3714 | return pos; | |
3715 | ||
3716 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
b1277a22 | 3717 | return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3718 | } |
3719 | ||
3720 | /** | |
3721 | * pci_rebar_set_size - set a new size for a BAR | |
3722 | * @pdev: PCI device | |
3723 | * @bar: BAR to set size to | |
3724 | * @size: new size as defined in the spec (0=1MB, 19=512GB) | |
3725 | * | |
3726 | * Set the new size of a BAR as defined in the spec. | |
3727 | * Returns zero if resizing was successful, error code otherwise. | |
3728 | */ | |
3729 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) | |
3730 | { | |
3731 | int pos; | |
3732 | u32 ctrl; | |
3733 | ||
3734 | pos = pci_rebar_find_pos(pdev, bar); | |
3735 | if (pos < 0) | |
3736 | return pos; | |
3737 | ||
3738 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3739 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
b1277a22 | 3740 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3741 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
3742 | return 0; | |
3743 | } | |
3744 | ||
430a2368 JC |
3745 | /** |
3746 | * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port | |
3747 | * @dev: the PCI device | |
3748 | * @cap_mask: mask of desired AtomicOp sizes, including one or more of: | |
3749 | * PCI_EXP_DEVCAP2_ATOMIC_COMP32 | |
3750 | * PCI_EXP_DEVCAP2_ATOMIC_COMP64 | |
3751 | * PCI_EXP_DEVCAP2_ATOMIC_COMP128 | |
3752 | * | |
3753 | * Return 0 if all upstream bridges support AtomicOp routing, egress | |
3754 | * blocking is disabled on all upstream ports, and the root port supports | |
3755 | * the requested completion capabilities (32-bit, 64-bit and/or 128-bit | |
3756 | * AtomicOp completion), or negative otherwise. | |
3757 | */ | |
3758 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) | |
3759 | { | |
3760 | struct pci_bus *bus = dev->bus; | |
3761 | struct pci_dev *bridge; | |
3762 | u32 cap, ctl2; | |
3763 | ||
59796c91 SX |
3764 | /* |
3765 | * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit | |
3766 | * in Device Control 2 is reserved in VFs and the PF value applies | |
3767 | * to all associated VFs. | |
3768 | */ | |
3769 | if (dev->is_virtfn) | |
3770 | return -EINVAL; | |
3771 | ||
430a2368 JC |
3772 | if (!pci_is_pcie(dev)) |
3773 | return -EINVAL; | |
3774 | ||
3775 | /* | |
3776 | * Per PCIe r4.0, sec 6.15, endpoints and root ports may be | |
3777 | * AtomicOp requesters. For now, we only support endpoints as | |
3778 | * requesters and root ports as completers. No endpoints as | |
3779 | * completers, and no peer-to-peer. | |
3780 | */ | |
3781 | ||
3782 | switch (pci_pcie_type(dev)) { | |
3783 | case PCI_EXP_TYPE_ENDPOINT: | |
3784 | case PCI_EXP_TYPE_LEG_END: | |
3785 | case PCI_EXP_TYPE_RC_END: | |
3786 | break; | |
3787 | default: | |
3788 | return -EINVAL; | |
3789 | } | |
3790 | ||
3791 | while (bus->parent) { | |
3792 | bridge = bus->self; | |
3793 | ||
3794 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); | |
3795 | ||
3796 | switch (pci_pcie_type(bridge)) { | |
3797 | /* Ensure switch ports support AtomicOp routing */ | |
3798 | case PCI_EXP_TYPE_UPSTREAM: | |
3799 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3800 | if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) | |
3801 | return -EINVAL; | |
3802 | break; | |
3803 | ||
3804 | /* Ensure root port supports all the sizes we care about */ | |
3805 | case PCI_EXP_TYPE_ROOT_PORT: | |
3806 | if ((cap & cap_mask) != cap_mask) | |
3807 | return -EINVAL; | |
3808 | break; | |
3809 | } | |
3810 | ||
3811 | /* Ensure upstream ports don't block AtomicOps on egress */ | |
ca784104 | 3812 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { |
430a2368 JC |
3813 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, |
3814 | &ctl2); | |
3815 | if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) | |
3816 | return -EINVAL; | |
3817 | } | |
3818 | ||
3819 | bus = bus->parent; | |
3820 | } | |
3821 | ||
3822 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, | |
3823 | PCI_EXP_DEVCTL2_ATOMIC_REQ); | |
3824 | return 0; | |
3825 | } | |
3826 | EXPORT_SYMBOL(pci_enable_atomic_ops_to_root); | |
3827 | ||
57c2cf71 BH |
3828 | /** |
3829 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
3830 | * @dev: the PCI device | |
bb5c2de2 | 3831 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
3832 | * |
3833 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
3834 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
3835 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
3836 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
3837 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 3838 | */ |
3df425f3 | 3839 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 3840 | { |
46b952a3 MW |
3841 | int slot; |
3842 | ||
3843 | if (pci_ari_enabled(dev->bus)) | |
3844 | slot = 0; | |
3845 | else | |
3846 | slot = PCI_SLOT(dev->devfn); | |
3847 | ||
3848 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
3849 | } |
3850 | ||
3c78bc61 | 3851 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
3852 | { |
3853 | u8 pin; | |
3854 | ||
514d207d | 3855 | pin = dev->pin; |
1da177e4 LT |
3856 | if (!pin) |
3857 | return -1; | |
878f2e50 | 3858 | |
8784fd4d | 3859 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 3860 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
3861 | dev = dev->bus->self; |
3862 | } | |
3863 | *bridge = dev; | |
3864 | return pin; | |
3865 | } | |
3866 | ||
68feac87 BH |
3867 | /** |
3868 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
3869 | * @dev: the PCI device | |
3870 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
3871 | * | |
3872 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
3873 | * bridges all the way up to a PCI root bus. | |
3874 | */ | |
3875 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
3876 | { | |
3877 | u8 pin = *pinp; | |
3878 | ||
1eb39487 | 3879 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
3880 | pin = pci_swizzle_interrupt_pin(dev, pin); |
3881 | dev = dev->bus->self; | |
3882 | } | |
3883 | *pinp = pin; | |
3884 | return PCI_SLOT(dev->devfn); | |
3885 | } | |
e6b29dea | 3886 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 3887 | |
1da177e4 | 3888 | /** |
74356add BH |
3889 | * pci_release_region - Release a PCI bar |
3890 | * @pdev: PCI device whose resources were previously reserved by | |
3891 | * pci_request_region() | |
3892 | * @bar: BAR to release | |
1da177e4 | 3893 | * |
74356add BH |
3894 | * Releases the PCI I/O and memory resources previously reserved by a |
3895 | * successful call to pci_request_region(). Call this function only | |
3896 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3897 | */ |
3898 | void pci_release_region(struct pci_dev *pdev, int bar) | |
3899 | { | |
9ac7849e TH |
3900 | struct pci_devres *dr; |
3901 | ||
1da177e4 LT |
3902 | if (pci_resource_len(pdev, bar) == 0) |
3903 | return; | |
3904 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
3905 | release_region(pci_resource_start(pdev, bar), | |
3906 | pci_resource_len(pdev, bar)); | |
3907 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
3908 | release_mem_region(pci_resource_start(pdev, bar), | |
3909 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
3910 | |
3911 | dr = find_pci_dr(pdev); | |
3912 | if (dr) | |
3913 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 3914 | } |
b7fe9434 | 3915 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
3916 | |
3917 | /** | |
74356add BH |
3918 | * __pci_request_region - Reserved PCI I/O and memory resource |
3919 | * @pdev: PCI device whose resources are to be reserved | |
3920 | * @bar: BAR to be reserved | |
3921 | * @res_name: Name to be associated with resource. | |
3922 | * @exclusive: whether the region access is exclusive or not | |
1da177e4 | 3923 | * |
74356add BH |
3924 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3925 | * being reserved by owner @res_name. Do not access any | |
3926 | * address inside the PCI regions unless this call returns | |
3927 | * successfully. | |
1da177e4 | 3928 | * |
74356add BH |
3929 | * If @exclusive is set, then the region is marked so that userspace |
3930 | * is explicitly not allowed to map the resource via /dev/mem or | |
3931 | * sysfs MMIO access. | |
f5ddcac4 | 3932 | * |
74356add BH |
3933 | * Returns 0 on success, or %EBUSY on error. A warning |
3934 | * message is also printed on failure. | |
1da177e4 | 3935 | */ |
3c78bc61 RD |
3936 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3937 | const char *res_name, int exclusive) | |
1da177e4 | 3938 | { |
9ac7849e TH |
3939 | struct pci_devres *dr; |
3940 | ||
1da177e4 LT |
3941 | if (pci_resource_len(pdev, bar) == 0) |
3942 | return 0; | |
f7625980 | 3943 | |
1da177e4 LT |
3944 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3945 | if (!request_region(pci_resource_start(pdev, bar), | |
3946 | pci_resource_len(pdev, bar), res_name)) | |
3947 | goto err_out; | |
3c78bc61 | 3948 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3949 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3950 | pci_resource_len(pdev, bar), res_name, | |
3951 | exclusive)) | |
1da177e4 LT |
3952 | goto err_out; |
3953 | } | |
9ac7849e TH |
3954 | |
3955 | dr = find_pci_dr(pdev); | |
3956 | if (dr) | |
3957 | dr->region_mask |= 1 << bar; | |
3958 | ||
1da177e4 LT |
3959 | return 0; |
3960 | ||
3961 | err_out: | |
7506dc79 | 3962 | pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3963 | &pdev->resource[bar]); |
1da177e4 LT |
3964 | return -EBUSY; |
3965 | } | |
3966 | ||
e8de1481 | 3967 | /** |
74356add BH |
3968 | * pci_request_region - Reserve PCI I/O and memory resource |
3969 | * @pdev: PCI device whose resources are to be reserved | |
3970 | * @bar: BAR to be reserved | |
3971 | * @res_name: Name to be associated with resource | |
e8de1481 | 3972 | * |
74356add BH |
3973 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3974 | * being reserved by owner @res_name. Do not access any | |
3975 | * address inside the PCI regions unless this call returns | |
3976 | * successfully. | |
e8de1481 | 3977 | * |
74356add BH |
3978 | * Returns 0 on success, or %EBUSY on error. A warning |
3979 | * message is also printed on failure. | |
e8de1481 AV |
3980 | */ |
3981 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3982 | { | |
3983 | return __pci_request_region(pdev, bar, res_name, 0); | |
3984 | } | |
b7fe9434 | 3985 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 | 3986 | |
c87deff7 HS |
3987 | /** |
3988 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3989 | * @pdev: PCI device whose resources were previously reserved | |
3990 | * @bars: Bitmask of BARs to be released | |
3991 | * | |
3992 | * Release selected PCI I/O and memory resources previously reserved. | |
3993 | * Call this function only after all use of the PCI regions has ceased. | |
3994 | */ | |
3995 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3996 | { | |
3997 | int i; | |
3998 | ||
c9c13ba4 | 3999 | for (i = 0; i < PCI_STD_NUM_BARS; i++) |
c87deff7 HS |
4000 | if (bars & (1 << i)) |
4001 | pci_release_region(pdev, i); | |
4002 | } | |
b7fe9434 | 4003 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 4004 | |
9738abed | 4005 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 4006 | const char *res_name, int excl) |
c87deff7 HS |
4007 | { |
4008 | int i; | |
4009 | ||
c9c13ba4 | 4010 | for (i = 0; i < PCI_STD_NUM_BARS; i++) |
c87deff7 | 4011 | if (bars & (1 << i)) |
e8de1481 | 4012 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
4013 | goto err_out; |
4014 | return 0; | |
4015 | ||
4016 | err_out: | |
3c78bc61 | 4017 | while (--i >= 0) |
c87deff7 HS |
4018 | if (bars & (1 << i)) |
4019 | pci_release_region(pdev, i); | |
4020 | ||
4021 | return -EBUSY; | |
4022 | } | |
1da177e4 | 4023 | |
e8de1481 AV |
4024 | |
4025 | /** | |
4026 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
4027 | * @pdev: PCI device whose resources are to be reserved | |
4028 | * @bars: Bitmask of BARs to be requested | |
4029 | * @res_name: Name to be associated with resource | |
4030 | */ | |
4031 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
4032 | const char *res_name) | |
4033 | { | |
4034 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
4035 | } | |
b7fe9434 | 4036 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 4037 | |
3c78bc61 RD |
4038 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
4039 | const char *res_name) | |
e8de1481 AV |
4040 | { |
4041 | return __pci_request_selected_regions(pdev, bars, res_name, | |
4042 | IORESOURCE_EXCLUSIVE); | |
4043 | } | |
b7fe9434 | 4044 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 4045 | |
1da177e4 | 4046 | /** |
74356add BH |
4047 | * pci_release_regions - Release reserved PCI I/O and memory resources |
4048 | * @pdev: PCI device whose resources were previously reserved by | |
4049 | * pci_request_regions() | |
1da177e4 | 4050 | * |
74356add BH |
4051 | * Releases all PCI I/O and memory resources previously reserved by a |
4052 | * successful call to pci_request_regions(). Call this function only | |
4053 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
4054 | */ |
4055 | ||
4056 | void pci_release_regions(struct pci_dev *pdev) | |
4057 | { | |
c9c13ba4 | 4058 | pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); |
1da177e4 | 4059 | } |
b7fe9434 | 4060 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
4061 | |
4062 | /** | |
74356add BH |
4063 | * pci_request_regions - Reserve PCI I/O and memory resources |
4064 | * @pdev: PCI device whose resources are to be reserved | |
4065 | * @res_name: Name to be associated with resource. | |
1da177e4 | 4066 | * |
74356add BH |
4067 | * Mark all PCI regions associated with PCI device @pdev as |
4068 | * being reserved by owner @res_name. Do not access any | |
4069 | * address inside the PCI regions unless this call returns | |
4070 | * successfully. | |
1da177e4 | 4071 | * |
74356add BH |
4072 | * Returns 0 on success, or %EBUSY on error. A warning |
4073 | * message is also printed on failure. | |
1da177e4 | 4074 | */ |
3c990e92 | 4075 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 4076 | { |
c9c13ba4 DE |
4077 | return pci_request_selected_regions(pdev, |
4078 | ((1 << PCI_STD_NUM_BARS) - 1), res_name); | |
1da177e4 | 4079 | } |
b7fe9434 | 4080 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 4081 | |
e8de1481 | 4082 | /** |
74356add BH |
4083 | * pci_request_regions_exclusive - Reserve PCI I/O and memory resources |
4084 | * @pdev: PCI device whose resources are to be reserved | |
4085 | * @res_name: Name to be associated with resource. | |
e8de1481 | 4086 | * |
74356add BH |
4087 | * Mark all PCI regions associated with PCI device @pdev as being reserved |
4088 | * by owner @res_name. Do not access any address inside the PCI regions | |
4089 | * unless this call returns successfully. | |
e8de1481 | 4090 | * |
74356add BH |
4091 | * pci_request_regions_exclusive() will mark the region so that /dev/mem |
4092 | * and the sysfs MMIO access will not be allowed. | |
e8de1481 | 4093 | * |
74356add BH |
4094 | * Returns 0 on success, or %EBUSY on error. A warning message is also |
4095 | * printed on failure. | |
e8de1481 AV |
4096 | */ |
4097 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
4098 | { | |
4099 | return pci_request_selected_regions_exclusive(pdev, | |
c9c13ba4 | 4100 | ((1 << PCI_STD_NUM_BARS) - 1), res_name); |
e8de1481 | 4101 | } |
b7fe9434 | 4102 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 4103 | |
c5076cfe TN |
4104 | /* |
4105 | * Record the PCI IO range (expressed as CPU physical address + size). | |
74356add | 4106 | * Return a negative value if an error has occurred, zero otherwise |
c5076cfe | 4107 | */ |
fcfaab30 GP |
4108 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
4109 | resource_size_t size) | |
c5076cfe | 4110 | { |
5745392e | 4111 | int ret = 0; |
c5076cfe | 4112 | #ifdef PCI_IOBASE |
5745392e | 4113 | struct logic_pio_hwaddr *range; |
c5076cfe | 4114 | |
5745392e ZY |
4115 | if (!size || addr + size < addr) |
4116 | return -EINVAL; | |
c5076cfe | 4117 | |
c5076cfe | 4118 | range = kzalloc(sizeof(*range), GFP_ATOMIC); |
5745392e ZY |
4119 | if (!range) |
4120 | return -ENOMEM; | |
c5076cfe | 4121 | |
5745392e | 4122 | range->fwnode = fwnode; |
c5076cfe | 4123 | range->size = size; |
5745392e ZY |
4124 | range->hw_start = addr; |
4125 | range->flags = LOGIC_PIO_CPU_MMIO; | |
c5076cfe | 4126 | |
5745392e ZY |
4127 | ret = logic_pio_register_range(range); |
4128 | if (ret) | |
4129 | kfree(range); | |
f6bda644 GU |
4130 | |
4131 | /* Ignore duplicates due to deferred probing */ | |
4132 | if (ret == -EEXIST) | |
4133 | ret = 0; | |
c5076cfe TN |
4134 | #endif |
4135 | ||
5745392e | 4136 | return ret; |
c5076cfe TN |
4137 | } |
4138 | ||
4139 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
4140 | { | |
4141 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
4142 | ||
4143 | #ifdef PCI_IOBASE | |
5745392e | 4144 | if (pio >= MMIO_UPPER_LIMIT) |
c5076cfe TN |
4145 | return address; |
4146 | ||
5745392e | 4147 | address = logic_pio_to_hwaddr(pio); |
c5076cfe TN |
4148 | #endif |
4149 | ||
4150 | return address; | |
4151 | } | |
9cc74207 | 4152 | EXPORT_SYMBOL_GPL(pci_pio_to_address); |
c5076cfe TN |
4153 | |
4154 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
4155 | { | |
4156 | #ifdef PCI_IOBASE | |
5745392e | 4157 | return logic_pio_trans_cpuaddr(address); |
c5076cfe TN |
4158 | #else |
4159 | if (address > IO_SPACE_LIMIT) | |
4160 | return (unsigned long)-1; | |
4161 | ||
4162 | return (unsigned long) address; | |
4163 | #endif | |
4164 | } | |
4165 | ||
8b921acf | 4166 | /** |
74356add BH |
4167 | * pci_remap_iospace - Remap the memory mapped I/O space |
4168 | * @res: Resource describing the I/O space | |
4169 | * @phys_addr: physical address of range to be mapped | |
8b921acf | 4170 | * |
74356add BH |
4171 | * Remap the memory mapped I/O space described by the @res and the CPU |
4172 | * physical address @phys_addr into virtual address space. Only | |
4173 | * architectures that have memory mapped IO functions defined (and the | |
4174 | * PCI_IOBASE value defined) should call this function. | |
8b921acf | 4175 | */ |
7b309aef | 4176 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) |
8b921acf LD |
4177 | { |
4178 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
4179 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
4180 | ||
4181 | if (!(res->flags & IORESOURCE_IO)) | |
4182 | return -EINVAL; | |
4183 | ||
4184 | if (res->end > IO_SPACE_LIMIT) | |
4185 | return -EINVAL; | |
4186 | ||
4187 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
4188 | pgprot_device(PAGE_KERNEL)); | |
4189 | #else | |
74356add BH |
4190 | /* |
4191 | * This architecture does not have memory mapped I/O space, | |
4192 | * so this function should never be called | |
4193 | */ | |
8b921acf LD |
4194 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); |
4195 | return -ENODEV; | |
4196 | #endif | |
4197 | } | |
f90b0875 | 4198 | EXPORT_SYMBOL(pci_remap_iospace); |
8b921acf | 4199 | |
4d3f1384 | 4200 | /** |
74356add BH |
4201 | * pci_unmap_iospace - Unmap the memory mapped I/O space |
4202 | * @res: resource to be unmapped | |
4d3f1384 | 4203 | * |
74356add BH |
4204 | * Unmap the CPU virtual address @res from virtual address space. Only |
4205 | * architectures that have memory mapped IO functions defined (and the | |
4206 | * PCI_IOBASE value defined) should call this function. | |
4d3f1384 SK |
4207 | */ |
4208 | void pci_unmap_iospace(struct resource *res) | |
4209 | { | |
4210 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
4211 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
4212 | ||
4ad0ae8c | 4213 | vunmap_range(vaddr, vaddr + resource_size(res)); |
4d3f1384 SK |
4214 | #endif |
4215 | } | |
f90b0875 | 4216 | EXPORT_SYMBOL(pci_unmap_iospace); |
4d3f1384 | 4217 | |
a5fb9fb0 SS |
4218 | static void devm_pci_unmap_iospace(struct device *dev, void *ptr) |
4219 | { | |
4220 | struct resource **res = ptr; | |
4221 | ||
4222 | pci_unmap_iospace(*res); | |
4223 | } | |
4224 | ||
4225 | /** | |
4226 | * devm_pci_remap_iospace - Managed pci_remap_iospace() | |
4227 | * @dev: Generic device to remap IO address for | |
4228 | * @res: Resource describing the I/O space | |
4229 | * @phys_addr: physical address of range to be mapped | |
4230 | * | |
4231 | * Managed pci_remap_iospace(). Map is automatically unmapped on driver | |
4232 | * detach. | |
4233 | */ | |
4234 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, | |
4235 | phys_addr_t phys_addr) | |
4236 | { | |
4237 | const struct resource **ptr; | |
4238 | int error; | |
4239 | ||
4240 | ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL); | |
4241 | if (!ptr) | |
4242 | return -ENOMEM; | |
4243 | ||
4244 | error = pci_remap_iospace(res, phys_addr); | |
4245 | if (error) { | |
4246 | devres_free(ptr); | |
4247 | } else { | |
4248 | *ptr = res; | |
4249 | devres_add(dev, ptr); | |
4250 | } | |
4251 | ||
4252 | return error; | |
4253 | } | |
4254 | EXPORT_SYMBOL(devm_pci_remap_iospace); | |
4255 | ||
490cb6dd LP |
4256 | /** |
4257 | * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace() | |
4258 | * @dev: Generic device to remap IO address for | |
4259 | * @offset: Resource address to map | |
4260 | * @size: Size of map | |
4261 | * | |
4262 | * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver | |
4263 | * detach. | |
4264 | */ | |
4265 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, | |
4266 | resource_size_t offset, | |
4267 | resource_size_t size) | |
4268 | { | |
4269 | void __iomem **ptr, *addr; | |
4270 | ||
4271 | ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); | |
4272 | if (!ptr) | |
4273 | return NULL; | |
4274 | ||
4275 | addr = pci_remap_cfgspace(offset, size); | |
4276 | if (addr) { | |
4277 | *ptr = addr; | |
4278 | devres_add(dev, ptr); | |
4279 | } else | |
4280 | devres_free(ptr); | |
4281 | ||
4282 | return addr; | |
4283 | } | |
4284 | EXPORT_SYMBOL(devm_pci_remap_cfgspace); | |
4285 | ||
4286 | /** | |
4287 | * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource | |
4288 | * @dev: generic device to handle the resource for | |
4289 | * @res: configuration space resource to be handled | |
4290 | * | |
4291 | * Checks that a resource is a valid memory region, requests the memory | |
4292 | * region and ioremaps with pci_remap_cfgspace() API that ensures the | |
4293 | * proper PCI configuration space memory attributes are guaranteed. | |
4294 | * | |
4295 | * All operations are managed and will be undone on driver detach. | |
4296 | * | |
4297 | * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code | |
505fb746 | 4298 | * on failure. Usage example:: |
490cb6dd LP |
4299 | * |
4300 | * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
4301 | * base = devm_pci_remap_cfg_resource(&pdev->dev, res); | |
4302 | * if (IS_ERR(base)) | |
4303 | * return PTR_ERR(base); | |
4304 | */ | |
4305 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
4306 | struct resource *res) | |
4307 | { | |
4308 | resource_size_t size; | |
4309 | const char *name; | |
4310 | void __iomem *dest_ptr; | |
4311 | ||
4312 | BUG_ON(!dev); | |
4313 | ||
4314 | if (!res || resource_type(res) != IORESOURCE_MEM) { | |
4315 | dev_err(dev, "invalid resource\n"); | |
4316 | return IOMEM_ERR_PTR(-EINVAL); | |
4317 | } | |
4318 | ||
4319 | size = resource_size(res); | |
0af6e21e AL |
4320 | |
4321 | if (res->name) | |
4322 | name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev), | |
4323 | res->name); | |
4324 | else | |
4325 | name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); | |
4326 | if (!name) | |
4327 | return IOMEM_ERR_PTR(-ENOMEM); | |
490cb6dd LP |
4328 | |
4329 | if (!devm_request_mem_region(dev, res->start, size, name)) { | |
4330 | dev_err(dev, "can't request region for resource %pR\n", res); | |
4331 | return IOMEM_ERR_PTR(-EBUSY); | |
4332 | } | |
4333 | ||
4334 | dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); | |
4335 | if (!dest_ptr) { | |
4336 | dev_err(dev, "ioremap failed for resource %pR\n", res); | |
4337 | devm_release_mem_region(dev, res->start, size); | |
4338 | dest_ptr = IOMEM_ERR_PTR(-ENOMEM); | |
4339 | } | |
4340 | ||
4341 | return dest_ptr; | |
4342 | } | |
4343 | EXPORT_SYMBOL(devm_pci_remap_cfg_resource); | |
4344 | ||
6a479079 BH |
4345 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
4346 | { | |
4347 | u16 old_cmd, cmd; | |
4348 | ||
4349 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
4350 | if (enable) | |
4351 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
4352 | else | |
4353 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
4354 | if (cmd != old_cmd) { | |
7506dc79 | 4355 | pci_dbg(dev, "%s bus mastering\n", |
6a479079 BH |
4356 | enable ? "enabling" : "disabling"); |
4357 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4358 | } | |
4359 | dev->is_busmaster = enable; | |
4360 | } | |
e8de1481 | 4361 | |
2b6f2c35 MS |
4362 | /** |
4363 | * pcibios_setup - process "pci=" kernel boot arguments | |
4364 | * @str: string used to pass in "pci=" kernel boot arguments | |
4365 | * | |
4366 | * Process kernel boot arguments. This is the default implementation. | |
4367 | * Architecture specific implementations can override this as necessary. | |
4368 | */ | |
4369 | char * __weak __init pcibios_setup(char *str) | |
4370 | { | |
4371 | return str; | |
4372 | } | |
4373 | ||
96c55900 MS |
4374 | /** |
4375 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
4376 | * @dev: the PCI device to enable | |
4377 | * | |
4378 | * Enables PCI bus-mastering for the device. This is the default | |
4379 | * implementation. Architecture specific implementations can override | |
4380 | * this if necessary. | |
4381 | */ | |
4382 | void __weak pcibios_set_master(struct pci_dev *dev) | |
4383 | { | |
4384 | u8 lat; | |
4385 | ||
f676678f MS |
4386 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
4387 | if (pci_is_pcie(dev)) | |
4388 | return; | |
4389 | ||
96c55900 MS |
4390 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
4391 | if (lat < 16) | |
4392 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
4393 | else if (lat > pcibios_max_latency) | |
4394 | lat = pcibios_max_latency; | |
4395 | else | |
4396 | return; | |
a006482b | 4397 | |
96c55900 MS |
4398 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
4399 | } | |
4400 | ||
1da177e4 LT |
4401 | /** |
4402 | * pci_set_master - enables bus-mastering for device dev | |
4403 | * @dev: the PCI device to enable | |
4404 | * | |
4405 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
4406 | * to do the needed arch specific settings. | |
4407 | */ | |
6a479079 | 4408 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 4409 | { |
6a479079 | 4410 | __pci_set_master(dev, true); |
1da177e4 LT |
4411 | pcibios_set_master(dev); |
4412 | } | |
b7fe9434 | 4413 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 4414 | |
6a479079 BH |
4415 | /** |
4416 | * pci_clear_master - disables bus-mastering for device dev | |
4417 | * @dev: the PCI device to disable | |
4418 | */ | |
4419 | void pci_clear_master(struct pci_dev *dev) | |
4420 | { | |
4421 | __pci_set_master(dev, false); | |
4422 | } | |
b7fe9434 | 4423 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 4424 | |
1da177e4 | 4425 | /** |
edb2d97e MW |
4426 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
4427 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 4428 | * |
edb2d97e MW |
4429 | * Helper function for pci_set_mwi. |
4430 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
4431 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
4432 | * | |
4433 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4434 | */ | |
15ea76d4 | 4435 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
4436 | { |
4437 | u8 cacheline_size; | |
4438 | ||
4439 | if (!pci_cache_line_size) | |
15ea76d4 | 4440 | return -EINVAL; |
1da177e4 LT |
4441 | |
4442 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
4443 | equal to or multiple of the right value. */ | |
4444 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4445 | if (cacheline_size >= pci_cache_line_size && | |
4446 | (cacheline_size % pci_cache_line_size) == 0) | |
4447 | return 0; | |
4448 | ||
4449 | /* Write the correct value. */ | |
4450 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
4451 | /* Read it back. */ | |
4452 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4453 | if (cacheline_size == pci_cache_line_size) | |
4454 | return 0; | |
4455 | ||
0aec75a5 | 4456 | pci_dbg(dev, "cache line size of %d is not supported\n", |
227f0647 | 4457 | pci_cache_line_size << 2); |
1da177e4 LT |
4458 | |
4459 | return -EINVAL; | |
4460 | } | |
15ea76d4 TH |
4461 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
4462 | ||
1da177e4 LT |
4463 | /** |
4464 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
4465 | * @dev: the PCI device for which MWI is enabled | |
4466 | * | |
694625c0 | 4467 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
4468 | * |
4469 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4470 | */ | |
3c78bc61 | 4471 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 4472 | { |
b7fe9434 RD |
4473 | #ifdef PCI_DISABLE_MWI |
4474 | return 0; | |
4475 | #else | |
1da177e4 LT |
4476 | int rc; |
4477 | u16 cmd; | |
4478 | ||
edb2d97e | 4479 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
4480 | if (rc) |
4481 | return rc; | |
4482 | ||
4483 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 4484 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
7506dc79 | 4485 | pci_dbg(dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
4486 | cmd |= PCI_COMMAND_INVALIDATE; |
4487 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4488 | } | |
1da177e4 | 4489 | return 0; |
b7fe9434 | 4490 | #endif |
1da177e4 | 4491 | } |
b7fe9434 | 4492 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 4493 | |
fc0f9f4d HK |
4494 | /** |
4495 | * pcim_set_mwi - a device-managed pci_set_mwi() | |
4496 | * @dev: the PCI device for which MWI is enabled | |
4497 | * | |
4498 | * Managed pci_set_mwi(). | |
4499 | * | |
4500 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4501 | */ | |
4502 | int pcim_set_mwi(struct pci_dev *dev) | |
4503 | { | |
4504 | struct pci_devres *dr; | |
4505 | ||
4506 | dr = find_pci_dr(dev); | |
4507 | if (!dr) | |
4508 | return -ENOMEM; | |
4509 | ||
4510 | dr->mwi = 1; | |
4511 | return pci_set_mwi(dev); | |
4512 | } | |
4513 | EXPORT_SYMBOL(pcim_set_mwi); | |
4514 | ||
694625c0 RD |
4515 | /** |
4516 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
4517 | * @dev: the PCI device for which MWI is enabled | |
4518 | * | |
4519 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
4520 | * Callers are not required to check the return value. | |
4521 | * | |
4522 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4523 | */ | |
4524 | int pci_try_set_mwi(struct pci_dev *dev) | |
4525 | { | |
b7fe9434 RD |
4526 | #ifdef PCI_DISABLE_MWI |
4527 | return 0; | |
4528 | #else | |
4529 | return pci_set_mwi(dev); | |
4530 | #endif | |
694625c0 | 4531 | } |
b7fe9434 | 4532 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 4533 | |
1da177e4 LT |
4534 | /** |
4535 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
4536 | * @dev: the PCI device to disable | |
4537 | * | |
4538 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
4539 | */ | |
3c78bc61 | 4540 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 4541 | { |
b7fe9434 | 4542 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
4543 | u16 cmd; |
4544 | ||
4545 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4546 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
4547 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
4548 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4549 | } | |
b7fe9434 | 4550 | #endif |
1da177e4 | 4551 | } |
b7fe9434 | 4552 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 4553 | |
1fd3dde5 BH |
4554 | /** |
4555 | * pci_disable_parity - disable parity checking for device | |
4556 | * @dev: the PCI device to operate on | |
4557 | * | |
4558 | * Disable parity checking for device @dev | |
4559 | */ | |
4560 | void pci_disable_parity(struct pci_dev *dev) | |
4561 | { | |
4562 | u16 cmd; | |
4563 | ||
4564 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4565 | if (cmd & PCI_COMMAND_PARITY) { | |
4566 | cmd &= ~PCI_COMMAND_PARITY; | |
4567 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4568 | } | |
4569 | } | |
4570 | ||
a04ce0ff BR |
4571 | /** |
4572 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
4573 | * @pdev: the PCI device to operate on |
4574 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff | 4575 | * |
74356add | 4576 | * Enables/disables PCI INTx for device @pdev |
a04ce0ff | 4577 | */ |
3c78bc61 | 4578 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
4579 | { |
4580 | u16 pci_command, new; | |
4581 | ||
4582 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
4583 | ||
3c78bc61 | 4584 | if (enable) |
a04ce0ff | 4585 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 4586 | else |
a04ce0ff | 4587 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
4588 | |
4589 | if (new != pci_command) { | |
9ac7849e TH |
4590 | struct pci_devres *dr; |
4591 | ||
2fd9d74b | 4592 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
4593 | |
4594 | dr = find_pci_dr(pdev); | |
4595 | if (dr && !dr->restore_intx) { | |
4596 | dr->restore_intx = 1; | |
4597 | dr->orig_intx = !enable; | |
4598 | } | |
a04ce0ff BR |
4599 | } |
4600 | } | |
b7fe9434 | 4601 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 4602 | |
a2e27787 JK |
4603 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) |
4604 | { | |
4605 | struct pci_bus *bus = dev->bus; | |
4606 | bool mask_updated = true; | |
4607 | u32 cmd_status_dword; | |
4608 | u16 origcmd, newcmd; | |
4609 | unsigned long flags; | |
4610 | bool irq_pending; | |
4611 | ||
4612 | /* | |
4613 | * We do a single dword read to retrieve both command and status. | |
4614 | * Document assumptions that make this possible. | |
4615 | */ | |
4616 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
4617 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
4618 | ||
4619 | raw_spin_lock_irqsave(&pci_lock, flags); | |
4620 | ||
4621 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
4622 | ||
4623 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
4624 | ||
4625 | /* | |
4626 | * Check interrupt status register to see whether our device | |
4627 | * triggered the interrupt (when masking) or the next IRQ is | |
4628 | * already pending (when unmasking). | |
4629 | */ | |
4630 | if (mask != irq_pending) { | |
4631 | mask_updated = false; | |
4632 | goto done; | |
4633 | } | |
4634 | ||
4635 | origcmd = cmd_status_dword; | |
4636 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
4637 | if (mask) | |
4638 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
4639 | if (newcmd != origcmd) | |
4640 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
4641 | ||
4642 | done: | |
4643 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
4644 | ||
4645 | return mask_updated; | |
4646 | } | |
4647 | ||
4648 | /** | |
4649 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 4650 | * @dev: the PCI device to operate on |
a2e27787 | 4651 | * |
74356add BH |
4652 | * Check if the device dev has its INTx line asserted, mask it and return |
4653 | * true in that case. False is returned if no interrupt was pending. | |
a2e27787 JK |
4654 | */ |
4655 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
4656 | { | |
4657 | return pci_check_and_set_intx_mask(dev, true); | |
4658 | } | |
4659 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
4660 | ||
4661 | /** | |
ebd50b93 | 4662 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 4663 | * @dev: the PCI device to operate on |
a2e27787 | 4664 | * |
74356add BH |
4665 | * Check if the device dev has its INTx line asserted, unmask it if not and |
4666 | * return true. False is returned and the mask remains active if there was | |
4667 | * still an interrupt pending. | |
a2e27787 JK |
4668 | */ |
4669 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
4670 | { | |
4671 | return pci_check_and_set_intx_mask(dev, false); | |
4672 | } | |
4673 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
4674 | ||
3775a209 | 4675 | /** |
74356add | 4676 | * pci_wait_for_pending_transaction - wait for pending transaction |
3775a209 CL |
4677 | * @dev: the PCI device to operate on |
4678 | * | |
4679 | * Return 0 if transaction is pending 1 otherwise. | |
4680 | */ | |
4681 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 4682 | { |
157e876f AW |
4683 | if (!pci_is_pcie(dev)) |
4684 | return 1; | |
8c1c699f | 4685 | |
d0b4cc4e GS |
4686 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
4687 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
4688 | } |
4689 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
4690 | ||
a60a2b73 CH |
4691 | /** |
4692 | * pcie_flr - initiate a PCIe function level reset | |
74356add | 4693 | * @dev: device to reset |
a60a2b73 | 4694 | * |
56f107d7 AN |
4695 | * Initiate a function level reset unconditionally on @dev without |
4696 | * checking any flags and DEVCAP | |
a60a2b73 | 4697 | */ |
91295d79 | 4698 | int pcie_flr(struct pci_dev *dev) |
a60a2b73 | 4699 | { |
3775a209 | 4700 | if (!pci_wait_for_pending_transaction(dev)) |
7506dc79 | 4701 | pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 4702 | |
59875ae4 | 4703 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
a2758b6b | 4704 | |
d6112f8d FB |
4705 | if (dev->imm_ready) |
4706 | return 0; | |
4707 | ||
a2758b6b SK |
4708 | /* |
4709 | * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within | |
4710 | * 100ms, but may silently discard requests while the FLR is in | |
4711 | * progress. Wait 100ms before trying to access the device. | |
4712 | */ | |
4713 | msleep(100); | |
4714 | ||
4715 | return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); | |
8dd7f803 | 4716 | } |
a60a2b73 | 4717 | EXPORT_SYMBOL_GPL(pcie_flr); |
d91cdc74 | 4718 | |
56f107d7 AN |
4719 | /** |
4720 | * pcie_reset_flr - initiate a PCIe function level reset | |
4721 | * @dev: device to reset | |
9bdc81ce | 4722 | * @probe: if true, return 0 if device can be reset this way |
56f107d7 AN |
4723 | * |
4724 | * Initiate a function level reset on @dev. | |
4725 | */ | |
9bdc81ce | 4726 | int pcie_reset_flr(struct pci_dev *dev, bool probe) |
56f107d7 AN |
4727 | { |
4728 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) | |
4729 | return -ENOTTY; | |
4730 | ||
4731 | if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) | |
4732 | return -ENOTTY; | |
4733 | ||
4734 | if (probe) | |
4735 | return 0; | |
4736 | ||
4737 | return pcie_flr(dev); | |
4738 | } | |
4739 | EXPORT_SYMBOL_GPL(pcie_reset_flr); | |
4740 | ||
9bdc81ce | 4741 | static int pci_af_flr(struct pci_dev *dev, bool probe) |
1ca88797 | 4742 | { |
8c1c699f | 4743 | int pos; |
1ca88797 SY |
4744 | u8 cap; |
4745 | ||
8c1c699f YZ |
4746 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
4747 | if (!pos) | |
1ca88797 | 4748 | return -ENOTTY; |
8c1c699f | 4749 | |
f65fd1aa SN |
4750 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
4751 | return -ENOTTY; | |
4752 | ||
8c1c699f | 4753 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); |
1ca88797 SY |
4754 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
4755 | return -ENOTTY; | |
4756 | ||
4757 | if (probe) | |
4758 | return 0; | |
4759 | ||
d066c946 AW |
4760 | /* |
4761 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
f6b6aefe | 4762 | * is used, so we use the control offset rather than status and shift |
d066c946 AW |
4763 | * the test bit to match. |
4764 | */ | |
bb383e28 | 4765 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 4766 | PCI_AF_STATUS_TP << 8)) |
7506dc79 | 4767 | pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 4768 | |
8c1c699f | 4769 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
a2758b6b | 4770 | |
d6112f8d FB |
4771 | if (dev->imm_ready) |
4772 | return 0; | |
4773 | ||
a2758b6b SK |
4774 | /* |
4775 | * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, | |
4776 | * updated 27 July 2006; a device must complete an FLR within | |
4777 | * 100ms, but may silently discard requests while the FLR is in | |
4778 | * progress. Wait 100ms before trying to access the device. | |
4779 | */ | |
4780 | msleep(100); | |
4781 | ||
4782 | return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); | |
1ca88797 SY |
4783 | } |
4784 | ||
83d74e03 RW |
4785 | /** |
4786 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
4787 | * @dev: Device to reset. | |
9bdc81ce | 4788 | * @probe: if true, return 0 if the device can be reset this way. |
83d74e03 RW |
4789 | * |
4790 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
4791 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
4792 | * PCI_D0. If that's the case and the device is not in a low-power state | |
4793 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
4794 | * | |
4795 | * NOTE: This causes the caller to sleep for twice the device power transition | |
4796 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
3789af9a | 4797 | * by default (i.e. unless the @dev's d3hot_delay field has a different value). |
83d74e03 RW |
4798 | * Moreover, only devices in D0 can be reset by this function. |
4799 | */ | |
9bdc81ce | 4800 | static int pci_pm_reset(struct pci_dev *dev, bool probe) |
d91cdc74 | 4801 | { |
f85876ba YZ |
4802 | u16 csr; |
4803 | ||
51e53738 | 4804 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 4805 | return -ENOTTY; |
d91cdc74 | 4806 | |
f85876ba YZ |
4807 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
4808 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
4809 | return -ENOTTY; | |
d91cdc74 | 4810 | |
f85876ba YZ |
4811 | if (probe) |
4812 | return 0; | |
1ca88797 | 4813 | |
f85876ba YZ |
4814 | if (dev->current_state != PCI_D0) |
4815 | return -EINVAL; | |
4816 | ||
4817 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4818 | csr |= PCI_D3hot; | |
4819 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4820 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
4821 | |
4822 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4823 | csr |= PCI_D0; | |
4824 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4825 | pci_dev_d3_sleep(dev); |
f85876ba | 4826 | |
993cc6d1 | 4827 | return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); |
f85876ba | 4828 | } |
4827d638 | 4829 | |
9f5a70f1 | 4830 | /** |
4827d638 | 4831 | * pcie_wait_for_link_delay - Wait until link is active or inactive |
9f5a70f1 OP |
4832 | * @pdev: Bridge device |
4833 | * @active: waiting for active or inactive? | |
d08c30d7 | 4834 | * @delay: Delay to wait after link has become active (in ms) |
9f5a70f1 OP |
4835 | * |
4836 | * Use this to wait till link becomes active or inactive. | |
4837 | */ | |
4827d638 MW |
4838 | static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, |
4839 | int delay) | |
9f5a70f1 OP |
4840 | { |
4841 | int timeout = 1000; | |
4842 | bool ret; | |
4843 | u16 lnk_status; | |
4844 | ||
f0157160 KB |
4845 | /* |
4846 | * Some controllers might not implement link active reporting. In this | |
f044baaf | 4847 | * case, we wait for 1000 ms + any delay requested by the caller. |
f0157160 KB |
4848 | */ |
4849 | if (!pdev->link_active_reporting) { | |
f044baaf | 4850 | msleep(timeout + delay); |
f0157160 KB |
4851 | return true; |
4852 | } | |
4853 | ||
4854 | /* | |
4855 | * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, | |
4856 | * after which we should expect an link active if the reset was | |
4857 | * successful. If so, software must wait a minimum 100ms before sending | |
4858 | * configuration requests to devices downstream this port. | |
4859 | * | |
4860 | * If the link fails to activate, either the device was physically | |
4861 | * removed or the link is permanently failed. | |
4862 | */ | |
4863 | if (active) | |
4864 | msleep(20); | |
9f5a70f1 OP |
4865 | for (;;) { |
4866 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); | |
4867 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | |
4868 | if (ret == active) | |
f0157160 | 4869 | break; |
9f5a70f1 OP |
4870 | if (timeout <= 0) |
4871 | break; | |
4872 | msleep(10); | |
4873 | timeout -= 10; | |
4874 | } | |
d08c30d7 | 4875 | if (active && ret) |
4827d638 | 4876 | msleep(delay); |
8a614499 | 4877 | |
f0157160 | 4878 | return ret == active; |
9f5a70f1 | 4879 | } |
f85876ba | 4880 | |
4827d638 MW |
4881 | /** |
4882 | * pcie_wait_for_link - Wait until link is active or inactive | |
4883 | * @pdev: Bridge device | |
4884 | * @active: waiting for active or inactive? | |
4885 | * | |
4886 | * Use this to wait till link becomes active or inactive. | |
4887 | */ | |
4888 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active) | |
4889 | { | |
4890 | return pcie_wait_for_link_delay(pdev, active, 100); | |
4891 | } | |
4892 | ||
ad9001f2 MW |
4893 | /* |
4894 | * Find maximum D3cold delay required by all the devices on the bus. The | |
4895 | * spec says 100 ms, but firmware can lower it and we allow drivers to | |
4896 | * increase it as well. | |
4897 | * | |
4898 | * Called with @pci_bus_sem locked for reading. | |
4899 | */ | |
4900 | static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) | |
4901 | { | |
4902 | const struct pci_dev *pdev; | |
4903 | int min_delay = 100; | |
4904 | int max_delay = 0; | |
4905 | ||
4906 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
4907 | if (pdev->d3cold_delay < min_delay) | |
4908 | min_delay = pdev->d3cold_delay; | |
4909 | if (pdev->d3cold_delay > max_delay) | |
4910 | max_delay = pdev->d3cold_delay; | |
4911 | } | |
4912 | ||
4913 | return max(min_delay, max_delay); | |
4914 | } | |
4915 | ||
4916 | /** | |
4917 | * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible | |
4918 | * @dev: PCI bridge | |
4919 | * | |
4920 | * Handle necessary delays before access to the devices on the secondary | |
4921 | * side of the bridge are permitted after D3cold to D0 transition. | |
4922 | * | |
4923 | * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For | |
4924 | * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section | |
4925 | * 4.3.2. | |
4926 | */ | |
4927 | void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) | |
4928 | { | |
4929 | struct pci_dev *child; | |
4930 | int delay; | |
4931 | ||
4932 | if (pci_dev_is_disconnected(dev)) | |
4933 | return; | |
4934 | ||
4935 | if (!pci_is_bridge(dev) || !dev->bridge_d3) | |
4936 | return; | |
4937 | ||
4938 | down_read(&pci_bus_sem); | |
4939 | ||
4940 | /* | |
4941 | * We only deal with devices that are present currently on the bus. | |
4942 | * For any hot-added devices the access delay is handled in pciehp | |
4943 | * board_added(). In case of ACPI hotplug the firmware is expected | |
4944 | * to configure the devices before OS is notified. | |
4945 | */ | |
4946 | if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { | |
4947 | up_read(&pci_bus_sem); | |
4948 | return; | |
4949 | } | |
4950 | ||
4951 | /* Take d3cold_delay requirements into account */ | |
4952 | delay = pci_bus_max_d3cold_delay(dev->subordinate); | |
4953 | if (!delay) { | |
4954 | up_read(&pci_bus_sem); | |
4955 | return; | |
4956 | } | |
4957 | ||
4958 | child = list_first_entry(&dev->subordinate->devices, struct pci_dev, | |
4959 | bus_list); | |
4960 | up_read(&pci_bus_sem); | |
4961 | ||
4962 | /* | |
4963 | * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before | |
4964 | * accessing the device after reset (that is 1000 ms + 100 ms). In | |
4965 | * practice this should not be needed because we don't do power | |
4966 | * management for them (see pci_bridge_d3_possible()). | |
4967 | */ | |
4968 | if (!pci_is_pcie(dev)) { | |
4969 | pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay); | |
4970 | msleep(1000 + delay); | |
4971 | return; | |
4972 | } | |
4973 | ||
4974 | /* | |
4975 | * For PCIe downstream and root ports that do not support speeds | |
4976 | * greater than 5 GT/s need to wait minimum 100 ms. For higher | |
4977 | * speeds (gen3) we need to wait first for the data link layer to | |
4978 | * become active. | |
4979 | * | |
4980 | * However, 100 ms is the minimum and the PCIe spec says the | |
4981 | * software must allow at least 1s before it can determine that the | |
4982 | * device that did not respond is a broken device. There is | |
4983 | * evidence that 100 ms is not always enough, for example certain | |
4984 | * Titan Ridge xHCI controller does not always respond to | |
4985 | * configuration requests if we only wait for 100 ms (see | |
4986 | * https://bugzilla.kernel.org/show_bug.cgi?id=203885). | |
4987 | * | |
4988 | * Therefore we wait for 100 ms and check for the device presence. | |
4989 | * If it is still not present give it an additional 100 ms. | |
4990 | */ | |
4991 | if (!pcie_downstream_port(dev)) | |
4992 | return; | |
4993 | ||
d08c30d7 BH |
4994 | if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) { |
4995 | pci_dbg(dev, "waiting %d ms for downstream link\n", delay); | |
4996 | msleep(delay); | |
4997 | } else { | |
4998 | pci_dbg(dev, "waiting %d ms for downstream link, after activation\n", | |
4999 | delay); | |
5000 | if (!pcie_wait_for_link_delay(dev, true, delay)) { | |
ad9001f2 | 5001 | /* Did not train, no need to wait any further */ |
8a614499 | 5002 | pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n"); |
ad9001f2 MW |
5003 | return; |
5004 | } | |
5005 | } | |
5006 | ||
5007 | if (!pci_device_is_present(child)) { | |
5008 | pci_dbg(child, "waiting additional %d ms to become accessible\n", delay); | |
5009 | msleep(delay); | |
5010 | } | |
5011 | } | |
5012 | ||
9e33002f | 5013 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
5014 | { |
5015 | u16 ctrl; | |
64e8674f AW |
5016 | |
5017 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
5018 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
5019 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
df62ab5e | 5020 | |
de0c548c AW |
5021 | /* |
5022 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 5023 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
5024 | */ |
5025 | msleep(2); | |
64e8674f AW |
5026 | |
5027 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
5028 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
5029 | |
5030 | /* | |
5031 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
5032 | * Assuming a minimum 33MHz clock this results in a 1s | |
5033 | * delay before we can consider subordinate devices to | |
5034 | * be re-initialized. PCIe has some ways to shorten this, | |
5035 | * but we don't make use of them yet. | |
5036 | */ | |
5037 | ssleep(1); | |
64e8674f | 5038 | } |
d92a208d | 5039 | |
9e33002f GS |
5040 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
5041 | { | |
5042 | pci_reset_secondary_bus(dev); | |
5043 | } | |
5044 | ||
d92a208d | 5045 | /** |
381634ca | 5046 | * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge. |
d92a208d GS |
5047 | * @dev: Bridge device |
5048 | * | |
5049 | * Use the bridge control register to assert reset on the secondary bus. | |
5050 | * Devices on the secondary bus are left in power-on state. | |
5051 | */ | |
381634ca | 5052 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev) |
d92a208d GS |
5053 | { |
5054 | pcibios_reset_secondary_bus(dev); | |
01fd61c0 | 5055 | |
6b2f1351 | 5056 | return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); |
d92a208d | 5057 | } |
bfc45606 | 5058 | EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); |
64e8674f | 5059 | |
9bdc81ce | 5060 | static int pci_parent_bus_reset(struct pci_dev *dev, bool probe) |
64e8674f | 5061 | { |
c12ff1df YZ |
5062 | struct pci_dev *pdev; |
5063 | ||
f331a859 AW |
5064 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
5065 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
5066 | return -ENOTTY; |
5067 | ||
5068 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
5069 | if (pdev != dev) | |
5070 | return -ENOTTY; | |
5071 | ||
5072 | if (probe) | |
5073 | return 0; | |
5074 | ||
381634ca | 5075 | return pci_bridge_secondary_bus_reset(dev->bus->self); |
c12ff1df YZ |
5076 | } |
5077 | ||
9bdc81ce | 5078 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe) |
608c3881 AW |
5079 | { |
5080 | int rc = -ENOTTY; | |
5081 | ||
81c4b5bf | 5082 | if (!hotplug || !try_module_get(hotplug->owner)) |
608c3881 AW |
5083 | return rc; |
5084 | ||
5085 | if (hotplug->ops->reset_slot) | |
5086 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
5087 | ||
81c4b5bf | 5088 | module_put(hotplug->owner); |
608c3881 AW |
5089 | |
5090 | return rc; | |
5091 | } | |
5092 | ||
9bdc81ce | 5093 | static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe) |
608c3881 | 5094 | { |
10791141 | 5095 | if (dev->multifunction || dev->subordinate || !dev->slot || |
f331a859 | 5096 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) |
608c3881 AW |
5097 | return -ENOTTY; |
5098 | ||
608c3881 AW |
5099 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); |
5100 | } | |
5101 | ||
9bdc81ce | 5102 | static int pci_reset_bus_function(struct pci_dev *dev, bool probe) |
0dad3ce5 RN |
5103 | { |
5104 | int rc; | |
5105 | ||
5106 | rc = pci_dev_reset_slot_function(dev, probe); | |
5107 | if (rc != -ENOTTY) | |
5108 | return rc; | |
5109 | return pci_parent_bus_reset(dev, probe); | |
5110 | } | |
5111 | ||
d8d4c54b | 5112 | void pci_dev_lock(struct pci_dev *dev) |
77cb985a | 5113 | { |
77cb985a AW |
5114 | /* block PM suspend, driver probe, etc. */ |
5115 | device_lock(&dev->dev); | |
be077922 | 5116 | pci_cfg_access_lock(dev); |
77cb985a | 5117 | } |
d8d4c54b | 5118 | EXPORT_SYMBOL_GPL(pci_dev_lock); |
77cb985a | 5119 | |
61cf16d8 | 5120 | /* Return 1 on successful lock, 0 on contention */ |
e3a9b121 | 5121 | int pci_dev_trylock(struct pci_dev *dev) |
61cf16d8 | 5122 | { |
be077922 YY |
5123 | if (device_trylock(&dev->dev)) { |
5124 | if (pci_cfg_access_trylock(dev)) | |
61cf16d8 | 5125 | return 1; |
be077922 | 5126 | device_unlock(&dev->dev); |
61cf16d8 AW |
5127 | } |
5128 | ||
5129 | return 0; | |
5130 | } | |
e3a9b121 | 5131 | EXPORT_SYMBOL_GPL(pci_dev_trylock); |
61cf16d8 | 5132 | |
e3a9b121 | 5133 | void pci_dev_unlock(struct pci_dev *dev) |
77cb985a | 5134 | { |
77cb985a | 5135 | pci_cfg_access_unlock(dev); |
be077922 | 5136 | device_unlock(&dev->dev); |
77cb985a | 5137 | } |
e3a9b121 | 5138 | EXPORT_SYMBOL_GPL(pci_dev_unlock); |
77cb985a | 5139 | |
775755ed | 5140 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3ebe7f9f KB |
5141 | { |
5142 | const struct pci_error_handlers *err_handler = | |
5143 | dev->driver ? dev->driver->err_handler : NULL; | |
3ebe7f9f | 5144 | |
b014e96d | 5145 | /* |
775755ed | 5146 | * dev->driver->err_handler->reset_prepare() is protected against |
b014e96d CH |
5147 | * races with ->remove() by the device lock, which must be held by |
5148 | * the caller. | |
5149 | */ | |
775755ed CH |
5150 | if (err_handler && err_handler->reset_prepare) |
5151 | err_handler->reset_prepare(dev); | |
3ebe7f9f | 5152 | |
a6cbaade AW |
5153 | /* |
5154 | * Wake-up device prior to save. PM registers default to D0 after | |
5155 | * reset and a simple register restore doesn't reliably return | |
5156 | * to a non-D0 state anyway. | |
5157 | */ | |
5158 | pci_set_power_state(dev, PCI_D0); | |
5159 | ||
77cb985a AW |
5160 | pci_save_state(dev); |
5161 | /* | |
5162 | * Disable the device by clearing the Command register, except for | |
5163 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
5164 | * BARs, but also prevents the device from being Bus Master, preventing | |
5165 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
5166 | * compliant devices, INTx-disable prevents legacy interrupts. | |
5167 | */ | |
5168 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
5169 | } | |
5170 | ||
5171 | static void pci_dev_restore(struct pci_dev *dev) | |
5172 | { | |
775755ed CH |
5173 | const struct pci_error_handlers *err_handler = |
5174 | dev->driver ? dev->driver->err_handler : NULL; | |
977f857c | 5175 | |
77cb985a | 5176 | pci_restore_state(dev); |
77cb985a | 5177 | |
775755ed CH |
5178 | /* |
5179 | * dev->driver->err_handler->reset_done() is protected against | |
5180 | * races with ->remove() by the device lock, which must be held by | |
5181 | * the caller. | |
5182 | */ | |
5183 | if (err_handler && err_handler->reset_done) | |
5184 | err_handler->reset_done(dev); | |
d91cdc74 | 5185 | } |
3ebe7f9f | 5186 | |
e20afa06 AN |
5187 | /* dev->reset_methods[] is a 0-terminated list of indices into this array */ |
5188 | static const struct pci_reset_fn_method pci_reset_fn_methods[] = { | |
5189 | { }, | |
5190 | { pci_dev_specific_reset, .name = "device_specific" }, | |
6937b7dd | 5191 | { pci_dev_acpi_reset, .name = "acpi" }, |
e20afa06 AN |
5192 | { pcie_reset_flr, .name = "flr" }, |
5193 | { pci_af_flr, .name = "af_flr" }, | |
5194 | { pci_pm_reset, .name = "pm" }, | |
5195 | { pci_reset_bus_function, .name = "bus" }, | |
5196 | }; | |
5197 | ||
d88f521d AN |
5198 | static ssize_t reset_method_show(struct device *dev, |
5199 | struct device_attribute *attr, char *buf) | |
5200 | { | |
5201 | struct pci_dev *pdev = to_pci_dev(dev); | |
5202 | ssize_t len = 0; | |
5203 | int i, m; | |
5204 | ||
5205 | for (i = 0; i < PCI_NUM_RESET_METHODS; i++) { | |
5206 | m = pdev->reset_methods[i]; | |
5207 | if (!m) | |
5208 | break; | |
5209 | ||
5210 | len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "", | |
5211 | pci_reset_fn_methods[m].name); | |
5212 | } | |
5213 | ||
5214 | if (len) | |
5215 | len += sysfs_emit_at(buf, len, "\n"); | |
5216 | ||
5217 | return len; | |
5218 | } | |
5219 | ||
5220 | static int reset_method_lookup(const char *name) | |
5221 | { | |
5222 | int m; | |
5223 | ||
5224 | for (m = 1; m < PCI_NUM_RESET_METHODS; m++) { | |
5225 | if (sysfs_streq(name, pci_reset_fn_methods[m].name)) | |
5226 | return m; | |
5227 | } | |
5228 | ||
5229 | return 0; /* not found */ | |
5230 | } | |
5231 | ||
5232 | static ssize_t reset_method_store(struct device *dev, | |
5233 | struct device_attribute *attr, | |
5234 | const char *buf, size_t count) | |
5235 | { | |
5236 | struct pci_dev *pdev = to_pci_dev(dev); | |
5237 | char *options, *name; | |
5238 | int m, n; | |
5239 | u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 }; | |
5240 | ||
5241 | if (sysfs_streq(buf, "")) { | |
5242 | pdev->reset_methods[0] = 0; | |
5243 | pci_warn(pdev, "All device reset methods disabled by user"); | |
5244 | return count; | |
5245 | } | |
5246 | ||
5247 | if (sysfs_streq(buf, "default")) { | |
5248 | pci_init_reset_methods(pdev); | |
5249 | return count; | |
5250 | } | |
5251 | ||
5252 | options = kstrndup(buf, count, GFP_KERNEL); | |
5253 | if (!options) | |
5254 | return -ENOMEM; | |
5255 | ||
5256 | n = 0; | |
5257 | while ((name = strsep(&options, " ")) != NULL) { | |
5258 | if (sysfs_streq(name, "")) | |
5259 | continue; | |
5260 | ||
5261 | name = strim(name); | |
5262 | ||
5263 | m = reset_method_lookup(name); | |
5264 | if (!m) { | |
5265 | pci_err(pdev, "Invalid reset method '%s'", name); | |
5266 | goto error; | |
5267 | } | |
5268 | ||
9bdc81ce | 5269 | if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) { |
d88f521d AN |
5270 | pci_err(pdev, "Unsupported reset method '%s'", name); |
5271 | goto error; | |
5272 | } | |
5273 | ||
5274 | if (n == PCI_NUM_RESET_METHODS - 1) { | |
5275 | pci_err(pdev, "Too many reset methods\n"); | |
5276 | goto error; | |
5277 | } | |
5278 | ||
5279 | reset_methods[n++] = m; | |
5280 | } | |
5281 | ||
5282 | reset_methods[n] = 0; | |
5283 | ||
5284 | /* Warn if dev-specific supported but not highest priority */ | |
9bdc81ce | 5285 | if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 && |
d88f521d AN |
5286 | reset_methods[0] != 1) |
5287 | pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user"); | |
5288 | memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods)); | |
5289 | kfree(options); | |
5290 | return count; | |
5291 | ||
5292 | error: | |
5293 | /* Leave previous methods unchanged */ | |
5294 | kfree(options); | |
5295 | return -EINVAL; | |
5296 | } | |
5297 | static DEVICE_ATTR_RW(reset_method); | |
5298 | ||
5299 | static struct attribute *pci_dev_reset_method_attrs[] = { | |
5300 | &dev_attr_reset_method.attr, | |
5301 | NULL, | |
5302 | }; | |
5303 | ||
5304 | static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj, | |
5305 | struct attribute *a, int n) | |
5306 | { | |
5307 | struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj)); | |
5308 | ||
5309 | if (!pci_reset_supported(pdev)) | |
5310 | return 0; | |
5311 | ||
5312 | return a->mode; | |
5313 | } | |
5314 | ||
5315 | const struct attribute_group pci_dev_reset_method_attr_group = { | |
5316 | .attrs = pci_dev_reset_method_attrs, | |
5317 | .is_visible = pci_dev_reset_method_attr_is_visible, | |
5318 | }; | |
5319 | ||
6fbf9e7a KRW |
5320 | /** |
5321 | * __pci_reset_function_locked - reset a PCI device function while holding | |
5322 | * the @dev mutex lock. | |
5323 | * @dev: PCI device to reset | |
5324 | * | |
5325 | * Some devices allow an individual function to be reset without affecting | |
5326 | * other functions in the same device. The PCI device must be responsive | |
5327 | * to PCI config space in order to use this function. | |
5328 | * | |
5329 | * The device function is presumed to be unused and the caller is holding | |
5330 | * the device mutex lock when this function is called. | |
74356add | 5331 | * |
6fbf9e7a KRW |
5332 | * Resetting the device will make the contents of PCI configuration space |
5333 | * random, so any caller of this must be prepared to reinitialise the | |
5334 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
5335 | * etc. | |
5336 | * | |
5337 | * Returns 0 if the device function was successfully reset or negative if the | |
5338 | * device doesn't support resetting a single function. | |
5339 | */ | |
5340 | int __pci_reset_function_locked(struct pci_dev *dev) | |
5341 | { | |
e20afa06 | 5342 | int i, m, rc = -ENOTTY; |
52354b9d CH |
5343 | |
5344 | might_sleep(); | |
5345 | ||
832c418a | 5346 | /* |
e20afa06 AN |
5347 | * A reset method returns -ENOTTY if it doesn't support this device and |
5348 | * we should try the next method. | |
832c418a | 5349 | * |
e20afa06 AN |
5350 | * If it returns 0 (success), we're finished. If it returns any other |
5351 | * error, we're also finished: this indicates that further reset | |
5352 | * mechanisms might be broken on the device. | |
832c418a | 5353 | */ |
e20afa06 AN |
5354 | for (i = 0; i < PCI_NUM_RESET_METHODS; i++) { |
5355 | m = dev->reset_methods[i]; | |
5356 | if (!m) | |
5357 | return -ENOTTY; | |
5358 | ||
9bdc81ce | 5359 | rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET); |
e20afa06 AN |
5360 | if (!rc) |
5361 | return 0; | |
91295d79 SK |
5362 | if (rc != -ENOTTY) |
5363 | return rc; | |
52354b9d | 5364 | } |
e20afa06 AN |
5365 | |
5366 | return -ENOTTY; | |
6fbf9e7a KRW |
5367 | } |
5368 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
5369 | ||
711d5779 | 5370 | /** |
e20afa06 AN |
5371 | * pci_init_reset_methods - check whether device can be safely reset |
5372 | * and store supported reset mechanisms. | |
5373 | * @dev: PCI device to check for reset mechanisms | |
711d5779 MT |
5374 | * |
5375 | * Some devices allow an individual function to be reset without affecting | |
e20afa06 AN |
5376 | * other functions in the same device. The PCI device must be in D0-D3hot |
5377 | * state. | |
711d5779 | 5378 | * |
e20afa06 AN |
5379 | * Stores reset mechanisms supported by device in reset_methods byte array |
5380 | * which is a member of struct pci_dev. | |
711d5779 | 5381 | */ |
e20afa06 | 5382 | void pci_init_reset_methods(struct pci_dev *dev) |
711d5779 | 5383 | { |
e20afa06 AN |
5384 | int m, i, rc; |
5385 | ||
5386 | BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS); | |
52354b9d CH |
5387 | |
5388 | might_sleep(); | |
5389 | ||
e20afa06 AN |
5390 | i = 0; |
5391 | for (m = 1; m < PCI_NUM_RESET_METHODS; m++) { | |
9bdc81ce | 5392 | rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE); |
e20afa06 AN |
5393 | if (!rc) |
5394 | dev->reset_methods[i++] = m; | |
5395 | else if (rc != -ENOTTY) | |
5396 | break; | |
5397 | } | |
52354b9d | 5398 | |
e20afa06 | 5399 | dev->reset_methods[i] = 0; |
711d5779 MT |
5400 | } |
5401 | ||
8dd7f803 | 5402 | /** |
8c1c699f YZ |
5403 | * pci_reset_function - quiesce and reset a PCI device function |
5404 | * @dev: PCI device to reset | |
8dd7f803 SY |
5405 | * |
5406 | * Some devices allow an individual function to be reset without affecting | |
5407 | * other functions in the same device. The PCI device must be responsive | |
5408 | * to PCI config space in order to use this function. | |
5409 | * | |
5410 | * This function does not just reset the PCI portion of a device, but | |
5411 | * clears all the state associated with the device. This function differs | |
79e699b6 JS |
5412 | * from __pci_reset_function_locked() in that it saves and restores device state |
5413 | * over the reset and takes the PCI device lock. | |
8dd7f803 | 5414 | * |
8c1c699f | 5415 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
5416 | * device doesn't support resetting a single function. |
5417 | */ | |
5418 | int pci_reset_function(struct pci_dev *dev) | |
5419 | { | |
8c1c699f | 5420 | int rc; |
8dd7f803 | 5421 | |
4ec36dfe | 5422 | if (!pci_reset_supported(dev)) |
204f4afa | 5423 | return -ENOTTY; |
8dd7f803 | 5424 | |
b014e96d | 5425 | pci_dev_lock(dev); |
77cb985a | 5426 | pci_dev_save_and_disable(dev); |
8dd7f803 | 5427 | |
52354b9d | 5428 | rc = __pci_reset_function_locked(dev); |
8dd7f803 | 5429 | |
77cb985a | 5430 | pci_dev_restore(dev); |
b014e96d | 5431 | pci_dev_unlock(dev); |
8dd7f803 | 5432 | |
8c1c699f | 5433 | return rc; |
8dd7f803 SY |
5434 | } |
5435 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
5436 | ||
a477b9cd MZ |
5437 | /** |
5438 | * pci_reset_function_locked - quiesce and reset a PCI device function | |
5439 | * @dev: PCI device to reset | |
5440 | * | |
5441 | * Some devices allow an individual function to be reset without affecting | |
5442 | * other functions in the same device. The PCI device must be responsive | |
5443 | * to PCI config space in order to use this function. | |
5444 | * | |
5445 | * This function does not just reset the PCI portion of a device, but | |
5446 | * clears all the state associated with the device. This function differs | |
79e699b6 | 5447 | * from __pci_reset_function_locked() in that it saves and restores device state |
a477b9cd MZ |
5448 | * over the reset. It also differs from pci_reset_function() in that it |
5449 | * requires the PCI device lock to be held. | |
5450 | * | |
5451 | * Returns 0 if the device function was successfully reset or negative if the | |
5452 | * device doesn't support resetting a single function. | |
5453 | */ | |
5454 | int pci_reset_function_locked(struct pci_dev *dev) | |
5455 | { | |
5456 | int rc; | |
5457 | ||
4ec36dfe | 5458 | if (!pci_reset_supported(dev)) |
204f4afa | 5459 | return -ENOTTY; |
a477b9cd MZ |
5460 | |
5461 | pci_dev_save_and_disable(dev); | |
5462 | ||
5463 | rc = __pci_reset_function_locked(dev); | |
5464 | ||
5465 | pci_dev_restore(dev); | |
5466 | ||
5467 | return rc; | |
5468 | } | |
5469 | EXPORT_SYMBOL_GPL(pci_reset_function_locked); | |
5470 | ||
61cf16d8 AW |
5471 | /** |
5472 | * pci_try_reset_function - quiesce and reset a PCI device function | |
5473 | * @dev: PCI device to reset | |
5474 | * | |
5475 | * Same as above, except return -EAGAIN if unable to lock device. | |
5476 | */ | |
5477 | int pci_try_reset_function(struct pci_dev *dev) | |
5478 | { | |
5479 | int rc; | |
5480 | ||
4ec36dfe | 5481 | if (!pci_reset_supported(dev)) |
204f4afa | 5482 | return -ENOTTY; |
61cf16d8 | 5483 | |
b014e96d CH |
5484 | if (!pci_dev_trylock(dev)) |
5485 | return -EAGAIN; | |
61cf16d8 | 5486 | |
b014e96d | 5487 | pci_dev_save_and_disable(dev); |
52354b9d | 5488 | rc = __pci_reset_function_locked(dev); |
cb5e0d06 | 5489 | pci_dev_restore(dev); |
b014e96d | 5490 | pci_dev_unlock(dev); |
61cf16d8 | 5491 | |
61cf16d8 AW |
5492 | return rc; |
5493 | } | |
5494 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
5495 | ||
f331a859 AW |
5496 | /* Do any devices on or below this bus prevent a bus reset? */ |
5497 | static bool pci_bus_resetable(struct pci_bus *bus) | |
5498 | { | |
5499 | struct pci_dev *dev; | |
5500 | ||
35702778 DD |
5501 | |
5502 | if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5503 | return false; | |
5504 | ||
f331a859 AW |
5505 | list_for_each_entry(dev, &bus->devices, bus_list) { |
5506 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5507 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5508 | return false; | |
5509 | } | |
5510 | ||
5511 | return true; | |
5512 | } | |
5513 | ||
090a3c53 AW |
5514 | /* Lock devices from the top of the tree down */ |
5515 | static void pci_bus_lock(struct pci_bus *bus) | |
5516 | { | |
5517 | struct pci_dev *dev; | |
5518 | ||
5519 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5520 | pci_dev_lock(dev); | |
5521 | if (dev->subordinate) | |
5522 | pci_bus_lock(dev->subordinate); | |
5523 | } | |
5524 | } | |
5525 | ||
5526 | /* Unlock devices from the bottom of the tree up */ | |
5527 | static void pci_bus_unlock(struct pci_bus *bus) | |
5528 | { | |
5529 | struct pci_dev *dev; | |
5530 | ||
5531 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5532 | if (dev->subordinate) | |
5533 | pci_bus_unlock(dev->subordinate); | |
5534 | pci_dev_unlock(dev); | |
5535 | } | |
5536 | } | |
5537 | ||
61cf16d8 AW |
5538 | /* Return 1 on successful lock, 0 on contention */ |
5539 | static int pci_bus_trylock(struct pci_bus *bus) | |
5540 | { | |
5541 | struct pci_dev *dev; | |
5542 | ||
5543 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5544 | if (!pci_dev_trylock(dev)) | |
5545 | goto unlock; | |
5546 | if (dev->subordinate) { | |
5547 | if (!pci_bus_trylock(dev->subordinate)) { | |
5548 | pci_dev_unlock(dev); | |
5549 | goto unlock; | |
5550 | } | |
5551 | } | |
5552 | } | |
5553 | return 1; | |
5554 | ||
5555 | unlock: | |
5556 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
5557 | if (dev->subordinate) | |
5558 | pci_bus_unlock(dev->subordinate); | |
5559 | pci_dev_unlock(dev); | |
5560 | } | |
5561 | return 0; | |
5562 | } | |
5563 | ||
f331a859 AW |
5564 | /* Do any devices on or below this slot prevent a bus reset? */ |
5565 | static bool pci_slot_resetable(struct pci_slot *slot) | |
5566 | { | |
5567 | struct pci_dev *dev; | |
5568 | ||
33ba90aa JG |
5569 | if (slot->bus->self && |
5570 | (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5571 | return false; | |
5572 | ||
f331a859 AW |
5573 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { |
5574 | if (!dev->slot || dev->slot != slot) | |
5575 | continue; | |
5576 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5577 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5578 | return false; | |
5579 | } | |
5580 | ||
5581 | return true; | |
5582 | } | |
5583 | ||
090a3c53 AW |
5584 | /* Lock devices from the top of the tree down */ |
5585 | static void pci_slot_lock(struct pci_slot *slot) | |
5586 | { | |
5587 | struct pci_dev *dev; | |
5588 | ||
5589 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5590 | if (!dev->slot || dev->slot != slot) | |
5591 | continue; | |
5592 | pci_dev_lock(dev); | |
5593 | if (dev->subordinate) | |
5594 | pci_bus_lock(dev->subordinate); | |
5595 | } | |
5596 | } | |
5597 | ||
5598 | /* Unlock devices from the bottom of the tree up */ | |
5599 | static void pci_slot_unlock(struct pci_slot *slot) | |
5600 | { | |
5601 | struct pci_dev *dev; | |
5602 | ||
5603 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5604 | if (!dev->slot || dev->slot != slot) | |
5605 | continue; | |
5606 | if (dev->subordinate) | |
5607 | pci_bus_unlock(dev->subordinate); | |
5608 | pci_dev_unlock(dev); | |
5609 | } | |
5610 | } | |
5611 | ||
61cf16d8 AW |
5612 | /* Return 1 on successful lock, 0 on contention */ |
5613 | static int pci_slot_trylock(struct pci_slot *slot) | |
5614 | { | |
5615 | struct pci_dev *dev; | |
5616 | ||
5617 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5618 | if (!dev->slot || dev->slot != slot) | |
5619 | continue; | |
5620 | if (!pci_dev_trylock(dev)) | |
5621 | goto unlock; | |
5622 | if (dev->subordinate) { | |
5623 | if (!pci_bus_trylock(dev->subordinate)) { | |
5624 | pci_dev_unlock(dev); | |
5625 | goto unlock; | |
5626 | } | |
5627 | } | |
5628 | } | |
5629 | return 1; | |
5630 | ||
5631 | unlock: | |
5632 | list_for_each_entry_continue_reverse(dev, | |
5633 | &slot->bus->devices, bus_list) { | |
5634 | if (!dev->slot || dev->slot != slot) | |
5635 | continue; | |
5636 | if (dev->subordinate) | |
5637 | pci_bus_unlock(dev->subordinate); | |
5638 | pci_dev_unlock(dev); | |
5639 | } | |
5640 | return 0; | |
5641 | } | |
5642 | ||
ddefc033 AW |
5643 | /* |
5644 | * Save and disable devices from the top of the tree down while holding | |
5645 | * the @dev mutex lock for the entire tree. | |
5646 | */ | |
5647 | static void pci_bus_save_and_disable_locked(struct pci_bus *bus) | |
090a3c53 AW |
5648 | { |
5649 | struct pci_dev *dev; | |
5650 | ||
5651 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5652 | pci_dev_save_and_disable(dev); | |
5653 | if (dev->subordinate) | |
ddefc033 | 5654 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5655 | } |
5656 | } | |
5657 | ||
5658 | /* | |
ddefc033 AW |
5659 | * Restore devices from top of the tree down while holding @dev mutex lock |
5660 | * for the entire tree. Parent bridges need to be restored before we can | |
5661 | * get to subordinate devices. | |
090a3c53 | 5662 | */ |
ddefc033 | 5663 | static void pci_bus_restore_locked(struct pci_bus *bus) |
090a3c53 AW |
5664 | { |
5665 | struct pci_dev *dev; | |
5666 | ||
5667 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5668 | pci_dev_restore(dev); | |
5669 | if (dev->subordinate) | |
ddefc033 | 5670 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5671 | } |
5672 | } | |
5673 | ||
ddefc033 AW |
5674 | /* |
5675 | * Save and disable devices from the top of the tree down while holding | |
5676 | * the @dev mutex lock for the entire tree. | |
5677 | */ | |
5678 | static void pci_slot_save_and_disable_locked(struct pci_slot *slot) | |
090a3c53 AW |
5679 | { |
5680 | struct pci_dev *dev; | |
5681 | ||
5682 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5683 | if (!dev->slot || dev->slot != slot) | |
5684 | continue; | |
5685 | pci_dev_save_and_disable(dev); | |
5686 | if (dev->subordinate) | |
ddefc033 | 5687 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5688 | } |
5689 | } | |
5690 | ||
5691 | /* | |
ddefc033 AW |
5692 | * Restore devices from top of the tree down while holding @dev mutex lock |
5693 | * for the entire tree. Parent bridges need to be restored before we can | |
5694 | * get to subordinate devices. | |
090a3c53 | 5695 | */ |
ddefc033 | 5696 | static void pci_slot_restore_locked(struct pci_slot *slot) |
090a3c53 AW |
5697 | { |
5698 | struct pci_dev *dev; | |
5699 | ||
5700 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5701 | if (!dev->slot || dev->slot != slot) | |
5702 | continue; | |
5703 | pci_dev_restore(dev); | |
5704 | if (dev->subordinate) | |
ddefc033 | 5705 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5706 | } |
5707 | } | |
5708 | ||
9bdc81ce | 5709 | static int pci_slot_reset(struct pci_slot *slot, bool probe) |
090a3c53 AW |
5710 | { |
5711 | int rc; | |
5712 | ||
f331a859 | 5713 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
5714 | return -ENOTTY; |
5715 | ||
5716 | if (!probe) | |
5717 | pci_slot_lock(slot); | |
5718 | ||
5719 | might_sleep(); | |
5720 | ||
5721 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
5722 | ||
5723 | if (!probe) | |
5724 | pci_slot_unlock(slot); | |
5725 | ||
5726 | return rc; | |
5727 | } | |
5728 | ||
9a3d2b9b AW |
5729 | /** |
5730 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
5731 | * @slot: PCI slot to probe | |
5732 | * | |
5733 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
5734 | */ | |
5735 | int pci_probe_reset_slot(struct pci_slot *slot) | |
5736 | { | |
9bdc81ce | 5737 | return pci_slot_reset(slot, PCI_RESET_PROBE); |
9a3d2b9b AW |
5738 | } |
5739 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
5740 | ||
090a3c53 | 5741 | /** |
c6a44ba9 | 5742 | * __pci_reset_slot - Try to reset a PCI slot |
090a3c53 AW |
5743 | * @slot: PCI slot to reset |
5744 | * | |
5745 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
5746 | * independent of other slots. For instance, some slots may support slot power | |
5747 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
5748 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
5749 | * Generally a slot reset should be attempted before a bus reset. All of the | |
5750 | * function of the slot and any subordinate buses behind the slot are reset | |
5751 | * through this function. PCI config space of all devices in the slot and | |
5752 | * behind the slot is saved before and restored after reset. | |
5753 | * | |
61cf16d8 AW |
5754 | * Same as above except return -EAGAIN if the slot cannot be locked |
5755 | */ | |
c6a44ba9 | 5756 | static int __pci_reset_slot(struct pci_slot *slot) |
61cf16d8 AW |
5757 | { |
5758 | int rc; | |
5759 | ||
9bdc81ce | 5760 | rc = pci_slot_reset(slot, PCI_RESET_PROBE); |
61cf16d8 AW |
5761 | if (rc) |
5762 | return rc; | |
5763 | ||
61cf16d8 | 5764 | if (pci_slot_trylock(slot)) { |
ddefc033 | 5765 | pci_slot_save_and_disable_locked(slot); |
61cf16d8 | 5766 | might_sleep(); |
9bdc81ce | 5767 | rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); |
ddefc033 | 5768 | pci_slot_restore_locked(slot); |
61cf16d8 AW |
5769 | pci_slot_unlock(slot); |
5770 | } else | |
5771 | rc = -EAGAIN; | |
5772 | ||
61cf16d8 AW |
5773 | return rc; |
5774 | } | |
61cf16d8 | 5775 | |
9bdc81ce | 5776 | static int pci_bus_reset(struct pci_bus *bus, bool probe) |
090a3c53 | 5777 | { |
18426238 SK |
5778 | int ret; |
5779 | ||
f331a859 | 5780 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
5781 | return -ENOTTY; |
5782 | ||
5783 | if (probe) | |
5784 | return 0; | |
5785 | ||
5786 | pci_bus_lock(bus); | |
5787 | ||
5788 | might_sleep(); | |
5789 | ||
381634ca | 5790 | ret = pci_bridge_secondary_bus_reset(bus->self); |
090a3c53 AW |
5791 | |
5792 | pci_bus_unlock(bus); | |
5793 | ||
18426238 | 5794 | return ret; |
090a3c53 AW |
5795 | } |
5796 | ||
c4eed62a KB |
5797 | /** |
5798 | * pci_bus_error_reset - reset the bridge's subordinate bus | |
5799 | * @bridge: The parent device that connects to the bus to reset | |
5800 | * | |
5801 | * This function will first try to reset the slots on this bus if the method is | |
5802 | * available. If slot reset fails or is not available, this will fall back to a | |
5803 | * secondary bus reset. | |
5804 | */ | |
5805 | int pci_bus_error_reset(struct pci_dev *bridge) | |
5806 | { | |
5807 | struct pci_bus *bus = bridge->subordinate; | |
5808 | struct pci_slot *slot; | |
5809 | ||
5810 | if (!bus) | |
5811 | return -ENOTTY; | |
5812 | ||
5813 | mutex_lock(&pci_slot_mutex); | |
5814 | if (list_empty(&bus->slots)) | |
5815 | goto bus_reset; | |
5816 | ||
5817 | list_for_each_entry(slot, &bus->slots, list) | |
5818 | if (pci_probe_reset_slot(slot)) | |
5819 | goto bus_reset; | |
5820 | ||
5821 | list_for_each_entry(slot, &bus->slots, list) | |
9bdc81ce | 5822 | if (pci_slot_reset(slot, PCI_RESET_DO_RESET)) |
c4eed62a KB |
5823 | goto bus_reset; |
5824 | ||
5825 | mutex_unlock(&pci_slot_mutex); | |
5826 | return 0; | |
5827 | bus_reset: | |
5828 | mutex_unlock(&pci_slot_mutex); | |
9bdc81ce | 5829 | return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); |
c4eed62a KB |
5830 | } |
5831 | ||
9a3d2b9b AW |
5832 | /** |
5833 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
5834 | * @bus: PCI bus to probe | |
5835 | * | |
5836 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
5837 | */ | |
5838 | int pci_probe_reset_bus(struct pci_bus *bus) | |
5839 | { | |
9bdc81ce | 5840 | return pci_bus_reset(bus, PCI_RESET_PROBE); |
9a3d2b9b AW |
5841 | } |
5842 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
5843 | ||
090a3c53 | 5844 | /** |
c6a44ba9 | 5845 | * __pci_reset_bus - Try to reset a PCI bus |
090a3c53 AW |
5846 | * @bus: top level PCI bus to reset |
5847 | * | |
61cf16d8 | 5848 | * Same as above except return -EAGAIN if the bus cannot be locked |
090a3c53 | 5849 | */ |
c6a44ba9 | 5850 | static int __pci_reset_bus(struct pci_bus *bus) |
090a3c53 AW |
5851 | { |
5852 | int rc; | |
5853 | ||
9bdc81ce | 5854 | rc = pci_bus_reset(bus, PCI_RESET_PROBE); |
090a3c53 AW |
5855 | if (rc) |
5856 | return rc; | |
5857 | ||
61cf16d8 | 5858 | if (pci_bus_trylock(bus)) { |
ddefc033 | 5859 | pci_bus_save_and_disable_locked(bus); |
61cf16d8 | 5860 | might_sleep(); |
381634ca | 5861 | rc = pci_bridge_secondary_bus_reset(bus->self); |
ddefc033 | 5862 | pci_bus_restore_locked(bus); |
61cf16d8 AW |
5863 | pci_bus_unlock(bus); |
5864 | } else | |
5865 | rc = -EAGAIN; | |
090a3c53 | 5866 | |
090a3c53 AW |
5867 | return rc; |
5868 | } | |
090a3c53 | 5869 | |
61cf16d8 | 5870 | /** |
c6a44ba9 | 5871 | * pci_reset_bus - Try to reset a PCI bus |
811c5cb3 | 5872 | * @pdev: top level PCI device to reset via slot/bus |
61cf16d8 AW |
5873 | * |
5874 | * Same as above except return -EAGAIN if the bus cannot be locked | |
5875 | */ | |
c6a44ba9 | 5876 | int pci_reset_bus(struct pci_dev *pdev) |
61cf16d8 | 5877 | { |
d8a52810 | 5878 | return (!pci_probe_reset_slot(pdev->slot)) ? |
c6a44ba9 | 5879 | __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); |
61cf16d8 | 5880 | } |
c6a44ba9 | 5881 | EXPORT_SYMBOL_GPL(pci_reset_bus); |
61cf16d8 | 5882 | |
d556ad4b PO |
5883 | /** |
5884 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
5885 | * @dev: PCI device to query | |
5886 | * | |
74356add BH |
5887 | * Returns mmrbc: maximum designed memory read count in bytes or |
5888 | * appropriate error value. | |
d556ad4b PO |
5889 | */ |
5890 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
5891 | { | |
7c9e2b1c | 5892 | int cap; |
d556ad4b PO |
5893 | u32 stat; |
5894 | ||
5895 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5896 | if (!cap) | |
5897 | return -EINVAL; | |
5898 | ||
7c9e2b1c | 5899 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
5900 | return -EINVAL; |
5901 | ||
25daeb55 | 5902 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
5903 | } |
5904 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
5905 | ||
5906 | /** | |
5907 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
5908 | * @dev: PCI device to query | |
5909 | * | |
74356add BH |
5910 | * Returns mmrbc: maximum memory read count in bytes or appropriate error |
5911 | * value. | |
d556ad4b PO |
5912 | */ |
5913 | int pcix_get_mmrbc(struct pci_dev *dev) | |
5914 | { | |
7c9e2b1c | 5915 | int cap; |
bdc2bda7 | 5916 | u16 cmd; |
d556ad4b PO |
5917 | |
5918 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5919 | if (!cap) | |
5920 | return -EINVAL; | |
5921 | ||
7c9e2b1c DN |
5922 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5923 | return -EINVAL; | |
d556ad4b | 5924 | |
7c9e2b1c | 5925 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
5926 | } |
5927 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
5928 | ||
5929 | /** | |
5930 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
5931 | * @dev: PCI device to query | |
5932 | * @mmrbc: maximum memory read count in bytes | |
5933 | * valid values are 512, 1024, 2048, 4096 | |
5934 | * | |
74356add | 5935 | * If possible sets maximum memory read byte count, some bridges have errata |
d556ad4b PO |
5936 | * that prevent this. |
5937 | */ | |
5938 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
5939 | { | |
7c9e2b1c | 5940 | int cap; |
bdc2bda7 DN |
5941 | u32 stat, v, o; |
5942 | u16 cmd; | |
d556ad4b | 5943 | |
229f5afd | 5944 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 5945 | return -EINVAL; |
d556ad4b PO |
5946 | |
5947 | v = ffs(mmrbc) - 10; | |
5948 | ||
5949 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5950 | if (!cap) | |
7c9e2b1c | 5951 | return -EINVAL; |
d556ad4b | 5952 | |
7c9e2b1c DN |
5953 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
5954 | return -EINVAL; | |
d556ad4b PO |
5955 | |
5956 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
5957 | return -E2BIG; | |
5958 | ||
7c9e2b1c DN |
5959 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5960 | return -EINVAL; | |
d556ad4b PO |
5961 | |
5962 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
5963 | if (o != v) { | |
809a3bf9 | 5964 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
5965 | return -EIO; |
5966 | ||
5967 | cmd &= ~PCI_X_CMD_MAX_READ; | |
5968 | cmd |= v << 2; | |
7c9e2b1c DN |
5969 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
5970 | return -EIO; | |
d556ad4b | 5971 | } |
7c9e2b1c | 5972 | return 0; |
d556ad4b PO |
5973 | } |
5974 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
5975 | ||
5976 | /** | |
5977 | * pcie_get_readrq - get PCI Express read request size | |
5978 | * @dev: PCI device to query | |
5979 | * | |
74356add | 5980 | * Returns maximum memory read request in bytes or appropriate error value. |
d556ad4b PO |
5981 | */ |
5982 | int pcie_get_readrq(struct pci_dev *dev) | |
5983 | { | |
d556ad4b PO |
5984 | u16 ctl; |
5985 | ||
59875ae4 | 5986 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 5987 | |
59875ae4 | 5988 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
5989 | } |
5990 | EXPORT_SYMBOL(pcie_get_readrq); | |
5991 | ||
5992 | /** | |
5993 | * pcie_set_readrq - set PCI Express maximum memory read request | |
5994 | * @dev: PCI device to query | |
42e61f4a | 5995 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
5996 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5997 | * | |
c9b378c7 | 5998 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
5999 | */ |
6000 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
6001 | { | |
59875ae4 | 6002 | u16 v; |
d20df83b | 6003 | int ret; |
d556ad4b | 6004 | |
229f5afd | 6005 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 6006 | return -EINVAL; |
d556ad4b | 6007 | |
a1c473aa | 6008 | /* |
74356add BH |
6009 | * If using the "performance" PCIe config, we clamp the read rq |
6010 | * size to the max packet size to keep the host bridge from | |
6011 | * generating requests larger than we can cope with. | |
a1c473aa BH |
6012 | */ |
6013 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
6014 | int mps = pcie_get_mps(dev); | |
6015 | ||
a1c473aa BH |
6016 | if (mps < rq) |
6017 | rq = mps; | |
6018 | } | |
6019 | ||
6020 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 6021 | |
d20df83b | 6022 | ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
59875ae4 | 6023 | PCI_EXP_DEVCTL_READRQ, v); |
d20df83b BOS |
6024 | |
6025 | return pcibios_err_to_errno(ret); | |
d556ad4b PO |
6026 | } |
6027 | EXPORT_SYMBOL(pcie_set_readrq); | |
6028 | ||
b03e7495 JM |
6029 | /** |
6030 | * pcie_get_mps - get PCI Express maximum payload size | |
6031 | * @dev: PCI device to query | |
6032 | * | |
6033 | * Returns maximum payload size in bytes | |
b03e7495 JM |
6034 | */ |
6035 | int pcie_get_mps(struct pci_dev *dev) | |
6036 | { | |
b03e7495 JM |
6037 | u16 ctl; |
6038 | ||
59875ae4 | 6039 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 6040 | |
59875ae4 | 6041 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 6042 | } |
f1c66c46 | 6043 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
6044 | |
6045 | /** | |
6046 | * pcie_set_mps - set PCI Express maximum payload size | |
6047 | * @dev: PCI device to query | |
47c08f31 | 6048 | * @mps: maximum payload size in bytes |
b03e7495 JM |
6049 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
6050 | * | |
6051 | * If possible sets maximum payload size | |
6052 | */ | |
6053 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
6054 | { | |
59875ae4 | 6055 | u16 v; |
d20df83b | 6056 | int ret; |
b03e7495 JM |
6057 | |
6058 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 6059 | return -EINVAL; |
b03e7495 JM |
6060 | |
6061 | v = ffs(mps) - 8; | |
f7625980 | 6062 | if (v > dev->pcie_mpss) |
59875ae4 | 6063 | return -EINVAL; |
b03e7495 JM |
6064 | v <<= 5; |
6065 | ||
d20df83b | 6066 | ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
59875ae4 | 6067 | PCI_EXP_DEVCTL_PAYLOAD, v); |
d20df83b BOS |
6068 | |
6069 | return pcibios_err_to_errno(ret); | |
b03e7495 | 6070 | } |
f1c66c46 | 6071 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 6072 | |
6db79a88 TG |
6073 | /** |
6074 | * pcie_bandwidth_available - determine minimum link settings of a PCIe | |
6075 | * device and its bandwidth limitation | |
6076 | * @dev: PCI device to query | |
6077 | * @limiting_dev: storage for device causing the bandwidth limitation | |
6078 | * @speed: storage for speed of limiting device | |
6079 | * @width: storage for width of limiting device | |
6080 | * | |
6081 | * Walk up the PCI device chain and find the point where the minimum | |
6082 | * bandwidth is available. Return the bandwidth available there and (if | |
6083 | * limiting_dev, speed, and width pointers are supplied) information about | |
6084 | * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of | |
6085 | * raw bandwidth. | |
6086 | */ | |
6087 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, | |
6088 | enum pci_bus_speed *speed, | |
6089 | enum pcie_link_width *width) | |
6090 | { | |
6091 | u16 lnksta; | |
6092 | enum pci_bus_speed next_speed; | |
6093 | enum pcie_link_width next_width; | |
6094 | u32 bw, next_bw; | |
6095 | ||
6096 | if (speed) | |
6097 | *speed = PCI_SPEED_UNKNOWN; | |
6098 | if (width) | |
6099 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
6100 | ||
6101 | bw = 0; | |
6102 | ||
6103 | while (dev) { | |
6104 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
6105 | ||
6106 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
6107 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
6108 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
6109 | ||
6110 | next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); | |
6111 | ||
6112 | /* Check if current device limits the total bandwidth */ | |
6113 | if (!bw || next_bw <= bw) { | |
6114 | bw = next_bw; | |
6115 | ||
6116 | if (limiting_dev) | |
6117 | *limiting_dev = dev; | |
6118 | if (speed) | |
6119 | *speed = next_speed; | |
6120 | if (width) | |
6121 | *width = next_width; | |
6122 | } | |
6123 | ||
6124 | dev = pci_upstream_bridge(dev); | |
6125 | } | |
6126 | ||
6127 | return bw; | |
6128 | } | |
6129 | EXPORT_SYMBOL(pcie_bandwidth_available); | |
6130 | ||
6cf57be0 TG |
6131 | /** |
6132 | * pcie_get_speed_cap - query for the PCI device's link speed capability | |
6133 | * @dev: PCI device to query | |
6134 | * | |
6135 | * Query the PCI device speed capability. Return the maximum link speed | |
6136 | * supported by the device. | |
6137 | */ | |
6138 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) | |
6139 | { | |
6140 | u32 lnkcap2, lnkcap; | |
6141 | ||
6142 | /* | |
f1f90e25 MP |
6143 | * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The |
6144 | * implementation note there recommends using the Supported Link | |
6145 | * Speeds Vector in Link Capabilities 2 when supported. | |
6146 | * | |
6147 | * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software | |
6148 | * should use the Supported Link Speeds field in Link Capabilities, | |
6149 | * where only 2.5 GT/s and 5.0 GT/s speeds were defined. | |
6cf57be0 TG |
6150 | */ |
6151 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); | |
757bfaa2 YY |
6152 | |
6153 | /* PCIe r3.0-compliant */ | |
6154 | if (lnkcap2) | |
6155 | return PCIE_LNKCAP2_SLS2SPEED(lnkcap2); | |
6cf57be0 TG |
6156 | |
6157 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
f1f90e25 MP |
6158 | if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) |
6159 | return PCIE_SPEED_5_0GT; | |
6160 | else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) | |
6161 | return PCIE_SPEED_2_5GT; | |
6cf57be0 TG |
6162 | |
6163 | return PCI_SPEED_UNKNOWN; | |
6164 | } | |
576c7218 | 6165 | EXPORT_SYMBOL(pcie_get_speed_cap); |
6cf57be0 | 6166 | |
c70b65fb TG |
6167 | /** |
6168 | * pcie_get_width_cap - query for the PCI device's link width capability | |
6169 | * @dev: PCI device to query | |
6170 | * | |
6171 | * Query the PCI device width capability. Return the maximum link width | |
6172 | * supported by the device. | |
6173 | */ | |
6174 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) | |
6175 | { | |
6176 | u32 lnkcap; | |
6177 | ||
6178 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
6179 | if (lnkcap) | |
6180 | return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; | |
6181 | ||
6182 | return PCIE_LNK_WIDTH_UNKNOWN; | |
6183 | } | |
576c7218 | 6184 | EXPORT_SYMBOL(pcie_get_width_cap); |
c70b65fb | 6185 | |
b852f63a TG |
6186 | /** |
6187 | * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability | |
6188 | * @dev: PCI device | |
6189 | * @speed: storage for link speed | |
6190 | * @width: storage for link width | |
6191 | * | |
6192 | * Calculate a PCI device's link bandwidth by querying for its link speed | |
6193 | * and width, multiplying them, and applying encoding overhead. The result | |
6194 | * is in Mb/s, i.e., megabits/second of raw bandwidth. | |
6195 | */ | |
6196 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, | |
6197 | enum pcie_link_width *width) | |
6198 | { | |
6199 | *speed = pcie_get_speed_cap(dev); | |
6200 | *width = pcie_get_width_cap(dev); | |
6201 | ||
6202 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
6203 | return 0; | |
6204 | ||
6205 | return *width * PCIE_SPEED2MBS_ENC(*speed); | |
6206 | } | |
6207 | ||
9e506a7b | 6208 | /** |
2d1ce5ec | 6209 | * __pcie_print_link_status - Report the PCI device's link speed and width |
9e506a7b | 6210 | * @dev: PCI device to query |
2d1ce5ec | 6211 | * @verbose: Print info even when enough bandwidth is available |
9e506a7b | 6212 | * |
2d1ce5ec AG |
6213 | * If the available bandwidth at the device is less than the device is |
6214 | * capable of, report the device's maximum possible bandwidth and the | |
6215 | * upstream link that limits its performance. If @verbose, always print | |
6216 | * the available bandwidth, even if the device isn't constrained. | |
9e506a7b | 6217 | */ |
2d1ce5ec | 6218 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose) |
9e506a7b TG |
6219 | { |
6220 | enum pcie_link_width width, width_cap; | |
6221 | enum pci_bus_speed speed, speed_cap; | |
6222 | struct pci_dev *limiting_dev = NULL; | |
6223 | u32 bw_avail, bw_cap; | |
6224 | ||
6225 | bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap); | |
6226 | bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width); | |
6227 | ||
2d1ce5ec | 6228 | if (bw_avail >= bw_cap && verbose) |
0cf22d6b | 6229 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n", |
9e506a7b | 6230 | bw_cap / 1000, bw_cap % 1000, |
6348a34d | 6231 | pci_speed_string(speed_cap), width_cap); |
2d1ce5ec | 6232 | else if (bw_avail < bw_cap) |
0cf22d6b | 6233 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n", |
9e506a7b | 6234 | bw_avail / 1000, bw_avail % 1000, |
6348a34d | 6235 | pci_speed_string(speed), width, |
9e506a7b TG |
6236 | limiting_dev ? pci_name(limiting_dev) : "<unknown>", |
6237 | bw_cap / 1000, bw_cap % 1000, | |
6348a34d | 6238 | pci_speed_string(speed_cap), width_cap); |
9e506a7b | 6239 | } |
2d1ce5ec AG |
6240 | |
6241 | /** | |
6242 | * pcie_print_link_status - Report the PCI device's link speed and width | |
6243 | * @dev: PCI device to query | |
6244 | * | |
6245 | * Report the available bandwidth at the device. | |
6246 | */ | |
6247 | void pcie_print_link_status(struct pci_dev *dev) | |
6248 | { | |
6249 | __pcie_print_link_status(dev, true); | |
6250 | } | |
9e506a7b TG |
6251 | EXPORT_SYMBOL(pcie_print_link_status); |
6252 | ||
c87deff7 HS |
6253 | /** |
6254 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 6255 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
6256 | * @flags: resource type mask to be selected |
6257 | * | |
6258 | * This helper routine makes bar mask from the type of resource. | |
6259 | */ | |
6260 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
6261 | { | |
6262 | int i, bars = 0; | |
6263 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
6264 | if (pci_resource_flags(dev, i) & flags) | |
6265 | bars |= (1 << i); | |
6266 | return bars; | |
6267 | } | |
b7fe9434 | 6268 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 6269 | |
95a8b6ef MT |
6270 | /* Some architectures require additional programming to enable VGA */ |
6271 | static arch_set_vga_state_t arch_set_vga_state; | |
6272 | ||
6273 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
6274 | { | |
6275 | arch_set_vga_state = func; /* NULL disables */ | |
6276 | } | |
6277 | ||
6278 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 6279 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
6280 | { |
6281 | if (arch_set_vga_state) | |
6282 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 6283 | flags); |
95a8b6ef MT |
6284 | return 0; |
6285 | } | |
6286 | ||
deb2d2ec BH |
6287 | /** |
6288 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
6289 | * @dev: the PCI device |
6290 | * @decode: true = enable decoding, false = disable decoding | |
6291 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 6292 | * @flags: traverse ancestors and change bridges |
3448a19d | 6293 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
6294 | */ |
6295 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 6296 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
6297 | { |
6298 | struct pci_bus *bus; | |
6299 | struct pci_dev *bridge; | |
6300 | u16 cmd; | |
95a8b6ef | 6301 | int rc; |
deb2d2ec | 6302 | |
67ebd814 | 6303 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 6304 | |
95a8b6ef | 6305 | /* ARCH specific VGA enables */ |
3448a19d | 6306 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
6307 | if (rc) |
6308 | return rc; | |
6309 | ||
3448a19d DA |
6310 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
6311 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
0a98bb98 | 6312 | if (decode) |
3448a19d DA |
6313 | cmd |= command_bits; |
6314 | else | |
6315 | cmd &= ~command_bits; | |
6316 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
6317 | } | |
deb2d2ec | 6318 | |
3448a19d | 6319 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
6320 | return 0; |
6321 | ||
6322 | bus = dev->bus; | |
6323 | while (bus) { | |
6324 | bridge = bus->self; | |
6325 | if (bridge) { | |
6326 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
6327 | &cmd); | |
0a98bb98 | 6328 | if (decode) |
deb2d2ec BH |
6329 | cmd |= PCI_BRIDGE_CTL_VGA; |
6330 | else | |
6331 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
6332 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
6333 | cmd); | |
6334 | } | |
6335 | bus = bus->parent; | |
6336 | } | |
6337 | return 0; | |
6338 | } | |
6339 | ||
52525b7a KHF |
6340 | #ifdef CONFIG_ACPI |
6341 | bool pci_pr3_present(struct pci_dev *pdev) | |
6342 | { | |
6343 | struct acpi_device *adev; | |
6344 | ||
6345 | if (acpi_disabled) | |
6346 | return false; | |
6347 | ||
6348 | adev = ACPI_COMPANION(&pdev->dev); | |
6349 | if (!adev) | |
6350 | return false; | |
6351 | ||
6352 | return adev->power.flags.power_resources && | |
6353 | acpi_has_method(adev->handle, "_PR3"); | |
6354 | } | |
6355 | EXPORT_SYMBOL_GPL(pci_pr3_present); | |
6356 | #endif | |
6357 | ||
f0af9593 BH |
6358 | /** |
6359 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
6360 | * @dev: the PCI device for which alias is added | |
09298542 JS |
6361 | * @devfn_from: alias slot and function |
6362 | * @nr_devfns: number of subsequent devfns to alias | |
f0af9593 | 6363 | * |
f778a0d2 LG |
6364 | * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask |
6365 | * which is used to program permissible bus-devfn source addresses for DMA | |
6366 | * requests in an IOMMU. These aliases factor into IOMMU group creation | |
6367 | * and are useful for devices generating DMA requests beyond or different | |
6368 | * from their logical bus-devfn. Examples include device quirks where the | |
6369 | * device simply uses the wrong devfn, as well as non-transparent bridges | |
6370 | * where the alias may be a proxy for devices in another domain. | |
6371 | * | |
6372 | * IOMMU group creation is performed during device discovery or addition, | |
6373 | * prior to any potential DMA mapping and therefore prior to driver probing | |
6374 | * (especially for userspace assigned devices where IOMMU group definition | |
6375 | * cannot be left as a userspace activity). DMA aliases should therefore | |
6376 | * be configured via quirks, such as the PCI fixup header quirk. | |
f0af9593 | 6377 | */ |
09298542 | 6378 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns) |
f0af9593 | 6379 | { |
09298542 JS |
6380 | int devfn_to; |
6381 | ||
6382 | nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from); | |
6383 | devfn_to = devfn_from + nr_devfns - 1; | |
6384 | ||
338c3149 | 6385 | if (!dev->dma_alias_mask) |
f8bf2aeb | 6386 | dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); |
338c3149 | 6387 | if (!dev->dma_alias_mask) { |
7506dc79 | 6388 | pci_warn(dev, "Unable to allocate DMA alias mask\n"); |
338c3149 JL |
6389 | return; |
6390 | } | |
6391 | ||
09298542 JS |
6392 | bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); |
6393 | ||
6394 | if (nr_devfns == 1) | |
6395 | pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n", | |
6396 | PCI_SLOT(devfn_from), PCI_FUNC(devfn_from)); | |
6397 | else if (nr_devfns > 1) | |
6398 | pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n", | |
6399 | PCI_SLOT(devfn_from), PCI_FUNC(devfn_from), | |
6400 | PCI_SLOT(devfn_to), PCI_FUNC(devfn_to)); | |
f0af9593 BH |
6401 | } |
6402 | ||
338c3149 JL |
6403 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
6404 | { | |
6405 | return (dev1->dma_alias_mask && | |
6406 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
6407 | (dev2->dma_alias_mask && | |
2856ba60 JD |
6408 | test_bit(dev1->devfn, dev2->dma_alias_mask)) || |
6409 | pci_real_dma_dev(dev1) == dev2 || | |
6410 | pci_real_dma_dev(dev2) == dev1; | |
338c3149 JL |
6411 | } |
6412 | ||
8496e85c RW |
6413 | bool pci_device_is_present(struct pci_dev *pdev) |
6414 | { | |
6415 | u32 v; | |
6416 | ||
fe2bd75b KB |
6417 | if (pci_dev_is_disconnected(pdev)) |
6418 | return false; | |
8496e85c RW |
6419 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); |
6420 | } | |
6421 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
6422 | ||
08249651 RW |
6423 | void pci_ignore_hotplug(struct pci_dev *dev) |
6424 | { | |
6425 | struct pci_dev *bridge = dev->bus->self; | |
6426 | ||
6427 | dev->ignore_hotplug = 1; | |
6428 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
6429 | if (bridge) | |
6430 | bridge->ignore_hotplug = 1; | |
6431 | } | |
6432 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
6433 | ||
2856ba60 JD |
6434 | /** |
6435 | * pci_real_dma_dev - Get PCI DMA device for PCI device | |
6436 | * @dev: the PCI device that may have a PCI DMA alias | |
6437 | * | |
6438 | * Permits the platform to provide architecture-specific functionality to | |
6439 | * devices needing to alias DMA to another PCI device on another PCI bus. If | |
6440 | * the PCI device is on the same bus, it is recommended to use | |
6441 | * pci_add_dma_alias(). This is the default implementation. Architecture | |
6442 | * implementations can override this. | |
6443 | */ | |
6444 | struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev) | |
6445 | { | |
6446 | return dev; | |
6447 | } | |
6448 | ||
0a701aa6 YX |
6449 | resource_size_t __weak pcibios_default_alignment(void) |
6450 | { | |
6451 | return 0; | |
6452 | } | |
6453 | ||
b8074aa2 DE |
6454 | /* |
6455 | * Arches that don't want to expose struct resource to userland as-is in | |
6456 | * sysfs and /proc can implement their own pci_resource_to_user(). | |
6457 | */ | |
6458 | void __weak pci_resource_to_user(const struct pci_dev *dev, int bar, | |
6459 | const struct resource *rsrc, | |
6460 | resource_size_t *start, resource_size_t *end) | |
6461 | { | |
6462 | *start = rsrc->start; | |
6463 | *end = rsrc->end; | |
6464 | } | |
6465 | ||
70aaf61a | 6466 | static char *resource_alignment_param; |
e9d1e492 | 6467 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
6468 | |
6469 | /** | |
6470 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
6471 | * @dev: the PCI device to get | |
e3adec72 | 6472 | * @resize: whether or not to change resources' size when reassigning alignment |
32a9a682 YS |
6473 | * |
6474 | * RETURNS: Resource alignment if it is specified. | |
6475 | * Zero if it is not specified. | |
6476 | */ | |
e3adec72 YX |
6477 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, |
6478 | bool *resize) | |
32a9a682 | 6479 | { |
07d8d7e5 | 6480 | int align_order, count; |
0a701aa6 | 6481 | resource_size_t align = pcibios_default_alignment(); |
07d8d7e5 LG |
6482 | const char *p; |
6483 | int ret; | |
32a9a682 YS |
6484 | |
6485 | spin_lock(&resource_alignment_lock); | |
6486 | p = resource_alignment_param; | |
70aaf61a | 6487 | if (!p || !*p) |
f0b99f70 YX |
6488 | goto out; |
6489 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
0a701aa6 | 6490 | align = 0; |
f0b99f70 YX |
6491 | pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); |
6492 | goto out; | |
6493 | } | |
6494 | ||
32a9a682 YS |
6495 | while (*p) { |
6496 | count = 0; | |
6497 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
6534aac1 | 6498 | p[count] == '@') { |
32a9a682 | 6499 | p += count + 1; |
6534aac1 BH |
6500 | if (align_order > 63) { |
6501 | pr_err("PCI: Invalid requested alignment (order %d)\n", | |
6502 | align_order); | |
6503 | align_order = PAGE_SHIFT; | |
6504 | } | |
32a9a682 | 6505 | } else { |
6534aac1 | 6506 | align_order = PAGE_SHIFT; |
32a9a682 | 6507 | } |
07d8d7e5 LG |
6508 | |
6509 | ret = pci_dev_str_match(dev, p, &p); | |
6510 | if (ret == 1) { | |
6511 | *resize = true; | |
cc73eb32 | 6512 | align = 1ULL << align_order; |
07d8d7e5 LG |
6513 | break; |
6514 | } else if (ret < 0) { | |
6515 | pr_err("PCI: Can't parse resource_alignment parameter: %s\n", | |
6516 | p); | |
6517 | break; | |
32a9a682 | 6518 | } |
07d8d7e5 | 6519 | |
32a9a682 YS |
6520 | if (*p != ';' && *p != ',') { |
6521 | /* End of param or invalid format */ | |
6522 | break; | |
6523 | } | |
6524 | p++; | |
6525 | } | |
f0b99f70 | 6526 | out: |
32a9a682 YS |
6527 | spin_unlock(&resource_alignment_lock); |
6528 | return align; | |
6529 | } | |
6530 | ||
81a5e70e | 6531 | static void pci_request_resource_alignment(struct pci_dev *dev, int bar, |
e3adec72 | 6532 | resource_size_t align, bool resize) |
81a5e70e BH |
6533 | { |
6534 | struct resource *r = &dev->resource[bar]; | |
6535 | resource_size_t size; | |
6536 | ||
6537 | if (!(r->flags & IORESOURCE_MEM)) | |
6538 | return; | |
6539 | ||
6540 | if (r->flags & IORESOURCE_PCI_FIXED) { | |
7506dc79 | 6541 | pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n", |
81a5e70e BH |
6542 | bar, r, (unsigned long long)align); |
6543 | return; | |
6544 | } | |
6545 | ||
6546 | size = resource_size(r); | |
0dde1c08 BH |
6547 | if (size >= align) |
6548 | return; | |
81a5e70e | 6549 | |
0dde1c08 | 6550 | /* |
e3adec72 YX |
6551 | * Increase the alignment of the resource. There are two ways we |
6552 | * can do this: | |
0dde1c08 | 6553 | * |
e3adec72 YX |
6554 | * 1) Increase the size of the resource. BARs are aligned on their |
6555 | * size, so when we reallocate space for this resource, we'll | |
6556 | * allocate it with the larger alignment. This also prevents | |
6557 | * assignment of any other BARs inside the alignment region, so | |
6558 | * if we're requesting page alignment, this means no other BARs | |
6559 | * will share the page. | |
6560 | * | |
6561 | * The disadvantage is that this makes the resource larger than | |
6562 | * the hardware BAR, which may break drivers that compute things | |
6563 | * based on the resource size, e.g., to find registers at a | |
6564 | * fixed offset before the end of the BAR. | |
6565 | * | |
6566 | * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and | |
6567 | * set r->start to the desired alignment. By itself this | |
6568 | * doesn't prevent other BARs being put inside the alignment | |
6569 | * region, but if we realign *every* resource of every device in | |
6570 | * the system, none of them will share an alignment region. | |
6571 | * | |
6572 | * When the user has requested alignment for only some devices via | |
6573 | * the "pci=resource_alignment" argument, "resize" is true and we | |
6574 | * use the first method. Otherwise we assume we're aligning all | |
6575 | * devices and we use the second. | |
0dde1c08 | 6576 | */ |
e3adec72 | 6577 | |
7506dc79 | 6578 | pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n", |
0dde1c08 | 6579 | bar, r, (unsigned long long)align); |
81a5e70e | 6580 | |
e3adec72 YX |
6581 | if (resize) { |
6582 | r->start = 0; | |
6583 | r->end = align - 1; | |
6584 | } else { | |
6585 | r->flags &= ~IORESOURCE_SIZEALIGN; | |
6586 | r->flags |= IORESOURCE_STARTALIGN; | |
6587 | r->start = align; | |
6588 | r->end = r->start + size - 1; | |
6589 | } | |
0dde1c08 | 6590 | r->flags |= IORESOURCE_UNSET; |
81a5e70e BH |
6591 | } |
6592 | ||
2069ecfb YL |
6593 | /* |
6594 | * This function disables memory decoding and releases memory resources | |
6595 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
6596 | * It also rounds up size to specified alignment. | |
6597 | * Later on, the kernel will assign page-aligned memory resource back | |
6598 | * to the device. | |
6599 | */ | |
6600 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
6601 | { | |
6602 | int i; | |
6603 | struct resource *r; | |
81a5e70e | 6604 | resource_size_t align; |
2069ecfb | 6605 | u16 command; |
e3adec72 | 6606 | bool resize = false; |
2069ecfb | 6607 | |
62d9a78f YX |
6608 | /* |
6609 | * VF BARs are read-only zero according to SR-IOV spec r1.1, sec | |
6610 | * 3.4.1.11. Their resources are allocated from the space | |
6611 | * described by the VF BARx register in the PF's SR-IOV capability. | |
6612 | * We can't influence their alignment here. | |
6613 | */ | |
6614 | if (dev->is_virtfn) | |
6615 | return; | |
6616 | ||
10c463a7 | 6617 | /* check if specified PCI is target device to reassign */ |
e3adec72 | 6618 | align = pci_specified_resource_alignment(dev, &resize); |
10c463a7 | 6619 | if (!align) |
2069ecfb YL |
6620 | return; |
6621 | ||
6622 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
6623 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
7506dc79 | 6624 | pci_warn(dev, "Can't reassign resources to host bridge\n"); |
2069ecfb YL |
6625 | return; |
6626 | } | |
6627 | ||
2069ecfb YL |
6628 | pci_read_config_word(dev, PCI_COMMAND, &command); |
6629 | command &= ~PCI_COMMAND_MEMORY; | |
6630 | pci_write_config_word(dev, PCI_COMMAND, command); | |
6631 | ||
81a5e70e | 6632 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
e3adec72 | 6633 | pci_request_resource_alignment(dev, i, align, resize); |
f0b99f70 | 6634 | |
81a5e70e BH |
6635 | /* |
6636 | * Need to disable bridge's resource window, | |
2069ecfb YL |
6637 | * to enable the kernel to reassign new resource |
6638 | * window later on. | |
6639 | */ | |
b2fb5cc5 | 6640 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { |
2069ecfb YL |
6641 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { |
6642 | r = &dev->resource[i]; | |
6643 | if (!(r->flags & IORESOURCE_MEM)) | |
6644 | continue; | |
bd064f0a | 6645 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
6646 | r->end = resource_size(r) - 1; |
6647 | r->start = 0; | |
6648 | } | |
6649 | pci_disable_bridge_window(dev); | |
6650 | } | |
6651 | } | |
6652 | ||
273b177c | 6653 | static ssize_t resource_alignment_show(struct bus_type *bus, char *buf) |
32a9a682 | 6654 | { |
70aaf61a | 6655 | size_t count = 0; |
32a9a682 | 6656 | |
32a9a682 | 6657 | spin_lock(&resource_alignment_lock); |
70aaf61a | 6658 | if (resource_alignment_param) |
381bd3fa | 6659 | count = sysfs_emit(buf, "%s\n", resource_alignment_param); |
32a9a682 | 6660 | spin_unlock(&resource_alignment_lock); |
32a9a682 | 6661 | |
32a9a682 | 6662 | return count; |
32a9a682 YS |
6663 | } |
6664 | ||
d61dfafc | 6665 | static ssize_t resource_alignment_store(struct bus_type *bus, |
32a9a682 YS |
6666 | const char *buf, size_t count) |
6667 | { | |
381bd3fa KW |
6668 | char *param, *old, *end; |
6669 | ||
6670 | if (count >= (PAGE_SIZE - 1)) | |
6671 | return -EINVAL; | |
273b177c | 6672 | |
381bd3fa | 6673 | param = kstrndup(buf, count, GFP_KERNEL); |
273b177c LG |
6674 | if (!param) |
6675 | return -ENOMEM; | |
6676 | ||
381bd3fa KW |
6677 | end = strchr(param, '\n'); |
6678 | if (end) | |
6679 | *end = '\0'; | |
6680 | ||
273b177c | 6681 | spin_lock(&resource_alignment_lock); |
381bd3fa KW |
6682 | old = resource_alignment_param; |
6683 | if (strlen(param)) { | |
6684 | resource_alignment_param = param; | |
6685 | } else { | |
6686 | kfree(param); | |
6687 | resource_alignment_param = NULL; | |
6688 | } | |
273b177c | 6689 | spin_unlock(&resource_alignment_lock); |
381bd3fa KW |
6690 | |
6691 | kfree(old); | |
6692 | ||
273b177c | 6693 | return count; |
32a9a682 YS |
6694 | } |
6695 | ||
d61dfafc | 6696 | static BUS_ATTR_RW(resource_alignment); |
32a9a682 YS |
6697 | |
6698 | static int __init pci_resource_alignment_sysfs_init(void) | |
6699 | { | |
6700 | return bus_create_file(&pci_bus_type, | |
6701 | &bus_attr_resource_alignment); | |
6702 | } | |
32a9a682 YS |
6703 | late_initcall(pci_resource_alignment_sysfs_init); |
6704 | ||
15856ad5 | 6705 | static void pci_no_domains(void) |
32a2eea7 JG |
6706 | { |
6707 | #ifdef CONFIG_PCI_DOMAINS | |
6708 | pci_domains_supported = 0; | |
6709 | #endif | |
6710 | } | |
6711 | ||
ae07b786 | 6712 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
41e5c0f8 LD |
6713 | static atomic_t __domain_nr = ATOMIC_INIT(-1); |
6714 | ||
ae07b786 | 6715 | static int pci_get_new_domain_nr(void) |
41e5c0f8 LD |
6716 | { |
6717 | return atomic_inc_return(&__domain_nr); | |
6718 | } | |
7c674700 | 6719 | |
1a4f93f7 | 6720 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
6721 | { |
6722 | static int use_dt_domains = -1; | |
54c6e2dd | 6723 | int domain = -1; |
7c674700 | 6724 | |
54c6e2dd KHC |
6725 | if (parent) |
6726 | domain = of_get_pci_domain_nr(parent->of_node); | |
74356add | 6727 | |
7c674700 LP |
6728 | /* |
6729 | * Check DT domain and use_dt_domains values. | |
6730 | * | |
6731 | * If DT domain property is valid (domain >= 0) and | |
6732 | * use_dt_domains != 0, the DT assignment is valid since this means | |
6733 | * we have not previously allocated a domain number by using | |
6734 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
6735 | * 1, to indicate that we have just assigned a domain number from | |
6736 | * DT. | |
6737 | * | |
6738 | * If DT domain property value is not valid (ie domain < 0), and we | |
6739 | * have not previously assigned a domain number from DT | |
6740 | * (use_dt_domains != 1) we should assign a domain number by | |
6741 | * using the: | |
6742 | * | |
6743 | * pci_get_new_domain_nr() | |
6744 | * | |
6745 | * API and update the use_dt_domains value to keep track of method we | |
6746 | * are using to assign domain numbers (use_dt_domains = 0). | |
6747 | * | |
6748 | * All other combinations imply we have a platform that is trying | |
6749 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
6750 | * which is a recipe for domain mishandling and it is prevented by | |
6751 | * invalidating the domain value (domain = -1) and printing a | |
6752 | * corresponding error. | |
6753 | */ | |
6754 | if (domain >= 0 && use_dt_domains) { | |
6755 | use_dt_domains = 1; | |
6756 | } else if (domain < 0 && use_dt_domains != 1) { | |
6757 | use_dt_domains = 0; | |
6758 | domain = pci_get_new_domain_nr(); | |
6759 | } else { | |
9df1c6ec SL |
6760 | if (parent) |
6761 | pr_err("Node %pOF has ", parent->of_node); | |
6762 | pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); | |
7c674700 LP |
6763 | domain = -1; |
6764 | } | |
6765 | ||
9c7cb891 | 6766 | return domain; |
7c674700 | 6767 | } |
1a4f93f7 TN |
6768 | |
6769 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
6770 | { | |
2ab51dde TN |
6771 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
6772 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
6773 | } |
6774 | #endif | |
41e5c0f8 | 6775 | |
0ef5f8f6 | 6776 | /** |
642c92da | 6777 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
6778 | * |
6779 | * Returns 1 if we can access PCI extended config space (offsets | |
6780 | * greater than 0xff). This is the default implementation. Architecture | |
6781 | * implementations can override this. | |
6782 | */ | |
642c92da | 6783 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
6784 | { |
6785 | return 1; | |
6786 | } | |
6787 | ||
2d1c8618 BH |
6788 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
6789 | { | |
6790 | } | |
6791 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
6792 | ||
ad04d31e | 6793 | static int __init pci_setup(char *str) |
1da177e4 LT |
6794 | { |
6795 | while (str) { | |
6796 | char *k = strchr(str, ','); | |
6797 | if (k) | |
6798 | *k++ = 0; | |
6799 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
6800 | if (!strcmp(str, "nomsi")) { |
6801 | pci_no_msi(); | |
cef74409 GK |
6802 | } else if (!strncmp(str, "noats", 5)) { |
6803 | pr_info("PCIe: ATS is disabled\n"); | |
6804 | pcie_ats_disabled = true; | |
7f785763 RD |
6805 | } else if (!strcmp(str, "noaer")) { |
6806 | pci_no_aer(); | |
11eb0e0e SK |
6807 | } else if (!strcmp(str, "earlydump")) { |
6808 | pci_early_dump = true; | |
b55438fd YL |
6809 | } else if (!strncmp(str, "realloc=", 8)) { |
6810 | pci_realloc_get_opt(str + 8); | |
f483d392 | 6811 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 6812 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
6813 | } else if (!strcmp(str, "nodomains")) { |
6814 | pci_no_domains(); | |
6748dcc2 RW |
6815 | } else if (!strncmp(str, "noari", 5)) { |
6816 | pcie_ari_disabled = true; | |
4516a618 AN |
6817 | } else if (!strncmp(str, "cbiosize=", 9)) { |
6818 | pci_cardbus_io_size = memparse(str + 9, &str); | |
6819 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
6820 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 | 6821 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
70aaf61a | 6822 | resource_alignment_param = str + 19; |
43c16408 AP |
6823 | } else if (!strncmp(str, "ecrc=", 5)) { |
6824 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
6825 | } else if (!strncmp(str, "hpiosize=", 9)) { |
6826 | pci_hotplug_io_size = memparse(str + 9, &str); | |
d7b8a217 NJ |
6827 | } else if (!strncmp(str, "hpmmiosize=", 11)) { |
6828 | pci_hotplug_mmio_size = memparse(str + 11, &str); | |
6829 | } else if (!strncmp(str, "hpmmioprefsize=", 15)) { | |
6830 | pci_hotplug_mmio_pref_size = memparse(str + 15, &str); | |
28760489 | 6831 | } else if (!strncmp(str, "hpmemsize=", 10)) { |
d7b8a217 NJ |
6832 | pci_hotplug_mmio_size = memparse(str + 10, &str); |
6833 | pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size; | |
e16b4660 KB |
6834 | } else if (!strncmp(str, "hpbussize=", 10)) { |
6835 | pci_hotplug_bus_size = | |
6836 | simple_strtoul(str + 10, &str, 0); | |
6837 | if (pci_hotplug_bus_size > 0xff) | |
6838 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
6839 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
6840 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
6841 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
6842 | pcie_bus_config = PCIE_BUS_SAFE; | |
6843 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
6844 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
6845 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
6846 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
6847 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
6848 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
aaca43fd | 6849 | } else if (!strncmp(str, "disable_acs_redir=", 18)) { |
d5bc73f3 | 6850 | disable_acs_redir_param = str + 18; |
309e57df | 6851 | } else { |
25da8dba | 6852 | pr_err("PCI: Unknown option `%s'\n", str); |
309e57df | 6853 | } |
1da177e4 LT |
6854 | } |
6855 | str = k; | |
6856 | } | |
0637a70a | 6857 | return 0; |
1da177e4 | 6858 | } |
0637a70a | 6859 | early_param("pci", pci_setup); |
d5bc73f3 LG |
6860 | |
6861 | /* | |
70aaf61a LG |
6862 | * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized |
6863 | * in pci_setup(), above, to point to data in the __initdata section which | |
6864 | * will be freed after the init sequence is complete. We can't allocate memory | |
6865 | * in pci_setup() because some architectures do not have any memory allocation | |
6866 | * service available during an early_param() call. So we allocate memory and | |
6867 | * copy the variable here before the init section is freed. | |
6868 | * | |
d5bc73f3 LG |
6869 | */ |
6870 | static int __init pci_realloc_setup_params(void) | |
6871 | { | |
70aaf61a LG |
6872 | resource_alignment_param = kstrdup(resource_alignment_param, |
6873 | GFP_KERNEL); | |
d5bc73f3 LG |
6874 | disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL); |
6875 | ||
6876 | return 0; | |
6877 | } | |
6878 | pure_initcall(pci_realloc_setup_params); |