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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
229f5afd | 19 | #include <linux/log2.h> |
7d715a6c | 20 | #include <linux/pci-aspm.h> |
c300bd2f | 21 | #include <linux/pm_wakeup.h> |
8dd7f803 | 22 | #include <linux/interrupt.h> |
32a9a682 | 23 | #include <linux/device.h> |
b67ea761 | 24 | #include <linux/pm_runtime.h> |
608c3881 | 25 | #include <linux/pci_hotplug.h> |
284f5f9d | 26 | #include <asm-generic/pci-bridge.h> |
32a9a682 | 27 | #include <asm/setup.h> |
bc56b9e0 | 28 | #include "pci.h" |
1da177e4 | 29 | |
00240c38 AS |
30 | const char *pci_power_names[] = { |
31 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
32 | }; | |
33 | EXPORT_SYMBOL_GPL(pci_power_names); | |
34 | ||
93177a74 RW |
35 | int isa_dma_bridge_buggy; |
36 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
37 | ||
38 | int pci_pci_problems; | |
39 | EXPORT_SYMBOL(pci_pci_problems); | |
40 | ||
1ae861e6 RW |
41 | unsigned int pci_pm_d3_delay; |
42 | ||
df17e62e MG |
43 | static void pci_pme_list_scan(struct work_struct *work); |
44 | ||
45 | static LIST_HEAD(pci_pme_list); | |
46 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
47 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
48 | ||
49 | struct pci_pme_device { | |
50 | struct list_head list; | |
51 | struct pci_dev *dev; | |
52 | }; | |
53 | ||
54 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
55 | ||
1ae861e6 RW |
56 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
57 | { | |
58 | unsigned int delay = dev->d3_delay; | |
59 | ||
60 | if (delay < pci_pm_d3_delay) | |
61 | delay = pci_pm_d3_delay; | |
62 | ||
63 | msleep(delay); | |
64 | } | |
1da177e4 | 65 | |
32a2eea7 JG |
66 | #ifdef CONFIG_PCI_DOMAINS |
67 | int pci_domains_supported = 1; | |
68 | #endif | |
69 | ||
4516a618 AN |
70 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
71 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
72 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
73 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
74 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
75 | ||
28760489 EB |
76 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
77 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
78 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
79 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
80 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
81 | ||
5f39e670 | 82 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; |
b03e7495 | 83 | |
ac1aa47b JB |
84 | /* |
85 | * The default CLS is used if arch didn't set CLS explicitly and not | |
86 | * all pci devices agree on the same value. Arch can override either | |
87 | * the dfl or actual value as it sees fit. Don't forget this is | |
88 | * measured in 32-bit words, not bytes. | |
89 | */ | |
15856ad5 | 90 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
91 | u8 pci_cache_line_size; |
92 | ||
96c55900 MS |
93 | /* |
94 | * If we set up a device for bus mastering, we need to check the latency | |
95 | * timer as certain BIOSes forget to set it properly. | |
96 | */ | |
97 | unsigned int pcibios_max_latency = 255; | |
98 | ||
6748dcc2 RW |
99 | /* If set, the PCIe ARI capability will not be used. */ |
100 | static bool pcie_ari_disabled; | |
101 | ||
1da177e4 LT |
102 | /** |
103 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
104 | * @bus: pointer to PCI bus structure to search | |
105 | * | |
106 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
107 | * including the given PCI bus and its list of child PCI buses. | |
108 | */ | |
96bde06a | 109 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 | 110 | { |
94e6a9b9 | 111 | struct pci_bus *tmp; |
1da177e4 LT |
112 | unsigned char max, n; |
113 | ||
b918c62e | 114 | max = bus->busn_res.end; |
94e6a9b9 YW |
115 | list_for_each_entry(tmp, &bus->children, node) { |
116 | n = pci_bus_max_busnr(tmp); | |
1da177e4 LT |
117 | if(n > max) |
118 | max = n; | |
119 | } | |
120 | return max; | |
121 | } | |
b82db5ce | 122 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 123 | |
1684f5dd AM |
124 | #ifdef CONFIG_HAS_IOMEM |
125 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
126 | { | |
127 | /* | |
128 | * Make sure the BAR is actually a memory resource, not an IO resource | |
129 | */ | |
130 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
131 | WARN_ON(1); | |
132 | return NULL; | |
133 | } | |
134 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
135 | pci_resource_len(pdev, bar)); | |
136 | } | |
137 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
138 | #endif | |
139 | ||
687d5fe3 ME |
140 | #define PCI_FIND_CAP_TTL 48 |
141 | ||
142 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
143 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
144 | { |
145 | u8 id; | |
24a4e377 | 146 | |
687d5fe3 | 147 | while ((*ttl)--) { |
24a4e377 RD |
148 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
149 | if (pos < 0x40) | |
150 | break; | |
151 | pos &= ~3; | |
152 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
153 | &id); | |
154 | if (id == 0xff) | |
155 | break; | |
156 | if (id == cap) | |
157 | return pos; | |
158 | pos += PCI_CAP_LIST_NEXT; | |
159 | } | |
160 | return 0; | |
161 | } | |
162 | ||
687d5fe3 ME |
163 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
164 | u8 pos, int cap) | |
165 | { | |
166 | int ttl = PCI_FIND_CAP_TTL; | |
167 | ||
168 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
169 | } | |
170 | ||
24a4e377 RD |
171 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
172 | { | |
173 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
174 | pos + PCI_CAP_LIST_NEXT, cap); | |
175 | } | |
176 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
177 | ||
d3bac118 ME |
178 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
179 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
180 | { |
181 | u16 status; | |
1da177e4 LT |
182 | |
183 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
184 | if (!(status & PCI_STATUS_CAP_LIST)) | |
185 | return 0; | |
186 | ||
187 | switch (hdr_type) { | |
188 | case PCI_HEADER_TYPE_NORMAL: | |
189 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 190 | return PCI_CAPABILITY_LIST; |
1da177e4 | 191 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 192 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
193 | default: |
194 | return 0; | |
195 | } | |
d3bac118 ME |
196 | |
197 | return 0; | |
1da177e4 LT |
198 | } |
199 | ||
200 | /** | |
f7625980 | 201 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
202 | * @dev: PCI device to query |
203 | * @cap: capability code | |
204 | * | |
205 | * Tell if a device supports a given PCI capability. | |
206 | * Returns the address of the requested capability structure within the | |
207 | * device's PCI configuration space or 0 in case the device does not | |
208 | * support it. Possible values for @cap: | |
209 | * | |
f7625980 BH |
210 | * %PCI_CAP_ID_PM Power Management |
211 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
212 | * %PCI_CAP_ID_VPD Vital Product Data | |
213 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 214 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 215 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
216 | * %PCI_CAP_ID_PCIX PCI-X |
217 | * %PCI_CAP_ID_EXP PCI Express | |
218 | */ | |
219 | int pci_find_capability(struct pci_dev *dev, int cap) | |
220 | { | |
d3bac118 ME |
221 | int pos; |
222 | ||
223 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
224 | if (pos) | |
225 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
226 | ||
227 | return pos; | |
1da177e4 LT |
228 | } |
229 | ||
230 | /** | |
f7625980 | 231 | * pci_bus_find_capability - query for devices' capabilities |
1da177e4 LT |
232 | * @bus: the PCI bus to query |
233 | * @devfn: PCI device to query | |
234 | * @cap: capability code | |
235 | * | |
236 | * Like pci_find_capability() but works for pci devices that do not have a | |
f7625980 | 237 | * pci_dev structure set up yet. |
1da177e4 LT |
238 | * |
239 | * Returns the address of the requested capability structure within the | |
240 | * device's PCI configuration space or 0 in case the device does not | |
241 | * support it. | |
242 | */ | |
243 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
244 | { | |
d3bac118 | 245 | int pos; |
1da177e4 LT |
246 | u8 hdr_type; |
247 | ||
248 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
249 | ||
d3bac118 ME |
250 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
251 | if (pos) | |
252 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
253 | ||
254 | return pos; | |
1da177e4 LT |
255 | } |
256 | ||
257 | /** | |
44a9a36f | 258 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 259 | * @dev: PCI device to query |
44a9a36f | 260 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
261 | * @cap: capability code |
262 | * | |
44a9a36f | 263 | * Returns the address of the next matching extended capability structure |
1da177e4 | 264 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
265 | * not support it. Some capabilities can occur several times, e.g., the |
266 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 267 | */ |
44a9a36f | 268 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
269 | { |
270 | u32 header; | |
557848c3 ZY |
271 | int ttl; |
272 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 273 | |
557848c3 ZY |
274 | /* minimum 8 bytes per capability */ |
275 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
276 | ||
277 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
278 | return 0; |
279 | ||
44a9a36f BH |
280 | if (start) |
281 | pos = start; | |
282 | ||
1da177e4 LT |
283 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
284 | return 0; | |
285 | ||
286 | /* | |
287 | * If we have no capabilities, this is indicated by cap ID, | |
288 | * cap version and next pointer all being 0. | |
289 | */ | |
290 | if (header == 0) | |
291 | return 0; | |
292 | ||
293 | while (ttl-- > 0) { | |
44a9a36f | 294 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
295 | return pos; |
296 | ||
297 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 298 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
299 | break; |
300 | ||
301 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
302 | break; | |
303 | } | |
304 | ||
305 | return 0; | |
306 | } | |
44a9a36f BH |
307 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
308 | ||
309 | /** | |
310 | * pci_find_ext_capability - Find an extended capability | |
311 | * @dev: PCI device to query | |
312 | * @cap: capability code | |
313 | * | |
314 | * Returns the address of the requested extended capability structure | |
315 | * within the device's PCI configuration space or 0 if the device does | |
316 | * not support it. Possible values for @cap: | |
317 | * | |
318 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
319 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
320 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
321 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
322 | */ | |
323 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
324 | { | |
325 | return pci_find_next_ext_capability(dev, 0, cap); | |
326 | } | |
3a720d72 | 327 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 328 | |
687d5fe3 ME |
329 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
330 | { | |
331 | int rc, ttl = PCI_FIND_CAP_TTL; | |
332 | u8 cap, mask; | |
333 | ||
334 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
335 | mask = HT_3BIT_CAP_MASK; | |
336 | else | |
337 | mask = HT_5BIT_CAP_MASK; | |
338 | ||
339 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
340 | PCI_CAP_ID_HT, &ttl); | |
341 | while (pos) { | |
342 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
343 | if (rc != PCIBIOS_SUCCESSFUL) | |
344 | return 0; | |
345 | ||
346 | if ((cap & mask) == ht_cap) | |
347 | return pos; | |
348 | ||
47a4d5be BG |
349 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
350 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
351 | PCI_CAP_ID_HT, &ttl); |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | /** | |
357 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
358 | * @dev: PCI device to query | |
359 | * @pos: Position from which to continue searching | |
360 | * @ht_cap: Hypertransport capability code | |
361 | * | |
362 | * To be used in conjunction with pci_find_ht_capability() to search for | |
363 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
364 | * from pci_find_ht_capability(). | |
365 | * | |
366 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
367 | * steps to avoid an infinite loop. | |
368 | */ | |
369 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
370 | { | |
371 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
372 | } | |
373 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
374 | ||
375 | /** | |
376 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
377 | * @dev: PCI device to query | |
378 | * @ht_cap: Hypertransport capability code | |
379 | * | |
380 | * Tell if a device supports a given Hypertransport capability. | |
381 | * Returns an address within the device's PCI configuration space | |
382 | * or 0 in case the device does not support the request capability. | |
383 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
384 | * which has a Hypertransport capability matching @ht_cap. | |
385 | */ | |
386 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
387 | { | |
388 | int pos; | |
389 | ||
390 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
391 | if (pos) | |
392 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
393 | ||
394 | return pos; | |
395 | } | |
396 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
397 | ||
1da177e4 LT |
398 | /** |
399 | * pci_find_parent_resource - return resource region of parent bus of given region | |
400 | * @dev: PCI device structure contains resources to be searched | |
401 | * @res: child resource record for which parent is sought | |
402 | * | |
403 | * For given resource region of given device, return the resource | |
f44116ae | 404 | * region of parent bus the given region is contained in. |
1da177e4 LT |
405 | */ |
406 | struct resource * | |
407 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
408 | { | |
409 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 410 | struct resource *r; |
1da177e4 | 411 | int i; |
1da177e4 | 412 | |
89a74ecc | 413 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
414 | if (!r) |
415 | continue; | |
f44116ae BH |
416 | if (res->start && resource_contains(r, res)) { |
417 | ||
418 | /* | |
419 | * If the window is prefetchable but the BAR is | |
420 | * not, the allocator made a mistake. | |
421 | */ | |
422 | if (r->flags & IORESOURCE_PREFETCH && | |
423 | !(res->flags & IORESOURCE_PREFETCH)) | |
424 | return NULL; | |
425 | ||
426 | /* | |
427 | * If we're below a transparent bridge, there may | |
428 | * be both a positively-decoded aperture and a | |
429 | * subtractively-decoded region that contain the BAR. | |
430 | * We want the positively-decoded one, so this depends | |
431 | * on pci_bus_for_each_resource() giving us those | |
432 | * first. | |
433 | */ | |
434 | return r; | |
435 | } | |
1da177e4 | 436 | } |
f44116ae | 437 | return NULL; |
1da177e4 LT |
438 | } |
439 | ||
157e876f AW |
440 | /** |
441 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
442 | * @dev: the PCI device to operate on | |
443 | * @pos: config space offset of status word | |
444 | * @mask: mask of bit(s) to care about in status word | |
445 | * | |
446 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
447 | */ | |
448 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
449 | { | |
450 | int i; | |
451 | ||
452 | /* Wait for Transaction Pending bit clean */ | |
453 | for (i = 0; i < 4; i++) { | |
454 | u16 status; | |
455 | if (i) | |
456 | msleep((1 << (i - 1)) * 100); | |
457 | ||
458 | pci_read_config_word(dev, pos, &status); | |
459 | if (!(status & mask)) | |
460 | return 1; | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
064b53db JL |
466 | /** |
467 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
468 | * @dev: PCI device to have its BARs restored | |
469 | * | |
470 | * Restore the BAR values for a given device, so as to make it | |
471 | * accessible by its driver. | |
472 | */ | |
ad668599 | 473 | static void |
064b53db JL |
474 | pci_restore_bars(struct pci_dev *dev) |
475 | { | |
bc5f5a82 | 476 | int i; |
064b53db | 477 | |
bc5f5a82 | 478 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 479 | pci_update_resource(dev, i); |
064b53db JL |
480 | } |
481 | ||
961d9120 RW |
482 | static struct pci_platform_pm_ops *pci_platform_pm; |
483 | ||
484 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
485 | { | |
eb9d0fe4 | 486 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
d2e5f0c1 | 487 | || !ops->sleep_wake) |
961d9120 RW |
488 | return -EINVAL; |
489 | pci_platform_pm = ops; | |
490 | return 0; | |
491 | } | |
492 | ||
493 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
494 | { | |
495 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
496 | } | |
497 | ||
498 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
499 | pci_power_t t) | |
500 | { | |
501 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
502 | } | |
503 | ||
504 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
505 | { | |
506 | return pci_platform_pm ? | |
507 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
508 | } | |
8f7020d3 | 509 | |
eb9d0fe4 RW |
510 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
511 | { | |
512 | return pci_platform_pm ? | |
513 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
514 | } | |
515 | ||
b67ea761 RW |
516 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
517 | { | |
518 | return pci_platform_pm ? | |
519 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
520 | } | |
521 | ||
1da177e4 | 522 | /** |
44e4e66e RW |
523 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
524 | * given PCI device | |
525 | * @dev: PCI device to handle. | |
44e4e66e | 526 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 527 | * |
44e4e66e RW |
528 | * RETURN VALUE: |
529 | * -EINVAL if the requested state is invalid. | |
530 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
531 | * wrong version, or device doesn't support the requested state. | |
532 | * 0 if device already is in the requested state. | |
533 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 534 | */ |
f00a20ef | 535 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 536 | { |
337001b6 | 537 | u16 pmcsr; |
44e4e66e | 538 | bool need_restore = false; |
1da177e4 | 539 | |
4a865905 RW |
540 | /* Check if we're already there */ |
541 | if (dev->current_state == state) | |
542 | return 0; | |
543 | ||
337001b6 | 544 | if (!dev->pm_cap) |
cca03dec AL |
545 | return -EIO; |
546 | ||
44e4e66e RW |
547 | if (state < PCI_D0 || state > PCI_D3hot) |
548 | return -EINVAL; | |
549 | ||
1da177e4 | 550 | /* Validate current state: |
f7625980 | 551 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
552 | * to sleep if we're already in a low power state |
553 | */ | |
4a865905 | 554 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 555 | && dev->current_state > state) { |
80ccba11 BH |
556 | dev_err(&dev->dev, "invalid power transition " |
557 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 558 | return -EINVAL; |
44e4e66e | 559 | } |
1da177e4 | 560 | |
1da177e4 | 561 | /* check if this device supports the desired state */ |
337001b6 RW |
562 | if ((state == PCI_D1 && !dev->d1_support) |
563 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 564 | return -EIO; |
1da177e4 | 565 | |
337001b6 | 566 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 567 | |
32a36585 | 568 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
569 | * This doesn't affect PME_Status, disables PME_En, and |
570 | * sets PowerState to 0. | |
571 | */ | |
32a36585 | 572 | switch (dev->current_state) { |
d3535fbb JL |
573 | case PCI_D0: |
574 | case PCI_D1: | |
575 | case PCI_D2: | |
576 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
577 | pmcsr |= state; | |
578 | break; | |
f62795f1 RW |
579 | case PCI_D3hot: |
580 | case PCI_D3cold: | |
32a36585 JL |
581 | case PCI_UNKNOWN: /* Boot-up */ |
582 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 583 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 584 | need_restore = true; |
32a36585 | 585 | /* Fall-through: force to D0 */ |
32a36585 | 586 | default: |
d3535fbb | 587 | pmcsr = 0; |
32a36585 | 588 | break; |
1da177e4 LT |
589 | } |
590 | ||
591 | /* enter specified state */ | |
337001b6 | 592 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
593 | |
594 | /* Mandatory power management transition delays */ | |
595 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
596 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 597 | pci_dev_d3_sleep(dev); |
1da177e4 | 598 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 599 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 600 | |
e13cdbd7 RW |
601 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
602 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
603 | if (dev->current_state != state && printk_ratelimit()) | |
604 | dev_info(&dev->dev, "Refused to change power state, " | |
605 | "currently in D%d\n", dev->current_state); | |
064b53db | 606 | |
448bd857 HY |
607 | /* |
608 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
609 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
610 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
611 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
612 | * For example, at least some versions of the 3c905B and the | |
613 | * 3c556B exhibit this behaviour. | |
614 | * | |
615 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
616 | * devices in a D3hot state at boot. Consequently, we need to | |
617 | * restore at least the BARs so that the device will be | |
618 | * accessible to its driver. | |
619 | */ | |
620 | if (need_restore) | |
621 | pci_restore_bars(dev); | |
622 | ||
f00a20ef | 623 | if (dev->bus->self) |
7d715a6c SL |
624 | pcie_aspm_pm_state_change(dev->bus->self); |
625 | ||
1da177e4 LT |
626 | return 0; |
627 | } | |
628 | ||
44e4e66e RW |
629 | /** |
630 | * pci_update_current_state - Read PCI power state of given device from its | |
631 | * PCI PM registers and cache it | |
632 | * @dev: PCI device to handle. | |
f06fc0b6 | 633 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 634 | */ |
73410429 | 635 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 636 | { |
337001b6 | 637 | if (dev->pm_cap) { |
44e4e66e RW |
638 | u16 pmcsr; |
639 | ||
448bd857 HY |
640 | /* |
641 | * Configuration space is not accessible for device in | |
642 | * D3cold, so just keep or set D3cold for safety | |
643 | */ | |
644 | if (dev->current_state == PCI_D3cold) | |
645 | return; | |
646 | if (state == PCI_D3cold) { | |
647 | dev->current_state = PCI_D3cold; | |
648 | return; | |
649 | } | |
337001b6 | 650 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 651 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
652 | } else { |
653 | dev->current_state = state; | |
44e4e66e RW |
654 | } |
655 | } | |
656 | ||
db288c9c RW |
657 | /** |
658 | * pci_power_up - Put the given device into D0 forcibly | |
659 | * @dev: PCI device to power up | |
660 | */ | |
661 | void pci_power_up(struct pci_dev *dev) | |
662 | { | |
663 | if (platform_pci_power_manageable(dev)) | |
664 | platform_pci_set_power_state(dev, PCI_D0); | |
665 | ||
666 | pci_raw_set_power_state(dev, PCI_D0); | |
667 | pci_update_current_state(dev, PCI_D0); | |
668 | } | |
669 | ||
0e5dd46b RW |
670 | /** |
671 | * pci_platform_power_transition - Use platform to change device power state | |
672 | * @dev: PCI device to handle. | |
673 | * @state: State to put the device into. | |
674 | */ | |
675 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
676 | { | |
677 | int error; | |
678 | ||
679 | if (platform_pci_power_manageable(dev)) { | |
680 | error = platform_pci_set_power_state(dev, state); | |
681 | if (!error) | |
682 | pci_update_current_state(dev, state); | |
769ba721 | 683 | } else |
0e5dd46b | 684 | error = -ENODEV; |
769ba721 RW |
685 | |
686 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
687 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
688 | |
689 | return error; | |
690 | } | |
691 | ||
0b950f0f SH |
692 | /** |
693 | * pci_wakeup - Wake up a PCI device | |
694 | * @pci_dev: Device to handle. | |
695 | * @ign: ignored parameter | |
696 | */ | |
697 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
698 | { | |
699 | pci_wakeup_event(pci_dev); | |
700 | pm_request_resume(&pci_dev->dev); | |
701 | return 0; | |
702 | } | |
703 | ||
704 | /** | |
705 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
706 | * @bus: Top bus of the subtree to walk. | |
707 | */ | |
708 | static void pci_wakeup_bus(struct pci_bus *bus) | |
709 | { | |
710 | if (bus) | |
711 | pci_walk_bus(bus, pci_wakeup, NULL); | |
712 | } | |
713 | ||
0e5dd46b RW |
714 | /** |
715 | * __pci_start_power_transition - Start power transition of a PCI device | |
716 | * @dev: PCI device to handle. | |
717 | * @state: State to put the device into. | |
718 | */ | |
719 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
720 | { | |
448bd857 | 721 | if (state == PCI_D0) { |
0e5dd46b | 722 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
723 | /* |
724 | * Mandatory power management transition delays, see | |
725 | * PCI Express Base Specification Revision 2.0 Section | |
726 | * 6.6.1: Conventional Reset. Do not delay for | |
727 | * devices powered on/off by corresponding bridge, | |
728 | * because have already delayed for the bridge. | |
729 | */ | |
730 | if (dev->runtime_d3cold) { | |
731 | msleep(dev->d3cold_delay); | |
732 | /* | |
733 | * When powering on a bridge from D3cold, the | |
734 | * whole hierarchy may be powered on into | |
735 | * D0uninitialized state, resume them to give | |
736 | * them a chance to suspend again | |
737 | */ | |
738 | pci_wakeup_bus(dev->subordinate); | |
739 | } | |
740 | } | |
741 | } | |
742 | ||
743 | /** | |
744 | * __pci_dev_set_current_state - Set current state of a PCI device | |
745 | * @dev: Device to handle | |
746 | * @data: pointer to state to be set | |
747 | */ | |
748 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
749 | { | |
750 | pci_power_t state = *(pci_power_t *)data; | |
751 | ||
752 | dev->current_state = state; | |
753 | return 0; | |
754 | } | |
755 | ||
756 | /** | |
757 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
758 | * @bus: Top bus of the subtree to walk. | |
759 | * @state: state to be set | |
760 | */ | |
761 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
762 | { | |
763 | if (bus) | |
764 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
765 | } |
766 | ||
767 | /** | |
768 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
769 | * @dev: PCI device to handle. | |
770 | * @state: State to put the device into. | |
771 | * | |
772 | * This function should not be called directly by device drivers. | |
773 | */ | |
774 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
775 | { | |
448bd857 HY |
776 | int ret; |
777 | ||
db288c9c | 778 | if (state <= PCI_D0) |
448bd857 HY |
779 | return -EINVAL; |
780 | ret = pci_platform_power_transition(dev, state); | |
781 | /* Power off the bridge may power off the whole hierarchy */ | |
782 | if (!ret && state == PCI_D3cold) | |
783 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
784 | return ret; | |
0e5dd46b RW |
785 | } |
786 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
787 | ||
44e4e66e RW |
788 | /** |
789 | * pci_set_power_state - Set the power state of a PCI device | |
790 | * @dev: PCI device to handle. | |
791 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
792 | * | |
877d0310 | 793 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
794 | * the device's PCI PM registers. |
795 | * | |
796 | * RETURN VALUE: | |
797 | * -EINVAL if the requested state is invalid. | |
798 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
799 | * wrong version, or device doesn't support the requested state. | |
800 | * 0 if device already is in the requested state. | |
801 | * 0 if device's power state has been successfully changed. | |
802 | */ | |
803 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
804 | { | |
337001b6 | 805 | int error; |
44e4e66e RW |
806 | |
807 | /* bound the state we're entering */ | |
448bd857 HY |
808 | if (state > PCI_D3cold) |
809 | state = PCI_D3cold; | |
44e4e66e RW |
810 | else if (state < PCI_D0) |
811 | state = PCI_D0; | |
812 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
813 | /* | |
814 | * If the device or the parent bridge do not support PCI PM, | |
815 | * ignore the request if we're doing anything other than putting | |
816 | * it into D0 (which would only happen on boot). | |
817 | */ | |
818 | return 0; | |
819 | ||
db288c9c RW |
820 | /* Check if we're already there */ |
821 | if (dev->current_state == state) | |
822 | return 0; | |
823 | ||
0e5dd46b RW |
824 | __pci_start_power_transition(dev, state); |
825 | ||
979b1791 AC |
826 | /* This device is quirked not to be put into D3, so |
827 | don't put it in D3 */ | |
448bd857 | 828 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 829 | return 0; |
44e4e66e | 830 | |
448bd857 HY |
831 | /* |
832 | * To put device in D3cold, we put device into D3hot in native | |
833 | * way, then put device into D3cold with platform ops | |
834 | */ | |
835 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
836 | PCI_D3hot : state); | |
44e4e66e | 837 | |
0e5dd46b RW |
838 | if (!__pci_complete_power_transition(dev, state)) |
839 | error = 0; | |
1a680b7c NC |
840 | /* |
841 | * When aspm_policy is "powersave" this call ensures | |
842 | * that ASPM is configured. | |
843 | */ | |
844 | if (!error && dev->bus->self) | |
845 | pcie_aspm_powersave_config_link(dev->bus->self); | |
44e4e66e RW |
846 | |
847 | return error; | |
848 | } | |
849 | ||
1da177e4 LT |
850 | /** |
851 | * pci_choose_state - Choose the power state of a PCI device | |
852 | * @dev: PCI device to be suspended | |
853 | * @state: target sleep state for the whole system. This is the value | |
854 | * that is passed to suspend() function. | |
855 | * | |
856 | * Returns PCI power state suitable for given device and given system | |
857 | * message. | |
858 | */ | |
859 | ||
860 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
861 | { | |
ab826ca4 | 862 | pci_power_t ret; |
0f64474b | 863 | |
728cdb75 | 864 | if (!dev->pm_cap) |
1da177e4 LT |
865 | return PCI_D0; |
866 | ||
961d9120 RW |
867 | ret = platform_pci_choose_state(dev); |
868 | if (ret != PCI_POWER_ERROR) | |
869 | return ret; | |
ca078bae PM |
870 | |
871 | switch (state.event) { | |
872 | case PM_EVENT_ON: | |
873 | return PCI_D0; | |
874 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
875 | case PM_EVENT_PRETHAW: |
876 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 877 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 878 | case PM_EVENT_HIBERNATE: |
ca078bae | 879 | return PCI_D3hot; |
1da177e4 | 880 | default: |
80ccba11 BH |
881 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
882 | state.event); | |
1da177e4 LT |
883 | BUG(); |
884 | } | |
885 | return PCI_D0; | |
886 | } | |
887 | ||
888 | EXPORT_SYMBOL(pci_choose_state); | |
889 | ||
89858517 YZ |
890 | #define PCI_EXP_SAVE_REGS 7 |
891 | ||
1b6b8ce2 | 892 | |
fd0f7f73 AW |
893 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
894 | u16 cap, bool extended) | |
34a4876e YL |
895 | { |
896 | struct pci_cap_saved_state *tmp; | |
34a4876e | 897 | |
b67bfe0d | 898 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 899 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
900 | return tmp; |
901 | } | |
902 | return NULL; | |
903 | } | |
904 | ||
fd0f7f73 AW |
905 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
906 | { | |
907 | return _pci_find_saved_cap(dev, cap, false); | |
908 | } | |
909 | ||
910 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
911 | { | |
912 | return _pci_find_saved_cap(dev, cap, true); | |
913 | } | |
914 | ||
b56a5a23 MT |
915 | static int pci_save_pcie_state(struct pci_dev *dev) |
916 | { | |
59875ae4 | 917 | int i = 0; |
b56a5a23 MT |
918 | struct pci_cap_saved_state *save_state; |
919 | u16 *cap; | |
920 | ||
59875ae4 | 921 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
922 | return 0; |
923 | ||
9f35575d | 924 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 925 | if (!save_state) { |
e496b617 | 926 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
927 | return -ENOMEM; |
928 | } | |
63f4898a | 929 | |
59875ae4 JL |
930 | cap = (u16 *)&save_state->cap.data[0]; |
931 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
932 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
933 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
934 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
935 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
936 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
937 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 938 | |
b56a5a23 MT |
939 | return 0; |
940 | } | |
941 | ||
942 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
943 | { | |
59875ae4 | 944 | int i = 0; |
b56a5a23 MT |
945 | struct pci_cap_saved_state *save_state; |
946 | u16 *cap; | |
947 | ||
948 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 949 | if (!save_state) |
9cb604ed MS |
950 | return; |
951 | ||
59875ae4 JL |
952 | cap = (u16 *)&save_state->cap.data[0]; |
953 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
954 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
955 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
956 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
957 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
958 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
959 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
960 | } |
961 | ||
cc692a5f SH |
962 | |
963 | static int pci_save_pcix_state(struct pci_dev *dev) | |
964 | { | |
63f4898a | 965 | int pos; |
cc692a5f | 966 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
967 | |
968 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
969 | if (pos <= 0) | |
970 | return 0; | |
971 | ||
f34303de | 972 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 973 | if (!save_state) { |
e496b617 | 974 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
975 | return -ENOMEM; |
976 | } | |
cc692a5f | 977 | |
24a4742f AW |
978 | pci_read_config_word(dev, pos + PCI_X_CMD, |
979 | (u16 *)save_state->cap.data); | |
63f4898a | 980 | |
cc692a5f SH |
981 | return 0; |
982 | } | |
983 | ||
984 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
985 | { | |
986 | int i = 0, pos; | |
987 | struct pci_cap_saved_state *save_state; | |
988 | u16 *cap; | |
989 | ||
990 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
991 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
992 | if (!save_state || pos <= 0) | |
993 | return; | |
24a4742f | 994 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
995 | |
996 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
997 | } |
998 | ||
999 | ||
1da177e4 LT |
1000 | /** |
1001 | * pci_save_state - save the PCI configuration space of a device before suspending | |
1002 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
1003 | */ |
1004 | int | |
1005 | pci_save_state(struct pci_dev *dev) | |
1006 | { | |
1007 | int i; | |
1008 | /* XXX: 100% dword access ok here? */ | |
1009 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1010 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1011 | dev->state_saved = true; |
b56a5a23 MT |
1012 | if ((i = pci_save_pcie_state(dev)) != 0) |
1013 | return i; | |
cc692a5f SH |
1014 | if ((i = pci_save_pcix_state(dev)) != 0) |
1015 | return i; | |
425c1b22 AW |
1016 | if ((i = pci_save_vc_state(dev)) != 0) |
1017 | return i; | |
1da177e4 LT |
1018 | return 0; |
1019 | } | |
1020 | ||
ebfc5b80 RW |
1021 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
1022 | u32 saved_val, int retry) | |
1023 | { | |
1024 | u32 val; | |
1025 | ||
1026 | pci_read_config_dword(pdev, offset, &val); | |
1027 | if (val == saved_val) | |
1028 | return; | |
1029 | ||
1030 | for (;;) { | |
1031 | dev_dbg(&pdev->dev, "restoring config space at offset " | |
1032 | "%#x (was %#x, writing %#x)\n", offset, val, saved_val); | |
1033 | pci_write_config_dword(pdev, offset, saved_val); | |
1034 | if (retry-- <= 0) | |
1035 | return; | |
1036 | ||
1037 | pci_read_config_dword(pdev, offset, &val); | |
1038 | if (val == saved_val) | |
1039 | return; | |
1040 | ||
1041 | mdelay(1); | |
1042 | } | |
1043 | } | |
1044 | ||
a6cb9ee7 RW |
1045 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
1046 | int start, int end, int retry) | |
ebfc5b80 RW |
1047 | { |
1048 | int index; | |
1049 | ||
1050 | for (index = end; index >= start; index--) | |
1051 | pci_restore_config_dword(pdev, 4 * index, | |
1052 | pdev->saved_config_space[index], | |
1053 | retry); | |
1054 | } | |
1055 | ||
a6cb9ee7 RW |
1056 | static void pci_restore_config_space(struct pci_dev *pdev) |
1057 | { | |
1058 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
1059 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
1060 | /* Restore BARs before the command register. */ | |
1061 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
1062 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
1063 | } else { | |
1064 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
1065 | } | |
1066 | } | |
1067 | ||
f7625980 | 1068 | /** |
1da177e4 LT |
1069 | * pci_restore_state - Restore the saved state of a PCI device |
1070 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1071 | */ |
1d3c16a8 | 1072 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1073 | { |
c82f63e4 | 1074 | if (!dev->state_saved) |
1d3c16a8 | 1075 | return; |
4b77b0a2 | 1076 | |
b56a5a23 MT |
1077 | /* PCI Express register must be restored first */ |
1078 | pci_restore_pcie_state(dev); | |
1900ca13 | 1079 | pci_restore_ats_state(dev); |
425c1b22 | 1080 | pci_restore_vc_state(dev); |
b56a5a23 | 1081 | |
a6cb9ee7 | 1082 | pci_restore_config_space(dev); |
ebfc5b80 | 1083 | |
cc692a5f | 1084 | pci_restore_pcix_state(dev); |
41017f0c | 1085 | pci_restore_msi_state(dev); |
8c5cdb6a | 1086 | pci_restore_iov_state(dev); |
8fed4b65 | 1087 | |
4b77b0a2 | 1088 | dev->state_saved = false; |
1da177e4 LT |
1089 | } |
1090 | ||
ffbdd3f7 AW |
1091 | struct pci_saved_state { |
1092 | u32 config_space[16]; | |
1093 | struct pci_cap_saved_data cap[0]; | |
1094 | }; | |
1095 | ||
1096 | /** | |
1097 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1098 | * the device saved state. | |
1099 | * @dev: PCI device that we're dealing with | |
1100 | * | |
f7625980 | 1101 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1102 | */ |
1103 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1104 | { | |
1105 | struct pci_saved_state *state; | |
1106 | struct pci_cap_saved_state *tmp; | |
1107 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1108 | size_t size; |
1109 | ||
1110 | if (!dev->state_saved) | |
1111 | return NULL; | |
1112 | ||
1113 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1114 | ||
b67bfe0d | 1115 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1116 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1117 | ||
1118 | state = kzalloc(size, GFP_KERNEL); | |
1119 | if (!state) | |
1120 | return NULL; | |
1121 | ||
1122 | memcpy(state->config_space, dev->saved_config_space, | |
1123 | sizeof(state->config_space)); | |
1124 | ||
1125 | cap = state->cap; | |
b67bfe0d | 1126 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1127 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1128 | memcpy(cap, &tmp->cap, len); | |
1129 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1130 | } | |
1131 | /* Empty cap_save terminates list */ | |
1132 | ||
1133 | return state; | |
1134 | } | |
1135 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1136 | ||
1137 | /** | |
1138 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1139 | * @dev: PCI device that we're dealing with | |
1140 | * @state: Saved state returned from pci_store_saved_state() | |
1141 | */ | |
0b950f0f SH |
1142 | static int pci_load_saved_state(struct pci_dev *dev, |
1143 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1144 | { |
1145 | struct pci_cap_saved_data *cap; | |
1146 | ||
1147 | dev->state_saved = false; | |
1148 | ||
1149 | if (!state) | |
1150 | return 0; | |
1151 | ||
1152 | memcpy(dev->saved_config_space, state->config_space, | |
1153 | sizeof(state->config_space)); | |
1154 | ||
1155 | cap = state->cap; | |
1156 | while (cap->size) { | |
1157 | struct pci_cap_saved_state *tmp; | |
1158 | ||
fd0f7f73 | 1159 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1160 | if (!tmp || tmp->cap.size != cap->size) |
1161 | return -EINVAL; | |
1162 | ||
1163 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1164 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1165 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1166 | } | |
1167 | ||
1168 | dev->state_saved = true; | |
1169 | return 0; | |
1170 | } | |
ffbdd3f7 AW |
1171 | |
1172 | /** | |
1173 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1174 | * and free the memory allocated for it. | |
1175 | * @dev: PCI device that we're dealing with | |
1176 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1177 | */ | |
1178 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1179 | struct pci_saved_state **state) | |
1180 | { | |
1181 | int ret = pci_load_saved_state(dev, *state); | |
1182 | kfree(*state); | |
1183 | *state = NULL; | |
1184 | return ret; | |
1185 | } | |
1186 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1187 | ||
8a9d5609 BH |
1188 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1189 | { | |
1190 | return pci_enable_resources(dev, bars); | |
1191 | } | |
1192 | ||
38cc1302 HS |
1193 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1194 | { | |
1195 | int err; | |
1e2571a7 BH |
1196 | u16 cmd; |
1197 | u8 pin; | |
38cc1302 HS |
1198 | |
1199 | err = pci_set_power_state(dev, PCI_D0); | |
1200 | if (err < 0 && err != -EIO) | |
1201 | return err; | |
1202 | err = pcibios_enable_device(dev, bars); | |
1203 | if (err < 0) | |
1204 | return err; | |
1205 | pci_fixup_device(pci_fixup_enable, dev); | |
1206 | ||
866d5417 BH |
1207 | if (dev->msi_enabled || dev->msix_enabled) |
1208 | return 0; | |
1209 | ||
1e2571a7 BH |
1210 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1211 | if (pin) { | |
1212 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1213 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1214 | pci_write_config_word(dev, PCI_COMMAND, | |
1215 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1216 | } | |
1217 | ||
38cc1302 HS |
1218 | return 0; |
1219 | } | |
1220 | ||
1221 | /** | |
0b62e13b | 1222 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1223 | * @dev: PCI device to be resumed |
1224 | * | |
1225 | * Note this function is a backend of pci_default_resume and is not supposed | |
1226 | * to be called by normal code, write proper resume handler and use it instead. | |
1227 | */ | |
0b62e13b | 1228 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1229 | { |
296ccb08 | 1230 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1231 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1232 | return 0; | |
1233 | } | |
1234 | ||
928bea96 YL |
1235 | static void pci_enable_bridge(struct pci_dev *dev) |
1236 | { | |
79272138 | 1237 | struct pci_dev *bridge; |
928bea96 YL |
1238 | int retval; |
1239 | ||
79272138 BH |
1240 | bridge = pci_upstream_bridge(dev); |
1241 | if (bridge) | |
1242 | pci_enable_bridge(bridge); | |
928bea96 | 1243 | |
cf3e1feb | 1244 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1245 | if (!dev->is_busmaster) |
cf3e1feb | 1246 | pci_set_master(dev); |
928bea96 | 1247 | return; |
cf3e1feb YL |
1248 | } |
1249 | ||
928bea96 YL |
1250 | retval = pci_enable_device(dev); |
1251 | if (retval) | |
1252 | dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", | |
1253 | retval); | |
1254 | pci_set_master(dev); | |
1255 | } | |
1256 | ||
b4b4fbba | 1257 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1258 | { |
79272138 | 1259 | struct pci_dev *bridge; |
1da177e4 | 1260 | int err; |
b718989d | 1261 | int i, bars = 0; |
1da177e4 | 1262 | |
97c145f7 JB |
1263 | /* |
1264 | * Power state could be unknown at this point, either due to a fresh | |
1265 | * boot or a device removal call. So get the current power state | |
1266 | * so that things like MSI message writing will behave as expected | |
1267 | * (e.g. if the device really is in D0 at enable time). | |
1268 | */ | |
1269 | if (dev->pm_cap) { | |
1270 | u16 pmcsr; | |
1271 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1272 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1273 | } | |
1274 | ||
cc7ba39b | 1275 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1276 | return 0; /* already enabled */ |
1277 | ||
79272138 BH |
1278 | bridge = pci_upstream_bridge(dev); |
1279 | if (bridge) | |
1280 | pci_enable_bridge(bridge); | |
928bea96 | 1281 | |
497f16f2 YL |
1282 | /* only skip sriov related */ |
1283 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1284 | if (dev->resource[i].flags & flags) | |
1285 | bars |= (1 << i); | |
1286 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1287 | if (dev->resource[i].flags & flags) |
1288 | bars |= (1 << i); | |
1289 | ||
38cc1302 | 1290 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1291 | if (err < 0) |
38cc1302 | 1292 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1293 | return err; |
1da177e4 LT |
1294 | } |
1295 | ||
b718989d BH |
1296 | /** |
1297 | * pci_enable_device_io - Initialize a device for use with IO space | |
1298 | * @dev: PCI device to be initialized | |
1299 | * | |
1300 | * Initialize device before it's used by a driver. Ask low-level code | |
1301 | * to enable I/O resources. Wake up the device if it was suspended. | |
1302 | * Beware, this function can fail. | |
1303 | */ | |
1304 | int pci_enable_device_io(struct pci_dev *dev) | |
1305 | { | |
b4b4fbba | 1306 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d BH |
1307 | } |
1308 | ||
1309 | /** | |
1310 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1311 | * @dev: PCI device to be initialized | |
1312 | * | |
1313 | * Initialize device before it's used by a driver. Ask low-level code | |
1314 | * to enable Memory resources. Wake up the device if it was suspended. | |
1315 | * Beware, this function can fail. | |
1316 | */ | |
1317 | int pci_enable_device_mem(struct pci_dev *dev) | |
1318 | { | |
b4b4fbba | 1319 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d BH |
1320 | } |
1321 | ||
bae94d02 IPG |
1322 | /** |
1323 | * pci_enable_device - Initialize device before it's used by a driver. | |
1324 | * @dev: PCI device to be initialized | |
1325 | * | |
1326 | * Initialize device before it's used by a driver. Ask low-level code | |
1327 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1328 | * Beware, this function can fail. | |
1329 | * | |
1330 | * Note we don't actually enable the device many times if we call | |
1331 | * this function repeatedly (we just increment the count). | |
1332 | */ | |
1333 | int pci_enable_device(struct pci_dev *dev) | |
1334 | { | |
b4b4fbba | 1335 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
1336 | } |
1337 | ||
9ac7849e TH |
1338 | /* |
1339 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1340 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1341 | * there's no need to track it separately. pci_devres is initialized | |
1342 | * when a device is enabled using managed PCI device enable interface. | |
1343 | */ | |
1344 | struct pci_devres { | |
7f375f32 TH |
1345 | unsigned int enabled:1; |
1346 | unsigned int pinned:1; | |
9ac7849e TH |
1347 | unsigned int orig_intx:1; |
1348 | unsigned int restore_intx:1; | |
1349 | u32 region_mask; | |
1350 | }; | |
1351 | ||
1352 | static void pcim_release(struct device *gendev, void *res) | |
1353 | { | |
1354 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
1355 | struct pci_devres *this = res; | |
1356 | int i; | |
1357 | ||
1358 | if (dev->msi_enabled) | |
1359 | pci_disable_msi(dev); | |
1360 | if (dev->msix_enabled) | |
1361 | pci_disable_msix(dev); | |
1362 | ||
1363 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1364 | if (this->region_mask & (1 << i)) | |
1365 | pci_release_region(dev, i); | |
1366 | ||
1367 | if (this->restore_intx) | |
1368 | pci_intx(dev, this->orig_intx); | |
1369 | ||
7f375f32 | 1370 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1371 | pci_disable_device(dev); |
1372 | } | |
1373 | ||
1374 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
1375 | { | |
1376 | struct pci_devres *dr, *new_dr; | |
1377 | ||
1378 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1379 | if (dr) | |
1380 | return dr; | |
1381 | ||
1382 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1383 | if (!new_dr) | |
1384 | return NULL; | |
1385 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1386 | } | |
1387 | ||
1388 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
1389 | { | |
1390 | if (pci_is_managed(pdev)) | |
1391 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1392 | return NULL; | |
1393 | } | |
1394 | ||
1395 | /** | |
1396 | * pcim_enable_device - Managed pci_enable_device() | |
1397 | * @pdev: PCI device to be initialized | |
1398 | * | |
1399 | * Managed pci_enable_device(). | |
1400 | */ | |
1401 | int pcim_enable_device(struct pci_dev *pdev) | |
1402 | { | |
1403 | struct pci_devres *dr; | |
1404 | int rc; | |
1405 | ||
1406 | dr = get_pci_dr(pdev); | |
1407 | if (unlikely(!dr)) | |
1408 | return -ENOMEM; | |
b95d58ea TH |
1409 | if (dr->enabled) |
1410 | return 0; | |
9ac7849e TH |
1411 | |
1412 | rc = pci_enable_device(pdev); | |
1413 | if (!rc) { | |
1414 | pdev->is_managed = 1; | |
7f375f32 | 1415 | dr->enabled = 1; |
9ac7849e TH |
1416 | } |
1417 | return rc; | |
1418 | } | |
1419 | ||
1420 | /** | |
1421 | * pcim_pin_device - Pin managed PCI device | |
1422 | * @pdev: PCI device to pin | |
1423 | * | |
1424 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1425 | * driver detach. @pdev must have been enabled with | |
1426 | * pcim_enable_device(). | |
1427 | */ | |
1428 | void pcim_pin_device(struct pci_dev *pdev) | |
1429 | { | |
1430 | struct pci_devres *dr; | |
1431 | ||
1432 | dr = find_pci_dr(pdev); | |
7f375f32 | 1433 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1434 | if (dr) |
7f375f32 | 1435 | dr->pinned = 1; |
9ac7849e TH |
1436 | } |
1437 | ||
eca0d467 MG |
1438 | /* |
1439 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1440 | * @dev: the PCI device being added | |
1441 | * | |
1442 | * Permits the platform to provide architecture specific functionality when | |
1443 | * devices are added. This is the default implementation. Architecture | |
1444 | * implementations can override this. | |
1445 | */ | |
1446 | int __weak pcibios_add_device (struct pci_dev *dev) | |
1447 | { | |
1448 | return 0; | |
1449 | } | |
1450 | ||
6ae32c53 SO |
1451 | /** |
1452 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1453 | * @dev: the PCI device being released | |
1454 | * | |
1455 | * Permits the platform to provide architecture specific functionality when | |
1456 | * devices are released. This is the default implementation. Architecture | |
1457 | * implementations can override this. | |
1458 | */ | |
1459 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1460 | ||
1da177e4 LT |
1461 | /** |
1462 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1463 | * @dev: the PCI device to disable | |
1464 | * | |
1465 | * Disables architecture specific PCI resources for the device. This | |
1466 | * is the default implementation. Architecture implementations can | |
1467 | * override this. | |
1468 | */ | |
d6d88c83 | 1469 | void __weak pcibios_disable_device (struct pci_dev *dev) {} |
1da177e4 | 1470 | |
fa58d305 RW |
1471 | static void do_pci_disable_device(struct pci_dev *dev) |
1472 | { | |
1473 | u16 pci_command; | |
1474 | ||
1475 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1476 | if (pci_command & PCI_COMMAND_MASTER) { | |
1477 | pci_command &= ~PCI_COMMAND_MASTER; | |
1478 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1479 | } | |
1480 | ||
1481 | pcibios_disable_device(dev); | |
1482 | } | |
1483 | ||
1484 | /** | |
1485 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1486 | * @dev: PCI device to disable | |
1487 | * | |
1488 | * NOTE: This function is a backend of PCI power management routines and is | |
1489 | * not supposed to be called drivers. | |
1490 | */ | |
1491 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1492 | { | |
296ccb08 | 1493 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1494 | do_pci_disable_device(dev); |
1495 | } | |
1496 | ||
1da177e4 LT |
1497 | /** |
1498 | * pci_disable_device - Disable PCI device after use | |
1499 | * @dev: PCI device to be disabled | |
1500 | * | |
1501 | * Signal to the system that the PCI device is not in use by the system | |
1502 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1503 | * |
1504 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1505 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 LT |
1506 | */ |
1507 | void | |
1508 | pci_disable_device(struct pci_dev *dev) | |
1509 | { | |
9ac7849e | 1510 | struct pci_devres *dr; |
99dc804d | 1511 | |
9ac7849e TH |
1512 | dr = find_pci_dr(dev); |
1513 | if (dr) | |
7f375f32 | 1514 | dr->enabled = 0; |
9ac7849e | 1515 | |
fd6dceab KK |
1516 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1517 | "disabling already-disabled device"); | |
1518 | ||
cc7ba39b | 1519 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1520 | return; |
1521 | ||
fa58d305 | 1522 | do_pci_disable_device(dev); |
1da177e4 | 1523 | |
fa58d305 | 1524 | dev->is_busmaster = 0; |
1da177e4 LT |
1525 | } |
1526 | ||
f7bdd12d BK |
1527 | /** |
1528 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1529 | * @dev: the PCIe device reset |
f7bdd12d BK |
1530 | * @state: Reset state to enter into |
1531 | * | |
1532 | * | |
45e829ea | 1533 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1534 | * implementation. Architecture implementations can override this. |
1535 | */ | |
d6d88c83 BH |
1536 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1537 | enum pcie_reset_state state) | |
f7bdd12d BK |
1538 | { |
1539 | return -EINVAL; | |
1540 | } | |
1541 | ||
1542 | /** | |
1543 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1544 | * @dev: the PCIe device reset |
f7bdd12d BK |
1545 | * @state: Reset state to enter into |
1546 | * | |
1547 | * | |
1548 | * Sets the PCI reset state for the device. | |
1549 | */ | |
1550 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1551 | { | |
1552 | return pcibios_set_pcie_reset_state(dev, state); | |
1553 | } | |
1554 | ||
58ff4633 RW |
1555 | /** |
1556 | * pci_check_pme_status - Check if given device has generated PME. | |
1557 | * @dev: Device to check. | |
1558 | * | |
1559 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1560 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1561 | * 'false' otherwise. | |
1562 | */ | |
1563 | bool pci_check_pme_status(struct pci_dev *dev) | |
1564 | { | |
1565 | int pmcsr_pos; | |
1566 | u16 pmcsr; | |
1567 | bool ret = false; | |
1568 | ||
1569 | if (!dev->pm_cap) | |
1570 | return false; | |
1571 | ||
1572 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1573 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1574 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1575 | return false; | |
1576 | ||
1577 | /* Clear PME status. */ | |
1578 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1579 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1580 | /* Disable PME to avoid interrupt flood. */ | |
1581 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1582 | ret = true; | |
1583 | } | |
1584 | ||
1585 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1586 | ||
1587 | return ret; | |
1588 | } | |
1589 | ||
b67ea761 RW |
1590 | /** |
1591 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1592 | * @dev: Device to handle. | |
379021d5 | 1593 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1594 | * |
1595 | * Check if @dev has generated PME and queue a resume request for it in that | |
1596 | * case. | |
1597 | */ | |
379021d5 | 1598 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1599 | { |
379021d5 RW |
1600 | if (pme_poll_reset && dev->pme_poll) |
1601 | dev->pme_poll = false; | |
1602 | ||
c125e96f | 1603 | if (pci_check_pme_status(dev)) { |
c125e96f | 1604 | pci_wakeup_event(dev); |
0f953bf6 | 1605 | pm_request_resume(&dev->dev); |
c125e96f | 1606 | } |
b67ea761 RW |
1607 | return 0; |
1608 | } | |
1609 | ||
1610 | /** | |
1611 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1612 | * @bus: Top bus of the subtree to walk. | |
1613 | */ | |
1614 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1615 | { | |
1616 | if (bus) | |
379021d5 | 1617 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1618 | } |
1619 | ||
448bd857 | 1620 | |
eb9d0fe4 RW |
1621 | /** |
1622 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1623 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1624 | * @state: PCI state from which device will issue PME#. |
1625 | */ | |
e5899e1b | 1626 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1627 | { |
337001b6 | 1628 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1629 | return false; |
1630 | ||
337001b6 | 1631 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1632 | } |
1633 | ||
df17e62e MG |
1634 | static void pci_pme_list_scan(struct work_struct *work) |
1635 | { | |
379021d5 | 1636 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1637 | |
1638 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
1639 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1640 | if (pme_dev->dev->pme_poll) { | |
1641 | struct pci_dev *bridge; | |
1642 | ||
1643 | bridge = pme_dev->dev->bus->self; | |
1644 | /* | |
1645 | * If bridge is in low power state, the | |
1646 | * configuration space of subordinate devices | |
1647 | * may be not accessible | |
1648 | */ | |
1649 | if (bridge && bridge->current_state != PCI_D0) | |
1650 | continue; | |
1651 | pci_pme_wakeup(pme_dev->dev, NULL); | |
1652 | } else { | |
1653 | list_del(&pme_dev->list); | |
1654 | kfree(pme_dev); | |
379021d5 | 1655 | } |
df17e62e | 1656 | } |
ce300008 BH |
1657 | if (!list_empty(&pci_pme_list)) |
1658 | schedule_delayed_work(&pci_pme_work, | |
1659 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1660 | mutex_unlock(&pci_pme_list_mutex); |
1661 | } | |
1662 | ||
eb9d0fe4 RW |
1663 | /** |
1664 | * pci_pme_active - enable or disable PCI device's PME# function | |
1665 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1666 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1667 | * | |
1668 | * The caller must verify that the device is capable of generating PME# before | |
1669 | * calling this function with @enable equal to 'true'. | |
1670 | */ | |
5a6c9b60 | 1671 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1672 | { |
1673 | u16 pmcsr; | |
1674 | ||
ffaddbe8 | 1675 | if (!dev->pme_support) |
eb9d0fe4 RW |
1676 | return; |
1677 | ||
337001b6 | 1678 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1679 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1680 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1681 | if (!enable) | |
1682 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1683 | ||
337001b6 | 1684 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 | 1685 | |
6e965e0d HY |
1686 | /* |
1687 | * PCI (as opposed to PCIe) PME requires that the device have | |
1688 | * its PME# line hooked up correctly. Not all hardware vendors | |
1689 | * do this, so the PME never gets delivered and the device | |
1690 | * remains asleep. The easiest way around this is to | |
1691 | * periodically walk the list of suspended devices and check | |
1692 | * whether any have their PME flag set. The assumption is that | |
1693 | * we'll wake up often enough anyway that this won't be a huge | |
1694 | * hit, and the power savings from the devices will still be a | |
1695 | * win. | |
1696 | * | |
1697 | * Although PCIe uses in-band PME message instead of PME# line | |
1698 | * to report PME, PME does not work for some PCIe devices in | |
1699 | * reality. For example, there are devices that set their PME | |
1700 | * status bits, but don't really bother to send a PME message; | |
1701 | * there are PCI Express Root Ports that don't bother to | |
1702 | * trigger interrupts when they receive PME messages from the | |
1703 | * devices below. So PME poll is used for PCIe devices too. | |
1704 | */ | |
df17e62e | 1705 | |
379021d5 | 1706 | if (dev->pme_poll) { |
df17e62e MG |
1707 | struct pci_pme_device *pme_dev; |
1708 | if (enable) { | |
1709 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1710 | GFP_KERNEL); | |
0394cb19 BH |
1711 | if (!pme_dev) { |
1712 | dev_warn(&dev->dev, "can't enable PME#\n"); | |
1713 | return; | |
1714 | } | |
df17e62e MG |
1715 | pme_dev->dev = dev; |
1716 | mutex_lock(&pci_pme_list_mutex); | |
1717 | list_add(&pme_dev->list, &pci_pme_list); | |
1718 | if (list_is_singular(&pci_pme_list)) | |
1719 | schedule_delayed_work(&pci_pme_work, | |
1720 | msecs_to_jiffies(PME_TIMEOUT)); | |
1721 | mutex_unlock(&pci_pme_list_mutex); | |
1722 | } else { | |
1723 | mutex_lock(&pci_pme_list_mutex); | |
1724 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1725 | if (pme_dev->dev == dev) { | |
1726 | list_del(&pme_dev->list); | |
1727 | kfree(pme_dev); | |
1728 | break; | |
1729 | } | |
1730 | } | |
1731 | mutex_unlock(&pci_pme_list_mutex); | |
1732 | } | |
1733 | } | |
1734 | ||
85b8582d | 1735 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 RW |
1736 | } |
1737 | ||
1da177e4 | 1738 | /** |
6cbf8214 | 1739 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1740 | * @dev: PCI device affected |
1741 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1742 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1743 | * @enable: True to enable event generation; false to disable |
1744 | * | |
1745 | * This enables the device as a wakeup event source, or disables it. | |
1746 | * When such events involves platform-specific hooks, those hooks are | |
1747 | * called automatically by this routine. | |
1748 | * | |
1749 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1750 | * always require such platform hooks. |
075c1771 | 1751 | * |
eb9d0fe4 RW |
1752 | * RETURN VALUE: |
1753 | * 0 is returned on success | |
1754 | * -EINVAL is returned if device is not supposed to wake up the system | |
1755 | * Error code depending on the platform is returned if both the platform and | |
1756 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1757 | */ |
6cbf8214 RW |
1758 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1759 | bool runtime, bool enable) | |
1da177e4 | 1760 | { |
5bcc2fb4 | 1761 | int ret = 0; |
075c1771 | 1762 | |
6cbf8214 | 1763 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1764 | return -EINVAL; |
1da177e4 | 1765 | |
e80bb09d RW |
1766 | /* Don't do the same thing twice in a row for one device. */ |
1767 | if (!!enable == !!dev->wakeup_prepared) | |
1768 | return 0; | |
1769 | ||
eb9d0fe4 RW |
1770 | /* |
1771 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1772 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1773 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1774 | */ |
1da177e4 | 1775 | |
5bcc2fb4 RW |
1776 | if (enable) { |
1777 | int error; | |
1da177e4 | 1778 | |
5bcc2fb4 RW |
1779 | if (pci_pme_capable(dev, state)) |
1780 | pci_pme_active(dev, true); | |
1781 | else | |
1782 | ret = 1; | |
6cbf8214 RW |
1783 | error = runtime ? platform_pci_run_wake(dev, true) : |
1784 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1785 | if (ret) |
1786 | ret = error; | |
e80bb09d RW |
1787 | if (!ret) |
1788 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1789 | } else { |
6cbf8214 RW |
1790 | if (runtime) |
1791 | platform_pci_run_wake(dev, false); | |
1792 | else | |
1793 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1794 | pci_pme_active(dev, false); |
e80bb09d | 1795 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1796 | } |
1da177e4 | 1797 | |
5bcc2fb4 | 1798 | return ret; |
eb9d0fe4 | 1799 | } |
6cbf8214 | 1800 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1801 | |
0235c4fc RW |
1802 | /** |
1803 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1804 | * @dev: PCI device to prepare | |
1805 | * @enable: True to enable wake-up event generation; false to disable | |
1806 | * | |
1807 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1808 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1809 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1810 | * ordering constraints. | |
1811 | * | |
1812 | * This function only returns error code if the device is not capable of | |
1813 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1814 | * enable wake-up power for it. | |
1815 | */ | |
1816 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1817 | { | |
1818 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1819 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1820 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1821 | } | |
1822 | ||
404cc2d8 | 1823 | /** |
37139074 JB |
1824 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1825 | * @dev: PCI device | |
1826 | * | |
1827 | * Use underlying platform code to find a supported low power state for @dev. | |
1828 | * If the platform can't manage @dev, return the deepest state from which it | |
1829 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1830 | */ |
0b950f0f | 1831 | static pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1832 | { |
1833 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1834 | |
1835 | if (platform_pci_power_manageable(dev)) { | |
1836 | /* | |
1837 | * Call the platform to choose the target state of the device | |
1838 | * and enable wake-up from this state if supported. | |
1839 | */ | |
1840 | pci_power_t state = platform_pci_choose_state(dev); | |
1841 | ||
1842 | switch (state) { | |
1843 | case PCI_POWER_ERROR: | |
1844 | case PCI_UNKNOWN: | |
1845 | break; | |
1846 | case PCI_D1: | |
1847 | case PCI_D2: | |
1848 | if (pci_no_d1d2(dev)) | |
1849 | break; | |
1850 | default: | |
1851 | target_state = state; | |
404cc2d8 | 1852 | } |
d2abdf62 RW |
1853 | } else if (!dev->pm_cap) { |
1854 | target_state = PCI_D0; | |
404cc2d8 RW |
1855 | } else if (device_may_wakeup(&dev->dev)) { |
1856 | /* | |
1857 | * Find the deepest state from which the device can generate | |
1858 | * wake-up events, make it the target state and enable device | |
1859 | * to generate PME#. | |
1860 | */ | |
337001b6 RW |
1861 | if (dev->pme_support) { |
1862 | while (target_state | |
1863 | && !(dev->pme_support & (1 << target_state))) | |
1864 | target_state--; | |
404cc2d8 RW |
1865 | } |
1866 | } | |
1867 | ||
e5899e1b RW |
1868 | return target_state; |
1869 | } | |
1870 | ||
1871 | /** | |
1872 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1873 | * @dev: Device to handle. | |
1874 | * | |
1875 | * Choose the power state appropriate for the device depending on whether | |
1876 | * it can wake up the system and/or is power manageable by the platform | |
1877 | * (PCI_D3hot is the default) and put the device into that state. | |
1878 | */ | |
1879 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1880 | { | |
1881 | pci_power_t target_state = pci_target_state(dev); | |
1882 | int error; | |
1883 | ||
1884 | if (target_state == PCI_POWER_ERROR) | |
1885 | return -EIO; | |
1886 | ||
448bd857 HY |
1887 | /* D3cold during system suspend/hibernate is not supported */ |
1888 | if (target_state > PCI_D3hot) | |
1889 | target_state = PCI_D3hot; | |
1890 | ||
8efb8c76 | 1891 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1892 | |
404cc2d8 RW |
1893 | error = pci_set_power_state(dev, target_state); |
1894 | ||
1895 | if (error) | |
1896 | pci_enable_wake(dev, target_state, false); | |
1897 | ||
1898 | return error; | |
1899 | } | |
1900 | ||
1901 | /** | |
443bd1c4 | 1902 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1903 | * @dev: Device to handle. |
1904 | * | |
88393161 | 1905 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
1906 | */ |
1907 | int pci_back_from_sleep(struct pci_dev *dev) | |
1908 | { | |
1909 | pci_enable_wake(dev, PCI_D0, false); | |
1910 | return pci_set_power_state(dev, PCI_D0); | |
1911 | } | |
1912 | ||
6cbf8214 RW |
1913 | /** |
1914 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
1915 | * @dev: PCI device being suspended. | |
1916 | * | |
1917 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
1918 | * power state. | |
1919 | */ | |
1920 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
1921 | { | |
1922 | pci_power_t target_state = pci_target_state(dev); | |
1923 | int error; | |
1924 | ||
1925 | if (target_state == PCI_POWER_ERROR) | |
1926 | return -EIO; | |
1927 | ||
448bd857 HY |
1928 | dev->runtime_d3cold = target_state == PCI_D3cold; |
1929 | ||
6cbf8214 RW |
1930 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
1931 | ||
1932 | error = pci_set_power_state(dev, target_state); | |
1933 | ||
448bd857 | 1934 | if (error) { |
6cbf8214 | 1935 | __pci_enable_wake(dev, target_state, true, false); |
448bd857 HY |
1936 | dev->runtime_d3cold = false; |
1937 | } | |
6cbf8214 RW |
1938 | |
1939 | return error; | |
1940 | } | |
1941 | ||
b67ea761 RW |
1942 | /** |
1943 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
1944 | * @dev: Device to check. | |
1945 | * | |
f7625980 | 1946 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
1947 | * (through the platform or using the native PCIe PME) or if the device supports |
1948 | * PME and one of its upstream bridges can generate wake-up events. | |
1949 | */ | |
1950 | bool pci_dev_run_wake(struct pci_dev *dev) | |
1951 | { | |
1952 | struct pci_bus *bus = dev->bus; | |
1953 | ||
1954 | if (device_run_wake(&dev->dev)) | |
1955 | return true; | |
1956 | ||
1957 | if (!dev->pme_support) | |
1958 | return false; | |
1959 | ||
1960 | while (bus->parent) { | |
1961 | struct pci_dev *bridge = bus->self; | |
1962 | ||
1963 | if (device_run_wake(&bridge->dev)) | |
1964 | return true; | |
1965 | ||
1966 | bus = bus->parent; | |
1967 | } | |
1968 | ||
1969 | /* We have reached the root bus. */ | |
1970 | if (bus->bridge) | |
1971 | return device_run_wake(bus->bridge); | |
1972 | ||
1973 | return false; | |
1974 | } | |
1975 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
1976 | ||
b3c32c4f HY |
1977 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
1978 | { | |
1979 | struct device *dev = &pdev->dev; | |
1980 | struct device *parent = dev->parent; | |
1981 | ||
1982 | if (parent) | |
1983 | pm_runtime_get_sync(parent); | |
1984 | pm_runtime_get_noresume(dev); | |
1985 | /* | |
1986 | * pdev->current_state is set to PCI_D3cold during suspending, | |
1987 | * so wait until suspending completes | |
1988 | */ | |
1989 | pm_runtime_barrier(dev); | |
1990 | /* | |
1991 | * Only need to resume devices in D3cold, because config | |
1992 | * registers are still accessible for devices suspended but | |
1993 | * not in D3cold. | |
1994 | */ | |
1995 | if (pdev->current_state == PCI_D3cold) | |
1996 | pm_runtime_resume(dev); | |
1997 | } | |
1998 | ||
1999 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2000 | { | |
2001 | struct device *dev = &pdev->dev; | |
2002 | struct device *parent = dev->parent; | |
2003 | ||
2004 | pm_runtime_put(dev); | |
2005 | if (parent) | |
2006 | pm_runtime_put_sync(parent); | |
2007 | } | |
2008 | ||
eb9d0fe4 RW |
2009 | /** |
2010 | * pci_pm_init - Initialize PM functions of given PCI device | |
2011 | * @dev: PCI device to handle. | |
2012 | */ | |
2013 | void pci_pm_init(struct pci_dev *dev) | |
2014 | { | |
2015 | int pm; | |
2016 | u16 pmc; | |
1da177e4 | 2017 | |
bb910a70 | 2018 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2019 | pm_runtime_set_active(&dev->dev); |
2020 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2021 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2022 | dev->wakeup_prepared = false; |
bb910a70 | 2023 | |
337001b6 | 2024 | dev->pm_cap = 0; |
ffaddbe8 | 2025 | dev->pme_support = 0; |
337001b6 | 2026 | |
eb9d0fe4 RW |
2027 | /* find PCI PM capability in list */ |
2028 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2029 | if (!pm) | |
50246dd4 | 2030 | return; |
eb9d0fe4 RW |
2031 | /* Check device's ability to generate PME# */ |
2032 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2033 | |
eb9d0fe4 RW |
2034 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
2035 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
2036 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 2037 | return; |
eb9d0fe4 RW |
2038 | } |
2039 | ||
337001b6 | 2040 | dev->pm_cap = pm; |
1ae861e6 | 2041 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2042 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
4f9c1397 | 2043 | dev->d3cold_allowed = true; |
337001b6 RW |
2044 | |
2045 | dev->d1_support = false; | |
2046 | dev->d2_support = false; | |
2047 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2048 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2049 | dev->d1_support = true; |
c9ed77ee | 2050 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2051 | dev->d2_support = true; |
c9ed77ee BH |
2052 | |
2053 | if (dev->d1_support || dev->d2_support) | |
2054 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
2055 | dev->d1_support ? " D1" : "", |
2056 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2057 | } |
2058 | ||
2059 | pmc &= PCI_PM_CAP_PME_MASK; | |
2060 | if (pmc) { | |
10c3d71d BH |
2061 | dev_printk(KERN_DEBUG, &dev->dev, |
2062 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
2063 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2064 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2065 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2066 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2067 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2068 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2069 | dev->pme_poll = true; |
eb9d0fe4 RW |
2070 | /* |
2071 | * Make device's PM flags reflect the wake-up capability, but | |
2072 | * let the user space enable it to wake up the system as needed. | |
2073 | */ | |
2074 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2075 | /* Disable the PME# generation functionality */ |
337001b6 | 2076 | pci_pme_active(dev, false); |
eb9d0fe4 | 2077 | } |
1da177e4 LT |
2078 | } |
2079 | ||
34a4876e YL |
2080 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
2081 | struct pci_cap_saved_state *new_cap) | |
2082 | { | |
2083 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
2084 | } | |
2085 | ||
63f4898a | 2086 | /** |
fd0f7f73 AW |
2087 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
2088 | * capability registers | |
63f4898a RW |
2089 | * @dev: the PCI device |
2090 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 2091 | * @extended: Standard or Extended capability ID |
63f4898a RW |
2092 | * @size: requested size of the buffer |
2093 | */ | |
fd0f7f73 AW |
2094 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
2095 | bool extended, unsigned int size) | |
63f4898a RW |
2096 | { |
2097 | int pos; | |
2098 | struct pci_cap_saved_state *save_state; | |
2099 | ||
fd0f7f73 AW |
2100 | if (extended) |
2101 | pos = pci_find_ext_capability(dev, cap); | |
2102 | else | |
2103 | pos = pci_find_capability(dev, cap); | |
2104 | ||
63f4898a RW |
2105 | if (pos <= 0) |
2106 | return 0; | |
2107 | ||
2108 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2109 | if (!save_state) | |
2110 | return -ENOMEM; | |
2111 | ||
24a4742f | 2112 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 2113 | save_state->cap.cap_extended = extended; |
24a4742f | 2114 | save_state->cap.size = size; |
63f4898a RW |
2115 | pci_add_saved_cap(dev, save_state); |
2116 | ||
2117 | return 0; | |
2118 | } | |
2119 | ||
fd0f7f73 AW |
2120 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
2121 | { | |
2122 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
2123 | } | |
2124 | ||
2125 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
2126 | { | |
2127 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
2128 | } | |
2129 | ||
63f4898a RW |
2130 | /** |
2131 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2132 | * @dev: the PCI device | |
2133 | */ | |
2134 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2135 | { | |
2136 | int error; | |
2137 | ||
89858517 YZ |
2138 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2139 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2140 | if (error) |
2141 | dev_err(&dev->dev, | |
2142 | "unable to preallocate PCI Express save buffer\n"); | |
2143 | ||
2144 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2145 | if (error) | |
2146 | dev_err(&dev->dev, | |
2147 | "unable to preallocate PCI-X save buffer\n"); | |
425c1b22 AW |
2148 | |
2149 | pci_allocate_vc_save_buffers(dev); | |
63f4898a RW |
2150 | } |
2151 | ||
f796841e YL |
2152 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2153 | { | |
2154 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 2155 | struct hlist_node *n; |
f796841e | 2156 | |
b67bfe0d | 2157 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
2158 | kfree(tmp); |
2159 | } | |
2160 | ||
58c3a727 | 2161 | /** |
31ab2476 | 2162 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 2163 | * @dev: the PCI device |
b0cc6020 YW |
2164 | * |
2165 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
2166 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 2167 | */ |
31ab2476 | 2168 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 2169 | { |
58c3a727 | 2170 | u32 cap; |
8113587c | 2171 | struct pci_dev *bridge; |
58c3a727 | 2172 | |
6748dcc2 | 2173 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2174 | return; |
2175 | ||
8113587c | 2176 | bridge = dev->bus->self; |
cb97ae34 | 2177 | if (!bridge) |
8113587c ZY |
2178 | return; |
2179 | ||
59875ae4 | 2180 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2181 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2182 | return; | |
2183 | ||
b0cc6020 YW |
2184 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
2185 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
2186 | PCI_EXP_DEVCTL2_ARI); | |
2187 | bridge->ari_enabled = 1; | |
2188 | } else { | |
2189 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
2190 | PCI_EXP_DEVCTL2_ARI); | |
2191 | bridge->ari_enabled = 0; | |
2192 | } | |
58c3a727 YZ |
2193 | } |
2194 | ||
5d990b62 CW |
2195 | static int pci_acs_enable; |
2196 | ||
2197 | /** | |
2198 | * pci_request_acs - ask for ACS to be enabled if supported | |
2199 | */ | |
2200 | void pci_request_acs(void) | |
2201 | { | |
2202 | pci_acs_enable = 1; | |
2203 | } | |
2204 | ||
ae21ee65 | 2205 | /** |
2c744244 | 2206 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites |
ae21ee65 AK |
2207 | * @dev: the PCI device |
2208 | */ | |
2c744244 | 2209 | static int pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
2210 | { |
2211 | int pos; | |
2212 | u16 cap; | |
2213 | u16 ctrl; | |
2214 | ||
ae21ee65 AK |
2215 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2216 | if (!pos) | |
2c744244 | 2217 | return -ENODEV; |
ae21ee65 AK |
2218 | |
2219 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2220 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2221 | ||
2222 | /* Source Validation */ | |
2223 | ctrl |= (cap & PCI_ACS_SV); | |
2224 | ||
2225 | /* P2P Request Redirect */ | |
2226 | ctrl |= (cap & PCI_ACS_RR); | |
2227 | ||
2228 | /* P2P Completion Redirect */ | |
2229 | ctrl |= (cap & PCI_ACS_CR); | |
2230 | ||
2231 | /* Upstream Forwarding */ | |
2232 | ctrl |= (cap & PCI_ACS_UF); | |
2233 | ||
2234 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
2235 | |
2236 | return 0; | |
2237 | } | |
2238 | ||
2239 | /** | |
2240 | * pci_enable_acs - enable ACS if hardware support it | |
2241 | * @dev: the PCI device | |
2242 | */ | |
2243 | void pci_enable_acs(struct pci_dev *dev) | |
2244 | { | |
2245 | if (!pci_acs_enable) | |
2246 | return; | |
2247 | ||
2248 | if (!pci_std_enable_acs(dev)) | |
2249 | return; | |
2250 | ||
2251 | pci_dev_specific_enable_acs(dev); | |
ae21ee65 AK |
2252 | } |
2253 | ||
0a67119f AW |
2254 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
2255 | { | |
2256 | int pos; | |
83db7e0b | 2257 | u16 cap, ctrl; |
0a67119f AW |
2258 | |
2259 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2260 | if (!pos) | |
2261 | return false; | |
2262 | ||
83db7e0b AW |
2263 | /* |
2264 | * Except for egress control, capabilities are either required | |
2265 | * or only required if controllable. Features missing from the | |
2266 | * capability field can therefore be assumed as hard-wired enabled. | |
2267 | */ | |
2268 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
2269 | acs_flags &= (cap | PCI_ACS_EC); | |
2270 | ||
0a67119f AW |
2271 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
2272 | return (ctrl & acs_flags) == acs_flags; | |
2273 | } | |
2274 | ||
ad805758 AW |
2275 | /** |
2276 | * pci_acs_enabled - test ACS against required flags for a given device | |
2277 | * @pdev: device to test | |
2278 | * @acs_flags: required PCI ACS flags | |
2279 | * | |
2280 | * Return true if the device supports the provided flags. Automatically | |
2281 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
2282 | * |
2283 | * Note that this interface checks the effective ACS capabilities of the | |
2284 | * device rather than the actual capabilities. For instance, most single | |
2285 | * function endpoints are not required to support ACS because they have no | |
2286 | * opportunity for peer-to-peer access. We therefore return 'true' | |
2287 | * regardless of whether the device exposes an ACS capability. This makes | |
2288 | * it much easier for callers of this function to ignore the actual type | |
2289 | * or topology of the device when testing ACS support. | |
ad805758 AW |
2290 | */ |
2291 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2292 | { | |
0a67119f | 2293 | int ret; |
ad805758 AW |
2294 | |
2295 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2296 | if (ret >= 0) | |
2297 | return ret > 0; | |
2298 | ||
0a67119f AW |
2299 | /* |
2300 | * Conventional PCI and PCI-X devices never support ACS, either | |
2301 | * effectively or actually. The shared bus topology implies that | |
2302 | * any device on the bus can receive or snoop DMA. | |
2303 | */ | |
ad805758 AW |
2304 | if (!pci_is_pcie(pdev)) |
2305 | return false; | |
2306 | ||
0a67119f AW |
2307 | switch (pci_pcie_type(pdev)) { |
2308 | /* | |
2309 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 2310 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
2311 | * handle them as we would a non-PCIe device. |
2312 | */ | |
2313 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
2314 | /* | |
2315 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
2316 | * applicable... must never implement an ACS Extended Capability...". | |
2317 | * This seems arbitrary, but we take a conservative interpretation | |
2318 | * of this statement. | |
2319 | */ | |
2320 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
2321 | case PCI_EXP_TYPE_RC_EC: | |
2322 | return false; | |
2323 | /* | |
2324 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
2325 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
2326 | * regardless of whether they are single- or multi-function devices. | |
2327 | */ | |
2328 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2329 | case PCI_EXP_TYPE_ROOT_PORT: | |
2330 | return pci_acs_flags_enabled(pdev, acs_flags); | |
2331 | /* | |
2332 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
2333 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 2334 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
2335 | * device. The footnote for section 6.12 indicates the specific |
2336 | * PCIe types included here. | |
2337 | */ | |
2338 | case PCI_EXP_TYPE_ENDPOINT: | |
2339 | case PCI_EXP_TYPE_UPSTREAM: | |
2340 | case PCI_EXP_TYPE_LEG_END: | |
2341 | case PCI_EXP_TYPE_RC_END: | |
2342 | if (!pdev->multifunction) | |
2343 | break; | |
2344 | ||
0a67119f | 2345 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
2346 | } |
2347 | ||
0a67119f | 2348 | /* |
f7625980 | 2349 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
2350 | * to single function devices with the exception of downstream ports. |
2351 | */ | |
ad805758 AW |
2352 | return true; |
2353 | } | |
2354 | ||
2355 | /** | |
2356 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2357 | * @start: starting downstream device | |
2358 | * @end: ending upstream device or NULL to search to the root bus | |
2359 | * @acs_flags: required flags | |
2360 | * | |
2361 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2362 | * any step along the way does not support the required flags, return false. | |
2363 | */ | |
2364 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2365 | struct pci_dev *end, u16 acs_flags) | |
2366 | { | |
2367 | struct pci_dev *pdev, *parent = start; | |
2368 | ||
2369 | do { | |
2370 | pdev = parent; | |
2371 | ||
2372 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2373 | return false; | |
2374 | ||
2375 | if (pci_is_root_bus(pdev->bus)) | |
2376 | return (end == NULL); | |
2377 | ||
2378 | parent = pdev->bus->self; | |
2379 | } while (pdev != end); | |
2380 | ||
2381 | return true; | |
2382 | } | |
2383 | ||
57c2cf71 BH |
2384 | /** |
2385 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
2386 | * @dev: the PCI device | |
bb5c2de2 | 2387 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
2388 | * |
2389 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
2390 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
2391 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
2392 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
2393 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 2394 | */ |
3df425f3 | 2395 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 2396 | { |
46b952a3 MW |
2397 | int slot; |
2398 | ||
2399 | if (pci_ari_enabled(dev->bus)) | |
2400 | slot = 0; | |
2401 | else | |
2402 | slot = PCI_SLOT(dev->devfn); | |
2403 | ||
2404 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
2405 | } |
2406 | ||
1da177e4 LT |
2407 | int |
2408 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
2409 | { | |
2410 | u8 pin; | |
2411 | ||
514d207d | 2412 | pin = dev->pin; |
1da177e4 LT |
2413 | if (!pin) |
2414 | return -1; | |
878f2e50 | 2415 | |
8784fd4d | 2416 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 2417 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
2418 | dev = dev->bus->self; |
2419 | } | |
2420 | *bridge = dev; | |
2421 | return pin; | |
2422 | } | |
2423 | ||
68feac87 BH |
2424 | /** |
2425 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
2426 | * @dev: the PCI device | |
2427 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2428 | * | |
2429 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
2430 | * bridges all the way up to a PCI root bus. | |
2431 | */ | |
2432 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
2433 | { | |
2434 | u8 pin = *pinp; | |
2435 | ||
1eb39487 | 2436 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
2437 | pin = pci_swizzle_interrupt_pin(dev, pin); |
2438 | dev = dev->bus->self; | |
2439 | } | |
2440 | *pinp = pin; | |
2441 | return PCI_SLOT(dev->devfn); | |
2442 | } | |
2443 | ||
1da177e4 LT |
2444 | /** |
2445 | * pci_release_region - Release a PCI bar | |
2446 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
2447 | * @bar: BAR to release | |
2448 | * | |
2449 | * Releases the PCI I/O and memory resources previously reserved by a | |
2450 | * successful call to pci_request_region. Call this function only | |
2451 | * after all use of the PCI regions has ceased. | |
2452 | */ | |
2453 | void pci_release_region(struct pci_dev *pdev, int bar) | |
2454 | { | |
9ac7849e TH |
2455 | struct pci_devres *dr; |
2456 | ||
1da177e4 LT |
2457 | if (pci_resource_len(pdev, bar) == 0) |
2458 | return; | |
2459 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
2460 | release_region(pci_resource_start(pdev, bar), | |
2461 | pci_resource_len(pdev, bar)); | |
2462 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
2463 | release_mem_region(pci_resource_start(pdev, bar), | |
2464 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
2465 | |
2466 | dr = find_pci_dr(pdev); | |
2467 | if (dr) | |
2468 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
2469 | } |
2470 | ||
2471 | /** | |
f5ddcac4 | 2472 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
2473 | * @pdev: PCI device whose resources are to be reserved |
2474 | * @bar: BAR to be reserved | |
2475 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 2476 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
2477 | * |
2478 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2479 | * being reserved by owner @res_name. Do not access any | |
2480 | * address inside the PCI regions unless this call returns | |
2481 | * successfully. | |
2482 | * | |
f5ddcac4 RD |
2483 | * If @exclusive is set, then the region is marked so that userspace |
2484 | * is explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 2485 | * sysfs MMIO access. |
f5ddcac4 | 2486 | * |
1da177e4 LT |
2487 | * Returns 0 on success, or %EBUSY on error. A warning |
2488 | * message is also printed on failure. | |
2489 | */ | |
e8de1481 AV |
2490 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
2491 | int exclusive) | |
1da177e4 | 2492 | { |
9ac7849e TH |
2493 | struct pci_devres *dr; |
2494 | ||
1da177e4 LT |
2495 | if (pci_resource_len(pdev, bar) == 0) |
2496 | return 0; | |
f7625980 | 2497 | |
1da177e4 LT |
2498 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
2499 | if (!request_region(pci_resource_start(pdev, bar), | |
2500 | pci_resource_len(pdev, bar), res_name)) | |
2501 | goto err_out; | |
2502 | } | |
2503 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
e8de1481 AV |
2504 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
2505 | pci_resource_len(pdev, bar), res_name, | |
2506 | exclusive)) | |
1da177e4 LT |
2507 | goto err_out; |
2508 | } | |
9ac7849e TH |
2509 | |
2510 | dr = find_pci_dr(pdev); | |
2511 | if (dr) | |
2512 | dr->region_mask |= 1 << bar; | |
2513 | ||
1da177e4 LT |
2514 | return 0; |
2515 | ||
2516 | err_out: | |
c7dabef8 | 2517 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 2518 | &pdev->resource[bar]); |
1da177e4 LT |
2519 | return -EBUSY; |
2520 | } | |
2521 | ||
e8de1481 | 2522 | /** |
f5ddcac4 | 2523 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
2524 | * @pdev: PCI device whose resources are to be reserved |
2525 | * @bar: BAR to be reserved | |
f5ddcac4 | 2526 | * @res_name: Name to be associated with resource |
e8de1481 | 2527 | * |
f5ddcac4 | 2528 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
2529 | * being reserved by owner @res_name. Do not access any |
2530 | * address inside the PCI regions unless this call returns | |
2531 | * successfully. | |
2532 | * | |
2533 | * Returns 0 on success, or %EBUSY on error. A warning | |
2534 | * message is also printed on failure. | |
2535 | */ | |
2536 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
2537 | { | |
2538 | return __pci_request_region(pdev, bar, res_name, 0); | |
2539 | } | |
2540 | ||
2541 | /** | |
2542 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
2543 | * @pdev: PCI device whose resources are to be reserved | |
2544 | * @bar: BAR to be reserved | |
2545 | * @res_name: Name to be associated with resource. | |
2546 | * | |
2547 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2548 | * being reserved by owner @res_name. Do not access any | |
2549 | * address inside the PCI regions unless this call returns | |
2550 | * successfully. | |
2551 | * | |
2552 | * Returns 0 on success, or %EBUSY on error. A warning | |
2553 | * message is also printed on failure. | |
2554 | * | |
2555 | * The key difference that _exclusive makes it that userspace is | |
2556 | * explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 2557 | * sysfs. |
e8de1481 AV |
2558 | */ |
2559 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) | |
2560 | { | |
2561 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
2562 | } | |
c87deff7 HS |
2563 | /** |
2564 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
2565 | * @pdev: PCI device whose resources were previously reserved | |
2566 | * @bars: Bitmask of BARs to be released | |
2567 | * | |
2568 | * Release selected PCI I/O and memory resources previously reserved. | |
2569 | * Call this function only after all use of the PCI regions has ceased. | |
2570 | */ | |
2571 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
2572 | { | |
2573 | int i; | |
2574 | ||
2575 | for (i = 0; i < 6; i++) | |
2576 | if (bars & (1 << i)) | |
2577 | pci_release_region(pdev, i); | |
2578 | } | |
2579 | ||
9738abed | 2580 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
e8de1481 | 2581 | const char *res_name, int excl) |
c87deff7 HS |
2582 | { |
2583 | int i; | |
2584 | ||
2585 | for (i = 0; i < 6; i++) | |
2586 | if (bars & (1 << i)) | |
e8de1481 | 2587 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
2588 | goto err_out; |
2589 | return 0; | |
2590 | ||
2591 | err_out: | |
2592 | while(--i >= 0) | |
2593 | if (bars & (1 << i)) | |
2594 | pci_release_region(pdev, i); | |
2595 | ||
2596 | return -EBUSY; | |
2597 | } | |
1da177e4 | 2598 | |
e8de1481 AV |
2599 | |
2600 | /** | |
2601 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
2602 | * @pdev: PCI device whose resources are to be reserved | |
2603 | * @bars: Bitmask of BARs to be requested | |
2604 | * @res_name: Name to be associated with resource | |
2605 | */ | |
2606 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
2607 | const char *res_name) | |
2608 | { | |
2609 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
2610 | } | |
2611 | ||
2612 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, | |
2613 | int bars, const char *res_name) | |
2614 | { | |
2615 | return __pci_request_selected_regions(pdev, bars, res_name, | |
2616 | IORESOURCE_EXCLUSIVE); | |
2617 | } | |
2618 | ||
1da177e4 LT |
2619 | /** |
2620 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
2621 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
2622 | * | |
2623 | * Releases all PCI I/O and memory resources previously reserved by a | |
2624 | * successful call to pci_request_regions. Call this function only | |
2625 | * after all use of the PCI regions has ceased. | |
2626 | */ | |
2627 | ||
2628 | void pci_release_regions(struct pci_dev *pdev) | |
2629 | { | |
c87deff7 | 2630 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
2631 | } |
2632 | ||
2633 | /** | |
2634 | * pci_request_regions - Reserved PCI I/O and memory resources | |
2635 | * @pdev: PCI device whose resources are to be reserved | |
2636 | * @res_name: Name to be associated with resource. | |
2637 | * | |
2638 | * Mark all PCI regions associated with PCI device @pdev as | |
2639 | * being reserved by owner @res_name. Do not access any | |
2640 | * address inside the PCI regions unless this call returns | |
2641 | * successfully. | |
2642 | * | |
2643 | * Returns 0 on success, or %EBUSY on error. A warning | |
2644 | * message is also printed on failure. | |
2645 | */ | |
3c990e92 | 2646 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 2647 | { |
c87deff7 | 2648 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
2649 | } |
2650 | ||
e8de1481 AV |
2651 | /** |
2652 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
2653 | * @pdev: PCI device whose resources are to be reserved | |
2654 | * @res_name: Name to be associated with resource. | |
2655 | * | |
2656 | * Mark all PCI regions associated with PCI device @pdev as | |
2657 | * being reserved by owner @res_name. Do not access any | |
2658 | * address inside the PCI regions unless this call returns | |
2659 | * successfully. | |
2660 | * | |
2661 | * pci_request_regions_exclusive() will mark the region so that | |
f7625980 | 2662 | * /dev/mem and the sysfs MMIO access will not be allowed. |
e8de1481 AV |
2663 | * |
2664 | * Returns 0 on success, or %EBUSY on error. A warning | |
2665 | * message is also printed on failure. | |
2666 | */ | |
2667 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
2668 | { | |
2669 | return pci_request_selected_regions_exclusive(pdev, | |
2670 | ((1 << 6) - 1), res_name); | |
2671 | } | |
2672 | ||
6a479079 BH |
2673 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
2674 | { | |
2675 | u16 old_cmd, cmd; | |
2676 | ||
2677 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
2678 | if (enable) | |
2679 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
2680 | else | |
2681 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
2682 | if (cmd != old_cmd) { | |
2683 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
2684 | enable ? "enabling" : "disabling"); | |
2685 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2686 | } | |
2687 | dev->is_busmaster = enable; | |
2688 | } | |
e8de1481 | 2689 | |
2b6f2c35 MS |
2690 | /** |
2691 | * pcibios_setup - process "pci=" kernel boot arguments | |
2692 | * @str: string used to pass in "pci=" kernel boot arguments | |
2693 | * | |
2694 | * Process kernel boot arguments. This is the default implementation. | |
2695 | * Architecture specific implementations can override this as necessary. | |
2696 | */ | |
2697 | char * __weak __init pcibios_setup(char *str) | |
2698 | { | |
2699 | return str; | |
2700 | } | |
2701 | ||
96c55900 MS |
2702 | /** |
2703 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
2704 | * @dev: the PCI device to enable | |
2705 | * | |
2706 | * Enables PCI bus-mastering for the device. This is the default | |
2707 | * implementation. Architecture specific implementations can override | |
2708 | * this if necessary. | |
2709 | */ | |
2710 | void __weak pcibios_set_master(struct pci_dev *dev) | |
2711 | { | |
2712 | u8 lat; | |
2713 | ||
f676678f MS |
2714 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
2715 | if (pci_is_pcie(dev)) | |
2716 | return; | |
2717 | ||
96c55900 MS |
2718 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
2719 | if (lat < 16) | |
2720 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
2721 | else if (lat > pcibios_max_latency) | |
2722 | lat = pcibios_max_latency; | |
2723 | else | |
2724 | return; | |
a006482b | 2725 | |
96c55900 MS |
2726 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
2727 | } | |
2728 | ||
1da177e4 LT |
2729 | /** |
2730 | * pci_set_master - enables bus-mastering for device dev | |
2731 | * @dev: the PCI device to enable | |
2732 | * | |
2733 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
2734 | * to do the needed arch specific settings. | |
2735 | */ | |
6a479079 | 2736 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 2737 | { |
6a479079 | 2738 | __pci_set_master(dev, true); |
1da177e4 LT |
2739 | pcibios_set_master(dev); |
2740 | } | |
2741 | ||
6a479079 BH |
2742 | /** |
2743 | * pci_clear_master - disables bus-mastering for device dev | |
2744 | * @dev: the PCI device to disable | |
2745 | */ | |
2746 | void pci_clear_master(struct pci_dev *dev) | |
2747 | { | |
2748 | __pci_set_master(dev, false); | |
2749 | } | |
2750 | ||
1da177e4 | 2751 | /** |
edb2d97e MW |
2752 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
2753 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 2754 | * |
edb2d97e MW |
2755 | * Helper function for pci_set_mwi. |
2756 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
2757 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
2758 | * | |
2759 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2760 | */ | |
15ea76d4 | 2761 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
2762 | { |
2763 | u8 cacheline_size; | |
2764 | ||
2765 | if (!pci_cache_line_size) | |
15ea76d4 | 2766 | return -EINVAL; |
1da177e4 LT |
2767 | |
2768 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
2769 | equal to or multiple of the right value. */ | |
2770 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2771 | if (cacheline_size >= pci_cache_line_size && | |
2772 | (cacheline_size % pci_cache_line_size) == 0) | |
2773 | return 0; | |
2774 | ||
2775 | /* Write the correct value. */ | |
2776 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
2777 | /* Read it back. */ | |
2778 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2779 | if (cacheline_size == pci_cache_line_size) | |
2780 | return 0; | |
2781 | ||
80ccba11 BH |
2782 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
2783 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
2784 | |
2785 | return -EINVAL; | |
2786 | } | |
15ea76d4 TH |
2787 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
2788 | ||
2789 | #ifdef PCI_DISABLE_MWI | |
2790 | int pci_set_mwi(struct pci_dev *dev) | |
2791 | { | |
2792 | return 0; | |
2793 | } | |
2794 | ||
2795 | int pci_try_set_mwi(struct pci_dev *dev) | |
2796 | { | |
2797 | return 0; | |
2798 | } | |
2799 | ||
2800 | void pci_clear_mwi(struct pci_dev *dev) | |
2801 | { | |
2802 | } | |
2803 | ||
2804 | #else | |
1da177e4 LT |
2805 | |
2806 | /** | |
2807 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
2808 | * @dev: the PCI device for which MWI is enabled | |
2809 | * | |
694625c0 | 2810 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
2811 | * |
2812 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2813 | */ | |
2814 | int | |
2815 | pci_set_mwi(struct pci_dev *dev) | |
2816 | { | |
2817 | int rc; | |
2818 | u16 cmd; | |
2819 | ||
edb2d97e | 2820 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
2821 | if (rc) |
2822 | return rc; | |
2823 | ||
2824 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2825 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 2826 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
2827 | cmd |= PCI_COMMAND_INVALIDATE; |
2828 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2829 | } | |
f7625980 | 2830 | |
1da177e4 LT |
2831 | return 0; |
2832 | } | |
2833 | ||
694625c0 RD |
2834 | /** |
2835 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
2836 | * @dev: the PCI device for which MWI is enabled | |
2837 | * | |
2838 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
2839 | * Callers are not required to check the return value. | |
2840 | * | |
2841 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2842 | */ | |
2843 | int pci_try_set_mwi(struct pci_dev *dev) | |
2844 | { | |
2845 | int rc = pci_set_mwi(dev); | |
2846 | return rc; | |
2847 | } | |
2848 | ||
1da177e4 LT |
2849 | /** |
2850 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
2851 | * @dev: the PCI device to disable | |
2852 | * | |
2853 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
2854 | */ | |
2855 | void | |
2856 | pci_clear_mwi(struct pci_dev *dev) | |
2857 | { | |
2858 | u16 cmd; | |
2859 | ||
2860 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2861 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
2862 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
2863 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2864 | } | |
2865 | } | |
edb2d97e | 2866 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 2867 | |
a04ce0ff BR |
2868 | /** |
2869 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
2870 | * @pdev: the PCI device to operate on |
2871 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
2872 | * |
2873 | * Enables/disables PCI INTx for device dev | |
2874 | */ | |
2875 | void | |
2876 | pci_intx(struct pci_dev *pdev, int enable) | |
2877 | { | |
2878 | u16 pci_command, new; | |
2879 | ||
2880 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
2881 | ||
2882 | if (enable) { | |
2883 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
2884 | } else { | |
2885 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
2886 | } | |
2887 | ||
2888 | if (new != pci_command) { | |
9ac7849e TH |
2889 | struct pci_devres *dr; |
2890 | ||
2fd9d74b | 2891 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
2892 | |
2893 | dr = find_pci_dr(pdev); | |
2894 | if (dr && !dr->restore_intx) { | |
2895 | dr->restore_intx = 1; | |
2896 | dr->orig_intx = !enable; | |
2897 | } | |
a04ce0ff BR |
2898 | } |
2899 | } | |
2900 | ||
a2e27787 JK |
2901 | /** |
2902 | * pci_intx_mask_supported - probe for INTx masking support | |
6e9292c5 | 2903 | * @dev: the PCI device to operate on |
a2e27787 JK |
2904 | * |
2905 | * Check if the device dev support INTx masking via the config space | |
2906 | * command word. | |
2907 | */ | |
2908 | bool pci_intx_mask_supported(struct pci_dev *dev) | |
2909 | { | |
2910 | bool mask_supported = false; | |
2911 | u16 orig, new; | |
2912 | ||
fbebb9fd BH |
2913 | if (dev->broken_intx_masking) |
2914 | return false; | |
2915 | ||
a2e27787 JK |
2916 | pci_cfg_access_lock(dev); |
2917 | ||
2918 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
2919 | pci_write_config_word(dev, PCI_COMMAND, | |
2920 | orig ^ PCI_COMMAND_INTX_DISABLE); | |
2921 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
2922 | ||
2923 | /* | |
2924 | * There's no way to protect against hardware bugs or detect them | |
2925 | * reliably, but as long as we know what the value should be, let's | |
2926 | * go ahead and check it. | |
2927 | */ | |
2928 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { | |
2929 | dev_err(&dev->dev, "Command register changed from " | |
2930 | "0x%x to 0x%x: driver or hardware bug?\n", orig, new); | |
2931 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { | |
2932 | mask_supported = true; | |
2933 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
2934 | } | |
2935 | ||
2936 | pci_cfg_access_unlock(dev); | |
2937 | return mask_supported; | |
2938 | } | |
2939 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); | |
2940 | ||
2941 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) | |
2942 | { | |
2943 | struct pci_bus *bus = dev->bus; | |
2944 | bool mask_updated = true; | |
2945 | u32 cmd_status_dword; | |
2946 | u16 origcmd, newcmd; | |
2947 | unsigned long flags; | |
2948 | bool irq_pending; | |
2949 | ||
2950 | /* | |
2951 | * We do a single dword read to retrieve both command and status. | |
2952 | * Document assumptions that make this possible. | |
2953 | */ | |
2954 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
2955 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
2956 | ||
2957 | raw_spin_lock_irqsave(&pci_lock, flags); | |
2958 | ||
2959 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
2960 | ||
2961 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
2962 | ||
2963 | /* | |
2964 | * Check interrupt status register to see whether our device | |
2965 | * triggered the interrupt (when masking) or the next IRQ is | |
2966 | * already pending (when unmasking). | |
2967 | */ | |
2968 | if (mask != irq_pending) { | |
2969 | mask_updated = false; | |
2970 | goto done; | |
2971 | } | |
2972 | ||
2973 | origcmd = cmd_status_dword; | |
2974 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
2975 | if (mask) | |
2976 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
2977 | if (newcmd != origcmd) | |
2978 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
2979 | ||
2980 | done: | |
2981 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
2982 | ||
2983 | return mask_updated; | |
2984 | } | |
2985 | ||
2986 | /** | |
2987 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 2988 | * @dev: the PCI device to operate on |
a2e27787 JK |
2989 | * |
2990 | * Check if the device dev has its INTx line asserted, mask it and | |
2991 | * return true in that case. False is returned if not interrupt was | |
2992 | * pending. | |
2993 | */ | |
2994 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
2995 | { | |
2996 | return pci_check_and_set_intx_mask(dev, true); | |
2997 | } | |
2998 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
2999 | ||
3000 | /** | |
ebd50b93 | 3001 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 3002 | * @dev: the PCI device to operate on |
a2e27787 JK |
3003 | * |
3004 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3005 | * and return true. False is returned and the mask remains active if | |
3006 | * there was still an interrupt pending. | |
3007 | */ | |
3008 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3009 | { | |
3010 | return pci_check_and_set_intx_mask(dev, false); | |
3011 | } | |
3012 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3013 | ||
f5f2b131 | 3014 | /** |
da27f4b3 | 3015 | * pci_msi_off - disables any MSI or MSI-X capabilities |
8d7d86e9 | 3016 | * @dev: the PCI device to operate on |
f5f2b131 | 3017 | * |
da27f4b3 BH |
3018 | * If you want to use MSI, see pci_enable_msi() and friends. |
3019 | * This is a lower-level primitive that allows us to disable | |
3020 | * MSI operation at the device level. | |
f5f2b131 EB |
3021 | */ |
3022 | void pci_msi_off(struct pci_dev *dev) | |
3023 | { | |
3024 | int pos; | |
3025 | u16 control; | |
3026 | ||
da27f4b3 BH |
3027 | /* |
3028 | * This looks like it could go in msi.c, but we need it even when | |
3029 | * CONFIG_PCI_MSI=n. For the same reason, we can't use | |
3030 | * dev->msi_cap or dev->msix_cap here. | |
3031 | */ | |
f5f2b131 EB |
3032 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
3033 | if (pos) { | |
3034 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
3035 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
3036 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
3037 | } | |
3038 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
3039 | if (pos) { | |
3040 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
3041 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
3042 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
3043 | } | |
3044 | } | |
b03214d5 | 3045 | EXPORT_SYMBOL_GPL(pci_msi_off); |
f5f2b131 | 3046 | |
4d57cdfa FT |
3047 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
3048 | { | |
3049 | return dma_set_max_seg_size(&dev->dev, size); | |
3050 | } | |
3051 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
4d57cdfa | 3052 | |
59fc67de FT |
3053 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
3054 | { | |
3055 | return dma_set_seg_boundary(&dev->dev, mask); | |
3056 | } | |
3057 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
59fc67de | 3058 | |
3775a209 CL |
3059 | /** |
3060 | * pci_wait_for_pending_transaction - waits for pending transaction | |
3061 | * @dev: the PCI device to operate on | |
3062 | * | |
3063 | * Return 0 if transaction is pending 1 otherwise. | |
3064 | */ | |
3065 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 3066 | { |
157e876f AW |
3067 | if (!pci_is_pcie(dev)) |
3068 | return 1; | |
8c1c699f | 3069 | |
157e876f | 3070 | return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND); |
3775a209 CL |
3071 | } |
3072 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
3073 | ||
3074 | static int pcie_flr(struct pci_dev *dev, int probe) | |
3075 | { | |
3076 | u32 cap; | |
3077 | ||
3078 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); | |
3079 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
3080 | return -ENOTTY; | |
3081 | ||
3082 | if (probe) | |
3083 | return 0; | |
3084 | ||
3085 | if (!pci_wait_for_pending_transaction(dev)) | |
3086 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); | |
8c1c699f | 3087 | |
59875ae4 | 3088 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
04b55c47 | 3089 | |
8c1c699f | 3090 | msleep(100); |
8dd7f803 | 3091 | |
8dd7f803 SY |
3092 | return 0; |
3093 | } | |
d91cdc74 | 3094 | |
8c1c699f | 3095 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3096 | { |
8c1c699f | 3097 | int pos; |
1ca88797 SY |
3098 | u8 cap; |
3099 | ||
8c1c699f YZ |
3100 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3101 | if (!pos) | |
1ca88797 | 3102 | return -ENOTTY; |
8c1c699f YZ |
3103 | |
3104 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
3105 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3106 | return -ENOTTY; | |
3107 | ||
3108 | if (probe) | |
3109 | return 0; | |
3110 | ||
1ca88797 | 3111 | /* Wait for Transaction Pending bit clean */ |
157e876f AW |
3112 | if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP)) |
3113 | goto clear; | |
5fe5db05 | 3114 | |
8c1c699f YZ |
3115 | dev_err(&dev->dev, "transaction is not cleared; " |
3116 | "proceeding with reset anyway\n"); | |
5fe5db05 | 3117 | |
8c1c699f YZ |
3118 | clear: |
3119 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | |
1ca88797 | 3120 | msleep(100); |
8c1c699f | 3121 | |
1ca88797 SY |
3122 | return 0; |
3123 | } | |
3124 | ||
83d74e03 RW |
3125 | /** |
3126 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3127 | * @dev: Device to reset. | |
3128 | * @probe: If set, only check if the device can be reset this way. | |
3129 | * | |
3130 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3131 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3132 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3133 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3134 | * | |
3135 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3136 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 3137 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
3138 | * Moreover, only devices in D0 can be reset by this function. |
3139 | */ | |
f85876ba | 3140 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3141 | { |
f85876ba YZ |
3142 | u16 csr; |
3143 | ||
3144 | if (!dev->pm_cap) | |
3145 | return -ENOTTY; | |
d91cdc74 | 3146 | |
f85876ba YZ |
3147 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
3148 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
3149 | return -ENOTTY; | |
d91cdc74 | 3150 | |
f85876ba YZ |
3151 | if (probe) |
3152 | return 0; | |
1ca88797 | 3153 | |
f85876ba YZ |
3154 | if (dev->current_state != PCI_D0) |
3155 | return -EINVAL; | |
3156 | ||
3157 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3158 | csr |= PCI_D3hot; | |
3159 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3160 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3161 | |
3162 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3163 | csr |= PCI_D0; | |
3164 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3165 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3166 | |
3167 | return 0; | |
3168 | } | |
3169 | ||
64e8674f AW |
3170 | /** |
3171 | * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. | |
3172 | * @dev: Bridge device | |
3173 | * | |
3174 | * Use the bridge control register to assert reset on the secondary bus. | |
3175 | * Devices on the secondary bus are left in power-on state. | |
3176 | */ | |
3177 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev) | |
c12ff1df YZ |
3178 | { |
3179 | u16 ctrl; | |
64e8674f AW |
3180 | |
3181 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
3182 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
3183 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3184 | /* |
3185 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 3186 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
3187 | */ |
3188 | msleep(2); | |
64e8674f AW |
3189 | |
3190 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
3191 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3192 | |
3193 | /* | |
3194 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
3195 | * Assuming a minimum 33MHz clock this results in a 1s | |
3196 | * delay before we can consider subordinate devices to | |
3197 | * be re-initialized. PCIe has some ways to shorten this, | |
3198 | * but we don't make use of them yet. | |
3199 | */ | |
3200 | ssleep(1); | |
64e8674f AW |
3201 | } |
3202 | EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); | |
3203 | ||
3204 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
3205 | { | |
c12ff1df YZ |
3206 | struct pci_dev *pdev; |
3207 | ||
654b75e0 | 3208 | if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) |
c12ff1df YZ |
3209 | return -ENOTTY; |
3210 | ||
3211 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3212 | if (pdev != dev) | |
3213 | return -ENOTTY; | |
3214 | ||
3215 | if (probe) | |
3216 | return 0; | |
3217 | ||
64e8674f | 3218 | pci_reset_bridge_secondary_bus(dev->bus->self); |
c12ff1df YZ |
3219 | |
3220 | return 0; | |
3221 | } | |
3222 | ||
608c3881 AW |
3223 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
3224 | { | |
3225 | int rc = -ENOTTY; | |
3226 | ||
3227 | if (!hotplug || !try_module_get(hotplug->ops->owner)) | |
3228 | return rc; | |
3229 | ||
3230 | if (hotplug->ops->reset_slot) | |
3231 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
3232 | ||
3233 | module_put(hotplug->ops->owner); | |
3234 | ||
3235 | return rc; | |
3236 | } | |
3237 | ||
3238 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
3239 | { | |
3240 | struct pci_dev *pdev; | |
3241 | ||
3242 | if (dev->subordinate || !dev->slot) | |
3243 | return -ENOTTY; | |
3244 | ||
3245 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3246 | if (pdev != dev && pdev->slot == dev->slot) | |
3247 | return -ENOTTY; | |
3248 | ||
3249 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
3250 | } | |
3251 | ||
977f857c | 3252 | static int __pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3253 | { |
8c1c699f YZ |
3254 | int rc; |
3255 | ||
3256 | might_sleep(); | |
3257 | ||
b9c3b266 DC |
3258 | rc = pci_dev_specific_reset(dev, probe); |
3259 | if (rc != -ENOTTY) | |
3260 | goto done; | |
3261 | ||
8c1c699f YZ |
3262 | rc = pcie_flr(dev, probe); |
3263 | if (rc != -ENOTTY) | |
3264 | goto done; | |
d91cdc74 | 3265 | |
8c1c699f | 3266 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
3267 | if (rc != -ENOTTY) |
3268 | goto done; | |
3269 | ||
3270 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
3271 | if (rc != -ENOTTY) |
3272 | goto done; | |
3273 | ||
608c3881 AW |
3274 | rc = pci_dev_reset_slot_function(dev, probe); |
3275 | if (rc != -ENOTTY) | |
3276 | goto done; | |
3277 | ||
c12ff1df | 3278 | rc = pci_parent_bus_reset(dev, probe); |
8c1c699f | 3279 | done: |
977f857c KRW |
3280 | return rc; |
3281 | } | |
3282 | ||
77cb985a AW |
3283 | static void pci_dev_lock(struct pci_dev *dev) |
3284 | { | |
3285 | pci_cfg_access_lock(dev); | |
3286 | /* block PM suspend, driver probe, etc. */ | |
3287 | device_lock(&dev->dev); | |
3288 | } | |
3289 | ||
61cf16d8 AW |
3290 | /* Return 1 on successful lock, 0 on contention */ |
3291 | static int pci_dev_trylock(struct pci_dev *dev) | |
3292 | { | |
3293 | if (pci_cfg_access_trylock(dev)) { | |
3294 | if (device_trylock(&dev->dev)) | |
3295 | return 1; | |
3296 | pci_cfg_access_unlock(dev); | |
3297 | } | |
3298 | ||
3299 | return 0; | |
3300 | } | |
3301 | ||
77cb985a AW |
3302 | static void pci_dev_unlock(struct pci_dev *dev) |
3303 | { | |
3304 | device_unlock(&dev->dev); | |
3305 | pci_cfg_access_unlock(dev); | |
3306 | } | |
3307 | ||
3308 | static void pci_dev_save_and_disable(struct pci_dev *dev) | |
3309 | { | |
a6cbaade AW |
3310 | /* |
3311 | * Wake-up device prior to save. PM registers default to D0 after | |
3312 | * reset and a simple register restore doesn't reliably return | |
3313 | * to a non-D0 state anyway. | |
3314 | */ | |
3315 | pci_set_power_state(dev, PCI_D0); | |
3316 | ||
77cb985a AW |
3317 | pci_save_state(dev); |
3318 | /* | |
3319 | * Disable the device by clearing the Command register, except for | |
3320 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
3321 | * BARs, but also prevents the device from being Bus Master, preventing | |
3322 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
3323 | * compliant devices, INTx-disable prevents legacy interrupts. | |
3324 | */ | |
3325 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
3326 | } | |
3327 | ||
3328 | static void pci_dev_restore(struct pci_dev *dev) | |
3329 | { | |
3330 | pci_restore_state(dev); | |
3331 | } | |
3332 | ||
977f857c KRW |
3333 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
3334 | { | |
3335 | int rc; | |
3336 | ||
77cb985a AW |
3337 | if (!probe) |
3338 | pci_dev_lock(dev); | |
977f857c KRW |
3339 | |
3340 | rc = __pci_dev_reset(dev, probe); | |
3341 | ||
77cb985a AW |
3342 | if (!probe) |
3343 | pci_dev_unlock(dev); | |
3344 | ||
8c1c699f | 3345 | return rc; |
d91cdc74 | 3346 | } |
d91cdc74 | 3347 | /** |
8c1c699f YZ |
3348 | * __pci_reset_function - reset a PCI device function |
3349 | * @dev: PCI device to reset | |
d91cdc74 SY |
3350 | * |
3351 | * Some devices allow an individual function to be reset without affecting | |
3352 | * other functions in the same device. The PCI device must be responsive | |
3353 | * to PCI config space in order to use this function. | |
3354 | * | |
3355 | * The device function is presumed to be unused when this function is called. | |
3356 | * Resetting the device will make the contents of PCI configuration space | |
3357 | * random, so any caller of this must be prepared to reinitialise the | |
3358 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3359 | * etc. | |
3360 | * | |
8c1c699f | 3361 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
3362 | * device doesn't support resetting a single function. |
3363 | */ | |
8c1c699f | 3364 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 3365 | { |
8c1c699f | 3366 | return pci_dev_reset(dev, 0); |
d91cdc74 | 3367 | } |
8c1c699f | 3368 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 3369 | |
6fbf9e7a KRW |
3370 | /** |
3371 | * __pci_reset_function_locked - reset a PCI device function while holding | |
3372 | * the @dev mutex lock. | |
3373 | * @dev: PCI device to reset | |
3374 | * | |
3375 | * Some devices allow an individual function to be reset without affecting | |
3376 | * other functions in the same device. The PCI device must be responsive | |
3377 | * to PCI config space in order to use this function. | |
3378 | * | |
3379 | * The device function is presumed to be unused and the caller is holding | |
3380 | * the device mutex lock when this function is called. | |
3381 | * Resetting the device will make the contents of PCI configuration space | |
3382 | * random, so any caller of this must be prepared to reinitialise the | |
3383 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3384 | * etc. | |
3385 | * | |
3386 | * Returns 0 if the device function was successfully reset or negative if the | |
3387 | * device doesn't support resetting a single function. | |
3388 | */ | |
3389 | int __pci_reset_function_locked(struct pci_dev *dev) | |
3390 | { | |
977f857c | 3391 | return __pci_dev_reset(dev, 0); |
6fbf9e7a KRW |
3392 | } |
3393 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
3394 | ||
711d5779 MT |
3395 | /** |
3396 | * pci_probe_reset_function - check whether the device can be safely reset | |
3397 | * @dev: PCI device to reset | |
3398 | * | |
3399 | * Some devices allow an individual function to be reset without affecting | |
3400 | * other functions in the same device. The PCI device must be responsive | |
3401 | * to PCI config space in order to use this function. | |
3402 | * | |
3403 | * Returns 0 if the device function can be reset or negative if the | |
3404 | * device doesn't support resetting a single function. | |
3405 | */ | |
3406 | int pci_probe_reset_function(struct pci_dev *dev) | |
3407 | { | |
3408 | return pci_dev_reset(dev, 1); | |
3409 | } | |
3410 | ||
8dd7f803 | 3411 | /** |
8c1c699f YZ |
3412 | * pci_reset_function - quiesce and reset a PCI device function |
3413 | * @dev: PCI device to reset | |
8dd7f803 SY |
3414 | * |
3415 | * Some devices allow an individual function to be reset without affecting | |
3416 | * other functions in the same device. The PCI device must be responsive | |
3417 | * to PCI config space in order to use this function. | |
3418 | * | |
3419 | * This function does not just reset the PCI portion of a device, but | |
3420 | * clears all the state associated with the device. This function differs | |
8c1c699f | 3421 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
3422 | * over the reset. |
3423 | * | |
8c1c699f | 3424 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
3425 | * device doesn't support resetting a single function. |
3426 | */ | |
3427 | int pci_reset_function(struct pci_dev *dev) | |
3428 | { | |
8c1c699f | 3429 | int rc; |
8dd7f803 | 3430 | |
8c1c699f YZ |
3431 | rc = pci_dev_reset(dev, 1); |
3432 | if (rc) | |
3433 | return rc; | |
8dd7f803 | 3434 | |
77cb985a | 3435 | pci_dev_save_and_disable(dev); |
8dd7f803 | 3436 | |
8c1c699f | 3437 | rc = pci_dev_reset(dev, 0); |
8dd7f803 | 3438 | |
77cb985a | 3439 | pci_dev_restore(dev); |
8dd7f803 | 3440 | |
8c1c699f | 3441 | return rc; |
8dd7f803 SY |
3442 | } |
3443 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
3444 | ||
61cf16d8 AW |
3445 | /** |
3446 | * pci_try_reset_function - quiesce and reset a PCI device function | |
3447 | * @dev: PCI device to reset | |
3448 | * | |
3449 | * Same as above, except return -EAGAIN if unable to lock device. | |
3450 | */ | |
3451 | int pci_try_reset_function(struct pci_dev *dev) | |
3452 | { | |
3453 | int rc; | |
3454 | ||
3455 | rc = pci_dev_reset(dev, 1); | |
3456 | if (rc) | |
3457 | return rc; | |
3458 | ||
3459 | pci_dev_save_and_disable(dev); | |
3460 | ||
3461 | if (pci_dev_trylock(dev)) { | |
3462 | rc = __pci_dev_reset(dev, 0); | |
3463 | pci_dev_unlock(dev); | |
3464 | } else | |
3465 | rc = -EAGAIN; | |
3466 | ||
3467 | pci_dev_restore(dev); | |
3468 | ||
3469 | return rc; | |
3470 | } | |
3471 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
3472 | ||
090a3c53 AW |
3473 | /* Lock devices from the top of the tree down */ |
3474 | static void pci_bus_lock(struct pci_bus *bus) | |
3475 | { | |
3476 | struct pci_dev *dev; | |
3477 | ||
3478 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3479 | pci_dev_lock(dev); | |
3480 | if (dev->subordinate) | |
3481 | pci_bus_lock(dev->subordinate); | |
3482 | } | |
3483 | } | |
3484 | ||
3485 | /* Unlock devices from the bottom of the tree up */ | |
3486 | static void pci_bus_unlock(struct pci_bus *bus) | |
3487 | { | |
3488 | struct pci_dev *dev; | |
3489 | ||
3490 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3491 | if (dev->subordinate) | |
3492 | pci_bus_unlock(dev->subordinate); | |
3493 | pci_dev_unlock(dev); | |
3494 | } | |
3495 | } | |
3496 | ||
61cf16d8 AW |
3497 | /* Return 1 on successful lock, 0 on contention */ |
3498 | static int pci_bus_trylock(struct pci_bus *bus) | |
3499 | { | |
3500 | struct pci_dev *dev; | |
3501 | ||
3502 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3503 | if (!pci_dev_trylock(dev)) | |
3504 | goto unlock; | |
3505 | if (dev->subordinate) { | |
3506 | if (!pci_bus_trylock(dev->subordinate)) { | |
3507 | pci_dev_unlock(dev); | |
3508 | goto unlock; | |
3509 | } | |
3510 | } | |
3511 | } | |
3512 | return 1; | |
3513 | ||
3514 | unlock: | |
3515 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
3516 | if (dev->subordinate) | |
3517 | pci_bus_unlock(dev->subordinate); | |
3518 | pci_dev_unlock(dev); | |
3519 | } | |
3520 | return 0; | |
3521 | } | |
3522 | ||
090a3c53 AW |
3523 | /* Lock devices from the top of the tree down */ |
3524 | static void pci_slot_lock(struct pci_slot *slot) | |
3525 | { | |
3526 | struct pci_dev *dev; | |
3527 | ||
3528 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3529 | if (!dev->slot || dev->slot != slot) | |
3530 | continue; | |
3531 | pci_dev_lock(dev); | |
3532 | if (dev->subordinate) | |
3533 | pci_bus_lock(dev->subordinate); | |
3534 | } | |
3535 | } | |
3536 | ||
3537 | /* Unlock devices from the bottom of the tree up */ | |
3538 | static void pci_slot_unlock(struct pci_slot *slot) | |
3539 | { | |
3540 | struct pci_dev *dev; | |
3541 | ||
3542 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3543 | if (!dev->slot || dev->slot != slot) | |
3544 | continue; | |
3545 | if (dev->subordinate) | |
3546 | pci_bus_unlock(dev->subordinate); | |
3547 | pci_dev_unlock(dev); | |
3548 | } | |
3549 | } | |
3550 | ||
61cf16d8 AW |
3551 | /* Return 1 on successful lock, 0 on contention */ |
3552 | static int pci_slot_trylock(struct pci_slot *slot) | |
3553 | { | |
3554 | struct pci_dev *dev; | |
3555 | ||
3556 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3557 | if (!dev->slot || dev->slot != slot) | |
3558 | continue; | |
3559 | if (!pci_dev_trylock(dev)) | |
3560 | goto unlock; | |
3561 | if (dev->subordinate) { | |
3562 | if (!pci_bus_trylock(dev->subordinate)) { | |
3563 | pci_dev_unlock(dev); | |
3564 | goto unlock; | |
3565 | } | |
3566 | } | |
3567 | } | |
3568 | return 1; | |
3569 | ||
3570 | unlock: | |
3571 | list_for_each_entry_continue_reverse(dev, | |
3572 | &slot->bus->devices, bus_list) { | |
3573 | if (!dev->slot || dev->slot != slot) | |
3574 | continue; | |
3575 | if (dev->subordinate) | |
3576 | pci_bus_unlock(dev->subordinate); | |
3577 | pci_dev_unlock(dev); | |
3578 | } | |
3579 | return 0; | |
3580 | } | |
3581 | ||
090a3c53 AW |
3582 | /* Save and disable devices from the top of the tree down */ |
3583 | static void pci_bus_save_and_disable(struct pci_bus *bus) | |
3584 | { | |
3585 | struct pci_dev *dev; | |
3586 | ||
3587 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3588 | pci_dev_save_and_disable(dev); | |
3589 | if (dev->subordinate) | |
3590 | pci_bus_save_and_disable(dev->subordinate); | |
3591 | } | |
3592 | } | |
3593 | ||
3594 | /* | |
3595 | * Restore devices from top of the tree down - parent bridges need to be | |
3596 | * restored before we can get to subordinate devices. | |
3597 | */ | |
3598 | static void pci_bus_restore(struct pci_bus *bus) | |
3599 | { | |
3600 | struct pci_dev *dev; | |
3601 | ||
3602 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3603 | pci_dev_restore(dev); | |
3604 | if (dev->subordinate) | |
3605 | pci_bus_restore(dev->subordinate); | |
3606 | } | |
3607 | } | |
3608 | ||
3609 | /* Save and disable devices from the top of the tree down */ | |
3610 | static void pci_slot_save_and_disable(struct pci_slot *slot) | |
3611 | { | |
3612 | struct pci_dev *dev; | |
3613 | ||
3614 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3615 | if (!dev->slot || dev->slot != slot) | |
3616 | continue; | |
3617 | pci_dev_save_and_disable(dev); | |
3618 | if (dev->subordinate) | |
3619 | pci_bus_save_and_disable(dev->subordinate); | |
3620 | } | |
3621 | } | |
3622 | ||
3623 | /* | |
3624 | * Restore devices from top of the tree down - parent bridges need to be | |
3625 | * restored before we can get to subordinate devices. | |
3626 | */ | |
3627 | static void pci_slot_restore(struct pci_slot *slot) | |
3628 | { | |
3629 | struct pci_dev *dev; | |
3630 | ||
3631 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3632 | if (!dev->slot || dev->slot != slot) | |
3633 | continue; | |
3634 | pci_dev_restore(dev); | |
3635 | if (dev->subordinate) | |
3636 | pci_bus_restore(dev->subordinate); | |
3637 | } | |
3638 | } | |
3639 | ||
3640 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
3641 | { | |
3642 | int rc; | |
3643 | ||
3644 | if (!slot) | |
3645 | return -ENOTTY; | |
3646 | ||
3647 | if (!probe) | |
3648 | pci_slot_lock(slot); | |
3649 | ||
3650 | might_sleep(); | |
3651 | ||
3652 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
3653 | ||
3654 | if (!probe) | |
3655 | pci_slot_unlock(slot); | |
3656 | ||
3657 | return rc; | |
3658 | } | |
3659 | ||
9a3d2b9b AW |
3660 | /** |
3661 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
3662 | * @slot: PCI slot to probe | |
3663 | * | |
3664 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
3665 | */ | |
3666 | int pci_probe_reset_slot(struct pci_slot *slot) | |
3667 | { | |
3668 | return pci_slot_reset(slot, 1); | |
3669 | } | |
3670 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
3671 | ||
090a3c53 AW |
3672 | /** |
3673 | * pci_reset_slot - reset a PCI slot | |
3674 | * @slot: PCI slot to reset | |
3675 | * | |
3676 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
3677 | * independent of other slots. For instance, some slots may support slot power | |
3678 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
3679 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
3680 | * Generally a slot reset should be attempted before a bus reset. All of the | |
3681 | * function of the slot and any subordinate buses behind the slot are reset | |
3682 | * through this function. PCI config space of all devices in the slot and | |
3683 | * behind the slot is saved before and restored after reset. | |
3684 | * | |
3685 | * Return 0 on success, non-zero on error. | |
3686 | */ | |
3687 | int pci_reset_slot(struct pci_slot *slot) | |
3688 | { | |
3689 | int rc; | |
3690 | ||
3691 | rc = pci_slot_reset(slot, 1); | |
3692 | if (rc) | |
3693 | return rc; | |
3694 | ||
3695 | pci_slot_save_and_disable(slot); | |
3696 | ||
3697 | rc = pci_slot_reset(slot, 0); | |
3698 | ||
3699 | pci_slot_restore(slot); | |
3700 | ||
3701 | return rc; | |
3702 | } | |
3703 | EXPORT_SYMBOL_GPL(pci_reset_slot); | |
3704 | ||
61cf16d8 AW |
3705 | /** |
3706 | * pci_try_reset_slot - Try to reset a PCI slot | |
3707 | * @slot: PCI slot to reset | |
3708 | * | |
3709 | * Same as above except return -EAGAIN if the slot cannot be locked | |
3710 | */ | |
3711 | int pci_try_reset_slot(struct pci_slot *slot) | |
3712 | { | |
3713 | int rc; | |
3714 | ||
3715 | rc = pci_slot_reset(slot, 1); | |
3716 | if (rc) | |
3717 | return rc; | |
3718 | ||
3719 | pci_slot_save_and_disable(slot); | |
3720 | ||
3721 | if (pci_slot_trylock(slot)) { | |
3722 | might_sleep(); | |
3723 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
3724 | pci_slot_unlock(slot); | |
3725 | } else | |
3726 | rc = -EAGAIN; | |
3727 | ||
3728 | pci_slot_restore(slot); | |
3729 | ||
3730 | return rc; | |
3731 | } | |
3732 | EXPORT_SYMBOL_GPL(pci_try_reset_slot); | |
3733 | ||
090a3c53 AW |
3734 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
3735 | { | |
3736 | if (!bus->self) | |
3737 | return -ENOTTY; | |
3738 | ||
3739 | if (probe) | |
3740 | return 0; | |
3741 | ||
3742 | pci_bus_lock(bus); | |
3743 | ||
3744 | might_sleep(); | |
3745 | ||
3746 | pci_reset_bridge_secondary_bus(bus->self); | |
3747 | ||
3748 | pci_bus_unlock(bus); | |
3749 | ||
3750 | return 0; | |
3751 | } | |
3752 | ||
9a3d2b9b AW |
3753 | /** |
3754 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
3755 | * @bus: PCI bus to probe | |
3756 | * | |
3757 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
3758 | */ | |
3759 | int pci_probe_reset_bus(struct pci_bus *bus) | |
3760 | { | |
3761 | return pci_bus_reset(bus, 1); | |
3762 | } | |
3763 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
3764 | ||
090a3c53 AW |
3765 | /** |
3766 | * pci_reset_bus - reset a PCI bus | |
3767 | * @bus: top level PCI bus to reset | |
3768 | * | |
3769 | * Do a bus reset on the given bus and any subordinate buses, saving | |
3770 | * and restoring state of all devices. | |
3771 | * | |
3772 | * Return 0 on success, non-zero on error. | |
3773 | */ | |
3774 | int pci_reset_bus(struct pci_bus *bus) | |
3775 | { | |
3776 | int rc; | |
3777 | ||
3778 | rc = pci_bus_reset(bus, 1); | |
3779 | if (rc) | |
3780 | return rc; | |
3781 | ||
3782 | pci_bus_save_and_disable(bus); | |
3783 | ||
3784 | rc = pci_bus_reset(bus, 0); | |
3785 | ||
3786 | pci_bus_restore(bus); | |
3787 | ||
3788 | return rc; | |
3789 | } | |
3790 | EXPORT_SYMBOL_GPL(pci_reset_bus); | |
3791 | ||
61cf16d8 AW |
3792 | /** |
3793 | * pci_try_reset_bus - Try to reset a PCI bus | |
3794 | * @bus: top level PCI bus to reset | |
3795 | * | |
3796 | * Same as above except return -EAGAIN if the bus cannot be locked | |
3797 | */ | |
3798 | int pci_try_reset_bus(struct pci_bus *bus) | |
3799 | { | |
3800 | int rc; | |
3801 | ||
3802 | rc = pci_bus_reset(bus, 1); | |
3803 | if (rc) | |
3804 | return rc; | |
3805 | ||
3806 | pci_bus_save_and_disable(bus); | |
3807 | ||
3808 | if (pci_bus_trylock(bus)) { | |
3809 | might_sleep(); | |
3810 | pci_reset_bridge_secondary_bus(bus->self); | |
3811 | pci_bus_unlock(bus); | |
3812 | } else | |
3813 | rc = -EAGAIN; | |
3814 | ||
3815 | pci_bus_restore(bus); | |
3816 | ||
3817 | return rc; | |
3818 | } | |
3819 | EXPORT_SYMBOL_GPL(pci_try_reset_bus); | |
3820 | ||
d556ad4b PO |
3821 | /** |
3822 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
3823 | * @dev: PCI device to query | |
3824 | * | |
3825 | * Returns mmrbc: maximum designed memory read count in bytes | |
3826 | * or appropriate error value. | |
3827 | */ | |
3828 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
3829 | { | |
7c9e2b1c | 3830 | int cap; |
d556ad4b PO |
3831 | u32 stat; |
3832 | ||
3833 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3834 | if (!cap) | |
3835 | return -EINVAL; | |
3836 | ||
7c9e2b1c | 3837 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
3838 | return -EINVAL; |
3839 | ||
25daeb55 | 3840 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
3841 | } |
3842 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
3843 | ||
3844 | /** | |
3845 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
3846 | * @dev: PCI device to query | |
3847 | * | |
3848 | * Returns mmrbc: maximum memory read count in bytes | |
3849 | * or appropriate error value. | |
3850 | */ | |
3851 | int pcix_get_mmrbc(struct pci_dev *dev) | |
3852 | { | |
7c9e2b1c | 3853 | int cap; |
bdc2bda7 | 3854 | u16 cmd; |
d556ad4b PO |
3855 | |
3856 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3857 | if (!cap) | |
3858 | return -EINVAL; | |
3859 | ||
7c9e2b1c DN |
3860 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3861 | return -EINVAL; | |
d556ad4b | 3862 | |
7c9e2b1c | 3863 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
3864 | } |
3865 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
3866 | ||
3867 | /** | |
3868 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
3869 | * @dev: PCI device to query | |
3870 | * @mmrbc: maximum memory read count in bytes | |
3871 | * valid values are 512, 1024, 2048, 4096 | |
3872 | * | |
3873 | * If possible sets maximum memory read byte count, some bridges have erratas | |
3874 | * that prevent this. | |
3875 | */ | |
3876 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
3877 | { | |
7c9e2b1c | 3878 | int cap; |
bdc2bda7 DN |
3879 | u32 stat, v, o; |
3880 | u16 cmd; | |
d556ad4b | 3881 | |
229f5afd | 3882 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 3883 | return -EINVAL; |
d556ad4b PO |
3884 | |
3885 | v = ffs(mmrbc) - 10; | |
3886 | ||
3887 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3888 | if (!cap) | |
7c9e2b1c | 3889 | return -EINVAL; |
d556ad4b | 3890 | |
7c9e2b1c DN |
3891 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
3892 | return -EINVAL; | |
d556ad4b PO |
3893 | |
3894 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
3895 | return -E2BIG; | |
3896 | ||
7c9e2b1c DN |
3897 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3898 | return -EINVAL; | |
d556ad4b PO |
3899 | |
3900 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
3901 | if (o != v) { | |
809a3bf9 | 3902 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
3903 | return -EIO; |
3904 | ||
3905 | cmd &= ~PCI_X_CMD_MAX_READ; | |
3906 | cmd |= v << 2; | |
7c9e2b1c DN |
3907 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
3908 | return -EIO; | |
d556ad4b | 3909 | } |
7c9e2b1c | 3910 | return 0; |
d556ad4b PO |
3911 | } |
3912 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
3913 | ||
3914 | /** | |
3915 | * pcie_get_readrq - get PCI Express read request size | |
3916 | * @dev: PCI device to query | |
3917 | * | |
3918 | * Returns maximum memory read request in bytes | |
3919 | * or appropriate error value. | |
3920 | */ | |
3921 | int pcie_get_readrq(struct pci_dev *dev) | |
3922 | { | |
d556ad4b PO |
3923 | u16 ctl; |
3924 | ||
59875ae4 | 3925 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 3926 | |
59875ae4 | 3927 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
3928 | } |
3929 | EXPORT_SYMBOL(pcie_get_readrq); | |
3930 | ||
3931 | /** | |
3932 | * pcie_set_readrq - set PCI Express maximum memory read request | |
3933 | * @dev: PCI device to query | |
42e61f4a | 3934 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
3935 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
3936 | * | |
c9b378c7 | 3937 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
3938 | */ |
3939 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
3940 | { | |
59875ae4 | 3941 | u16 v; |
d556ad4b | 3942 | |
229f5afd | 3943 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 3944 | return -EINVAL; |
d556ad4b | 3945 | |
a1c473aa BH |
3946 | /* |
3947 | * If using the "performance" PCIe config, we clamp the | |
3948 | * read rq size to the max packet size to prevent the | |
3949 | * host bridge generating requests larger than we can | |
3950 | * cope with | |
3951 | */ | |
3952 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
3953 | int mps = pcie_get_mps(dev); | |
3954 | ||
a1c473aa BH |
3955 | if (mps < rq) |
3956 | rq = mps; | |
3957 | } | |
3958 | ||
3959 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 3960 | |
59875ae4 JL |
3961 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
3962 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
3963 | } |
3964 | EXPORT_SYMBOL(pcie_set_readrq); | |
3965 | ||
b03e7495 JM |
3966 | /** |
3967 | * pcie_get_mps - get PCI Express maximum payload size | |
3968 | * @dev: PCI device to query | |
3969 | * | |
3970 | * Returns maximum payload size in bytes | |
b03e7495 JM |
3971 | */ |
3972 | int pcie_get_mps(struct pci_dev *dev) | |
3973 | { | |
b03e7495 JM |
3974 | u16 ctl; |
3975 | ||
59875ae4 | 3976 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 3977 | |
59875ae4 | 3978 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 3979 | } |
f1c66c46 | 3980 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
3981 | |
3982 | /** | |
3983 | * pcie_set_mps - set PCI Express maximum payload size | |
3984 | * @dev: PCI device to query | |
47c08f31 | 3985 | * @mps: maximum payload size in bytes |
b03e7495 JM |
3986 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
3987 | * | |
3988 | * If possible sets maximum payload size | |
3989 | */ | |
3990 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
3991 | { | |
59875ae4 | 3992 | u16 v; |
b03e7495 JM |
3993 | |
3994 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 3995 | return -EINVAL; |
b03e7495 JM |
3996 | |
3997 | v = ffs(mps) - 8; | |
f7625980 | 3998 | if (v > dev->pcie_mpss) |
59875ae4 | 3999 | return -EINVAL; |
b03e7495 JM |
4000 | v <<= 5; |
4001 | ||
59875ae4 JL |
4002 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4003 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 4004 | } |
f1c66c46 | 4005 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 4006 | |
81377c8d JK |
4007 | /** |
4008 | * pcie_get_minimum_link - determine minimum link settings of a PCI device | |
4009 | * @dev: PCI device to query | |
4010 | * @speed: storage for minimum speed | |
4011 | * @width: storage for minimum width | |
4012 | * | |
4013 | * This function will walk up the PCI device chain and determine the minimum | |
4014 | * link width and speed of the device. | |
4015 | */ | |
4016 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, | |
4017 | enum pcie_link_width *width) | |
4018 | { | |
4019 | int ret; | |
4020 | ||
4021 | *speed = PCI_SPEED_UNKNOWN; | |
4022 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4023 | ||
4024 | while (dev) { | |
4025 | u16 lnksta; | |
4026 | enum pci_bus_speed next_speed; | |
4027 | enum pcie_link_width next_width; | |
4028 | ||
4029 | ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
4030 | if (ret) | |
4031 | return ret; | |
4032 | ||
4033 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
4034 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
4035 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
4036 | ||
4037 | if (next_speed < *speed) | |
4038 | *speed = next_speed; | |
4039 | ||
4040 | if (next_width < *width) | |
4041 | *width = next_width; | |
4042 | ||
4043 | dev = dev->bus->self; | |
4044 | } | |
4045 | ||
4046 | return 0; | |
4047 | } | |
4048 | EXPORT_SYMBOL(pcie_get_minimum_link); | |
4049 | ||
c87deff7 HS |
4050 | /** |
4051 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 4052 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
4053 | * @flags: resource type mask to be selected |
4054 | * | |
4055 | * This helper routine makes bar mask from the type of resource. | |
4056 | */ | |
4057 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
4058 | { | |
4059 | int i, bars = 0; | |
4060 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
4061 | if (pci_resource_flags(dev, i) & flags) | |
4062 | bars |= (1 << i); | |
4063 | return bars; | |
4064 | } | |
4065 | ||
613e7ed6 YZ |
4066 | /** |
4067 | * pci_resource_bar - get position of the BAR associated with a resource | |
4068 | * @dev: the PCI device | |
4069 | * @resno: the resource number | |
4070 | * @type: the BAR type to be filled in | |
4071 | * | |
4072 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
4073 | */ | |
4074 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
4075 | { | |
d1b054da YZ |
4076 | int reg; |
4077 | ||
613e7ed6 YZ |
4078 | if (resno < PCI_ROM_RESOURCE) { |
4079 | *type = pci_bar_unknown; | |
4080 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
4081 | } else if (resno == PCI_ROM_RESOURCE) { | |
4082 | *type = pci_bar_mem32; | |
4083 | return dev->rom_base_reg; | |
d1b054da YZ |
4084 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
4085 | /* device specific resource */ | |
4086 | reg = pci_iov_resource_bar(dev, resno, type); | |
4087 | if (reg) | |
4088 | return reg; | |
613e7ed6 YZ |
4089 | } |
4090 | ||
865df576 | 4091 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
4092 | return 0; |
4093 | } | |
4094 | ||
95a8b6ef MT |
4095 | /* Some architectures require additional programming to enable VGA */ |
4096 | static arch_set_vga_state_t arch_set_vga_state; | |
4097 | ||
4098 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
4099 | { | |
4100 | arch_set_vga_state = func; /* NULL disables */ | |
4101 | } | |
4102 | ||
4103 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
7ad35cf2 | 4104 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
4105 | { |
4106 | if (arch_set_vga_state) | |
4107 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 4108 | flags); |
95a8b6ef MT |
4109 | return 0; |
4110 | } | |
4111 | ||
deb2d2ec BH |
4112 | /** |
4113 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
4114 | * @dev: the PCI device |
4115 | * @decode: true = enable decoding, false = disable decoding | |
4116 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 4117 | * @flags: traverse ancestors and change bridges |
3448a19d | 4118 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
4119 | */ |
4120 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 4121 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
4122 | { |
4123 | struct pci_bus *bus; | |
4124 | struct pci_dev *bridge; | |
4125 | u16 cmd; | |
95a8b6ef | 4126 | int rc; |
deb2d2ec | 4127 | |
3448a19d | 4128 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 4129 | |
95a8b6ef | 4130 | /* ARCH specific VGA enables */ |
3448a19d | 4131 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
4132 | if (rc) |
4133 | return rc; | |
4134 | ||
3448a19d DA |
4135 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
4136 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4137 | if (decode == true) | |
4138 | cmd |= command_bits; | |
4139 | else | |
4140 | cmd &= ~command_bits; | |
4141 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4142 | } | |
deb2d2ec | 4143 | |
3448a19d | 4144 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
4145 | return 0; |
4146 | ||
4147 | bus = dev->bus; | |
4148 | while (bus) { | |
4149 | bridge = bus->self; | |
4150 | if (bridge) { | |
4151 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4152 | &cmd); | |
4153 | if (decode == true) | |
4154 | cmd |= PCI_BRIDGE_CTL_VGA; | |
4155 | else | |
4156 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
4157 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4158 | cmd); | |
4159 | } | |
4160 | bus = bus->parent; | |
4161 | } | |
4162 | return 0; | |
4163 | } | |
4164 | ||
8496e85c RW |
4165 | bool pci_device_is_present(struct pci_dev *pdev) |
4166 | { | |
4167 | u32 v; | |
4168 | ||
4169 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); | |
4170 | } | |
4171 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
4172 | ||
32a9a682 YS |
4173 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
4174 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 4175 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
4176 | |
4177 | /** | |
4178 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
4179 | * @dev: the PCI device to get | |
4180 | * | |
4181 | * RETURNS: Resource alignment if it is specified. | |
4182 | * Zero if it is not specified. | |
4183 | */ | |
9738abed | 4184 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) |
32a9a682 YS |
4185 | { |
4186 | int seg, bus, slot, func, align_order, count; | |
4187 | resource_size_t align = 0; | |
4188 | char *p; | |
4189 | ||
4190 | spin_lock(&resource_alignment_lock); | |
4191 | p = resource_alignment_param; | |
4192 | while (*p) { | |
4193 | count = 0; | |
4194 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
4195 | p[count] == '@') { | |
4196 | p += count + 1; | |
4197 | } else { | |
4198 | align_order = -1; | |
4199 | } | |
4200 | if (sscanf(p, "%x:%x:%x.%x%n", | |
4201 | &seg, &bus, &slot, &func, &count) != 4) { | |
4202 | seg = 0; | |
4203 | if (sscanf(p, "%x:%x.%x%n", | |
4204 | &bus, &slot, &func, &count) != 3) { | |
4205 | /* Invalid format */ | |
4206 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
4207 | p); | |
4208 | break; | |
4209 | } | |
4210 | } | |
4211 | p += count; | |
4212 | if (seg == pci_domain_nr(dev->bus) && | |
4213 | bus == dev->bus->number && | |
4214 | slot == PCI_SLOT(dev->devfn) && | |
4215 | func == PCI_FUNC(dev->devfn)) { | |
4216 | if (align_order == -1) { | |
4217 | align = PAGE_SIZE; | |
4218 | } else { | |
4219 | align = 1 << align_order; | |
4220 | } | |
4221 | /* Found */ | |
4222 | break; | |
4223 | } | |
4224 | if (*p != ';' && *p != ',') { | |
4225 | /* End of param or invalid format */ | |
4226 | break; | |
4227 | } | |
4228 | p++; | |
4229 | } | |
4230 | spin_unlock(&resource_alignment_lock); | |
4231 | return align; | |
4232 | } | |
4233 | ||
2069ecfb YL |
4234 | /* |
4235 | * This function disables memory decoding and releases memory resources | |
4236 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
4237 | * It also rounds up size to specified alignment. | |
4238 | * Later on, the kernel will assign page-aligned memory resource back | |
4239 | * to the device. | |
4240 | */ | |
4241 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
4242 | { | |
4243 | int i; | |
4244 | struct resource *r; | |
4245 | resource_size_t align, size; | |
4246 | u16 command; | |
4247 | ||
10c463a7 YL |
4248 | /* check if specified PCI is target device to reassign */ |
4249 | align = pci_specified_resource_alignment(dev); | |
4250 | if (!align) | |
2069ecfb YL |
4251 | return; |
4252 | ||
4253 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
4254 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
4255 | dev_warn(&dev->dev, | |
4256 | "Can't reassign resources to host bridge.\n"); | |
4257 | return; | |
4258 | } | |
4259 | ||
4260 | dev_info(&dev->dev, | |
4261 | "Disabling memory decoding and releasing memory resources.\n"); | |
4262 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
4263 | command &= ~PCI_COMMAND_MEMORY; | |
4264 | pci_write_config_word(dev, PCI_COMMAND, command); | |
4265 | ||
2069ecfb YL |
4266 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { |
4267 | r = &dev->resource[i]; | |
4268 | if (!(r->flags & IORESOURCE_MEM)) | |
4269 | continue; | |
4270 | size = resource_size(r); | |
4271 | if (size < align) { | |
4272 | size = align; | |
4273 | dev_info(&dev->dev, | |
4274 | "Rounding up size of resource #%d to %#llx.\n", | |
4275 | i, (unsigned long long)size); | |
4276 | } | |
bd064f0a | 4277 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
4278 | r->end = size - 1; |
4279 | r->start = 0; | |
4280 | } | |
4281 | /* Need to disable bridge's resource window, | |
4282 | * to enable the kernel to reassign new resource | |
4283 | * window later on. | |
4284 | */ | |
4285 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
4286 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
4287 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
4288 | r = &dev->resource[i]; | |
4289 | if (!(r->flags & IORESOURCE_MEM)) | |
4290 | continue; | |
bd064f0a | 4291 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
4292 | r->end = resource_size(r) - 1; |
4293 | r->start = 0; | |
4294 | } | |
4295 | pci_disable_bridge_window(dev); | |
4296 | } | |
4297 | } | |
4298 | ||
9738abed | 4299 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
4300 | { |
4301 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
4302 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
4303 | spin_lock(&resource_alignment_lock); | |
4304 | strncpy(resource_alignment_param, buf, count); | |
4305 | resource_alignment_param[count] = '\0'; | |
4306 | spin_unlock(&resource_alignment_lock); | |
4307 | return count; | |
4308 | } | |
4309 | ||
9738abed | 4310 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
4311 | { |
4312 | size_t count; | |
4313 | spin_lock(&resource_alignment_lock); | |
4314 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
4315 | spin_unlock(&resource_alignment_lock); | |
4316 | return count; | |
4317 | } | |
4318 | ||
4319 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
4320 | { | |
4321 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
4322 | } | |
4323 | ||
4324 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
4325 | const char *buf, size_t count) | |
4326 | { | |
4327 | return pci_set_resource_alignment_param(buf, count); | |
4328 | } | |
4329 | ||
4330 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, | |
4331 | pci_resource_alignment_store); | |
4332 | ||
4333 | static int __init pci_resource_alignment_sysfs_init(void) | |
4334 | { | |
4335 | return bus_create_file(&pci_bus_type, | |
4336 | &bus_attr_resource_alignment); | |
4337 | } | |
4338 | ||
4339 | late_initcall(pci_resource_alignment_sysfs_init); | |
4340 | ||
15856ad5 | 4341 | static void pci_no_domains(void) |
32a2eea7 JG |
4342 | { |
4343 | #ifdef CONFIG_PCI_DOMAINS | |
4344 | pci_domains_supported = 0; | |
4345 | #endif | |
4346 | } | |
4347 | ||
0ef5f8f6 | 4348 | /** |
642c92da | 4349 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
4350 | * |
4351 | * Returns 1 if we can access PCI extended config space (offsets | |
4352 | * greater than 0xff). This is the default implementation. Architecture | |
4353 | * implementations can override this. | |
4354 | */ | |
642c92da | 4355 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
4356 | { |
4357 | return 1; | |
4358 | } | |
4359 | ||
2d1c8618 BH |
4360 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
4361 | { | |
4362 | } | |
4363 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
4364 | ||
ad04d31e | 4365 | static int __init pci_setup(char *str) |
1da177e4 LT |
4366 | { |
4367 | while (str) { | |
4368 | char *k = strchr(str, ','); | |
4369 | if (k) | |
4370 | *k++ = 0; | |
4371 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
4372 | if (!strcmp(str, "nomsi")) { |
4373 | pci_no_msi(); | |
7f785763 RD |
4374 | } else if (!strcmp(str, "noaer")) { |
4375 | pci_no_aer(); | |
b55438fd YL |
4376 | } else if (!strncmp(str, "realloc=", 8)) { |
4377 | pci_realloc_get_opt(str + 8); | |
f483d392 | 4378 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 4379 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
4380 | } else if (!strcmp(str, "nodomains")) { |
4381 | pci_no_domains(); | |
6748dcc2 RW |
4382 | } else if (!strncmp(str, "noari", 5)) { |
4383 | pcie_ari_disabled = true; | |
4516a618 AN |
4384 | } else if (!strncmp(str, "cbiosize=", 9)) { |
4385 | pci_cardbus_io_size = memparse(str + 9, &str); | |
4386 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
4387 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
4388 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
4389 | pci_set_resource_alignment_param(str + 19, | |
4390 | strlen(str + 19)); | |
43c16408 AP |
4391 | } else if (!strncmp(str, "ecrc=", 5)) { |
4392 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
4393 | } else if (!strncmp(str, "hpiosize=", 9)) { |
4394 | pci_hotplug_io_size = memparse(str + 9, &str); | |
4395 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
4396 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
5f39e670 JM |
4397 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
4398 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
4399 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
4400 | pcie_bus_config = PCIE_BUS_SAFE; | |
4401 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
4402 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
4403 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
4404 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
4405 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
4406 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
4407 | } else { |
4408 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
4409 | str); | |
4410 | } | |
1da177e4 LT |
4411 | } |
4412 | str = k; | |
4413 | } | |
0637a70a | 4414 | return 0; |
1da177e4 | 4415 | } |
0637a70a | 4416 | early_param("pci", pci_setup); |
1da177e4 | 4417 | |
0b62e13b | 4418 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
4419 | EXPORT_SYMBOL(pci_enable_device_io); |
4420 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 4421 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
4422 | EXPORT_SYMBOL(pcim_enable_device); |
4423 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 4424 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
4425 | EXPORT_SYMBOL(pci_find_capability); |
4426 | EXPORT_SYMBOL(pci_bus_find_capability); | |
4427 | EXPORT_SYMBOL(pci_release_regions); | |
4428 | EXPORT_SYMBOL(pci_request_regions); | |
e8de1481 | 4429 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
1da177e4 LT |
4430 | EXPORT_SYMBOL(pci_release_region); |
4431 | EXPORT_SYMBOL(pci_request_region); | |
e8de1481 | 4432 | EXPORT_SYMBOL(pci_request_region_exclusive); |
c87deff7 HS |
4433 | EXPORT_SYMBOL(pci_release_selected_regions); |
4434 | EXPORT_SYMBOL(pci_request_selected_regions); | |
e8de1481 | 4435 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
1da177e4 | 4436 | EXPORT_SYMBOL(pci_set_master); |
6a479079 | 4437 | EXPORT_SYMBOL(pci_clear_master); |
1da177e4 | 4438 | EXPORT_SYMBOL(pci_set_mwi); |
694625c0 | 4439 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 4440 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 4441 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 LT |
4442 | EXPORT_SYMBOL(pci_assign_resource); |
4443 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 4444 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
4445 | |
4446 | EXPORT_SYMBOL(pci_set_power_state); | |
4447 | EXPORT_SYMBOL(pci_save_state); | |
4448 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 4449 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 4450 | EXPORT_SYMBOL(pci_pme_active); |
0235c4fc | 4451 | EXPORT_SYMBOL(pci_wake_from_d3); |
404cc2d8 RW |
4452 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
4453 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 4454 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |