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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
2ab51dde | 10 | #include <linux/acpi.h> |
1da177e4 LT |
11 | #include <linux/kernel.h> |
12 | #include <linux/delay.h> | |
9d26d3a8 | 13 | #include <linux/dmi.h> |
1da177e4 | 14 | #include <linux/init.h> |
7c674700 LP |
15 | #include <linux/of.h> |
16 | #include <linux/of_pci.h> | |
1da177e4 | 17 | #include <linux/pci.h> |
075c1771 | 18 | #include <linux/pm.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1da177e4 LT |
20 | #include <linux/module.h> |
21 | #include <linux/spinlock.h> | |
4e57b681 | 22 | #include <linux/string.h> |
229f5afd | 23 | #include <linux/log2.h> |
7d715a6c | 24 | #include <linux/pci-aspm.h> |
c300bd2f | 25 | #include <linux/pm_wakeup.h> |
8dd7f803 | 26 | #include <linux/interrupt.h> |
32a9a682 | 27 | #include <linux/device.h> |
b67ea761 | 28 | #include <linux/pm_runtime.h> |
608c3881 | 29 | #include <linux/pci_hotplug.h> |
4d3f1384 | 30 | #include <linux/vmalloc.h> |
32a9a682 | 31 | #include <asm/setup.h> |
2a2aca31 | 32 | #include <asm/dma.h> |
b07461a8 | 33 | #include <linux/aer.h> |
bc56b9e0 | 34 | #include "pci.h" |
1da177e4 | 35 | |
00240c38 AS |
36 | const char *pci_power_names[] = { |
37 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
38 | }; | |
39 | EXPORT_SYMBOL_GPL(pci_power_names); | |
40 | ||
93177a74 RW |
41 | int isa_dma_bridge_buggy; |
42 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
43 | ||
44 | int pci_pci_problems; | |
45 | EXPORT_SYMBOL(pci_pci_problems); | |
46 | ||
1ae861e6 RW |
47 | unsigned int pci_pm_d3_delay; |
48 | ||
df17e62e MG |
49 | static void pci_pme_list_scan(struct work_struct *work); |
50 | ||
51 | static LIST_HEAD(pci_pme_list); | |
52 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
53 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
54 | ||
55 | struct pci_pme_device { | |
56 | struct list_head list; | |
57 | struct pci_dev *dev; | |
58 | }; | |
59 | ||
60 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
61 | ||
1ae861e6 RW |
62 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
63 | { | |
64 | unsigned int delay = dev->d3_delay; | |
65 | ||
66 | if (delay < pci_pm_d3_delay) | |
67 | delay = pci_pm_d3_delay; | |
68 | ||
69 | msleep(delay); | |
70 | } | |
1da177e4 | 71 | |
32a2eea7 JG |
72 | #ifdef CONFIG_PCI_DOMAINS |
73 | int pci_domains_supported = 1; | |
74 | #endif | |
75 | ||
4516a618 AN |
76 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
77 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
78 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
79 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
80 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
81 | ||
28760489 EB |
82 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
83 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
84 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
85 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
86 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
87 | ||
e16b4660 KB |
88 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
89 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
90 | ||
27d868b5 | 91 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b03e7495 | 92 | |
ac1aa47b JB |
93 | /* |
94 | * The default CLS is used if arch didn't set CLS explicitly and not | |
95 | * all pci devices agree on the same value. Arch can override either | |
96 | * the dfl or actual value as it sees fit. Don't forget this is | |
97 | * measured in 32-bit words, not bytes. | |
98 | */ | |
15856ad5 | 99 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
100 | u8 pci_cache_line_size; |
101 | ||
96c55900 MS |
102 | /* |
103 | * If we set up a device for bus mastering, we need to check the latency | |
104 | * timer as certain BIOSes forget to set it properly. | |
105 | */ | |
106 | unsigned int pcibios_max_latency = 255; | |
107 | ||
6748dcc2 RW |
108 | /* If set, the PCIe ARI capability will not be used. */ |
109 | static bool pcie_ari_disabled; | |
110 | ||
9d26d3a8 MW |
111 | /* Disable bridge_d3 for all PCIe ports */ |
112 | static bool pci_bridge_d3_disable; | |
113 | /* Force bridge_d3 for all PCIe ports */ | |
114 | static bool pci_bridge_d3_force; | |
115 | ||
116 | static int __init pcie_port_pm_setup(char *str) | |
117 | { | |
118 | if (!strcmp(str, "off")) | |
119 | pci_bridge_d3_disable = true; | |
120 | else if (!strcmp(str, "force")) | |
121 | pci_bridge_d3_force = true; | |
122 | return 1; | |
123 | } | |
124 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
125 | ||
1da177e4 LT |
126 | /** |
127 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
128 | * @bus: pointer to PCI bus structure to search | |
129 | * | |
130 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
131 | * including the given PCI bus and its list of child PCI buses. | |
132 | */ | |
07656d83 | 133 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 134 | { |
94e6a9b9 | 135 | struct pci_bus *tmp; |
1da177e4 LT |
136 | unsigned char max, n; |
137 | ||
b918c62e | 138 | max = bus->busn_res.end; |
94e6a9b9 YW |
139 | list_for_each_entry(tmp, &bus->children, node) { |
140 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 141 | if (n > max) |
1da177e4 LT |
142 | max = n; |
143 | } | |
144 | return max; | |
145 | } | |
b82db5ce | 146 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 147 | |
1684f5dd AM |
148 | #ifdef CONFIG_HAS_IOMEM |
149 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
150 | { | |
1f7bf3bf BH |
151 | struct resource *res = &pdev->resource[bar]; |
152 | ||
1684f5dd AM |
153 | /* |
154 | * Make sure the BAR is actually a memory resource, not an IO resource | |
155 | */ | |
646c0282 | 156 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
1f7bf3bf | 157 | dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
158 | return NULL; |
159 | } | |
1f7bf3bf | 160 | return ioremap_nocache(res->start, resource_size(res)); |
1684f5dd AM |
161 | } |
162 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
163 | |
164 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
165 | { | |
166 | /* | |
167 | * Make sure the BAR is actually a memory resource, not an IO resource | |
168 | */ | |
169 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
170 | WARN_ON(1); | |
171 | return NULL; | |
172 | } | |
173 | return ioremap_wc(pci_resource_start(pdev, bar), | |
174 | pci_resource_len(pdev, bar)); | |
175 | } | |
176 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
177 | #endif |
178 | ||
687d5fe3 ME |
179 | |
180 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
181 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
182 | { |
183 | u8 id; | |
55db3208 SS |
184 | u16 ent; |
185 | ||
186 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 187 | |
687d5fe3 | 188 | while ((*ttl)--) { |
24a4e377 RD |
189 | if (pos < 0x40) |
190 | break; | |
191 | pos &= ~3; | |
55db3208 SS |
192 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
193 | ||
194 | id = ent & 0xff; | |
24a4e377 RD |
195 | if (id == 0xff) |
196 | break; | |
197 | if (id == cap) | |
198 | return pos; | |
55db3208 | 199 | pos = (ent >> 8); |
24a4e377 RD |
200 | } |
201 | return 0; | |
202 | } | |
203 | ||
687d5fe3 ME |
204 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
205 | u8 pos, int cap) | |
206 | { | |
207 | int ttl = PCI_FIND_CAP_TTL; | |
208 | ||
209 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
210 | } | |
211 | ||
24a4e377 RD |
212 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
213 | { | |
214 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
215 | pos + PCI_CAP_LIST_NEXT, cap); | |
216 | } | |
217 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
218 | ||
d3bac118 ME |
219 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
220 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
221 | { |
222 | u16 status; | |
1da177e4 LT |
223 | |
224 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
225 | if (!(status & PCI_STATUS_CAP_LIST)) | |
226 | return 0; | |
227 | ||
228 | switch (hdr_type) { | |
229 | case PCI_HEADER_TYPE_NORMAL: | |
230 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 231 | return PCI_CAPABILITY_LIST; |
1da177e4 | 232 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 233 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 234 | } |
d3bac118 ME |
235 | |
236 | return 0; | |
1da177e4 LT |
237 | } |
238 | ||
239 | /** | |
f7625980 | 240 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
241 | * @dev: PCI device to query |
242 | * @cap: capability code | |
243 | * | |
244 | * Tell if a device supports a given PCI capability. | |
245 | * Returns the address of the requested capability structure within the | |
246 | * device's PCI configuration space or 0 in case the device does not | |
247 | * support it. Possible values for @cap: | |
248 | * | |
f7625980 BH |
249 | * %PCI_CAP_ID_PM Power Management |
250 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
251 | * %PCI_CAP_ID_VPD Vital Product Data | |
252 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 253 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 254 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
255 | * %PCI_CAP_ID_PCIX PCI-X |
256 | * %PCI_CAP_ID_EXP PCI Express | |
257 | */ | |
258 | int pci_find_capability(struct pci_dev *dev, int cap) | |
259 | { | |
d3bac118 ME |
260 | int pos; |
261 | ||
262 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
263 | if (pos) | |
264 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
265 | ||
266 | return pos; | |
1da177e4 | 267 | } |
b7fe9434 | 268 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
269 | |
270 | /** | |
f7625980 | 271 | * pci_bus_find_capability - query for devices' capabilities |
1da177e4 LT |
272 | * @bus: the PCI bus to query |
273 | * @devfn: PCI device to query | |
274 | * @cap: capability code | |
275 | * | |
276 | * Like pci_find_capability() but works for pci devices that do not have a | |
f7625980 | 277 | * pci_dev structure set up yet. |
1da177e4 LT |
278 | * |
279 | * Returns the address of the requested capability structure within the | |
280 | * device's PCI configuration space or 0 in case the device does not | |
281 | * support it. | |
282 | */ | |
283 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
284 | { | |
d3bac118 | 285 | int pos; |
1da177e4 LT |
286 | u8 hdr_type; |
287 | ||
288 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
289 | ||
d3bac118 ME |
290 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
291 | if (pos) | |
292 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
293 | ||
294 | return pos; | |
1da177e4 | 295 | } |
b7fe9434 | 296 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
297 | |
298 | /** | |
44a9a36f | 299 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 300 | * @dev: PCI device to query |
44a9a36f | 301 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
302 | * @cap: capability code |
303 | * | |
44a9a36f | 304 | * Returns the address of the next matching extended capability structure |
1da177e4 | 305 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
306 | * not support it. Some capabilities can occur several times, e.g., the |
307 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 308 | */ |
44a9a36f | 309 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
310 | { |
311 | u32 header; | |
557848c3 ZY |
312 | int ttl; |
313 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 314 | |
557848c3 ZY |
315 | /* minimum 8 bytes per capability */ |
316 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
317 | ||
318 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
319 | return 0; |
320 | ||
44a9a36f BH |
321 | if (start) |
322 | pos = start; | |
323 | ||
1da177e4 LT |
324 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
325 | return 0; | |
326 | ||
327 | /* | |
328 | * If we have no capabilities, this is indicated by cap ID, | |
329 | * cap version and next pointer all being 0. | |
330 | */ | |
331 | if (header == 0) | |
332 | return 0; | |
333 | ||
334 | while (ttl-- > 0) { | |
44a9a36f | 335 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
336 | return pos; |
337 | ||
338 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 339 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
340 | break; |
341 | ||
342 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
343 | break; | |
344 | } | |
345 | ||
346 | return 0; | |
347 | } | |
44a9a36f BH |
348 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
349 | ||
350 | /** | |
351 | * pci_find_ext_capability - Find an extended capability | |
352 | * @dev: PCI device to query | |
353 | * @cap: capability code | |
354 | * | |
355 | * Returns the address of the requested extended capability structure | |
356 | * within the device's PCI configuration space or 0 if the device does | |
357 | * not support it. Possible values for @cap: | |
358 | * | |
359 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
360 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
361 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
362 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
363 | */ | |
364 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
365 | { | |
366 | return pci_find_next_ext_capability(dev, 0, cap); | |
367 | } | |
3a720d72 | 368 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 369 | |
687d5fe3 ME |
370 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
371 | { | |
372 | int rc, ttl = PCI_FIND_CAP_TTL; | |
373 | u8 cap, mask; | |
374 | ||
375 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
376 | mask = HT_3BIT_CAP_MASK; | |
377 | else | |
378 | mask = HT_5BIT_CAP_MASK; | |
379 | ||
380 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
381 | PCI_CAP_ID_HT, &ttl); | |
382 | while (pos) { | |
383 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
384 | if (rc != PCIBIOS_SUCCESSFUL) | |
385 | return 0; | |
386 | ||
387 | if ((cap & mask) == ht_cap) | |
388 | return pos; | |
389 | ||
47a4d5be BG |
390 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
391 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
392 | PCI_CAP_ID_HT, &ttl); |
393 | } | |
394 | ||
395 | return 0; | |
396 | } | |
397 | /** | |
398 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
399 | * @dev: PCI device to query | |
400 | * @pos: Position from which to continue searching | |
401 | * @ht_cap: Hypertransport capability code | |
402 | * | |
403 | * To be used in conjunction with pci_find_ht_capability() to search for | |
404 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
405 | * from pci_find_ht_capability(). | |
406 | * | |
407 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
408 | * steps to avoid an infinite loop. | |
409 | */ | |
410 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
411 | { | |
412 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
415 | ||
416 | /** | |
417 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
418 | * @dev: PCI device to query | |
419 | * @ht_cap: Hypertransport capability code | |
420 | * | |
421 | * Tell if a device supports a given Hypertransport capability. | |
422 | * Returns an address within the device's PCI configuration space | |
423 | * or 0 in case the device does not support the request capability. | |
424 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
425 | * which has a Hypertransport capability matching @ht_cap. | |
426 | */ | |
427 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
428 | { | |
429 | int pos; | |
430 | ||
431 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
432 | if (pos) | |
433 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
434 | ||
435 | return pos; | |
436 | } | |
437 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
438 | ||
1da177e4 LT |
439 | /** |
440 | * pci_find_parent_resource - return resource region of parent bus of given region | |
441 | * @dev: PCI device structure contains resources to be searched | |
442 | * @res: child resource record for which parent is sought | |
443 | * | |
444 | * For given resource region of given device, return the resource | |
f44116ae | 445 | * region of parent bus the given region is contained in. |
1da177e4 | 446 | */ |
3c78bc61 RD |
447 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
448 | struct resource *res) | |
1da177e4 LT |
449 | { |
450 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 451 | struct resource *r; |
1da177e4 | 452 | int i; |
1da177e4 | 453 | |
89a74ecc | 454 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
455 | if (!r) |
456 | continue; | |
f44116ae BH |
457 | if (res->start && resource_contains(r, res)) { |
458 | ||
459 | /* | |
460 | * If the window is prefetchable but the BAR is | |
461 | * not, the allocator made a mistake. | |
462 | */ | |
463 | if (r->flags & IORESOURCE_PREFETCH && | |
464 | !(res->flags & IORESOURCE_PREFETCH)) | |
465 | return NULL; | |
466 | ||
467 | /* | |
468 | * If we're below a transparent bridge, there may | |
469 | * be both a positively-decoded aperture and a | |
470 | * subtractively-decoded region that contain the BAR. | |
471 | * We want the positively-decoded one, so this depends | |
472 | * on pci_bus_for_each_resource() giving us those | |
473 | * first. | |
474 | */ | |
475 | return r; | |
476 | } | |
1da177e4 | 477 | } |
f44116ae | 478 | return NULL; |
1da177e4 | 479 | } |
b7fe9434 | 480 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 481 | |
afd29f90 MW |
482 | /** |
483 | * pci_find_resource - Return matching PCI device resource | |
484 | * @dev: PCI device to query | |
485 | * @res: Resource to look for | |
486 | * | |
487 | * Goes over standard PCI resources (BARs) and checks if the given resource | |
488 | * is partially or fully contained in any of them. In that case the | |
489 | * matching resource is returned, %NULL otherwise. | |
490 | */ | |
491 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) | |
492 | { | |
493 | int i; | |
494 | ||
495 | for (i = 0; i < PCI_ROM_RESOURCE; i++) { | |
496 | struct resource *r = &dev->resource[i]; | |
497 | ||
498 | if (r->start && resource_contains(r, res)) | |
499 | return r; | |
500 | } | |
501 | ||
502 | return NULL; | |
503 | } | |
504 | EXPORT_SYMBOL(pci_find_resource); | |
505 | ||
c56d4450 HS |
506 | /** |
507 | * pci_find_pcie_root_port - return PCIe Root Port | |
508 | * @dev: PCI device to query | |
509 | * | |
510 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
511 | * for a given PCI Device. | |
512 | */ | |
513 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) | |
514 | { | |
515 | struct pci_dev *bridge, *highest_pcie_bridge = NULL; | |
516 | ||
517 | bridge = pci_upstream_bridge(dev); | |
518 | while (bridge && pci_is_pcie(bridge)) { | |
519 | highest_pcie_bridge = bridge; | |
520 | bridge = pci_upstream_bridge(bridge); | |
521 | } | |
522 | ||
523 | if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) | |
524 | return NULL; | |
525 | ||
526 | return highest_pcie_bridge; | |
527 | } | |
528 | EXPORT_SYMBOL(pci_find_pcie_root_port); | |
529 | ||
157e876f AW |
530 | /** |
531 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
532 | * @dev: the PCI device to operate on | |
533 | * @pos: config space offset of status word | |
534 | * @mask: mask of bit(s) to care about in status word | |
535 | * | |
536 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
537 | */ | |
538 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
539 | { | |
540 | int i; | |
541 | ||
542 | /* Wait for Transaction Pending bit clean */ | |
543 | for (i = 0; i < 4; i++) { | |
544 | u16 status; | |
545 | if (i) | |
546 | msleep((1 << (i - 1)) * 100); | |
547 | ||
548 | pci_read_config_word(dev, pos, &status); | |
549 | if (!(status & mask)) | |
550 | return 1; | |
551 | } | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
064b53db | 556 | /** |
70675e0b | 557 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
558 | * @dev: PCI device to have its BARs restored |
559 | * | |
560 | * Restore the BAR values for a given device, so as to make it | |
561 | * accessible by its driver. | |
562 | */ | |
3c78bc61 | 563 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 564 | { |
bc5f5a82 | 565 | int i; |
064b53db | 566 | |
bc5f5a82 | 567 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 568 | pci_update_resource(dev, i); |
064b53db JL |
569 | } |
570 | ||
299f2ffe | 571 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 572 | |
299f2ffe | 573 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 574 | { |
cc7cc02b LW |
575 | if (!ops->is_manageable || !ops->set_state || !ops->get_state || |
576 | !ops->choose_state || !ops->sleep_wake || !ops->run_wake || | |
577 | !ops->need_resume) | |
961d9120 RW |
578 | return -EINVAL; |
579 | pci_platform_pm = ops; | |
580 | return 0; | |
581 | } | |
582 | ||
583 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
584 | { | |
585 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
586 | } | |
587 | ||
588 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 589 | pci_power_t t) |
961d9120 RW |
590 | { |
591 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
592 | } | |
593 | ||
cc7cc02b LW |
594 | static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) |
595 | { | |
596 | return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; | |
597 | } | |
598 | ||
961d9120 RW |
599 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
600 | { | |
601 | return pci_platform_pm ? | |
602 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
603 | } | |
8f7020d3 | 604 | |
eb9d0fe4 RW |
605 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
606 | { | |
607 | return pci_platform_pm ? | |
608 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
609 | } | |
610 | ||
b67ea761 RW |
611 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
612 | { | |
613 | return pci_platform_pm ? | |
614 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
615 | } | |
616 | ||
bac2a909 RW |
617 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
618 | { | |
619 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
620 | } | |
621 | ||
1da177e4 | 622 | /** |
44e4e66e RW |
623 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
624 | * given PCI device | |
625 | * @dev: PCI device to handle. | |
44e4e66e | 626 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 627 | * |
44e4e66e RW |
628 | * RETURN VALUE: |
629 | * -EINVAL if the requested state is invalid. | |
630 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
631 | * wrong version, or device doesn't support the requested state. | |
632 | * 0 if device already is in the requested state. | |
633 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 634 | */ |
f00a20ef | 635 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 636 | { |
337001b6 | 637 | u16 pmcsr; |
44e4e66e | 638 | bool need_restore = false; |
1da177e4 | 639 | |
4a865905 RW |
640 | /* Check if we're already there */ |
641 | if (dev->current_state == state) | |
642 | return 0; | |
643 | ||
337001b6 | 644 | if (!dev->pm_cap) |
cca03dec AL |
645 | return -EIO; |
646 | ||
44e4e66e RW |
647 | if (state < PCI_D0 || state > PCI_D3hot) |
648 | return -EINVAL; | |
649 | ||
1da177e4 | 650 | /* Validate current state: |
f7625980 | 651 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
652 | * to sleep if we're already in a low power state |
653 | */ | |
4a865905 | 654 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 655 | && dev->current_state > state) { |
227f0647 RD |
656 | dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", |
657 | dev->current_state, state); | |
1da177e4 | 658 | return -EINVAL; |
44e4e66e | 659 | } |
1da177e4 | 660 | |
1da177e4 | 661 | /* check if this device supports the desired state */ |
337001b6 RW |
662 | if ((state == PCI_D1 && !dev->d1_support) |
663 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 664 | return -EIO; |
1da177e4 | 665 | |
337001b6 | 666 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 667 | |
32a36585 | 668 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
669 | * This doesn't affect PME_Status, disables PME_En, and |
670 | * sets PowerState to 0. | |
671 | */ | |
32a36585 | 672 | switch (dev->current_state) { |
d3535fbb JL |
673 | case PCI_D0: |
674 | case PCI_D1: | |
675 | case PCI_D2: | |
676 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
677 | pmcsr |= state; | |
678 | break; | |
f62795f1 RW |
679 | case PCI_D3hot: |
680 | case PCI_D3cold: | |
32a36585 JL |
681 | case PCI_UNKNOWN: /* Boot-up */ |
682 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 683 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 684 | need_restore = true; |
32a36585 | 685 | /* Fall-through: force to D0 */ |
32a36585 | 686 | default: |
d3535fbb | 687 | pmcsr = 0; |
32a36585 | 688 | break; |
1da177e4 LT |
689 | } |
690 | ||
691 | /* enter specified state */ | |
337001b6 | 692 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
693 | |
694 | /* Mandatory power management transition delays */ | |
695 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
696 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 697 | pci_dev_d3_sleep(dev); |
1da177e4 | 698 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 699 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 700 | |
e13cdbd7 RW |
701 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
702 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
703 | if (dev->current_state != state && printk_ratelimit()) | |
227f0647 RD |
704 | dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", |
705 | dev->current_state); | |
064b53db | 706 | |
448bd857 HY |
707 | /* |
708 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
709 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
710 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
711 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
712 | * For example, at least some versions of the 3c905B and the | |
713 | * 3c556B exhibit this behaviour. | |
714 | * | |
715 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
716 | * devices in a D3hot state at boot. Consequently, we need to | |
717 | * restore at least the BARs so that the device will be | |
718 | * accessible to its driver. | |
719 | */ | |
720 | if (need_restore) | |
721 | pci_restore_bars(dev); | |
722 | ||
f00a20ef | 723 | if (dev->bus->self) |
7d715a6c SL |
724 | pcie_aspm_pm_state_change(dev->bus->self); |
725 | ||
1da177e4 LT |
726 | return 0; |
727 | } | |
728 | ||
44e4e66e | 729 | /** |
a6a64026 | 730 | * pci_update_current_state - Read power state of given device and cache it |
44e4e66e | 731 | * @dev: PCI device to handle. |
f06fc0b6 | 732 | * @state: State to cache in case the device doesn't have the PM capability |
a6a64026 LW |
733 | * |
734 | * The power state is read from the PMCSR register, which however is | |
735 | * inaccessible in D3cold. The platform firmware is therefore queried first | |
736 | * to detect accessibility of the register. In case the platform firmware | |
737 | * reports an incorrect state or the device isn't power manageable by the | |
738 | * platform at all, we try to detect D3cold by testing accessibility of the | |
739 | * vendor ID in config space. | |
44e4e66e | 740 | */ |
73410429 | 741 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 742 | { |
a6a64026 LW |
743 | if (platform_pci_get_power_state(dev) == PCI_D3cold || |
744 | !pci_device_is_present(dev)) { | |
745 | dev->current_state = PCI_D3cold; | |
746 | } else if (dev->pm_cap) { | |
44e4e66e RW |
747 | u16 pmcsr; |
748 | ||
337001b6 | 749 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 750 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
751 | } else { |
752 | dev->current_state = state; | |
44e4e66e RW |
753 | } |
754 | } | |
755 | ||
db288c9c RW |
756 | /** |
757 | * pci_power_up - Put the given device into D0 forcibly | |
758 | * @dev: PCI device to power up | |
759 | */ | |
760 | void pci_power_up(struct pci_dev *dev) | |
761 | { | |
762 | if (platform_pci_power_manageable(dev)) | |
763 | platform_pci_set_power_state(dev, PCI_D0); | |
764 | ||
765 | pci_raw_set_power_state(dev, PCI_D0); | |
766 | pci_update_current_state(dev, PCI_D0); | |
767 | } | |
768 | ||
0e5dd46b RW |
769 | /** |
770 | * pci_platform_power_transition - Use platform to change device power state | |
771 | * @dev: PCI device to handle. | |
772 | * @state: State to put the device into. | |
773 | */ | |
774 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
775 | { | |
776 | int error; | |
777 | ||
778 | if (platform_pci_power_manageable(dev)) { | |
779 | error = platform_pci_set_power_state(dev, state); | |
780 | if (!error) | |
781 | pci_update_current_state(dev, state); | |
769ba721 | 782 | } else |
0e5dd46b | 783 | error = -ENODEV; |
769ba721 RW |
784 | |
785 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
786 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
787 | |
788 | return error; | |
789 | } | |
790 | ||
0b950f0f SH |
791 | /** |
792 | * pci_wakeup - Wake up a PCI device | |
793 | * @pci_dev: Device to handle. | |
794 | * @ign: ignored parameter | |
795 | */ | |
796 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
797 | { | |
798 | pci_wakeup_event(pci_dev); | |
799 | pm_request_resume(&pci_dev->dev); | |
800 | return 0; | |
801 | } | |
802 | ||
803 | /** | |
804 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
805 | * @bus: Top bus of the subtree to walk. | |
806 | */ | |
807 | static void pci_wakeup_bus(struct pci_bus *bus) | |
808 | { | |
809 | if (bus) | |
810 | pci_walk_bus(bus, pci_wakeup, NULL); | |
811 | } | |
812 | ||
0e5dd46b RW |
813 | /** |
814 | * __pci_start_power_transition - Start power transition of a PCI device | |
815 | * @dev: PCI device to handle. | |
816 | * @state: State to put the device into. | |
817 | */ | |
818 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
819 | { | |
448bd857 | 820 | if (state == PCI_D0) { |
0e5dd46b | 821 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
822 | /* |
823 | * Mandatory power management transition delays, see | |
824 | * PCI Express Base Specification Revision 2.0 Section | |
825 | * 6.6.1: Conventional Reset. Do not delay for | |
826 | * devices powered on/off by corresponding bridge, | |
827 | * because have already delayed for the bridge. | |
828 | */ | |
829 | if (dev->runtime_d3cold) { | |
830 | msleep(dev->d3cold_delay); | |
831 | /* | |
832 | * When powering on a bridge from D3cold, the | |
833 | * whole hierarchy may be powered on into | |
834 | * D0uninitialized state, resume them to give | |
835 | * them a chance to suspend again | |
836 | */ | |
837 | pci_wakeup_bus(dev->subordinate); | |
838 | } | |
839 | } | |
840 | } | |
841 | ||
842 | /** | |
843 | * __pci_dev_set_current_state - Set current state of a PCI device | |
844 | * @dev: Device to handle | |
845 | * @data: pointer to state to be set | |
846 | */ | |
847 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
848 | { | |
849 | pci_power_t state = *(pci_power_t *)data; | |
850 | ||
851 | dev->current_state = state; | |
852 | return 0; | |
853 | } | |
854 | ||
855 | /** | |
856 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
857 | * @bus: Top bus of the subtree to walk. | |
858 | * @state: state to be set | |
859 | */ | |
860 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
861 | { | |
862 | if (bus) | |
863 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
864 | } |
865 | ||
866 | /** | |
867 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
868 | * @dev: PCI device to handle. | |
869 | * @state: State to put the device into. | |
870 | * | |
871 | * This function should not be called directly by device drivers. | |
872 | */ | |
873 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
874 | { | |
448bd857 HY |
875 | int ret; |
876 | ||
db288c9c | 877 | if (state <= PCI_D0) |
448bd857 HY |
878 | return -EINVAL; |
879 | ret = pci_platform_power_transition(dev, state); | |
880 | /* Power off the bridge may power off the whole hierarchy */ | |
881 | if (!ret && state == PCI_D3cold) | |
882 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
883 | return ret; | |
0e5dd46b RW |
884 | } |
885 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
886 | ||
44e4e66e RW |
887 | /** |
888 | * pci_set_power_state - Set the power state of a PCI device | |
889 | * @dev: PCI device to handle. | |
890 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
891 | * | |
877d0310 | 892 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
893 | * the device's PCI PM registers. |
894 | * | |
895 | * RETURN VALUE: | |
896 | * -EINVAL if the requested state is invalid. | |
897 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
898 | * wrong version, or device doesn't support the requested state. | |
899 | * 0 if device already is in the requested state. | |
900 | * 0 if device's power state has been successfully changed. | |
901 | */ | |
902 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
903 | { | |
337001b6 | 904 | int error; |
44e4e66e RW |
905 | |
906 | /* bound the state we're entering */ | |
448bd857 HY |
907 | if (state > PCI_D3cold) |
908 | state = PCI_D3cold; | |
44e4e66e RW |
909 | else if (state < PCI_D0) |
910 | state = PCI_D0; | |
911 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
912 | /* | |
913 | * If the device or the parent bridge do not support PCI PM, | |
914 | * ignore the request if we're doing anything other than putting | |
915 | * it into D0 (which would only happen on boot). | |
916 | */ | |
917 | return 0; | |
918 | ||
db288c9c RW |
919 | /* Check if we're already there */ |
920 | if (dev->current_state == state) | |
921 | return 0; | |
922 | ||
0e5dd46b RW |
923 | __pci_start_power_transition(dev, state); |
924 | ||
979b1791 AC |
925 | /* This device is quirked not to be put into D3, so |
926 | don't put it in D3 */ | |
448bd857 | 927 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 928 | return 0; |
44e4e66e | 929 | |
448bd857 HY |
930 | /* |
931 | * To put device in D3cold, we put device into D3hot in native | |
932 | * way, then put device into D3cold with platform ops | |
933 | */ | |
934 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
935 | PCI_D3hot : state); | |
44e4e66e | 936 | |
0e5dd46b RW |
937 | if (!__pci_complete_power_transition(dev, state)) |
938 | error = 0; | |
44e4e66e RW |
939 | |
940 | return error; | |
941 | } | |
b7fe9434 | 942 | EXPORT_SYMBOL(pci_set_power_state); |
44e4e66e | 943 | |
1da177e4 LT |
944 | /** |
945 | * pci_choose_state - Choose the power state of a PCI device | |
946 | * @dev: PCI device to be suspended | |
947 | * @state: target sleep state for the whole system. This is the value | |
948 | * that is passed to suspend() function. | |
949 | * | |
950 | * Returns PCI power state suitable for given device and given system | |
951 | * message. | |
952 | */ | |
953 | ||
954 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
955 | { | |
ab826ca4 | 956 | pci_power_t ret; |
0f64474b | 957 | |
728cdb75 | 958 | if (!dev->pm_cap) |
1da177e4 LT |
959 | return PCI_D0; |
960 | ||
961d9120 RW |
961 | ret = platform_pci_choose_state(dev); |
962 | if (ret != PCI_POWER_ERROR) | |
963 | return ret; | |
ca078bae PM |
964 | |
965 | switch (state.event) { | |
966 | case PM_EVENT_ON: | |
967 | return PCI_D0; | |
968 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
969 | case PM_EVENT_PRETHAW: |
970 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 971 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 972 | case PM_EVENT_HIBERNATE: |
ca078bae | 973 | return PCI_D3hot; |
1da177e4 | 974 | default: |
80ccba11 BH |
975 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
976 | state.event); | |
1da177e4 LT |
977 | BUG(); |
978 | } | |
979 | return PCI_D0; | |
980 | } | |
1da177e4 LT |
981 | EXPORT_SYMBOL(pci_choose_state); |
982 | ||
89858517 YZ |
983 | #define PCI_EXP_SAVE_REGS 7 |
984 | ||
fd0f7f73 AW |
985 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
986 | u16 cap, bool extended) | |
34a4876e YL |
987 | { |
988 | struct pci_cap_saved_state *tmp; | |
34a4876e | 989 | |
b67bfe0d | 990 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 991 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
992 | return tmp; |
993 | } | |
994 | return NULL; | |
995 | } | |
996 | ||
fd0f7f73 AW |
997 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
998 | { | |
999 | return _pci_find_saved_cap(dev, cap, false); | |
1000 | } | |
1001 | ||
1002 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
1003 | { | |
1004 | return _pci_find_saved_cap(dev, cap, true); | |
1005 | } | |
1006 | ||
b56a5a23 MT |
1007 | static int pci_save_pcie_state(struct pci_dev *dev) |
1008 | { | |
59875ae4 | 1009 | int i = 0; |
b56a5a23 MT |
1010 | struct pci_cap_saved_state *save_state; |
1011 | u16 *cap; | |
1012 | ||
59875ae4 | 1013 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
1014 | return 0; |
1015 | ||
9f35575d | 1016 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 1017 | if (!save_state) { |
e496b617 | 1018 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
1019 | return -ENOMEM; |
1020 | } | |
63f4898a | 1021 | |
59875ae4 JL |
1022 | cap = (u16 *)&save_state->cap.data[0]; |
1023 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
1024 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1025 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1026 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1027 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1028 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1029 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1030 | |
b56a5a23 MT |
1031 | return 0; |
1032 | } | |
1033 | ||
1034 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
1035 | { | |
59875ae4 | 1036 | int i = 0; |
b56a5a23 MT |
1037 | struct pci_cap_saved_state *save_state; |
1038 | u16 *cap; | |
1039 | ||
1040 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1041 | if (!save_state) |
9cb604ed MS |
1042 | return; |
1043 | ||
59875ae4 JL |
1044 | cap = (u16 *)&save_state->cap.data[0]; |
1045 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1046 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1047 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1048 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1049 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1050 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1051 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1052 | } |
1053 | ||
cc692a5f SH |
1054 | |
1055 | static int pci_save_pcix_state(struct pci_dev *dev) | |
1056 | { | |
63f4898a | 1057 | int pos; |
cc692a5f | 1058 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1059 | |
1060 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1061 | if (!pos) |
cc692a5f SH |
1062 | return 0; |
1063 | ||
f34303de | 1064 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1065 | if (!save_state) { |
e496b617 | 1066 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1067 | return -ENOMEM; |
1068 | } | |
cc692a5f | 1069 | |
24a4742f AW |
1070 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1071 | (u16 *)save_state->cap.data); | |
63f4898a | 1072 | |
cc692a5f SH |
1073 | return 0; |
1074 | } | |
1075 | ||
1076 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1077 | { | |
1078 | int i = 0, pos; | |
1079 | struct pci_cap_saved_state *save_state; | |
1080 | u16 *cap; | |
1081 | ||
1082 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1083 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1084 | if (!save_state || !pos) |
cc692a5f | 1085 | return; |
24a4742f | 1086 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1087 | |
1088 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1089 | } |
1090 | ||
1091 | ||
1da177e4 LT |
1092 | /** |
1093 | * pci_save_state - save the PCI configuration space of a device before suspending | |
1094 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1095 | */ |
3c78bc61 | 1096 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1097 | { |
1098 | int i; | |
1099 | /* XXX: 100% dword access ok here? */ | |
1100 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1101 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1102 | dev->state_saved = true; |
79e50e72 QL |
1103 | |
1104 | i = pci_save_pcie_state(dev); | |
1105 | if (i != 0) | |
b56a5a23 | 1106 | return i; |
79e50e72 QL |
1107 | |
1108 | i = pci_save_pcix_state(dev); | |
1109 | if (i != 0) | |
cc692a5f | 1110 | return i; |
79e50e72 | 1111 | |
754834b9 | 1112 | return pci_save_vc_state(dev); |
1da177e4 | 1113 | } |
b7fe9434 | 1114 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1115 | |
ebfc5b80 RW |
1116 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
1117 | u32 saved_val, int retry) | |
1118 | { | |
1119 | u32 val; | |
1120 | ||
1121 | pci_read_config_dword(pdev, offset, &val); | |
1122 | if (val == saved_val) | |
1123 | return; | |
1124 | ||
1125 | for (;;) { | |
227f0647 RD |
1126 | dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
1127 | offset, val, saved_val); | |
ebfc5b80 RW |
1128 | pci_write_config_dword(pdev, offset, saved_val); |
1129 | if (retry-- <= 0) | |
1130 | return; | |
1131 | ||
1132 | pci_read_config_dword(pdev, offset, &val); | |
1133 | if (val == saved_val) | |
1134 | return; | |
1135 | ||
1136 | mdelay(1); | |
1137 | } | |
1138 | } | |
1139 | ||
a6cb9ee7 RW |
1140 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
1141 | int start, int end, int retry) | |
ebfc5b80 RW |
1142 | { |
1143 | int index; | |
1144 | ||
1145 | for (index = end; index >= start; index--) | |
1146 | pci_restore_config_dword(pdev, 4 * index, | |
1147 | pdev->saved_config_space[index], | |
1148 | retry); | |
1149 | } | |
1150 | ||
a6cb9ee7 RW |
1151 | static void pci_restore_config_space(struct pci_dev *pdev) |
1152 | { | |
1153 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
1154 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
1155 | /* Restore BARs before the command register. */ | |
1156 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
1157 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
1158 | } else { | |
1159 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
1160 | } | |
1161 | } | |
1162 | ||
f7625980 | 1163 | /** |
1da177e4 LT |
1164 | * pci_restore_state - Restore the saved state of a PCI device |
1165 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1166 | */ |
1d3c16a8 | 1167 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1168 | { |
c82f63e4 | 1169 | if (!dev->state_saved) |
1d3c16a8 | 1170 | return; |
4b77b0a2 | 1171 | |
b56a5a23 MT |
1172 | /* PCI Express register must be restored first */ |
1173 | pci_restore_pcie_state(dev); | |
1900ca13 | 1174 | pci_restore_ats_state(dev); |
425c1b22 | 1175 | pci_restore_vc_state(dev); |
b56a5a23 | 1176 | |
b07461a8 TI |
1177 | pci_cleanup_aer_error_status_regs(dev); |
1178 | ||
a6cb9ee7 | 1179 | pci_restore_config_space(dev); |
ebfc5b80 | 1180 | |
cc692a5f | 1181 | pci_restore_pcix_state(dev); |
41017f0c | 1182 | pci_restore_msi_state(dev); |
ccbc175a AD |
1183 | |
1184 | /* Restore ACS and IOV configuration state */ | |
1185 | pci_enable_acs(dev); | |
8c5cdb6a | 1186 | pci_restore_iov_state(dev); |
8fed4b65 | 1187 | |
4b77b0a2 | 1188 | dev->state_saved = false; |
1da177e4 | 1189 | } |
b7fe9434 | 1190 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1191 | |
ffbdd3f7 AW |
1192 | struct pci_saved_state { |
1193 | u32 config_space[16]; | |
1194 | struct pci_cap_saved_data cap[0]; | |
1195 | }; | |
1196 | ||
1197 | /** | |
1198 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1199 | * the device saved state. | |
1200 | * @dev: PCI device that we're dealing with | |
1201 | * | |
f7625980 | 1202 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1203 | */ |
1204 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1205 | { | |
1206 | struct pci_saved_state *state; | |
1207 | struct pci_cap_saved_state *tmp; | |
1208 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1209 | size_t size; |
1210 | ||
1211 | if (!dev->state_saved) | |
1212 | return NULL; | |
1213 | ||
1214 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1215 | ||
b67bfe0d | 1216 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1217 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1218 | ||
1219 | state = kzalloc(size, GFP_KERNEL); | |
1220 | if (!state) | |
1221 | return NULL; | |
1222 | ||
1223 | memcpy(state->config_space, dev->saved_config_space, | |
1224 | sizeof(state->config_space)); | |
1225 | ||
1226 | cap = state->cap; | |
b67bfe0d | 1227 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1228 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1229 | memcpy(cap, &tmp->cap, len); | |
1230 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1231 | } | |
1232 | /* Empty cap_save terminates list */ | |
1233 | ||
1234 | return state; | |
1235 | } | |
1236 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1237 | ||
1238 | /** | |
1239 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1240 | * @dev: PCI device that we're dealing with | |
1241 | * @state: Saved state returned from pci_store_saved_state() | |
1242 | */ | |
98d9b271 KRW |
1243 | int pci_load_saved_state(struct pci_dev *dev, |
1244 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1245 | { |
1246 | struct pci_cap_saved_data *cap; | |
1247 | ||
1248 | dev->state_saved = false; | |
1249 | ||
1250 | if (!state) | |
1251 | return 0; | |
1252 | ||
1253 | memcpy(dev->saved_config_space, state->config_space, | |
1254 | sizeof(state->config_space)); | |
1255 | ||
1256 | cap = state->cap; | |
1257 | while (cap->size) { | |
1258 | struct pci_cap_saved_state *tmp; | |
1259 | ||
fd0f7f73 | 1260 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1261 | if (!tmp || tmp->cap.size != cap->size) |
1262 | return -EINVAL; | |
1263 | ||
1264 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1265 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1266 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1267 | } | |
1268 | ||
1269 | dev->state_saved = true; | |
1270 | return 0; | |
1271 | } | |
98d9b271 | 1272 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1273 | |
1274 | /** | |
1275 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1276 | * and free the memory allocated for it. | |
1277 | * @dev: PCI device that we're dealing with | |
1278 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1279 | */ | |
1280 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1281 | struct pci_saved_state **state) | |
1282 | { | |
1283 | int ret = pci_load_saved_state(dev, *state); | |
1284 | kfree(*state); | |
1285 | *state = NULL; | |
1286 | return ret; | |
1287 | } | |
1288 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1289 | ||
8a9d5609 BH |
1290 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1291 | { | |
1292 | return pci_enable_resources(dev, bars); | |
1293 | } | |
1294 | ||
38cc1302 HS |
1295 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1296 | { | |
1297 | int err; | |
1f6ae47e | 1298 | struct pci_dev *bridge; |
1e2571a7 BH |
1299 | u16 cmd; |
1300 | u8 pin; | |
38cc1302 HS |
1301 | |
1302 | err = pci_set_power_state(dev, PCI_D0); | |
1303 | if (err < 0 && err != -EIO) | |
1304 | return err; | |
1f6ae47e VS |
1305 | |
1306 | bridge = pci_upstream_bridge(dev); | |
1307 | if (bridge) | |
1308 | pcie_aspm_powersave_config_link(bridge); | |
1309 | ||
38cc1302 HS |
1310 | err = pcibios_enable_device(dev, bars); |
1311 | if (err < 0) | |
1312 | return err; | |
1313 | pci_fixup_device(pci_fixup_enable, dev); | |
1314 | ||
866d5417 BH |
1315 | if (dev->msi_enabled || dev->msix_enabled) |
1316 | return 0; | |
1317 | ||
1e2571a7 BH |
1318 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1319 | if (pin) { | |
1320 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1321 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1322 | pci_write_config_word(dev, PCI_COMMAND, | |
1323 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1324 | } | |
1325 | ||
38cc1302 HS |
1326 | return 0; |
1327 | } | |
1328 | ||
1329 | /** | |
0b62e13b | 1330 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1331 | * @dev: PCI device to be resumed |
1332 | * | |
1333 | * Note this function is a backend of pci_default_resume and is not supposed | |
1334 | * to be called by normal code, write proper resume handler and use it instead. | |
1335 | */ | |
0b62e13b | 1336 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1337 | { |
296ccb08 | 1338 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1339 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1340 | return 0; | |
1341 | } | |
b7fe9434 | 1342 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1343 | |
928bea96 YL |
1344 | static void pci_enable_bridge(struct pci_dev *dev) |
1345 | { | |
79272138 | 1346 | struct pci_dev *bridge; |
928bea96 YL |
1347 | int retval; |
1348 | ||
79272138 BH |
1349 | bridge = pci_upstream_bridge(dev); |
1350 | if (bridge) | |
1351 | pci_enable_bridge(bridge); | |
928bea96 | 1352 | |
cf3e1feb | 1353 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1354 | if (!dev->is_busmaster) |
cf3e1feb | 1355 | pci_set_master(dev); |
928bea96 | 1356 | return; |
cf3e1feb YL |
1357 | } |
1358 | ||
928bea96 YL |
1359 | retval = pci_enable_device(dev); |
1360 | if (retval) | |
1361 | dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", | |
1362 | retval); | |
1363 | pci_set_master(dev); | |
1364 | } | |
1365 | ||
b4b4fbba | 1366 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1367 | { |
79272138 | 1368 | struct pci_dev *bridge; |
1da177e4 | 1369 | int err; |
b718989d | 1370 | int i, bars = 0; |
1da177e4 | 1371 | |
97c145f7 JB |
1372 | /* |
1373 | * Power state could be unknown at this point, either due to a fresh | |
1374 | * boot or a device removal call. So get the current power state | |
1375 | * so that things like MSI message writing will behave as expected | |
1376 | * (e.g. if the device really is in D0 at enable time). | |
1377 | */ | |
1378 | if (dev->pm_cap) { | |
1379 | u16 pmcsr; | |
1380 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1381 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1382 | } | |
1383 | ||
cc7ba39b | 1384 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1385 | return 0; /* already enabled */ |
1386 | ||
79272138 BH |
1387 | bridge = pci_upstream_bridge(dev); |
1388 | if (bridge) | |
1389 | pci_enable_bridge(bridge); | |
928bea96 | 1390 | |
497f16f2 YL |
1391 | /* only skip sriov related */ |
1392 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1393 | if (dev->resource[i].flags & flags) | |
1394 | bars |= (1 << i); | |
1395 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1396 | if (dev->resource[i].flags & flags) |
1397 | bars |= (1 << i); | |
1398 | ||
38cc1302 | 1399 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1400 | if (err < 0) |
38cc1302 | 1401 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1402 | return err; |
1da177e4 LT |
1403 | } |
1404 | ||
b718989d BH |
1405 | /** |
1406 | * pci_enable_device_io - Initialize a device for use with IO space | |
1407 | * @dev: PCI device to be initialized | |
1408 | * | |
1409 | * Initialize device before it's used by a driver. Ask low-level code | |
1410 | * to enable I/O resources. Wake up the device if it was suspended. | |
1411 | * Beware, this function can fail. | |
1412 | */ | |
1413 | int pci_enable_device_io(struct pci_dev *dev) | |
1414 | { | |
b4b4fbba | 1415 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1416 | } |
b7fe9434 | 1417 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1418 | |
1419 | /** | |
1420 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1421 | * @dev: PCI device to be initialized | |
1422 | * | |
1423 | * Initialize device before it's used by a driver. Ask low-level code | |
1424 | * to enable Memory resources. Wake up the device if it was suspended. | |
1425 | * Beware, this function can fail. | |
1426 | */ | |
1427 | int pci_enable_device_mem(struct pci_dev *dev) | |
1428 | { | |
b4b4fbba | 1429 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1430 | } |
b7fe9434 | 1431 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1432 | |
bae94d02 IPG |
1433 | /** |
1434 | * pci_enable_device - Initialize device before it's used by a driver. | |
1435 | * @dev: PCI device to be initialized | |
1436 | * | |
1437 | * Initialize device before it's used by a driver. Ask low-level code | |
1438 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1439 | * Beware, this function can fail. | |
1440 | * | |
1441 | * Note we don't actually enable the device many times if we call | |
1442 | * this function repeatedly (we just increment the count). | |
1443 | */ | |
1444 | int pci_enable_device(struct pci_dev *dev) | |
1445 | { | |
b4b4fbba | 1446 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1447 | } |
b7fe9434 | 1448 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1449 | |
9ac7849e TH |
1450 | /* |
1451 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1452 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1453 | * there's no need to track it separately. pci_devres is initialized | |
1454 | * when a device is enabled using managed PCI device enable interface. | |
1455 | */ | |
1456 | struct pci_devres { | |
7f375f32 TH |
1457 | unsigned int enabled:1; |
1458 | unsigned int pinned:1; | |
9ac7849e TH |
1459 | unsigned int orig_intx:1; |
1460 | unsigned int restore_intx:1; | |
1461 | u32 region_mask; | |
1462 | }; | |
1463 | ||
1464 | static void pcim_release(struct device *gendev, void *res) | |
1465 | { | |
f3d2f165 | 1466 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
1467 | struct pci_devres *this = res; |
1468 | int i; | |
1469 | ||
1470 | if (dev->msi_enabled) | |
1471 | pci_disable_msi(dev); | |
1472 | if (dev->msix_enabled) | |
1473 | pci_disable_msix(dev); | |
1474 | ||
1475 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1476 | if (this->region_mask & (1 << i)) | |
1477 | pci_release_region(dev, i); | |
1478 | ||
1479 | if (this->restore_intx) | |
1480 | pci_intx(dev, this->orig_intx); | |
1481 | ||
7f375f32 | 1482 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1483 | pci_disable_device(dev); |
1484 | } | |
1485 | ||
07656d83 | 1486 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1487 | { |
1488 | struct pci_devres *dr, *new_dr; | |
1489 | ||
1490 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1491 | if (dr) | |
1492 | return dr; | |
1493 | ||
1494 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1495 | if (!new_dr) | |
1496 | return NULL; | |
1497 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1498 | } | |
1499 | ||
07656d83 | 1500 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1501 | { |
1502 | if (pci_is_managed(pdev)) | |
1503 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1504 | return NULL; | |
1505 | } | |
1506 | ||
1507 | /** | |
1508 | * pcim_enable_device - Managed pci_enable_device() | |
1509 | * @pdev: PCI device to be initialized | |
1510 | * | |
1511 | * Managed pci_enable_device(). | |
1512 | */ | |
1513 | int pcim_enable_device(struct pci_dev *pdev) | |
1514 | { | |
1515 | struct pci_devres *dr; | |
1516 | int rc; | |
1517 | ||
1518 | dr = get_pci_dr(pdev); | |
1519 | if (unlikely(!dr)) | |
1520 | return -ENOMEM; | |
b95d58ea TH |
1521 | if (dr->enabled) |
1522 | return 0; | |
9ac7849e TH |
1523 | |
1524 | rc = pci_enable_device(pdev); | |
1525 | if (!rc) { | |
1526 | pdev->is_managed = 1; | |
7f375f32 | 1527 | dr->enabled = 1; |
9ac7849e TH |
1528 | } |
1529 | return rc; | |
1530 | } | |
b7fe9434 | 1531 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1532 | |
1533 | /** | |
1534 | * pcim_pin_device - Pin managed PCI device | |
1535 | * @pdev: PCI device to pin | |
1536 | * | |
1537 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1538 | * driver detach. @pdev must have been enabled with | |
1539 | * pcim_enable_device(). | |
1540 | */ | |
1541 | void pcim_pin_device(struct pci_dev *pdev) | |
1542 | { | |
1543 | struct pci_devres *dr; | |
1544 | ||
1545 | dr = find_pci_dr(pdev); | |
7f375f32 | 1546 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1547 | if (dr) |
7f375f32 | 1548 | dr->pinned = 1; |
9ac7849e | 1549 | } |
b7fe9434 | 1550 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1551 | |
eca0d467 MG |
1552 | /* |
1553 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1554 | * @dev: the PCI device being added | |
1555 | * | |
1556 | * Permits the platform to provide architecture specific functionality when | |
1557 | * devices are added. This is the default implementation. Architecture | |
1558 | * implementations can override this. | |
1559 | */ | |
3c78bc61 | 1560 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
1561 | { |
1562 | return 0; | |
1563 | } | |
1564 | ||
6ae32c53 SO |
1565 | /** |
1566 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1567 | * @dev: the PCI device being released | |
1568 | * | |
1569 | * Permits the platform to provide architecture specific functionality when | |
1570 | * devices are released. This is the default implementation. Architecture | |
1571 | * implementations can override this. | |
1572 | */ | |
1573 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1574 | ||
1da177e4 LT |
1575 | /** |
1576 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1577 | * @dev: the PCI device to disable | |
1578 | * | |
1579 | * Disables architecture specific PCI resources for the device. This | |
1580 | * is the default implementation. Architecture implementations can | |
1581 | * override this. | |
1582 | */ | |
ff3ce480 | 1583 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 1584 | |
a43ae58c HG |
1585 | /** |
1586 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1587 | * @irq: ISA IRQ to penalize | |
1588 | * @active: IRQ active or not | |
1589 | * | |
1590 | * Permits the platform to provide architecture-specific functionality when | |
1591 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1592 | * implementations can override this. | |
1593 | */ | |
1594 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1595 | ||
fa58d305 RW |
1596 | static void do_pci_disable_device(struct pci_dev *dev) |
1597 | { | |
1598 | u16 pci_command; | |
1599 | ||
1600 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1601 | if (pci_command & PCI_COMMAND_MASTER) { | |
1602 | pci_command &= ~PCI_COMMAND_MASTER; | |
1603 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1604 | } | |
1605 | ||
1606 | pcibios_disable_device(dev); | |
1607 | } | |
1608 | ||
1609 | /** | |
1610 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1611 | * @dev: PCI device to disable | |
1612 | * | |
1613 | * NOTE: This function is a backend of PCI power management routines and is | |
1614 | * not supposed to be called drivers. | |
1615 | */ | |
1616 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1617 | { | |
296ccb08 | 1618 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1619 | do_pci_disable_device(dev); |
1620 | } | |
1621 | ||
1da177e4 LT |
1622 | /** |
1623 | * pci_disable_device - Disable PCI device after use | |
1624 | * @dev: PCI device to be disabled | |
1625 | * | |
1626 | * Signal to the system that the PCI device is not in use by the system | |
1627 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1628 | * |
1629 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1630 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 1631 | */ |
3c78bc61 | 1632 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 1633 | { |
9ac7849e | 1634 | struct pci_devres *dr; |
99dc804d | 1635 | |
9ac7849e TH |
1636 | dr = find_pci_dr(dev); |
1637 | if (dr) | |
7f375f32 | 1638 | dr->enabled = 0; |
9ac7849e | 1639 | |
fd6dceab KK |
1640 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1641 | "disabling already-disabled device"); | |
1642 | ||
cc7ba39b | 1643 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1644 | return; |
1645 | ||
fa58d305 | 1646 | do_pci_disable_device(dev); |
1da177e4 | 1647 | |
fa58d305 | 1648 | dev->is_busmaster = 0; |
1da177e4 | 1649 | } |
b7fe9434 | 1650 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1651 | |
f7bdd12d BK |
1652 | /** |
1653 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1654 | * @dev: the PCIe device reset |
f7bdd12d BK |
1655 | * @state: Reset state to enter into |
1656 | * | |
1657 | * | |
45e829ea | 1658 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1659 | * implementation. Architecture implementations can override this. |
1660 | */ | |
d6d88c83 BH |
1661 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1662 | enum pcie_reset_state state) | |
f7bdd12d BK |
1663 | { |
1664 | return -EINVAL; | |
1665 | } | |
1666 | ||
1667 | /** | |
1668 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1669 | * @dev: the PCIe device reset |
f7bdd12d BK |
1670 | * @state: Reset state to enter into |
1671 | * | |
1672 | * | |
1673 | * Sets the PCI reset state for the device. | |
1674 | */ | |
1675 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1676 | { | |
1677 | return pcibios_set_pcie_reset_state(dev, state); | |
1678 | } | |
b7fe9434 | 1679 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 1680 | |
58ff4633 RW |
1681 | /** |
1682 | * pci_check_pme_status - Check if given device has generated PME. | |
1683 | * @dev: Device to check. | |
1684 | * | |
1685 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1686 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1687 | * 'false' otherwise. | |
1688 | */ | |
1689 | bool pci_check_pme_status(struct pci_dev *dev) | |
1690 | { | |
1691 | int pmcsr_pos; | |
1692 | u16 pmcsr; | |
1693 | bool ret = false; | |
1694 | ||
1695 | if (!dev->pm_cap) | |
1696 | return false; | |
1697 | ||
1698 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1699 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1700 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1701 | return false; | |
1702 | ||
1703 | /* Clear PME status. */ | |
1704 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1705 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1706 | /* Disable PME to avoid interrupt flood. */ | |
1707 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1708 | ret = true; | |
1709 | } | |
1710 | ||
1711 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1712 | ||
1713 | return ret; | |
1714 | } | |
1715 | ||
b67ea761 RW |
1716 | /** |
1717 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1718 | * @dev: Device to handle. | |
379021d5 | 1719 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1720 | * |
1721 | * Check if @dev has generated PME and queue a resume request for it in that | |
1722 | * case. | |
1723 | */ | |
379021d5 | 1724 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1725 | { |
379021d5 RW |
1726 | if (pme_poll_reset && dev->pme_poll) |
1727 | dev->pme_poll = false; | |
1728 | ||
c125e96f | 1729 | if (pci_check_pme_status(dev)) { |
c125e96f | 1730 | pci_wakeup_event(dev); |
0f953bf6 | 1731 | pm_request_resume(&dev->dev); |
c125e96f | 1732 | } |
b67ea761 RW |
1733 | return 0; |
1734 | } | |
1735 | ||
1736 | /** | |
1737 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1738 | * @bus: Top bus of the subtree to walk. | |
1739 | */ | |
1740 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1741 | { | |
1742 | if (bus) | |
379021d5 | 1743 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1744 | } |
1745 | ||
448bd857 | 1746 | |
eb9d0fe4 RW |
1747 | /** |
1748 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1749 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1750 | * @state: PCI state from which device will issue PME#. |
1751 | */ | |
e5899e1b | 1752 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1753 | { |
337001b6 | 1754 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1755 | return false; |
1756 | ||
337001b6 | 1757 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 1758 | } |
b7fe9434 | 1759 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 1760 | |
df17e62e MG |
1761 | static void pci_pme_list_scan(struct work_struct *work) |
1762 | { | |
379021d5 | 1763 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1764 | |
1765 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
1766 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1767 | if (pme_dev->dev->pme_poll) { | |
1768 | struct pci_dev *bridge; | |
1769 | ||
1770 | bridge = pme_dev->dev->bus->self; | |
1771 | /* | |
1772 | * If bridge is in low power state, the | |
1773 | * configuration space of subordinate devices | |
1774 | * may be not accessible | |
1775 | */ | |
1776 | if (bridge && bridge->current_state != PCI_D0) | |
1777 | continue; | |
1778 | pci_pme_wakeup(pme_dev->dev, NULL); | |
1779 | } else { | |
1780 | list_del(&pme_dev->list); | |
1781 | kfree(pme_dev); | |
379021d5 | 1782 | } |
df17e62e | 1783 | } |
ce300008 BH |
1784 | if (!list_empty(&pci_pme_list)) |
1785 | schedule_delayed_work(&pci_pme_work, | |
1786 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1787 | mutex_unlock(&pci_pme_list_mutex); |
1788 | } | |
1789 | ||
2cef548a | 1790 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1791 | { |
1792 | u16 pmcsr; | |
1793 | ||
ffaddbe8 | 1794 | if (!dev->pme_support) |
eb9d0fe4 RW |
1795 | return; |
1796 | ||
337001b6 | 1797 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1798 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1799 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1800 | if (!enable) | |
1801 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1802 | ||
337001b6 | 1803 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
1804 | } |
1805 | ||
1806 | /** | |
1807 | * pci_pme_active - enable or disable PCI device's PME# function | |
1808 | * @dev: PCI device to handle. | |
1809 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
1810 | * | |
1811 | * The caller must verify that the device is capable of generating PME# before | |
1812 | * calling this function with @enable equal to 'true'. | |
1813 | */ | |
1814 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
1815 | { | |
1816 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 1817 | |
6e965e0d HY |
1818 | /* |
1819 | * PCI (as opposed to PCIe) PME requires that the device have | |
1820 | * its PME# line hooked up correctly. Not all hardware vendors | |
1821 | * do this, so the PME never gets delivered and the device | |
1822 | * remains asleep. The easiest way around this is to | |
1823 | * periodically walk the list of suspended devices and check | |
1824 | * whether any have their PME flag set. The assumption is that | |
1825 | * we'll wake up often enough anyway that this won't be a huge | |
1826 | * hit, and the power savings from the devices will still be a | |
1827 | * win. | |
1828 | * | |
1829 | * Although PCIe uses in-band PME message instead of PME# line | |
1830 | * to report PME, PME does not work for some PCIe devices in | |
1831 | * reality. For example, there are devices that set their PME | |
1832 | * status bits, but don't really bother to send a PME message; | |
1833 | * there are PCI Express Root Ports that don't bother to | |
1834 | * trigger interrupts when they receive PME messages from the | |
1835 | * devices below. So PME poll is used for PCIe devices too. | |
1836 | */ | |
df17e62e | 1837 | |
379021d5 | 1838 | if (dev->pme_poll) { |
df17e62e MG |
1839 | struct pci_pme_device *pme_dev; |
1840 | if (enable) { | |
1841 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1842 | GFP_KERNEL); | |
0394cb19 BH |
1843 | if (!pme_dev) { |
1844 | dev_warn(&dev->dev, "can't enable PME#\n"); | |
1845 | return; | |
1846 | } | |
df17e62e MG |
1847 | pme_dev->dev = dev; |
1848 | mutex_lock(&pci_pme_list_mutex); | |
1849 | list_add(&pme_dev->list, &pci_pme_list); | |
1850 | if (list_is_singular(&pci_pme_list)) | |
1851 | schedule_delayed_work(&pci_pme_work, | |
1852 | msecs_to_jiffies(PME_TIMEOUT)); | |
1853 | mutex_unlock(&pci_pme_list_mutex); | |
1854 | } else { | |
1855 | mutex_lock(&pci_pme_list_mutex); | |
1856 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1857 | if (pme_dev->dev == dev) { | |
1858 | list_del(&pme_dev->list); | |
1859 | kfree(pme_dev); | |
1860 | break; | |
1861 | } | |
1862 | } | |
1863 | mutex_unlock(&pci_pme_list_mutex); | |
1864 | } | |
1865 | } | |
1866 | ||
85b8582d | 1867 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 1868 | } |
b7fe9434 | 1869 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 1870 | |
1da177e4 | 1871 | /** |
6cbf8214 | 1872 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1873 | * @dev: PCI device affected |
1874 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1875 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1876 | * @enable: True to enable event generation; false to disable |
1877 | * | |
1878 | * This enables the device as a wakeup event source, or disables it. | |
1879 | * When such events involves platform-specific hooks, those hooks are | |
1880 | * called automatically by this routine. | |
1881 | * | |
1882 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1883 | * always require such platform hooks. |
075c1771 | 1884 | * |
eb9d0fe4 RW |
1885 | * RETURN VALUE: |
1886 | * 0 is returned on success | |
1887 | * -EINVAL is returned if device is not supposed to wake up the system | |
1888 | * Error code depending on the platform is returned if both the platform and | |
1889 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1890 | */ |
6cbf8214 RW |
1891 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1892 | bool runtime, bool enable) | |
1da177e4 | 1893 | { |
5bcc2fb4 | 1894 | int ret = 0; |
075c1771 | 1895 | |
6cbf8214 | 1896 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1897 | return -EINVAL; |
1da177e4 | 1898 | |
e80bb09d RW |
1899 | /* Don't do the same thing twice in a row for one device. */ |
1900 | if (!!enable == !!dev->wakeup_prepared) | |
1901 | return 0; | |
1902 | ||
eb9d0fe4 RW |
1903 | /* |
1904 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1905 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1906 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1907 | */ |
1da177e4 | 1908 | |
5bcc2fb4 RW |
1909 | if (enable) { |
1910 | int error; | |
1da177e4 | 1911 | |
5bcc2fb4 RW |
1912 | if (pci_pme_capable(dev, state)) |
1913 | pci_pme_active(dev, true); | |
1914 | else | |
1915 | ret = 1; | |
6cbf8214 RW |
1916 | error = runtime ? platform_pci_run_wake(dev, true) : |
1917 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1918 | if (ret) |
1919 | ret = error; | |
e80bb09d RW |
1920 | if (!ret) |
1921 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1922 | } else { |
6cbf8214 RW |
1923 | if (runtime) |
1924 | platform_pci_run_wake(dev, false); | |
1925 | else | |
1926 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1927 | pci_pme_active(dev, false); |
e80bb09d | 1928 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1929 | } |
1da177e4 | 1930 | |
5bcc2fb4 | 1931 | return ret; |
eb9d0fe4 | 1932 | } |
6cbf8214 | 1933 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1934 | |
0235c4fc RW |
1935 | /** |
1936 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1937 | * @dev: PCI device to prepare | |
1938 | * @enable: True to enable wake-up event generation; false to disable | |
1939 | * | |
1940 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1941 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1942 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1943 | * ordering constraints. | |
1944 | * | |
1945 | * This function only returns error code if the device is not capable of | |
1946 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1947 | * enable wake-up power for it. | |
1948 | */ | |
1949 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1950 | { | |
1951 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1952 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1953 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1954 | } | |
b7fe9434 | 1955 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 1956 | |
404cc2d8 | 1957 | /** |
37139074 JB |
1958 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1959 | * @dev: PCI device | |
1960 | * | |
1961 | * Use underlying platform code to find a supported low power state for @dev. | |
1962 | * If the platform can't manage @dev, return the deepest state from which it | |
1963 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1964 | */ |
0b950f0f | 1965 | static pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1966 | { |
1967 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1968 | |
1969 | if (platform_pci_power_manageable(dev)) { | |
1970 | /* | |
1971 | * Call the platform to choose the target state of the device | |
1972 | * and enable wake-up from this state if supported. | |
1973 | */ | |
1974 | pci_power_t state = platform_pci_choose_state(dev); | |
1975 | ||
1976 | switch (state) { | |
1977 | case PCI_POWER_ERROR: | |
1978 | case PCI_UNKNOWN: | |
1979 | break; | |
1980 | case PCI_D1: | |
1981 | case PCI_D2: | |
1982 | if (pci_no_d1d2(dev)) | |
1983 | break; | |
1984 | default: | |
1985 | target_state = state; | |
404cc2d8 | 1986 | } |
4132a577 LW |
1987 | |
1988 | return target_state; | |
1989 | } | |
1990 | ||
1991 | if (!dev->pm_cap) | |
d2abdf62 | 1992 | target_state = PCI_D0; |
4132a577 LW |
1993 | |
1994 | /* | |
1995 | * If the device is in D3cold even though it's not power-manageable by | |
1996 | * the platform, it may have been powered down by non-standard means. | |
1997 | * Best to let it slumber. | |
1998 | */ | |
1999 | if (dev->current_state == PCI_D3cold) | |
2000 | target_state = PCI_D3cold; | |
2001 | ||
2002 | if (device_may_wakeup(&dev->dev)) { | |
404cc2d8 RW |
2003 | /* |
2004 | * Find the deepest state from which the device can generate | |
2005 | * wake-up events, make it the target state and enable device | |
2006 | * to generate PME#. | |
2007 | */ | |
337001b6 RW |
2008 | if (dev->pme_support) { |
2009 | while (target_state | |
2010 | && !(dev->pme_support & (1 << target_state))) | |
2011 | target_state--; | |
404cc2d8 RW |
2012 | } |
2013 | } | |
2014 | ||
e5899e1b RW |
2015 | return target_state; |
2016 | } | |
2017 | ||
2018 | /** | |
2019 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
2020 | * @dev: Device to handle. | |
2021 | * | |
2022 | * Choose the power state appropriate for the device depending on whether | |
2023 | * it can wake up the system and/or is power manageable by the platform | |
2024 | * (PCI_D3hot is the default) and put the device into that state. | |
2025 | */ | |
2026 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
2027 | { | |
2028 | pci_power_t target_state = pci_target_state(dev); | |
2029 | int error; | |
2030 | ||
2031 | if (target_state == PCI_POWER_ERROR) | |
2032 | return -EIO; | |
2033 | ||
8efb8c76 | 2034 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 2035 | |
404cc2d8 RW |
2036 | error = pci_set_power_state(dev, target_state); |
2037 | ||
2038 | if (error) | |
2039 | pci_enable_wake(dev, target_state, false); | |
2040 | ||
2041 | return error; | |
2042 | } | |
b7fe9434 | 2043 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2044 | |
2045 | /** | |
443bd1c4 | 2046 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
2047 | * @dev: Device to handle. |
2048 | * | |
88393161 | 2049 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2050 | */ |
2051 | int pci_back_from_sleep(struct pci_dev *dev) | |
2052 | { | |
2053 | pci_enable_wake(dev, PCI_D0, false); | |
2054 | return pci_set_power_state(dev, PCI_D0); | |
2055 | } | |
b7fe9434 | 2056 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2057 | |
6cbf8214 RW |
2058 | /** |
2059 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2060 | * @dev: PCI device being suspended. | |
2061 | * | |
2062 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2063 | * power state. | |
2064 | */ | |
2065 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2066 | { | |
2067 | pci_power_t target_state = pci_target_state(dev); | |
2068 | int error; | |
2069 | ||
2070 | if (target_state == PCI_POWER_ERROR) | |
2071 | return -EIO; | |
2072 | ||
448bd857 HY |
2073 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2074 | ||
6cbf8214 RW |
2075 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
2076 | ||
2077 | error = pci_set_power_state(dev, target_state); | |
2078 | ||
448bd857 | 2079 | if (error) { |
6cbf8214 | 2080 | __pci_enable_wake(dev, target_state, true, false); |
448bd857 HY |
2081 | dev->runtime_d3cold = false; |
2082 | } | |
6cbf8214 RW |
2083 | |
2084 | return error; | |
2085 | } | |
2086 | ||
b67ea761 RW |
2087 | /** |
2088 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2089 | * @dev: Device to check. | |
2090 | * | |
f7625980 | 2091 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2092 | * (through the platform or using the native PCIe PME) or if the device supports |
2093 | * PME and one of its upstream bridges can generate wake-up events. | |
2094 | */ | |
2095 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2096 | { | |
2097 | struct pci_bus *bus = dev->bus; | |
2098 | ||
2099 | if (device_run_wake(&dev->dev)) | |
2100 | return true; | |
2101 | ||
2102 | if (!dev->pme_support) | |
2103 | return false; | |
2104 | ||
6496ebd7 AS |
2105 | /* PME-capable in principle, but not from the intended sleep state */ |
2106 | if (!pci_pme_capable(dev, pci_target_state(dev))) | |
2107 | return false; | |
2108 | ||
b67ea761 RW |
2109 | while (bus->parent) { |
2110 | struct pci_dev *bridge = bus->self; | |
2111 | ||
2112 | if (device_run_wake(&bridge->dev)) | |
2113 | return true; | |
2114 | ||
2115 | bus = bus->parent; | |
2116 | } | |
2117 | ||
2118 | /* We have reached the root bus. */ | |
2119 | if (bus->bridge) | |
2120 | return device_run_wake(bus->bridge); | |
2121 | ||
2122 | return false; | |
2123 | } | |
2124 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2125 | ||
bac2a909 RW |
2126 | /** |
2127 | * pci_dev_keep_suspended - Check if the device can stay in the suspended state. | |
2128 | * @pci_dev: Device to check. | |
2129 | * | |
2130 | * Return 'true' if the device is runtime-suspended, it doesn't have to be | |
2131 | * reconfigured due to wakeup settings difference between system and runtime | |
2132 | * suspend and the current power state of it is suitable for the upcoming | |
2133 | * (system) transition. | |
2cef548a RW |
2134 | * |
2135 | * If the device is not configured for system wakeup, disable PME for it before | |
2136 | * returning 'true' to prevent it from waking up the system unnecessarily. | |
bac2a909 RW |
2137 | */ |
2138 | bool pci_dev_keep_suspended(struct pci_dev *pci_dev) | |
2139 | { | |
2140 | struct device *dev = &pci_dev->dev; | |
2141 | ||
2142 | if (!pm_runtime_suspended(dev) | |
2cef548a | 2143 | || pci_target_state(pci_dev) != pci_dev->current_state |
bac2a909 RW |
2144 | || platform_pci_need_resume(pci_dev)) |
2145 | return false; | |
2146 | ||
2cef548a RW |
2147 | /* |
2148 | * At this point the device is good to go unless it's been configured | |
2149 | * to generate PME at the runtime suspend time, but it is not supposed | |
2150 | * to wake up the system. In that case, simply disable PME for it | |
2151 | * (it will have to be re-enabled on exit from system resume). | |
2152 | * | |
2153 | * If the device's power state is D3cold and the platform check above | |
2154 | * hasn't triggered, the device's configuration is suitable and we don't | |
2155 | * need to manipulate it at all. | |
2156 | */ | |
2157 | spin_lock_irq(&dev->power.lock); | |
2158 | ||
2159 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && | |
2160 | !device_may_wakeup(dev)) | |
2161 | __pci_pme_active(pci_dev, false); | |
2162 | ||
2163 | spin_unlock_irq(&dev->power.lock); | |
2164 | return true; | |
2165 | } | |
2166 | ||
2167 | /** | |
2168 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2169 | * @pci_dev: Device to handle. | |
2170 | * | |
2171 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2172 | * it might have been disabled during the prepare phase of system suspend if | |
2173 | * the device was not configured for system wakeup. | |
2174 | */ | |
2175 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2176 | { | |
2177 | struct device *dev = &pci_dev->dev; | |
2178 | ||
2179 | if (!pci_dev_run_wake(pci_dev)) | |
2180 | return; | |
2181 | ||
2182 | spin_lock_irq(&dev->power.lock); | |
2183 | ||
2184 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2185 | __pci_pme_active(pci_dev, true); | |
2186 | ||
2187 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2188 | } |
2189 | ||
b3c32c4f HY |
2190 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2191 | { | |
2192 | struct device *dev = &pdev->dev; | |
2193 | struct device *parent = dev->parent; | |
2194 | ||
2195 | if (parent) | |
2196 | pm_runtime_get_sync(parent); | |
2197 | pm_runtime_get_noresume(dev); | |
2198 | /* | |
2199 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2200 | * so wait until suspending completes | |
2201 | */ | |
2202 | pm_runtime_barrier(dev); | |
2203 | /* | |
2204 | * Only need to resume devices in D3cold, because config | |
2205 | * registers are still accessible for devices suspended but | |
2206 | * not in D3cold. | |
2207 | */ | |
2208 | if (pdev->current_state == PCI_D3cold) | |
2209 | pm_runtime_resume(dev); | |
2210 | } | |
2211 | ||
2212 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2213 | { | |
2214 | struct device *dev = &pdev->dev; | |
2215 | struct device *parent = dev->parent; | |
2216 | ||
2217 | pm_runtime_put(dev); | |
2218 | if (parent) | |
2219 | pm_runtime_put_sync(parent); | |
2220 | } | |
2221 | ||
9d26d3a8 MW |
2222 | /** |
2223 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2224 | * @bridge: Bridge to check | |
2225 | * | |
2226 | * This function checks if it is possible to move the bridge to D3. | |
2227 | * Currently we only allow D3 for recent enough PCIe ports. | |
2228 | */ | |
c6a63307 | 2229 | bool pci_bridge_d3_possible(struct pci_dev *bridge) |
9d26d3a8 MW |
2230 | { |
2231 | unsigned int year; | |
2232 | ||
2233 | if (!pci_is_pcie(bridge)) | |
2234 | return false; | |
2235 | ||
2236 | switch (pci_pcie_type(bridge)) { | |
2237 | case PCI_EXP_TYPE_ROOT_PORT: | |
2238 | case PCI_EXP_TYPE_UPSTREAM: | |
2239 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2240 | if (pci_bridge_d3_disable) | |
2241 | return false; | |
97a90aee LW |
2242 | |
2243 | /* | |
d98e0929 BH |
2244 | * Hotplug interrupts cannot be delivered if the link is down, |
2245 | * so parents of a hotplug port must stay awake. In addition, | |
2246 | * hotplug ports handled by firmware in System Management Mode | |
97a90aee | 2247 | * may not be put into D3 by the OS (Thunderbolt on non-Macs). |
d98e0929 | 2248 | * For simplicity, disallow in general for now. |
97a90aee | 2249 | */ |
d98e0929 | 2250 | if (bridge->is_hotplug_bridge) |
97a90aee LW |
2251 | return false; |
2252 | ||
9d26d3a8 MW |
2253 | if (pci_bridge_d3_force) |
2254 | return true; | |
2255 | ||
2256 | /* | |
2257 | * It should be safe to put PCIe ports from 2015 or newer | |
2258 | * to D3. | |
2259 | */ | |
2260 | if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && | |
2261 | year >= 2015) { | |
2262 | return true; | |
2263 | } | |
2264 | break; | |
2265 | } | |
2266 | ||
2267 | return false; | |
2268 | } | |
2269 | ||
2270 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2271 | { | |
2272 | bool *d3cold_ok = data; | |
9d26d3a8 | 2273 | |
718a0609 LW |
2274 | if (/* The device needs to be allowed to go D3cold ... */ |
2275 | dev->no_d3cold || !dev->d3cold_allowed || | |
2276 | ||
2277 | /* ... and if it is wakeup capable to do so from D3cold. */ | |
2278 | (device_may_wakeup(&dev->dev) && | |
2279 | !pci_pme_capable(dev, PCI_D3cold)) || | |
2280 | ||
2281 | /* If it is a bridge it must be allowed to go to D3. */ | |
d98e0929 | 2282 | !pci_power_manageable(dev)) |
9d26d3a8 | 2283 | |
718a0609 | 2284 | *d3cold_ok = false; |
9d26d3a8 | 2285 | |
718a0609 | 2286 | return !*d3cold_ok; |
9d26d3a8 MW |
2287 | } |
2288 | ||
2289 | /* | |
2290 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
2291 | * @dev: PCI device which is changed | |
9d26d3a8 MW |
2292 | * |
2293 | * Update upstream bridge PM capabilities accordingly depending on if the | |
2294 | * device PM configuration was changed or the device is being removed. The | |
2295 | * change is also propagated upstream. | |
2296 | */ | |
1ed276a7 | 2297 | void pci_bridge_d3_update(struct pci_dev *dev) |
9d26d3a8 | 2298 | { |
1ed276a7 | 2299 | bool remove = !device_is_registered(&dev->dev); |
9d26d3a8 MW |
2300 | struct pci_dev *bridge; |
2301 | bool d3cold_ok = true; | |
2302 | ||
2303 | bridge = pci_upstream_bridge(dev); | |
2304 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
2305 | return; | |
2306 | ||
9d26d3a8 | 2307 | /* |
e8559b71 LW |
2308 | * If D3 is currently allowed for the bridge, removing one of its |
2309 | * children won't change that. | |
2310 | */ | |
2311 | if (remove && bridge->bridge_d3) | |
2312 | return; | |
2313 | ||
2314 | /* | |
2315 | * If D3 is currently allowed for the bridge and a child is added or | |
2316 | * changed, disallowance of D3 can only be caused by that child, so | |
2317 | * we only need to check that single device, not any of its siblings. | |
2318 | * | |
2319 | * If D3 is currently not allowed for the bridge, checking the device | |
2320 | * first may allow us to skip checking its siblings. | |
9d26d3a8 MW |
2321 | */ |
2322 | if (!remove) | |
2323 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
2324 | ||
e8559b71 LW |
2325 | /* |
2326 | * If D3 is currently not allowed for the bridge, this may be caused | |
2327 | * either by the device being changed/removed or any of its siblings, | |
2328 | * so we need to go through all children to find out if one of them | |
2329 | * continues to block D3. | |
2330 | */ | |
2331 | if (d3cold_ok && !bridge->bridge_d3) | |
9d26d3a8 MW |
2332 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, |
2333 | &d3cold_ok); | |
9d26d3a8 MW |
2334 | |
2335 | if (bridge->bridge_d3 != d3cold_ok) { | |
2336 | bridge->bridge_d3 = d3cold_ok; | |
2337 | /* Propagate change to upstream bridges */ | |
1ed276a7 | 2338 | pci_bridge_d3_update(bridge); |
9d26d3a8 | 2339 | } |
9d26d3a8 MW |
2340 | } |
2341 | ||
9d26d3a8 MW |
2342 | /** |
2343 | * pci_d3cold_enable - Enable D3cold for device | |
2344 | * @dev: PCI device to handle | |
2345 | * | |
2346 | * This function can be used in drivers to enable D3cold from the device | |
2347 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2348 | * accordingly. | |
2349 | */ | |
2350 | void pci_d3cold_enable(struct pci_dev *dev) | |
2351 | { | |
2352 | if (dev->no_d3cold) { | |
2353 | dev->no_d3cold = false; | |
1ed276a7 | 2354 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2355 | } |
2356 | } | |
2357 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
2358 | ||
2359 | /** | |
2360 | * pci_d3cold_disable - Disable D3cold for device | |
2361 | * @dev: PCI device to handle | |
2362 | * | |
2363 | * This function can be used in drivers to disable D3cold from the device | |
2364 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2365 | * accordingly. | |
2366 | */ | |
2367 | void pci_d3cold_disable(struct pci_dev *dev) | |
2368 | { | |
2369 | if (!dev->no_d3cold) { | |
2370 | dev->no_d3cold = true; | |
1ed276a7 | 2371 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2372 | } |
2373 | } | |
2374 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
2375 | ||
eb9d0fe4 RW |
2376 | /** |
2377 | * pci_pm_init - Initialize PM functions of given PCI device | |
2378 | * @dev: PCI device to handle. | |
2379 | */ | |
2380 | void pci_pm_init(struct pci_dev *dev) | |
2381 | { | |
2382 | int pm; | |
2383 | u16 pmc; | |
1da177e4 | 2384 | |
bb910a70 | 2385 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2386 | pm_runtime_set_active(&dev->dev); |
2387 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2388 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2389 | dev->wakeup_prepared = false; |
bb910a70 | 2390 | |
337001b6 | 2391 | dev->pm_cap = 0; |
ffaddbe8 | 2392 | dev->pme_support = 0; |
337001b6 | 2393 | |
eb9d0fe4 RW |
2394 | /* find PCI PM capability in list */ |
2395 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2396 | if (!pm) | |
50246dd4 | 2397 | return; |
eb9d0fe4 RW |
2398 | /* Check device's ability to generate PME# */ |
2399 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2400 | |
eb9d0fe4 RW |
2401 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
2402 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
2403 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 2404 | return; |
eb9d0fe4 RW |
2405 | } |
2406 | ||
337001b6 | 2407 | dev->pm_cap = pm; |
1ae861e6 | 2408 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2409 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 2410 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 2411 | dev->d3cold_allowed = true; |
337001b6 RW |
2412 | |
2413 | dev->d1_support = false; | |
2414 | dev->d2_support = false; | |
2415 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2416 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2417 | dev->d1_support = true; |
c9ed77ee | 2418 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2419 | dev->d2_support = true; |
c9ed77ee BH |
2420 | |
2421 | if (dev->d1_support || dev->d2_support) | |
2422 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
2423 | dev->d1_support ? " D1" : "", |
2424 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2425 | } |
2426 | ||
2427 | pmc &= PCI_PM_CAP_PME_MASK; | |
2428 | if (pmc) { | |
10c3d71d BH |
2429 | dev_printk(KERN_DEBUG, &dev->dev, |
2430 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
2431 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2432 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2433 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2434 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2435 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2436 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2437 | dev->pme_poll = true; |
eb9d0fe4 RW |
2438 | /* |
2439 | * Make device's PM flags reflect the wake-up capability, but | |
2440 | * let the user space enable it to wake up the system as needed. | |
2441 | */ | |
2442 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2443 | /* Disable the PME# generation functionality */ |
337001b6 | 2444 | pci_pme_active(dev, false); |
eb9d0fe4 | 2445 | } |
1da177e4 LT |
2446 | } |
2447 | ||
938174e5 SS |
2448 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
2449 | { | |
92efb1bd | 2450 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
2451 | |
2452 | switch (prop) { | |
2453 | case PCI_EA_P_MEM: | |
2454 | case PCI_EA_P_VF_MEM: | |
2455 | flags |= IORESOURCE_MEM; | |
2456 | break; | |
2457 | case PCI_EA_P_MEM_PREFETCH: | |
2458 | case PCI_EA_P_VF_MEM_PREFETCH: | |
2459 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
2460 | break; | |
2461 | case PCI_EA_P_IO: | |
2462 | flags |= IORESOURCE_IO; | |
2463 | break; | |
2464 | default: | |
2465 | return 0; | |
2466 | } | |
2467 | ||
2468 | return flags; | |
2469 | } | |
2470 | ||
2471 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
2472 | u8 prop) | |
2473 | { | |
2474 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
2475 | return &dev->resource[bei]; | |
11183991 DD |
2476 | #ifdef CONFIG_PCI_IOV |
2477 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
2478 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
2479 | return &dev->resource[PCI_IOV_RESOURCES + | |
2480 | bei - PCI_EA_BEI_VF_BAR0]; | |
2481 | #endif | |
938174e5 SS |
2482 | else if (bei == PCI_EA_BEI_ROM) |
2483 | return &dev->resource[PCI_ROM_RESOURCE]; | |
2484 | else | |
2485 | return NULL; | |
2486 | } | |
2487 | ||
2488 | /* Read an Enhanced Allocation (EA) entry */ | |
2489 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
2490 | { | |
2491 | struct resource *res; | |
2492 | int ent_size, ent_offset = offset; | |
2493 | resource_size_t start, end; | |
2494 | unsigned long flags; | |
26635112 | 2495 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
2496 | u8 prop; |
2497 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
2498 | ||
2499 | pci_read_config_dword(dev, ent_offset, &dw0); | |
2500 | ent_offset += 4; | |
2501 | ||
2502 | /* Entry size field indicates DWORDs after 1st */ | |
2503 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
2504 | ||
2505 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
2506 | goto out; | |
2507 | ||
26635112 BH |
2508 | bei = (dw0 & PCI_EA_BEI) >> 4; |
2509 | prop = (dw0 & PCI_EA_PP) >> 8; | |
2510 | ||
938174e5 SS |
2511 | /* |
2512 | * If the Property is in the reserved range, try the Secondary | |
2513 | * Property instead. | |
2514 | */ | |
2515 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 2516 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
2517 | if (prop > PCI_EA_P_BRIDGE_IO) |
2518 | goto out; | |
2519 | ||
26635112 | 2520 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 2521 | if (!res) { |
26635112 | 2522 | dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
2523 | goto out; |
2524 | } | |
2525 | ||
2526 | flags = pci_ea_flags(dev, prop); | |
2527 | if (!flags) { | |
2528 | dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop); | |
2529 | goto out; | |
2530 | } | |
2531 | ||
2532 | /* Read Base */ | |
2533 | pci_read_config_dword(dev, ent_offset, &base); | |
2534 | start = (base & PCI_EA_FIELD_MASK); | |
2535 | ent_offset += 4; | |
2536 | ||
2537 | /* Read MaxOffset */ | |
2538 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
2539 | ent_offset += 4; | |
2540 | ||
2541 | /* Read Base MSBs (if 64-bit entry) */ | |
2542 | if (base & PCI_EA_IS_64) { | |
2543 | u32 base_upper; | |
2544 | ||
2545 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
2546 | ent_offset += 4; | |
2547 | ||
2548 | flags |= IORESOURCE_MEM_64; | |
2549 | ||
2550 | /* entry starts above 32-bit boundary, can't use */ | |
2551 | if (!support_64 && base_upper) | |
2552 | goto out; | |
2553 | ||
2554 | if (support_64) | |
2555 | start |= ((u64)base_upper << 32); | |
2556 | } | |
2557 | ||
2558 | end = start + (max_offset | 0x03); | |
2559 | ||
2560 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
2561 | if (max_offset & PCI_EA_IS_64) { | |
2562 | u32 max_offset_upper; | |
2563 | ||
2564 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
2565 | ent_offset += 4; | |
2566 | ||
2567 | flags |= IORESOURCE_MEM_64; | |
2568 | ||
2569 | /* entry too big, can't use */ | |
2570 | if (!support_64 && max_offset_upper) | |
2571 | goto out; | |
2572 | ||
2573 | if (support_64) | |
2574 | end += ((u64)max_offset_upper << 32); | |
2575 | } | |
2576 | ||
2577 | if (end < start) { | |
2578 | dev_err(&dev->dev, "EA Entry crosses address boundary\n"); | |
2579 | goto out; | |
2580 | } | |
2581 | ||
2582 | if (ent_size != ent_offset - offset) { | |
2583 | dev_err(&dev->dev, | |
2584 | "EA Entry Size (%d) does not match length read (%d)\n", | |
2585 | ent_size, ent_offset - offset); | |
2586 | goto out; | |
2587 | } | |
2588 | ||
2589 | res->name = pci_name(dev); | |
2590 | res->start = start; | |
2591 | res->end = end; | |
2592 | res->flags = flags; | |
597becb4 BH |
2593 | |
2594 | if (bei <= PCI_EA_BEI_BAR5) | |
2595 | dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2596 | bei, res, prop); | |
2597 | else if (bei == PCI_EA_BEI_ROM) | |
2598 | dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2599 | res, prop); | |
2600 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
2601 | dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2602 | bei - PCI_EA_BEI_VF_BAR0, res, prop); | |
2603 | else | |
2604 | dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2605 | bei, res, prop); | |
2606 | ||
938174e5 SS |
2607 | out: |
2608 | return offset + ent_size; | |
2609 | } | |
2610 | ||
dcbb408a | 2611 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
2612 | void pci_ea_init(struct pci_dev *dev) |
2613 | { | |
2614 | int ea; | |
2615 | u8 num_ent; | |
2616 | int offset; | |
2617 | int i; | |
2618 | ||
2619 | /* find PCI EA capability in list */ | |
2620 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
2621 | if (!ea) | |
2622 | return; | |
2623 | ||
2624 | /* determine the number of entries */ | |
2625 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
2626 | &num_ent); | |
2627 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
2628 | ||
2629 | offset = ea + PCI_EA_FIRST_ENT; | |
2630 | ||
2631 | /* Skip DWORD 2 for type 1 functions */ | |
2632 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
2633 | offset += 4; | |
2634 | ||
2635 | /* parse each EA entry */ | |
2636 | for (i = 0; i < num_ent; ++i) | |
2637 | offset = pci_ea_read(dev, offset); | |
2638 | } | |
2639 | ||
34a4876e YL |
2640 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
2641 | struct pci_cap_saved_state *new_cap) | |
2642 | { | |
2643 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
2644 | } | |
2645 | ||
63f4898a | 2646 | /** |
fd0f7f73 AW |
2647 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
2648 | * capability registers | |
63f4898a RW |
2649 | * @dev: the PCI device |
2650 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 2651 | * @extended: Standard or Extended capability ID |
63f4898a RW |
2652 | * @size: requested size of the buffer |
2653 | */ | |
fd0f7f73 AW |
2654 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
2655 | bool extended, unsigned int size) | |
63f4898a RW |
2656 | { |
2657 | int pos; | |
2658 | struct pci_cap_saved_state *save_state; | |
2659 | ||
fd0f7f73 AW |
2660 | if (extended) |
2661 | pos = pci_find_ext_capability(dev, cap); | |
2662 | else | |
2663 | pos = pci_find_capability(dev, cap); | |
2664 | ||
0a1a9b49 | 2665 | if (!pos) |
63f4898a RW |
2666 | return 0; |
2667 | ||
2668 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2669 | if (!save_state) | |
2670 | return -ENOMEM; | |
2671 | ||
24a4742f | 2672 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 2673 | save_state->cap.cap_extended = extended; |
24a4742f | 2674 | save_state->cap.size = size; |
63f4898a RW |
2675 | pci_add_saved_cap(dev, save_state); |
2676 | ||
2677 | return 0; | |
2678 | } | |
2679 | ||
fd0f7f73 AW |
2680 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
2681 | { | |
2682 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
2683 | } | |
2684 | ||
2685 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
2686 | { | |
2687 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
2688 | } | |
2689 | ||
63f4898a RW |
2690 | /** |
2691 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2692 | * @dev: the PCI device | |
2693 | */ | |
2694 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2695 | { | |
2696 | int error; | |
2697 | ||
89858517 YZ |
2698 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2699 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2700 | if (error) |
2701 | dev_err(&dev->dev, | |
2702 | "unable to preallocate PCI Express save buffer\n"); | |
2703 | ||
2704 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2705 | if (error) | |
2706 | dev_err(&dev->dev, | |
2707 | "unable to preallocate PCI-X save buffer\n"); | |
425c1b22 AW |
2708 | |
2709 | pci_allocate_vc_save_buffers(dev); | |
63f4898a RW |
2710 | } |
2711 | ||
f796841e YL |
2712 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2713 | { | |
2714 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 2715 | struct hlist_node *n; |
f796841e | 2716 | |
b67bfe0d | 2717 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
2718 | kfree(tmp); |
2719 | } | |
2720 | ||
58c3a727 | 2721 | /** |
31ab2476 | 2722 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 2723 | * @dev: the PCI device |
b0cc6020 YW |
2724 | * |
2725 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
2726 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 2727 | */ |
31ab2476 | 2728 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 2729 | { |
58c3a727 | 2730 | u32 cap; |
8113587c | 2731 | struct pci_dev *bridge; |
58c3a727 | 2732 | |
6748dcc2 | 2733 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2734 | return; |
2735 | ||
8113587c | 2736 | bridge = dev->bus->self; |
cb97ae34 | 2737 | if (!bridge) |
8113587c ZY |
2738 | return; |
2739 | ||
59875ae4 | 2740 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2741 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2742 | return; | |
2743 | ||
b0cc6020 YW |
2744 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
2745 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
2746 | PCI_EXP_DEVCTL2_ARI); | |
2747 | bridge->ari_enabled = 1; | |
2748 | } else { | |
2749 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
2750 | PCI_EXP_DEVCTL2_ARI); | |
2751 | bridge->ari_enabled = 0; | |
2752 | } | |
58c3a727 YZ |
2753 | } |
2754 | ||
5d990b62 CW |
2755 | static int pci_acs_enable; |
2756 | ||
2757 | /** | |
2758 | * pci_request_acs - ask for ACS to be enabled if supported | |
2759 | */ | |
2760 | void pci_request_acs(void) | |
2761 | { | |
2762 | pci_acs_enable = 1; | |
2763 | } | |
2764 | ||
ae21ee65 | 2765 | /** |
2c744244 | 2766 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites |
ae21ee65 AK |
2767 | * @dev: the PCI device |
2768 | */ | |
c1d61c9b | 2769 | static void pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
2770 | { |
2771 | int pos; | |
2772 | u16 cap; | |
2773 | u16 ctrl; | |
2774 | ||
ae21ee65 AK |
2775 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2776 | if (!pos) | |
c1d61c9b | 2777 | return; |
ae21ee65 AK |
2778 | |
2779 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2780 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2781 | ||
2782 | /* Source Validation */ | |
2783 | ctrl |= (cap & PCI_ACS_SV); | |
2784 | ||
2785 | /* P2P Request Redirect */ | |
2786 | ctrl |= (cap & PCI_ACS_RR); | |
2787 | ||
2788 | /* P2P Completion Redirect */ | |
2789 | ctrl |= (cap & PCI_ACS_CR); | |
2790 | ||
2791 | /* Upstream Forwarding */ | |
2792 | ctrl |= (cap & PCI_ACS_UF); | |
2793 | ||
2794 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
2795 | } |
2796 | ||
2797 | /** | |
2798 | * pci_enable_acs - enable ACS if hardware support it | |
2799 | * @dev: the PCI device | |
2800 | */ | |
2801 | void pci_enable_acs(struct pci_dev *dev) | |
2802 | { | |
2803 | if (!pci_acs_enable) | |
2804 | return; | |
2805 | ||
c1d61c9b | 2806 | if (!pci_dev_specific_enable_acs(dev)) |
2c744244 AW |
2807 | return; |
2808 | ||
c1d61c9b | 2809 | pci_std_enable_acs(dev); |
ae21ee65 AK |
2810 | } |
2811 | ||
0a67119f AW |
2812 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
2813 | { | |
2814 | int pos; | |
83db7e0b | 2815 | u16 cap, ctrl; |
0a67119f AW |
2816 | |
2817 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2818 | if (!pos) | |
2819 | return false; | |
2820 | ||
83db7e0b AW |
2821 | /* |
2822 | * Except for egress control, capabilities are either required | |
2823 | * or only required if controllable. Features missing from the | |
2824 | * capability field can therefore be assumed as hard-wired enabled. | |
2825 | */ | |
2826 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
2827 | acs_flags &= (cap | PCI_ACS_EC); | |
2828 | ||
0a67119f AW |
2829 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
2830 | return (ctrl & acs_flags) == acs_flags; | |
2831 | } | |
2832 | ||
ad805758 AW |
2833 | /** |
2834 | * pci_acs_enabled - test ACS against required flags for a given device | |
2835 | * @pdev: device to test | |
2836 | * @acs_flags: required PCI ACS flags | |
2837 | * | |
2838 | * Return true if the device supports the provided flags. Automatically | |
2839 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
2840 | * |
2841 | * Note that this interface checks the effective ACS capabilities of the | |
2842 | * device rather than the actual capabilities. For instance, most single | |
2843 | * function endpoints are not required to support ACS because they have no | |
2844 | * opportunity for peer-to-peer access. We therefore return 'true' | |
2845 | * regardless of whether the device exposes an ACS capability. This makes | |
2846 | * it much easier for callers of this function to ignore the actual type | |
2847 | * or topology of the device when testing ACS support. | |
ad805758 AW |
2848 | */ |
2849 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2850 | { | |
0a67119f | 2851 | int ret; |
ad805758 AW |
2852 | |
2853 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2854 | if (ret >= 0) | |
2855 | return ret > 0; | |
2856 | ||
0a67119f AW |
2857 | /* |
2858 | * Conventional PCI and PCI-X devices never support ACS, either | |
2859 | * effectively or actually. The shared bus topology implies that | |
2860 | * any device on the bus can receive or snoop DMA. | |
2861 | */ | |
ad805758 AW |
2862 | if (!pci_is_pcie(pdev)) |
2863 | return false; | |
2864 | ||
0a67119f AW |
2865 | switch (pci_pcie_type(pdev)) { |
2866 | /* | |
2867 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 2868 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
2869 | * handle them as we would a non-PCIe device. |
2870 | */ | |
2871 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
2872 | /* | |
2873 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
2874 | * applicable... must never implement an ACS Extended Capability...". | |
2875 | * This seems arbitrary, but we take a conservative interpretation | |
2876 | * of this statement. | |
2877 | */ | |
2878 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
2879 | case PCI_EXP_TYPE_RC_EC: | |
2880 | return false; | |
2881 | /* | |
2882 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
2883 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
2884 | * regardless of whether they are single- or multi-function devices. | |
2885 | */ | |
2886 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2887 | case PCI_EXP_TYPE_ROOT_PORT: | |
2888 | return pci_acs_flags_enabled(pdev, acs_flags); | |
2889 | /* | |
2890 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
2891 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 2892 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
2893 | * device. The footnote for section 6.12 indicates the specific |
2894 | * PCIe types included here. | |
2895 | */ | |
2896 | case PCI_EXP_TYPE_ENDPOINT: | |
2897 | case PCI_EXP_TYPE_UPSTREAM: | |
2898 | case PCI_EXP_TYPE_LEG_END: | |
2899 | case PCI_EXP_TYPE_RC_END: | |
2900 | if (!pdev->multifunction) | |
2901 | break; | |
2902 | ||
0a67119f | 2903 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
2904 | } |
2905 | ||
0a67119f | 2906 | /* |
f7625980 | 2907 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
2908 | * to single function devices with the exception of downstream ports. |
2909 | */ | |
ad805758 AW |
2910 | return true; |
2911 | } | |
2912 | ||
2913 | /** | |
2914 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2915 | * @start: starting downstream device | |
2916 | * @end: ending upstream device or NULL to search to the root bus | |
2917 | * @acs_flags: required flags | |
2918 | * | |
2919 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2920 | * any step along the way does not support the required flags, return false. | |
2921 | */ | |
2922 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2923 | struct pci_dev *end, u16 acs_flags) | |
2924 | { | |
2925 | struct pci_dev *pdev, *parent = start; | |
2926 | ||
2927 | do { | |
2928 | pdev = parent; | |
2929 | ||
2930 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2931 | return false; | |
2932 | ||
2933 | if (pci_is_root_bus(pdev->bus)) | |
2934 | return (end == NULL); | |
2935 | ||
2936 | parent = pdev->bus->self; | |
2937 | } while (pdev != end); | |
2938 | ||
2939 | return true; | |
2940 | } | |
2941 | ||
57c2cf71 BH |
2942 | /** |
2943 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
2944 | * @dev: the PCI device | |
bb5c2de2 | 2945 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
2946 | * |
2947 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
2948 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
2949 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
2950 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
2951 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 2952 | */ |
3df425f3 | 2953 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 2954 | { |
46b952a3 MW |
2955 | int slot; |
2956 | ||
2957 | if (pci_ari_enabled(dev->bus)) | |
2958 | slot = 0; | |
2959 | else | |
2960 | slot = PCI_SLOT(dev->devfn); | |
2961 | ||
2962 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
2963 | } |
2964 | ||
3c78bc61 | 2965 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
2966 | { |
2967 | u8 pin; | |
2968 | ||
514d207d | 2969 | pin = dev->pin; |
1da177e4 LT |
2970 | if (!pin) |
2971 | return -1; | |
878f2e50 | 2972 | |
8784fd4d | 2973 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 2974 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
2975 | dev = dev->bus->self; |
2976 | } | |
2977 | *bridge = dev; | |
2978 | return pin; | |
2979 | } | |
2980 | ||
68feac87 BH |
2981 | /** |
2982 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
2983 | * @dev: the PCI device | |
2984 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2985 | * | |
2986 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
2987 | * bridges all the way up to a PCI root bus. | |
2988 | */ | |
2989 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
2990 | { | |
2991 | u8 pin = *pinp; | |
2992 | ||
1eb39487 | 2993 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
2994 | pin = pci_swizzle_interrupt_pin(dev, pin); |
2995 | dev = dev->bus->self; | |
2996 | } | |
2997 | *pinp = pin; | |
2998 | return PCI_SLOT(dev->devfn); | |
2999 | } | |
e6b29dea | 3000 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 3001 | |
1da177e4 LT |
3002 | /** |
3003 | * pci_release_region - Release a PCI bar | |
3004 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
3005 | * @bar: BAR to release | |
3006 | * | |
3007 | * Releases the PCI I/O and memory resources previously reserved by a | |
3008 | * successful call to pci_request_region. Call this function only | |
3009 | * after all use of the PCI regions has ceased. | |
3010 | */ | |
3011 | void pci_release_region(struct pci_dev *pdev, int bar) | |
3012 | { | |
9ac7849e TH |
3013 | struct pci_devres *dr; |
3014 | ||
1da177e4 LT |
3015 | if (pci_resource_len(pdev, bar) == 0) |
3016 | return; | |
3017 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
3018 | release_region(pci_resource_start(pdev, bar), | |
3019 | pci_resource_len(pdev, bar)); | |
3020 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
3021 | release_mem_region(pci_resource_start(pdev, bar), | |
3022 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
3023 | |
3024 | dr = find_pci_dr(pdev); | |
3025 | if (dr) | |
3026 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 3027 | } |
b7fe9434 | 3028 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
3029 | |
3030 | /** | |
f5ddcac4 | 3031 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
3032 | * @pdev: PCI device whose resources are to be reserved |
3033 | * @bar: BAR to be reserved | |
3034 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 3035 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
3036 | * |
3037 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
3038 | * being reserved by owner @res_name. Do not access any | |
3039 | * address inside the PCI regions unless this call returns | |
3040 | * successfully. | |
3041 | * | |
f5ddcac4 RD |
3042 | * If @exclusive is set, then the region is marked so that userspace |
3043 | * is explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 3044 | * sysfs MMIO access. |
f5ddcac4 | 3045 | * |
1da177e4 LT |
3046 | * Returns 0 on success, or %EBUSY on error. A warning |
3047 | * message is also printed on failure. | |
3048 | */ | |
3c78bc61 RD |
3049 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3050 | const char *res_name, int exclusive) | |
1da177e4 | 3051 | { |
9ac7849e TH |
3052 | struct pci_devres *dr; |
3053 | ||
1da177e4 LT |
3054 | if (pci_resource_len(pdev, bar) == 0) |
3055 | return 0; | |
f7625980 | 3056 | |
1da177e4 LT |
3057 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3058 | if (!request_region(pci_resource_start(pdev, bar), | |
3059 | pci_resource_len(pdev, bar), res_name)) | |
3060 | goto err_out; | |
3c78bc61 | 3061 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3062 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3063 | pci_resource_len(pdev, bar), res_name, | |
3064 | exclusive)) | |
1da177e4 LT |
3065 | goto err_out; |
3066 | } | |
9ac7849e TH |
3067 | |
3068 | dr = find_pci_dr(pdev); | |
3069 | if (dr) | |
3070 | dr->region_mask |= 1 << bar; | |
3071 | ||
1da177e4 LT |
3072 | return 0; |
3073 | ||
3074 | err_out: | |
c7dabef8 | 3075 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3076 | &pdev->resource[bar]); |
1da177e4 LT |
3077 | return -EBUSY; |
3078 | } | |
3079 | ||
e8de1481 | 3080 | /** |
f5ddcac4 | 3081 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
3082 | * @pdev: PCI device whose resources are to be reserved |
3083 | * @bar: BAR to be reserved | |
f5ddcac4 | 3084 | * @res_name: Name to be associated with resource |
e8de1481 | 3085 | * |
f5ddcac4 | 3086 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
3087 | * being reserved by owner @res_name. Do not access any |
3088 | * address inside the PCI regions unless this call returns | |
3089 | * successfully. | |
3090 | * | |
3091 | * Returns 0 on success, or %EBUSY on error. A warning | |
3092 | * message is also printed on failure. | |
3093 | */ | |
3094 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3095 | { | |
3096 | return __pci_request_region(pdev, bar, res_name, 0); | |
3097 | } | |
b7fe9434 | 3098 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 AV |
3099 | |
3100 | /** | |
3101 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
3102 | * @pdev: PCI device whose resources are to be reserved | |
3103 | * @bar: BAR to be reserved | |
3104 | * @res_name: Name to be associated with resource. | |
3105 | * | |
3106 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
3107 | * being reserved by owner @res_name. Do not access any | |
3108 | * address inside the PCI regions unless this call returns | |
3109 | * successfully. | |
3110 | * | |
3111 | * Returns 0 on success, or %EBUSY on error. A warning | |
3112 | * message is also printed on failure. | |
3113 | * | |
3114 | * The key difference that _exclusive makes it that userspace is | |
3115 | * explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 3116 | * sysfs. |
e8de1481 | 3117 | */ |
3c78bc61 RD |
3118 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, |
3119 | const char *res_name) | |
e8de1481 AV |
3120 | { |
3121 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
3122 | } | |
b7fe9434 RD |
3123 | EXPORT_SYMBOL(pci_request_region_exclusive); |
3124 | ||
c87deff7 HS |
3125 | /** |
3126 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3127 | * @pdev: PCI device whose resources were previously reserved | |
3128 | * @bars: Bitmask of BARs to be released | |
3129 | * | |
3130 | * Release selected PCI I/O and memory resources previously reserved. | |
3131 | * Call this function only after all use of the PCI regions has ceased. | |
3132 | */ | |
3133 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3134 | { | |
3135 | int i; | |
3136 | ||
3137 | for (i = 0; i < 6; i++) | |
3138 | if (bars & (1 << i)) | |
3139 | pci_release_region(pdev, i); | |
3140 | } | |
b7fe9434 | 3141 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 3142 | |
9738abed | 3143 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 3144 | const char *res_name, int excl) |
c87deff7 HS |
3145 | { |
3146 | int i; | |
3147 | ||
3148 | for (i = 0; i < 6; i++) | |
3149 | if (bars & (1 << i)) | |
e8de1481 | 3150 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
3151 | goto err_out; |
3152 | return 0; | |
3153 | ||
3154 | err_out: | |
3c78bc61 | 3155 | while (--i >= 0) |
c87deff7 HS |
3156 | if (bars & (1 << i)) |
3157 | pci_release_region(pdev, i); | |
3158 | ||
3159 | return -EBUSY; | |
3160 | } | |
1da177e4 | 3161 | |
e8de1481 AV |
3162 | |
3163 | /** | |
3164 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
3165 | * @pdev: PCI device whose resources are to be reserved | |
3166 | * @bars: Bitmask of BARs to be requested | |
3167 | * @res_name: Name to be associated with resource | |
3168 | */ | |
3169 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
3170 | const char *res_name) | |
3171 | { | |
3172 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
3173 | } | |
b7fe9434 | 3174 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 3175 | |
3c78bc61 RD |
3176 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
3177 | const char *res_name) | |
e8de1481 AV |
3178 | { |
3179 | return __pci_request_selected_regions(pdev, bars, res_name, | |
3180 | IORESOURCE_EXCLUSIVE); | |
3181 | } | |
b7fe9434 | 3182 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 3183 | |
1da177e4 LT |
3184 | /** |
3185 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
3186 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
3187 | * | |
3188 | * Releases all PCI I/O and memory resources previously reserved by a | |
3189 | * successful call to pci_request_regions. Call this function only | |
3190 | * after all use of the PCI regions has ceased. | |
3191 | */ | |
3192 | ||
3193 | void pci_release_regions(struct pci_dev *pdev) | |
3194 | { | |
c87deff7 | 3195 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 | 3196 | } |
b7fe9434 | 3197 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
3198 | |
3199 | /** | |
3200 | * pci_request_regions - Reserved PCI I/O and memory resources | |
3201 | * @pdev: PCI device whose resources are to be reserved | |
3202 | * @res_name: Name to be associated with resource. | |
3203 | * | |
3204 | * Mark all PCI regions associated with PCI device @pdev as | |
3205 | * being reserved by owner @res_name. Do not access any | |
3206 | * address inside the PCI regions unless this call returns | |
3207 | * successfully. | |
3208 | * | |
3209 | * Returns 0 on success, or %EBUSY on error. A warning | |
3210 | * message is also printed on failure. | |
3211 | */ | |
3c990e92 | 3212 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 3213 | { |
c87deff7 | 3214 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 | 3215 | } |
b7fe9434 | 3216 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 3217 | |
e8de1481 AV |
3218 | /** |
3219 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
3220 | * @pdev: PCI device whose resources are to be reserved | |
3221 | * @res_name: Name to be associated with resource. | |
3222 | * | |
3223 | * Mark all PCI regions associated with PCI device @pdev as | |
3224 | * being reserved by owner @res_name. Do not access any | |
3225 | * address inside the PCI regions unless this call returns | |
3226 | * successfully. | |
3227 | * | |
3228 | * pci_request_regions_exclusive() will mark the region so that | |
f7625980 | 3229 | * /dev/mem and the sysfs MMIO access will not be allowed. |
e8de1481 AV |
3230 | * |
3231 | * Returns 0 on success, or %EBUSY on error. A warning | |
3232 | * message is also printed on failure. | |
3233 | */ | |
3234 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
3235 | { | |
3236 | return pci_request_selected_regions_exclusive(pdev, | |
3237 | ((1 << 6) - 1), res_name); | |
3238 | } | |
b7fe9434 | 3239 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 3240 | |
c5076cfe TN |
3241 | #ifdef PCI_IOBASE |
3242 | struct io_range { | |
3243 | struct list_head list; | |
3244 | phys_addr_t start; | |
3245 | resource_size_t size; | |
3246 | }; | |
3247 | ||
3248 | static LIST_HEAD(io_range_list); | |
3249 | static DEFINE_SPINLOCK(io_range_lock); | |
3250 | #endif | |
3251 | ||
3252 | /* | |
3253 | * Record the PCI IO range (expressed as CPU physical address + size). | |
3254 | * Return a negative value if an error has occured, zero otherwise | |
3255 | */ | |
3256 | int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size) | |
3257 | { | |
3258 | int err = 0; | |
3259 | ||
3260 | #ifdef PCI_IOBASE | |
3261 | struct io_range *range; | |
3262 | resource_size_t allocated_size = 0; | |
3263 | ||
3264 | /* check if the range hasn't been previously recorded */ | |
3265 | spin_lock(&io_range_lock); | |
3266 | list_for_each_entry(range, &io_range_list, list) { | |
3267 | if (addr >= range->start && addr + size <= range->start + size) { | |
3268 | /* range already registered, bail out */ | |
3269 | goto end_register; | |
3270 | } | |
3271 | allocated_size += range->size; | |
3272 | } | |
3273 | ||
3274 | /* range not registed yet, check for available space */ | |
3275 | if (allocated_size + size - 1 > IO_SPACE_LIMIT) { | |
3276 | /* if it's too big check if 64K space can be reserved */ | |
3277 | if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) { | |
3278 | err = -E2BIG; | |
3279 | goto end_register; | |
3280 | } | |
3281 | ||
3282 | size = SZ_64K; | |
3283 | pr_warn("Requested IO range too big, new size set to 64K\n"); | |
3284 | } | |
3285 | ||
3286 | /* add the range to the list */ | |
3287 | range = kzalloc(sizeof(*range), GFP_ATOMIC); | |
3288 | if (!range) { | |
3289 | err = -ENOMEM; | |
3290 | goto end_register; | |
3291 | } | |
3292 | ||
3293 | range->start = addr; | |
3294 | range->size = size; | |
3295 | ||
3296 | list_add_tail(&range->list, &io_range_list); | |
3297 | ||
3298 | end_register: | |
3299 | spin_unlock(&io_range_lock); | |
3300 | #endif | |
3301 | ||
3302 | return err; | |
3303 | } | |
3304 | ||
3305 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
3306 | { | |
3307 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
3308 | ||
3309 | #ifdef PCI_IOBASE | |
3310 | struct io_range *range; | |
3311 | resource_size_t allocated_size = 0; | |
3312 | ||
3313 | if (pio > IO_SPACE_LIMIT) | |
3314 | return address; | |
3315 | ||
3316 | spin_lock(&io_range_lock); | |
3317 | list_for_each_entry(range, &io_range_list, list) { | |
3318 | if (pio >= allocated_size && pio < allocated_size + range->size) { | |
3319 | address = range->start + pio - allocated_size; | |
3320 | break; | |
3321 | } | |
3322 | allocated_size += range->size; | |
3323 | } | |
3324 | spin_unlock(&io_range_lock); | |
3325 | #endif | |
3326 | ||
3327 | return address; | |
3328 | } | |
3329 | ||
3330 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
3331 | { | |
3332 | #ifdef PCI_IOBASE | |
3333 | struct io_range *res; | |
3334 | resource_size_t offset = 0; | |
3335 | unsigned long addr = -1; | |
3336 | ||
3337 | spin_lock(&io_range_lock); | |
3338 | list_for_each_entry(res, &io_range_list, list) { | |
3339 | if (address >= res->start && address < res->start + res->size) { | |
3340 | addr = address - res->start + offset; | |
3341 | break; | |
3342 | } | |
3343 | offset += res->size; | |
3344 | } | |
3345 | spin_unlock(&io_range_lock); | |
3346 | ||
3347 | return addr; | |
3348 | #else | |
3349 | if (address > IO_SPACE_LIMIT) | |
3350 | return (unsigned long)-1; | |
3351 | ||
3352 | return (unsigned long) address; | |
3353 | #endif | |
3354 | } | |
3355 | ||
8b921acf LD |
3356 | /** |
3357 | * pci_remap_iospace - Remap the memory mapped I/O space | |
3358 | * @res: Resource describing the I/O space | |
3359 | * @phys_addr: physical address of range to be mapped | |
3360 | * | |
3361 | * Remap the memory mapped I/O space described by the @res | |
3362 | * and the CPU physical address @phys_addr into virtual address space. | |
3363 | * Only architectures that have memory mapped IO functions defined | |
3364 | * (and the PCI_IOBASE value defined) should call this function. | |
3365 | */ | |
3366 | int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) | |
3367 | { | |
3368 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3369 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3370 | ||
3371 | if (!(res->flags & IORESOURCE_IO)) | |
3372 | return -EINVAL; | |
3373 | ||
3374 | if (res->end > IO_SPACE_LIMIT) | |
3375 | return -EINVAL; | |
3376 | ||
3377 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
3378 | pgprot_device(PAGE_KERNEL)); | |
3379 | #else | |
3380 | /* this architecture does not have memory mapped I/O space, | |
3381 | so this function should never be called */ | |
3382 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); | |
3383 | return -ENODEV; | |
3384 | #endif | |
3385 | } | |
3386 | ||
4d3f1384 SK |
3387 | /** |
3388 | * pci_unmap_iospace - Unmap the memory mapped I/O space | |
3389 | * @res: resource to be unmapped | |
3390 | * | |
3391 | * Unmap the CPU virtual address @res from virtual address space. | |
3392 | * Only architectures that have memory mapped IO functions defined | |
3393 | * (and the PCI_IOBASE value defined) should call this function. | |
3394 | */ | |
3395 | void pci_unmap_iospace(struct resource *res) | |
3396 | { | |
3397 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3398 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3399 | ||
3400 | unmap_kernel_range(vaddr, resource_size(res)); | |
3401 | #endif | |
3402 | } | |
3403 | ||
6a479079 BH |
3404 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
3405 | { | |
3406 | u16 old_cmd, cmd; | |
3407 | ||
3408 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
3409 | if (enable) | |
3410 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
3411 | else | |
3412 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
3413 | if (cmd != old_cmd) { | |
3414 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
3415 | enable ? "enabling" : "disabling"); | |
3416 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3417 | } | |
3418 | dev->is_busmaster = enable; | |
3419 | } | |
e8de1481 | 3420 | |
2b6f2c35 MS |
3421 | /** |
3422 | * pcibios_setup - process "pci=" kernel boot arguments | |
3423 | * @str: string used to pass in "pci=" kernel boot arguments | |
3424 | * | |
3425 | * Process kernel boot arguments. This is the default implementation. | |
3426 | * Architecture specific implementations can override this as necessary. | |
3427 | */ | |
3428 | char * __weak __init pcibios_setup(char *str) | |
3429 | { | |
3430 | return str; | |
3431 | } | |
3432 | ||
96c55900 MS |
3433 | /** |
3434 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
3435 | * @dev: the PCI device to enable | |
3436 | * | |
3437 | * Enables PCI bus-mastering for the device. This is the default | |
3438 | * implementation. Architecture specific implementations can override | |
3439 | * this if necessary. | |
3440 | */ | |
3441 | void __weak pcibios_set_master(struct pci_dev *dev) | |
3442 | { | |
3443 | u8 lat; | |
3444 | ||
f676678f MS |
3445 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
3446 | if (pci_is_pcie(dev)) | |
3447 | return; | |
3448 | ||
96c55900 MS |
3449 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
3450 | if (lat < 16) | |
3451 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
3452 | else if (lat > pcibios_max_latency) | |
3453 | lat = pcibios_max_latency; | |
3454 | else | |
3455 | return; | |
a006482b | 3456 | |
96c55900 MS |
3457 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
3458 | } | |
3459 | ||
1da177e4 LT |
3460 | /** |
3461 | * pci_set_master - enables bus-mastering for device dev | |
3462 | * @dev: the PCI device to enable | |
3463 | * | |
3464 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
3465 | * to do the needed arch specific settings. | |
3466 | */ | |
6a479079 | 3467 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 3468 | { |
6a479079 | 3469 | __pci_set_master(dev, true); |
1da177e4 LT |
3470 | pcibios_set_master(dev); |
3471 | } | |
b7fe9434 | 3472 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 3473 | |
6a479079 BH |
3474 | /** |
3475 | * pci_clear_master - disables bus-mastering for device dev | |
3476 | * @dev: the PCI device to disable | |
3477 | */ | |
3478 | void pci_clear_master(struct pci_dev *dev) | |
3479 | { | |
3480 | __pci_set_master(dev, false); | |
3481 | } | |
b7fe9434 | 3482 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 3483 | |
1da177e4 | 3484 | /** |
edb2d97e MW |
3485 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
3486 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 3487 | * |
edb2d97e MW |
3488 | * Helper function for pci_set_mwi. |
3489 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
3490 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
3491 | * | |
3492 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3493 | */ | |
15ea76d4 | 3494 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
3495 | { |
3496 | u8 cacheline_size; | |
3497 | ||
3498 | if (!pci_cache_line_size) | |
15ea76d4 | 3499 | return -EINVAL; |
1da177e4 LT |
3500 | |
3501 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
3502 | equal to or multiple of the right value. */ | |
3503 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
3504 | if (cacheline_size >= pci_cache_line_size && | |
3505 | (cacheline_size % pci_cache_line_size) == 0) | |
3506 | return 0; | |
3507 | ||
3508 | /* Write the correct value. */ | |
3509 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
3510 | /* Read it back. */ | |
3511 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
3512 | if (cacheline_size == pci_cache_line_size) | |
3513 | return 0; | |
3514 | ||
227f0647 RD |
3515 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", |
3516 | pci_cache_line_size << 2); | |
1da177e4 LT |
3517 | |
3518 | return -EINVAL; | |
3519 | } | |
15ea76d4 TH |
3520 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
3521 | ||
1da177e4 LT |
3522 | /** |
3523 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
3524 | * @dev: the PCI device for which MWI is enabled | |
3525 | * | |
694625c0 | 3526 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
3527 | * |
3528 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3529 | */ | |
3c78bc61 | 3530 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 3531 | { |
b7fe9434 RD |
3532 | #ifdef PCI_DISABLE_MWI |
3533 | return 0; | |
3534 | #else | |
1da177e4 LT |
3535 | int rc; |
3536 | u16 cmd; | |
3537 | ||
edb2d97e | 3538 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
3539 | if (rc) |
3540 | return rc; | |
3541 | ||
3542 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 3543 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
80ccba11 | 3544 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
3545 | cmd |= PCI_COMMAND_INVALIDATE; |
3546 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3547 | } | |
1da177e4 | 3548 | return 0; |
b7fe9434 | 3549 | #endif |
1da177e4 | 3550 | } |
b7fe9434 | 3551 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 3552 | |
694625c0 RD |
3553 | /** |
3554 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
3555 | * @dev: the PCI device for which MWI is enabled | |
3556 | * | |
3557 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
3558 | * Callers are not required to check the return value. | |
3559 | * | |
3560 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3561 | */ | |
3562 | int pci_try_set_mwi(struct pci_dev *dev) | |
3563 | { | |
b7fe9434 RD |
3564 | #ifdef PCI_DISABLE_MWI |
3565 | return 0; | |
3566 | #else | |
3567 | return pci_set_mwi(dev); | |
3568 | #endif | |
694625c0 | 3569 | } |
b7fe9434 | 3570 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 3571 | |
1da177e4 LT |
3572 | /** |
3573 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
3574 | * @dev: the PCI device to disable | |
3575 | * | |
3576 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
3577 | */ | |
3c78bc61 | 3578 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 3579 | { |
b7fe9434 | 3580 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
3581 | u16 cmd; |
3582 | ||
3583 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3584 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
3585 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
3586 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3587 | } | |
b7fe9434 | 3588 | #endif |
1da177e4 | 3589 | } |
b7fe9434 | 3590 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 3591 | |
a04ce0ff BR |
3592 | /** |
3593 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
3594 | * @pdev: the PCI device to operate on |
3595 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
3596 | * |
3597 | * Enables/disables PCI INTx for device dev | |
3598 | */ | |
3c78bc61 | 3599 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
3600 | { |
3601 | u16 pci_command, new; | |
3602 | ||
3603 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
3604 | ||
3c78bc61 | 3605 | if (enable) |
a04ce0ff | 3606 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 3607 | else |
a04ce0ff | 3608 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
3609 | |
3610 | if (new != pci_command) { | |
9ac7849e TH |
3611 | struct pci_devres *dr; |
3612 | ||
2fd9d74b | 3613 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
3614 | |
3615 | dr = find_pci_dr(pdev); | |
3616 | if (dr && !dr->restore_intx) { | |
3617 | dr->restore_intx = 1; | |
3618 | dr->orig_intx = !enable; | |
3619 | } | |
a04ce0ff BR |
3620 | } |
3621 | } | |
b7fe9434 | 3622 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 3623 | |
a2e27787 JK |
3624 | /** |
3625 | * pci_intx_mask_supported - probe for INTx masking support | |
6e9292c5 | 3626 | * @dev: the PCI device to operate on |
a2e27787 JK |
3627 | * |
3628 | * Check if the device dev support INTx masking via the config space | |
3629 | * command word. | |
3630 | */ | |
3631 | bool pci_intx_mask_supported(struct pci_dev *dev) | |
3632 | { | |
3633 | bool mask_supported = false; | |
3634 | u16 orig, new; | |
3635 | ||
fbebb9fd BH |
3636 | if (dev->broken_intx_masking) |
3637 | return false; | |
3638 | ||
a2e27787 JK |
3639 | pci_cfg_access_lock(dev); |
3640 | ||
3641 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
3642 | pci_write_config_word(dev, PCI_COMMAND, | |
3643 | orig ^ PCI_COMMAND_INTX_DISABLE); | |
3644 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
3645 | ||
3646 | /* | |
3647 | * There's no way to protect against hardware bugs or detect them | |
3648 | * reliably, but as long as we know what the value should be, let's | |
3649 | * go ahead and check it. | |
3650 | */ | |
3651 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { | |
227f0647 RD |
3652 | dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n", |
3653 | orig, new); | |
a2e27787 JK |
3654 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { |
3655 | mask_supported = true; | |
3656 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
3657 | } | |
3658 | ||
3659 | pci_cfg_access_unlock(dev); | |
3660 | return mask_supported; | |
3661 | } | |
3662 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); | |
3663 | ||
3664 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) | |
3665 | { | |
3666 | struct pci_bus *bus = dev->bus; | |
3667 | bool mask_updated = true; | |
3668 | u32 cmd_status_dword; | |
3669 | u16 origcmd, newcmd; | |
3670 | unsigned long flags; | |
3671 | bool irq_pending; | |
3672 | ||
3673 | /* | |
3674 | * We do a single dword read to retrieve both command and status. | |
3675 | * Document assumptions that make this possible. | |
3676 | */ | |
3677 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
3678 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
3679 | ||
3680 | raw_spin_lock_irqsave(&pci_lock, flags); | |
3681 | ||
3682 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
3683 | ||
3684 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
3685 | ||
3686 | /* | |
3687 | * Check interrupt status register to see whether our device | |
3688 | * triggered the interrupt (when masking) or the next IRQ is | |
3689 | * already pending (when unmasking). | |
3690 | */ | |
3691 | if (mask != irq_pending) { | |
3692 | mask_updated = false; | |
3693 | goto done; | |
3694 | } | |
3695 | ||
3696 | origcmd = cmd_status_dword; | |
3697 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
3698 | if (mask) | |
3699 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
3700 | if (newcmd != origcmd) | |
3701 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
3702 | ||
3703 | done: | |
3704 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
3705 | ||
3706 | return mask_updated; | |
3707 | } | |
3708 | ||
3709 | /** | |
3710 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 3711 | * @dev: the PCI device to operate on |
a2e27787 JK |
3712 | * |
3713 | * Check if the device dev has its INTx line asserted, mask it and | |
3714 | * return true in that case. False is returned if not interrupt was | |
3715 | * pending. | |
3716 | */ | |
3717 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
3718 | { | |
3719 | return pci_check_and_set_intx_mask(dev, true); | |
3720 | } | |
3721 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
3722 | ||
3723 | /** | |
ebd50b93 | 3724 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 3725 | * @dev: the PCI device to operate on |
a2e27787 JK |
3726 | * |
3727 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3728 | * and return true. False is returned and the mask remains active if | |
3729 | * there was still an interrupt pending. | |
3730 | */ | |
3731 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3732 | { | |
3733 | return pci_check_and_set_intx_mask(dev, false); | |
3734 | } | |
3735 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3736 | ||
3775a209 CL |
3737 | /** |
3738 | * pci_wait_for_pending_transaction - waits for pending transaction | |
3739 | * @dev: the PCI device to operate on | |
3740 | * | |
3741 | * Return 0 if transaction is pending 1 otherwise. | |
3742 | */ | |
3743 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 3744 | { |
157e876f AW |
3745 | if (!pci_is_pcie(dev)) |
3746 | return 1; | |
8c1c699f | 3747 | |
d0b4cc4e GS |
3748 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
3749 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
3750 | } |
3751 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
3752 | ||
5adecf81 AW |
3753 | /* |
3754 | * We should only need to wait 100ms after FLR, but some devices take longer. | |
3755 | * Wait for up to 1000ms for config space to return something other than -1. | |
3756 | * Intel IGD requires this when an LCD panel is attached. We read the 2nd | |
3757 | * dword because VFs don't implement the 1st dword. | |
3758 | */ | |
3759 | static void pci_flr_wait(struct pci_dev *dev) | |
3760 | { | |
3761 | int i = 0; | |
3762 | u32 id; | |
3763 | ||
3764 | do { | |
3765 | msleep(100); | |
3766 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
3767 | } while (i++ < 10 && id == ~0); | |
3768 | ||
3769 | if (id == ~0) | |
3770 | dev_warn(&dev->dev, "Failed to return from FLR\n"); | |
3771 | else if (i > 1) | |
3772 | dev_info(&dev->dev, "Required additional %dms to return from FLR\n", | |
3773 | (i - 1) * 100); | |
3774 | } | |
3775 | ||
3775a209 CL |
3776 | static int pcie_flr(struct pci_dev *dev, int probe) |
3777 | { | |
3778 | u32 cap; | |
3779 | ||
3780 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); | |
3781 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
3782 | return -ENOTTY; | |
3783 | ||
3784 | if (probe) | |
3785 | return 0; | |
3786 | ||
3787 | if (!pci_wait_for_pending_transaction(dev)) | |
bb383e28 | 3788 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 3789 | |
59875ae4 | 3790 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
5adecf81 | 3791 | pci_flr_wait(dev); |
8dd7f803 SY |
3792 | return 0; |
3793 | } | |
d91cdc74 | 3794 | |
8c1c699f | 3795 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3796 | { |
8c1c699f | 3797 | int pos; |
1ca88797 SY |
3798 | u8 cap; |
3799 | ||
8c1c699f YZ |
3800 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3801 | if (!pos) | |
1ca88797 | 3802 | return -ENOTTY; |
8c1c699f YZ |
3803 | |
3804 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
3805 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3806 | return -ENOTTY; | |
3807 | ||
3808 | if (probe) | |
3809 | return 0; | |
3810 | ||
d066c946 AW |
3811 | /* |
3812 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
3813 | * is used, so we use the conrol offset rather than status and shift | |
3814 | * the test bit to match. | |
3815 | */ | |
bb383e28 | 3816 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 3817 | PCI_AF_STATUS_TP << 8)) |
bb383e28 | 3818 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 3819 | |
8c1c699f | 3820 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
5adecf81 | 3821 | pci_flr_wait(dev); |
1ca88797 SY |
3822 | return 0; |
3823 | } | |
3824 | ||
83d74e03 RW |
3825 | /** |
3826 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3827 | * @dev: Device to reset. | |
3828 | * @probe: If set, only check if the device can be reset this way. | |
3829 | * | |
3830 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3831 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3832 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3833 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3834 | * | |
3835 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3836 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 3837 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
3838 | * Moreover, only devices in D0 can be reset by this function. |
3839 | */ | |
f85876ba | 3840 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3841 | { |
f85876ba YZ |
3842 | u16 csr; |
3843 | ||
51e53738 | 3844 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 3845 | return -ENOTTY; |
d91cdc74 | 3846 | |
f85876ba YZ |
3847 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
3848 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
3849 | return -ENOTTY; | |
d91cdc74 | 3850 | |
f85876ba YZ |
3851 | if (probe) |
3852 | return 0; | |
1ca88797 | 3853 | |
f85876ba YZ |
3854 | if (dev->current_state != PCI_D0) |
3855 | return -EINVAL; | |
3856 | ||
3857 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3858 | csr |= PCI_D3hot; | |
3859 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3860 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3861 | |
3862 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3863 | csr |= PCI_D0; | |
3864 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3865 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3866 | |
3867 | return 0; | |
3868 | } | |
3869 | ||
9e33002f | 3870 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
3871 | { |
3872 | u16 ctrl; | |
64e8674f AW |
3873 | |
3874 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
3875 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
3876 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3877 | /* |
3878 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 3879 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
3880 | */ |
3881 | msleep(2); | |
64e8674f AW |
3882 | |
3883 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
3884 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3885 | |
3886 | /* | |
3887 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
3888 | * Assuming a minimum 33MHz clock this results in a 1s | |
3889 | * delay before we can consider subordinate devices to | |
3890 | * be re-initialized. PCIe has some ways to shorten this, | |
3891 | * but we don't make use of them yet. | |
3892 | */ | |
3893 | ssleep(1); | |
64e8674f | 3894 | } |
d92a208d | 3895 | |
9e33002f GS |
3896 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
3897 | { | |
3898 | pci_reset_secondary_bus(dev); | |
3899 | } | |
3900 | ||
d92a208d GS |
3901 | /** |
3902 | * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. | |
3903 | * @dev: Bridge device | |
3904 | * | |
3905 | * Use the bridge control register to assert reset on the secondary bus. | |
3906 | * Devices on the secondary bus are left in power-on state. | |
3907 | */ | |
3908 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev) | |
3909 | { | |
3910 | pcibios_reset_secondary_bus(dev); | |
3911 | } | |
64e8674f AW |
3912 | EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); |
3913 | ||
3914 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
3915 | { | |
c12ff1df YZ |
3916 | struct pci_dev *pdev; |
3917 | ||
f331a859 AW |
3918 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
3919 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
3920 | return -ENOTTY; |
3921 | ||
3922 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3923 | if (pdev != dev) | |
3924 | return -ENOTTY; | |
3925 | ||
3926 | if (probe) | |
3927 | return 0; | |
3928 | ||
64e8674f | 3929 | pci_reset_bridge_secondary_bus(dev->bus->self); |
c12ff1df YZ |
3930 | |
3931 | return 0; | |
3932 | } | |
3933 | ||
608c3881 AW |
3934 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
3935 | { | |
3936 | int rc = -ENOTTY; | |
3937 | ||
3938 | if (!hotplug || !try_module_get(hotplug->ops->owner)) | |
3939 | return rc; | |
3940 | ||
3941 | if (hotplug->ops->reset_slot) | |
3942 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
3943 | ||
3944 | module_put(hotplug->ops->owner); | |
3945 | ||
3946 | return rc; | |
3947 | } | |
3948 | ||
3949 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
3950 | { | |
3951 | struct pci_dev *pdev; | |
3952 | ||
f331a859 AW |
3953 | if (dev->subordinate || !dev->slot || |
3954 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
3955 | return -ENOTTY; |
3956 | ||
3957 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3958 | if (pdev != dev && pdev->slot == dev->slot) | |
3959 | return -ENOTTY; | |
3960 | ||
3961 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
3962 | } | |
3963 | ||
977f857c | 3964 | static int __pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3965 | { |
8c1c699f YZ |
3966 | int rc; |
3967 | ||
3968 | might_sleep(); | |
3969 | ||
b9c3b266 DC |
3970 | rc = pci_dev_specific_reset(dev, probe); |
3971 | if (rc != -ENOTTY) | |
3972 | goto done; | |
3973 | ||
8c1c699f YZ |
3974 | rc = pcie_flr(dev, probe); |
3975 | if (rc != -ENOTTY) | |
3976 | goto done; | |
d91cdc74 | 3977 | |
8c1c699f | 3978 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
3979 | if (rc != -ENOTTY) |
3980 | goto done; | |
3981 | ||
3982 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
3983 | if (rc != -ENOTTY) |
3984 | goto done; | |
3985 | ||
608c3881 AW |
3986 | rc = pci_dev_reset_slot_function(dev, probe); |
3987 | if (rc != -ENOTTY) | |
3988 | goto done; | |
3989 | ||
c12ff1df | 3990 | rc = pci_parent_bus_reset(dev, probe); |
8c1c699f | 3991 | done: |
977f857c KRW |
3992 | return rc; |
3993 | } | |
3994 | ||
77cb985a AW |
3995 | static void pci_dev_lock(struct pci_dev *dev) |
3996 | { | |
3997 | pci_cfg_access_lock(dev); | |
3998 | /* block PM suspend, driver probe, etc. */ | |
3999 | device_lock(&dev->dev); | |
4000 | } | |
4001 | ||
61cf16d8 AW |
4002 | /* Return 1 on successful lock, 0 on contention */ |
4003 | static int pci_dev_trylock(struct pci_dev *dev) | |
4004 | { | |
4005 | if (pci_cfg_access_trylock(dev)) { | |
4006 | if (device_trylock(&dev->dev)) | |
4007 | return 1; | |
4008 | pci_cfg_access_unlock(dev); | |
4009 | } | |
4010 | ||
4011 | return 0; | |
4012 | } | |
4013 | ||
77cb985a AW |
4014 | static void pci_dev_unlock(struct pci_dev *dev) |
4015 | { | |
4016 | device_unlock(&dev->dev); | |
4017 | pci_cfg_access_unlock(dev); | |
4018 | } | |
4019 | ||
3ebe7f9f KB |
4020 | /** |
4021 | * pci_reset_notify - notify device driver of reset | |
4022 | * @dev: device to be notified of reset | |
4023 | * @prepare: 'true' if device is about to be reset; 'false' if reset attempt | |
4024 | * completed | |
4025 | * | |
4026 | * Must be called prior to device access being disabled and after device | |
4027 | * access is restored. | |
4028 | */ | |
4029 | static void pci_reset_notify(struct pci_dev *dev, bool prepare) | |
4030 | { | |
4031 | const struct pci_error_handlers *err_handler = | |
4032 | dev->driver ? dev->driver->err_handler : NULL; | |
4033 | if (err_handler && err_handler->reset_notify) | |
4034 | err_handler->reset_notify(dev, prepare); | |
4035 | } | |
4036 | ||
77cb985a AW |
4037 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
4038 | { | |
3ebe7f9f KB |
4039 | pci_reset_notify(dev, true); |
4040 | ||
a6cbaade AW |
4041 | /* |
4042 | * Wake-up device prior to save. PM registers default to D0 after | |
4043 | * reset and a simple register restore doesn't reliably return | |
4044 | * to a non-D0 state anyway. | |
4045 | */ | |
4046 | pci_set_power_state(dev, PCI_D0); | |
4047 | ||
77cb985a AW |
4048 | pci_save_state(dev); |
4049 | /* | |
4050 | * Disable the device by clearing the Command register, except for | |
4051 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
4052 | * BARs, but also prevents the device from being Bus Master, preventing | |
4053 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
4054 | * compliant devices, INTx-disable prevents legacy interrupts. | |
4055 | */ | |
4056 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
4057 | } | |
4058 | ||
4059 | static void pci_dev_restore(struct pci_dev *dev) | |
4060 | { | |
4061 | pci_restore_state(dev); | |
3ebe7f9f | 4062 | pci_reset_notify(dev, false); |
77cb985a AW |
4063 | } |
4064 | ||
977f857c KRW |
4065 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
4066 | { | |
4067 | int rc; | |
4068 | ||
77cb985a AW |
4069 | if (!probe) |
4070 | pci_dev_lock(dev); | |
977f857c KRW |
4071 | |
4072 | rc = __pci_dev_reset(dev, probe); | |
4073 | ||
77cb985a AW |
4074 | if (!probe) |
4075 | pci_dev_unlock(dev); | |
4076 | ||
8c1c699f | 4077 | return rc; |
d91cdc74 | 4078 | } |
3ebe7f9f | 4079 | |
d91cdc74 | 4080 | /** |
8c1c699f YZ |
4081 | * __pci_reset_function - reset a PCI device function |
4082 | * @dev: PCI device to reset | |
d91cdc74 SY |
4083 | * |
4084 | * Some devices allow an individual function to be reset without affecting | |
4085 | * other functions in the same device. The PCI device must be responsive | |
4086 | * to PCI config space in order to use this function. | |
4087 | * | |
4088 | * The device function is presumed to be unused when this function is called. | |
4089 | * Resetting the device will make the contents of PCI configuration space | |
4090 | * random, so any caller of this must be prepared to reinitialise the | |
4091 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
4092 | * etc. | |
4093 | * | |
8c1c699f | 4094 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
4095 | * device doesn't support resetting a single function. |
4096 | */ | |
8c1c699f | 4097 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 4098 | { |
8c1c699f | 4099 | return pci_dev_reset(dev, 0); |
d91cdc74 | 4100 | } |
8c1c699f | 4101 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 4102 | |
6fbf9e7a KRW |
4103 | /** |
4104 | * __pci_reset_function_locked - reset a PCI device function while holding | |
4105 | * the @dev mutex lock. | |
4106 | * @dev: PCI device to reset | |
4107 | * | |
4108 | * Some devices allow an individual function to be reset without affecting | |
4109 | * other functions in the same device. The PCI device must be responsive | |
4110 | * to PCI config space in order to use this function. | |
4111 | * | |
4112 | * The device function is presumed to be unused and the caller is holding | |
4113 | * the device mutex lock when this function is called. | |
4114 | * Resetting the device will make the contents of PCI configuration space | |
4115 | * random, so any caller of this must be prepared to reinitialise the | |
4116 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
4117 | * etc. | |
4118 | * | |
4119 | * Returns 0 if the device function was successfully reset or negative if the | |
4120 | * device doesn't support resetting a single function. | |
4121 | */ | |
4122 | int __pci_reset_function_locked(struct pci_dev *dev) | |
4123 | { | |
977f857c | 4124 | return __pci_dev_reset(dev, 0); |
6fbf9e7a KRW |
4125 | } |
4126 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
4127 | ||
711d5779 MT |
4128 | /** |
4129 | * pci_probe_reset_function - check whether the device can be safely reset | |
4130 | * @dev: PCI device to reset | |
4131 | * | |
4132 | * Some devices allow an individual function to be reset without affecting | |
4133 | * other functions in the same device. The PCI device must be responsive | |
4134 | * to PCI config space in order to use this function. | |
4135 | * | |
4136 | * Returns 0 if the device function can be reset or negative if the | |
4137 | * device doesn't support resetting a single function. | |
4138 | */ | |
4139 | int pci_probe_reset_function(struct pci_dev *dev) | |
4140 | { | |
4141 | return pci_dev_reset(dev, 1); | |
4142 | } | |
4143 | ||
8dd7f803 | 4144 | /** |
8c1c699f YZ |
4145 | * pci_reset_function - quiesce and reset a PCI device function |
4146 | * @dev: PCI device to reset | |
8dd7f803 SY |
4147 | * |
4148 | * Some devices allow an individual function to be reset without affecting | |
4149 | * other functions in the same device. The PCI device must be responsive | |
4150 | * to PCI config space in order to use this function. | |
4151 | * | |
4152 | * This function does not just reset the PCI portion of a device, but | |
4153 | * clears all the state associated with the device. This function differs | |
8c1c699f | 4154 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
4155 | * over the reset. |
4156 | * | |
8c1c699f | 4157 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
4158 | * device doesn't support resetting a single function. |
4159 | */ | |
4160 | int pci_reset_function(struct pci_dev *dev) | |
4161 | { | |
8c1c699f | 4162 | int rc; |
8dd7f803 | 4163 | |
8c1c699f YZ |
4164 | rc = pci_dev_reset(dev, 1); |
4165 | if (rc) | |
4166 | return rc; | |
8dd7f803 | 4167 | |
77cb985a | 4168 | pci_dev_save_and_disable(dev); |
8dd7f803 | 4169 | |
8c1c699f | 4170 | rc = pci_dev_reset(dev, 0); |
8dd7f803 | 4171 | |
77cb985a | 4172 | pci_dev_restore(dev); |
8dd7f803 | 4173 | |
8c1c699f | 4174 | return rc; |
8dd7f803 SY |
4175 | } |
4176 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
4177 | ||
61cf16d8 AW |
4178 | /** |
4179 | * pci_try_reset_function - quiesce and reset a PCI device function | |
4180 | * @dev: PCI device to reset | |
4181 | * | |
4182 | * Same as above, except return -EAGAIN if unable to lock device. | |
4183 | */ | |
4184 | int pci_try_reset_function(struct pci_dev *dev) | |
4185 | { | |
4186 | int rc; | |
4187 | ||
4188 | rc = pci_dev_reset(dev, 1); | |
4189 | if (rc) | |
4190 | return rc; | |
4191 | ||
4192 | pci_dev_save_and_disable(dev); | |
4193 | ||
4194 | if (pci_dev_trylock(dev)) { | |
4195 | rc = __pci_dev_reset(dev, 0); | |
4196 | pci_dev_unlock(dev); | |
4197 | } else | |
4198 | rc = -EAGAIN; | |
4199 | ||
4200 | pci_dev_restore(dev); | |
4201 | ||
4202 | return rc; | |
4203 | } | |
4204 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
4205 | ||
f331a859 AW |
4206 | /* Do any devices on or below this bus prevent a bus reset? */ |
4207 | static bool pci_bus_resetable(struct pci_bus *bus) | |
4208 | { | |
4209 | struct pci_dev *dev; | |
4210 | ||
4211 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4212 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
4213 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
4214 | return false; | |
4215 | } | |
4216 | ||
4217 | return true; | |
4218 | } | |
4219 | ||
090a3c53 AW |
4220 | /* Lock devices from the top of the tree down */ |
4221 | static void pci_bus_lock(struct pci_bus *bus) | |
4222 | { | |
4223 | struct pci_dev *dev; | |
4224 | ||
4225 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4226 | pci_dev_lock(dev); | |
4227 | if (dev->subordinate) | |
4228 | pci_bus_lock(dev->subordinate); | |
4229 | } | |
4230 | } | |
4231 | ||
4232 | /* Unlock devices from the bottom of the tree up */ | |
4233 | static void pci_bus_unlock(struct pci_bus *bus) | |
4234 | { | |
4235 | struct pci_dev *dev; | |
4236 | ||
4237 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4238 | if (dev->subordinate) | |
4239 | pci_bus_unlock(dev->subordinate); | |
4240 | pci_dev_unlock(dev); | |
4241 | } | |
4242 | } | |
4243 | ||
61cf16d8 AW |
4244 | /* Return 1 on successful lock, 0 on contention */ |
4245 | static int pci_bus_trylock(struct pci_bus *bus) | |
4246 | { | |
4247 | struct pci_dev *dev; | |
4248 | ||
4249 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4250 | if (!pci_dev_trylock(dev)) | |
4251 | goto unlock; | |
4252 | if (dev->subordinate) { | |
4253 | if (!pci_bus_trylock(dev->subordinate)) { | |
4254 | pci_dev_unlock(dev); | |
4255 | goto unlock; | |
4256 | } | |
4257 | } | |
4258 | } | |
4259 | return 1; | |
4260 | ||
4261 | unlock: | |
4262 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
4263 | if (dev->subordinate) | |
4264 | pci_bus_unlock(dev->subordinate); | |
4265 | pci_dev_unlock(dev); | |
4266 | } | |
4267 | return 0; | |
4268 | } | |
4269 | ||
f331a859 AW |
4270 | /* Do any devices on or below this slot prevent a bus reset? */ |
4271 | static bool pci_slot_resetable(struct pci_slot *slot) | |
4272 | { | |
4273 | struct pci_dev *dev; | |
4274 | ||
4275 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4276 | if (!dev->slot || dev->slot != slot) | |
4277 | continue; | |
4278 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
4279 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
4280 | return false; | |
4281 | } | |
4282 | ||
4283 | return true; | |
4284 | } | |
4285 | ||
090a3c53 AW |
4286 | /* Lock devices from the top of the tree down */ |
4287 | static void pci_slot_lock(struct pci_slot *slot) | |
4288 | { | |
4289 | struct pci_dev *dev; | |
4290 | ||
4291 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4292 | if (!dev->slot || dev->slot != slot) | |
4293 | continue; | |
4294 | pci_dev_lock(dev); | |
4295 | if (dev->subordinate) | |
4296 | pci_bus_lock(dev->subordinate); | |
4297 | } | |
4298 | } | |
4299 | ||
4300 | /* Unlock devices from the bottom of the tree up */ | |
4301 | static void pci_slot_unlock(struct pci_slot *slot) | |
4302 | { | |
4303 | struct pci_dev *dev; | |
4304 | ||
4305 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4306 | if (!dev->slot || dev->slot != slot) | |
4307 | continue; | |
4308 | if (dev->subordinate) | |
4309 | pci_bus_unlock(dev->subordinate); | |
4310 | pci_dev_unlock(dev); | |
4311 | } | |
4312 | } | |
4313 | ||
61cf16d8 AW |
4314 | /* Return 1 on successful lock, 0 on contention */ |
4315 | static int pci_slot_trylock(struct pci_slot *slot) | |
4316 | { | |
4317 | struct pci_dev *dev; | |
4318 | ||
4319 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4320 | if (!dev->slot || dev->slot != slot) | |
4321 | continue; | |
4322 | if (!pci_dev_trylock(dev)) | |
4323 | goto unlock; | |
4324 | if (dev->subordinate) { | |
4325 | if (!pci_bus_trylock(dev->subordinate)) { | |
4326 | pci_dev_unlock(dev); | |
4327 | goto unlock; | |
4328 | } | |
4329 | } | |
4330 | } | |
4331 | return 1; | |
4332 | ||
4333 | unlock: | |
4334 | list_for_each_entry_continue_reverse(dev, | |
4335 | &slot->bus->devices, bus_list) { | |
4336 | if (!dev->slot || dev->slot != slot) | |
4337 | continue; | |
4338 | if (dev->subordinate) | |
4339 | pci_bus_unlock(dev->subordinate); | |
4340 | pci_dev_unlock(dev); | |
4341 | } | |
4342 | return 0; | |
4343 | } | |
4344 | ||
090a3c53 AW |
4345 | /* Save and disable devices from the top of the tree down */ |
4346 | static void pci_bus_save_and_disable(struct pci_bus *bus) | |
4347 | { | |
4348 | struct pci_dev *dev; | |
4349 | ||
4350 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4351 | pci_dev_save_and_disable(dev); | |
4352 | if (dev->subordinate) | |
4353 | pci_bus_save_and_disable(dev->subordinate); | |
4354 | } | |
4355 | } | |
4356 | ||
4357 | /* | |
4358 | * Restore devices from top of the tree down - parent bridges need to be | |
4359 | * restored before we can get to subordinate devices. | |
4360 | */ | |
4361 | static void pci_bus_restore(struct pci_bus *bus) | |
4362 | { | |
4363 | struct pci_dev *dev; | |
4364 | ||
4365 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4366 | pci_dev_restore(dev); | |
4367 | if (dev->subordinate) | |
4368 | pci_bus_restore(dev->subordinate); | |
4369 | } | |
4370 | } | |
4371 | ||
4372 | /* Save and disable devices from the top of the tree down */ | |
4373 | static void pci_slot_save_and_disable(struct pci_slot *slot) | |
4374 | { | |
4375 | struct pci_dev *dev; | |
4376 | ||
4377 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4378 | if (!dev->slot || dev->slot != slot) | |
4379 | continue; | |
4380 | pci_dev_save_and_disable(dev); | |
4381 | if (dev->subordinate) | |
4382 | pci_bus_save_and_disable(dev->subordinate); | |
4383 | } | |
4384 | } | |
4385 | ||
4386 | /* | |
4387 | * Restore devices from top of the tree down - parent bridges need to be | |
4388 | * restored before we can get to subordinate devices. | |
4389 | */ | |
4390 | static void pci_slot_restore(struct pci_slot *slot) | |
4391 | { | |
4392 | struct pci_dev *dev; | |
4393 | ||
4394 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4395 | if (!dev->slot || dev->slot != slot) | |
4396 | continue; | |
4397 | pci_dev_restore(dev); | |
4398 | if (dev->subordinate) | |
4399 | pci_bus_restore(dev->subordinate); | |
4400 | } | |
4401 | } | |
4402 | ||
4403 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
4404 | { | |
4405 | int rc; | |
4406 | ||
f331a859 | 4407 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
4408 | return -ENOTTY; |
4409 | ||
4410 | if (!probe) | |
4411 | pci_slot_lock(slot); | |
4412 | ||
4413 | might_sleep(); | |
4414 | ||
4415 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
4416 | ||
4417 | if (!probe) | |
4418 | pci_slot_unlock(slot); | |
4419 | ||
4420 | return rc; | |
4421 | } | |
4422 | ||
9a3d2b9b AW |
4423 | /** |
4424 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
4425 | * @slot: PCI slot to probe | |
4426 | * | |
4427 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
4428 | */ | |
4429 | int pci_probe_reset_slot(struct pci_slot *slot) | |
4430 | { | |
4431 | return pci_slot_reset(slot, 1); | |
4432 | } | |
4433 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
4434 | ||
090a3c53 AW |
4435 | /** |
4436 | * pci_reset_slot - reset a PCI slot | |
4437 | * @slot: PCI slot to reset | |
4438 | * | |
4439 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
4440 | * independent of other slots. For instance, some slots may support slot power | |
4441 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
4442 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
4443 | * Generally a slot reset should be attempted before a bus reset. All of the | |
4444 | * function of the slot and any subordinate buses behind the slot are reset | |
4445 | * through this function. PCI config space of all devices in the slot and | |
4446 | * behind the slot is saved before and restored after reset. | |
4447 | * | |
4448 | * Return 0 on success, non-zero on error. | |
4449 | */ | |
4450 | int pci_reset_slot(struct pci_slot *slot) | |
4451 | { | |
4452 | int rc; | |
4453 | ||
4454 | rc = pci_slot_reset(slot, 1); | |
4455 | if (rc) | |
4456 | return rc; | |
4457 | ||
4458 | pci_slot_save_and_disable(slot); | |
4459 | ||
4460 | rc = pci_slot_reset(slot, 0); | |
4461 | ||
4462 | pci_slot_restore(slot); | |
4463 | ||
4464 | return rc; | |
4465 | } | |
4466 | EXPORT_SYMBOL_GPL(pci_reset_slot); | |
4467 | ||
61cf16d8 AW |
4468 | /** |
4469 | * pci_try_reset_slot - Try to reset a PCI slot | |
4470 | * @slot: PCI slot to reset | |
4471 | * | |
4472 | * Same as above except return -EAGAIN if the slot cannot be locked | |
4473 | */ | |
4474 | int pci_try_reset_slot(struct pci_slot *slot) | |
4475 | { | |
4476 | int rc; | |
4477 | ||
4478 | rc = pci_slot_reset(slot, 1); | |
4479 | if (rc) | |
4480 | return rc; | |
4481 | ||
4482 | pci_slot_save_and_disable(slot); | |
4483 | ||
4484 | if (pci_slot_trylock(slot)) { | |
4485 | might_sleep(); | |
4486 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
4487 | pci_slot_unlock(slot); | |
4488 | } else | |
4489 | rc = -EAGAIN; | |
4490 | ||
4491 | pci_slot_restore(slot); | |
4492 | ||
4493 | return rc; | |
4494 | } | |
4495 | EXPORT_SYMBOL_GPL(pci_try_reset_slot); | |
4496 | ||
090a3c53 AW |
4497 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
4498 | { | |
f331a859 | 4499 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
4500 | return -ENOTTY; |
4501 | ||
4502 | if (probe) | |
4503 | return 0; | |
4504 | ||
4505 | pci_bus_lock(bus); | |
4506 | ||
4507 | might_sleep(); | |
4508 | ||
4509 | pci_reset_bridge_secondary_bus(bus->self); | |
4510 | ||
4511 | pci_bus_unlock(bus); | |
4512 | ||
4513 | return 0; | |
4514 | } | |
4515 | ||
9a3d2b9b AW |
4516 | /** |
4517 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
4518 | * @bus: PCI bus to probe | |
4519 | * | |
4520 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
4521 | */ | |
4522 | int pci_probe_reset_bus(struct pci_bus *bus) | |
4523 | { | |
4524 | return pci_bus_reset(bus, 1); | |
4525 | } | |
4526 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
4527 | ||
090a3c53 AW |
4528 | /** |
4529 | * pci_reset_bus - reset a PCI bus | |
4530 | * @bus: top level PCI bus to reset | |
4531 | * | |
4532 | * Do a bus reset on the given bus and any subordinate buses, saving | |
4533 | * and restoring state of all devices. | |
4534 | * | |
4535 | * Return 0 on success, non-zero on error. | |
4536 | */ | |
4537 | int pci_reset_bus(struct pci_bus *bus) | |
4538 | { | |
4539 | int rc; | |
4540 | ||
4541 | rc = pci_bus_reset(bus, 1); | |
4542 | if (rc) | |
4543 | return rc; | |
4544 | ||
4545 | pci_bus_save_and_disable(bus); | |
4546 | ||
4547 | rc = pci_bus_reset(bus, 0); | |
4548 | ||
4549 | pci_bus_restore(bus); | |
4550 | ||
4551 | return rc; | |
4552 | } | |
4553 | EXPORT_SYMBOL_GPL(pci_reset_bus); | |
4554 | ||
61cf16d8 AW |
4555 | /** |
4556 | * pci_try_reset_bus - Try to reset a PCI bus | |
4557 | * @bus: top level PCI bus to reset | |
4558 | * | |
4559 | * Same as above except return -EAGAIN if the bus cannot be locked | |
4560 | */ | |
4561 | int pci_try_reset_bus(struct pci_bus *bus) | |
4562 | { | |
4563 | int rc; | |
4564 | ||
4565 | rc = pci_bus_reset(bus, 1); | |
4566 | if (rc) | |
4567 | return rc; | |
4568 | ||
4569 | pci_bus_save_and_disable(bus); | |
4570 | ||
4571 | if (pci_bus_trylock(bus)) { | |
4572 | might_sleep(); | |
4573 | pci_reset_bridge_secondary_bus(bus->self); | |
4574 | pci_bus_unlock(bus); | |
4575 | } else | |
4576 | rc = -EAGAIN; | |
4577 | ||
4578 | pci_bus_restore(bus); | |
4579 | ||
4580 | return rc; | |
4581 | } | |
4582 | EXPORT_SYMBOL_GPL(pci_try_reset_bus); | |
4583 | ||
d556ad4b PO |
4584 | /** |
4585 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
4586 | * @dev: PCI device to query | |
4587 | * | |
4588 | * Returns mmrbc: maximum designed memory read count in bytes | |
4589 | * or appropriate error value. | |
4590 | */ | |
4591 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
4592 | { | |
7c9e2b1c | 4593 | int cap; |
d556ad4b PO |
4594 | u32 stat; |
4595 | ||
4596 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4597 | if (!cap) | |
4598 | return -EINVAL; | |
4599 | ||
7c9e2b1c | 4600 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
4601 | return -EINVAL; |
4602 | ||
25daeb55 | 4603 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
4604 | } |
4605 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
4606 | ||
4607 | /** | |
4608 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
4609 | * @dev: PCI device to query | |
4610 | * | |
4611 | * Returns mmrbc: maximum memory read count in bytes | |
4612 | * or appropriate error value. | |
4613 | */ | |
4614 | int pcix_get_mmrbc(struct pci_dev *dev) | |
4615 | { | |
7c9e2b1c | 4616 | int cap; |
bdc2bda7 | 4617 | u16 cmd; |
d556ad4b PO |
4618 | |
4619 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4620 | if (!cap) | |
4621 | return -EINVAL; | |
4622 | ||
7c9e2b1c DN |
4623 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4624 | return -EINVAL; | |
d556ad4b | 4625 | |
7c9e2b1c | 4626 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
4627 | } |
4628 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
4629 | ||
4630 | /** | |
4631 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
4632 | * @dev: PCI device to query | |
4633 | * @mmrbc: maximum memory read count in bytes | |
4634 | * valid values are 512, 1024, 2048, 4096 | |
4635 | * | |
4636 | * If possible sets maximum memory read byte count, some bridges have erratas | |
4637 | * that prevent this. | |
4638 | */ | |
4639 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
4640 | { | |
7c9e2b1c | 4641 | int cap; |
bdc2bda7 DN |
4642 | u32 stat, v, o; |
4643 | u16 cmd; | |
d556ad4b | 4644 | |
229f5afd | 4645 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 4646 | return -EINVAL; |
d556ad4b PO |
4647 | |
4648 | v = ffs(mmrbc) - 10; | |
4649 | ||
4650 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4651 | if (!cap) | |
7c9e2b1c | 4652 | return -EINVAL; |
d556ad4b | 4653 | |
7c9e2b1c DN |
4654 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
4655 | return -EINVAL; | |
d556ad4b PO |
4656 | |
4657 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
4658 | return -E2BIG; | |
4659 | ||
7c9e2b1c DN |
4660 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4661 | return -EINVAL; | |
d556ad4b PO |
4662 | |
4663 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
4664 | if (o != v) { | |
809a3bf9 | 4665 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
4666 | return -EIO; |
4667 | ||
4668 | cmd &= ~PCI_X_CMD_MAX_READ; | |
4669 | cmd |= v << 2; | |
7c9e2b1c DN |
4670 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
4671 | return -EIO; | |
d556ad4b | 4672 | } |
7c9e2b1c | 4673 | return 0; |
d556ad4b PO |
4674 | } |
4675 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
4676 | ||
4677 | /** | |
4678 | * pcie_get_readrq - get PCI Express read request size | |
4679 | * @dev: PCI device to query | |
4680 | * | |
4681 | * Returns maximum memory read request in bytes | |
4682 | * or appropriate error value. | |
4683 | */ | |
4684 | int pcie_get_readrq(struct pci_dev *dev) | |
4685 | { | |
d556ad4b PO |
4686 | u16 ctl; |
4687 | ||
59875ae4 | 4688 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 4689 | |
59875ae4 | 4690 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
4691 | } |
4692 | EXPORT_SYMBOL(pcie_get_readrq); | |
4693 | ||
4694 | /** | |
4695 | * pcie_set_readrq - set PCI Express maximum memory read request | |
4696 | * @dev: PCI device to query | |
42e61f4a | 4697 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
4698 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4699 | * | |
c9b378c7 | 4700 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
4701 | */ |
4702 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
4703 | { | |
59875ae4 | 4704 | u16 v; |
d556ad4b | 4705 | |
229f5afd | 4706 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 4707 | return -EINVAL; |
d556ad4b | 4708 | |
a1c473aa BH |
4709 | /* |
4710 | * If using the "performance" PCIe config, we clamp the | |
4711 | * read rq size to the max packet size to prevent the | |
4712 | * host bridge generating requests larger than we can | |
4713 | * cope with | |
4714 | */ | |
4715 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
4716 | int mps = pcie_get_mps(dev); | |
4717 | ||
a1c473aa BH |
4718 | if (mps < rq) |
4719 | rq = mps; | |
4720 | } | |
4721 | ||
4722 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 4723 | |
59875ae4 JL |
4724 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4725 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
4726 | } |
4727 | EXPORT_SYMBOL(pcie_set_readrq); | |
4728 | ||
b03e7495 JM |
4729 | /** |
4730 | * pcie_get_mps - get PCI Express maximum payload size | |
4731 | * @dev: PCI device to query | |
4732 | * | |
4733 | * Returns maximum payload size in bytes | |
b03e7495 JM |
4734 | */ |
4735 | int pcie_get_mps(struct pci_dev *dev) | |
4736 | { | |
b03e7495 JM |
4737 | u16 ctl; |
4738 | ||
59875ae4 | 4739 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 4740 | |
59875ae4 | 4741 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 4742 | } |
f1c66c46 | 4743 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
4744 | |
4745 | /** | |
4746 | * pcie_set_mps - set PCI Express maximum payload size | |
4747 | * @dev: PCI device to query | |
47c08f31 | 4748 | * @mps: maximum payload size in bytes |
b03e7495 JM |
4749 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4750 | * | |
4751 | * If possible sets maximum payload size | |
4752 | */ | |
4753 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
4754 | { | |
59875ae4 | 4755 | u16 v; |
b03e7495 JM |
4756 | |
4757 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 4758 | return -EINVAL; |
b03e7495 JM |
4759 | |
4760 | v = ffs(mps) - 8; | |
f7625980 | 4761 | if (v > dev->pcie_mpss) |
59875ae4 | 4762 | return -EINVAL; |
b03e7495 JM |
4763 | v <<= 5; |
4764 | ||
59875ae4 JL |
4765 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4766 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 4767 | } |
f1c66c46 | 4768 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 4769 | |
81377c8d JK |
4770 | /** |
4771 | * pcie_get_minimum_link - determine minimum link settings of a PCI device | |
4772 | * @dev: PCI device to query | |
4773 | * @speed: storage for minimum speed | |
4774 | * @width: storage for minimum width | |
4775 | * | |
4776 | * This function will walk up the PCI device chain and determine the minimum | |
4777 | * link width and speed of the device. | |
4778 | */ | |
4779 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, | |
4780 | enum pcie_link_width *width) | |
4781 | { | |
4782 | int ret; | |
4783 | ||
4784 | *speed = PCI_SPEED_UNKNOWN; | |
4785 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4786 | ||
4787 | while (dev) { | |
4788 | u16 lnksta; | |
4789 | enum pci_bus_speed next_speed; | |
4790 | enum pcie_link_width next_width; | |
4791 | ||
4792 | ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
4793 | if (ret) | |
4794 | return ret; | |
4795 | ||
4796 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
4797 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
4798 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
4799 | ||
4800 | if (next_speed < *speed) | |
4801 | *speed = next_speed; | |
4802 | ||
4803 | if (next_width < *width) | |
4804 | *width = next_width; | |
4805 | ||
4806 | dev = dev->bus->self; | |
4807 | } | |
4808 | ||
4809 | return 0; | |
4810 | } | |
4811 | EXPORT_SYMBOL(pcie_get_minimum_link); | |
4812 | ||
c87deff7 HS |
4813 | /** |
4814 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 4815 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
4816 | * @flags: resource type mask to be selected |
4817 | * | |
4818 | * This helper routine makes bar mask from the type of resource. | |
4819 | */ | |
4820 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
4821 | { | |
4822 | int i, bars = 0; | |
4823 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
4824 | if (pci_resource_flags(dev, i) & flags) | |
4825 | bars |= (1 << i); | |
4826 | return bars; | |
4827 | } | |
b7fe9434 | 4828 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 4829 | |
95a8b6ef MT |
4830 | /* Some architectures require additional programming to enable VGA */ |
4831 | static arch_set_vga_state_t arch_set_vga_state; | |
4832 | ||
4833 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
4834 | { | |
4835 | arch_set_vga_state = func; /* NULL disables */ | |
4836 | } | |
4837 | ||
4838 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 4839 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
4840 | { |
4841 | if (arch_set_vga_state) | |
4842 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 4843 | flags); |
95a8b6ef MT |
4844 | return 0; |
4845 | } | |
4846 | ||
deb2d2ec BH |
4847 | /** |
4848 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
4849 | * @dev: the PCI device |
4850 | * @decode: true = enable decoding, false = disable decoding | |
4851 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 4852 | * @flags: traverse ancestors and change bridges |
3448a19d | 4853 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
4854 | */ |
4855 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 4856 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
4857 | { |
4858 | struct pci_bus *bus; | |
4859 | struct pci_dev *bridge; | |
4860 | u16 cmd; | |
95a8b6ef | 4861 | int rc; |
deb2d2ec | 4862 | |
67ebd814 | 4863 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 4864 | |
95a8b6ef | 4865 | /* ARCH specific VGA enables */ |
3448a19d | 4866 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
4867 | if (rc) |
4868 | return rc; | |
4869 | ||
3448a19d DA |
4870 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
4871 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4872 | if (decode == true) | |
4873 | cmd |= command_bits; | |
4874 | else | |
4875 | cmd &= ~command_bits; | |
4876 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4877 | } | |
deb2d2ec | 4878 | |
3448a19d | 4879 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
4880 | return 0; |
4881 | ||
4882 | bus = dev->bus; | |
4883 | while (bus) { | |
4884 | bridge = bus->self; | |
4885 | if (bridge) { | |
4886 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4887 | &cmd); | |
4888 | if (decode == true) | |
4889 | cmd |= PCI_BRIDGE_CTL_VGA; | |
4890 | else | |
4891 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
4892 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4893 | cmd); | |
4894 | } | |
4895 | bus = bus->parent; | |
4896 | } | |
4897 | return 0; | |
4898 | } | |
4899 | ||
f0af9593 BH |
4900 | /** |
4901 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
4902 | * @dev: the PCI device for which alias is added | |
4903 | * @devfn: alias slot and function | |
4904 | * | |
4905 | * This helper encodes 8-bit devfn as bit number in dma_alias_mask. | |
4906 | * It should be called early, preferably as PCI fixup header quirk. | |
4907 | */ | |
4908 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn) | |
4909 | { | |
338c3149 JL |
4910 | if (!dev->dma_alias_mask) |
4911 | dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX), | |
4912 | sizeof(long), GFP_KERNEL); | |
4913 | if (!dev->dma_alias_mask) { | |
4914 | dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n"); | |
4915 | return; | |
4916 | } | |
4917 | ||
4918 | set_bit(devfn, dev->dma_alias_mask); | |
48c83080 BH |
4919 | dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", |
4920 | PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
f0af9593 BH |
4921 | } |
4922 | ||
338c3149 JL |
4923 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
4924 | { | |
4925 | return (dev1->dma_alias_mask && | |
4926 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
4927 | (dev2->dma_alias_mask && | |
4928 | test_bit(dev1->devfn, dev2->dma_alias_mask)); | |
4929 | } | |
4930 | ||
8496e85c RW |
4931 | bool pci_device_is_present(struct pci_dev *pdev) |
4932 | { | |
4933 | u32 v; | |
4934 | ||
4935 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); | |
4936 | } | |
4937 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
4938 | ||
08249651 RW |
4939 | void pci_ignore_hotplug(struct pci_dev *dev) |
4940 | { | |
4941 | struct pci_dev *bridge = dev->bus->self; | |
4942 | ||
4943 | dev->ignore_hotplug = 1; | |
4944 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
4945 | if (bridge) | |
4946 | bridge->ignore_hotplug = 1; | |
4947 | } | |
4948 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
4949 | ||
32a9a682 YS |
4950 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
4951 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 4952 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
4953 | |
4954 | /** | |
4955 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
4956 | * @dev: the PCI device to get | |
4957 | * | |
4958 | * RETURNS: Resource alignment if it is specified. | |
4959 | * Zero if it is not specified. | |
4960 | */ | |
9738abed | 4961 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) |
32a9a682 YS |
4962 | { |
4963 | int seg, bus, slot, func, align_order, count; | |
644a544f | 4964 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
32a9a682 YS |
4965 | resource_size_t align = 0; |
4966 | char *p; | |
4967 | ||
4968 | spin_lock(&resource_alignment_lock); | |
4969 | p = resource_alignment_param; | |
f0b99f70 YX |
4970 | if (!*p) |
4971 | goto out; | |
4972 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
4973 | pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); | |
4974 | goto out; | |
4975 | } | |
4976 | ||
32a9a682 YS |
4977 | while (*p) { |
4978 | count = 0; | |
4979 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
4980 | p[count] == '@') { | |
4981 | p += count + 1; | |
4982 | } else { | |
4983 | align_order = -1; | |
4984 | } | |
644a544f KMEE |
4985 | if (strncmp(p, "pci:", 4) == 0) { |
4986 | /* PCI vendor/device (subvendor/subdevice) ids are specified */ | |
4987 | p += 4; | |
4988 | if (sscanf(p, "%hx:%hx:%hx:%hx%n", | |
4989 | &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) { | |
4990 | if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) { | |
4991 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n", | |
4992 | p); | |
4993 | break; | |
4994 | } | |
4995 | subsystem_vendor = subsystem_device = 0; | |
4996 | } | |
4997 | p += count; | |
4998 | if ((!vendor || (vendor == dev->vendor)) && | |
4999 | (!device || (device == dev->device)) && | |
5000 | (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) && | |
5001 | (!subsystem_device || (subsystem_device == dev->subsystem_device))) { | |
5002 | if (align_order == -1) | |
5003 | align = PAGE_SIZE; | |
5004 | else | |
5005 | align = 1 << align_order; | |
5006 | /* Found */ | |
32a9a682 YS |
5007 | break; |
5008 | } | |
5009 | } | |
644a544f KMEE |
5010 | else { |
5011 | if (sscanf(p, "%x:%x:%x.%x%n", | |
5012 | &seg, &bus, &slot, &func, &count) != 4) { | |
5013 | seg = 0; | |
5014 | if (sscanf(p, "%x:%x.%x%n", | |
5015 | &bus, &slot, &func, &count) != 3) { | |
5016 | /* Invalid format */ | |
5017 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
5018 | p); | |
5019 | break; | |
5020 | } | |
5021 | } | |
5022 | p += count; | |
5023 | if (seg == pci_domain_nr(dev->bus) && | |
5024 | bus == dev->bus->number && | |
5025 | slot == PCI_SLOT(dev->devfn) && | |
5026 | func == PCI_FUNC(dev->devfn)) { | |
5027 | if (align_order == -1) | |
5028 | align = PAGE_SIZE; | |
5029 | else | |
5030 | align = 1 << align_order; | |
5031 | /* Found */ | |
5032 | break; | |
5033 | } | |
32a9a682 YS |
5034 | } |
5035 | if (*p != ';' && *p != ',') { | |
5036 | /* End of param or invalid format */ | |
5037 | break; | |
5038 | } | |
5039 | p++; | |
5040 | } | |
f0b99f70 | 5041 | out: |
32a9a682 YS |
5042 | spin_unlock(&resource_alignment_lock); |
5043 | return align; | |
5044 | } | |
5045 | ||
2069ecfb YL |
5046 | /* |
5047 | * This function disables memory decoding and releases memory resources | |
5048 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
5049 | * It also rounds up size to specified alignment. | |
5050 | * Later on, the kernel will assign page-aligned memory resource back | |
5051 | * to the device. | |
5052 | */ | |
5053 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
5054 | { | |
5055 | int i; | |
5056 | struct resource *r; | |
5057 | resource_size_t align, size; | |
5058 | u16 command; | |
5059 | ||
62d9a78f YX |
5060 | /* |
5061 | * VF BARs are read-only zero according to SR-IOV spec r1.1, sec | |
5062 | * 3.4.1.11. Their resources are allocated from the space | |
5063 | * described by the VF BARx register in the PF's SR-IOV capability. | |
5064 | * We can't influence their alignment here. | |
5065 | */ | |
5066 | if (dev->is_virtfn) | |
5067 | return; | |
5068 | ||
10c463a7 YL |
5069 | /* check if specified PCI is target device to reassign */ |
5070 | align = pci_specified_resource_alignment(dev); | |
5071 | if (!align) | |
2069ecfb YL |
5072 | return; |
5073 | ||
5074 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
5075 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
5076 | dev_warn(&dev->dev, | |
5077 | "Can't reassign resources to host bridge.\n"); | |
5078 | return; | |
5079 | } | |
5080 | ||
5081 | dev_info(&dev->dev, | |
5082 | "Disabling memory decoding and releasing memory resources.\n"); | |
5083 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
5084 | command &= ~PCI_COMMAND_MEMORY; | |
5085 | pci_write_config_word(dev, PCI_COMMAND, command); | |
5086 | ||
2069ecfb YL |
5087 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { |
5088 | r = &dev->resource[i]; | |
5089 | if (!(r->flags & IORESOURCE_MEM)) | |
5090 | continue; | |
f0b99f70 YX |
5091 | if (r->flags & IORESOURCE_PCI_FIXED) { |
5092 | dev_info(&dev->dev, "Ignoring requested alignment for BAR%d: %pR\n", | |
5093 | i, r); | |
5094 | continue; | |
5095 | } | |
5096 | ||
2069ecfb YL |
5097 | size = resource_size(r); |
5098 | if (size < align) { | |
5099 | size = align; | |
5100 | dev_info(&dev->dev, | |
5101 | "Rounding up size of resource #%d to %#llx.\n", | |
5102 | i, (unsigned long long)size); | |
5103 | } | |
bd064f0a | 5104 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
5105 | r->end = size - 1; |
5106 | r->start = 0; | |
5107 | } | |
5108 | /* Need to disable bridge's resource window, | |
5109 | * to enable the kernel to reassign new resource | |
5110 | * window later on. | |
5111 | */ | |
5112 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
5113 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
5114 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
5115 | r = &dev->resource[i]; | |
5116 | if (!(r->flags & IORESOURCE_MEM)) | |
5117 | continue; | |
bd064f0a | 5118 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
5119 | r->end = resource_size(r) - 1; |
5120 | r->start = 0; | |
5121 | } | |
5122 | pci_disable_bridge_window(dev); | |
5123 | } | |
5124 | } | |
5125 | ||
9738abed | 5126 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
5127 | { |
5128 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
5129 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
5130 | spin_lock(&resource_alignment_lock); | |
5131 | strncpy(resource_alignment_param, buf, count); | |
5132 | resource_alignment_param[count] = '\0'; | |
5133 | spin_unlock(&resource_alignment_lock); | |
5134 | return count; | |
5135 | } | |
5136 | ||
9738abed | 5137 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
5138 | { |
5139 | size_t count; | |
5140 | spin_lock(&resource_alignment_lock); | |
5141 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
5142 | spin_unlock(&resource_alignment_lock); | |
5143 | return count; | |
5144 | } | |
5145 | ||
5146 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
5147 | { | |
5148 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
5149 | } | |
5150 | ||
5151 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
5152 | const char *buf, size_t count) | |
5153 | { | |
5154 | return pci_set_resource_alignment_param(buf, count); | |
5155 | } | |
5156 | ||
21751a9a | 5157 | static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, |
32a9a682 YS |
5158 | pci_resource_alignment_store); |
5159 | ||
5160 | static int __init pci_resource_alignment_sysfs_init(void) | |
5161 | { | |
5162 | return bus_create_file(&pci_bus_type, | |
5163 | &bus_attr_resource_alignment); | |
5164 | } | |
32a9a682 YS |
5165 | late_initcall(pci_resource_alignment_sysfs_init); |
5166 | ||
15856ad5 | 5167 | static void pci_no_domains(void) |
32a2eea7 JG |
5168 | { |
5169 | #ifdef CONFIG_PCI_DOMAINS | |
5170 | pci_domains_supported = 0; | |
5171 | #endif | |
5172 | } | |
5173 | ||
41e5c0f8 LD |
5174 | #ifdef CONFIG_PCI_DOMAINS |
5175 | static atomic_t __domain_nr = ATOMIC_INIT(-1); | |
5176 | ||
5177 | int pci_get_new_domain_nr(void) | |
5178 | { | |
5179 | return atomic_inc_return(&__domain_nr); | |
5180 | } | |
7c674700 LP |
5181 | |
5182 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1a4f93f7 | 5183 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
5184 | { |
5185 | static int use_dt_domains = -1; | |
54c6e2dd | 5186 | int domain = -1; |
7c674700 | 5187 | |
54c6e2dd KHC |
5188 | if (parent) |
5189 | domain = of_get_pci_domain_nr(parent->of_node); | |
7c674700 LP |
5190 | /* |
5191 | * Check DT domain and use_dt_domains values. | |
5192 | * | |
5193 | * If DT domain property is valid (domain >= 0) and | |
5194 | * use_dt_domains != 0, the DT assignment is valid since this means | |
5195 | * we have not previously allocated a domain number by using | |
5196 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
5197 | * 1, to indicate that we have just assigned a domain number from | |
5198 | * DT. | |
5199 | * | |
5200 | * If DT domain property value is not valid (ie domain < 0), and we | |
5201 | * have not previously assigned a domain number from DT | |
5202 | * (use_dt_domains != 1) we should assign a domain number by | |
5203 | * using the: | |
5204 | * | |
5205 | * pci_get_new_domain_nr() | |
5206 | * | |
5207 | * API and update the use_dt_domains value to keep track of method we | |
5208 | * are using to assign domain numbers (use_dt_domains = 0). | |
5209 | * | |
5210 | * All other combinations imply we have a platform that is trying | |
5211 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
5212 | * which is a recipe for domain mishandling and it is prevented by | |
5213 | * invalidating the domain value (domain = -1) and printing a | |
5214 | * corresponding error. | |
5215 | */ | |
5216 | if (domain >= 0 && use_dt_domains) { | |
5217 | use_dt_domains = 1; | |
5218 | } else if (domain < 0 && use_dt_domains != 1) { | |
5219 | use_dt_domains = 0; | |
5220 | domain = pci_get_new_domain_nr(); | |
5221 | } else { | |
5222 | dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n", | |
5223 | parent->of_node->full_name); | |
5224 | domain = -1; | |
5225 | } | |
5226 | ||
9c7cb891 | 5227 | return domain; |
7c674700 | 5228 | } |
1a4f93f7 TN |
5229 | |
5230 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
5231 | { | |
2ab51dde TN |
5232 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
5233 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
5234 | } |
5235 | #endif | |
41e5c0f8 LD |
5236 | #endif |
5237 | ||
0ef5f8f6 | 5238 | /** |
642c92da | 5239 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
5240 | * |
5241 | * Returns 1 if we can access PCI extended config space (offsets | |
5242 | * greater than 0xff). This is the default implementation. Architecture | |
5243 | * implementations can override this. | |
5244 | */ | |
642c92da | 5245 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
5246 | { |
5247 | return 1; | |
5248 | } | |
5249 | ||
2d1c8618 BH |
5250 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
5251 | { | |
5252 | } | |
5253 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
5254 | ||
ad04d31e | 5255 | static int __init pci_setup(char *str) |
1da177e4 LT |
5256 | { |
5257 | while (str) { | |
5258 | char *k = strchr(str, ','); | |
5259 | if (k) | |
5260 | *k++ = 0; | |
5261 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
5262 | if (!strcmp(str, "nomsi")) { |
5263 | pci_no_msi(); | |
7f785763 RD |
5264 | } else if (!strcmp(str, "noaer")) { |
5265 | pci_no_aer(); | |
b55438fd YL |
5266 | } else if (!strncmp(str, "realloc=", 8)) { |
5267 | pci_realloc_get_opt(str + 8); | |
f483d392 | 5268 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 5269 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
5270 | } else if (!strcmp(str, "nodomains")) { |
5271 | pci_no_domains(); | |
6748dcc2 RW |
5272 | } else if (!strncmp(str, "noari", 5)) { |
5273 | pcie_ari_disabled = true; | |
4516a618 AN |
5274 | } else if (!strncmp(str, "cbiosize=", 9)) { |
5275 | pci_cardbus_io_size = memparse(str + 9, &str); | |
5276 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
5277 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
5278 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
5279 | pci_set_resource_alignment_param(str + 19, | |
5280 | strlen(str + 19)); | |
43c16408 AP |
5281 | } else if (!strncmp(str, "ecrc=", 5)) { |
5282 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
5283 | } else if (!strncmp(str, "hpiosize=", 9)) { |
5284 | pci_hotplug_io_size = memparse(str + 9, &str); | |
5285 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
5286 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
e16b4660 KB |
5287 | } else if (!strncmp(str, "hpbussize=", 10)) { |
5288 | pci_hotplug_bus_size = | |
5289 | simple_strtoul(str + 10, &str, 0); | |
5290 | if (pci_hotplug_bus_size > 0xff) | |
5291 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
5292 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
5293 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
5294 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
5295 | pcie_bus_config = PCIE_BUS_SAFE; | |
5296 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
5297 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
5298 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
5299 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
5300 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
5301 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
5302 | } else { |
5303 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
5304 | str); | |
5305 | } | |
1da177e4 LT |
5306 | } |
5307 | str = k; | |
5308 | } | |
0637a70a | 5309 | return 0; |
1da177e4 | 5310 | } |
0637a70a | 5311 | early_param("pci", pci_setup); |