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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
1da177e4 | 4 | * |
df62ab5e BH |
5 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
6 | * David Mosberger-Tang | |
1da177e4 | 7 | * |
df62ab5e | 8 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
1da177e4 LT |
9 | */ |
10 | ||
2ab51dde | 11 | #include <linux/acpi.h> |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/delay.h> | |
9d26d3a8 | 14 | #include <linux/dmi.h> |
1da177e4 | 15 | #include <linux/init.h> |
bbd8810d | 16 | #include <linux/msi.h> |
7c674700 | 17 | #include <linux/of.h> |
1da177e4 | 18 | #include <linux/pci.h> |
075c1771 | 19 | #include <linux/pm.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1da177e4 LT |
21 | #include <linux/module.h> |
22 | #include <linux/spinlock.h> | |
4e57b681 | 23 | #include <linux/string.h> |
229f5afd | 24 | #include <linux/log2.h> |
5745392e | 25 | #include <linux/logic_pio.h> |
c300bd2f | 26 | #include <linux/pm_wakeup.h> |
8dd7f803 | 27 | #include <linux/interrupt.h> |
32a9a682 | 28 | #include <linux/device.h> |
b67ea761 | 29 | #include <linux/pm_runtime.h> |
608c3881 | 30 | #include <linux/pci_hotplug.h> |
4d3f1384 | 31 | #include <linux/vmalloc.h> |
2a2aca31 | 32 | #include <asm/dma.h> |
b07461a8 | 33 | #include <linux/aer.h> |
bc56b9e0 | 34 | #include "pci.h" |
1da177e4 | 35 | |
c4eed62a KB |
36 | DEFINE_MUTEX(pci_slot_mutex); |
37 | ||
00240c38 AS |
38 | const char *pci_power_names[] = { |
39 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
40 | }; | |
41 | EXPORT_SYMBOL_GPL(pci_power_names); | |
42 | ||
93177a74 RW |
43 | int isa_dma_bridge_buggy; |
44 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
45 | ||
46 | int pci_pci_problems; | |
47 | EXPORT_SYMBOL(pci_pci_problems); | |
48 | ||
3789af9a | 49 | unsigned int pci_pm_d3hot_delay; |
1ae861e6 | 50 | |
df17e62e MG |
51 | static void pci_pme_list_scan(struct work_struct *work); |
52 | ||
53 | static LIST_HEAD(pci_pme_list); | |
54 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
55 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
56 | ||
57 | struct pci_pme_device { | |
58 | struct list_head list; | |
59 | struct pci_dev *dev; | |
60 | }; | |
61 | ||
62 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
63 | ||
1ae861e6 RW |
64 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
65 | { | |
3789af9a | 66 | unsigned int delay = dev->d3hot_delay; |
1ae861e6 | 67 | |
3789af9a KW |
68 | if (delay < pci_pm_d3hot_delay) |
69 | delay = pci_pm_d3hot_delay; | |
1ae861e6 | 70 | |
50b2b540 AH |
71 | if (delay) |
72 | msleep(delay); | |
1ae861e6 | 73 | } |
1da177e4 | 74 | |
32a2eea7 JG |
75 | #ifdef CONFIG_PCI_DOMAINS |
76 | int pci_domains_supported = 1; | |
77 | #endif | |
78 | ||
4516a618 AN |
79 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
80 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
81 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
82 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
83 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
84 | ||
28760489 | 85 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
d7b8a217 NJ |
86 | #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024) |
87 | #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024) | |
88 | /* hpiosize=nn can override this */ | |
28760489 | 89 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; |
d7b8a217 NJ |
90 | /* |
91 | * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size, | |
92 | * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size; | |
93 | * pci=hpmemsize=nnM overrides both | |
94 | */ | |
95 | unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE; | |
96 | unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE; | |
28760489 | 97 | |
e16b4660 KB |
98 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
99 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
100 | ||
b0e85c3c JQ |
101 | |
102 | /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */ | |
103 | #ifdef CONFIG_PCIE_BUS_TUNE_OFF | |
104 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
105 | #elif defined CONFIG_PCIE_BUS_SAFE | |
106 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE; | |
107 | #elif defined CONFIG_PCIE_BUS_PERFORMANCE | |
108 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
109 | #elif defined CONFIG_PCIE_BUS_PEER2PEER | |
110 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER; | |
111 | #else | |
27d868b5 | 112 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b0e85c3c | 113 | #endif |
b03e7495 | 114 | |
ac1aa47b JB |
115 | /* |
116 | * The default CLS is used if arch didn't set CLS explicitly and not | |
117 | * all pci devices agree on the same value. Arch can override either | |
118 | * the dfl or actual value as it sees fit. Don't forget this is | |
119 | * measured in 32-bit words, not bytes. | |
120 | */ | |
15856ad5 | 121 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
122 | u8 pci_cache_line_size; |
123 | ||
96c55900 MS |
124 | /* |
125 | * If we set up a device for bus mastering, we need to check the latency | |
126 | * timer as certain BIOSes forget to set it properly. | |
127 | */ | |
128 | unsigned int pcibios_max_latency = 255; | |
129 | ||
6748dcc2 RW |
130 | /* If set, the PCIe ARI capability will not be used. */ |
131 | static bool pcie_ari_disabled; | |
132 | ||
cef74409 GK |
133 | /* If set, the PCIe ATS capability will not be used. */ |
134 | static bool pcie_ats_disabled; | |
135 | ||
11eb0e0e SK |
136 | /* If set, the PCI config space of each device is printed during boot. */ |
137 | bool pci_early_dump; | |
138 | ||
cef74409 GK |
139 | bool pci_ats_disabled(void) |
140 | { | |
141 | return pcie_ats_disabled; | |
142 | } | |
1a373a78 | 143 | EXPORT_SYMBOL_GPL(pci_ats_disabled); |
cef74409 | 144 | |
9d26d3a8 MW |
145 | /* Disable bridge_d3 for all PCIe ports */ |
146 | static bool pci_bridge_d3_disable; | |
147 | /* Force bridge_d3 for all PCIe ports */ | |
148 | static bool pci_bridge_d3_force; | |
149 | ||
150 | static int __init pcie_port_pm_setup(char *str) | |
151 | { | |
152 | if (!strcmp(str, "off")) | |
153 | pci_bridge_d3_disable = true; | |
154 | else if (!strcmp(str, "force")) | |
155 | pci_bridge_d3_force = true; | |
156 | return 1; | |
157 | } | |
158 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
159 | ||
a2758b6b SK |
160 | /* Time to wait after a reset for device to become responsive */ |
161 | #define PCIE_RESET_READY_POLL_MS 60000 | |
162 | ||
1da177e4 LT |
163 | /** |
164 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
165 | * @bus: pointer to PCI bus structure to search | |
166 | * | |
167 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
168 | * including the given PCI bus and its list of child PCI buses. | |
169 | */ | |
07656d83 | 170 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 171 | { |
94e6a9b9 | 172 | struct pci_bus *tmp; |
1da177e4 LT |
173 | unsigned char max, n; |
174 | ||
b918c62e | 175 | max = bus->busn_res.end; |
94e6a9b9 YW |
176 | list_for_each_entry(tmp, &bus->children, node) { |
177 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 178 | if (n > max) |
1da177e4 LT |
179 | max = n; |
180 | } | |
181 | return max; | |
182 | } | |
b82db5ce | 183 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 184 | |
ec5d9e87 HK |
185 | /** |
186 | * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS | |
187 | * @pdev: the PCI device | |
188 | * | |
189 | * Returns error bits set in PCI_STATUS and clears them. | |
190 | */ | |
191 | int pci_status_get_and_clear_errors(struct pci_dev *pdev) | |
192 | { | |
193 | u16 status; | |
194 | int ret; | |
195 | ||
196 | ret = pci_read_config_word(pdev, PCI_STATUS, &status); | |
197 | if (ret != PCIBIOS_SUCCESSFUL) | |
198 | return -EIO; | |
199 | ||
200 | status &= PCI_STATUS_ERROR_BITS; | |
201 | if (status) | |
202 | pci_write_config_word(pdev, PCI_STATUS, status); | |
203 | ||
204 | return status; | |
205 | } | |
206 | EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors); | |
207 | ||
1684f5dd AM |
208 | #ifdef CONFIG_HAS_IOMEM |
209 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
210 | { | |
1f7bf3bf BH |
211 | struct resource *res = &pdev->resource[bar]; |
212 | ||
1684f5dd AM |
213 | /* |
214 | * Make sure the BAR is actually a memory resource, not an IO resource | |
215 | */ | |
646c0282 | 216 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
7506dc79 | 217 | pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
218 | return NULL; |
219 | } | |
4bdc0d67 | 220 | return ioremap(res->start, resource_size(res)); |
1684f5dd AM |
221 | } |
222 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
223 | |
224 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
225 | { | |
226 | /* | |
227 | * Make sure the BAR is actually a memory resource, not an IO resource | |
228 | */ | |
229 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
230 | WARN_ON(1); | |
231 | return NULL; | |
232 | } | |
233 | return ioremap_wc(pci_resource_start(pdev, bar), | |
234 | pci_resource_len(pdev, bar)); | |
235 | } | |
236 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
237 | #endif |
238 | ||
45db3370 LG |
239 | /** |
240 | * pci_dev_str_match_path - test if a path string matches a device | |
74356add BH |
241 | * @dev: the PCI device to test |
242 | * @path: string to match the device against | |
45db3370 LG |
243 | * @endptr: pointer to the string after the match |
244 | * | |
245 | * Test if a string (typically from a kernel parameter) formatted as a | |
246 | * path of device/function addresses matches a PCI device. The string must | |
247 | * be of the form: | |
248 | * | |
249 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* | |
250 | * | |
251 | * A path for a device can be obtained using 'lspci -t'. Using a path | |
252 | * is more robust against bus renumbering than using only a single bus, | |
253 | * device and function address. | |
254 | * | |
255 | * Returns 1 if the string matches the device, 0 if it does not and | |
256 | * a negative error code if it fails to parse the string. | |
257 | */ | |
258 | static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, | |
259 | const char **endptr) | |
260 | { | |
261 | int ret; | |
262 | int seg, bus, slot, func; | |
263 | char *wpath, *p; | |
264 | char end; | |
265 | ||
266 | *endptr = strchrnul(path, ';'); | |
267 | ||
268 | wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL); | |
269 | if (!wpath) | |
270 | return -ENOMEM; | |
271 | ||
272 | while (1) { | |
273 | p = strrchr(wpath, '/'); | |
274 | if (!p) | |
275 | break; | |
276 | ret = sscanf(p, "/%x.%x%c", &slot, &func, &end); | |
277 | if (ret != 2) { | |
278 | ret = -EINVAL; | |
279 | goto free_and_exit; | |
280 | } | |
281 | ||
282 | if (dev->devfn != PCI_DEVFN(slot, func)) { | |
283 | ret = 0; | |
284 | goto free_and_exit; | |
285 | } | |
286 | ||
287 | /* | |
288 | * Note: we don't need to get a reference to the upstream | |
289 | * bridge because we hold a reference to the top level | |
290 | * device which should hold a reference to the bridge, | |
291 | * and so on. | |
292 | */ | |
293 | dev = pci_upstream_bridge(dev); | |
294 | if (!dev) { | |
295 | ret = 0; | |
296 | goto free_and_exit; | |
297 | } | |
298 | ||
299 | *p = 0; | |
300 | } | |
301 | ||
302 | ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot, | |
303 | &func, &end); | |
304 | if (ret != 4) { | |
305 | seg = 0; | |
306 | ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end); | |
307 | if (ret != 3) { | |
308 | ret = -EINVAL; | |
309 | goto free_and_exit; | |
310 | } | |
311 | } | |
312 | ||
313 | ret = (seg == pci_domain_nr(dev->bus) && | |
314 | bus == dev->bus->number && | |
315 | dev->devfn == PCI_DEVFN(slot, func)); | |
316 | ||
317 | free_and_exit: | |
318 | kfree(wpath); | |
319 | return ret; | |
320 | } | |
321 | ||
07d8d7e5 LG |
322 | /** |
323 | * pci_dev_str_match - test if a string matches a device | |
74356add BH |
324 | * @dev: the PCI device to test |
325 | * @p: string to match the device against | |
07d8d7e5 LG |
326 | * @endptr: pointer to the string after the match |
327 | * | |
328 | * Test if a string (typically from a kernel parameter) matches a specified | |
329 | * PCI device. The string may be of one of the following formats: | |
330 | * | |
45db3370 | 331 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* |
07d8d7e5 LG |
332 | * pci:<vendor>:<device>[:<subvendor>:<subdevice>] |
333 | * | |
334 | * The first format specifies a PCI bus/device/function address which | |
335 | * may change if new hardware is inserted, if motherboard firmware changes, | |
336 | * or due to changes caused in kernel parameters. If the domain is | |
45db3370 LG |
337 | * left unspecified, it is taken to be 0. In order to be robust against |
338 | * bus renumbering issues, a path of PCI device/function numbers may be used | |
339 | * to address the specific device. The path for a device can be determined | |
340 | * through the use of 'lspci -t'. | |
07d8d7e5 LG |
341 | * |
342 | * The second format matches devices using IDs in the configuration | |
343 | * space which may match multiple devices in the system. A value of 0 | |
344 | * for any field will match all devices. (Note: this differs from | |
345 | * in-kernel code that uses PCI_ANY_ID which is ~0; this is for | |
346 | * legacy reasons and convenience so users don't have to specify | |
347 | * FFFFFFFFs on the command line.) | |
348 | * | |
349 | * Returns 1 if the string matches the device, 0 if it does not and | |
350 | * a negative error code if the string cannot be parsed. | |
351 | */ | |
352 | static int pci_dev_str_match(struct pci_dev *dev, const char *p, | |
353 | const char **endptr) | |
354 | { | |
355 | int ret; | |
45db3370 | 356 | int count; |
07d8d7e5 LG |
357 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
358 | ||
359 | if (strncmp(p, "pci:", 4) == 0) { | |
360 | /* PCI vendor/device (subvendor/subdevice) IDs are specified */ | |
361 | p += 4; | |
362 | ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device, | |
363 | &subsystem_vendor, &subsystem_device, &count); | |
364 | if (ret != 4) { | |
365 | ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count); | |
366 | if (ret != 2) | |
367 | return -EINVAL; | |
368 | ||
369 | subsystem_vendor = 0; | |
370 | subsystem_device = 0; | |
371 | } | |
372 | ||
373 | p += count; | |
374 | ||
375 | if ((!vendor || vendor == dev->vendor) && | |
376 | (!device || device == dev->device) && | |
377 | (!subsystem_vendor || | |
378 | subsystem_vendor == dev->subsystem_vendor) && | |
379 | (!subsystem_device || | |
380 | subsystem_device == dev->subsystem_device)) | |
381 | goto found; | |
07d8d7e5 | 382 | } else { |
45db3370 LG |
383 | /* |
384 | * PCI Bus, Device, Function IDs are specified | |
74356add | 385 | * (optionally, may include a path of devfns following it) |
45db3370 LG |
386 | */ |
387 | ret = pci_dev_str_match_path(dev, p, &p); | |
388 | if (ret < 0) | |
389 | return ret; | |
390 | else if (ret) | |
07d8d7e5 LG |
391 | goto found; |
392 | } | |
393 | ||
394 | *endptr = p; | |
395 | return 0; | |
396 | ||
397 | found: | |
398 | *endptr = p; | |
399 | return 1; | |
400 | } | |
687d5fe3 | 401 | |
f646c2a0 PM |
402 | static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, |
403 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
404 | { |
405 | u8 id; | |
55db3208 SS |
406 | u16 ent; |
407 | ||
408 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 409 | |
687d5fe3 | 410 | while ((*ttl)--) { |
24a4e377 RD |
411 | if (pos < 0x40) |
412 | break; | |
413 | pos &= ~3; | |
55db3208 SS |
414 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
415 | ||
416 | id = ent & 0xff; | |
24a4e377 RD |
417 | if (id == 0xff) |
418 | break; | |
419 | if (id == cap) | |
420 | return pos; | |
55db3208 | 421 | pos = (ent >> 8); |
24a4e377 RD |
422 | } |
423 | return 0; | |
424 | } | |
425 | ||
f646c2a0 PM |
426 | static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
427 | u8 pos, int cap) | |
687d5fe3 ME |
428 | { |
429 | int ttl = PCI_FIND_CAP_TTL; | |
430 | ||
431 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
432 | } | |
433 | ||
f646c2a0 | 434 | u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
24a4e377 RD |
435 | { |
436 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
437 | pos + PCI_CAP_LIST_NEXT, cap); | |
438 | } | |
439 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
440 | ||
f646c2a0 | 441 | static u8 __pci_bus_find_cap_start(struct pci_bus *bus, |
d3bac118 | 442 | unsigned int devfn, u8 hdr_type) |
1da177e4 LT |
443 | { |
444 | u16 status; | |
1da177e4 LT |
445 | |
446 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
447 | if (!(status & PCI_STATUS_CAP_LIST)) | |
448 | return 0; | |
449 | ||
450 | switch (hdr_type) { | |
451 | case PCI_HEADER_TYPE_NORMAL: | |
452 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 453 | return PCI_CAPABILITY_LIST; |
1da177e4 | 454 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 455 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 456 | } |
d3bac118 ME |
457 | |
458 | return 0; | |
1da177e4 LT |
459 | } |
460 | ||
461 | /** | |
f7625980 | 462 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
463 | * @dev: PCI device to query |
464 | * @cap: capability code | |
465 | * | |
466 | * Tell if a device supports a given PCI capability. | |
467 | * Returns the address of the requested capability structure within the | |
468 | * device's PCI configuration space or 0 in case the device does not | |
74356add | 469 | * support it. Possible values for @cap include: |
1da177e4 | 470 | * |
f7625980 BH |
471 | * %PCI_CAP_ID_PM Power Management |
472 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
473 | * %PCI_CAP_ID_VPD Vital Product Data | |
474 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 475 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 476 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
477 | * %PCI_CAP_ID_PCIX PCI-X |
478 | * %PCI_CAP_ID_EXP PCI Express | |
479 | */ | |
f646c2a0 | 480 | u8 pci_find_capability(struct pci_dev *dev, int cap) |
1da177e4 | 481 | { |
f646c2a0 | 482 | u8 pos; |
d3bac118 ME |
483 | |
484 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
485 | if (pos) | |
486 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
487 | ||
488 | return pos; | |
1da177e4 | 489 | } |
b7fe9434 | 490 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
491 | |
492 | /** | |
f7625980 | 493 | * pci_bus_find_capability - query for devices' capabilities |
74356add | 494 | * @bus: the PCI bus to query |
1da177e4 | 495 | * @devfn: PCI device to query |
74356add | 496 | * @cap: capability code |
1da177e4 | 497 | * |
74356add | 498 | * Like pci_find_capability() but works for PCI devices that do not have a |
f7625980 | 499 | * pci_dev structure set up yet. |
1da177e4 LT |
500 | * |
501 | * Returns the address of the requested capability structure within the | |
502 | * device's PCI configuration space or 0 in case the device does not | |
503 | * support it. | |
504 | */ | |
f646c2a0 | 505 | u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) |
1da177e4 | 506 | { |
f646c2a0 | 507 | u8 hdr_type, pos; |
1da177e4 LT |
508 | |
509 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
510 | ||
d3bac118 ME |
511 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
512 | if (pos) | |
513 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
514 | ||
515 | return pos; | |
1da177e4 | 516 | } |
b7fe9434 | 517 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
518 | |
519 | /** | |
44a9a36f | 520 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 521 | * @dev: PCI device to query |
44a9a36f | 522 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
523 | * @cap: capability code |
524 | * | |
44a9a36f | 525 | * Returns the address of the next matching extended capability structure |
1da177e4 | 526 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
527 | * not support it. Some capabilities can occur several times, e.g., the |
528 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 529 | */ |
ee8b1c47 | 530 | u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) |
1da177e4 LT |
531 | { |
532 | u32 header; | |
557848c3 | 533 | int ttl; |
ee8b1c47 | 534 | u16 pos = PCI_CFG_SPACE_SIZE; |
1da177e4 | 535 | |
557848c3 ZY |
536 | /* minimum 8 bytes per capability */ |
537 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
538 | ||
539 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
540 | return 0; |
541 | ||
44a9a36f BH |
542 | if (start) |
543 | pos = start; | |
544 | ||
1da177e4 LT |
545 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
546 | return 0; | |
547 | ||
548 | /* | |
549 | * If we have no capabilities, this is indicated by cap ID, | |
550 | * cap version and next pointer all being 0. | |
551 | */ | |
552 | if (header == 0) | |
553 | return 0; | |
554 | ||
555 | while (ttl-- > 0) { | |
44a9a36f | 556 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
557 | return pos; |
558 | ||
559 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 560 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
561 | break; |
562 | ||
563 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
564 | break; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
44a9a36f BH |
569 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
570 | ||
571 | /** | |
572 | * pci_find_ext_capability - Find an extended capability | |
573 | * @dev: PCI device to query | |
574 | * @cap: capability code | |
575 | * | |
576 | * Returns the address of the requested extended capability structure | |
577 | * within the device's PCI configuration space or 0 if the device does | |
74356add | 578 | * not support it. Possible values for @cap include: |
44a9a36f BH |
579 | * |
580 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
581 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
582 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
583 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
584 | */ | |
ee8b1c47 | 585 | u16 pci_find_ext_capability(struct pci_dev *dev, int cap) |
44a9a36f BH |
586 | { |
587 | return pci_find_next_ext_capability(dev, 0, cap); | |
588 | } | |
3a720d72 | 589 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 590 | |
70c0923b JK |
591 | /** |
592 | * pci_get_dsn - Read and return the 8-byte Device Serial Number | |
593 | * @dev: PCI device to query | |
594 | * | |
595 | * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial | |
596 | * Number. | |
597 | * | |
598 | * Returns the DSN, or zero if the capability does not exist. | |
599 | */ | |
600 | u64 pci_get_dsn(struct pci_dev *dev) | |
601 | { | |
602 | u32 dword; | |
603 | u64 dsn; | |
604 | int pos; | |
605 | ||
606 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN); | |
607 | if (!pos) | |
608 | return 0; | |
609 | ||
610 | /* | |
611 | * The Device Serial Number is two dwords offset 4 bytes from the | |
612 | * capability position. The specification says that the first dword is | |
613 | * the lower half, and the second dword is the upper half. | |
614 | */ | |
615 | pos += 4; | |
616 | pci_read_config_dword(dev, pos, &dword); | |
617 | dsn = (u64)dword; | |
618 | pci_read_config_dword(dev, pos + 4, &dword); | |
619 | dsn |= ((u64)dword) << 32; | |
620 | ||
621 | return dsn; | |
622 | } | |
623 | EXPORT_SYMBOL_GPL(pci_get_dsn); | |
624 | ||
f646c2a0 | 625 | static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) |
687d5fe3 ME |
626 | { |
627 | int rc, ttl = PCI_FIND_CAP_TTL; | |
628 | u8 cap, mask; | |
629 | ||
630 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
631 | mask = HT_3BIT_CAP_MASK; | |
632 | else | |
633 | mask = HT_5BIT_CAP_MASK; | |
634 | ||
635 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
636 | PCI_CAP_ID_HT, &ttl); | |
637 | while (pos) { | |
638 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
639 | if (rc != PCIBIOS_SUCCESSFUL) | |
640 | return 0; | |
641 | ||
642 | if ((cap & mask) == ht_cap) | |
643 | return pos; | |
644 | ||
47a4d5be BG |
645 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
646 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
647 | PCI_CAP_ID_HT, &ttl); |
648 | } | |
649 | ||
650 | return 0; | |
651 | } | |
f646c2a0 | 652 | |
687d5fe3 | 653 | /** |
f646c2a0 | 654 | * pci_find_next_ht_capability - query a device's HyperTransport capabilities |
687d5fe3 ME |
655 | * @dev: PCI device to query |
656 | * @pos: Position from which to continue searching | |
f646c2a0 | 657 | * @ht_cap: HyperTransport capability code |
687d5fe3 ME |
658 | * |
659 | * To be used in conjunction with pci_find_ht_capability() to search for | |
660 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
661 | * from pci_find_ht_capability(). | |
662 | * | |
663 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
664 | * steps to avoid an infinite loop. | |
665 | */ | |
f646c2a0 | 666 | u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap) |
687d5fe3 ME |
667 | { |
668 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
669 | } | |
670 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
671 | ||
672 | /** | |
f646c2a0 | 673 | * pci_find_ht_capability - query a device's HyperTransport capabilities |
687d5fe3 | 674 | * @dev: PCI device to query |
f646c2a0 | 675 | * @ht_cap: HyperTransport capability code |
687d5fe3 | 676 | * |
f646c2a0 | 677 | * Tell if a device supports a given HyperTransport capability. |
687d5fe3 ME |
678 | * Returns an address within the device's PCI configuration space |
679 | * or 0 in case the device does not support the request capability. | |
680 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
f646c2a0 | 681 | * which has a HyperTransport capability matching @ht_cap. |
687d5fe3 | 682 | */ |
f646c2a0 | 683 | u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap) |
687d5fe3 | 684 | { |
f646c2a0 | 685 | u8 pos; |
687d5fe3 ME |
686 | |
687 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
688 | if (pos) | |
689 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
690 | ||
691 | return pos; | |
692 | } | |
693 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
694 | ||
c124fd9a GP |
695 | /** |
696 | * pci_find_vsec_capability - Find a vendor-specific extended capability | |
697 | * @dev: PCI device to query | |
698 | * @vendor: Vendor ID for which capability is defined | |
699 | * @cap: Vendor-specific capability ID | |
700 | * | |
701 | * If @dev has Vendor ID @vendor, search for a VSEC capability with | |
702 | * VSEC ID @cap. If found, return the capability offset in | |
703 | * config space; otherwise return 0. | |
704 | */ | |
705 | u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap) | |
706 | { | |
707 | u16 vsec = 0; | |
708 | u32 header; | |
709 | ||
710 | if (vendor != dev->vendor) | |
711 | return 0; | |
712 | ||
713 | while ((vsec = pci_find_next_ext_capability(dev, vsec, | |
714 | PCI_EXT_CAP_ID_VNDR))) { | |
715 | if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, | |
716 | &header) == PCIBIOS_SUCCESSFUL && | |
717 | PCI_VNDR_HEADER_ID(header) == cap) | |
718 | return vsec; | |
719 | } | |
720 | ||
721 | return 0; | |
722 | } | |
723 | EXPORT_SYMBOL_GPL(pci_find_vsec_capability); | |
724 | ||
1da177e4 | 725 | /** |
74356add BH |
726 | * pci_find_parent_resource - return resource region of parent bus of given |
727 | * region | |
1da177e4 LT |
728 | * @dev: PCI device structure contains resources to be searched |
729 | * @res: child resource record for which parent is sought | |
730 | * | |
74356add BH |
731 | * For given resource region of given device, return the resource region of |
732 | * parent bus the given region is contained in. | |
1da177e4 | 733 | */ |
3c78bc61 RD |
734 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
735 | struct resource *res) | |
1da177e4 LT |
736 | { |
737 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 738 | struct resource *r; |
1da177e4 | 739 | int i; |
1da177e4 | 740 | |
89a74ecc | 741 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
742 | if (!r) |
743 | continue; | |
31342330 | 744 | if (resource_contains(r, res)) { |
f44116ae BH |
745 | |
746 | /* | |
747 | * If the window is prefetchable but the BAR is | |
748 | * not, the allocator made a mistake. | |
749 | */ | |
750 | if (r->flags & IORESOURCE_PREFETCH && | |
751 | !(res->flags & IORESOURCE_PREFETCH)) | |
752 | return NULL; | |
753 | ||
754 | /* | |
755 | * If we're below a transparent bridge, there may | |
756 | * be both a positively-decoded aperture and a | |
757 | * subtractively-decoded region that contain the BAR. | |
758 | * We want the positively-decoded one, so this depends | |
759 | * on pci_bus_for_each_resource() giving us those | |
760 | * first. | |
761 | */ | |
762 | return r; | |
763 | } | |
1da177e4 | 764 | } |
f44116ae | 765 | return NULL; |
1da177e4 | 766 | } |
b7fe9434 | 767 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 768 | |
afd29f90 MW |
769 | /** |
770 | * pci_find_resource - Return matching PCI device resource | |
771 | * @dev: PCI device to query | |
772 | * @res: Resource to look for | |
773 | * | |
774 | * Goes over standard PCI resources (BARs) and checks if the given resource | |
775 | * is partially or fully contained in any of them. In that case the | |
776 | * matching resource is returned, %NULL otherwise. | |
777 | */ | |
778 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) | |
779 | { | |
780 | int i; | |
781 | ||
c9c13ba4 | 782 | for (i = 0; i < PCI_STD_NUM_BARS; i++) { |
afd29f90 MW |
783 | struct resource *r = &dev->resource[i]; |
784 | ||
785 | if (r->start && resource_contains(r, res)) | |
786 | return r; | |
787 | } | |
788 | ||
789 | return NULL; | |
790 | } | |
791 | EXPORT_SYMBOL(pci_find_resource); | |
792 | ||
157e876f AW |
793 | /** |
794 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
795 | * @dev: the PCI device to operate on | |
796 | * @pos: config space offset of status word | |
797 | * @mask: mask of bit(s) to care about in status word | |
798 | * | |
799 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
800 | */ | |
801 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
802 | { | |
803 | int i; | |
804 | ||
805 | /* Wait for Transaction Pending bit clean */ | |
806 | for (i = 0; i < 4; i++) { | |
807 | u16 status; | |
808 | if (i) | |
809 | msleep((1 << (i - 1)) * 100); | |
810 | ||
811 | pci_read_config_word(dev, pos, &status); | |
812 | if (!(status & mask)) | |
813 | return 1; | |
814 | } | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
cbe42036 RJ |
819 | static int pci_acs_enable; |
820 | ||
821 | /** | |
822 | * pci_request_acs - ask for ACS to be enabled if supported | |
823 | */ | |
824 | void pci_request_acs(void) | |
825 | { | |
826 | pci_acs_enable = 1; | |
827 | } | |
828 | ||
829 | static const char *disable_acs_redir_param; | |
830 | ||
831 | /** | |
832 | * pci_disable_acs_redir - disable ACS redirect capabilities | |
833 | * @dev: the PCI device | |
834 | * | |
835 | * For only devices specified in the disable_acs_redir parameter. | |
836 | */ | |
837 | static void pci_disable_acs_redir(struct pci_dev *dev) | |
838 | { | |
839 | int ret = 0; | |
840 | const char *p; | |
841 | int pos; | |
842 | u16 ctrl; | |
843 | ||
844 | if (!disable_acs_redir_param) | |
845 | return; | |
846 | ||
847 | p = disable_acs_redir_param; | |
848 | while (*p) { | |
849 | ret = pci_dev_str_match(dev, p, &p); | |
850 | if (ret < 0) { | |
851 | pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n", | |
852 | disable_acs_redir_param); | |
853 | ||
854 | break; | |
855 | } else if (ret == 1) { | |
856 | /* Found a match */ | |
857 | break; | |
858 | } | |
859 | ||
860 | if (*p != ';' && *p != ',') { | |
861 | /* End of param or invalid format */ | |
862 | break; | |
863 | } | |
864 | p++; | |
865 | } | |
866 | ||
867 | if (ret != 1) | |
868 | return; | |
869 | ||
870 | if (!pci_dev_specific_disable_acs_redir(dev)) | |
871 | return; | |
872 | ||
52fbf5bd | 873 | pos = dev->acs_cap; |
cbe42036 RJ |
874 | if (!pos) { |
875 | pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n"); | |
876 | return; | |
877 | } | |
878 | ||
879 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
880 | ||
881 | /* P2P Request & Completion Redirect */ | |
882 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); | |
883 | ||
884 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
885 | ||
886 | pci_info(dev, "disabled ACS redirect\n"); | |
887 | } | |
888 | ||
889 | /** | |
890 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities | |
891 | * @dev: the PCI device | |
892 | */ | |
893 | static void pci_std_enable_acs(struct pci_dev *dev) | |
894 | { | |
895 | int pos; | |
896 | u16 cap; | |
897 | u16 ctrl; | |
898 | ||
52fbf5bd | 899 | pos = dev->acs_cap; |
cbe42036 RJ |
900 | if (!pos) |
901 | return; | |
902 | ||
903 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
904 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
905 | ||
906 | /* Source Validation */ | |
907 | ctrl |= (cap & PCI_ACS_SV); | |
908 | ||
909 | /* P2P Request Redirect */ | |
910 | ctrl |= (cap & PCI_ACS_RR); | |
911 | ||
912 | /* P2P Completion Redirect */ | |
913 | ctrl |= (cap & PCI_ACS_CR); | |
914 | ||
915 | /* Upstream Forwarding */ | |
916 | ctrl |= (cap & PCI_ACS_UF); | |
917 | ||
76fc8e85 RJ |
918 | /* Enable Translation Blocking for external devices */ |
919 | if (dev->external_facing || dev->untrusted) | |
920 | ctrl |= (cap & PCI_ACS_TB); | |
921 | ||
cbe42036 RJ |
922 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); |
923 | } | |
924 | ||
925 | /** | |
926 | * pci_enable_acs - enable ACS if hardware support it | |
927 | * @dev: the PCI device | |
928 | */ | |
52fbf5bd | 929 | static void pci_enable_acs(struct pci_dev *dev) |
cbe42036 RJ |
930 | { |
931 | if (!pci_acs_enable) | |
932 | goto disable_acs_redir; | |
933 | ||
934 | if (!pci_dev_specific_enable_acs(dev)) | |
935 | goto disable_acs_redir; | |
936 | ||
937 | pci_std_enable_acs(dev); | |
938 | ||
939 | disable_acs_redir: | |
940 | /* | |
941 | * Note: pci_disable_acs_redir() must be called even if ACS was not | |
942 | * enabled by the kernel because it may have been enabled by | |
943 | * platform firmware. So if we are told to disable it, we should | |
944 | * always disable it after setting the kernel's default | |
945 | * preferences. | |
946 | */ | |
947 | pci_disable_acs_redir(dev); | |
948 | } | |
949 | ||
064b53db | 950 | /** |
70675e0b | 951 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
952 | * @dev: PCI device to have its BARs restored |
953 | * | |
954 | * Restore the BAR values for a given device, so as to make it | |
955 | * accessible by its driver. | |
956 | */ | |
3c78bc61 | 957 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 958 | { |
bc5f5a82 | 959 | int i; |
064b53db | 960 | |
bc5f5a82 | 961 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 962 | pci_update_resource(dev, i); |
064b53db JL |
963 | } |
964 | ||
299f2ffe | 965 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 966 | |
299f2ffe | 967 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 968 | { |
cc7cc02b | 969 | if (!ops->is_manageable || !ops->set_state || !ops->get_state || |
0847684c | 970 | !ops->choose_state || !ops->set_wakeup || !ops->need_resume) |
961d9120 RW |
971 | return -EINVAL; |
972 | pci_platform_pm = ops; | |
973 | return 0; | |
974 | } | |
975 | ||
976 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
977 | { | |
978 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
979 | } | |
980 | ||
981 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 982 | pci_power_t t) |
961d9120 RW |
983 | { |
984 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
985 | } | |
986 | ||
cc7cc02b LW |
987 | static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) |
988 | { | |
989 | return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; | |
990 | } | |
991 | ||
b51033e0 RW |
992 | static inline void platform_pci_refresh_power_state(struct pci_dev *dev) |
993 | { | |
994 | if (pci_platform_pm && pci_platform_pm->refresh_state) | |
995 | pci_platform_pm->refresh_state(dev); | |
996 | } | |
997 | ||
961d9120 RW |
998 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
999 | { | |
1000 | return pci_platform_pm ? | |
1001 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
1002 | } | |
8f7020d3 | 1003 | |
0847684c | 1004 | static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1005 | { |
1006 | return pci_platform_pm ? | |
0847684c | 1007 | pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; |
b67ea761 RW |
1008 | } |
1009 | ||
bac2a909 RW |
1010 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
1011 | { | |
1012 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
1013 | } | |
1014 | ||
26ad34d5 MW |
1015 | static inline bool platform_pci_bridge_d3(struct pci_dev *dev) |
1016 | { | |
c3aaf086 BH |
1017 | if (pci_platform_pm && pci_platform_pm->bridge_d3) |
1018 | return pci_platform_pm->bridge_d3(dev); | |
1019 | return false; | |
26ad34d5 MW |
1020 | } |
1021 | ||
1da177e4 | 1022 | /** |
44e4e66e | 1023 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
74356add | 1024 | * given PCI device |
44e4e66e | 1025 | * @dev: PCI device to handle. |
44e4e66e | 1026 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 1027 | * |
44e4e66e RW |
1028 | * RETURN VALUE: |
1029 | * -EINVAL if the requested state is invalid. | |
1030 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
1031 | * wrong version, or device doesn't support the requested state. | |
1032 | * 0 if device already is in the requested state. | |
1033 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 1034 | */ |
f00a20ef | 1035 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 1036 | { |
337001b6 | 1037 | u16 pmcsr; |
44e4e66e | 1038 | bool need_restore = false; |
1da177e4 | 1039 | |
4a865905 RW |
1040 | /* Check if we're already there */ |
1041 | if (dev->current_state == state) | |
1042 | return 0; | |
1043 | ||
337001b6 | 1044 | if (!dev->pm_cap) |
cca03dec AL |
1045 | return -EIO; |
1046 | ||
44e4e66e RW |
1047 | if (state < PCI_D0 || state > PCI_D3hot) |
1048 | return -EINVAL; | |
1049 | ||
74356add | 1050 | /* |
e43f15ea BH |
1051 | * Validate transition: We can enter D0 from any state, but if |
1052 | * we're already in a low-power state, we can only go deeper. E.g., | |
1053 | * we can go from D1 to D3, but we can't go directly from D3 to D1; | |
1054 | * we'd have to go from D3 to D0, then to D1. | |
1da177e4 | 1055 | */ |
4a865905 | 1056 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 1057 | && dev->current_state > state) { |
e43f15ea BH |
1058 | pci_err(dev, "invalid power transition (from %s to %s)\n", |
1059 | pci_power_name(dev->current_state), | |
1060 | pci_power_name(state)); | |
1da177e4 | 1061 | return -EINVAL; |
44e4e66e | 1062 | } |
1da177e4 | 1063 | |
74356add | 1064 | /* Check if this device supports the desired state */ |
337001b6 RW |
1065 | if ((state == PCI_D1 && !dev->d1_support) |
1066 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 1067 | return -EIO; |
1da177e4 | 1068 | |
337001b6 | 1069 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
327ccbbc BH |
1070 | if (pmcsr == (u16) ~0) { |
1071 | pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n", | |
1072 | pci_power_name(dev->current_state), | |
1073 | pci_power_name(state)); | |
1074 | return -EIO; | |
1075 | } | |
064b53db | 1076 | |
74356add BH |
1077 | /* |
1078 | * If we're (effectively) in D3, force entire word to 0. | |
1da177e4 LT |
1079 | * This doesn't affect PME_Status, disables PME_En, and |
1080 | * sets PowerState to 0. | |
1081 | */ | |
32a36585 | 1082 | switch (dev->current_state) { |
d3535fbb JL |
1083 | case PCI_D0: |
1084 | case PCI_D1: | |
1085 | case PCI_D2: | |
1086 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
1087 | pmcsr |= state; | |
1088 | break; | |
f62795f1 RW |
1089 | case PCI_D3hot: |
1090 | case PCI_D3cold: | |
32a36585 JL |
1091 | case PCI_UNKNOWN: /* Boot-up */ |
1092 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 1093 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 1094 | need_restore = true; |
df561f66 | 1095 | fallthrough; /* force to D0 */ |
32a36585 | 1096 | default: |
d3535fbb | 1097 | pmcsr = 0; |
32a36585 | 1098 | break; |
1da177e4 LT |
1099 | } |
1100 | ||
74356add | 1101 | /* Enter specified state */ |
337001b6 | 1102 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 | 1103 | |
74356add BH |
1104 | /* |
1105 | * Mandatory power management transition delays; see PCI PM 1.1 | |
1106 | * 5.6.1 table 18 | |
1107 | */ | |
1da177e4 | 1108 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
1ae861e6 | 1109 | pci_dev_d3_sleep(dev); |
1da177e4 | 1110 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
638c133e | 1111 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 1112 | |
e13cdbd7 RW |
1113 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
1114 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
7f1c62c4 | 1115 | if (dev->current_state != state) |
e43f15ea BH |
1116 | pci_info_ratelimited(dev, "refused to change power state from %s to %s\n", |
1117 | pci_power_name(dev->current_state), | |
1118 | pci_power_name(state)); | |
064b53db | 1119 | |
448bd857 HY |
1120 | /* |
1121 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
1122 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
1123 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
1124 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
1125 | * For example, at least some versions of the 3c905B and the | |
1126 | * 3c556B exhibit this behaviour. | |
1127 | * | |
1128 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
1129 | * devices in a D3hot state at boot. Consequently, we need to | |
1130 | * restore at least the BARs so that the device will be | |
1131 | * accessible to its driver. | |
1132 | */ | |
1133 | if (need_restore) | |
1134 | pci_restore_bars(dev); | |
1135 | ||
f00a20ef | 1136 | if (dev->bus->self) |
7d715a6c SL |
1137 | pcie_aspm_pm_state_change(dev->bus->self); |
1138 | ||
1da177e4 LT |
1139 | return 0; |
1140 | } | |
1141 | ||
44e4e66e | 1142 | /** |
a6a64026 | 1143 | * pci_update_current_state - Read power state of given device and cache it |
44e4e66e | 1144 | * @dev: PCI device to handle. |
f06fc0b6 | 1145 | * @state: State to cache in case the device doesn't have the PM capability |
a6a64026 LW |
1146 | * |
1147 | * The power state is read from the PMCSR register, which however is | |
1148 | * inaccessible in D3cold. The platform firmware is therefore queried first | |
1149 | * to detect accessibility of the register. In case the platform firmware | |
1150 | * reports an incorrect state or the device isn't power manageable by the | |
1151 | * platform at all, we try to detect D3cold by testing accessibility of the | |
1152 | * vendor ID in config space. | |
44e4e66e | 1153 | */ |
73410429 | 1154 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 1155 | { |
a6a64026 LW |
1156 | if (platform_pci_get_power_state(dev) == PCI_D3cold || |
1157 | !pci_device_is_present(dev)) { | |
1158 | dev->current_state = PCI_D3cold; | |
1159 | } else if (dev->pm_cap) { | |
44e4e66e RW |
1160 | u16 pmcsr; |
1161 | ||
337001b6 | 1162 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 1163 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
1164 | } else { |
1165 | dev->current_state = state; | |
44e4e66e RW |
1166 | } |
1167 | } | |
1168 | ||
b51033e0 RW |
1169 | /** |
1170 | * pci_refresh_power_state - Refresh the given device's power state data | |
1171 | * @dev: Target PCI device. | |
1172 | * | |
1173 | * Ask the platform to refresh the devices power state information and invoke | |
1174 | * pci_update_current_state() to update its current PCI power state. | |
1175 | */ | |
1176 | void pci_refresh_power_state(struct pci_dev *dev) | |
1177 | { | |
1178 | if (platform_pci_power_manageable(dev)) | |
1179 | platform_pci_refresh_power_state(dev); | |
1180 | ||
1181 | pci_update_current_state(dev, dev->current_state); | |
1182 | } | |
1183 | ||
0e5dd46b RW |
1184 | /** |
1185 | * pci_platform_power_transition - Use platform to change device power state | |
1186 | * @dev: PCI device to handle. | |
1187 | * @state: State to put the device into. | |
1188 | */ | |
d6aa37cd | 1189 | int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) |
0e5dd46b RW |
1190 | { |
1191 | int error; | |
1192 | ||
1193 | if (platform_pci_power_manageable(dev)) { | |
1194 | error = platform_pci_set_power_state(dev, state); | |
1195 | if (!error) | |
1196 | pci_update_current_state(dev, state); | |
769ba721 | 1197 | } else |
0e5dd46b | 1198 | error = -ENODEV; |
769ba721 RW |
1199 | |
1200 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
1201 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
1202 | |
1203 | return error; | |
1204 | } | |
d6aa37cd | 1205 | EXPORT_SYMBOL_GPL(pci_platform_power_transition); |
0e5dd46b | 1206 | |
99efde6c | 1207 | static int pci_resume_one(struct pci_dev *pci_dev, void *ign) |
0b950f0f | 1208 | { |
0b950f0f SH |
1209 | pm_request_resume(&pci_dev->dev); |
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | /** | |
99efde6c | 1214 | * pci_resume_bus - Walk given bus and runtime resume devices on it |
0b950f0f SH |
1215 | * @bus: Top bus of the subtree to walk. |
1216 | */ | |
99efde6c | 1217 | void pci_resume_bus(struct pci_bus *bus) |
0b950f0f SH |
1218 | { |
1219 | if (bus) | |
99efde6c | 1220 | pci_walk_bus(bus, pci_resume_one, NULL); |
0b950f0f SH |
1221 | } |
1222 | ||
bae26849 VS |
1223 | static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) |
1224 | { | |
1225 | int delay = 1; | |
1226 | u32 id; | |
1227 | ||
1228 | /* | |
1229 | * After reset, the device should not silently discard config | |
1230 | * requests, but it may still indicate that it needs more time by | |
1231 | * responding to them with CRS completions. The Root Port will | |
1232 | * generally synthesize ~0 data to complete the read (except when | |
1233 | * CRS SV is enabled and the read was for the Vendor ID; in that | |
1234 | * case it synthesizes 0x0001 data). | |
1235 | * | |
1236 | * Wait for the device to return a non-CRS completion. Read the | |
1237 | * Command register instead of Vendor ID so we don't have to | |
1238 | * contend with the CRS SV value. | |
1239 | */ | |
1240 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
1241 | while (id == ~0) { | |
1242 | if (delay > timeout) { | |
1243 | pci_warn(dev, "not ready %dms after %s; giving up\n", | |
1244 | delay - 1, reset_type); | |
1245 | return -ENOTTY; | |
1246 | } | |
1247 | ||
1248 | if (delay > 1000) | |
1249 | pci_info(dev, "not ready %dms after %s; waiting\n", | |
1250 | delay - 1, reset_type); | |
1251 | ||
1252 | msleep(delay); | |
1253 | delay *= 2; | |
1254 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
1255 | } | |
1256 | ||
1257 | if (delay > 1000) | |
1258 | pci_info(dev, "ready %dms after %s\n", delay - 1, | |
1259 | reset_type); | |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
0e5dd46b | 1264 | /** |
dc2256b0 RW |
1265 | * pci_power_up - Put the given device into D0 |
1266 | * @dev: PCI device to power up | |
0e5dd46b | 1267 | */ |
dc2256b0 | 1268 | int pci_power_up(struct pci_dev *dev) |
0e5dd46b | 1269 | { |
dc2256b0 RW |
1270 | pci_platform_power_transition(dev, PCI_D0); |
1271 | ||
1272 | /* | |
ad9001f2 MW |
1273 | * Mandatory power management transition delays are handled in |
1274 | * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the | |
1275 | * corresponding bridge. | |
dc2256b0 RW |
1276 | */ |
1277 | if (dev->runtime_d3cold) { | |
448bd857 | 1278 | /* |
dc2256b0 RW |
1279 | * When powering on a bridge from D3cold, the whole hierarchy |
1280 | * may be powered on into D0uninitialized state, resume them to | |
1281 | * give them a chance to suspend again | |
448bd857 | 1282 | */ |
99efde6c | 1283 | pci_resume_bus(dev->subordinate); |
448bd857 | 1284 | } |
448bd857 | 1285 | |
adfac8f6 | 1286 | return pci_raw_set_power_state(dev, PCI_D0); |
448bd857 HY |
1287 | } |
1288 | ||
1289 | /** | |
1290 | * __pci_dev_set_current_state - Set current state of a PCI device | |
1291 | * @dev: Device to handle | |
1292 | * @data: pointer to state to be set | |
1293 | */ | |
1294 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
1295 | { | |
1296 | pci_power_t state = *(pci_power_t *)data; | |
1297 | ||
1298 | dev->current_state = state; | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | /** | |
2a4d2c42 | 1303 | * pci_bus_set_current_state - Walk given bus and set current state of devices |
448bd857 HY |
1304 | * @bus: Top bus of the subtree to walk. |
1305 | * @state: state to be set | |
1306 | */ | |
2a4d2c42 | 1307 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) |
448bd857 HY |
1308 | { |
1309 | if (bus) | |
1310 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
1311 | } |
1312 | ||
44e4e66e RW |
1313 | /** |
1314 | * pci_set_power_state - Set the power state of a PCI device | |
1315 | * @dev: PCI device to handle. | |
1316 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
1317 | * | |
877d0310 | 1318 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
1319 | * the device's PCI PM registers. |
1320 | * | |
1321 | * RETURN VALUE: | |
1322 | * -EINVAL if the requested state is invalid. | |
1323 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
1324 | * wrong version, or device doesn't support the requested state. | |
ab4b8a47 | 1325 | * 0 if the transition is to D1 or D2 but D1 and D2 are not supported. |
44e4e66e | 1326 | * 0 if device already is in the requested state. |
ab4b8a47 | 1327 | * 0 if the transition is to D3 but D3 is not supported. |
44e4e66e RW |
1328 | * 0 if device's power state has been successfully changed. |
1329 | */ | |
1330 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
1331 | { | |
337001b6 | 1332 | int error; |
44e4e66e | 1333 | |
74356add | 1334 | /* Bound the state we're entering */ |
448bd857 HY |
1335 | if (state > PCI_D3cold) |
1336 | state = PCI_D3cold; | |
44e4e66e RW |
1337 | else if (state < PCI_D0) |
1338 | state = PCI_D0; | |
1339 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
74356add | 1340 | |
44e4e66e | 1341 | /* |
74356add BH |
1342 | * If the device or the parent bridge do not support PCI |
1343 | * PM, ignore the request if we're doing anything other | |
1344 | * than putting it into D0 (which would only happen on | |
1345 | * boot). | |
44e4e66e RW |
1346 | */ |
1347 | return 0; | |
1348 | ||
db288c9c RW |
1349 | /* Check if we're already there */ |
1350 | if (dev->current_state == state) | |
1351 | return 0; | |
1352 | ||
adfac8f6 RW |
1353 | if (state == PCI_D0) |
1354 | return pci_power_up(dev); | |
0e5dd46b | 1355 | |
74356add BH |
1356 | /* |
1357 | * This device is quirked not to be put into D3, so don't put it in | |
1358 | * D3 | |
1359 | */ | |
448bd857 | 1360 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 1361 | return 0; |
44e4e66e | 1362 | |
448bd857 HY |
1363 | /* |
1364 | * To put device in D3cold, we put device into D3hot in native | |
1365 | * way, then put device into D3cold with platform ops | |
1366 | */ | |
1367 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
1368 | PCI_D3hot : state); | |
44e4e66e | 1369 | |
9c77e63b RW |
1370 | if (pci_platform_power_transition(dev, state)) |
1371 | return error; | |
44e4e66e | 1372 | |
9c77e63b RW |
1373 | /* Powering off a bridge may power off the whole hierarchy */ |
1374 | if (state == PCI_D3cold) | |
1375 | pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
44e4e66e | 1376 | |
9c77e63b | 1377 | return 0; |
45144d42 | 1378 | } |
b7fe9434 | 1379 | EXPORT_SYMBOL(pci_set_power_state); |
45144d42 | 1380 | |
1da177e4 LT |
1381 | /** |
1382 | * pci_choose_state - Choose the power state of a PCI device | |
1383 | * @dev: PCI device to be suspended | |
1384 | * @state: target sleep state for the whole system. This is the value | |
74356add | 1385 | * that is passed to suspend() function. |
1da177e4 LT |
1386 | * |
1387 | * Returns PCI power state suitable for given device and given system | |
1388 | * message. | |
1389 | */ | |
1da177e4 LT |
1390 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) |
1391 | { | |
ab826ca4 | 1392 | pci_power_t ret; |
0f64474b | 1393 | |
728cdb75 | 1394 | if (!dev->pm_cap) |
1da177e4 LT |
1395 | return PCI_D0; |
1396 | ||
961d9120 RW |
1397 | ret = platform_pci_choose_state(dev); |
1398 | if (ret != PCI_POWER_ERROR) | |
1399 | return ret; | |
ca078bae PM |
1400 | |
1401 | switch (state.event) { | |
1402 | case PM_EVENT_ON: | |
1403 | return PCI_D0; | |
1404 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
1405 | case PM_EVENT_PRETHAW: |
1406 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 1407 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 1408 | case PM_EVENT_HIBERNATE: |
ca078bae | 1409 | return PCI_D3hot; |
1da177e4 | 1410 | default: |
7506dc79 | 1411 | pci_info(dev, "unrecognized suspend event %d\n", |
80ccba11 | 1412 | state.event); |
1da177e4 LT |
1413 | BUG(); |
1414 | } | |
1415 | return PCI_D0; | |
1416 | } | |
1da177e4 LT |
1417 | EXPORT_SYMBOL(pci_choose_state); |
1418 | ||
89858517 YZ |
1419 | #define PCI_EXP_SAVE_REGS 7 |
1420 | ||
fd0f7f73 AW |
1421 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
1422 | u16 cap, bool extended) | |
34a4876e YL |
1423 | { |
1424 | struct pci_cap_saved_state *tmp; | |
34a4876e | 1425 | |
b67bfe0d | 1426 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 1427 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
1428 | return tmp; |
1429 | } | |
1430 | return NULL; | |
1431 | } | |
1432 | ||
fd0f7f73 AW |
1433 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
1434 | { | |
1435 | return _pci_find_saved_cap(dev, cap, false); | |
1436 | } | |
1437 | ||
1438 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
1439 | { | |
1440 | return _pci_find_saved_cap(dev, cap, true); | |
1441 | } | |
1442 | ||
b56a5a23 MT |
1443 | static int pci_save_pcie_state(struct pci_dev *dev) |
1444 | { | |
59875ae4 | 1445 | int i = 0; |
b56a5a23 MT |
1446 | struct pci_cap_saved_state *save_state; |
1447 | u16 *cap; | |
1448 | ||
59875ae4 | 1449 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
1450 | return 0; |
1451 | ||
9f35575d | 1452 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 1453 | if (!save_state) { |
7506dc79 | 1454 | pci_err(dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
1455 | return -ENOMEM; |
1456 | } | |
63f4898a | 1457 | |
59875ae4 JL |
1458 | cap = (u16 *)&save_state->cap.data[0]; |
1459 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
1460 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1461 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1462 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1463 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1464 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1465 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1466 | |
b56a5a23 MT |
1467 | return 0; |
1468 | } | |
1469 | ||
1470 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
1471 | { | |
59875ae4 | 1472 | int i = 0; |
b56a5a23 MT |
1473 | struct pci_cap_saved_state *save_state; |
1474 | u16 *cap; | |
1475 | ||
1476 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1477 | if (!save_state) |
9cb604ed MS |
1478 | return; |
1479 | ||
59875ae4 JL |
1480 | cap = (u16 *)&save_state->cap.data[0]; |
1481 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1482 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1483 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1484 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1485 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1486 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1487 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1488 | } |
1489 | ||
cc692a5f SH |
1490 | static int pci_save_pcix_state(struct pci_dev *dev) |
1491 | { | |
63f4898a | 1492 | int pos; |
cc692a5f | 1493 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1494 | |
1495 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1496 | if (!pos) |
cc692a5f SH |
1497 | return 0; |
1498 | ||
f34303de | 1499 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1500 | if (!save_state) { |
7506dc79 | 1501 | pci_err(dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1502 | return -ENOMEM; |
1503 | } | |
cc692a5f | 1504 | |
24a4742f AW |
1505 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1506 | (u16 *)save_state->cap.data); | |
63f4898a | 1507 | |
cc692a5f SH |
1508 | return 0; |
1509 | } | |
1510 | ||
1511 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1512 | { | |
1513 | int i = 0, pos; | |
1514 | struct pci_cap_saved_state *save_state; | |
1515 | u16 *cap; | |
1516 | ||
1517 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1518 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1519 | if (!save_state || !pos) |
cc692a5f | 1520 | return; |
24a4742f | 1521 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1522 | |
1523 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1524 | } |
1525 | ||
dbbfadf2 BH |
1526 | static void pci_save_ltr_state(struct pci_dev *dev) |
1527 | { | |
1528 | int ltr; | |
1529 | struct pci_cap_saved_state *save_state; | |
1530 | u16 *cap; | |
1531 | ||
1532 | if (!pci_is_pcie(dev)) | |
1533 | return; | |
1534 | ||
1535 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1536 | if (!ltr) | |
1537 | return; | |
1538 | ||
1539 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1540 | if (!save_state) { | |
1541 | pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); | |
1542 | return; | |
1543 | } | |
1544 | ||
1545 | cap = (u16 *)&save_state->cap.data[0]; | |
1546 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++); | |
1547 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++); | |
1548 | } | |
1549 | ||
1550 | static void pci_restore_ltr_state(struct pci_dev *dev) | |
1551 | { | |
1552 | struct pci_cap_saved_state *save_state; | |
1553 | int ltr; | |
1554 | u16 *cap; | |
1555 | ||
1556 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1557 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1558 | if (!save_state || !ltr) | |
1559 | return; | |
1560 | ||
1561 | cap = (u16 *)&save_state->cap.data[0]; | |
1562 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++); | |
1563 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++); | |
1564 | } | |
cc692a5f | 1565 | |
1da177e4 | 1566 | /** |
74356add BH |
1567 | * pci_save_state - save the PCI configuration space of a device before |
1568 | * suspending | |
1569 | * @dev: PCI device that we're dealing with | |
1da177e4 | 1570 | */ |
3c78bc61 | 1571 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1572 | { |
1573 | int i; | |
1574 | /* XXX: 100% dword access ok here? */ | |
47b802d5 | 1575 | for (i = 0; i < 16; i++) { |
9e0b5b2c | 1576 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
47b802d5 CY |
1577 | pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n", |
1578 | i * 4, dev->saved_config_space[i]); | |
1579 | } | |
aa8c6c93 | 1580 | dev->state_saved = true; |
79e50e72 QL |
1581 | |
1582 | i = pci_save_pcie_state(dev); | |
1583 | if (i != 0) | |
b56a5a23 | 1584 | return i; |
79e50e72 QL |
1585 | |
1586 | i = pci_save_pcix_state(dev); | |
1587 | if (i != 0) | |
cc692a5f | 1588 | return i; |
79e50e72 | 1589 | |
dbbfadf2 | 1590 | pci_save_ltr_state(dev); |
4f802170 | 1591 | pci_save_dpc_state(dev); |
af65d1ad | 1592 | pci_save_aer_state(dev); |
39850ed5 | 1593 | pci_save_ptm_state(dev); |
754834b9 | 1594 | return pci_save_vc_state(dev); |
1da177e4 | 1595 | } |
b7fe9434 | 1596 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1597 | |
ebfc5b80 | 1598 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
08387454 | 1599 | u32 saved_val, int retry, bool force) |
ebfc5b80 RW |
1600 | { |
1601 | u32 val; | |
1602 | ||
1603 | pci_read_config_dword(pdev, offset, &val); | |
08387454 | 1604 | if (!force && val == saved_val) |
ebfc5b80 RW |
1605 | return; |
1606 | ||
1607 | for (;;) { | |
7506dc79 | 1608 | pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
227f0647 | 1609 | offset, val, saved_val); |
ebfc5b80 RW |
1610 | pci_write_config_dword(pdev, offset, saved_val); |
1611 | if (retry-- <= 0) | |
1612 | return; | |
1613 | ||
1614 | pci_read_config_dword(pdev, offset, &val); | |
1615 | if (val == saved_val) | |
1616 | return; | |
1617 | ||
1618 | mdelay(1); | |
1619 | } | |
1620 | } | |
1621 | ||
a6cb9ee7 | 1622 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
08387454 DD |
1623 | int start, int end, int retry, |
1624 | bool force) | |
ebfc5b80 RW |
1625 | { |
1626 | int index; | |
1627 | ||
1628 | for (index = end; index >= start; index--) | |
1629 | pci_restore_config_dword(pdev, 4 * index, | |
1630 | pdev->saved_config_space[index], | |
08387454 | 1631 | retry, force); |
ebfc5b80 RW |
1632 | } |
1633 | ||
a6cb9ee7 RW |
1634 | static void pci_restore_config_space(struct pci_dev *pdev) |
1635 | { | |
1636 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
08387454 | 1637 | pci_restore_config_space_range(pdev, 10, 15, 0, false); |
a6cb9ee7 | 1638 | /* Restore BARs before the command register. */ |
08387454 DD |
1639 | pci_restore_config_space_range(pdev, 4, 9, 10, false); |
1640 | pci_restore_config_space_range(pdev, 0, 3, 0, false); | |
1641 | } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1642 | pci_restore_config_space_range(pdev, 12, 15, 0, false); | |
1643 | ||
1644 | /* | |
1645 | * Force rewriting of prefetch registers to avoid S3 resume | |
1646 | * issues on Intel PCI bridges that occur when these | |
1647 | * registers are not explicitly written. | |
1648 | */ | |
1649 | pci_restore_config_space_range(pdev, 9, 11, 0, true); | |
1650 | pci_restore_config_space_range(pdev, 0, 8, 0, false); | |
a6cb9ee7 | 1651 | } else { |
08387454 | 1652 | pci_restore_config_space_range(pdev, 0, 15, 0, false); |
a6cb9ee7 RW |
1653 | } |
1654 | } | |
1655 | ||
d3252ace CK |
1656 | static void pci_restore_rebar_state(struct pci_dev *pdev) |
1657 | { | |
1658 | unsigned int pos, nbars, i; | |
1659 | u32 ctrl; | |
1660 | ||
1661 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
1662 | if (!pos) | |
1663 | return; | |
1664 | ||
1665 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1666 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
1667 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
1668 | ||
1669 | for (i = 0; i < nbars; i++, pos += 8) { | |
1670 | struct resource *res; | |
1671 | int bar_idx, size; | |
1672 | ||
1673 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1674 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
1675 | res = pdev->resource + bar_idx; | |
192f1bf7 | 1676 | size = pci_rebar_bytes_to_size(resource_size(res)); |
d3252ace | 1677 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; |
b1277a22 | 1678 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
d3252ace CK |
1679 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
1680 | } | |
1681 | } | |
1682 | ||
f7625980 | 1683 | /** |
1da177e4 | 1684 | * pci_restore_state - Restore the saved state of a PCI device |
74356add | 1685 | * @dev: PCI device that we're dealing with |
1da177e4 | 1686 | */ |
1d3c16a8 | 1687 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1688 | { |
c82f63e4 | 1689 | if (!dev->state_saved) |
1d3c16a8 | 1690 | return; |
4b77b0a2 | 1691 | |
dbbfadf2 BH |
1692 | /* |
1693 | * Restore max latencies (in the LTR capability) before enabling | |
1694 | * LTR itself (in the PCIe capability). | |
1695 | */ | |
1696 | pci_restore_ltr_state(dev); | |
1697 | ||
b56a5a23 | 1698 | pci_restore_pcie_state(dev); |
4ebeb1ec CT |
1699 | pci_restore_pasid_state(dev); |
1700 | pci_restore_pri_state(dev); | |
1900ca13 | 1701 | pci_restore_ats_state(dev); |
425c1b22 | 1702 | pci_restore_vc_state(dev); |
d3252ace | 1703 | pci_restore_rebar_state(dev); |
4f802170 | 1704 | pci_restore_dpc_state(dev); |
39850ed5 | 1705 | pci_restore_ptm_state(dev); |
b56a5a23 | 1706 | |
894020fd | 1707 | pci_aer_clear_status(dev); |
af65d1ad | 1708 | pci_restore_aer_state(dev); |
b07461a8 | 1709 | |
a6cb9ee7 | 1710 | pci_restore_config_space(dev); |
ebfc5b80 | 1711 | |
cc692a5f | 1712 | pci_restore_pcix_state(dev); |
41017f0c | 1713 | pci_restore_msi_state(dev); |
ccbc175a AD |
1714 | |
1715 | /* Restore ACS and IOV configuration state */ | |
1716 | pci_enable_acs(dev); | |
8c5cdb6a | 1717 | pci_restore_iov_state(dev); |
8fed4b65 | 1718 | |
4b77b0a2 | 1719 | dev->state_saved = false; |
1da177e4 | 1720 | } |
b7fe9434 | 1721 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1722 | |
ffbdd3f7 AW |
1723 | struct pci_saved_state { |
1724 | u32 config_space[16]; | |
914a1951 | 1725 | struct pci_cap_saved_data cap[]; |
ffbdd3f7 AW |
1726 | }; |
1727 | ||
1728 | /** | |
1729 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1730 | * the device saved state. | |
1731 | * @dev: PCI device that we're dealing with | |
1732 | * | |
f7625980 | 1733 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1734 | */ |
1735 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1736 | { | |
1737 | struct pci_saved_state *state; | |
1738 | struct pci_cap_saved_state *tmp; | |
1739 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1740 | size_t size; |
1741 | ||
1742 | if (!dev->state_saved) | |
1743 | return NULL; | |
1744 | ||
1745 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1746 | ||
b67bfe0d | 1747 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1748 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1749 | ||
1750 | state = kzalloc(size, GFP_KERNEL); | |
1751 | if (!state) | |
1752 | return NULL; | |
1753 | ||
1754 | memcpy(state->config_space, dev->saved_config_space, | |
1755 | sizeof(state->config_space)); | |
1756 | ||
1757 | cap = state->cap; | |
b67bfe0d | 1758 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1759 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1760 | memcpy(cap, &tmp->cap, len); | |
1761 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1762 | } | |
1763 | /* Empty cap_save terminates list */ | |
1764 | ||
1765 | return state; | |
1766 | } | |
1767 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1768 | ||
1769 | /** | |
1770 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1771 | * @dev: PCI device that we're dealing with | |
1772 | * @state: Saved state returned from pci_store_saved_state() | |
1773 | */ | |
98d9b271 KRW |
1774 | int pci_load_saved_state(struct pci_dev *dev, |
1775 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1776 | { |
1777 | struct pci_cap_saved_data *cap; | |
1778 | ||
1779 | dev->state_saved = false; | |
1780 | ||
1781 | if (!state) | |
1782 | return 0; | |
1783 | ||
1784 | memcpy(dev->saved_config_space, state->config_space, | |
1785 | sizeof(state->config_space)); | |
1786 | ||
1787 | cap = state->cap; | |
1788 | while (cap->size) { | |
1789 | struct pci_cap_saved_state *tmp; | |
1790 | ||
fd0f7f73 | 1791 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1792 | if (!tmp || tmp->cap.size != cap->size) |
1793 | return -EINVAL; | |
1794 | ||
1795 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1796 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1797 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1798 | } | |
1799 | ||
1800 | dev->state_saved = true; | |
1801 | return 0; | |
1802 | } | |
98d9b271 | 1803 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1804 | |
1805 | /** | |
1806 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1807 | * and free the memory allocated for it. | |
1808 | * @dev: PCI device that we're dealing with | |
1809 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1810 | */ | |
1811 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1812 | struct pci_saved_state **state) | |
1813 | { | |
1814 | int ret = pci_load_saved_state(dev, *state); | |
1815 | kfree(*state); | |
1816 | *state = NULL; | |
1817 | return ret; | |
1818 | } | |
1819 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1820 | ||
8a9d5609 BH |
1821 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1822 | { | |
1823 | return pci_enable_resources(dev, bars); | |
1824 | } | |
1825 | ||
38cc1302 HS |
1826 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1827 | { | |
1828 | int err; | |
1f6ae47e | 1829 | struct pci_dev *bridge; |
1e2571a7 BH |
1830 | u16 cmd; |
1831 | u8 pin; | |
38cc1302 HS |
1832 | |
1833 | err = pci_set_power_state(dev, PCI_D0); | |
1834 | if (err < 0 && err != -EIO) | |
1835 | return err; | |
1f6ae47e VS |
1836 | |
1837 | bridge = pci_upstream_bridge(dev); | |
1838 | if (bridge) | |
1839 | pcie_aspm_powersave_config_link(bridge); | |
1840 | ||
38cc1302 HS |
1841 | err = pcibios_enable_device(dev, bars); |
1842 | if (err < 0) | |
1843 | return err; | |
1844 | pci_fixup_device(pci_fixup_enable, dev); | |
1845 | ||
866d5417 BH |
1846 | if (dev->msi_enabled || dev->msix_enabled) |
1847 | return 0; | |
1848 | ||
1e2571a7 BH |
1849 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1850 | if (pin) { | |
1851 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1852 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1853 | pci_write_config_word(dev, PCI_COMMAND, | |
1854 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1855 | } | |
1856 | ||
38cc1302 HS |
1857 | return 0; |
1858 | } | |
1859 | ||
1860 | /** | |
0b62e13b | 1861 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1862 | * @dev: PCI device to be resumed |
1863 | * | |
74356add BH |
1864 | * NOTE: This function is a backend of pci_default_resume() and is not supposed |
1865 | * to be called by normal code, write proper resume handler and use it instead. | |
38cc1302 | 1866 | */ |
0b62e13b | 1867 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1868 | { |
296ccb08 | 1869 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1870 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1871 | return 0; | |
1872 | } | |
b7fe9434 | 1873 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1874 | |
928bea96 YL |
1875 | static void pci_enable_bridge(struct pci_dev *dev) |
1876 | { | |
79272138 | 1877 | struct pci_dev *bridge; |
928bea96 YL |
1878 | int retval; |
1879 | ||
79272138 BH |
1880 | bridge = pci_upstream_bridge(dev); |
1881 | if (bridge) | |
1882 | pci_enable_bridge(bridge); | |
928bea96 | 1883 | |
cf3e1feb | 1884 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1885 | if (!dev->is_busmaster) |
cf3e1feb | 1886 | pci_set_master(dev); |
0f50a49e | 1887 | return; |
cf3e1feb YL |
1888 | } |
1889 | ||
928bea96 YL |
1890 | retval = pci_enable_device(dev); |
1891 | if (retval) | |
7506dc79 | 1892 | pci_err(dev, "Error enabling bridge (%d), continuing\n", |
928bea96 YL |
1893 | retval); |
1894 | pci_set_master(dev); | |
1895 | } | |
1896 | ||
b4b4fbba | 1897 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1898 | { |
79272138 | 1899 | struct pci_dev *bridge; |
1da177e4 | 1900 | int err; |
b718989d | 1901 | int i, bars = 0; |
1da177e4 | 1902 | |
4514d991 RW |
1903 | if (atomic_inc_return(&dev->enable_cnt) > 1) { |
1904 | pci_update_current_state(dev, dev->current_state); | |
9fb625c3 | 1905 | return 0; /* already enabled */ |
4514d991 | 1906 | } |
9fb625c3 | 1907 | |
79272138 | 1908 | bridge = pci_upstream_bridge(dev); |
0f50a49e | 1909 | if (bridge) |
79272138 | 1910 | pci_enable_bridge(bridge); |
928bea96 | 1911 | |
497f16f2 YL |
1912 | /* only skip sriov related */ |
1913 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1914 | if (dev->resource[i].flags & flags) | |
1915 | bars |= (1 << i); | |
1916 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1917 | if (dev->resource[i].flags & flags) |
1918 | bars |= (1 << i); | |
1919 | ||
38cc1302 | 1920 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1921 | if (err < 0) |
38cc1302 | 1922 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1923 | return err; |
1da177e4 LT |
1924 | } |
1925 | ||
b718989d BH |
1926 | /** |
1927 | * pci_enable_device_io - Initialize a device for use with IO space | |
1928 | * @dev: PCI device to be initialized | |
1929 | * | |
74356add BH |
1930 | * Initialize device before it's used by a driver. Ask low-level code |
1931 | * to enable I/O resources. Wake up the device if it was suspended. | |
1932 | * Beware, this function can fail. | |
b718989d BH |
1933 | */ |
1934 | int pci_enable_device_io(struct pci_dev *dev) | |
1935 | { | |
b4b4fbba | 1936 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1937 | } |
b7fe9434 | 1938 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1939 | |
1940 | /** | |
1941 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1942 | * @dev: PCI device to be initialized | |
1943 | * | |
74356add BH |
1944 | * Initialize device before it's used by a driver. Ask low-level code |
1945 | * to enable Memory resources. Wake up the device if it was suspended. | |
1946 | * Beware, this function can fail. | |
b718989d BH |
1947 | */ |
1948 | int pci_enable_device_mem(struct pci_dev *dev) | |
1949 | { | |
b4b4fbba | 1950 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1951 | } |
b7fe9434 | 1952 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1953 | |
bae94d02 IPG |
1954 | /** |
1955 | * pci_enable_device - Initialize device before it's used by a driver. | |
1956 | * @dev: PCI device to be initialized | |
1957 | * | |
74356add BH |
1958 | * Initialize device before it's used by a driver. Ask low-level code |
1959 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1960 | * Beware, this function can fail. | |
bae94d02 | 1961 | * |
74356add BH |
1962 | * Note we don't actually enable the device many times if we call |
1963 | * this function repeatedly (we just increment the count). | |
bae94d02 IPG |
1964 | */ |
1965 | int pci_enable_device(struct pci_dev *dev) | |
1966 | { | |
b4b4fbba | 1967 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1968 | } |
b7fe9434 | 1969 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1970 | |
9ac7849e | 1971 | /* |
74356add BH |
1972 | * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X |
1973 | * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so | |
9ac7849e TH |
1974 | * there's no need to track it separately. pci_devres is initialized |
1975 | * when a device is enabled using managed PCI device enable interface. | |
1976 | */ | |
1977 | struct pci_devres { | |
7f375f32 TH |
1978 | unsigned int enabled:1; |
1979 | unsigned int pinned:1; | |
9ac7849e TH |
1980 | unsigned int orig_intx:1; |
1981 | unsigned int restore_intx:1; | |
fc0f9f4d | 1982 | unsigned int mwi:1; |
9ac7849e TH |
1983 | u32 region_mask; |
1984 | }; | |
1985 | ||
1986 | static void pcim_release(struct device *gendev, void *res) | |
1987 | { | |
f3d2f165 | 1988 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
1989 | struct pci_devres *this = res; |
1990 | int i; | |
1991 | ||
1992 | if (dev->msi_enabled) | |
1993 | pci_disable_msi(dev); | |
1994 | if (dev->msix_enabled) | |
1995 | pci_disable_msix(dev); | |
1996 | ||
1997 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1998 | if (this->region_mask & (1 << i)) | |
1999 | pci_release_region(dev, i); | |
2000 | ||
fc0f9f4d HK |
2001 | if (this->mwi) |
2002 | pci_clear_mwi(dev); | |
2003 | ||
9ac7849e TH |
2004 | if (this->restore_intx) |
2005 | pci_intx(dev, this->orig_intx); | |
2006 | ||
7f375f32 | 2007 | if (this->enabled && !this->pinned) |
9ac7849e TH |
2008 | pci_disable_device(dev); |
2009 | } | |
2010 | ||
07656d83 | 2011 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
2012 | { |
2013 | struct pci_devres *dr, *new_dr; | |
2014 | ||
2015 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
2016 | if (dr) | |
2017 | return dr; | |
2018 | ||
2019 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
2020 | if (!new_dr) | |
2021 | return NULL; | |
2022 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
2023 | } | |
2024 | ||
07656d83 | 2025 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
2026 | { |
2027 | if (pci_is_managed(pdev)) | |
2028 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
2029 | return NULL; | |
2030 | } | |
2031 | ||
2032 | /** | |
2033 | * pcim_enable_device - Managed pci_enable_device() | |
2034 | * @pdev: PCI device to be initialized | |
2035 | * | |
2036 | * Managed pci_enable_device(). | |
2037 | */ | |
2038 | int pcim_enable_device(struct pci_dev *pdev) | |
2039 | { | |
2040 | struct pci_devres *dr; | |
2041 | int rc; | |
2042 | ||
2043 | dr = get_pci_dr(pdev); | |
2044 | if (unlikely(!dr)) | |
2045 | return -ENOMEM; | |
b95d58ea TH |
2046 | if (dr->enabled) |
2047 | return 0; | |
9ac7849e TH |
2048 | |
2049 | rc = pci_enable_device(pdev); | |
2050 | if (!rc) { | |
2051 | pdev->is_managed = 1; | |
7f375f32 | 2052 | dr->enabled = 1; |
9ac7849e TH |
2053 | } |
2054 | return rc; | |
2055 | } | |
b7fe9434 | 2056 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
2057 | |
2058 | /** | |
2059 | * pcim_pin_device - Pin managed PCI device | |
2060 | * @pdev: PCI device to pin | |
2061 | * | |
2062 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
2063 | * driver detach. @pdev must have been enabled with | |
2064 | * pcim_enable_device(). | |
2065 | */ | |
2066 | void pcim_pin_device(struct pci_dev *pdev) | |
2067 | { | |
2068 | struct pci_devres *dr; | |
2069 | ||
2070 | dr = find_pci_dr(pdev); | |
7f375f32 | 2071 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 2072 | if (dr) |
7f375f32 | 2073 | dr->pinned = 1; |
9ac7849e | 2074 | } |
b7fe9434 | 2075 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 2076 | |
eca0d467 MG |
2077 | /* |
2078 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
2079 | * @dev: the PCI device being added | |
2080 | * | |
2081 | * Permits the platform to provide architecture specific functionality when | |
2082 | * devices are added. This is the default implementation. Architecture | |
2083 | * implementations can override this. | |
2084 | */ | |
3c78bc61 | 2085 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
2086 | { |
2087 | return 0; | |
2088 | } | |
2089 | ||
6ae32c53 | 2090 | /** |
74356add BH |
2091 | * pcibios_release_device - provide arch specific hooks when releasing |
2092 | * device dev | |
6ae32c53 SO |
2093 | * @dev: the PCI device being released |
2094 | * | |
2095 | * Permits the platform to provide architecture specific functionality when | |
2096 | * devices are released. This is the default implementation. Architecture | |
2097 | * implementations can override this. | |
2098 | */ | |
2099 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
2100 | ||
1da177e4 LT |
2101 | /** |
2102 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
2103 | * @dev: the PCI device to disable | |
2104 | * | |
2105 | * Disables architecture specific PCI resources for the device. This | |
2106 | * is the default implementation. Architecture implementations can | |
2107 | * override this. | |
2108 | */ | |
ff3ce480 | 2109 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 2110 | |
a43ae58c HG |
2111 | /** |
2112 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
2113 | * @irq: ISA IRQ to penalize | |
2114 | * @active: IRQ active or not | |
2115 | * | |
2116 | * Permits the platform to provide architecture-specific functionality when | |
2117 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
2118 | * implementations can override this. | |
2119 | */ | |
2120 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
2121 | ||
fa58d305 RW |
2122 | static void do_pci_disable_device(struct pci_dev *dev) |
2123 | { | |
2124 | u16 pci_command; | |
2125 | ||
2126 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
2127 | if (pci_command & PCI_COMMAND_MASTER) { | |
2128 | pci_command &= ~PCI_COMMAND_MASTER; | |
2129 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
2130 | } | |
2131 | ||
2132 | pcibios_disable_device(dev); | |
2133 | } | |
2134 | ||
2135 | /** | |
2136 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
2137 | * @dev: PCI device to disable | |
2138 | * | |
2139 | * NOTE: This function is a backend of PCI power management routines and is | |
2140 | * not supposed to be called drivers. | |
2141 | */ | |
2142 | void pci_disable_enabled_device(struct pci_dev *dev) | |
2143 | { | |
296ccb08 | 2144 | if (pci_is_enabled(dev)) |
fa58d305 RW |
2145 | do_pci_disable_device(dev); |
2146 | } | |
2147 | ||
1da177e4 LT |
2148 | /** |
2149 | * pci_disable_device - Disable PCI device after use | |
2150 | * @dev: PCI device to be disabled | |
2151 | * | |
2152 | * Signal to the system that the PCI device is not in use by the system | |
2153 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
2154 | * |
2155 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 2156 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 2157 | */ |
3c78bc61 | 2158 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 2159 | { |
9ac7849e | 2160 | struct pci_devres *dr; |
99dc804d | 2161 | |
9ac7849e TH |
2162 | dr = find_pci_dr(dev); |
2163 | if (dr) | |
7f375f32 | 2164 | dr->enabled = 0; |
9ac7849e | 2165 | |
fd6dceab KK |
2166 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
2167 | "disabling already-disabled device"); | |
2168 | ||
cc7ba39b | 2169 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
2170 | return; |
2171 | ||
fa58d305 | 2172 | do_pci_disable_device(dev); |
1da177e4 | 2173 | |
fa58d305 | 2174 | dev->is_busmaster = 0; |
1da177e4 | 2175 | } |
b7fe9434 | 2176 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 2177 | |
f7bdd12d BK |
2178 | /** |
2179 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 2180 | * @dev: the PCIe device reset |
f7bdd12d BK |
2181 | * @state: Reset state to enter into |
2182 | * | |
74356add | 2183 | * Set the PCIe reset state for the device. This is the default |
f7bdd12d BK |
2184 | * implementation. Architecture implementations can override this. |
2185 | */ | |
d6d88c83 BH |
2186 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
2187 | enum pcie_reset_state state) | |
f7bdd12d BK |
2188 | { |
2189 | return -EINVAL; | |
2190 | } | |
2191 | ||
2192 | /** | |
2193 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 2194 | * @dev: the PCIe device reset |
f7bdd12d BK |
2195 | * @state: Reset state to enter into |
2196 | * | |
f7bdd12d BK |
2197 | * Sets the PCI reset state for the device. |
2198 | */ | |
2199 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
2200 | { | |
2201 | return pcibios_set_pcie_reset_state(dev, state); | |
2202 | } | |
b7fe9434 | 2203 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 2204 | |
600a5b4f BH |
2205 | void pcie_clear_device_status(struct pci_dev *dev) |
2206 | { | |
2207 | u16 sta; | |
2208 | ||
2209 | pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); | |
2210 | pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); | |
2211 | } | |
2212 | ||
dcb0453d BH |
2213 | /** |
2214 | * pcie_clear_root_pme_status - Clear root port PME interrupt status. | |
2215 | * @dev: PCIe root port or event collector. | |
2216 | */ | |
2217 | void pcie_clear_root_pme_status(struct pci_dev *dev) | |
2218 | { | |
2219 | pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME); | |
2220 | } | |
2221 | ||
58ff4633 RW |
2222 | /** |
2223 | * pci_check_pme_status - Check if given device has generated PME. | |
2224 | * @dev: Device to check. | |
2225 | * | |
2226 | * Check the PME status of the device and if set, clear it and clear PME enable | |
2227 | * (if set). Return 'true' if PME status and PME enable were both set or | |
2228 | * 'false' otherwise. | |
2229 | */ | |
2230 | bool pci_check_pme_status(struct pci_dev *dev) | |
2231 | { | |
2232 | int pmcsr_pos; | |
2233 | u16 pmcsr; | |
2234 | bool ret = false; | |
2235 | ||
2236 | if (!dev->pm_cap) | |
2237 | return false; | |
2238 | ||
2239 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
2240 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
2241 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
2242 | return false; | |
2243 | ||
2244 | /* Clear PME status. */ | |
2245 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2246 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
2247 | /* Disable PME to avoid interrupt flood. */ | |
2248 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2249 | ret = true; | |
2250 | } | |
2251 | ||
2252 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
2253 | ||
2254 | return ret; | |
2255 | } | |
2256 | ||
b67ea761 RW |
2257 | /** |
2258 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
2259 | * @dev: Device to handle. | |
379021d5 | 2260 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
2261 | * |
2262 | * Check if @dev has generated PME and queue a resume request for it in that | |
2263 | * case. | |
2264 | */ | |
379021d5 | 2265 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 2266 | { |
379021d5 RW |
2267 | if (pme_poll_reset && dev->pme_poll) |
2268 | dev->pme_poll = false; | |
2269 | ||
c125e96f | 2270 | if (pci_check_pme_status(dev)) { |
c125e96f | 2271 | pci_wakeup_event(dev); |
0f953bf6 | 2272 | pm_request_resume(&dev->dev); |
c125e96f | 2273 | } |
b67ea761 RW |
2274 | return 0; |
2275 | } | |
2276 | ||
2277 | /** | |
2278 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
2279 | * @bus: Top bus of the subtree to walk. | |
2280 | */ | |
2281 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
2282 | { | |
2283 | if (bus) | |
379021d5 | 2284 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
2285 | } |
2286 | ||
448bd857 | 2287 | |
eb9d0fe4 RW |
2288 | /** |
2289 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
2290 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
2291 | * @state: PCI state from which device will issue PME#. |
2292 | */ | |
e5899e1b | 2293 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 2294 | { |
337001b6 | 2295 | if (!dev->pm_cap) |
eb9d0fe4 RW |
2296 | return false; |
2297 | ||
337001b6 | 2298 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 2299 | } |
b7fe9434 | 2300 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 2301 | |
df17e62e MG |
2302 | static void pci_pme_list_scan(struct work_struct *work) |
2303 | { | |
379021d5 | 2304 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
2305 | |
2306 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
2307 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
2308 | if (pme_dev->dev->pme_poll) { | |
2309 | struct pci_dev *bridge; | |
2310 | ||
2311 | bridge = pme_dev->dev->bus->self; | |
2312 | /* | |
2313 | * If bridge is in low power state, the | |
2314 | * configuration space of subordinate devices | |
2315 | * may be not accessible | |
2316 | */ | |
2317 | if (bridge && bridge->current_state != PCI_D0) | |
2318 | continue; | |
000dd531 MW |
2319 | /* |
2320 | * If the device is in D3cold it should not be | |
2321 | * polled either. | |
2322 | */ | |
2323 | if (pme_dev->dev->current_state == PCI_D3cold) | |
2324 | continue; | |
2325 | ||
ce300008 BH |
2326 | pci_pme_wakeup(pme_dev->dev, NULL); |
2327 | } else { | |
2328 | list_del(&pme_dev->list); | |
2329 | kfree(pme_dev); | |
379021d5 | 2330 | } |
df17e62e | 2331 | } |
ce300008 | 2332 | if (!list_empty(&pci_pme_list)) |
ea00353f LW |
2333 | queue_delayed_work(system_freezable_wq, &pci_pme_work, |
2334 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2335 | mutex_unlock(&pci_pme_list_mutex); |
2336 | } | |
2337 | ||
2cef548a | 2338 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
2339 | { |
2340 | u16 pmcsr; | |
2341 | ||
ffaddbe8 | 2342 | if (!dev->pme_support) |
eb9d0fe4 RW |
2343 | return; |
2344 | ||
337001b6 | 2345 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
2346 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
2347 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
2348 | if (!enable) | |
2349 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2350 | ||
337001b6 | 2351 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
2352 | } |
2353 | ||
0ce3fcaf RW |
2354 | /** |
2355 | * pci_pme_restore - Restore PME configuration after config space restore. | |
2356 | * @dev: PCI device to update. | |
2357 | */ | |
2358 | void pci_pme_restore(struct pci_dev *dev) | |
dc15e71e RW |
2359 | { |
2360 | u16 pmcsr; | |
2361 | ||
2362 | if (!dev->pme_support) | |
2363 | return; | |
2364 | ||
2365 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
2366 | if (dev->wakeup_prepared) { | |
2367 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
0ce3fcaf | 2368 | pmcsr &= ~PCI_PM_CTRL_PME_STATUS; |
dc15e71e RW |
2369 | } else { |
2370 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2371 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2372 | } | |
2373 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); | |
2374 | } | |
2375 | ||
2cef548a RW |
2376 | /** |
2377 | * pci_pme_active - enable or disable PCI device's PME# function | |
2378 | * @dev: PCI device to handle. | |
2379 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
2380 | * | |
2381 | * The caller must verify that the device is capable of generating PME# before | |
2382 | * calling this function with @enable equal to 'true'. | |
2383 | */ | |
2384 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
2385 | { | |
2386 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 2387 | |
6e965e0d HY |
2388 | /* |
2389 | * PCI (as opposed to PCIe) PME requires that the device have | |
2390 | * its PME# line hooked up correctly. Not all hardware vendors | |
2391 | * do this, so the PME never gets delivered and the device | |
2392 | * remains asleep. The easiest way around this is to | |
2393 | * periodically walk the list of suspended devices and check | |
2394 | * whether any have their PME flag set. The assumption is that | |
2395 | * we'll wake up often enough anyway that this won't be a huge | |
2396 | * hit, and the power savings from the devices will still be a | |
2397 | * win. | |
2398 | * | |
2399 | * Although PCIe uses in-band PME message instead of PME# line | |
2400 | * to report PME, PME does not work for some PCIe devices in | |
2401 | * reality. For example, there are devices that set their PME | |
2402 | * status bits, but don't really bother to send a PME message; | |
2403 | * there are PCI Express Root Ports that don't bother to | |
2404 | * trigger interrupts when they receive PME messages from the | |
2405 | * devices below. So PME poll is used for PCIe devices too. | |
2406 | */ | |
df17e62e | 2407 | |
379021d5 | 2408 | if (dev->pme_poll) { |
df17e62e MG |
2409 | struct pci_pme_device *pme_dev; |
2410 | if (enable) { | |
2411 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
2412 | GFP_KERNEL); | |
0394cb19 | 2413 | if (!pme_dev) { |
7506dc79 | 2414 | pci_warn(dev, "can't enable PME#\n"); |
0394cb19 BH |
2415 | return; |
2416 | } | |
df17e62e MG |
2417 | pme_dev->dev = dev; |
2418 | mutex_lock(&pci_pme_list_mutex); | |
2419 | list_add(&pme_dev->list, &pci_pme_list); | |
2420 | if (list_is_singular(&pci_pme_list)) | |
ea00353f LW |
2421 | queue_delayed_work(system_freezable_wq, |
2422 | &pci_pme_work, | |
2423 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2424 | mutex_unlock(&pci_pme_list_mutex); |
2425 | } else { | |
2426 | mutex_lock(&pci_pme_list_mutex); | |
2427 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
2428 | if (pme_dev->dev == dev) { | |
2429 | list_del(&pme_dev->list); | |
2430 | kfree(pme_dev); | |
2431 | break; | |
2432 | } | |
2433 | } | |
2434 | mutex_unlock(&pci_pme_list_mutex); | |
2435 | } | |
2436 | } | |
2437 | ||
7506dc79 | 2438 | pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 2439 | } |
b7fe9434 | 2440 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 2441 | |
1da177e4 | 2442 | /** |
cfcadfaa | 2443 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
2444 | * @dev: PCI device affected |
2445 | * @state: PCI state from which device will issue wakeup events | |
2446 | * @enable: True to enable event generation; false to disable | |
2447 | * | |
2448 | * This enables the device as a wakeup event source, or disables it. | |
2449 | * When such events involves platform-specific hooks, those hooks are | |
2450 | * called automatically by this routine. | |
2451 | * | |
2452 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 2453 | * always require such platform hooks. |
075c1771 | 2454 | * |
eb9d0fe4 RW |
2455 | * RETURN VALUE: |
2456 | * 0 is returned on success | |
2457 | * -EINVAL is returned if device is not supposed to wake up the system | |
2458 | * Error code depending on the platform is returned if both the platform and | |
2459 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 2460 | */ |
cfcadfaa | 2461 | static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1da177e4 | 2462 | { |
5bcc2fb4 | 2463 | int ret = 0; |
075c1771 | 2464 | |
baecc470 | 2465 | /* |
ac86e8ee MW |
2466 | * Bridges that are not power-manageable directly only signal |
2467 | * wakeup on behalf of subordinate devices which is set up | |
2468 | * elsewhere, so skip them. However, bridges that are | |
2469 | * power-manageable may signal wakeup for themselves (for example, | |
2470 | * on a hotplug event) and they need to be covered here. | |
baecc470 | 2471 | */ |
ac86e8ee | 2472 | if (!pci_power_manageable(dev)) |
baecc470 RW |
2473 | return 0; |
2474 | ||
0ce3fcaf RW |
2475 | /* Don't do the same thing twice in a row for one device. */ |
2476 | if (!!enable == !!dev->wakeup_prepared) | |
e80bb09d RW |
2477 | return 0; |
2478 | ||
eb9d0fe4 RW |
2479 | /* |
2480 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
2481 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
2482 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 2483 | */ |
1da177e4 | 2484 | |
5bcc2fb4 RW |
2485 | if (enable) { |
2486 | int error; | |
1da177e4 | 2487 | |
5bcc2fb4 RW |
2488 | if (pci_pme_capable(dev, state)) |
2489 | pci_pme_active(dev, true); | |
2490 | else | |
2491 | ret = 1; | |
0847684c | 2492 | error = platform_pci_set_wakeup(dev, true); |
5bcc2fb4 RW |
2493 | if (ret) |
2494 | ret = error; | |
e80bb09d RW |
2495 | if (!ret) |
2496 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 2497 | } else { |
0847684c | 2498 | platform_pci_set_wakeup(dev, false); |
5bcc2fb4 | 2499 | pci_pme_active(dev, false); |
e80bb09d | 2500 | dev->wakeup_prepared = false; |
5bcc2fb4 | 2501 | } |
1da177e4 | 2502 | |
5bcc2fb4 | 2503 | return ret; |
eb9d0fe4 | 2504 | } |
cfcadfaa RW |
2505 | |
2506 | /** | |
2507 | * pci_enable_wake - change wakeup settings for a PCI device | |
2508 | * @pci_dev: Target device | |
2509 | * @state: PCI state from which device will issue wakeup events | |
2510 | * @enable: Whether or not to enable event generation | |
2511 | * | |
2512 | * If @enable is set, check device_may_wakeup() for the device before calling | |
2513 | * __pci_enable_wake() for it. | |
2514 | */ | |
2515 | int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) | |
2516 | { | |
2517 | if (enable && !device_may_wakeup(&pci_dev->dev)) | |
2518 | return -EINVAL; | |
2519 | ||
2520 | return __pci_enable_wake(pci_dev, state, enable); | |
2521 | } | |
0847684c | 2522 | EXPORT_SYMBOL(pci_enable_wake); |
1da177e4 | 2523 | |
0235c4fc RW |
2524 | /** |
2525 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
2526 | * @dev: PCI device to prepare | |
2527 | * @enable: True to enable wake-up event generation; false to disable | |
2528 | * | |
2529 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
2530 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
2531 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
2532 | * ordering constraints. | |
2533 | * | |
cfcadfaa RW |
2534 | * This function only returns error code if the device is not allowed to wake |
2535 | * up the system from sleep or it is not capable of generating PME# from both | |
2536 | * D3_hot and D3_cold and the platform is unable to enable wake-up power for it. | |
0235c4fc RW |
2537 | */ |
2538 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
2539 | { | |
2540 | return pci_pme_capable(dev, PCI_D3cold) ? | |
2541 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
2542 | pci_enable_wake(dev, PCI_D3hot, enable); | |
2543 | } | |
b7fe9434 | 2544 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 2545 | |
404cc2d8 | 2546 | /** |
37139074 JB |
2547 | * pci_target_state - find an appropriate low power state for a given PCI dev |
2548 | * @dev: PCI device | |
666ff6f8 | 2549 | * @wakeup: Whether or not wakeup functionality will be enabled for the device. |
37139074 JB |
2550 | * |
2551 | * Use underlying platform code to find a supported low power state for @dev. | |
2552 | * If the platform can't manage @dev, return the deepest state from which it | |
2553 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 2554 | */ |
666ff6f8 | 2555 | static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) |
404cc2d8 RW |
2556 | { |
2557 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
2558 | |
2559 | if (platform_pci_power_manageable(dev)) { | |
2560 | /* | |
60ee031a | 2561 | * Call the platform to find the target state for the device. |
404cc2d8 RW |
2562 | */ |
2563 | pci_power_t state = platform_pci_choose_state(dev); | |
2564 | ||
2565 | switch (state) { | |
2566 | case PCI_POWER_ERROR: | |
2567 | case PCI_UNKNOWN: | |
2568 | break; | |
2569 | case PCI_D1: | |
2570 | case PCI_D2: | |
2571 | if (pci_no_d1d2(dev)) | |
2572 | break; | |
df561f66 | 2573 | fallthrough; |
404cc2d8 RW |
2574 | default: |
2575 | target_state = state; | |
404cc2d8 | 2576 | } |
4132a577 LW |
2577 | |
2578 | return target_state; | |
2579 | } | |
2580 | ||
2581 | if (!dev->pm_cap) | |
d2abdf62 | 2582 | target_state = PCI_D0; |
4132a577 LW |
2583 | |
2584 | /* | |
2585 | * If the device is in D3cold even though it's not power-manageable by | |
2586 | * the platform, it may have been powered down by non-standard means. | |
2587 | * Best to let it slumber. | |
2588 | */ | |
2589 | if (dev->current_state == PCI_D3cold) | |
2590 | target_state = PCI_D3cold; | |
2591 | ||
666ff6f8 | 2592 | if (wakeup) { |
404cc2d8 RW |
2593 | /* |
2594 | * Find the deepest state from which the device can generate | |
60ee031a | 2595 | * PME#. |
404cc2d8 | 2596 | */ |
337001b6 RW |
2597 | if (dev->pme_support) { |
2598 | while (target_state | |
2599 | && !(dev->pme_support & (1 << target_state))) | |
2600 | target_state--; | |
404cc2d8 RW |
2601 | } |
2602 | } | |
2603 | ||
e5899e1b RW |
2604 | return target_state; |
2605 | } | |
2606 | ||
2607 | /** | |
74356add BH |
2608 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition |
2609 | * into a sleep state | |
e5899e1b RW |
2610 | * @dev: Device to handle. |
2611 | * | |
2612 | * Choose the power state appropriate for the device depending on whether | |
2613 | * it can wake up the system and/or is power manageable by the platform | |
2614 | * (PCI_D3hot is the default) and put the device into that state. | |
2615 | */ | |
2616 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
2617 | { | |
666ff6f8 RW |
2618 | bool wakeup = device_may_wakeup(&dev->dev); |
2619 | pci_power_t target_state = pci_target_state(dev, wakeup); | |
e5899e1b RW |
2620 | int error; |
2621 | ||
2622 | if (target_state == PCI_POWER_ERROR) | |
2623 | return -EIO; | |
2624 | ||
a697f072 DB |
2625 | /* |
2626 | * There are systems (for example, Intel mobile chips since Coffee | |
2627 | * Lake) where the power drawn while suspended can be significantly | |
2628 | * reduced by disabling PTM on PCIe root ports as this allows the | |
2629 | * port to enter a lower-power PM state and the SoC to reach a | |
2630 | * lower-power idle state as a whole. | |
2631 | */ | |
2632 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) | |
2633 | pci_disable_ptm(dev); | |
2634 | ||
666ff6f8 | 2635 | pci_enable_wake(dev, target_state, wakeup); |
c157dfa3 | 2636 | |
404cc2d8 RW |
2637 | error = pci_set_power_state(dev, target_state); |
2638 | ||
a697f072 | 2639 | if (error) { |
404cc2d8 | 2640 | pci_enable_wake(dev, target_state, false); |
a697f072 DB |
2641 | pci_restore_ptm_state(dev); |
2642 | } | |
404cc2d8 RW |
2643 | |
2644 | return error; | |
2645 | } | |
b7fe9434 | 2646 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2647 | |
2648 | /** | |
74356add BH |
2649 | * pci_back_from_sleep - turn PCI device on during system-wide transition |
2650 | * into working state | |
404cc2d8 RW |
2651 | * @dev: Device to handle. |
2652 | * | |
88393161 | 2653 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2654 | */ |
2655 | int pci_back_from_sleep(struct pci_dev *dev) | |
2656 | { | |
2657 | pci_enable_wake(dev, PCI_D0, false); | |
2658 | return pci_set_power_state(dev, PCI_D0); | |
2659 | } | |
b7fe9434 | 2660 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2661 | |
6cbf8214 RW |
2662 | /** |
2663 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2664 | * @dev: PCI device being suspended. | |
2665 | * | |
2666 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2667 | * power state. | |
2668 | */ | |
2669 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2670 | { | |
666ff6f8 | 2671 | pci_power_t target_state; |
6cbf8214 RW |
2672 | int error; |
2673 | ||
666ff6f8 | 2674 | target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); |
6cbf8214 RW |
2675 | if (target_state == PCI_POWER_ERROR) |
2676 | return -EIO; | |
2677 | ||
448bd857 HY |
2678 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2679 | ||
a697f072 DB |
2680 | /* |
2681 | * There are systems (for example, Intel mobile chips since Coffee | |
2682 | * Lake) where the power drawn while suspended can be significantly | |
2683 | * reduced by disabling PTM on PCIe root ports as this allows the | |
2684 | * port to enter a lower-power PM state and the SoC to reach a | |
2685 | * lower-power idle state as a whole. | |
2686 | */ | |
2687 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) | |
2688 | pci_disable_ptm(dev); | |
2689 | ||
cfcadfaa | 2690 | __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); |
6cbf8214 RW |
2691 | |
2692 | error = pci_set_power_state(dev, target_state); | |
2693 | ||
448bd857 | 2694 | if (error) { |
0847684c | 2695 | pci_enable_wake(dev, target_state, false); |
a697f072 | 2696 | pci_restore_ptm_state(dev); |
448bd857 HY |
2697 | dev->runtime_d3cold = false; |
2698 | } | |
6cbf8214 RW |
2699 | |
2700 | return error; | |
2701 | } | |
2702 | ||
b67ea761 RW |
2703 | /** |
2704 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2705 | * @dev: Device to check. | |
2706 | * | |
f7625980 | 2707 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2708 | * (through the platform or using the native PCIe PME) or if the device supports |
2709 | * PME and one of its upstream bridges can generate wake-up events. | |
2710 | */ | |
2711 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2712 | { | |
2713 | struct pci_bus *bus = dev->bus; | |
2714 | ||
b67ea761 RW |
2715 | if (!dev->pme_support) |
2716 | return false; | |
2717 | ||
666ff6f8 | 2718 | /* PME-capable in principle, but not from the target power state */ |
8feaec33 | 2719 | if (!pci_pme_capable(dev, pci_target_state(dev, true))) |
6496ebd7 AS |
2720 | return false; |
2721 | ||
8feaec33 KHF |
2722 | if (device_can_wakeup(&dev->dev)) |
2723 | return true; | |
2724 | ||
b67ea761 RW |
2725 | while (bus->parent) { |
2726 | struct pci_dev *bridge = bus->self; | |
2727 | ||
de3ef1eb | 2728 | if (device_can_wakeup(&bridge->dev)) |
b67ea761 RW |
2729 | return true; |
2730 | ||
2731 | bus = bus->parent; | |
2732 | } | |
2733 | ||
2734 | /* We have reached the root bus. */ | |
2735 | if (bus->bridge) | |
de3ef1eb | 2736 | return device_can_wakeup(bus->bridge); |
b67ea761 RW |
2737 | |
2738 | return false; | |
2739 | } | |
2740 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2741 | ||
bac2a909 | 2742 | /** |
0c7376ad | 2743 | * pci_dev_need_resume - Check if it is necessary to resume the device. |
bac2a909 RW |
2744 | * @pci_dev: Device to check. |
2745 | * | |
0c7376ad | 2746 | * Return 'true' if the device is not runtime-suspended or it has to be |
bac2a909 | 2747 | * reconfigured due to wakeup settings difference between system and runtime |
0c7376ad RW |
2748 | * suspend, or the current power state of it is not suitable for the upcoming |
2749 | * (system-wide) transition. | |
bac2a909 | 2750 | */ |
0c7376ad | 2751 | bool pci_dev_need_resume(struct pci_dev *pci_dev) |
bac2a909 RW |
2752 | { |
2753 | struct device *dev = &pci_dev->dev; | |
234f223d RW |
2754 | pci_power_t target_state; |
2755 | ||
2756 | if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev)) | |
0c7376ad | 2757 | return true; |
bac2a909 | 2758 | |
0c7376ad | 2759 | target_state = pci_target_state(pci_dev, device_may_wakeup(dev)); |
234f223d RW |
2760 | |
2761 | /* | |
2762 | * If the earlier platform check has not triggered, D3cold is just power | |
2763 | * removal on top of D3hot, so no need to resume the device in that | |
2764 | * case. | |
2765 | */ | |
0c7376ad RW |
2766 | return target_state != pci_dev->current_state && |
2767 | target_state != PCI_D3cold && | |
2768 | pci_dev->current_state != PCI_D3hot; | |
2769 | } | |
2770 | ||
2771 | /** | |
2772 | * pci_dev_adjust_pme - Adjust PME setting for a suspended device. | |
2773 | * @pci_dev: Device to check. | |
2774 | * | |
2775 | * If the device is suspended and it is not configured for system wakeup, | |
2776 | * disable PME for it to prevent it from waking up the system unnecessarily. | |
2777 | * | |
2778 | * Note that if the device's power state is D3cold and the platform check in | |
2779 | * pci_dev_need_resume() has not triggered, the device's configuration need not | |
2780 | * be changed. | |
2781 | */ | |
2782 | void pci_dev_adjust_pme(struct pci_dev *pci_dev) | |
2783 | { | |
2784 | struct device *dev = &pci_dev->dev; | |
bac2a909 | 2785 | |
2cef548a RW |
2786 | spin_lock_irq(&dev->power.lock); |
2787 | ||
0c7376ad RW |
2788 | if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) && |
2789 | pci_dev->current_state < PCI_D3cold) | |
2cef548a RW |
2790 | __pci_pme_active(pci_dev, false); |
2791 | ||
2792 | spin_unlock_irq(&dev->power.lock); | |
2cef548a RW |
2793 | } |
2794 | ||
2795 | /** | |
2796 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2797 | * @pci_dev: Device to handle. | |
2798 | * | |
2799 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2800 | * it might have been disabled during the prepare phase of system suspend if | |
2801 | * the device was not configured for system wakeup. | |
2802 | */ | |
2803 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2804 | { | |
2805 | struct device *dev = &pci_dev->dev; | |
2806 | ||
2807 | if (!pci_dev_run_wake(pci_dev)) | |
2808 | return; | |
2809 | ||
2810 | spin_lock_irq(&dev->power.lock); | |
2811 | ||
2812 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2813 | __pci_pme_active(pci_dev, true); | |
2814 | ||
2815 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2816 | } |
2817 | ||
b3c32c4f HY |
2818 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2819 | { | |
2820 | struct device *dev = &pdev->dev; | |
2821 | struct device *parent = dev->parent; | |
2822 | ||
2823 | if (parent) | |
2824 | pm_runtime_get_sync(parent); | |
2825 | pm_runtime_get_noresume(dev); | |
2826 | /* | |
2827 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2828 | * so wait until suspending completes | |
2829 | */ | |
2830 | pm_runtime_barrier(dev); | |
2831 | /* | |
2832 | * Only need to resume devices in D3cold, because config | |
2833 | * registers are still accessible for devices suspended but | |
2834 | * not in D3cold. | |
2835 | */ | |
2836 | if (pdev->current_state == PCI_D3cold) | |
2837 | pm_runtime_resume(dev); | |
2838 | } | |
2839 | ||
2840 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2841 | { | |
2842 | struct device *dev = &pdev->dev; | |
2843 | struct device *parent = dev->parent; | |
2844 | ||
2845 | pm_runtime_put(dev); | |
2846 | if (parent) | |
2847 | pm_runtime_put_sync(parent); | |
2848 | } | |
2849 | ||
85b0cae8 MW |
2850 | static const struct dmi_system_id bridge_d3_blacklist[] = { |
2851 | #ifdef CONFIG_X86 | |
2852 | { | |
2853 | /* | |
2854 | * Gigabyte X299 root port is not marked as hotplug capable | |
2855 | * which allows Linux to power manage it. However, this | |
2856 | * confuses the BIOS SMI handler so don't power manage root | |
2857 | * ports on that system. | |
2858 | */ | |
2859 | .ident = "X299 DESIGNARE EX-CF", | |
2860 | .matches = { | |
2861 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
2862 | DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"), | |
2863 | }, | |
2864 | }, | |
2865 | #endif | |
2866 | { } | |
2867 | }; | |
2868 | ||
9d26d3a8 MW |
2869 | /** |
2870 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2871 | * @bridge: Bridge to check | |
2872 | * | |
2873 | * This function checks if it is possible to move the bridge to D3. | |
47a8e237 | 2874 | * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt. |
9d26d3a8 | 2875 | */ |
c6a63307 | 2876 | bool pci_bridge_d3_possible(struct pci_dev *bridge) |
9d26d3a8 | 2877 | { |
9d26d3a8 MW |
2878 | if (!pci_is_pcie(bridge)) |
2879 | return false; | |
2880 | ||
2881 | switch (pci_pcie_type(bridge)) { | |
2882 | case PCI_EXP_TYPE_ROOT_PORT: | |
2883 | case PCI_EXP_TYPE_UPSTREAM: | |
2884 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2885 | if (pci_bridge_d3_disable) | |
2886 | return false; | |
97a90aee LW |
2887 | |
2888 | /* | |
eb3b5bf1 | 2889 | * Hotplug ports handled by firmware in System Management Mode |
97a90aee | 2890 | * may not be put into D3 by the OS (Thunderbolt on non-Macs). |
97a90aee | 2891 | */ |
eb3b5bf1 | 2892 | if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) |
97a90aee LW |
2893 | return false; |
2894 | ||
9d26d3a8 MW |
2895 | if (pci_bridge_d3_force) |
2896 | return true; | |
2897 | ||
47a8e237 LW |
2898 | /* Even the oldest 2010 Thunderbolt controller supports D3. */ |
2899 | if (bridge->is_thunderbolt) | |
2900 | return true; | |
2901 | ||
26ad34d5 MW |
2902 | /* Platform might know better if the bridge supports D3 */ |
2903 | if (platform_pci_bridge_d3(bridge)) | |
2904 | return true; | |
2905 | ||
eb3b5bf1 LW |
2906 | /* |
2907 | * Hotplug ports handled natively by the OS were not validated | |
2908 | * by vendors for runtime D3 at least until 2018 because there | |
2909 | * was no OS support. | |
2910 | */ | |
2911 | if (bridge->is_hotplug_bridge) | |
2912 | return false; | |
2913 | ||
85b0cae8 MW |
2914 | if (dmi_check_system(bridge_d3_blacklist)) |
2915 | return false; | |
2916 | ||
9d26d3a8 MW |
2917 | /* |
2918 | * It should be safe to put PCIe ports from 2015 or newer | |
2919 | * to D3. | |
2920 | */ | |
ac95090a | 2921 | if (dmi_get_bios_year() >= 2015) |
9d26d3a8 | 2922 | return true; |
9d26d3a8 MW |
2923 | break; |
2924 | } | |
2925 | ||
2926 | return false; | |
2927 | } | |
2928 | ||
2929 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2930 | { | |
2931 | bool *d3cold_ok = data; | |
9d26d3a8 | 2932 | |
718a0609 LW |
2933 | if (/* The device needs to be allowed to go D3cold ... */ |
2934 | dev->no_d3cold || !dev->d3cold_allowed || | |
2935 | ||
2936 | /* ... and if it is wakeup capable to do so from D3cold. */ | |
2937 | (device_may_wakeup(&dev->dev) && | |
2938 | !pci_pme_capable(dev, PCI_D3cold)) || | |
2939 | ||
2940 | /* If it is a bridge it must be allowed to go to D3. */ | |
d98e0929 | 2941 | !pci_power_manageable(dev)) |
9d26d3a8 | 2942 | |
718a0609 | 2943 | *d3cold_ok = false; |
9d26d3a8 | 2944 | |
718a0609 | 2945 | return !*d3cold_ok; |
9d26d3a8 MW |
2946 | } |
2947 | ||
2948 | /* | |
2949 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
2950 | * @dev: PCI device which is changed | |
9d26d3a8 MW |
2951 | * |
2952 | * Update upstream bridge PM capabilities accordingly depending on if the | |
2953 | * device PM configuration was changed or the device is being removed. The | |
2954 | * change is also propagated upstream. | |
2955 | */ | |
1ed276a7 | 2956 | void pci_bridge_d3_update(struct pci_dev *dev) |
9d26d3a8 | 2957 | { |
1ed276a7 | 2958 | bool remove = !device_is_registered(&dev->dev); |
9d26d3a8 MW |
2959 | struct pci_dev *bridge; |
2960 | bool d3cold_ok = true; | |
2961 | ||
2962 | bridge = pci_upstream_bridge(dev); | |
2963 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
2964 | return; | |
2965 | ||
9d26d3a8 | 2966 | /* |
e8559b71 LW |
2967 | * If D3 is currently allowed for the bridge, removing one of its |
2968 | * children won't change that. | |
2969 | */ | |
2970 | if (remove && bridge->bridge_d3) | |
2971 | return; | |
2972 | ||
2973 | /* | |
2974 | * If D3 is currently allowed for the bridge and a child is added or | |
2975 | * changed, disallowance of D3 can only be caused by that child, so | |
2976 | * we only need to check that single device, not any of its siblings. | |
2977 | * | |
2978 | * If D3 is currently not allowed for the bridge, checking the device | |
2979 | * first may allow us to skip checking its siblings. | |
9d26d3a8 MW |
2980 | */ |
2981 | if (!remove) | |
2982 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
2983 | ||
e8559b71 LW |
2984 | /* |
2985 | * If D3 is currently not allowed for the bridge, this may be caused | |
2986 | * either by the device being changed/removed or any of its siblings, | |
2987 | * so we need to go through all children to find out if one of them | |
2988 | * continues to block D3. | |
2989 | */ | |
2990 | if (d3cold_ok && !bridge->bridge_d3) | |
9d26d3a8 MW |
2991 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, |
2992 | &d3cold_ok); | |
9d26d3a8 MW |
2993 | |
2994 | if (bridge->bridge_d3 != d3cold_ok) { | |
2995 | bridge->bridge_d3 = d3cold_ok; | |
2996 | /* Propagate change to upstream bridges */ | |
1ed276a7 | 2997 | pci_bridge_d3_update(bridge); |
9d26d3a8 | 2998 | } |
9d26d3a8 MW |
2999 | } |
3000 | ||
9d26d3a8 MW |
3001 | /** |
3002 | * pci_d3cold_enable - Enable D3cold for device | |
3003 | * @dev: PCI device to handle | |
3004 | * | |
3005 | * This function can be used in drivers to enable D3cold from the device | |
3006 | * they handle. It also updates upstream PCI bridge PM capabilities | |
3007 | * accordingly. | |
3008 | */ | |
3009 | void pci_d3cold_enable(struct pci_dev *dev) | |
3010 | { | |
3011 | if (dev->no_d3cold) { | |
3012 | dev->no_d3cold = false; | |
1ed276a7 | 3013 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
3014 | } |
3015 | } | |
3016 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
3017 | ||
3018 | /** | |
3019 | * pci_d3cold_disable - Disable D3cold for device | |
3020 | * @dev: PCI device to handle | |
3021 | * | |
3022 | * This function can be used in drivers to disable D3cold from the device | |
3023 | * they handle. It also updates upstream PCI bridge PM capabilities | |
3024 | * accordingly. | |
3025 | */ | |
3026 | void pci_d3cold_disable(struct pci_dev *dev) | |
3027 | { | |
3028 | if (!dev->no_d3cold) { | |
3029 | dev->no_d3cold = true; | |
1ed276a7 | 3030 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
3031 | } |
3032 | } | |
3033 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
3034 | ||
eb9d0fe4 RW |
3035 | /** |
3036 | * pci_pm_init - Initialize PM functions of given PCI device | |
3037 | * @dev: PCI device to handle. | |
3038 | */ | |
3039 | void pci_pm_init(struct pci_dev *dev) | |
3040 | { | |
3041 | int pm; | |
d6112f8d | 3042 | u16 status; |
eb9d0fe4 | 3043 | u16 pmc; |
1da177e4 | 3044 | |
bb910a70 | 3045 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
3046 | pm_runtime_set_active(&dev->dev); |
3047 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 3048 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 3049 | dev->wakeup_prepared = false; |
bb910a70 | 3050 | |
337001b6 | 3051 | dev->pm_cap = 0; |
ffaddbe8 | 3052 | dev->pme_support = 0; |
337001b6 | 3053 | |
eb9d0fe4 RW |
3054 | /* find PCI PM capability in list */ |
3055 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
3056 | if (!pm) | |
50246dd4 | 3057 | return; |
eb9d0fe4 RW |
3058 | /* Check device's ability to generate PME# */ |
3059 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 3060 | |
eb9d0fe4 | 3061 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
7506dc79 | 3062 | pci_err(dev, "unsupported PM cap regs version (%u)\n", |
eb9d0fe4 | 3063 | pmc & PCI_PM_CAP_VER_MASK); |
50246dd4 | 3064 | return; |
eb9d0fe4 RW |
3065 | } |
3066 | ||
337001b6 | 3067 | dev->pm_cap = pm; |
3789af9a | 3068 | dev->d3hot_delay = PCI_PM_D3HOT_WAIT; |
448bd857 | 3069 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 3070 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 3071 | dev->d3cold_allowed = true; |
337001b6 RW |
3072 | |
3073 | dev->d1_support = false; | |
3074 | dev->d2_support = false; | |
3075 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 3076 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 3077 | dev->d1_support = true; |
c9ed77ee | 3078 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 3079 | dev->d2_support = true; |
c9ed77ee BH |
3080 | |
3081 | if (dev->d1_support || dev->d2_support) | |
34c6b710 | 3082 | pci_info(dev, "supports%s%s\n", |
ec84f126 JB |
3083 | dev->d1_support ? " D1" : "", |
3084 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
3085 | } |
3086 | ||
3087 | pmc &= PCI_PM_CAP_PME_MASK; | |
3088 | if (pmc) { | |
34c6b710 | 3089 | pci_info(dev, "PME# supported from%s%s%s%s%s\n", |
c9ed77ee BH |
3090 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
3091 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
3092 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
3789af9a | 3093 | (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "", |
c9ed77ee | 3094 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); |
337001b6 | 3095 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 3096 | dev->pme_poll = true; |
eb9d0fe4 RW |
3097 | /* |
3098 | * Make device's PM flags reflect the wake-up capability, but | |
3099 | * let the user space enable it to wake up the system as needed. | |
3100 | */ | |
3101 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 3102 | /* Disable the PME# generation functionality */ |
337001b6 | 3103 | pci_pme_active(dev, false); |
eb9d0fe4 | 3104 | } |
d6112f8d FB |
3105 | |
3106 | pci_read_config_word(dev, PCI_STATUS, &status); | |
3107 | if (status & PCI_STATUS_IMM_READY) | |
3108 | dev->imm_ready = 1; | |
1da177e4 LT |
3109 | } |
3110 | ||
938174e5 SS |
3111 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
3112 | { | |
92efb1bd | 3113 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
3114 | |
3115 | switch (prop) { | |
3116 | case PCI_EA_P_MEM: | |
3117 | case PCI_EA_P_VF_MEM: | |
3118 | flags |= IORESOURCE_MEM; | |
3119 | break; | |
3120 | case PCI_EA_P_MEM_PREFETCH: | |
3121 | case PCI_EA_P_VF_MEM_PREFETCH: | |
3122 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
3123 | break; | |
3124 | case PCI_EA_P_IO: | |
3125 | flags |= IORESOURCE_IO; | |
3126 | break; | |
3127 | default: | |
3128 | return 0; | |
3129 | } | |
3130 | ||
3131 | return flags; | |
3132 | } | |
3133 | ||
3134 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
3135 | u8 prop) | |
3136 | { | |
3137 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
3138 | return &dev->resource[bei]; | |
11183991 DD |
3139 | #ifdef CONFIG_PCI_IOV |
3140 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
3141 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
3142 | return &dev->resource[PCI_IOV_RESOURCES + | |
3143 | bei - PCI_EA_BEI_VF_BAR0]; | |
3144 | #endif | |
938174e5 SS |
3145 | else if (bei == PCI_EA_BEI_ROM) |
3146 | return &dev->resource[PCI_ROM_RESOURCE]; | |
3147 | else | |
3148 | return NULL; | |
3149 | } | |
3150 | ||
3151 | /* Read an Enhanced Allocation (EA) entry */ | |
3152 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
3153 | { | |
3154 | struct resource *res; | |
3155 | int ent_size, ent_offset = offset; | |
3156 | resource_size_t start, end; | |
3157 | unsigned long flags; | |
26635112 | 3158 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
3159 | u8 prop; |
3160 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
3161 | ||
3162 | pci_read_config_dword(dev, ent_offset, &dw0); | |
3163 | ent_offset += 4; | |
3164 | ||
3165 | /* Entry size field indicates DWORDs after 1st */ | |
3166 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
3167 | ||
3168 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
3169 | goto out; | |
3170 | ||
26635112 BH |
3171 | bei = (dw0 & PCI_EA_BEI) >> 4; |
3172 | prop = (dw0 & PCI_EA_PP) >> 8; | |
3173 | ||
938174e5 SS |
3174 | /* |
3175 | * If the Property is in the reserved range, try the Secondary | |
3176 | * Property instead. | |
3177 | */ | |
3178 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 3179 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
3180 | if (prop > PCI_EA_P_BRIDGE_IO) |
3181 | goto out; | |
3182 | ||
26635112 | 3183 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 3184 | if (!res) { |
7506dc79 | 3185 | pci_err(dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
3186 | goto out; |
3187 | } | |
3188 | ||
3189 | flags = pci_ea_flags(dev, prop); | |
3190 | if (!flags) { | |
7506dc79 | 3191 | pci_err(dev, "Unsupported EA properties: %#x\n", prop); |
938174e5 SS |
3192 | goto out; |
3193 | } | |
3194 | ||
3195 | /* Read Base */ | |
3196 | pci_read_config_dword(dev, ent_offset, &base); | |
3197 | start = (base & PCI_EA_FIELD_MASK); | |
3198 | ent_offset += 4; | |
3199 | ||
3200 | /* Read MaxOffset */ | |
3201 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
3202 | ent_offset += 4; | |
3203 | ||
3204 | /* Read Base MSBs (if 64-bit entry) */ | |
3205 | if (base & PCI_EA_IS_64) { | |
3206 | u32 base_upper; | |
3207 | ||
3208 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
3209 | ent_offset += 4; | |
3210 | ||
3211 | flags |= IORESOURCE_MEM_64; | |
3212 | ||
3213 | /* entry starts above 32-bit boundary, can't use */ | |
3214 | if (!support_64 && base_upper) | |
3215 | goto out; | |
3216 | ||
3217 | if (support_64) | |
3218 | start |= ((u64)base_upper << 32); | |
3219 | } | |
3220 | ||
3221 | end = start + (max_offset | 0x03); | |
3222 | ||
3223 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
3224 | if (max_offset & PCI_EA_IS_64) { | |
3225 | u32 max_offset_upper; | |
3226 | ||
3227 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
3228 | ent_offset += 4; | |
3229 | ||
3230 | flags |= IORESOURCE_MEM_64; | |
3231 | ||
3232 | /* entry too big, can't use */ | |
3233 | if (!support_64 && max_offset_upper) | |
3234 | goto out; | |
3235 | ||
3236 | if (support_64) | |
3237 | end += ((u64)max_offset_upper << 32); | |
3238 | } | |
3239 | ||
3240 | if (end < start) { | |
7506dc79 | 3241 | pci_err(dev, "EA Entry crosses address boundary\n"); |
938174e5 SS |
3242 | goto out; |
3243 | } | |
3244 | ||
3245 | if (ent_size != ent_offset - offset) { | |
7506dc79 | 3246 | pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", |
938174e5 SS |
3247 | ent_size, ent_offset - offset); |
3248 | goto out; | |
3249 | } | |
3250 | ||
3251 | res->name = pci_name(dev); | |
3252 | res->start = start; | |
3253 | res->end = end; | |
3254 | res->flags = flags; | |
597becb4 BH |
3255 | |
3256 | if (bei <= PCI_EA_BEI_BAR5) | |
34c6b710 | 3257 | pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3258 | bei, res, prop); |
3259 | else if (bei == PCI_EA_BEI_ROM) | |
34c6b710 | 3260 | pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3261 | res, prop); |
3262 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
34c6b710 | 3263 | pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3264 | bei - PCI_EA_BEI_VF_BAR0, res, prop); |
3265 | else | |
34c6b710 | 3266 | pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3267 | bei, res, prop); |
3268 | ||
938174e5 SS |
3269 | out: |
3270 | return offset + ent_size; | |
3271 | } | |
3272 | ||
dcbb408a | 3273 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
3274 | void pci_ea_init(struct pci_dev *dev) |
3275 | { | |
3276 | int ea; | |
3277 | u8 num_ent; | |
3278 | int offset; | |
3279 | int i; | |
3280 | ||
3281 | /* find PCI EA capability in list */ | |
3282 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
3283 | if (!ea) | |
3284 | return; | |
3285 | ||
3286 | /* determine the number of entries */ | |
3287 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
3288 | &num_ent); | |
3289 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
3290 | ||
3291 | offset = ea + PCI_EA_FIRST_ENT; | |
3292 | ||
3293 | /* Skip DWORD 2 for type 1 functions */ | |
3294 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
3295 | offset += 4; | |
3296 | ||
3297 | /* parse each EA entry */ | |
3298 | for (i = 0; i < num_ent; ++i) | |
3299 | offset = pci_ea_read(dev, offset); | |
3300 | } | |
3301 | ||
34a4876e YL |
3302 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
3303 | struct pci_cap_saved_state *new_cap) | |
3304 | { | |
3305 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
3306 | } | |
3307 | ||
63f4898a | 3308 | /** |
fd0f7f73 | 3309 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
74356add | 3310 | * capability registers |
63f4898a RW |
3311 | * @dev: the PCI device |
3312 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 3313 | * @extended: Standard or Extended capability ID |
63f4898a RW |
3314 | * @size: requested size of the buffer |
3315 | */ | |
fd0f7f73 AW |
3316 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
3317 | bool extended, unsigned int size) | |
63f4898a RW |
3318 | { |
3319 | int pos; | |
3320 | struct pci_cap_saved_state *save_state; | |
3321 | ||
fd0f7f73 AW |
3322 | if (extended) |
3323 | pos = pci_find_ext_capability(dev, cap); | |
3324 | else | |
3325 | pos = pci_find_capability(dev, cap); | |
3326 | ||
0a1a9b49 | 3327 | if (!pos) |
63f4898a RW |
3328 | return 0; |
3329 | ||
3330 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
3331 | if (!save_state) | |
3332 | return -ENOMEM; | |
3333 | ||
24a4742f | 3334 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 3335 | save_state->cap.cap_extended = extended; |
24a4742f | 3336 | save_state->cap.size = size; |
63f4898a RW |
3337 | pci_add_saved_cap(dev, save_state); |
3338 | ||
3339 | return 0; | |
3340 | } | |
3341 | ||
fd0f7f73 AW |
3342 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
3343 | { | |
3344 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
3345 | } | |
3346 | ||
3347 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
3348 | { | |
3349 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
3350 | } | |
3351 | ||
63f4898a RW |
3352 | /** |
3353 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
3354 | * @dev: the PCI device | |
3355 | */ | |
3356 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
3357 | { | |
3358 | int error; | |
3359 | ||
89858517 YZ |
3360 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
3361 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a | 3362 | if (error) |
7506dc79 | 3363 | pci_err(dev, "unable to preallocate PCI Express save buffer\n"); |
63f4898a RW |
3364 | |
3365 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
3366 | if (error) | |
7506dc79 | 3367 | pci_err(dev, "unable to preallocate PCI-X save buffer\n"); |
425c1b22 | 3368 | |
dbbfadf2 BH |
3369 | error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR, |
3370 | 2 * sizeof(u16)); | |
3371 | if (error) | |
3372 | pci_err(dev, "unable to allocate suspend buffer for LTR\n"); | |
3373 | ||
425c1b22 | 3374 | pci_allocate_vc_save_buffers(dev); |
63f4898a RW |
3375 | } |
3376 | ||
f796841e YL |
3377 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
3378 | { | |
3379 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 3380 | struct hlist_node *n; |
f796841e | 3381 | |
b67bfe0d | 3382 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
3383 | kfree(tmp); |
3384 | } | |
3385 | ||
58c3a727 | 3386 | /** |
31ab2476 | 3387 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 3388 | * @dev: the PCI device |
b0cc6020 YW |
3389 | * |
3390 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
3391 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 3392 | */ |
31ab2476 | 3393 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 3394 | { |
58c3a727 | 3395 | u32 cap; |
8113587c | 3396 | struct pci_dev *bridge; |
58c3a727 | 3397 | |
6748dcc2 | 3398 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
3399 | return; |
3400 | ||
8113587c | 3401 | bridge = dev->bus->self; |
cb97ae34 | 3402 | if (!bridge) |
8113587c ZY |
3403 | return; |
3404 | ||
59875ae4 | 3405 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
3406 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
3407 | return; | |
3408 | ||
b0cc6020 YW |
3409 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
3410 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
3411 | PCI_EXP_DEVCTL2_ARI); | |
3412 | bridge->ari_enabled = 1; | |
3413 | } else { | |
3414 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
3415 | PCI_EXP_DEVCTL2_ARI); | |
3416 | bridge->ari_enabled = 0; | |
3417 | } | |
58c3a727 YZ |
3418 | } |
3419 | ||
0a67119f AW |
3420 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
3421 | { | |
3422 | int pos; | |
83db7e0b | 3423 | u16 cap, ctrl; |
0a67119f | 3424 | |
52fbf5bd | 3425 | pos = pdev->acs_cap; |
0a67119f AW |
3426 | if (!pos) |
3427 | return false; | |
3428 | ||
83db7e0b AW |
3429 | /* |
3430 | * Except for egress control, capabilities are either required | |
3431 | * or only required if controllable. Features missing from the | |
3432 | * capability field can therefore be assumed as hard-wired enabled. | |
3433 | */ | |
3434 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
3435 | acs_flags &= (cap | PCI_ACS_EC); | |
3436 | ||
0a67119f AW |
3437 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
3438 | return (ctrl & acs_flags) == acs_flags; | |
3439 | } | |
3440 | ||
ad805758 AW |
3441 | /** |
3442 | * pci_acs_enabled - test ACS against required flags for a given device | |
3443 | * @pdev: device to test | |
3444 | * @acs_flags: required PCI ACS flags | |
3445 | * | |
3446 | * Return true if the device supports the provided flags. Automatically | |
3447 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
3448 | * |
3449 | * Note that this interface checks the effective ACS capabilities of the | |
3450 | * device rather than the actual capabilities. For instance, most single | |
3451 | * function endpoints are not required to support ACS because they have no | |
3452 | * opportunity for peer-to-peer access. We therefore return 'true' | |
3453 | * regardless of whether the device exposes an ACS capability. This makes | |
3454 | * it much easier for callers of this function to ignore the actual type | |
3455 | * or topology of the device when testing ACS support. | |
ad805758 AW |
3456 | */ |
3457 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
3458 | { | |
0a67119f | 3459 | int ret; |
ad805758 AW |
3460 | |
3461 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
3462 | if (ret >= 0) | |
3463 | return ret > 0; | |
3464 | ||
0a67119f AW |
3465 | /* |
3466 | * Conventional PCI and PCI-X devices never support ACS, either | |
3467 | * effectively or actually. The shared bus topology implies that | |
3468 | * any device on the bus can receive or snoop DMA. | |
3469 | */ | |
ad805758 AW |
3470 | if (!pci_is_pcie(pdev)) |
3471 | return false; | |
3472 | ||
0a67119f AW |
3473 | switch (pci_pcie_type(pdev)) { |
3474 | /* | |
3475 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 3476 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
3477 | * handle them as we would a non-PCIe device. |
3478 | */ | |
3479 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
3480 | /* | |
3481 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
3482 | * applicable... must never implement an ACS Extended Capability...". | |
3483 | * This seems arbitrary, but we take a conservative interpretation | |
3484 | * of this statement. | |
3485 | */ | |
3486 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
3487 | case PCI_EXP_TYPE_RC_EC: | |
3488 | return false; | |
3489 | /* | |
3490 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
3491 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
3492 | * regardless of whether they are single- or multi-function devices. | |
3493 | */ | |
3494 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3495 | case PCI_EXP_TYPE_ROOT_PORT: | |
3496 | return pci_acs_flags_enabled(pdev, acs_flags); | |
3497 | /* | |
3498 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
3499 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 3500 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
3501 | * device. The footnote for section 6.12 indicates the specific |
3502 | * PCIe types included here. | |
3503 | */ | |
3504 | case PCI_EXP_TYPE_ENDPOINT: | |
3505 | case PCI_EXP_TYPE_UPSTREAM: | |
3506 | case PCI_EXP_TYPE_LEG_END: | |
3507 | case PCI_EXP_TYPE_RC_END: | |
3508 | if (!pdev->multifunction) | |
3509 | break; | |
3510 | ||
0a67119f | 3511 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
3512 | } |
3513 | ||
0a67119f | 3514 | /* |
f7625980 | 3515 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
3516 | * to single function devices with the exception of downstream ports. |
3517 | */ | |
ad805758 AW |
3518 | return true; |
3519 | } | |
3520 | ||
3521 | /** | |
2f0cd59c | 3522 | * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy |
ad805758 AW |
3523 | * @start: starting downstream device |
3524 | * @end: ending upstream device or NULL to search to the root bus | |
3525 | * @acs_flags: required flags | |
3526 | * | |
3527 | * Walk up a device tree from start to end testing PCI ACS support. If | |
3528 | * any step along the way does not support the required flags, return false. | |
3529 | */ | |
3530 | bool pci_acs_path_enabled(struct pci_dev *start, | |
3531 | struct pci_dev *end, u16 acs_flags) | |
3532 | { | |
3533 | struct pci_dev *pdev, *parent = start; | |
3534 | ||
3535 | do { | |
3536 | pdev = parent; | |
3537 | ||
3538 | if (!pci_acs_enabled(pdev, acs_flags)) | |
3539 | return false; | |
3540 | ||
3541 | if (pci_is_root_bus(pdev->bus)) | |
3542 | return (end == NULL); | |
3543 | ||
3544 | parent = pdev->bus->self; | |
3545 | } while (pdev != end); | |
3546 | ||
3547 | return true; | |
3548 | } | |
3549 | ||
52fbf5bd RJ |
3550 | /** |
3551 | * pci_acs_init - Initialize ACS if hardware supports it | |
3552 | * @dev: the PCI device | |
3553 | */ | |
3554 | void pci_acs_init(struct pci_dev *dev) | |
3555 | { | |
3556 | dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
3557 | ||
462b58fb RJ |
3558 | /* |
3559 | * Attempt to enable ACS regardless of capability because some Root | |
3560 | * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have | |
3561 | * the standard ACS capability but still support ACS via those | |
3562 | * quirks. | |
3563 | */ | |
3564 | pci_enable_acs(dev); | |
52fbf5bd RJ |
3565 | } |
3566 | ||
276b738d CK |
3567 | /** |
3568 | * pci_rebar_find_pos - find position of resize ctrl reg for BAR | |
3569 | * @pdev: PCI device | |
3570 | * @bar: BAR to find | |
3571 | * | |
3572 | * Helper to find the position of the ctrl register for a BAR. | |
3573 | * Returns -ENOTSUPP if resizable BARs are not supported at all. | |
3574 | * Returns -ENOENT if no ctrl register for the BAR could be found. | |
3575 | */ | |
3576 | static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) | |
3577 | { | |
3578 | unsigned int pos, nbars, i; | |
3579 | u32 ctrl; | |
3580 | ||
3581 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
3582 | if (!pos) | |
3583 | return -ENOTSUPP; | |
3584 | ||
3585 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3586 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
3587 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
3588 | ||
3589 | for (i = 0; i < nbars; i++, pos += 8) { | |
3590 | int bar_idx; | |
3591 | ||
3592 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3593 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
3594 | if (bar_idx == bar) | |
3595 | return pos; | |
3596 | } | |
3597 | ||
3598 | return -ENOENT; | |
3599 | } | |
3600 | ||
3601 | /** | |
3602 | * pci_rebar_get_possible_sizes - get possible sizes for BAR | |
3603 | * @pdev: PCI device | |
3604 | * @bar: BAR to query | |
3605 | * | |
3606 | * Get the possible sizes of a resizable BAR as bitmask defined in the spec | |
3607 | * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable. | |
3608 | */ | |
3609 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) | |
3610 | { | |
3611 | int pos; | |
3612 | u32 cap; | |
3613 | ||
3614 | pos = pci_rebar_find_pos(pdev, bar); | |
3615 | if (pos < 0) | |
3616 | return 0; | |
3617 | ||
3618 | pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); | |
907830b0 ND |
3619 | cap &= PCI_REBAR_CAP_SIZES; |
3620 | ||
3621 | /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ | |
3622 | if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && | |
3623 | bar == 0 && cap == 0x7000) | |
3624 | cap = 0x3f000; | |
3625 | ||
3626 | return cap >> 4; | |
276b738d | 3627 | } |
8fbdbb66 | 3628 | EXPORT_SYMBOL(pci_rebar_get_possible_sizes); |
276b738d CK |
3629 | |
3630 | /** | |
3631 | * pci_rebar_get_current_size - get the current size of a BAR | |
3632 | * @pdev: PCI device | |
3633 | * @bar: BAR to set size to | |
3634 | * | |
3635 | * Read the size of a BAR from the resizable BAR config. | |
3636 | * Returns size if found or negative error code. | |
3637 | */ | |
3638 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) | |
3639 | { | |
3640 | int pos; | |
3641 | u32 ctrl; | |
3642 | ||
3643 | pos = pci_rebar_find_pos(pdev, bar); | |
3644 | if (pos < 0) | |
3645 | return pos; | |
3646 | ||
3647 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
b1277a22 | 3648 | return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3649 | } |
3650 | ||
3651 | /** | |
3652 | * pci_rebar_set_size - set a new size for a BAR | |
3653 | * @pdev: PCI device | |
3654 | * @bar: BAR to set size to | |
3655 | * @size: new size as defined in the spec (0=1MB, 19=512GB) | |
3656 | * | |
3657 | * Set the new size of a BAR as defined in the spec. | |
3658 | * Returns zero if resizing was successful, error code otherwise. | |
3659 | */ | |
3660 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) | |
3661 | { | |
3662 | int pos; | |
3663 | u32 ctrl; | |
3664 | ||
3665 | pos = pci_rebar_find_pos(pdev, bar); | |
3666 | if (pos < 0) | |
3667 | return pos; | |
3668 | ||
3669 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3670 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
b1277a22 | 3671 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3672 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
3673 | return 0; | |
3674 | } | |
3675 | ||
430a2368 JC |
3676 | /** |
3677 | * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port | |
3678 | * @dev: the PCI device | |
3679 | * @cap_mask: mask of desired AtomicOp sizes, including one or more of: | |
3680 | * PCI_EXP_DEVCAP2_ATOMIC_COMP32 | |
3681 | * PCI_EXP_DEVCAP2_ATOMIC_COMP64 | |
3682 | * PCI_EXP_DEVCAP2_ATOMIC_COMP128 | |
3683 | * | |
3684 | * Return 0 if all upstream bridges support AtomicOp routing, egress | |
3685 | * blocking is disabled on all upstream ports, and the root port supports | |
3686 | * the requested completion capabilities (32-bit, 64-bit and/or 128-bit | |
3687 | * AtomicOp completion), or negative otherwise. | |
3688 | */ | |
3689 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) | |
3690 | { | |
3691 | struct pci_bus *bus = dev->bus; | |
3692 | struct pci_dev *bridge; | |
3693 | u32 cap, ctl2; | |
3694 | ||
3695 | if (!pci_is_pcie(dev)) | |
3696 | return -EINVAL; | |
3697 | ||
3698 | /* | |
3699 | * Per PCIe r4.0, sec 6.15, endpoints and root ports may be | |
3700 | * AtomicOp requesters. For now, we only support endpoints as | |
3701 | * requesters and root ports as completers. No endpoints as | |
3702 | * completers, and no peer-to-peer. | |
3703 | */ | |
3704 | ||
3705 | switch (pci_pcie_type(dev)) { | |
3706 | case PCI_EXP_TYPE_ENDPOINT: | |
3707 | case PCI_EXP_TYPE_LEG_END: | |
3708 | case PCI_EXP_TYPE_RC_END: | |
3709 | break; | |
3710 | default: | |
3711 | return -EINVAL; | |
3712 | } | |
3713 | ||
3714 | while (bus->parent) { | |
3715 | bridge = bus->self; | |
3716 | ||
3717 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); | |
3718 | ||
3719 | switch (pci_pcie_type(bridge)) { | |
3720 | /* Ensure switch ports support AtomicOp routing */ | |
3721 | case PCI_EXP_TYPE_UPSTREAM: | |
3722 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3723 | if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) | |
3724 | return -EINVAL; | |
3725 | break; | |
3726 | ||
3727 | /* Ensure root port supports all the sizes we care about */ | |
3728 | case PCI_EXP_TYPE_ROOT_PORT: | |
3729 | if ((cap & cap_mask) != cap_mask) | |
3730 | return -EINVAL; | |
3731 | break; | |
3732 | } | |
3733 | ||
3734 | /* Ensure upstream ports don't block AtomicOps on egress */ | |
ca784104 | 3735 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { |
430a2368 JC |
3736 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, |
3737 | &ctl2); | |
3738 | if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) | |
3739 | return -EINVAL; | |
3740 | } | |
3741 | ||
3742 | bus = bus->parent; | |
3743 | } | |
3744 | ||
3745 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, | |
3746 | PCI_EXP_DEVCTL2_ATOMIC_REQ); | |
3747 | return 0; | |
3748 | } | |
3749 | EXPORT_SYMBOL(pci_enable_atomic_ops_to_root); | |
3750 | ||
57c2cf71 BH |
3751 | /** |
3752 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
3753 | * @dev: the PCI device | |
bb5c2de2 | 3754 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
3755 | * |
3756 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
3757 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
3758 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
3759 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
3760 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 3761 | */ |
3df425f3 | 3762 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 3763 | { |
46b952a3 MW |
3764 | int slot; |
3765 | ||
3766 | if (pci_ari_enabled(dev->bus)) | |
3767 | slot = 0; | |
3768 | else | |
3769 | slot = PCI_SLOT(dev->devfn); | |
3770 | ||
3771 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
3772 | } |
3773 | ||
3c78bc61 | 3774 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
3775 | { |
3776 | u8 pin; | |
3777 | ||
514d207d | 3778 | pin = dev->pin; |
1da177e4 LT |
3779 | if (!pin) |
3780 | return -1; | |
878f2e50 | 3781 | |
8784fd4d | 3782 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 3783 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
3784 | dev = dev->bus->self; |
3785 | } | |
3786 | *bridge = dev; | |
3787 | return pin; | |
3788 | } | |
3789 | ||
68feac87 BH |
3790 | /** |
3791 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
3792 | * @dev: the PCI device | |
3793 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
3794 | * | |
3795 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
3796 | * bridges all the way up to a PCI root bus. | |
3797 | */ | |
3798 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
3799 | { | |
3800 | u8 pin = *pinp; | |
3801 | ||
1eb39487 | 3802 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
3803 | pin = pci_swizzle_interrupt_pin(dev, pin); |
3804 | dev = dev->bus->self; | |
3805 | } | |
3806 | *pinp = pin; | |
3807 | return PCI_SLOT(dev->devfn); | |
3808 | } | |
e6b29dea | 3809 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 3810 | |
1da177e4 | 3811 | /** |
74356add BH |
3812 | * pci_release_region - Release a PCI bar |
3813 | * @pdev: PCI device whose resources were previously reserved by | |
3814 | * pci_request_region() | |
3815 | * @bar: BAR to release | |
1da177e4 | 3816 | * |
74356add BH |
3817 | * Releases the PCI I/O and memory resources previously reserved by a |
3818 | * successful call to pci_request_region(). Call this function only | |
3819 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3820 | */ |
3821 | void pci_release_region(struct pci_dev *pdev, int bar) | |
3822 | { | |
9ac7849e TH |
3823 | struct pci_devres *dr; |
3824 | ||
1da177e4 LT |
3825 | if (pci_resource_len(pdev, bar) == 0) |
3826 | return; | |
3827 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
3828 | release_region(pci_resource_start(pdev, bar), | |
3829 | pci_resource_len(pdev, bar)); | |
3830 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
3831 | release_mem_region(pci_resource_start(pdev, bar), | |
3832 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
3833 | |
3834 | dr = find_pci_dr(pdev); | |
3835 | if (dr) | |
3836 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 3837 | } |
b7fe9434 | 3838 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
3839 | |
3840 | /** | |
74356add BH |
3841 | * __pci_request_region - Reserved PCI I/O and memory resource |
3842 | * @pdev: PCI device whose resources are to be reserved | |
3843 | * @bar: BAR to be reserved | |
3844 | * @res_name: Name to be associated with resource. | |
3845 | * @exclusive: whether the region access is exclusive or not | |
1da177e4 | 3846 | * |
74356add BH |
3847 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3848 | * being reserved by owner @res_name. Do not access any | |
3849 | * address inside the PCI regions unless this call returns | |
3850 | * successfully. | |
1da177e4 | 3851 | * |
74356add BH |
3852 | * If @exclusive is set, then the region is marked so that userspace |
3853 | * is explicitly not allowed to map the resource via /dev/mem or | |
3854 | * sysfs MMIO access. | |
f5ddcac4 | 3855 | * |
74356add BH |
3856 | * Returns 0 on success, or %EBUSY on error. A warning |
3857 | * message is also printed on failure. | |
1da177e4 | 3858 | */ |
3c78bc61 RD |
3859 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3860 | const char *res_name, int exclusive) | |
1da177e4 | 3861 | { |
9ac7849e TH |
3862 | struct pci_devres *dr; |
3863 | ||
1da177e4 LT |
3864 | if (pci_resource_len(pdev, bar) == 0) |
3865 | return 0; | |
f7625980 | 3866 | |
1da177e4 LT |
3867 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3868 | if (!request_region(pci_resource_start(pdev, bar), | |
3869 | pci_resource_len(pdev, bar), res_name)) | |
3870 | goto err_out; | |
3c78bc61 | 3871 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3872 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3873 | pci_resource_len(pdev, bar), res_name, | |
3874 | exclusive)) | |
1da177e4 LT |
3875 | goto err_out; |
3876 | } | |
9ac7849e TH |
3877 | |
3878 | dr = find_pci_dr(pdev); | |
3879 | if (dr) | |
3880 | dr->region_mask |= 1 << bar; | |
3881 | ||
1da177e4 LT |
3882 | return 0; |
3883 | ||
3884 | err_out: | |
7506dc79 | 3885 | pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3886 | &pdev->resource[bar]); |
1da177e4 LT |
3887 | return -EBUSY; |
3888 | } | |
3889 | ||
e8de1481 | 3890 | /** |
74356add BH |
3891 | * pci_request_region - Reserve PCI I/O and memory resource |
3892 | * @pdev: PCI device whose resources are to be reserved | |
3893 | * @bar: BAR to be reserved | |
3894 | * @res_name: Name to be associated with resource | |
e8de1481 | 3895 | * |
74356add BH |
3896 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3897 | * being reserved by owner @res_name. Do not access any | |
3898 | * address inside the PCI regions unless this call returns | |
3899 | * successfully. | |
e8de1481 | 3900 | * |
74356add BH |
3901 | * Returns 0 on success, or %EBUSY on error. A warning |
3902 | * message is also printed on failure. | |
e8de1481 AV |
3903 | */ |
3904 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3905 | { | |
3906 | return __pci_request_region(pdev, bar, res_name, 0); | |
3907 | } | |
b7fe9434 | 3908 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 | 3909 | |
c87deff7 HS |
3910 | /** |
3911 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3912 | * @pdev: PCI device whose resources were previously reserved | |
3913 | * @bars: Bitmask of BARs to be released | |
3914 | * | |
3915 | * Release selected PCI I/O and memory resources previously reserved. | |
3916 | * Call this function only after all use of the PCI regions has ceased. | |
3917 | */ | |
3918 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3919 | { | |
3920 | int i; | |
3921 | ||
c9c13ba4 | 3922 | for (i = 0; i < PCI_STD_NUM_BARS; i++) |
c87deff7 HS |
3923 | if (bars & (1 << i)) |
3924 | pci_release_region(pdev, i); | |
3925 | } | |
b7fe9434 | 3926 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 3927 | |
9738abed | 3928 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 3929 | const char *res_name, int excl) |
c87deff7 HS |
3930 | { |
3931 | int i; | |
3932 | ||
c9c13ba4 | 3933 | for (i = 0; i < PCI_STD_NUM_BARS; i++) |
c87deff7 | 3934 | if (bars & (1 << i)) |
e8de1481 | 3935 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
3936 | goto err_out; |
3937 | return 0; | |
3938 | ||
3939 | err_out: | |
3c78bc61 | 3940 | while (--i >= 0) |
c87deff7 HS |
3941 | if (bars & (1 << i)) |
3942 | pci_release_region(pdev, i); | |
3943 | ||
3944 | return -EBUSY; | |
3945 | } | |
1da177e4 | 3946 | |
e8de1481 AV |
3947 | |
3948 | /** | |
3949 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
3950 | * @pdev: PCI device whose resources are to be reserved | |
3951 | * @bars: Bitmask of BARs to be requested | |
3952 | * @res_name: Name to be associated with resource | |
3953 | */ | |
3954 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
3955 | const char *res_name) | |
3956 | { | |
3957 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
3958 | } | |
b7fe9434 | 3959 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 3960 | |
3c78bc61 RD |
3961 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
3962 | const char *res_name) | |
e8de1481 AV |
3963 | { |
3964 | return __pci_request_selected_regions(pdev, bars, res_name, | |
3965 | IORESOURCE_EXCLUSIVE); | |
3966 | } | |
b7fe9434 | 3967 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 3968 | |
1da177e4 | 3969 | /** |
74356add BH |
3970 | * pci_release_regions - Release reserved PCI I/O and memory resources |
3971 | * @pdev: PCI device whose resources were previously reserved by | |
3972 | * pci_request_regions() | |
1da177e4 | 3973 | * |
74356add BH |
3974 | * Releases all PCI I/O and memory resources previously reserved by a |
3975 | * successful call to pci_request_regions(). Call this function only | |
3976 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3977 | */ |
3978 | ||
3979 | void pci_release_regions(struct pci_dev *pdev) | |
3980 | { | |
c9c13ba4 | 3981 | pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); |
1da177e4 | 3982 | } |
b7fe9434 | 3983 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
3984 | |
3985 | /** | |
74356add BH |
3986 | * pci_request_regions - Reserve PCI I/O and memory resources |
3987 | * @pdev: PCI device whose resources are to be reserved | |
3988 | * @res_name: Name to be associated with resource. | |
1da177e4 | 3989 | * |
74356add BH |
3990 | * Mark all PCI regions associated with PCI device @pdev as |
3991 | * being reserved by owner @res_name. Do not access any | |
3992 | * address inside the PCI regions unless this call returns | |
3993 | * successfully. | |
1da177e4 | 3994 | * |
74356add BH |
3995 | * Returns 0 on success, or %EBUSY on error. A warning |
3996 | * message is also printed on failure. | |
1da177e4 | 3997 | */ |
3c990e92 | 3998 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 3999 | { |
c9c13ba4 DE |
4000 | return pci_request_selected_regions(pdev, |
4001 | ((1 << PCI_STD_NUM_BARS) - 1), res_name); | |
1da177e4 | 4002 | } |
b7fe9434 | 4003 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 4004 | |
e8de1481 | 4005 | /** |
74356add BH |
4006 | * pci_request_regions_exclusive - Reserve PCI I/O and memory resources |
4007 | * @pdev: PCI device whose resources are to be reserved | |
4008 | * @res_name: Name to be associated with resource. | |
e8de1481 | 4009 | * |
74356add BH |
4010 | * Mark all PCI regions associated with PCI device @pdev as being reserved |
4011 | * by owner @res_name. Do not access any address inside the PCI regions | |
4012 | * unless this call returns successfully. | |
e8de1481 | 4013 | * |
74356add BH |
4014 | * pci_request_regions_exclusive() will mark the region so that /dev/mem |
4015 | * and the sysfs MMIO access will not be allowed. | |
e8de1481 | 4016 | * |
74356add BH |
4017 | * Returns 0 on success, or %EBUSY on error. A warning message is also |
4018 | * printed on failure. | |
e8de1481 AV |
4019 | */ |
4020 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
4021 | { | |
4022 | return pci_request_selected_regions_exclusive(pdev, | |
c9c13ba4 | 4023 | ((1 << PCI_STD_NUM_BARS) - 1), res_name); |
e8de1481 | 4024 | } |
b7fe9434 | 4025 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 4026 | |
c5076cfe TN |
4027 | /* |
4028 | * Record the PCI IO range (expressed as CPU physical address + size). | |
74356add | 4029 | * Return a negative value if an error has occurred, zero otherwise |
c5076cfe | 4030 | */ |
fcfaab30 GP |
4031 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
4032 | resource_size_t size) | |
c5076cfe | 4033 | { |
5745392e | 4034 | int ret = 0; |
c5076cfe | 4035 | #ifdef PCI_IOBASE |
5745392e | 4036 | struct logic_pio_hwaddr *range; |
c5076cfe | 4037 | |
5745392e ZY |
4038 | if (!size || addr + size < addr) |
4039 | return -EINVAL; | |
c5076cfe | 4040 | |
c5076cfe | 4041 | range = kzalloc(sizeof(*range), GFP_ATOMIC); |
5745392e ZY |
4042 | if (!range) |
4043 | return -ENOMEM; | |
c5076cfe | 4044 | |
5745392e | 4045 | range->fwnode = fwnode; |
c5076cfe | 4046 | range->size = size; |
5745392e ZY |
4047 | range->hw_start = addr; |
4048 | range->flags = LOGIC_PIO_CPU_MMIO; | |
c5076cfe | 4049 | |
5745392e ZY |
4050 | ret = logic_pio_register_range(range); |
4051 | if (ret) | |
4052 | kfree(range); | |
f6bda644 GU |
4053 | |
4054 | /* Ignore duplicates due to deferred probing */ | |
4055 | if (ret == -EEXIST) | |
4056 | ret = 0; | |
c5076cfe TN |
4057 | #endif |
4058 | ||
5745392e | 4059 | return ret; |
c5076cfe TN |
4060 | } |
4061 | ||
4062 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
4063 | { | |
4064 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
4065 | ||
4066 | #ifdef PCI_IOBASE | |
5745392e | 4067 | if (pio >= MMIO_UPPER_LIMIT) |
c5076cfe TN |
4068 | return address; |
4069 | ||
5745392e | 4070 | address = logic_pio_to_hwaddr(pio); |
c5076cfe TN |
4071 | #endif |
4072 | ||
4073 | return address; | |
4074 | } | |
9cc74207 | 4075 | EXPORT_SYMBOL_GPL(pci_pio_to_address); |
c5076cfe TN |
4076 | |
4077 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
4078 | { | |
4079 | #ifdef PCI_IOBASE | |
5745392e | 4080 | return logic_pio_trans_cpuaddr(address); |
c5076cfe TN |
4081 | #else |
4082 | if (address > IO_SPACE_LIMIT) | |
4083 | return (unsigned long)-1; | |
4084 | ||
4085 | return (unsigned long) address; | |
4086 | #endif | |
4087 | } | |
4088 | ||
8b921acf | 4089 | /** |
74356add BH |
4090 | * pci_remap_iospace - Remap the memory mapped I/O space |
4091 | * @res: Resource describing the I/O space | |
4092 | * @phys_addr: physical address of range to be mapped | |
8b921acf | 4093 | * |
74356add BH |
4094 | * Remap the memory mapped I/O space described by the @res and the CPU |
4095 | * physical address @phys_addr into virtual address space. Only | |
4096 | * architectures that have memory mapped IO functions defined (and the | |
4097 | * PCI_IOBASE value defined) should call this function. | |
8b921acf | 4098 | */ |
7b309aef | 4099 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) |
8b921acf LD |
4100 | { |
4101 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
4102 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
4103 | ||
4104 | if (!(res->flags & IORESOURCE_IO)) | |
4105 | return -EINVAL; | |
4106 | ||
4107 | if (res->end > IO_SPACE_LIMIT) | |
4108 | return -EINVAL; | |
4109 | ||
4110 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
4111 | pgprot_device(PAGE_KERNEL)); | |
4112 | #else | |
74356add BH |
4113 | /* |
4114 | * This architecture does not have memory mapped I/O space, | |
4115 | * so this function should never be called | |
4116 | */ | |
8b921acf LD |
4117 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); |
4118 | return -ENODEV; | |
4119 | #endif | |
4120 | } | |
f90b0875 | 4121 | EXPORT_SYMBOL(pci_remap_iospace); |
8b921acf | 4122 | |
4d3f1384 | 4123 | /** |
74356add BH |
4124 | * pci_unmap_iospace - Unmap the memory mapped I/O space |
4125 | * @res: resource to be unmapped | |
4d3f1384 | 4126 | * |
74356add BH |
4127 | * Unmap the CPU virtual address @res from virtual address space. Only |
4128 | * architectures that have memory mapped IO functions defined (and the | |
4129 | * PCI_IOBASE value defined) should call this function. | |
4d3f1384 SK |
4130 | */ |
4131 | void pci_unmap_iospace(struct resource *res) | |
4132 | { | |
4133 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
4134 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
4135 | ||
4ad0ae8c | 4136 | vunmap_range(vaddr, vaddr + resource_size(res)); |
4d3f1384 SK |
4137 | #endif |
4138 | } | |
f90b0875 | 4139 | EXPORT_SYMBOL(pci_unmap_iospace); |
4d3f1384 | 4140 | |
a5fb9fb0 SS |
4141 | static void devm_pci_unmap_iospace(struct device *dev, void *ptr) |
4142 | { | |
4143 | struct resource **res = ptr; | |
4144 | ||
4145 | pci_unmap_iospace(*res); | |
4146 | } | |
4147 | ||
4148 | /** | |
4149 | * devm_pci_remap_iospace - Managed pci_remap_iospace() | |
4150 | * @dev: Generic device to remap IO address for | |
4151 | * @res: Resource describing the I/O space | |
4152 | * @phys_addr: physical address of range to be mapped | |
4153 | * | |
4154 | * Managed pci_remap_iospace(). Map is automatically unmapped on driver | |
4155 | * detach. | |
4156 | */ | |
4157 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, | |
4158 | phys_addr_t phys_addr) | |
4159 | { | |
4160 | const struct resource **ptr; | |
4161 | int error; | |
4162 | ||
4163 | ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL); | |
4164 | if (!ptr) | |
4165 | return -ENOMEM; | |
4166 | ||
4167 | error = pci_remap_iospace(res, phys_addr); | |
4168 | if (error) { | |
4169 | devres_free(ptr); | |
4170 | } else { | |
4171 | *ptr = res; | |
4172 | devres_add(dev, ptr); | |
4173 | } | |
4174 | ||
4175 | return error; | |
4176 | } | |
4177 | EXPORT_SYMBOL(devm_pci_remap_iospace); | |
4178 | ||
490cb6dd LP |
4179 | /** |
4180 | * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace() | |
4181 | * @dev: Generic device to remap IO address for | |
4182 | * @offset: Resource address to map | |
4183 | * @size: Size of map | |
4184 | * | |
4185 | * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver | |
4186 | * detach. | |
4187 | */ | |
4188 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, | |
4189 | resource_size_t offset, | |
4190 | resource_size_t size) | |
4191 | { | |
4192 | void __iomem **ptr, *addr; | |
4193 | ||
4194 | ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); | |
4195 | if (!ptr) | |
4196 | return NULL; | |
4197 | ||
4198 | addr = pci_remap_cfgspace(offset, size); | |
4199 | if (addr) { | |
4200 | *ptr = addr; | |
4201 | devres_add(dev, ptr); | |
4202 | } else | |
4203 | devres_free(ptr); | |
4204 | ||
4205 | return addr; | |
4206 | } | |
4207 | EXPORT_SYMBOL(devm_pci_remap_cfgspace); | |
4208 | ||
4209 | /** | |
4210 | * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource | |
4211 | * @dev: generic device to handle the resource for | |
4212 | * @res: configuration space resource to be handled | |
4213 | * | |
4214 | * Checks that a resource is a valid memory region, requests the memory | |
4215 | * region and ioremaps with pci_remap_cfgspace() API that ensures the | |
4216 | * proper PCI configuration space memory attributes are guaranteed. | |
4217 | * | |
4218 | * All operations are managed and will be undone on driver detach. | |
4219 | * | |
4220 | * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code | |
505fb746 | 4221 | * on failure. Usage example:: |
490cb6dd LP |
4222 | * |
4223 | * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
4224 | * base = devm_pci_remap_cfg_resource(&pdev->dev, res); | |
4225 | * if (IS_ERR(base)) | |
4226 | * return PTR_ERR(base); | |
4227 | */ | |
4228 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
4229 | struct resource *res) | |
4230 | { | |
4231 | resource_size_t size; | |
4232 | const char *name; | |
4233 | void __iomem *dest_ptr; | |
4234 | ||
4235 | BUG_ON(!dev); | |
4236 | ||
4237 | if (!res || resource_type(res) != IORESOURCE_MEM) { | |
4238 | dev_err(dev, "invalid resource\n"); | |
4239 | return IOMEM_ERR_PTR(-EINVAL); | |
4240 | } | |
4241 | ||
4242 | size = resource_size(res); | |
0af6e21e AL |
4243 | |
4244 | if (res->name) | |
4245 | name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev), | |
4246 | res->name); | |
4247 | else | |
4248 | name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); | |
4249 | if (!name) | |
4250 | return IOMEM_ERR_PTR(-ENOMEM); | |
490cb6dd LP |
4251 | |
4252 | if (!devm_request_mem_region(dev, res->start, size, name)) { | |
4253 | dev_err(dev, "can't request region for resource %pR\n", res); | |
4254 | return IOMEM_ERR_PTR(-EBUSY); | |
4255 | } | |
4256 | ||
4257 | dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); | |
4258 | if (!dest_ptr) { | |
4259 | dev_err(dev, "ioremap failed for resource %pR\n", res); | |
4260 | devm_release_mem_region(dev, res->start, size); | |
4261 | dest_ptr = IOMEM_ERR_PTR(-ENOMEM); | |
4262 | } | |
4263 | ||
4264 | return dest_ptr; | |
4265 | } | |
4266 | EXPORT_SYMBOL(devm_pci_remap_cfg_resource); | |
4267 | ||
6a479079 BH |
4268 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
4269 | { | |
4270 | u16 old_cmd, cmd; | |
4271 | ||
4272 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
4273 | if (enable) | |
4274 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
4275 | else | |
4276 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
4277 | if (cmd != old_cmd) { | |
7506dc79 | 4278 | pci_dbg(dev, "%s bus mastering\n", |
6a479079 BH |
4279 | enable ? "enabling" : "disabling"); |
4280 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4281 | } | |
4282 | dev->is_busmaster = enable; | |
4283 | } | |
e8de1481 | 4284 | |
2b6f2c35 MS |
4285 | /** |
4286 | * pcibios_setup - process "pci=" kernel boot arguments | |
4287 | * @str: string used to pass in "pci=" kernel boot arguments | |
4288 | * | |
4289 | * Process kernel boot arguments. This is the default implementation. | |
4290 | * Architecture specific implementations can override this as necessary. | |
4291 | */ | |
4292 | char * __weak __init pcibios_setup(char *str) | |
4293 | { | |
4294 | return str; | |
4295 | } | |
4296 | ||
96c55900 MS |
4297 | /** |
4298 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
4299 | * @dev: the PCI device to enable | |
4300 | * | |
4301 | * Enables PCI bus-mastering for the device. This is the default | |
4302 | * implementation. Architecture specific implementations can override | |
4303 | * this if necessary. | |
4304 | */ | |
4305 | void __weak pcibios_set_master(struct pci_dev *dev) | |
4306 | { | |
4307 | u8 lat; | |
4308 | ||
f676678f MS |
4309 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
4310 | if (pci_is_pcie(dev)) | |
4311 | return; | |
4312 | ||
96c55900 MS |
4313 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
4314 | if (lat < 16) | |
4315 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
4316 | else if (lat > pcibios_max_latency) | |
4317 | lat = pcibios_max_latency; | |
4318 | else | |
4319 | return; | |
a006482b | 4320 | |
96c55900 MS |
4321 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
4322 | } | |
4323 | ||
1da177e4 LT |
4324 | /** |
4325 | * pci_set_master - enables bus-mastering for device dev | |
4326 | * @dev: the PCI device to enable | |
4327 | * | |
4328 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
4329 | * to do the needed arch specific settings. | |
4330 | */ | |
6a479079 | 4331 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 4332 | { |
6a479079 | 4333 | __pci_set_master(dev, true); |
1da177e4 LT |
4334 | pcibios_set_master(dev); |
4335 | } | |
b7fe9434 | 4336 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 4337 | |
6a479079 BH |
4338 | /** |
4339 | * pci_clear_master - disables bus-mastering for device dev | |
4340 | * @dev: the PCI device to disable | |
4341 | */ | |
4342 | void pci_clear_master(struct pci_dev *dev) | |
4343 | { | |
4344 | __pci_set_master(dev, false); | |
4345 | } | |
b7fe9434 | 4346 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 4347 | |
1da177e4 | 4348 | /** |
edb2d97e MW |
4349 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
4350 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 4351 | * |
edb2d97e MW |
4352 | * Helper function for pci_set_mwi. |
4353 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
4354 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
4355 | * | |
4356 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4357 | */ | |
15ea76d4 | 4358 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
4359 | { |
4360 | u8 cacheline_size; | |
4361 | ||
4362 | if (!pci_cache_line_size) | |
15ea76d4 | 4363 | return -EINVAL; |
1da177e4 LT |
4364 | |
4365 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
4366 | equal to or multiple of the right value. */ | |
4367 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4368 | if (cacheline_size >= pci_cache_line_size && | |
4369 | (cacheline_size % pci_cache_line_size) == 0) | |
4370 | return 0; | |
4371 | ||
4372 | /* Write the correct value. */ | |
4373 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
4374 | /* Read it back. */ | |
4375 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4376 | if (cacheline_size == pci_cache_line_size) | |
4377 | return 0; | |
4378 | ||
0aec75a5 | 4379 | pci_dbg(dev, "cache line size of %d is not supported\n", |
227f0647 | 4380 | pci_cache_line_size << 2); |
1da177e4 LT |
4381 | |
4382 | return -EINVAL; | |
4383 | } | |
15ea76d4 TH |
4384 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
4385 | ||
1da177e4 LT |
4386 | /** |
4387 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
4388 | * @dev: the PCI device for which MWI is enabled | |
4389 | * | |
694625c0 | 4390 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
4391 | * |
4392 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4393 | */ | |
3c78bc61 | 4394 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 4395 | { |
b7fe9434 RD |
4396 | #ifdef PCI_DISABLE_MWI |
4397 | return 0; | |
4398 | #else | |
1da177e4 LT |
4399 | int rc; |
4400 | u16 cmd; | |
4401 | ||
edb2d97e | 4402 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
4403 | if (rc) |
4404 | return rc; | |
4405 | ||
4406 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 4407 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
7506dc79 | 4408 | pci_dbg(dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
4409 | cmd |= PCI_COMMAND_INVALIDATE; |
4410 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4411 | } | |
1da177e4 | 4412 | return 0; |
b7fe9434 | 4413 | #endif |
1da177e4 | 4414 | } |
b7fe9434 | 4415 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 4416 | |
fc0f9f4d HK |
4417 | /** |
4418 | * pcim_set_mwi - a device-managed pci_set_mwi() | |
4419 | * @dev: the PCI device for which MWI is enabled | |
4420 | * | |
4421 | * Managed pci_set_mwi(). | |
4422 | * | |
4423 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4424 | */ | |
4425 | int pcim_set_mwi(struct pci_dev *dev) | |
4426 | { | |
4427 | struct pci_devres *dr; | |
4428 | ||
4429 | dr = find_pci_dr(dev); | |
4430 | if (!dr) | |
4431 | return -ENOMEM; | |
4432 | ||
4433 | dr->mwi = 1; | |
4434 | return pci_set_mwi(dev); | |
4435 | } | |
4436 | EXPORT_SYMBOL(pcim_set_mwi); | |
4437 | ||
694625c0 RD |
4438 | /** |
4439 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
4440 | * @dev: the PCI device for which MWI is enabled | |
4441 | * | |
4442 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
4443 | * Callers are not required to check the return value. | |
4444 | * | |
4445 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4446 | */ | |
4447 | int pci_try_set_mwi(struct pci_dev *dev) | |
4448 | { | |
b7fe9434 RD |
4449 | #ifdef PCI_DISABLE_MWI |
4450 | return 0; | |
4451 | #else | |
4452 | return pci_set_mwi(dev); | |
4453 | #endif | |
694625c0 | 4454 | } |
b7fe9434 | 4455 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 4456 | |
1da177e4 LT |
4457 | /** |
4458 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
4459 | * @dev: the PCI device to disable | |
4460 | * | |
4461 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
4462 | */ | |
3c78bc61 | 4463 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 4464 | { |
b7fe9434 | 4465 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
4466 | u16 cmd; |
4467 | ||
4468 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4469 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
4470 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
4471 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4472 | } | |
b7fe9434 | 4473 | #endif |
1da177e4 | 4474 | } |
b7fe9434 | 4475 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 4476 | |
1fd3dde5 BH |
4477 | /** |
4478 | * pci_disable_parity - disable parity checking for device | |
4479 | * @dev: the PCI device to operate on | |
4480 | * | |
4481 | * Disable parity checking for device @dev | |
4482 | */ | |
4483 | void pci_disable_parity(struct pci_dev *dev) | |
4484 | { | |
4485 | u16 cmd; | |
4486 | ||
4487 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4488 | if (cmd & PCI_COMMAND_PARITY) { | |
4489 | cmd &= ~PCI_COMMAND_PARITY; | |
4490 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4491 | } | |
4492 | } | |
4493 | ||
a04ce0ff BR |
4494 | /** |
4495 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
4496 | * @pdev: the PCI device to operate on |
4497 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff | 4498 | * |
74356add | 4499 | * Enables/disables PCI INTx for device @pdev |
a04ce0ff | 4500 | */ |
3c78bc61 | 4501 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
4502 | { |
4503 | u16 pci_command, new; | |
4504 | ||
4505 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
4506 | ||
3c78bc61 | 4507 | if (enable) |
a04ce0ff | 4508 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 4509 | else |
a04ce0ff | 4510 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
4511 | |
4512 | if (new != pci_command) { | |
9ac7849e TH |
4513 | struct pci_devres *dr; |
4514 | ||
2fd9d74b | 4515 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
4516 | |
4517 | dr = find_pci_dr(pdev); | |
4518 | if (dr && !dr->restore_intx) { | |
4519 | dr->restore_intx = 1; | |
4520 | dr->orig_intx = !enable; | |
4521 | } | |
a04ce0ff BR |
4522 | } |
4523 | } | |
b7fe9434 | 4524 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 4525 | |
a2e27787 JK |
4526 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) |
4527 | { | |
4528 | struct pci_bus *bus = dev->bus; | |
4529 | bool mask_updated = true; | |
4530 | u32 cmd_status_dword; | |
4531 | u16 origcmd, newcmd; | |
4532 | unsigned long flags; | |
4533 | bool irq_pending; | |
4534 | ||
4535 | /* | |
4536 | * We do a single dword read to retrieve both command and status. | |
4537 | * Document assumptions that make this possible. | |
4538 | */ | |
4539 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
4540 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
4541 | ||
4542 | raw_spin_lock_irqsave(&pci_lock, flags); | |
4543 | ||
4544 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
4545 | ||
4546 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
4547 | ||
4548 | /* | |
4549 | * Check interrupt status register to see whether our device | |
4550 | * triggered the interrupt (when masking) or the next IRQ is | |
4551 | * already pending (when unmasking). | |
4552 | */ | |
4553 | if (mask != irq_pending) { | |
4554 | mask_updated = false; | |
4555 | goto done; | |
4556 | } | |
4557 | ||
4558 | origcmd = cmd_status_dword; | |
4559 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
4560 | if (mask) | |
4561 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
4562 | if (newcmd != origcmd) | |
4563 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
4564 | ||
4565 | done: | |
4566 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
4567 | ||
4568 | return mask_updated; | |
4569 | } | |
4570 | ||
4571 | /** | |
4572 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 4573 | * @dev: the PCI device to operate on |
a2e27787 | 4574 | * |
74356add BH |
4575 | * Check if the device dev has its INTx line asserted, mask it and return |
4576 | * true in that case. False is returned if no interrupt was pending. | |
a2e27787 JK |
4577 | */ |
4578 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
4579 | { | |
4580 | return pci_check_and_set_intx_mask(dev, true); | |
4581 | } | |
4582 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
4583 | ||
4584 | /** | |
ebd50b93 | 4585 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 4586 | * @dev: the PCI device to operate on |
a2e27787 | 4587 | * |
74356add BH |
4588 | * Check if the device dev has its INTx line asserted, unmask it if not and |
4589 | * return true. False is returned and the mask remains active if there was | |
4590 | * still an interrupt pending. | |
a2e27787 JK |
4591 | */ |
4592 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
4593 | { | |
4594 | return pci_check_and_set_intx_mask(dev, false); | |
4595 | } | |
4596 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
4597 | ||
3775a209 | 4598 | /** |
74356add | 4599 | * pci_wait_for_pending_transaction - wait for pending transaction |
3775a209 CL |
4600 | * @dev: the PCI device to operate on |
4601 | * | |
4602 | * Return 0 if transaction is pending 1 otherwise. | |
4603 | */ | |
4604 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 4605 | { |
157e876f AW |
4606 | if (!pci_is_pcie(dev)) |
4607 | return 1; | |
8c1c699f | 4608 | |
d0b4cc4e GS |
4609 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
4610 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
4611 | } |
4612 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
4613 | ||
a60a2b73 CH |
4614 | /** |
4615 | * pcie_has_flr - check if a device supports function level resets | |
74356add | 4616 | * @dev: device to check |
a60a2b73 CH |
4617 | * |
4618 | * Returns true if the device advertises support for PCIe function level | |
4619 | * resets. | |
4620 | */ | |
2d2917f7 | 4621 | bool pcie_has_flr(struct pci_dev *dev) |
3775a209 CL |
4622 | { |
4623 | u32 cap; | |
4624 | ||
f65fd1aa | 4625 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
a60a2b73 | 4626 | return false; |
3775a209 | 4627 | |
a60a2b73 CH |
4628 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
4629 | return cap & PCI_EXP_DEVCAP_FLR; | |
4630 | } | |
2d2917f7 | 4631 | EXPORT_SYMBOL_GPL(pcie_has_flr); |
3775a209 | 4632 | |
a60a2b73 CH |
4633 | /** |
4634 | * pcie_flr - initiate a PCIe function level reset | |
74356add | 4635 | * @dev: device to reset |
a60a2b73 CH |
4636 | * |
4637 | * Initiate a function level reset on @dev. The caller should ensure the | |
4638 | * device supports FLR before calling this function, e.g. by using the | |
4639 | * pcie_has_flr() helper. | |
4640 | */ | |
91295d79 | 4641 | int pcie_flr(struct pci_dev *dev) |
a60a2b73 | 4642 | { |
3775a209 | 4643 | if (!pci_wait_for_pending_transaction(dev)) |
7506dc79 | 4644 | pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 4645 | |
59875ae4 | 4646 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
a2758b6b | 4647 | |
d6112f8d FB |
4648 | if (dev->imm_ready) |
4649 | return 0; | |
4650 | ||
a2758b6b SK |
4651 | /* |
4652 | * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within | |
4653 | * 100ms, but may silently discard requests while the FLR is in | |
4654 | * progress. Wait 100ms before trying to access the device. | |
4655 | */ | |
4656 | msleep(100); | |
4657 | ||
4658 | return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); | |
8dd7f803 | 4659 | } |
a60a2b73 | 4660 | EXPORT_SYMBOL_GPL(pcie_flr); |
d91cdc74 | 4661 | |
8c1c699f | 4662 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 4663 | { |
8c1c699f | 4664 | int pos; |
1ca88797 SY |
4665 | u8 cap; |
4666 | ||
8c1c699f YZ |
4667 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
4668 | if (!pos) | |
1ca88797 | 4669 | return -ENOTTY; |
8c1c699f | 4670 | |
f65fd1aa SN |
4671 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
4672 | return -ENOTTY; | |
4673 | ||
8c1c699f | 4674 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); |
1ca88797 SY |
4675 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
4676 | return -ENOTTY; | |
4677 | ||
4678 | if (probe) | |
4679 | return 0; | |
4680 | ||
d066c946 AW |
4681 | /* |
4682 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
f6b6aefe | 4683 | * is used, so we use the control offset rather than status and shift |
d066c946 AW |
4684 | * the test bit to match. |
4685 | */ | |
bb383e28 | 4686 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 4687 | PCI_AF_STATUS_TP << 8)) |
7506dc79 | 4688 | pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 4689 | |
8c1c699f | 4690 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
a2758b6b | 4691 | |
d6112f8d FB |
4692 | if (dev->imm_ready) |
4693 | return 0; | |
4694 | ||
a2758b6b SK |
4695 | /* |
4696 | * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, | |
4697 | * updated 27 July 2006; a device must complete an FLR within | |
4698 | * 100ms, but may silently discard requests while the FLR is in | |
4699 | * progress. Wait 100ms before trying to access the device. | |
4700 | */ | |
4701 | msleep(100); | |
4702 | ||
4703 | return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); | |
1ca88797 SY |
4704 | } |
4705 | ||
83d74e03 RW |
4706 | /** |
4707 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
4708 | * @dev: Device to reset. | |
4709 | * @probe: If set, only check if the device can be reset this way. | |
4710 | * | |
4711 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
4712 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
4713 | * PCI_D0. If that's the case and the device is not in a low-power state | |
4714 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
4715 | * | |
4716 | * NOTE: This causes the caller to sleep for twice the device power transition | |
4717 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
3789af9a | 4718 | * by default (i.e. unless the @dev's d3hot_delay field has a different value). |
83d74e03 RW |
4719 | * Moreover, only devices in D0 can be reset by this function. |
4720 | */ | |
f85876ba | 4721 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 4722 | { |
f85876ba YZ |
4723 | u16 csr; |
4724 | ||
51e53738 | 4725 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 4726 | return -ENOTTY; |
d91cdc74 | 4727 | |
f85876ba YZ |
4728 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
4729 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
4730 | return -ENOTTY; | |
d91cdc74 | 4731 | |
f85876ba YZ |
4732 | if (probe) |
4733 | return 0; | |
1ca88797 | 4734 | |
f85876ba YZ |
4735 | if (dev->current_state != PCI_D0) |
4736 | return -EINVAL; | |
4737 | ||
4738 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4739 | csr |= PCI_D3hot; | |
4740 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4741 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
4742 | |
4743 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4744 | csr |= PCI_D0; | |
4745 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4746 | pci_dev_d3_sleep(dev); |
f85876ba | 4747 | |
993cc6d1 | 4748 | return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); |
f85876ba | 4749 | } |
4827d638 | 4750 | |
9f5a70f1 | 4751 | /** |
4827d638 | 4752 | * pcie_wait_for_link_delay - Wait until link is active or inactive |
9f5a70f1 OP |
4753 | * @pdev: Bridge device |
4754 | * @active: waiting for active or inactive? | |
d08c30d7 | 4755 | * @delay: Delay to wait after link has become active (in ms) |
9f5a70f1 OP |
4756 | * |
4757 | * Use this to wait till link becomes active or inactive. | |
4758 | */ | |
4827d638 MW |
4759 | static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, |
4760 | int delay) | |
9f5a70f1 OP |
4761 | { |
4762 | int timeout = 1000; | |
4763 | bool ret; | |
4764 | u16 lnk_status; | |
4765 | ||
f0157160 KB |
4766 | /* |
4767 | * Some controllers might not implement link active reporting. In this | |
f044baaf | 4768 | * case, we wait for 1000 ms + any delay requested by the caller. |
f0157160 KB |
4769 | */ |
4770 | if (!pdev->link_active_reporting) { | |
f044baaf | 4771 | msleep(timeout + delay); |
f0157160 KB |
4772 | return true; |
4773 | } | |
4774 | ||
4775 | /* | |
4776 | * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, | |
4777 | * after which we should expect an link active if the reset was | |
4778 | * successful. If so, software must wait a minimum 100ms before sending | |
4779 | * configuration requests to devices downstream this port. | |
4780 | * | |
4781 | * If the link fails to activate, either the device was physically | |
4782 | * removed or the link is permanently failed. | |
4783 | */ | |
4784 | if (active) | |
4785 | msleep(20); | |
9f5a70f1 OP |
4786 | for (;;) { |
4787 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); | |
4788 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | |
4789 | if (ret == active) | |
f0157160 | 4790 | break; |
9f5a70f1 OP |
4791 | if (timeout <= 0) |
4792 | break; | |
4793 | msleep(10); | |
4794 | timeout -= 10; | |
4795 | } | |
d08c30d7 | 4796 | if (active && ret) |
4827d638 | 4797 | msleep(delay); |
8a614499 | 4798 | |
f0157160 | 4799 | return ret == active; |
9f5a70f1 | 4800 | } |
f85876ba | 4801 | |
4827d638 MW |
4802 | /** |
4803 | * pcie_wait_for_link - Wait until link is active or inactive | |
4804 | * @pdev: Bridge device | |
4805 | * @active: waiting for active or inactive? | |
4806 | * | |
4807 | * Use this to wait till link becomes active or inactive. | |
4808 | */ | |
4809 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active) | |
4810 | { | |
4811 | return pcie_wait_for_link_delay(pdev, active, 100); | |
4812 | } | |
4813 | ||
ad9001f2 MW |
4814 | /* |
4815 | * Find maximum D3cold delay required by all the devices on the bus. The | |
4816 | * spec says 100 ms, but firmware can lower it and we allow drivers to | |
4817 | * increase it as well. | |
4818 | * | |
4819 | * Called with @pci_bus_sem locked for reading. | |
4820 | */ | |
4821 | static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) | |
4822 | { | |
4823 | const struct pci_dev *pdev; | |
4824 | int min_delay = 100; | |
4825 | int max_delay = 0; | |
4826 | ||
4827 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
4828 | if (pdev->d3cold_delay < min_delay) | |
4829 | min_delay = pdev->d3cold_delay; | |
4830 | if (pdev->d3cold_delay > max_delay) | |
4831 | max_delay = pdev->d3cold_delay; | |
4832 | } | |
4833 | ||
4834 | return max(min_delay, max_delay); | |
4835 | } | |
4836 | ||
4837 | /** | |
4838 | * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible | |
4839 | * @dev: PCI bridge | |
4840 | * | |
4841 | * Handle necessary delays before access to the devices on the secondary | |
4842 | * side of the bridge are permitted after D3cold to D0 transition. | |
4843 | * | |
4844 | * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For | |
4845 | * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section | |
4846 | * 4.3.2. | |
4847 | */ | |
4848 | void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) | |
4849 | { | |
4850 | struct pci_dev *child; | |
4851 | int delay; | |
4852 | ||
4853 | if (pci_dev_is_disconnected(dev)) | |
4854 | return; | |
4855 | ||
4856 | if (!pci_is_bridge(dev) || !dev->bridge_d3) | |
4857 | return; | |
4858 | ||
4859 | down_read(&pci_bus_sem); | |
4860 | ||
4861 | /* | |
4862 | * We only deal with devices that are present currently on the bus. | |
4863 | * For any hot-added devices the access delay is handled in pciehp | |
4864 | * board_added(). In case of ACPI hotplug the firmware is expected | |
4865 | * to configure the devices before OS is notified. | |
4866 | */ | |
4867 | if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { | |
4868 | up_read(&pci_bus_sem); | |
4869 | return; | |
4870 | } | |
4871 | ||
4872 | /* Take d3cold_delay requirements into account */ | |
4873 | delay = pci_bus_max_d3cold_delay(dev->subordinate); | |
4874 | if (!delay) { | |
4875 | up_read(&pci_bus_sem); | |
4876 | return; | |
4877 | } | |
4878 | ||
4879 | child = list_first_entry(&dev->subordinate->devices, struct pci_dev, | |
4880 | bus_list); | |
4881 | up_read(&pci_bus_sem); | |
4882 | ||
4883 | /* | |
4884 | * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before | |
4885 | * accessing the device after reset (that is 1000 ms + 100 ms). In | |
4886 | * practice this should not be needed because we don't do power | |
4887 | * management for them (see pci_bridge_d3_possible()). | |
4888 | */ | |
4889 | if (!pci_is_pcie(dev)) { | |
4890 | pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay); | |
4891 | msleep(1000 + delay); | |
4892 | return; | |
4893 | } | |
4894 | ||
4895 | /* | |
4896 | * For PCIe downstream and root ports that do not support speeds | |
4897 | * greater than 5 GT/s need to wait minimum 100 ms. For higher | |
4898 | * speeds (gen3) we need to wait first for the data link layer to | |
4899 | * become active. | |
4900 | * | |
4901 | * However, 100 ms is the minimum and the PCIe spec says the | |
4902 | * software must allow at least 1s before it can determine that the | |
4903 | * device that did not respond is a broken device. There is | |
4904 | * evidence that 100 ms is not always enough, for example certain | |
4905 | * Titan Ridge xHCI controller does not always respond to | |
4906 | * configuration requests if we only wait for 100 ms (see | |
4907 | * https://bugzilla.kernel.org/show_bug.cgi?id=203885). | |
4908 | * | |
4909 | * Therefore we wait for 100 ms and check for the device presence. | |
4910 | * If it is still not present give it an additional 100 ms. | |
4911 | */ | |
4912 | if (!pcie_downstream_port(dev)) | |
4913 | return; | |
4914 | ||
d08c30d7 BH |
4915 | if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) { |
4916 | pci_dbg(dev, "waiting %d ms for downstream link\n", delay); | |
4917 | msleep(delay); | |
4918 | } else { | |
4919 | pci_dbg(dev, "waiting %d ms for downstream link, after activation\n", | |
4920 | delay); | |
4921 | if (!pcie_wait_for_link_delay(dev, true, delay)) { | |
ad9001f2 | 4922 | /* Did not train, no need to wait any further */ |
8a614499 | 4923 | pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n"); |
ad9001f2 MW |
4924 | return; |
4925 | } | |
4926 | } | |
4927 | ||
4928 | if (!pci_device_is_present(child)) { | |
4929 | pci_dbg(child, "waiting additional %d ms to become accessible\n", delay); | |
4930 | msleep(delay); | |
4931 | } | |
4932 | } | |
4933 | ||
9e33002f | 4934 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
4935 | { |
4936 | u16 ctrl; | |
64e8674f AW |
4937 | |
4938 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
4939 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
4940 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
df62ab5e | 4941 | |
de0c548c AW |
4942 | /* |
4943 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 4944 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
4945 | */ |
4946 | msleep(2); | |
64e8674f AW |
4947 | |
4948 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
4949 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
4950 | |
4951 | /* | |
4952 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
4953 | * Assuming a minimum 33MHz clock this results in a 1s | |
4954 | * delay before we can consider subordinate devices to | |
4955 | * be re-initialized. PCIe has some ways to shorten this, | |
4956 | * but we don't make use of them yet. | |
4957 | */ | |
4958 | ssleep(1); | |
64e8674f | 4959 | } |
d92a208d | 4960 | |
9e33002f GS |
4961 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
4962 | { | |
4963 | pci_reset_secondary_bus(dev); | |
4964 | } | |
4965 | ||
d92a208d | 4966 | /** |
381634ca | 4967 | * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge. |
d92a208d GS |
4968 | * @dev: Bridge device |
4969 | * | |
4970 | * Use the bridge control register to assert reset on the secondary bus. | |
4971 | * Devices on the secondary bus are left in power-on state. | |
4972 | */ | |
381634ca | 4973 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev) |
d92a208d GS |
4974 | { |
4975 | pcibios_reset_secondary_bus(dev); | |
01fd61c0 | 4976 | |
6b2f1351 | 4977 | return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); |
d92a208d | 4978 | } |
bfc45606 | 4979 | EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); |
64e8674f AW |
4980 | |
4981 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
4982 | { | |
c12ff1df YZ |
4983 | struct pci_dev *pdev; |
4984 | ||
f331a859 AW |
4985 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
4986 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
4987 | return -ENOTTY; |
4988 | ||
4989 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4990 | if (pdev != dev) | |
4991 | return -ENOTTY; | |
4992 | ||
4993 | if (probe) | |
4994 | return 0; | |
4995 | ||
381634ca | 4996 | return pci_bridge_secondary_bus_reset(dev->bus->self); |
c12ff1df YZ |
4997 | } |
4998 | ||
608c3881 AW |
4999 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
5000 | { | |
5001 | int rc = -ENOTTY; | |
5002 | ||
81c4b5bf | 5003 | if (!hotplug || !try_module_get(hotplug->owner)) |
608c3881 AW |
5004 | return rc; |
5005 | ||
5006 | if (hotplug->ops->reset_slot) | |
5007 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
5008 | ||
81c4b5bf | 5009 | module_put(hotplug->owner); |
608c3881 AW |
5010 | |
5011 | return rc; | |
5012 | } | |
5013 | ||
5014 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
5015 | { | |
10791141 | 5016 | if (dev->multifunction || dev->subordinate || !dev->slot || |
f331a859 | 5017 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) |
608c3881 AW |
5018 | return -ENOTTY; |
5019 | ||
608c3881 AW |
5020 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); |
5021 | } | |
5022 | ||
77cb985a AW |
5023 | static void pci_dev_lock(struct pci_dev *dev) |
5024 | { | |
5025 | pci_cfg_access_lock(dev); | |
5026 | /* block PM suspend, driver probe, etc. */ | |
5027 | device_lock(&dev->dev); | |
5028 | } | |
5029 | ||
61cf16d8 AW |
5030 | /* Return 1 on successful lock, 0 on contention */ |
5031 | static int pci_dev_trylock(struct pci_dev *dev) | |
5032 | { | |
5033 | if (pci_cfg_access_trylock(dev)) { | |
5034 | if (device_trylock(&dev->dev)) | |
5035 | return 1; | |
5036 | pci_cfg_access_unlock(dev); | |
5037 | } | |
5038 | ||
5039 | return 0; | |
5040 | } | |
5041 | ||
77cb985a AW |
5042 | static void pci_dev_unlock(struct pci_dev *dev) |
5043 | { | |
5044 | device_unlock(&dev->dev); | |
5045 | pci_cfg_access_unlock(dev); | |
5046 | } | |
5047 | ||
775755ed | 5048 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3ebe7f9f KB |
5049 | { |
5050 | const struct pci_error_handlers *err_handler = | |
5051 | dev->driver ? dev->driver->err_handler : NULL; | |
3ebe7f9f | 5052 | |
b014e96d | 5053 | /* |
775755ed | 5054 | * dev->driver->err_handler->reset_prepare() is protected against |
b014e96d CH |
5055 | * races with ->remove() by the device lock, which must be held by |
5056 | * the caller. | |
5057 | */ | |
775755ed CH |
5058 | if (err_handler && err_handler->reset_prepare) |
5059 | err_handler->reset_prepare(dev); | |
3ebe7f9f | 5060 | |
a6cbaade AW |
5061 | /* |
5062 | * Wake-up device prior to save. PM registers default to D0 after | |
5063 | * reset and a simple register restore doesn't reliably return | |
5064 | * to a non-D0 state anyway. | |
5065 | */ | |
5066 | pci_set_power_state(dev, PCI_D0); | |
5067 | ||
77cb985a AW |
5068 | pci_save_state(dev); |
5069 | /* | |
5070 | * Disable the device by clearing the Command register, except for | |
5071 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
5072 | * BARs, but also prevents the device from being Bus Master, preventing | |
5073 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
5074 | * compliant devices, INTx-disable prevents legacy interrupts. | |
5075 | */ | |
5076 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
5077 | } | |
5078 | ||
5079 | static void pci_dev_restore(struct pci_dev *dev) | |
5080 | { | |
775755ed CH |
5081 | const struct pci_error_handlers *err_handler = |
5082 | dev->driver ? dev->driver->err_handler : NULL; | |
977f857c | 5083 | |
77cb985a | 5084 | pci_restore_state(dev); |
77cb985a | 5085 | |
775755ed CH |
5086 | /* |
5087 | * dev->driver->err_handler->reset_done() is protected against | |
5088 | * races with ->remove() by the device lock, which must be held by | |
5089 | * the caller. | |
5090 | */ | |
5091 | if (err_handler && err_handler->reset_done) | |
5092 | err_handler->reset_done(dev); | |
d91cdc74 | 5093 | } |
3ebe7f9f | 5094 | |
6fbf9e7a KRW |
5095 | /** |
5096 | * __pci_reset_function_locked - reset a PCI device function while holding | |
5097 | * the @dev mutex lock. | |
5098 | * @dev: PCI device to reset | |
5099 | * | |
5100 | * Some devices allow an individual function to be reset without affecting | |
5101 | * other functions in the same device. The PCI device must be responsive | |
5102 | * to PCI config space in order to use this function. | |
5103 | * | |
5104 | * The device function is presumed to be unused and the caller is holding | |
5105 | * the device mutex lock when this function is called. | |
74356add | 5106 | * |
6fbf9e7a KRW |
5107 | * Resetting the device will make the contents of PCI configuration space |
5108 | * random, so any caller of this must be prepared to reinitialise the | |
5109 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
5110 | * etc. | |
5111 | * | |
5112 | * Returns 0 if the device function was successfully reset or negative if the | |
5113 | * device doesn't support resetting a single function. | |
5114 | */ | |
5115 | int __pci_reset_function_locked(struct pci_dev *dev) | |
5116 | { | |
52354b9d CH |
5117 | int rc; |
5118 | ||
5119 | might_sleep(); | |
5120 | ||
832c418a BH |
5121 | /* |
5122 | * A reset method returns -ENOTTY if it doesn't support this device | |
5123 | * and we should try the next method. | |
5124 | * | |
5125 | * If it returns 0 (success), we're finished. If it returns any | |
5126 | * other error, we're also finished: this indicates that further | |
5127 | * reset mechanisms might be broken on the device. | |
5128 | */ | |
52354b9d CH |
5129 | rc = pci_dev_specific_reset(dev, 0); |
5130 | if (rc != -ENOTTY) | |
5131 | return rc; | |
5132 | if (pcie_has_flr(dev)) { | |
91295d79 SK |
5133 | rc = pcie_flr(dev); |
5134 | if (rc != -ENOTTY) | |
5135 | return rc; | |
52354b9d CH |
5136 | } |
5137 | rc = pci_af_flr(dev, 0); | |
5138 | if (rc != -ENOTTY) | |
5139 | return rc; | |
5140 | rc = pci_pm_reset(dev, 0); | |
5141 | if (rc != -ENOTTY) | |
5142 | return rc; | |
5143 | rc = pci_dev_reset_slot_function(dev, 0); | |
5144 | if (rc != -ENOTTY) | |
5145 | return rc; | |
5146 | return pci_parent_bus_reset(dev, 0); | |
6fbf9e7a KRW |
5147 | } |
5148 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
5149 | ||
711d5779 MT |
5150 | /** |
5151 | * pci_probe_reset_function - check whether the device can be safely reset | |
5152 | * @dev: PCI device to reset | |
5153 | * | |
5154 | * Some devices allow an individual function to be reset without affecting | |
5155 | * other functions in the same device. The PCI device must be responsive | |
5156 | * to PCI config space in order to use this function. | |
5157 | * | |
5158 | * Returns 0 if the device function can be reset or negative if the | |
5159 | * device doesn't support resetting a single function. | |
5160 | */ | |
5161 | int pci_probe_reset_function(struct pci_dev *dev) | |
5162 | { | |
52354b9d CH |
5163 | int rc; |
5164 | ||
5165 | might_sleep(); | |
5166 | ||
5167 | rc = pci_dev_specific_reset(dev, 1); | |
5168 | if (rc != -ENOTTY) | |
5169 | return rc; | |
5170 | if (pcie_has_flr(dev)) | |
5171 | return 0; | |
5172 | rc = pci_af_flr(dev, 1); | |
5173 | if (rc != -ENOTTY) | |
5174 | return rc; | |
5175 | rc = pci_pm_reset(dev, 1); | |
5176 | if (rc != -ENOTTY) | |
5177 | return rc; | |
5178 | rc = pci_dev_reset_slot_function(dev, 1); | |
5179 | if (rc != -ENOTTY) | |
5180 | return rc; | |
5181 | ||
5182 | return pci_parent_bus_reset(dev, 1); | |
711d5779 MT |
5183 | } |
5184 | ||
8dd7f803 | 5185 | /** |
8c1c699f YZ |
5186 | * pci_reset_function - quiesce and reset a PCI device function |
5187 | * @dev: PCI device to reset | |
8dd7f803 SY |
5188 | * |
5189 | * Some devices allow an individual function to be reset without affecting | |
5190 | * other functions in the same device. The PCI device must be responsive | |
5191 | * to PCI config space in order to use this function. | |
5192 | * | |
5193 | * This function does not just reset the PCI portion of a device, but | |
5194 | * clears all the state associated with the device. This function differs | |
79e699b6 JS |
5195 | * from __pci_reset_function_locked() in that it saves and restores device state |
5196 | * over the reset and takes the PCI device lock. | |
8dd7f803 | 5197 | * |
8c1c699f | 5198 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
5199 | * device doesn't support resetting a single function. |
5200 | */ | |
5201 | int pci_reset_function(struct pci_dev *dev) | |
5202 | { | |
8c1c699f | 5203 | int rc; |
8dd7f803 | 5204 | |
204f4afa BH |
5205 | if (!dev->reset_fn) |
5206 | return -ENOTTY; | |
8dd7f803 | 5207 | |
b014e96d | 5208 | pci_dev_lock(dev); |
77cb985a | 5209 | pci_dev_save_and_disable(dev); |
8dd7f803 | 5210 | |
52354b9d | 5211 | rc = __pci_reset_function_locked(dev); |
8dd7f803 | 5212 | |
77cb985a | 5213 | pci_dev_restore(dev); |
b014e96d | 5214 | pci_dev_unlock(dev); |
8dd7f803 | 5215 | |
8c1c699f | 5216 | return rc; |
8dd7f803 SY |
5217 | } |
5218 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
5219 | ||
a477b9cd MZ |
5220 | /** |
5221 | * pci_reset_function_locked - quiesce and reset a PCI device function | |
5222 | * @dev: PCI device to reset | |
5223 | * | |
5224 | * Some devices allow an individual function to be reset without affecting | |
5225 | * other functions in the same device. The PCI device must be responsive | |
5226 | * to PCI config space in order to use this function. | |
5227 | * | |
5228 | * This function does not just reset the PCI portion of a device, but | |
5229 | * clears all the state associated with the device. This function differs | |
79e699b6 | 5230 | * from __pci_reset_function_locked() in that it saves and restores device state |
a477b9cd MZ |
5231 | * over the reset. It also differs from pci_reset_function() in that it |
5232 | * requires the PCI device lock to be held. | |
5233 | * | |
5234 | * Returns 0 if the device function was successfully reset or negative if the | |
5235 | * device doesn't support resetting a single function. | |
5236 | */ | |
5237 | int pci_reset_function_locked(struct pci_dev *dev) | |
5238 | { | |
5239 | int rc; | |
5240 | ||
204f4afa BH |
5241 | if (!dev->reset_fn) |
5242 | return -ENOTTY; | |
a477b9cd MZ |
5243 | |
5244 | pci_dev_save_and_disable(dev); | |
5245 | ||
5246 | rc = __pci_reset_function_locked(dev); | |
5247 | ||
5248 | pci_dev_restore(dev); | |
5249 | ||
5250 | return rc; | |
5251 | } | |
5252 | EXPORT_SYMBOL_GPL(pci_reset_function_locked); | |
5253 | ||
61cf16d8 AW |
5254 | /** |
5255 | * pci_try_reset_function - quiesce and reset a PCI device function | |
5256 | * @dev: PCI device to reset | |
5257 | * | |
5258 | * Same as above, except return -EAGAIN if unable to lock device. | |
5259 | */ | |
5260 | int pci_try_reset_function(struct pci_dev *dev) | |
5261 | { | |
5262 | int rc; | |
5263 | ||
204f4afa BH |
5264 | if (!dev->reset_fn) |
5265 | return -ENOTTY; | |
61cf16d8 | 5266 | |
b014e96d CH |
5267 | if (!pci_dev_trylock(dev)) |
5268 | return -EAGAIN; | |
61cf16d8 | 5269 | |
b014e96d | 5270 | pci_dev_save_and_disable(dev); |
52354b9d | 5271 | rc = __pci_reset_function_locked(dev); |
cb5e0d06 | 5272 | pci_dev_restore(dev); |
b014e96d | 5273 | pci_dev_unlock(dev); |
61cf16d8 | 5274 | |
61cf16d8 AW |
5275 | return rc; |
5276 | } | |
5277 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
5278 | ||
f331a859 AW |
5279 | /* Do any devices on or below this bus prevent a bus reset? */ |
5280 | static bool pci_bus_resetable(struct pci_bus *bus) | |
5281 | { | |
5282 | struct pci_dev *dev; | |
5283 | ||
35702778 DD |
5284 | |
5285 | if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5286 | return false; | |
5287 | ||
f331a859 AW |
5288 | list_for_each_entry(dev, &bus->devices, bus_list) { |
5289 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5290 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5291 | return false; | |
5292 | } | |
5293 | ||
5294 | return true; | |
5295 | } | |
5296 | ||
090a3c53 AW |
5297 | /* Lock devices from the top of the tree down */ |
5298 | static void pci_bus_lock(struct pci_bus *bus) | |
5299 | { | |
5300 | struct pci_dev *dev; | |
5301 | ||
5302 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5303 | pci_dev_lock(dev); | |
5304 | if (dev->subordinate) | |
5305 | pci_bus_lock(dev->subordinate); | |
5306 | } | |
5307 | } | |
5308 | ||
5309 | /* Unlock devices from the bottom of the tree up */ | |
5310 | static void pci_bus_unlock(struct pci_bus *bus) | |
5311 | { | |
5312 | struct pci_dev *dev; | |
5313 | ||
5314 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5315 | if (dev->subordinate) | |
5316 | pci_bus_unlock(dev->subordinate); | |
5317 | pci_dev_unlock(dev); | |
5318 | } | |
5319 | } | |
5320 | ||
61cf16d8 AW |
5321 | /* Return 1 on successful lock, 0 on contention */ |
5322 | static int pci_bus_trylock(struct pci_bus *bus) | |
5323 | { | |
5324 | struct pci_dev *dev; | |
5325 | ||
5326 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5327 | if (!pci_dev_trylock(dev)) | |
5328 | goto unlock; | |
5329 | if (dev->subordinate) { | |
5330 | if (!pci_bus_trylock(dev->subordinate)) { | |
5331 | pci_dev_unlock(dev); | |
5332 | goto unlock; | |
5333 | } | |
5334 | } | |
5335 | } | |
5336 | return 1; | |
5337 | ||
5338 | unlock: | |
5339 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
5340 | if (dev->subordinate) | |
5341 | pci_bus_unlock(dev->subordinate); | |
5342 | pci_dev_unlock(dev); | |
5343 | } | |
5344 | return 0; | |
5345 | } | |
5346 | ||
f331a859 AW |
5347 | /* Do any devices on or below this slot prevent a bus reset? */ |
5348 | static bool pci_slot_resetable(struct pci_slot *slot) | |
5349 | { | |
5350 | struct pci_dev *dev; | |
5351 | ||
33ba90aa JG |
5352 | if (slot->bus->self && |
5353 | (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5354 | return false; | |
5355 | ||
f331a859 AW |
5356 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { |
5357 | if (!dev->slot || dev->slot != slot) | |
5358 | continue; | |
5359 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5360 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5361 | return false; | |
5362 | } | |
5363 | ||
5364 | return true; | |
5365 | } | |
5366 | ||
090a3c53 AW |
5367 | /* Lock devices from the top of the tree down */ |
5368 | static void pci_slot_lock(struct pci_slot *slot) | |
5369 | { | |
5370 | struct pci_dev *dev; | |
5371 | ||
5372 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5373 | if (!dev->slot || dev->slot != slot) | |
5374 | continue; | |
5375 | pci_dev_lock(dev); | |
5376 | if (dev->subordinate) | |
5377 | pci_bus_lock(dev->subordinate); | |
5378 | } | |
5379 | } | |
5380 | ||
5381 | /* Unlock devices from the bottom of the tree up */ | |
5382 | static void pci_slot_unlock(struct pci_slot *slot) | |
5383 | { | |
5384 | struct pci_dev *dev; | |
5385 | ||
5386 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5387 | if (!dev->slot || dev->slot != slot) | |
5388 | continue; | |
5389 | if (dev->subordinate) | |
5390 | pci_bus_unlock(dev->subordinate); | |
5391 | pci_dev_unlock(dev); | |
5392 | } | |
5393 | } | |
5394 | ||
61cf16d8 AW |
5395 | /* Return 1 on successful lock, 0 on contention */ |
5396 | static int pci_slot_trylock(struct pci_slot *slot) | |
5397 | { | |
5398 | struct pci_dev *dev; | |
5399 | ||
5400 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5401 | if (!dev->slot || dev->slot != slot) | |
5402 | continue; | |
5403 | if (!pci_dev_trylock(dev)) | |
5404 | goto unlock; | |
5405 | if (dev->subordinate) { | |
5406 | if (!pci_bus_trylock(dev->subordinate)) { | |
5407 | pci_dev_unlock(dev); | |
5408 | goto unlock; | |
5409 | } | |
5410 | } | |
5411 | } | |
5412 | return 1; | |
5413 | ||
5414 | unlock: | |
5415 | list_for_each_entry_continue_reverse(dev, | |
5416 | &slot->bus->devices, bus_list) { | |
5417 | if (!dev->slot || dev->slot != slot) | |
5418 | continue; | |
5419 | if (dev->subordinate) | |
5420 | pci_bus_unlock(dev->subordinate); | |
5421 | pci_dev_unlock(dev); | |
5422 | } | |
5423 | return 0; | |
5424 | } | |
5425 | ||
ddefc033 AW |
5426 | /* |
5427 | * Save and disable devices from the top of the tree down while holding | |
5428 | * the @dev mutex lock for the entire tree. | |
5429 | */ | |
5430 | static void pci_bus_save_and_disable_locked(struct pci_bus *bus) | |
090a3c53 AW |
5431 | { |
5432 | struct pci_dev *dev; | |
5433 | ||
5434 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5435 | pci_dev_save_and_disable(dev); | |
5436 | if (dev->subordinate) | |
ddefc033 | 5437 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5438 | } |
5439 | } | |
5440 | ||
5441 | /* | |
ddefc033 AW |
5442 | * Restore devices from top of the tree down while holding @dev mutex lock |
5443 | * for the entire tree. Parent bridges need to be restored before we can | |
5444 | * get to subordinate devices. | |
090a3c53 | 5445 | */ |
ddefc033 | 5446 | static void pci_bus_restore_locked(struct pci_bus *bus) |
090a3c53 AW |
5447 | { |
5448 | struct pci_dev *dev; | |
5449 | ||
5450 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5451 | pci_dev_restore(dev); | |
5452 | if (dev->subordinate) | |
ddefc033 | 5453 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5454 | } |
5455 | } | |
5456 | ||
ddefc033 AW |
5457 | /* |
5458 | * Save and disable devices from the top of the tree down while holding | |
5459 | * the @dev mutex lock for the entire tree. | |
5460 | */ | |
5461 | static void pci_slot_save_and_disable_locked(struct pci_slot *slot) | |
090a3c53 AW |
5462 | { |
5463 | struct pci_dev *dev; | |
5464 | ||
5465 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5466 | if (!dev->slot || dev->slot != slot) | |
5467 | continue; | |
5468 | pci_dev_save_and_disable(dev); | |
5469 | if (dev->subordinate) | |
ddefc033 | 5470 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5471 | } |
5472 | } | |
5473 | ||
5474 | /* | |
ddefc033 AW |
5475 | * Restore devices from top of the tree down while holding @dev mutex lock |
5476 | * for the entire tree. Parent bridges need to be restored before we can | |
5477 | * get to subordinate devices. | |
090a3c53 | 5478 | */ |
ddefc033 | 5479 | static void pci_slot_restore_locked(struct pci_slot *slot) |
090a3c53 AW |
5480 | { |
5481 | struct pci_dev *dev; | |
5482 | ||
5483 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5484 | if (!dev->slot || dev->slot != slot) | |
5485 | continue; | |
5486 | pci_dev_restore(dev); | |
5487 | if (dev->subordinate) | |
ddefc033 | 5488 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5489 | } |
5490 | } | |
5491 | ||
5492 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
5493 | { | |
5494 | int rc; | |
5495 | ||
f331a859 | 5496 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
5497 | return -ENOTTY; |
5498 | ||
5499 | if (!probe) | |
5500 | pci_slot_lock(slot); | |
5501 | ||
5502 | might_sleep(); | |
5503 | ||
5504 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
5505 | ||
5506 | if (!probe) | |
5507 | pci_slot_unlock(slot); | |
5508 | ||
5509 | return rc; | |
5510 | } | |
5511 | ||
9a3d2b9b AW |
5512 | /** |
5513 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
5514 | * @slot: PCI slot to probe | |
5515 | * | |
5516 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
5517 | */ | |
5518 | int pci_probe_reset_slot(struct pci_slot *slot) | |
5519 | { | |
5520 | return pci_slot_reset(slot, 1); | |
5521 | } | |
5522 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
5523 | ||
090a3c53 | 5524 | /** |
c6a44ba9 | 5525 | * __pci_reset_slot - Try to reset a PCI slot |
090a3c53 AW |
5526 | * @slot: PCI slot to reset |
5527 | * | |
5528 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
5529 | * independent of other slots. For instance, some slots may support slot power | |
5530 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
5531 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
5532 | * Generally a slot reset should be attempted before a bus reset. All of the | |
5533 | * function of the slot and any subordinate buses behind the slot are reset | |
5534 | * through this function. PCI config space of all devices in the slot and | |
5535 | * behind the slot is saved before and restored after reset. | |
5536 | * | |
61cf16d8 AW |
5537 | * Same as above except return -EAGAIN if the slot cannot be locked |
5538 | */ | |
c6a44ba9 | 5539 | static int __pci_reset_slot(struct pci_slot *slot) |
61cf16d8 AW |
5540 | { |
5541 | int rc; | |
5542 | ||
5543 | rc = pci_slot_reset(slot, 1); | |
5544 | if (rc) | |
5545 | return rc; | |
5546 | ||
61cf16d8 | 5547 | if (pci_slot_trylock(slot)) { |
ddefc033 | 5548 | pci_slot_save_and_disable_locked(slot); |
61cf16d8 AW |
5549 | might_sleep(); |
5550 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
ddefc033 | 5551 | pci_slot_restore_locked(slot); |
61cf16d8 AW |
5552 | pci_slot_unlock(slot); |
5553 | } else | |
5554 | rc = -EAGAIN; | |
5555 | ||
61cf16d8 AW |
5556 | return rc; |
5557 | } | |
61cf16d8 | 5558 | |
090a3c53 AW |
5559 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
5560 | { | |
18426238 SK |
5561 | int ret; |
5562 | ||
f331a859 | 5563 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
5564 | return -ENOTTY; |
5565 | ||
5566 | if (probe) | |
5567 | return 0; | |
5568 | ||
5569 | pci_bus_lock(bus); | |
5570 | ||
5571 | might_sleep(); | |
5572 | ||
381634ca | 5573 | ret = pci_bridge_secondary_bus_reset(bus->self); |
090a3c53 AW |
5574 | |
5575 | pci_bus_unlock(bus); | |
5576 | ||
18426238 | 5577 | return ret; |
090a3c53 AW |
5578 | } |
5579 | ||
c4eed62a KB |
5580 | /** |
5581 | * pci_bus_error_reset - reset the bridge's subordinate bus | |
5582 | * @bridge: The parent device that connects to the bus to reset | |
5583 | * | |
5584 | * This function will first try to reset the slots on this bus if the method is | |
5585 | * available. If slot reset fails or is not available, this will fall back to a | |
5586 | * secondary bus reset. | |
5587 | */ | |
5588 | int pci_bus_error_reset(struct pci_dev *bridge) | |
5589 | { | |
5590 | struct pci_bus *bus = bridge->subordinate; | |
5591 | struct pci_slot *slot; | |
5592 | ||
5593 | if (!bus) | |
5594 | return -ENOTTY; | |
5595 | ||
5596 | mutex_lock(&pci_slot_mutex); | |
5597 | if (list_empty(&bus->slots)) | |
5598 | goto bus_reset; | |
5599 | ||
5600 | list_for_each_entry(slot, &bus->slots, list) | |
5601 | if (pci_probe_reset_slot(slot)) | |
5602 | goto bus_reset; | |
5603 | ||
5604 | list_for_each_entry(slot, &bus->slots, list) | |
5605 | if (pci_slot_reset(slot, 0)) | |
5606 | goto bus_reset; | |
5607 | ||
5608 | mutex_unlock(&pci_slot_mutex); | |
5609 | return 0; | |
5610 | bus_reset: | |
5611 | mutex_unlock(&pci_slot_mutex); | |
5612 | return pci_bus_reset(bridge->subordinate, 0); | |
5613 | } | |
5614 | ||
9a3d2b9b AW |
5615 | /** |
5616 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
5617 | * @bus: PCI bus to probe | |
5618 | * | |
5619 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
5620 | */ | |
5621 | int pci_probe_reset_bus(struct pci_bus *bus) | |
5622 | { | |
5623 | return pci_bus_reset(bus, 1); | |
5624 | } | |
5625 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
5626 | ||
090a3c53 | 5627 | /** |
c6a44ba9 | 5628 | * __pci_reset_bus - Try to reset a PCI bus |
090a3c53 AW |
5629 | * @bus: top level PCI bus to reset |
5630 | * | |
61cf16d8 | 5631 | * Same as above except return -EAGAIN if the bus cannot be locked |
090a3c53 | 5632 | */ |
c6a44ba9 | 5633 | static int __pci_reset_bus(struct pci_bus *bus) |
090a3c53 AW |
5634 | { |
5635 | int rc; | |
5636 | ||
5637 | rc = pci_bus_reset(bus, 1); | |
5638 | if (rc) | |
5639 | return rc; | |
5640 | ||
61cf16d8 | 5641 | if (pci_bus_trylock(bus)) { |
ddefc033 | 5642 | pci_bus_save_and_disable_locked(bus); |
61cf16d8 | 5643 | might_sleep(); |
381634ca | 5644 | rc = pci_bridge_secondary_bus_reset(bus->self); |
ddefc033 | 5645 | pci_bus_restore_locked(bus); |
61cf16d8 AW |
5646 | pci_bus_unlock(bus); |
5647 | } else | |
5648 | rc = -EAGAIN; | |
090a3c53 | 5649 | |
090a3c53 AW |
5650 | return rc; |
5651 | } | |
090a3c53 | 5652 | |
61cf16d8 | 5653 | /** |
c6a44ba9 | 5654 | * pci_reset_bus - Try to reset a PCI bus |
811c5cb3 | 5655 | * @pdev: top level PCI device to reset via slot/bus |
61cf16d8 AW |
5656 | * |
5657 | * Same as above except return -EAGAIN if the bus cannot be locked | |
5658 | */ | |
c6a44ba9 | 5659 | int pci_reset_bus(struct pci_dev *pdev) |
61cf16d8 | 5660 | { |
d8a52810 | 5661 | return (!pci_probe_reset_slot(pdev->slot)) ? |
c6a44ba9 | 5662 | __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); |
61cf16d8 | 5663 | } |
c6a44ba9 | 5664 | EXPORT_SYMBOL_GPL(pci_reset_bus); |
61cf16d8 | 5665 | |
d556ad4b PO |
5666 | /** |
5667 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
5668 | * @dev: PCI device to query | |
5669 | * | |
74356add BH |
5670 | * Returns mmrbc: maximum designed memory read count in bytes or |
5671 | * appropriate error value. | |
d556ad4b PO |
5672 | */ |
5673 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
5674 | { | |
7c9e2b1c | 5675 | int cap; |
d556ad4b PO |
5676 | u32 stat; |
5677 | ||
5678 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5679 | if (!cap) | |
5680 | return -EINVAL; | |
5681 | ||
7c9e2b1c | 5682 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
5683 | return -EINVAL; |
5684 | ||
25daeb55 | 5685 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
5686 | } |
5687 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
5688 | ||
5689 | /** | |
5690 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
5691 | * @dev: PCI device to query | |
5692 | * | |
74356add BH |
5693 | * Returns mmrbc: maximum memory read count in bytes or appropriate error |
5694 | * value. | |
d556ad4b PO |
5695 | */ |
5696 | int pcix_get_mmrbc(struct pci_dev *dev) | |
5697 | { | |
7c9e2b1c | 5698 | int cap; |
bdc2bda7 | 5699 | u16 cmd; |
d556ad4b PO |
5700 | |
5701 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5702 | if (!cap) | |
5703 | return -EINVAL; | |
5704 | ||
7c9e2b1c DN |
5705 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5706 | return -EINVAL; | |
d556ad4b | 5707 | |
7c9e2b1c | 5708 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
5709 | } |
5710 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
5711 | ||
5712 | /** | |
5713 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
5714 | * @dev: PCI device to query | |
5715 | * @mmrbc: maximum memory read count in bytes | |
5716 | * valid values are 512, 1024, 2048, 4096 | |
5717 | * | |
74356add | 5718 | * If possible sets maximum memory read byte count, some bridges have errata |
d556ad4b PO |
5719 | * that prevent this. |
5720 | */ | |
5721 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
5722 | { | |
7c9e2b1c | 5723 | int cap; |
bdc2bda7 DN |
5724 | u32 stat, v, o; |
5725 | u16 cmd; | |
d556ad4b | 5726 | |
229f5afd | 5727 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 5728 | return -EINVAL; |
d556ad4b PO |
5729 | |
5730 | v = ffs(mmrbc) - 10; | |
5731 | ||
5732 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5733 | if (!cap) | |
7c9e2b1c | 5734 | return -EINVAL; |
d556ad4b | 5735 | |
7c9e2b1c DN |
5736 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
5737 | return -EINVAL; | |
d556ad4b PO |
5738 | |
5739 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
5740 | return -E2BIG; | |
5741 | ||
7c9e2b1c DN |
5742 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5743 | return -EINVAL; | |
d556ad4b PO |
5744 | |
5745 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
5746 | if (o != v) { | |
809a3bf9 | 5747 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
5748 | return -EIO; |
5749 | ||
5750 | cmd &= ~PCI_X_CMD_MAX_READ; | |
5751 | cmd |= v << 2; | |
7c9e2b1c DN |
5752 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
5753 | return -EIO; | |
d556ad4b | 5754 | } |
7c9e2b1c | 5755 | return 0; |
d556ad4b PO |
5756 | } |
5757 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
5758 | ||
5759 | /** | |
5760 | * pcie_get_readrq - get PCI Express read request size | |
5761 | * @dev: PCI device to query | |
5762 | * | |
74356add | 5763 | * Returns maximum memory read request in bytes or appropriate error value. |
d556ad4b PO |
5764 | */ |
5765 | int pcie_get_readrq(struct pci_dev *dev) | |
5766 | { | |
d556ad4b PO |
5767 | u16 ctl; |
5768 | ||
59875ae4 | 5769 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 5770 | |
59875ae4 | 5771 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
5772 | } |
5773 | EXPORT_SYMBOL(pcie_get_readrq); | |
5774 | ||
5775 | /** | |
5776 | * pcie_set_readrq - set PCI Express maximum memory read request | |
5777 | * @dev: PCI device to query | |
42e61f4a | 5778 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
5779 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5780 | * | |
c9b378c7 | 5781 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
5782 | */ |
5783 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
5784 | { | |
59875ae4 | 5785 | u16 v; |
d20df83b | 5786 | int ret; |
d556ad4b | 5787 | |
229f5afd | 5788 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 5789 | return -EINVAL; |
d556ad4b | 5790 | |
a1c473aa | 5791 | /* |
74356add BH |
5792 | * If using the "performance" PCIe config, we clamp the read rq |
5793 | * size to the max packet size to keep the host bridge from | |
5794 | * generating requests larger than we can cope with. | |
a1c473aa BH |
5795 | */ |
5796 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
5797 | int mps = pcie_get_mps(dev); | |
5798 | ||
a1c473aa BH |
5799 | if (mps < rq) |
5800 | rq = mps; | |
5801 | } | |
5802 | ||
5803 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 5804 | |
d20df83b | 5805 | ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
59875ae4 | 5806 | PCI_EXP_DEVCTL_READRQ, v); |
d20df83b BOS |
5807 | |
5808 | return pcibios_err_to_errno(ret); | |
d556ad4b PO |
5809 | } |
5810 | EXPORT_SYMBOL(pcie_set_readrq); | |
5811 | ||
b03e7495 JM |
5812 | /** |
5813 | * pcie_get_mps - get PCI Express maximum payload size | |
5814 | * @dev: PCI device to query | |
5815 | * | |
5816 | * Returns maximum payload size in bytes | |
b03e7495 JM |
5817 | */ |
5818 | int pcie_get_mps(struct pci_dev *dev) | |
5819 | { | |
b03e7495 JM |
5820 | u16 ctl; |
5821 | ||
59875ae4 | 5822 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 5823 | |
59875ae4 | 5824 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 5825 | } |
f1c66c46 | 5826 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
5827 | |
5828 | /** | |
5829 | * pcie_set_mps - set PCI Express maximum payload size | |
5830 | * @dev: PCI device to query | |
47c08f31 | 5831 | * @mps: maximum payload size in bytes |
b03e7495 JM |
5832 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5833 | * | |
5834 | * If possible sets maximum payload size | |
5835 | */ | |
5836 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
5837 | { | |
59875ae4 | 5838 | u16 v; |
d20df83b | 5839 | int ret; |
b03e7495 JM |
5840 | |
5841 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 5842 | return -EINVAL; |
b03e7495 JM |
5843 | |
5844 | v = ffs(mps) - 8; | |
f7625980 | 5845 | if (v > dev->pcie_mpss) |
59875ae4 | 5846 | return -EINVAL; |
b03e7495 JM |
5847 | v <<= 5; |
5848 | ||
d20df83b | 5849 | ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
59875ae4 | 5850 | PCI_EXP_DEVCTL_PAYLOAD, v); |
d20df83b BOS |
5851 | |
5852 | return pcibios_err_to_errno(ret); | |
b03e7495 | 5853 | } |
f1c66c46 | 5854 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 5855 | |
6db79a88 TG |
5856 | /** |
5857 | * pcie_bandwidth_available - determine minimum link settings of a PCIe | |
5858 | * device and its bandwidth limitation | |
5859 | * @dev: PCI device to query | |
5860 | * @limiting_dev: storage for device causing the bandwidth limitation | |
5861 | * @speed: storage for speed of limiting device | |
5862 | * @width: storage for width of limiting device | |
5863 | * | |
5864 | * Walk up the PCI device chain and find the point where the minimum | |
5865 | * bandwidth is available. Return the bandwidth available there and (if | |
5866 | * limiting_dev, speed, and width pointers are supplied) information about | |
5867 | * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of | |
5868 | * raw bandwidth. | |
5869 | */ | |
5870 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, | |
5871 | enum pci_bus_speed *speed, | |
5872 | enum pcie_link_width *width) | |
5873 | { | |
5874 | u16 lnksta; | |
5875 | enum pci_bus_speed next_speed; | |
5876 | enum pcie_link_width next_width; | |
5877 | u32 bw, next_bw; | |
5878 | ||
5879 | if (speed) | |
5880 | *speed = PCI_SPEED_UNKNOWN; | |
5881 | if (width) | |
5882 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
5883 | ||
5884 | bw = 0; | |
5885 | ||
5886 | while (dev) { | |
5887 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
5888 | ||
5889 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
5890 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
5891 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
5892 | ||
5893 | next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); | |
5894 | ||
5895 | /* Check if current device limits the total bandwidth */ | |
5896 | if (!bw || next_bw <= bw) { | |
5897 | bw = next_bw; | |
5898 | ||
5899 | if (limiting_dev) | |
5900 | *limiting_dev = dev; | |
5901 | if (speed) | |
5902 | *speed = next_speed; | |
5903 | if (width) | |
5904 | *width = next_width; | |
5905 | } | |
5906 | ||
5907 | dev = pci_upstream_bridge(dev); | |
5908 | } | |
5909 | ||
5910 | return bw; | |
5911 | } | |
5912 | EXPORT_SYMBOL(pcie_bandwidth_available); | |
5913 | ||
6cf57be0 TG |
5914 | /** |
5915 | * pcie_get_speed_cap - query for the PCI device's link speed capability | |
5916 | * @dev: PCI device to query | |
5917 | * | |
5918 | * Query the PCI device speed capability. Return the maximum link speed | |
5919 | * supported by the device. | |
5920 | */ | |
5921 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) | |
5922 | { | |
5923 | u32 lnkcap2, lnkcap; | |
5924 | ||
5925 | /* | |
f1f90e25 MP |
5926 | * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The |
5927 | * implementation note there recommends using the Supported Link | |
5928 | * Speeds Vector in Link Capabilities 2 when supported. | |
5929 | * | |
5930 | * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software | |
5931 | * should use the Supported Link Speeds field in Link Capabilities, | |
5932 | * where only 2.5 GT/s and 5.0 GT/s speeds were defined. | |
6cf57be0 TG |
5933 | */ |
5934 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); | |
757bfaa2 YY |
5935 | |
5936 | /* PCIe r3.0-compliant */ | |
5937 | if (lnkcap2) | |
5938 | return PCIE_LNKCAP2_SLS2SPEED(lnkcap2); | |
6cf57be0 TG |
5939 | |
5940 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
f1f90e25 MP |
5941 | if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) |
5942 | return PCIE_SPEED_5_0GT; | |
5943 | else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) | |
5944 | return PCIE_SPEED_2_5GT; | |
6cf57be0 TG |
5945 | |
5946 | return PCI_SPEED_UNKNOWN; | |
5947 | } | |
576c7218 | 5948 | EXPORT_SYMBOL(pcie_get_speed_cap); |
6cf57be0 | 5949 | |
c70b65fb TG |
5950 | /** |
5951 | * pcie_get_width_cap - query for the PCI device's link width capability | |
5952 | * @dev: PCI device to query | |
5953 | * | |
5954 | * Query the PCI device width capability. Return the maximum link width | |
5955 | * supported by the device. | |
5956 | */ | |
5957 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) | |
5958 | { | |
5959 | u32 lnkcap; | |
5960 | ||
5961 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
5962 | if (lnkcap) | |
5963 | return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; | |
5964 | ||
5965 | return PCIE_LNK_WIDTH_UNKNOWN; | |
5966 | } | |
576c7218 | 5967 | EXPORT_SYMBOL(pcie_get_width_cap); |
c70b65fb | 5968 | |
b852f63a TG |
5969 | /** |
5970 | * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability | |
5971 | * @dev: PCI device | |
5972 | * @speed: storage for link speed | |
5973 | * @width: storage for link width | |
5974 | * | |
5975 | * Calculate a PCI device's link bandwidth by querying for its link speed | |
5976 | * and width, multiplying them, and applying encoding overhead. The result | |
5977 | * is in Mb/s, i.e., megabits/second of raw bandwidth. | |
5978 | */ | |
5979 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, | |
5980 | enum pcie_link_width *width) | |
5981 | { | |
5982 | *speed = pcie_get_speed_cap(dev); | |
5983 | *width = pcie_get_width_cap(dev); | |
5984 | ||
5985 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
5986 | return 0; | |
5987 | ||
5988 | return *width * PCIE_SPEED2MBS_ENC(*speed); | |
5989 | } | |
5990 | ||
9e506a7b | 5991 | /** |
2d1ce5ec | 5992 | * __pcie_print_link_status - Report the PCI device's link speed and width |
9e506a7b | 5993 | * @dev: PCI device to query |
2d1ce5ec | 5994 | * @verbose: Print info even when enough bandwidth is available |
9e506a7b | 5995 | * |
2d1ce5ec AG |
5996 | * If the available bandwidth at the device is less than the device is |
5997 | * capable of, report the device's maximum possible bandwidth and the | |
5998 | * upstream link that limits its performance. If @verbose, always print | |
5999 | * the available bandwidth, even if the device isn't constrained. | |
9e506a7b | 6000 | */ |
2d1ce5ec | 6001 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose) |
9e506a7b TG |
6002 | { |
6003 | enum pcie_link_width width, width_cap; | |
6004 | enum pci_bus_speed speed, speed_cap; | |
6005 | struct pci_dev *limiting_dev = NULL; | |
6006 | u32 bw_avail, bw_cap; | |
6007 | ||
6008 | bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap); | |
6009 | bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width); | |
6010 | ||
2d1ce5ec | 6011 | if (bw_avail >= bw_cap && verbose) |
0cf22d6b | 6012 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n", |
9e506a7b | 6013 | bw_cap / 1000, bw_cap % 1000, |
6348a34d | 6014 | pci_speed_string(speed_cap), width_cap); |
2d1ce5ec | 6015 | else if (bw_avail < bw_cap) |
0cf22d6b | 6016 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n", |
9e506a7b | 6017 | bw_avail / 1000, bw_avail % 1000, |
6348a34d | 6018 | pci_speed_string(speed), width, |
9e506a7b TG |
6019 | limiting_dev ? pci_name(limiting_dev) : "<unknown>", |
6020 | bw_cap / 1000, bw_cap % 1000, | |
6348a34d | 6021 | pci_speed_string(speed_cap), width_cap); |
9e506a7b | 6022 | } |
2d1ce5ec AG |
6023 | |
6024 | /** | |
6025 | * pcie_print_link_status - Report the PCI device's link speed and width | |
6026 | * @dev: PCI device to query | |
6027 | * | |
6028 | * Report the available bandwidth at the device. | |
6029 | */ | |
6030 | void pcie_print_link_status(struct pci_dev *dev) | |
6031 | { | |
6032 | __pcie_print_link_status(dev, true); | |
6033 | } | |
9e506a7b TG |
6034 | EXPORT_SYMBOL(pcie_print_link_status); |
6035 | ||
c87deff7 HS |
6036 | /** |
6037 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 6038 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
6039 | * @flags: resource type mask to be selected |
6040 | * | |
6041 | * This helper routine makes bar mask from the type of resource. | |
6042 | */ | |
6043 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
6044 | { | |
6045 | int i, bars = 0; | |
6046 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
6047 | if (pci_resource_flags(dev, i) & flags) | |
6048 | bars |= (1 << i); | |
6049 | return bars; | |
6050 | } | |
b7fe9434 | 6051 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 6052 | |
95a8b6ef MT |
6053 | /* Some architectures require additional programming to enable VGA */ |
6054 | static arch_set_vga_state_t arch_set_vga_state; | |
6055 | ||
6056 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
6057 | { | |
6058 | arch_set_vga_state = func; /* NULL disables */ | |
6059 | } | |
6060 | ||
6061 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 6062 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
6063 | { |
6064 | if (arch_set_vga_state) | |
6065 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 6066 | flags); |
95a8b6ef MT |
6067 | return 0; |
6068 | } | |
6069 | ||
deb2d2ec BH |
6070 | /** |
6071 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
6072 | * @dev: the PCI device |
6073 | * @decode: true = enable decoding, false = disable decoding | |
6074 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 6075 | * @flags: traverse ancestors and change bridges |
3448a19d | 6076 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
6077 | */ |
6078 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 6079 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
6080 | { |
6081 | struct pci_bus *bus; | |
6082 | struct pci_dev *bridge; | |
6083 | u16 cmd; | |
95a8b6ef | 6084 | int rc; |
deb2d2ec | 6085 | |
67ebd814 | 6086 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 6087 | |
95a8b6ef | 6088 | /* ARCH specific VGA enables */ |
3448a19d | 6089 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
6090 | if (rc) |
6091 | return rc; | |
6092 | ||
3448a19d DA |
6093 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
6094 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
0a98bb98 | 6095 | if (decode) |
3448a19d DA |
6096 | cmd |= command_bits; |
6097 | else | |
6098 | cmd &= ~command_bits; | |
6099 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
6100 | } | |
deb2d2ec | 6101 | |
3448a19d | 6102 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
6103 | return 0; |
6104 | ||
6105 | bus = dev->bus; | |
6106 | while (bus) { | |
6107 | bridge = bus->self; | |
6108 | if (bridge) { | |
6109 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
6110 | &cmd); | |
0a98bb98 | 6111 | if (decode) |
deb2d2ec BH |
6112 | cmd |= PCI_BRIDGE_CTL_VGA; |
6113 | else | |
6114 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
6115 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
6116 | cmd); | |
6117 | } | |
6118 | bus = bus->parent; | |
6119 | } | |
6120 | return 0; | |
6121 | } | |
6122 | ||
52525b7a KHF |
6123 | #ifdef CONFIG_ACPI |
6124 | bool pci_pr3_present(struct pci_dev *pdev) | |
6125 | { | |
6126 | struct acpi_device *adev; | |
6127 | ||
6128 | if (acpi_disabled) | |
6129 | return false; | |
6130 | ||
6131 | adev = ACPI_COMPANION(&pdev->dev); | |
6132 | if (!adev) | |
6133 | return false; | |
6134 | ||
6135 | return adev->power.flags.power_resources && | |
6136 | acpi_has_method(adev->handle, "_PR3"); | |
6137 | } | |
6138 | EXPORT_SYMBOL_GPL(pci_pr3_present); | |
6139 | #endif | |
6140 | ||
f0af9593 BH |
6141 | /** |
6142 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
6143 | * @dev: the PCI device for which alias is added | |
09298542 JS |
6144 | * @devfn_from: alias slot and function |
6145 | * @nr_devfns: number of subsequent devfns to alias | |
f0af9593 | 6146 | * |
f778a0d2 LG |
6147 | * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask |
6148 | * which is used to program permissible bus-devfn source addresses for DMA | |
6149 | * requests in an IOMMU. These aliases factor into IOMMU group creation | |
6150 | * and are useful for devices generating DMA requests beyond or different | |
6151 | * from their logical bus-devfn. Examples include device quirks where the | |
6152 | * device simply uses the wrong devfn, as well as non-transparent bridges | |
6153 | * where the alias may be a proxy for devices in another domain. | |
6154 | * | |
6155 | * IOMMU group creation is performed during device discovery or addition, | |
6156 | * prior to any potential DMA mapping and therefore prior to driver probing | |
6157 | * (especially for userspace assigned devices where IOMMU group definition | |
6158 | * cannot be left as a userspace activity). DMA aliases should therefore | |
6159 | * be configured via quirks, such as the PCI fixup header quirk. | |
f0af9593 | 6160 | */ |
09298542 | 6161 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns) |
f0af9593 | 6162 | { |
09298542 JS |
6163 | int devfn_to; |
6164 | ||
6165 | nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from); | |
6166 | devfn_to = devfn_from + nr_devfns - 1; | |
6167 | ||
338c3149 | 6168 | if (!dev->dma_alias_mask) |
f8bf2aeb | 6169 | dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); |
338c3149 | 6170 | if (!dev->dma_alias_mask) { |
7506dc79 | 6171 | pci_warn(dev, "Unable to allocate DMA alias mask\n"); |
338c3149 JL |
6172 | return; |
6173 | } | |
6174 | ||
09298542 JS |
6175 | bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); |
6176 | ||
6177 | if (nr_devfns == 1) | |
6178 | pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n", | |
6179 | PCI_SLOT(devfn_from), PCI_FUNC(devfn_from)); | |
6180 | else if (nr_devfns > 1) | |
6181 | pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n", | |
6182 | PCI_SLOT(devfn_from), PCI_FUNC(devfn_from), | |
6183 | PCI_SLOT(devfn_to), PCI_FUNC(devfn_to)); | |
f0af9593 BH |
6184 | } |
6185 | ||
338c3149 JL |
6186 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
6187 | { | |
6188 | return (dev1->dma_alias_mask && | |
6189 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
6190 | (dev2->dma_alias_mask && | |
2856ba60 JD |
6191 | test_bit(dev1->devfn, dev2->dma_alias_mask)) || |
6192 | pci_real_dma_dev(dev1) == dev2 || | |
6193 | pci_real_dma_dev(dev2) == dev1; | |
338c3149 JL |
6194 | } |
6195 | ||
8496e85c RW |
6196 | bool pci_device_is_present(struct pci_dev *pdev) |
6197 | { | |
6198 | u32 v; | |
6199 | ||
fe2bd75b KB |
6200 | if (pci_dev_is_disconnected(pdev)) |
6201 | return false; | |
8496e85c RW |
6202 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); |
6203 | } | |
6204 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
6205 | ||
08249651 RW |
6206 | void pci_ignore_hotplug(struct pci_dev *dev) |
6207 | { | |
6208 | struct pci_dev *bridge = dev->bus->self; | |
6209 | ||
6210 | dev->ignore_hotplug = 1; | |
6211 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
6212 | if (bridge) | |
6213 | bridge->ignore_hotplug = 1; | |
6214 | } | |
6215 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
6216 | ||
2856ba60 JD |
6217 | /** |
6218 | * pci_real_dma_dev - Get PCI DMA device for PCI device | |
6219 | * @dev: the PCI device that may have a PCI DMA alias | |
6220 | * | |
6221 | * Permits the platform to provide architecture-specific functionality to | |
6222 | * devices needing to alias DMA to another PCI device on another PCI bus. If | |
6223 | * the PCI device is on the same bus, it is recommended to use | |
6224 | * pci_add_dma_alias(). This is the default implementation. Architecture | |
6225 | * implementations can override this. | |
6226 | */ | |
6227 | struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev) | |
6228 | { | |
6229 | return dev; | |
6230 | } | |
6231 | ||
0a701aa6 YX |
6232 | resource_size_t __weak pcibios_default_alignment(void) |
6233 | { | |
6234 | return 0; | |
6235 | } | |
6236 | ||
b8074aa2 DE |
6237 | /* |
6238 | * Arches that don't want to expose struct resource to userland as-is in | |
6239 | * sysfs and /proc can implement their own pci_resource_to_user(). | |
6240 | */ | |
6241 | void __weak pci_resource_to_user(const struct pci_dev *dev, int bar, | |
6242 | const struct resource *rsrc, | |
6243 | resource_size_t *start, resource_size_t *end) | |
6244 | { | |
6245 | *start = rsrc->start; | |
6246 | *end = rsrc->end; | |
6247 | } | |
6248 | ||
70aaf61a | 6249 | static char *resource_alignment_param; |
e9d1e492 | 6250 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
6251 | |
6252 | /** | |
6253 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
6254 | * @dev: the PCI device to get | |
e3adec72 | 6255 | * @resize: whether or not to change resources' size when reassigning alignment |
32a9a682 YS |
6256 | * |
6257 | * RETURNS: Resource alignment if it is specified. | |
6258 | * Zero if it is not specified. | |
6259 | */ | |
e3adec72 YX |
6260 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, |
6261 | bool *resize) | |
32a9a682 | 6262 | { |
07d8d7e5 | 6263 | int align_order, count; |
0a701aa6 | 6264 | resource_size_t align = pcibios_default_alignment(); |
07d8d7e5 LG |
6265 | const char *p; |
6266 | int ret; | |
32a9a682 YS |
6267 | |
6268 | spin_lock(&resource_alignment_lock); | |
6269 | p = resource_alignment_param; | |
70aaf61a | 6270 | if (!p || !*p) |
f0b99f70 YX |
6271 | goto out; |
6272 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
0a701aa6 | 6273 | align = 0; |
f0b99f70 YX |
6274 | pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); |
6275 | goto out; | |
6276 | } | |
6277 | ||
32a9a682 YS |
6278 | while (*p) { |
6279 | count = 0; | |
6280 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
6534aac1 | 6281 | p[count] == '@') { |
32a9a682 | 6282 | p += count + 1; |
6534aac1 BH |
6283 | if (align_order > 63) { |
6284 | pr_err("PCI: Invalid requested alignment (order %d)\n", | |
6285 | align_order); | |
6286 | align_order = PAGE_SHIFT; | |
6287 | } | |
32a9a682 | 6288 | } else { |
6534aac1 | 6289 | align_order = PAGE_SHIFT; |
32a9a682 | 6290 | } |
07d8d7e5 LG |
6291 | |
6292 | ret = pci_dev_str_match(dev, p, &p); | |
6293 | if (ret == 1) { | |
6294 | *resize = true; | |
cc73eb32 | 6295 | align = 1ULL << align_order; |
07d8d7e5 LG |
6296 | break; |
6297 | } else if (ret < 0) { | |
6298 | pr_err("PCI: Can't parse resource_alignment parameter: %s\n", | |
6299 | p); | |
6300 | break; | |
32a9a682 | 6301 | } |
07d8d7e5 | 6302 | |
32a9a682 YS |
6303 | if (*p != ';' && *p != ',') { |
6304 | /* End of param or invalid format */ | |
6305 | break; | |
6306 | } | |
6307 | p++; | |
6308 | } | |
f0b99f70 | 6309 | out: |
32a9a682 YS |
6310 | spin_unlock(&resource_alignment_lock); |
6311 | return align; | |
6312 | } | |
6313 | ||
81a5e70e | 6314 | static void pci_request_resource_alignment(struct pci_dev *dev, int bar, |
e3adec72 | 6315 | resource_size_t align, bool resize) |
81a5e70e BH |
6316 | { |
6317 | struct resource *r = &dev->resource[bar]; | |
6318 | resource_size_t size; | |
6319 | ||
6320 | if (!(r->flags & IORESOURCE_MEM)) | |
6321 | return; | |
6322 | ||
6323 | if (r->flags & IORESOURCE_PCI_FIXED) { | |
7506dc79 | 6324 | pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n", |
81a5e70e BH |
6325 | bar, r, (unsigned long long)align); |
6326 | return; | |
6327 | } | |
6328 | ||
6329 | size = resource_size(r); | |
0dde1c08 BH |
6330 | if (size >= align) |
6331 | return; | |
81a5e70e | 6332 | |
0dde1c08 | 6333 | /* |
e3adec72 YX |
6334 | * Increase the alignment of the resource. There are two ways we |
6335 | * can do this: | |
0dde1c08 | 6336 | * |
e3adec72 YX |
6337 | * 1) Increase the size of the resource. BARs are aligned on their |
6338 | * size, so when we reallocate space for this resource, we'll | |
6339 | * allocate it with the larger alignment. This also prevents | |
6340 | * assignment of any other BARs inside the alignment region, so | |
6341 | * if we're requesting page alignment, this means no other BARs | |
6342 | * will share the page. | |
6343 | * | |
6344 | * The disadvantage is that this makes the resource larger than | |
6345 | * the hardware BAR, which may break drivers that compute things | |
6346 | * based on the resource size, e.g., to find registers at a | |
6347 | * fixed offset before the end of the BAR. | |
6348 | * | |
6349 | * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and | |
6350 | * set r->start to the desired alignment. By itself this | |
6351 | * doesn't prevent other BARs being put inside the alignment | |
6352 | * region, but if we realign *every* resource of every device in | |
6353 | * the system, none of them will share an alignment region. | |
6354 | * | |
6355 | * When the user has requested alignment for only some devices via | |
6356 | * the "pci=resource_alignment" argument, "resize" is true and we | |
6357 | * use the first method. Otherwise we assume we're aligning all | |
6358 | * devices and we use the second. | |
0dde1c08 | 6359 | */ |
e3adec72 | 6360 | |
7506dc79 | 6361 | pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n", |
0dde1c08 | 6362 | bar, r, (unsigned long long)align); |
81a5e70e | 6363 | |
e3adec72 YX |
6364 | if (resize) { |
6365 | r->start = 0; | |
6366 | r->end = align - 1; | |
6367 | } else { | |
6368 | r->flags &= ~IORESOURCE_SIZEALIGN; | |
6369 | r->flags |= IORESOURCE_STARTALIGN; | |
6370 | r->start = align; | |
6371 | r->end = r->start + size - 1; | |
6372 | } | |
0dde1c08 | 6373 | r->flags |= IORESOURCE_UNSET; |
81a5e70e BH |
6374 | } |
6375 | ||
2069ecfb YL |
6376 | /* |
6377 | * This function disables memory decoding and releases memory resources | |
6378 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
6379 | * It also rounds up size to specified alignment. | |
6380 | * Later on, the kernel will assign page-aligned memory resource back | |
6381 | * to the device. | |
6382 | */ | |
6383 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
6384 | { | |
6385 | int i; | |
6386 | struct resource *r; | |
81a5e70e | 6387 | resource_size_t align; |
2069ecfb | 6388 | u16 command; |
e3adec72 | 6389 | bool resize = false; |
2069ecfb | 6390 | |
62d9a78f YX |
6391 | /* |
6392 | * VF BARs are read-only zero according to SR-IOV spec r1.1, sec | |
6393 | * 3.4.1.11. Their resources are allocated from the space | |
6394 | * described by the VF BARx register in the PF's SR-IOV capability. | |
6395 | * We can't influence their alignment here. | |
6396 | */ | |
6397 | if (dev->is_virtfn) | |
6398 | return; | |
6399 | ||
10c463a7 | 6400 | /* check if specified PCI is target device to reassign */ |
e3adec72 | 6401 | align = pci_specified_resource_alignment(dev, &resize); |
10c463a7 | 6402 | if (!align) |
2069ecfb YL |
6403 | return; |
6404 | ||
6405 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
6406 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
7506dc79 | 6407 | pci_warn(dev, "Can't reassign resources to host bridge\n"); |
2069ecfb YL |
6408 | return; |
6409 | } | |
6410 | ||
2069ecfb YL |
6411 | pci_read_config_word(dev, PCI_COMMAND, &command); |
6412 | command &= ~PCI_COMMAND_MEMORY; | |
6413 | pci_write_config_word(dev, PCI_COMMAND, command); | |
6414 | ||
81a5e70e | 6415 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
e3adec72 | 6416 | pci_request_resource_alignment(dev, i, align, resize); |
f0b99f70 | 6417 | |
81a5e70e BH |
6418 | /* |
6419 | * Need to disable bridge's resource window, | |
2069ecfb YL |
6420 | * to enable the kernel to reassign new resource |
6421 | * window later on. | |
6422 | */ | |
b2fb5cc5 | 6423 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { |
2069ecfb YL |
6424 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { |
6425 | r = &dev->resource[i]; | |
6426 | if (!(r->flags & IORESOURCE_MEM)) | |
6427 | continue; | |
bd064f0a | 6428 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
6429 | r->end = resource_size(r) - 1; |
6430 | r->start = 0; | |
6431 | } | |
6432 | pci_disable_bridge_window(dev); | |
6433 | } | |
6434 | } | |
6435 | ||
273b177c | 6436 | static ssize_t resource_alignment_show(struct bus_type *bus, char *buf) |
32a9a682 | 6437 | { |
70aaf61a | 6438 | size_t count = 0; |
32a9a682 | 6439 | |
32a9a682 | 6440 | spin_lock(&resource_alignment_lock); |
70aaf61a | 6441 | if (resource_alignment_param) |
e7a7499d | 6442 | count = scnprintf(buf, PAGE_SIZE, "%s", resource_alignment_param); |
32a9a682 | 6443 | spin_unlock(&resource_alignment_lock); |
32a9a682 | 6444 | |
e499081d LG |
6445 | /* |
6446 | * When set by the command line, resource_alignment_param will not | |
6447 | * have a trailing line feed, which is ugly. So conditionally add | |
6448 | * it here. | |
6449 | */ | |
6450 | if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) { | |
6451 | buf[count - 1] = '\n'; | |
6452 | buf[count++] = 0; | |
6453 | } | |
6454 | ||
32a9a682 | 6455 | return count; |
32a9a682 YS |
6456 | } |
6457 | ||
d61dfafc | 6458 | static ssize_t resource_alignment_store(struct bus_type *bus, |
32a9a682 YS |
6459 | const char *buf, size_t count) |
6460 | { | |
273b177c LG |
6461 | char *param = kstrndup(buf, count, GFP_KERNEL); |
6462 | ||
6463 | if (!param) | |
6464 | return -ENOMEM; | |
6465 | ||
6466 | spin_lock(&resource_alignment_lock); | |
6467 | kfree(resource_alignment_param); | |
6468 | resource_alignment_param = param; | |
6469 | spin_unlock(&resource_alignment_lock); | |
6470 | return count; | |
32a9a682 YS |
6471 | } |
6472 | ||
d61dfafc | 6473 | static BUS_ATTR_RW(resource_alignment); |
32a9a682 YS |
6474 | |
6475 | static int __init pci_resource_alignment_sysfs_init(void) | |
6476 | { | |
6477 | return bus_create_file(&pci_bus_type, | |
6478 | &bus_attr_resource_alignment); | |
6479 | } | |
32a9a682 YS |
6480 | late_initcall(pci_resource_alignment_sysfs_init); |
6481 | ||
15856ad5 | 6482 | static void pci_no_domains(void) |
32a2eea7 JG |
6483 | { |
6484 | #ifdef CONFIG_PCI_DOMAINS | |
6485 | pci_domains_supported = 0; | |
6486 | #endif | |
6487 | } | |
6488 | ||
ae07b786 | 6489 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
41e5c0f8 LD |
6490 | static atomic_t __domain_nr = ATOMIC_INIT(-1); |
6491 | ||
ae07b786 | 6492 | static int pci_get_new_domain_nr(void) |
41e5c0f8 LD |
6493 | { |
6494 | return atomic_inc_return(&__domain_nr); | |
6495 | } | |
7c674700 | 6496 | |
1a4f93f7 | 6497 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
6498 | { |
6499 | static int use_dt_domains = -1; | |
54c6e2dd | 6500 | int domain = -1; |
7c674700 | 6501 | |
54c6e2dd KHC |
6502 | if (parent) |
6503 | domain = of_get_pci_domain_nr(parent->of_node); | |
74356add | 6504 | |
7c674700 LP |
6505 | /* |
6506 | * Check DT domain and use_dt_domains values. | |
6507 | * | |
6508 | * If DT domain property is valid (domain >= 0) and | |
6509 | * use_dt_domains != 0, the DT assignment is valid since this means | |
6510 | * we have not previously allocated a domain number by using | |
6511 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
6512 | * 1, to indicate that we have just assigned a domain number from | |
6513 | * DT. | |
6514 | * | |
6515 | * If DT domain property value is not valid (ie domain < 0), and we | |
6516 | * have not previously assigned a domain number from DT | |
6517 | * (use_dt_domains != 1) we should assign a domain number by | |
6518 | * using the: | |
6519 | * | |
6520 | * pci_get_new_domain_nr() | |
6521 | * | |
6522 | * API and update the use_dt_domains value to keep track of method we | |
6523 | * are using to assign domain numbers (use_dt_domains = 0). | |
6524 | * | |
6525 | * All other combinations imply we have a platform that is trying | |
6526 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
6527 | * which is a recipe for domain mishandling and it is prevented by | |
6528 | * invalidating the domain value (domain = -1) and printing a | |
6529 | * corresponding error. | |
6530 | */ | |
6531 | if (domain >= 0 && use_dt_domains) { | |
6532 | use_dt_domains = 1; | |
6533 | } else if (domain < 0 && use_dt_domains != 1) { | |
6534 | use_dt_domains = 0; | |
6535 | domain = pci_get_new_domain_nr(); | |
6536 | } else { | |
9df1c6ec SL |
6537 | if (parent) |
6538 | pr_err("Node %pOF has ", parent->of_node); | |
6539 | pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); | |
7c674700 LP |
6540 | domain = -1; |
6541 | } | |
6542 | ||
9c7cb891 | 6543 | return domain; |
7c674700 | 6544 | } |
1a4f93f7 TN |
6545 | |
6546 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
6547 | { | |
2ab51dde TN |
6548 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
6549 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
6550 | } |
6551 | #endif | |
41e5c0f8 | 6552 | |
0ef5f8f6 | 6553 | /** |
642c92da | 6554 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
6555 | * |
6556 | * Returns 1 if we can access PCI extended config space (offsets | |
6557 | * greater than 0xff). This is the default implementation. Architecture | |
6558 | * implementations can override this. | |
6559 | */ | |
642c92da | 6560 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
6561 | { |
6562 | return 1; | |
6563 | } | |
6564 | ||
2d1c8618 BH |
6565 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
6566 | { | |
6567 | } | |
6568 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
6569 | ||
ad04d31e | 6570 | static int __init pci_setup(char *str) |
1da177e4 LT |
6571 | { |
6572 | while (str) { | |
6573 | char *k = strchr(str, ','); | |
6574 | if (k) | |
6575 | *k++ = 0; | |
6576 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
6577 | if (!strcmp(str, "nomsi")) { |
6578 | pci_no_msi(); | |
cef74409 GK |
6579 | } else if (!strncmp(str, "noats", 5)) { |
6580 | pr_info("PCIe: ATS is disabled\n"); | |
6581 | pcie_ats_disabled = true; | |
7f785763 RD |
6582 | } else if (!strcmp(str, "noaer")) { |
6583 | pci_no_aer(); | |
11eb0e0e SK |
6584 | } else if (!strcmp(str, "earlydump")) { |
6585 | pci_early_dump = true; | |
b55438fd YL |
6586 | } else if (!strncmp(str, "realloc=", 8)) { |
6587 | pci_realloc_get_opt(str + 8); | |
f483d392 | 6588 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 6589 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
6590 | } else if (!strcmp(str, "nodomains")) { |
6591 | pci_no_domains(); | |
6748dcc2 RW |
6592 | } else if (!strncmp(str, "noari", 5)) { |
6593 | pcie_ari_disabled = true; | |
4516a618 AN |
6594 | } else if (!strncmp(str, "cbiosize=", 9)) { |
6595 | pci_cardbus_io_size = memparse(str + 9, &str); | |
6596 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
6597 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 | 6598 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
70aaf61a | 6599 | resource_alignment_param = str + 19; |
43c16408 AP |
6600 | } else if (!strncmp(str, "ecrc=", 5)) { |
6601 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
6602 | } else if (!strncmp(str, "hpiosize=", 9)) { |
6603 | pci_hotplug_io_size = memparse(str + 9, &str); | |
d7b8a217 NJ |
6604 | } else if (!strncmp(str, "hpmmiosize=", 11)) { |
6605 | pci_hotplug_mmio_size = memparse(str + 11, &str); | |
6606 | } else if (!strncmp(str, "hpmmioprefsize=", 15)) { | |
6607 | pci_hotplug_mmio_pref_size = memparse(str + 15, &str); | |
28760489 | 6608 | } else if (!strncmp(str, "hpmemsize=", 10)) { |
d7b8a217 NJ |
6609 | pci_hotplug_mmio_size = memparse(str + 10, &str); |
6610 | pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size; | |
e16b4660 KB |
6611 | } else if (!strncmp(str, "hpbussize=", 10)) { |
6612 | pci_hotplug_bus_size = | |
6613 | simple_strtoul(str + 10, &str, 0); | |
6614 | if (pci_hotplug_bus_size > 0xff) | |
6615 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
6616 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
6617 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
6618 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
6619 | pcie_bus_config = PCIE_BUS_SAFE; | |
6620 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
6621 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
6622 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
6623 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
6624 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
6625 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
aaca43fd | 6626 | } else if (!strncmp(str, "disable_acs_redir=", 18)) { |
d5bc73f3 | 6627 | disable_acs_redir_param = str + 18; |
309e57df | 6628 | } else { |
25da8dba | 6629 | pr_err("PCI: Unknown option `%s'\n", str); |
309e57df | 6630 | } |
1da177e4 LT |
6631 | } |
6632 | str = k; | |
6633 | } | |
0637a70a | 6634 | return 0; |
1da177e4 | 6635 | } |
0637a70a | 6636 | early_param("pci", pci_setup); |
d5bc73f3 LG |
6637 | |
6638 | /* | |
70aaf61a LG |
6639 | * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized |
6640 | * in pci_setup(), above, to point to data in the __initdata section which | |
6641 | * will be freed after the init sequence is complete. We can't allocate memory | |
6642 | * in pci_setup() because some architectures do not have any memory allocation | |
6643 | * service available during an early_param() call. So we allocate memory and | |
6644 | * copy the variable here before the init section is freed. | |
6645 | * | |
d5bc73f3 LG |
6646 | */ |
6647 | static int __init pci_realloc_setup_params(void) | |
6648 | { | |
70aaf61a LG |
6649 | resource_alignment_param = kstrdup(resource_alignment_param, |
6650 | GFP_KERNEL); | |
d5bc73f3 LG |
6651 | disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL); |
6652 | ||
6653 | return 0; | |
6654 | } | |
6655 | pure_initcall(pci_realloc_setup_params); |