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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
1da177e4 | 4 | * |
df62ab5e BH |
5 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
6 | * David Mosberger-Tang | |
1da177e4 | 7 | * |
df62ab5e | 8 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
1da177e4 LT |
9 | */ |
10 | ||
2ab51dde | 11 | #include <linux/acpi.h> |
1da177e4 LT |
12 | #include <linux/kernel.h> |
13 | #include <linux/delay.h> | |
9d26d3a8 | 14 | #include <linux/dmi.h> |
1da177e4 | 15 | #include <linux/init.h> |
bbd8810d | 16 | #include <linux/msi.h> |
7c674700 LP |
17 | #include <linux/of.h> |
18 | #include <linux/of_pci.h> | |
1da177e4 | 19 | #include <linux/pci.h> |
075c1771 | 20 | #include <linux/pm.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
1da177e4 LT |
22 | #include <linux/module.h> |
23 | #include <linux/spinlock.h> | |
4e57b681 | 24 | #include <linux/string.h> |
229f5afd | 25 | #include <linux/log2.h> |
5745392e | 26 | #include <linux/logic_pio.h> |
c300bd2f | 27 | #include <linux/pm_wakeup.h> |
8dd7f803 | 28 | #include <linux/interrupt.h> |
32a9a682 | 29 | #include <linux/device.h> |
b67ea761 | 30 | #include <linux/pm_runtime.h> |
608c3881 | 31 | #include <linux/pci_hotplug.h> |
4d3f1384 | 32 | #include <linux/vmalloc.h> |
4ebeb1ec | 33 | #include <linux/pci-ats.h> |
32a9a682 | 34 | #include <asm/setup.h> |
2a2aca31 | 35 | #include <asm/dma.h> |
b07461a8 | 36 | #include <linux/aer.h> |
bc56b9e0 | 37 | #include "pci.h" |
1da177e4 | 38 | |
c4eed62a KB |
39 | DEFINE_MUTEX(pci_slot_mutex); |
40 | ||
00240c38 AS |
41 | const char *pci_power_names[] = { |
42 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
43 | }; | |
44 | EXPORT_SYMBOL_GPL(pci_power_names); | |
45 | ||
93177a74 RW |
46 | int isa_dma_bridge_buggy; |
47 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
48 | ||
49 | int pci_pci_problems; | |
50 | EXPORT_SYMBOL(pci_pci_problems); | |
51 | ||
1ae861e6 RW |
52 | unsigned int pci_pm_d3_delay; |
53 | ||
df17e62e MG |
54 | static void pci_pme_list_scan(struct work_struct *work); |
55 | ||
56 | static LIST_HEAD(pci_pme_list); | |
57 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
58 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
59 | ||
60 | struct pci_pme_device { | |
61 | struct list_head list; | |
62 | struct pci_dev *dev; | |
63 | }; | |
64 | ||
65 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
66 | ||
1ae861e6 RW |
67 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
68 | { | |
69 | unsigned int delay = dev->d3_delay; | |
70 | ||
71 | if (delay < pci_pm_d3_delay) | |
72 | delay = pci_pm_d3_delay; | |
73 | ||
50b2b540 AH |
74 | if (delay) |
75 | msleep(delay); | |
1ae861e6 | 76 | } |
1da177e4 | 77 | |
32a2eea7 JG |
78 | #ifdef CONFIG_PCI_DOMAINS |
79 | int pci_domains_supported = 1; | |
80 | #endif | |
81 | ||
4516a618 AN |
82 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
83 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
84 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
85 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
86 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
87 | ||
28760489 | 88 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
d7b8a217 NJ |
89 | #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024) |
90 | #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024) | |
91 | /* hpiosize=nn can override this */ | |
28760489 | 92 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; |
d7b8a217 NJ |
93 | /* |
94 | * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size, | |
95 | * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size; | |
96 | * pci=hpmemsize=nnM overrides both | |
97 | */ | |
98 | unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE; | |
99 | unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE; | |
28760489 | 100 | |
e16b4660 KB |
101 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
102 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
103 | ||
27d868b5 | 104 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b03e7495 | 105 | |
ac1aa47b JB |
106 | /* |
107 | * The default CLS is used if arch didn't set CLS explicitly and not | |
108 | * all pci devices agree on the same value. Arch can override either | |
109 | * the dfl or actual value as it sees fit. Don't forget this is | |
110 | * measured in 32-bit words, not bytes. | |
111 | */ | |
15856ad5 | 112 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
113 | u8 pci_cache_line_size; |
114 | ||
96c55900 MS |
115 | /* |
116 | * If we set up a device for bus mastering, we need to check the latency | |
117 | * timer as certain BIOSes forget to set it properly. | |
118 | */ | |
119 | unsigned int pcibios_max_latency = 255; | |
120 | ||
6748dcc2 RW |
121 | /* If set, the PCIe ARI capability will not be used. */ |
122 | static bool pcie_ari_disabled; | |
123 | ||
cef74409 GK |
124 | /* If set, the PCIe ATS capability will not be used. */ |
125 | static bool pcie_ats_disabled; | |
126 | ||
11eb0e0e SK |
127 | /* If set, the PCI config space of each device is printed during boot. */ |
128 | bool pci_early_dump; | |
129 | ||
cef74409 GK |
130 | bool pci_ats_disabled(void) |
131 | { | |
132 | return pcie_ats_disabled; | |
133 | } | |
1a373a78 | 134 | EXPORT_SYMBOL_GPL(pci_ats_disabled); |
cef74409 | 135 | |
9d26d3a8 MW |
136 | /* Disable bridge_d3 for all PCIe ports */ |
137 | static bool pci_bridge_d3_disable; | |
138 | /* Force bridge_d3 for all PCIe ports */ | |
139 | static bool pci_bridge_d3_force; | |
140 | ||
141 | static int __init pcie_port_pm_setup(char *str) | |
142 | { | |
143 | if (!strcmp(str, "off")) | |
144 | pci_bridge_d3_disable = true; | |
145 | else if (!strcmp(str, "force")) | |
146 | pci_bridge_d3_force = true; | |
147 | return 1; | |
148 | } | |
149 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
150 | ||
a2758b6b SK |
151 | /* Time to wait after a reset for device to become responsive */ |
152 | #define PCIE_RESET_READY_POLL_MS 60000 | |
153 | ||
1da177e4 LT |
154 | /** |
155 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
156 | * @bus: pointer to PCI bus structure to search | |
157 | * | |
158 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
159 | * including the given PCI bus and its list of child PCI buses. | |
160 | */ | |
07656d83 | 161 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 162 | { |
94e6a9b9 | 163 | struct pci_bus *tmp; |
1da177e4 LT |
164 | unsigned char max, n; |
165 | ||
b918c62e | 166 | max = bus->busn_res.end; |
94e6a9b9 YW |
167 | list_for_each_entry(tmp, &bus->children, node) { |
168 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 169 | if (n > max) |
1da177e4 LT |
170 | max = n; |
171 | } | |
172 | return max; | |
173 | } | |
b82db5ce | 174 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 175 | |
1684f5dd AM |
176 | #ifdef CONFIG_HAS_IOMEM |
177 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
178 | { | |
1f7bf3bf BH |
179 | struct resource *res = &pdev->resource[bar]; |
180 | ||
1684f5dd AM |
181 | /* |
182 | * Make sure the BAR is actually a memory resource, not an IO resource | |
183 | */ | |
646c0282 | 184 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
7506dc79 | 185 | pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
186 | return NULL; |
187 | } | |
4bdc0d67 | 188 | return ioremap(res->start, resource_size(res)); |
1684f5dd AM |
189 | } |
190 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
191 | |
192 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
193 | { | |
194 | /* | |
195 | * Make sure the BAR is actually a memory resource, not an IO resource | |
196 | */ | |
197 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
198 | WARN_ON(1); | |
199 | return NULL; | |
200 | } | |
201 | return ioremap_wc(pci_resource_start(pdev, bar), | |
202 | pci_resource_len(pdev, bar)); | |
203 | } | |
204 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
205 | #endif |
206 | ||
45db3370 LG |
207 | /** |
208 | * pci_dev_str_match_path - test if a path string matches a device | |
74356add BH |
209 | * @dev: the PCI device to test |
210 | * @path: string to match the device against | |
45db3370 LG |
211 | * @endptr: pointer to the string after the match |
212 | * | |
213 | * Test if a string (typically from a kernel parameter) formatted as a | |
214 | * path of device/function addresses matches a PCI device. The string must | |
215 | * be of the form: | |
216 | * | |
217 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* | |
218 | * | |
219 | * A path for a device can be obtained using 'lspci -t'. Using a path | |
220 | * is more robust against bus renumbering than using only a single bus, | |
221 | * device and function address. | |
222 | * | |
223 | * Returns 1 if the string matches the device, 0 if it does not and | |
224 | * a negative error code if it fails to parse the string. | |
225 | */ | |
226 | static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, | |
227 | const char **endptr) | |
228 | { | |
229 | int ret; | |
230 | int seg, bus, slot, func; | |
231 | char *wpath, *p; | |
232 | char end; | |
233 | ||
234 | *endptr = strchrnul(path, ';'); | |
235 | ||
236 | wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL); | |
237 | if (!wpath) | |
238 | return -ENOMEM; | |
239 | ||
240 | while (1) { | |
241 | p = strrchr(wpath, '/'); | |
242 | if (!p) | |
243 | break; | |
244 | ret = sscanf(p, "/%x.%x%c", &slot, &func, &end); | |
245 | if (ret != 2) { | |
246 | ret = -EINVAL; | |
247 | goto free_and_exit; | |
248 | } | |
249 | ||
250 | if (dev->devfn != PCI_DEVFN(slot, func)) { | |
251 | ret = 0; | |
252 | goto free_and_exit; | |
253 | } | |
254 | ||
255 | /* | |
256 | * Note: we don't need to get a reference to the upstream | |
257 | * bridge because we hold a reference to the top level | |
258 | * device which should hold a reference to the bridge, | |
259 | * and so on. | |
260 | */ | |
261 | dev = pci_upstream_bridge(dev); | |
262 | if (!dev) { | |
263 | ret = 0; | |
264 | goto free_and_exit; | |
265 | } | |
266 | ||
267 | *p = 0; | |
268 | } | |
269 | ||
270 | ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot, | |
271 | &func, &end); | |
272 | if (ret != 4) { | |
273 | seg = 0; | |
274 | ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end); | |
275 | if (ret != 3) { | |
276 | ret = -EINVAL; | |
277 | goto free_and_exit; | |
278 | } | |
279 | } | |
280 | ||
281 | ret = (seg == pci_domain_nr(dev->bus) && | |
282 | bus == dev->bus->number && | |
283 | dev->devfn == PCI_DEVFN(slot, func)); | |
284 | ||
285 | free_and_exit: | |
286 | kfree(wpath); | |
287 | return ret; | |
288 | } | |
289 | ||
07d8d7e5 LG |
290 | /** |
291 | * pci_dev_str_match - test if a string matches a device | |
74356add BH |
292 | * @dev: the PCI device to test |
293 | * @p: string to match the device against | |
07d8d7e5 LG |
294 | * @endptr: pointer to the string after the match |
295 | * | |
296 | * Test if a string (typically from a kernel parameter) matches a specified | |
297 | * PCI device. The string may be of one of the following formats: | |
298 | * | |
45db3370 | 299 | * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]* |
07d8d7e5 LG |
300 | * pci:<vendor>:<device>[:<subvendor>:<subdevice>] |
301 | * | |
302 | * The first format specifies a PCI bus/device/function address which | |
303 | * may change if new hardware is inserted, if motherboard firmware changes, | |
304 | * or due to changes caused in kernel parameters. If the domain is | |
45db3370 LG |
305 | * left unspecified, it is taken to be 0. In order to be robust against |
306 | * bus renumbering issues, a path of PCI device/function numbers may be used | |
307 | * to address the specific device. The path for a device can be determined | |
308 | * through the use of 'lspci -t'. | |
07d8d7e5 LG |
309 | * |
310 | * The second format matches devices using IDs in the configuration | |
311 | * space which may match multiple devices in the system. A value of 0 | |
312 | * for any field will match all devices. (Note: this differs from | |
313 | * in-kernel code that uses PCI_ANY_ID which is ~0; this is for | |
314 | * legacy reasons and convenience so users don't have to specify | |
315 | * FFFFFFFFs on the command line.) | |
316 | * | |
317 | * Returns 1 if the string matches the device, 0 if it does not and | |
318 | * a negative error code if the string cannot be parsed. | |
319 | */ | |
320 | static int pci_dev_str_match(struct pci_dev *dev, const char *p, | |
321 | const char **endptr) | |
322 | { | |
323 | int ret; | |
45db3370 | 324 | int count; |
07d8d7e5 LG |
325 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
326 | ||
327 | if (strncmp(p, "pci:", 4) == 0) { | |
328 | /* PCI vendor/device (subvendor/subdevice) IDs are specified */ | |
329 | p += 4; | |
330 | ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device, | |
331 | &subsystem_vendor, &subsystem_device, &count); | |
332 | if (ret != 4) { | |
333 | ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count); | |
334 | if (ret != 2) | |
335 | return -EINVAL; | |
336 | ||
337 | subsystem_vendor = 0; | |
338 | subsystem_device = 0; | |
339 | } | |
340 | ||
341 | p += count; | |
342 | ||
343 | if ((!vendor || vendor == dev->vendor) && | |
344 | (!device || device == dev->device) && | |
345 | (!subsystem_vendor || | |
346 | subsystem_vendor == dev->subsystem_vendor) && | |
347 | (!subsystem_device || | |
348 | subsystem_device == dev->subsystem_device)) | |
349 | goto found; | |
07d8d7e5 | 350 | } else { |
45db3370 LG |
351 | /* |
352 | * PCI Bus, Device, Function IDs are specified | |
74356add | 353 | * (optionally, may include a path of devfns following it) |
45db3370 LG |
354 | */ |
355 | ret = pci_dev_str_match_path(dev, p, &p); | |
356 | if (ret < 0) | |
357 | return ret; | |
358 | else if (ret) | |
07d8d7e5 LG |
359 | goto found; |
360 | } | |
361 | ||
362 | *endptr = p; | |
363 | return 0; | |
364 | ||
365 | found: | |
366 | *endptr = p; | |
367 | return 1; | |
368 | } | |
687d5fe3 ME |
369 | |
370 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
371 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
372 | { |
373 | u8 id; | |
55db3208 SS |
374 | u16 ent; |
375 | ||
376 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 377 | |
687d5fe3 | 378 | while ((*ttl)--) { |
24a4e377 RD |
379 | if (pos < 0x40) |
380 | break; | |
381 | pos &= ~3; | |
55db3208 SS |
382 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
383 | ||
384 | id = ent & 0xff; | |
24a4e377 RD |
385 | if (id == 0xff) |
386 | break; | |
387 | if (id == cap) | |
388 | return pos; | |
55db3208 | 389 | pos = (ent >> 8); |
24a4e377 RD |
390 | } |
391 | return 0; | |
392 | } | |
393 | ||
687d5fe3 ME |
394 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
395 | u8 pos, int cap) | |
396 | { | |
397 | int ttl = PCI_FIND_CAP_TTL; | |
398 | ||
399 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
400 | } | |
401 | ||
24a4e377 RD |
402 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
403 | { | |
404 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
405 | pos + PCI_CAP_LIST_NEXT, cap); | |
406 | } | |
407 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
408 | ||
d3bac118 ME |
409 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
410 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
411 | { |
412 | u16 status; | |
1da177e4 LT |
413 | |
414 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
415 | if (!(status & PCI_STATUS_CAP_LIST)) | |
416 | return 0; | |
417 | ||
418 | switch (hdr_type) { | |
419 | case PCI_HEADER_TYPE_NORMAL: | |
420 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 421 | return PCI_CAPABILITY_LIST; |
1da177e4 | 422 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 423 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 424 | } |
d3bac118 ME |
425 | |
426 | return 0; | |
1da177e4 LT |
427 | } |
428 | ||
429 | /** | |
f7625980 | 430 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
431 | * @dev: PCI device to query |
432 | * @cap: capability code | |
433 | * | |
434 | * Tell if a device supports a given PCI capability. | |
435 | * Returns the address of the requested capability structure within the | |
436 | * device's PCI configuration space or 0 in case the device does not | |
74356add | 437 | * support it. Possible values for @cap include: |
1da177e4 | 438 | * |
f7625980 BH |
439 | * %PCI_CAP_ID_PM Power Management |
440 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
441 | * %PCI_CAP_ID_VPD Vital Product Data | |
442 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 443 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 444 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
445 | * %PCI_CAP_ID_PCIX PCI-X |
446 | * %PCI_CAP_ID_EXP PCI Express | |
447 | */ | |
448 | int pci_find_capability(struct pci_dev *dev, int cap) | |
449 | { | |
d3bac118 ME |
450 | int pos; |
451 | ||
452 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
453 | if (pos) | |
454 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
455 | ||
456 | return pos; | |
1da177e4 | 457 | } |
b7fe9434 | 458 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
459 | |
460 | /** | |
f7625980 | 461 | * pci_bus_find_capability - query for devices' capabilities |
74356add | 462 | * @bus: the PCI bus to query |
1da177e4 | 463 | * @devfn: PCI device to query |
74356add | 464 | * @cap: capability code |
1da177e4 | 465 | * |
74356add | 466 | * Like pci_find_capability() but works for PCI devices that do not have a |
f7625980 | 467 | * pci_dev structure set up yet. |
1da177e4 LT |
468 | * |
469 | * Returns the address of the requested capability structure within the | |
470 | * device's PCI configuration space or 0 in case the device does not | |
471 | * support it. | |
472 | */ | |
473 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
474 | { | |
d3bac118 | 475 | int pos; |
1da177e4 LT |
476 | u8 hdr_type; |
477 | ||
478 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
479 | ||
d3bac118 ME |
480 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
481 | if (pos) | |
482 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
483 | ||
484 | return pos; | |
1da177e4 | 485 | } |
b7fe9434 | 486 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
487 | |
488 | /** | |
44a9a36f | 489 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 490 | * @dev: PCI device to query |
44a9a36f | 491 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
492 | * @cap: capability code |
493 | * | |
44a9a36f | 494 | * Returns the address of the next matching extended capability structure |
1da177e4 | 495 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
496 | * not support it. Some capabilities can occur several times, e.g., the |
497 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 498 | */ |
44a9a36f | 499 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
500 | { |
501 | u32 header; | |
557848c3 ZY |
502 | int ttl; |
503 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 504 | |
557848c3 ZY |
505 | /* minimum 8 bytes per capability */ |
506 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
507 | ||
508 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
509 | return 0; |
510 | ||
44a9a36f BH |
511 | if (start) |
512 | pos = start; | |
513 | ||
1da177e4 LT |
514 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
515 | return 0; | |
516 | ||
517 | /* | |
518 | * If we have no capabilities, this is indicated by cap ID, | |
519 | * cap version and next pointer all being 0. | |
520 | */ | |
521 | if (header == 0) | |
522 | return 0; | |
523 | ||
524 | while (ttl-- > 0) { | |
44a9a36f | 525 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
526 | return pos; |
527 | ||
528 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 529 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
530 | break; |
531 | ||
532 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
533 | break; | |
534 | } | |
535 | ||
536 | return 0; | |
537 | } | |
44a9a36f BH |
538 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
539 | ||
540 | /** | |
541 | * pci_find_ext_capability - Find an extended capability | |
542 | * @dev: PCI device to query | |
543 | * @cap: capability code | |
544 | * | |
545 | * Returns the address of the requested extended capability structure | |
546 | * within the device's PCI configuration space or 0 if the device does | |
74356add | 547 | * not support it. Possible values for @cap include: |
44a9a36f BH |
548 | * |
549 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
550 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
551 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
552 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
553 | */ | |
554 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
555 | { | |
556 | return pci_find_next_ext_capability(dev, 0, cap); | |
557 | } | |
3a720d72 | 558 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 559 | |
687d5fe3 ME |
560 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
561 | { | |
562 | int rc, ttl = PCI_FIND_CAP_TTL; | |
563 | u8 cap, mask; | |
564 | ||
565 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
566 | mask = HT_3BIT_CAP_MASK; | |
567 | else | |
568 | mask = HT_5BIT_CAP_MASK; | |
569 | ||
570 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
571 | PCI_CAP_ID_HT, &ttl); | |
572 | while (pos) { | |
573 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
574 | if (rc != PCIBIOS_SUCCESSFUL) | |
575 | return 0; | |
576 | ||
577 | if ((cap & mask) == ht_cap) | |
578 | return pos; | |
579 | ||
47a4d5be BG |
580 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
581 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
582 | PCI_CAP_ID_HT, &ttl); |
583 | } | |
584 | ||
585 | return 0; | |
586 | } | |
587 | /** | |
588 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
589 | * @dev: PCI device to query | |
590 | * @pos: Position from which to continue searching | |
591 | * @ht_cap: Hypertransport capability code | |
592 | * | |
593 | * To be used in conjunction with pci_find_ht_capability() to search for | |
594 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
595 | * from pci_find_ht_capability(). | |
596 | * | |
597 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
598 | * steps to avoid an infinite loop. | |
599 | */ | |
600 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
601 | { | |
602 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
603 | } | |
604 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
605 | ||
606 | /** | |
607 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
608 | * @dev: PCI device to query | |
609 | * @ht_cap: Hypertransport capability code | |
610 | * | |
611 | * Tell if a device supports a given Hypertransport capability. | |
612 | * Returns an address within the device's PCI configuration space | |
613 | * or 0 in case the device does not support the request capability. | |
614 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
615 | * which has a Hypertransport capability matching @ht_cap. | |
616 | */ | |
617 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
618 | { | |
619 | int pos; | |
620 | ||
621 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
622 | if (pos) | |
623 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
624 | ||
625 | return pos; | |
626 | } | |
627 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
628 | ||
1da177e4 | 629 | /** |
74356add BH |
630 | * pci_find_parent_resource - return resource region of parent bus of given |
631 | * region | |
1da177e4 LT |
632 | * @dev: PCI device structure contains resources to be searched |
633 | * @res: child resource record for which parent is sought | |
634 | * | |
74356add BH |
635 | * For given resource region of given device, return the resource region of |
636 | * parent bus the given region is contained in. | |
1da177e4 | 637 | */ |
3c78bc61 RD |
638 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
639 | struct resource *res) | |
1da177e4 LT |
640 | { |
641 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 642 | struct resource *r; |
1da177e4 | 643 | int i; |
1da177e4 | 644 | |
89a74ecc | 645 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
646 | if (!r) |
647 | continue; | |
31342330 | 648 | if (resource_contains(r, res)) { |
f44116ae BH |
649 | |
650 | /* | |
651 | * If the window is prefetchable but the BAR is | |
652 | * not, the allocator made a mistake. | |
653 | */ | |
654 | if (r->flags & IORESOURCE_PREFETCH && | |
655 | !(res->flags & IORESOURCE_PREFETCH)) | |
656 | return NULL; | |
657 | ||
658 | /* | |
659 | * If we're below a transparent bridge, there may | |
660 | * be both a positively-decoded aperture and a | |
661 | * subtractively-decoded region that contain the BAR. | |
662 | * We want the positively-decoded one, so this depends | |
663 | * on pci_bus_for_each_resource() giving us those | |
664 | * first. | |
665 | */ | |
666 | return r; | |
667 | } | |
1da177e4 | 668 | } |
f44116ae | 669 | return NULL; |
1da177e4 | 670 | } |
b7fe9434 | 671 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 672 | |
afd29f90 MW |
673 | /** |
674 | * pci_find_resource - Return matching PCI device resource | |
675 | * @dev: PCI device to query | |
676 | * @res: Resource to look for | |
677 | * | |
678 | * Goes over standard PCI resources (BARs) and checks if the given resource | |
679 | * is partially or fully contained in any of them. In that case the | |
680 | * matching resource is returned, %NULL otherwise. | |
681 | */ | |
682 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) | |
683 | { | |
684 | int i; | |
685 | ||
c9c13ba4 | 686 | for (i = 0; i < PCI_STD_NUM_BARS; i++) { |
afd29f90 MW |
687 | struct resource *r = &dev->resource[i]; |
688 | ||
689 | if (r->start && resource_contains(r, res)) | |
690 | return r; | |
691 | } | |
692 | ||
693 | return NULL; | |
694 | } | |
695 | EXPORT_SYMBOL(pci_find_resource); | |
696 | ||
c56d4450 HS |
697 | /** |
698 | * pci_find_pcie_root_port - return PCIe Root Port | |
699 | * @dev: PCI device to query | |
700 | * | |
701 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
702 | * for a given PCI Device. | |
703 | */ | |
704 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) | |
705 | { | |
b6f6d56c | 706 | struct pci_dev *bridge, *highest_pcie_bridge = dev; |
c56d4450 HS |
707 | |
708 | bridge = pci_upstream_bridge(dev); | |
709 | while (bridge && pci_is_pcie(bridge)) { | |
710 | highest_pcie_bridge = bridge; | |
711 | bridge = pci_upstream_bridge(bridge); | |
712 | } | |
713 | ||
b6f6d56c TR |
714 | if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) |
715 | return NULL; | |
c56d4450 | 716 | |
b6f6d56c | 717 | return highest_pcie_bridge; |
c56d4450 HS |
718 | } |
719 | EXPORT_SYMBOL(pci_find_pcie_root_port); | |
720 | ||
157e876f AW |
721 | /** |
722 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
723 | * @dev: the PCI device to operate on | |
724 | * @pos: config space offset of status word | |
725 | * @mask: mask of bit(s) to care about in status word | |
726 | * | |
727 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
728 | */ | |
729 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
730 | { | |
731 | int i; | |
732 | ||
733 | /* Wait for Transaction Pending bit clean */ | |
734 | for (i = 0; i < 4; i++) { | |
735 | u16 status; | |
736 | if (i) | |
737 | msleep((1 << (i - 1)) * 100); | |
738 | ||
739 | pci_read_config_word(dev, pos, &status); | |
740 | if (!(status & mask)) | |
741 | return 1; | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
064b53db | 747 | /** |
70675e0b | 748 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
749 | * @dev: PCI device to have its BARs restored |
750 | * | |
751 | * Restore the BAR values for a given device, so as to make it | |
752 | * accessible by its driver. | |
753 | */ | |
3c78bc61 | 754 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 755 | { |
bc5f5a82 | 756 | int i; |
064b53db | 757 | |
bc5f5a82 | 758 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 759 | pci_update_resource(dev, i); |
064b53db JL |
760 | } |
761 | ||
299f2ffe | 762 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 763 | |
299f2ffe | 764 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 765 | { |
cc7cc02b | 766 | if (!ops->is_manageable || !ops->set_state || !ops->get_state || |
0847684c | 767 | !ops->choose_state || !ops->set_wakeup || !ops->need_resume) |
961d9120 RW |
768 | return -EINVAL; |
769 | pci_platform_pm = ops; | |
770 | return 0; | |
771 | } | |
772 | ||
773 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
774 | { | |
775 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
776 | } | |
777 | ||
778 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 779 | pci_power_t t) |
961d9120 RW |
780 | { |
781 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
782 | } | |
783 | ||
cc7cc02b LW |
784 | static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) |
785 | { | |
786 | return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; | |
787 | } | |
788 | ||
b51033e0 RW |
789 | static inline void platform_pci_refresh_power_state(struct pci_dev *dev) |
790 | { | |
791 | if (pci_platform_pm && pci_platform_pm->refresh_state) | |
792 | pci_platform_pm->refresh_state(dev); | |
793 | } | |
794 | ||
961d9120 RW |
795 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
796 | { | |
797 | return pci_platform_pm ? | |
798 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
799 | } | |
8f7020d3 | 800 | |
0847684c | 801 | static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
802 | { |
803 | return pci_platform_pm ? | |
0847684c | 804 | pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; |
b67ea761 RW |
805 | } |
806 | ||
bac2a909 RW |
807 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
808 | { | |
809 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
810 | } | |
811 | ||
26ad34d5 MW |
812 | static inline bool platform_pci_bridge_d3(struct pci_dev *dev) |
813 | { | |
814 | return pci_platform_pm ? pci_platform_pm->bridge_d3(dev) : false; | |
815 | } | |
816 | ||
1da177e4 | 817 | /** |
44e4e66e | 818 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
74356add | 819 | * given PCI device |
44e4e66e | 820 | * @dev: PCI device to handle. |
44e4e66e | 821 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 822 | * |
44e4e66e RW |
823 | * RETURN VALUE: |
824 | * -EINVAL if the requested state is invalid. | |
825 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
826 | * wrong version, or device doesn't support the requested state. | |
827 | * 0 if device already is in the requested state. | |
828 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 829 | */ |
f00a20ef | 830 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 831 | { |
337001b6 | 832 | u16 pmcsr; |
44e4e66e | 833 | bool need_restore = false; |
1da177e4 | 834 | |
4a865905 RW |
835 | /* Check if we're already there */ |
836 | if (dev->current_state == state) | |
837 | return 0; | |
838 | ||
337001b6 | 839 | if (!dev->pm_cap) |
cca03dec AL |
840 | return -EIO; |
841 | ||
44e4e66e RW |
842 | if (state < PCI_D0 || state > PCI_D3hot) |
843 | return -EINVAL; | |
844 | ||
74356add | 845 | /* |
e43f15ea BH |
846 | * Validate transition: We can enter D0 from any state, but if |
847 | * we're already in a low-power state, we can only go deeper. E.g., | |
848 | * we can go from D1 to D3, but we can't go directly from D3 to D1; | |
849 | * we'd have to go from D3 to D0, then to D1. | |
1da177e4 | 850 | */ |
4a865905 | 851 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 852 | && dev->current_state > state) { |
e43f15ea BH |
853 | pci_err(dev, "invalid power transition (from %s to %s)\n", |
854 | pci_power_name(dev->current_state), | |
855 | pci_power_name(state)); | |
1da177e4 | 856 | return -EINVAL; |
44e4e66e | 857 | } |
1da177e4 | 858 | |
74356add | 859 | /* Check if this device supports the desired state */ |
337001b6 RW |
860 | if ((state == PCI_D1 && !dev->d1_support) |
861 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 862 | return -EIO; |
1da177e4 | 863 | |
337001b6 | 864 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
327ccbbc BH |
865 | if (pmcsr == (u16) ~0) { |
866 | pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n", | |
867 | pci_power_name(dev->current_state), | |
868 | pci_power_name(state)); | |
869 | return -EIO; | |
870 | } | |
064b53db | 871 | |
74356add BH |
872 | /* |
873 | * If we're (effectively) in D3, force entire word to 0. | |
1da177e4 LT |
874 | * This doesn't affect PME_Status, disables PME_En, and |
875 | * sets PowerState to 0. | |
876 | */ | |
32a36585 | 877 | switch (dev->current_state) { |
d3535fbb JL |
878 | case PCI_D0: |
879 | case PCI_D1: | |
880 | case PCI_D2: | |
881 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
882 | pmcsr |= state; | |
883 | break; | |
f62795f1 RW |
884 | case PCI_D3hot: |
885 | case PCI_D3cold: | |
32a36585 JL |
886 | case PCI_UNKNOWN: /* Boot-up */ |
887 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 888 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 889 | need_restore = true; |
1d09d577 | 890 | /* Fall-through - force to D0 */ |
32a36585 | 891 | default: |
d3535fbb | 892 | pmcsr = 0; |
32a36585 | 893 | break; |
1da177e4 LT |
894 | } |
895 | ||
74356add | 896 | /* Enter specified state */ |
337001b6 | 897 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 | 898 | |
74356add BH |
899 | /* |
900 | * Mandatory power management transition delays; see PCI PM 1.1 | |
901 | * 5.6.1 table 18 | |
902 | */ | |
1da177e4 | 903 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
1ae861e6 | 904 | pci_dev_d3_sleep(dev); |
1da177e4 | 905 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
7e24bc34 | 906 | msleep(PCI_PM_D2_DELAY); |
1da177e4 | 907 | |
e13cdbd7 RW |
908 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
909 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
7f1c62c4 | 910 | if (dev->current_state != state) |
e43f15ea BH |
911 | pci_info_ratelimited(dev, "refused to change power state from %s to %s\n", |
912 | pci_power_name(dev->current_state), | |
913 | pci_power_name(state)); | |
064b53db | 914 | |
448bd857 HY |
915 | /* |
916 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
917 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
918 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
919 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
920 | * For example, at least some versions of the 3c905B and the | |
921 | * 3c556B exhibit this behaviour. | |
922 | * | |
923 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
924 | * devices in a D3hot state at boot. Consequently, we need to | |
925 | * restore at least the BARs so that the device will be | |
926 | * accessible to its driver. | |
927 | */ | |
928 | if (need_restore) | |
929 | pci_restore_bars(dev); | |
930 | ||
f00a20ef | 931 | if (dev->bus->self) |
7d715a6c SL |
932 | pcie_aspm_pm_state_change(dev->bus->self); |
933 | ||
1da177e4 LT |
934 | return 0; |
935 | } | |
936 | ||
44e4e66e | 937 | /** |
a6a64026 | 938 | * pci_update_current_state - Read power state of given device and cache it |
44e4e66e | 939 | * @dev: PCI device to handle. |
f06fc0b6 | 940 | * @state: State to cache in case the device doesn't have the PM capability |
a6a64026 LW |
941 | * |
942 | * The power state is read from the PMCSR register, which however is | |
943 | * inaccessible in D3cold. The platform firmware is therefore queried first | |
944 | * to detect accessibility of the register. In case the platform firmware | |
945 | * reports an incorrect state or the device isn't power manageable by the | |
946 | * platform at all, we try to detect D3cold by testing accessibility of the | |
947 | * vendor ID in config space. | |
44e4e66e | 948 | */ |
73410429 | 949 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 950 | { |
a6a64026 LW |
951 | if (platform_pci_get_power_state(dev) == PCI_D3cold || |
952 | !pci_device_is_present(dev)) { | |
953 | dev->current_state = PCI_D3cold; | |
954 | } else if (dev->pm_cap) { | |
44e4e66e RW |
955 | u16 pmcsr; |
956 | ||
337001b6 | 957 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 958 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
959 | } else { |
960 | dev->current_state = state; | |
44e4e66e RW |
961 | } |
962 | } | |
963 | ||
b51033e0 RW |
964 | /** |
965 | * pci_refresh_power_state - Refresh the given device's power state data | |
966 | * @dev: Target PCI device. | |
967 | * | |
968 | * Ask the platform to refresh the devices power state information and invoke | |
969 | * pci_update_current_state() to update its current PCI power state. | |
970 | */ | |
971 | void pci_refresh_power_state(struct pci_dev *dev) | |
972 | { | |
973 | if (platform_pci_power_manageable(dev)) | |
974 | platform_pci_refresh_power_state(dev); | |
975 | ||
976 | pci_update_current_state(dev, dev->current_state); | |
977 | } | |
978 | ||
0e5dd46b RW |
979 | /** |
980 | * pci_platform_power_transition - Use platform to change device power state | |
981 | * @dev: PCI device to handle. | |
982 | * @state: State to put the device into. | |
983 | */ | |
d6aa37cd | 984 | int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) |
0e5dd46b RW |
985 | { |
986 | int error; | |
987 | ||
988 | if (platform_pci_power_manageable(dev)) { | |
989 | error = platform_pci_set_power_state(dev, state); | |
990 | if (!error) | |
991 | pci_update_current_state(dev, state); | |
769ba721 | 992 | } else |
0e5dd46b | 993 | error = -ENODEV; |
769ba721 RW |
994 | |
995 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
996 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
997 | |
998 | return error; | |
999 | } | |
d6aa37cd | 1000 | EXPORT_SYMBOL_GPL(pci_platform_power_transition); |
0e5dd46b | 1001 | |
0b950f0f SH |
1002 | /** |
1003 | * pci_wakeup - Wake up a PCI device | |
1004 | * @pci_dev: Device to handle. | |
1005 | * @ign: ignored parameter | |
1006 | */ | |
1007 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
1008 | { | |
1009 | pci_wakeup_event(pci_dev); | |
1010 | pm_request_resume(&pci_dev->dev); | |
1011 | return 0; | |
1012 | } | |
1013 | ||
1014 | /** | |
1015 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
1016 | * @bus: Top bus of the subtree to walk. | |
1017 | */ | |
2a4d2c42 | 1018 | void pci_wakeup_bus(struct pci_bus *bus) |
0b950f0f SH |
1019 | { |
1020 | if (bus) | |
1021 | pci_walk_bus(bus, pci_wakeup, NULL); | |
1022 | } | |
1023 | ||
bae26849 VS |
1024 | static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) |
1025 | { | |
1026 | int delay = 1; | |
1027 | u32 id; | |
1028 | ||
1029 | /* | |
1030 | * After reset, the device should not silently discard config | |
1031 | * requests, but it may still indicate that it needs more time by | |
1032 | * responding to them with CRS completions. The Root Port will | |
1033 | * generally synthesize ~0 data to complete the read (except when | |
1034 | * CRS SV is enabled and the read was for the Vendor ID; in that | |
1035 | * case it synthesizes 0x0001 data). | |
1036 | * | |
1037 | * Wait for the device to return a non-CRS completion. Read the | |
1038 | * Command register instead of Vendor ID so we don't have to | |
1039 | * contend with the CRS SV value. | |
1040 | */ | |
1041 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
1042 | while (id == ~0) { | |
1043 | if (delay > timeout) { | |
1044 | pci_warn(dev, "not ready %dms after %s; giving up\n", | |
1045 | delay - 1, reset_type); | |
1046 | return -ENOTTY; | |
1047 | } | |
1048 | ||
1049 | if (delay > 1000) | |
1050 | pci_info(dev, "not ready %dms after %s; waiting\n", | |
1051 | delay - 1, reset_type); | |
1052 | ||
1053 | msleep(delay); | |
1054 | delay *= 2; | |
1055 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
1056 | } | |
1057 | ||
1058 | if (delay > 1000) | |
1059 | pci_info(dev, "ready %dms after %s\n", delay - 1, | |
1060 | reset_type); | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
0e5dd46b | 1065 | /** |
dc2256b0 RW |
1066 | * pci_power_up - Put the given device into D0 |
1067 | * @dev: PCI device to power up | |
0e5dd46b | 1068 | */ |
dc2256b0 | 1069 | int pci_power_up(struct pci_dev *dev) |
0e5dd46b | 1070 | { |
dc2256b0 RW |
1071 | pci_platform_power_transition(dev, PCI_D0); |
1072 | ||
1073 | /* | |
ad9001f2 MW |
1074 | * Mandatory power management transition delays are handled in |
1075 | * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the | |
1076 | * corresponding bridge. | |
dc2256b0 RW |
1077 | */ |
1078 | if (dev->runtime_d3cold) { | |
448bd857 | 1079 | /* |
dc2256b0 RW |
1080 | * When powering on a bridge from D3cold, the whole hierarchy |
1081 | * may be powered on into D0uninitialized state, resume them to | |
1082 | * give them a chance to suspend again | |
448bd857 | 1083 | */ |
dc2256b0 | 1084 | pci_wakeup_bus(dev->subordinate); |
448bd857 | 1085 | } |
448bd857 | 1086 | |
adfac8f6 | 1087 | return pci_raw_set_power_state(dev, PCI_D0); |
448bd857 HY |
1088 | } |
1089 | ||
1090 | /** | |
1091 | * __pci_dev_set_current_state - Set current state of a PCI device | |
1092 | * @dev: Device to handle | |
1093 | * @data: pointer to state to be set | |
1094 | */ | |
1095 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
1096 | { | |
1097 | pci_power_t state = *(pci_power_t *)data; | |
1098 | ||
1099 | dev->current_state = state; | |
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | /** | |
2a4d2c42 | 1104 | * pci_bus_set_current_state - Walk given bus and set current state of devices |
448bd857 HY |
1105 | * @bus: Top bus of the subtree to walk. |
1106 | * @state: state to be set | |
1107 | */ | |
2a4d2c42 | 1108 | void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) |
448bd857 HY |
1109 | { |
1110 | if (bus) | |
1111 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
1112 | } |
1113 | ||
44e4e66e RW |
1114 | /** |
1115 | * pci_set_power_state - Set the power state of a PCI device | |
1116 | * @dev: PCI device to handle. | |
1117 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
1118 | * | |
877d0310 | 1119 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
1120 | * the device's PCI PM registers. |
1121 | * | |
1122 | * RETURN VALUE: | |
1123 | * -EINVAL if the requested state is invalid. | |
1124 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
1125 | * wrong version, or device doesn't support the requested state. | |
ab4b8a47 | 1126 | * 0 if the transition is to D1 or D2 but D1 and D2 are not supported. |
44e4e66e | 1127 | * 0 if device already is in the requested state. |
ab4b8a47 | 1128 | * 0 if the transition is to D3 but D3 is not supported. |
44e4e66e RW |
1129 | * 0 if device's power state has been successfully changed. |
1130 | */ | |
1131 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
1132 | { | |
337001b6 | 1133 | int error; |
44e4e66e | 1134 | |
74356add | 1135 | /* Bound the state we're entering */ |
448bd857 HY |
1136 | if (state > PCI_D3cold) |
1137 | state = PCI_D3cold; | |
44e4e66e RW |
1138 | else if (state < PCI_D0) |
1139 | state = PCI_D0; | |
1140 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
74356add | 1141 | |
44e4e66e | 1142 | /* |
74356add BH |
1143 | * If the device or the parent bridge do not support PCI |
1144 | * PM, ignore the request if we're doing anything other | |
1145 | * than putting it into D0 (which would only happen on | |
1146 | * boot). | |
44e4e66e RW |
1147 | */ |
1148 | return 0; | |
1149 | ||
db288c9c RW |
1150 | /* Check if we're already there */ |
1151 | if (dev->current_state == state) | |
1152 | return 0; | |
1153 | ||
adfac8f6 RW |
1154 | if (state == PCI_D0) |
1155 | return pci_power_up(dev); | |
0e5dd46b | 1156 | |
74356add BH |
1157 | /* |
1158 | * This device is quirked not to be put into D3, so don't put it in | |
1159 | * D3 | |
1160 | */ | |
448bd857 | 1161 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 1162 | return 0; |
44e4e66e | 1163 | |
448bd857 HY |
1164 | /* |
1165 | * To put device in D3cold, we put device into D3hot in native | |
1166 | * way, then put device into D3cold with platform ops | |
1167 | */ | |
1168 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
1169 | PCI_D3hot : state); | |
44e4e66e | 1170 | |
9c77e63b RW |
1171 | if (pci_platform_power_transition(dev, state)) |
1172 | return error; | |
44e4e66e | 1173 | |
9c77e63b RW |
1174 | /* Powering off a bridge may power off the whole hierarchy */ |
1175 | if (state == PCI_D3cold) | |
1176 | pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
44e4e66e | 1177 | |
9c77e63b | 1178 | return 0; |
45144d42 | 1179 | } |
b7fe9434 | 1180 | EXPORT_SYMBOL(pci_set_power_state); |
45144d42 | 1181 | |
1da177e4 LT |
1182 | /** |
1183 | * pci_choose_state - Choose the power state of a PCI device | |
1184 | * @dev: PCI device to be suspended | |
1185 | * @state: target sleep state for the whole system. This is the value | |
74356add | 1186 | * that is passed to suspend() function. |
1da177e4 LT |
1187 | * |
1188 | * Returns PCI power state suitable for given device and given system | |
1189 | * message. | |
1190 | */ | |
1da177e4 LT |
1191 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) |
1192 | { | |
ab826ca4 | 1193 | pci_power_t ret; |
0f64474b | 1194 | |
728cdb75 | 1195 | if (!dev->pm_cap) |
1da177e4 LT |
1196 | return PCI_D0; |
1197 | ||
961d9120 RW |
1198 | ret = platform_pci_choose_state(dev); |
1199 | if (ret != PCI_POWER_ERROR) | |
1200 | return ret; | |
ca078bae PM |
1201 | |
1202 | switch (state.event) { | |
1203 | case PM_EVENT_ON: | |
1204 | return PCI_D0; | |
1205 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
1206 | case PM_EVENT_PRETHAW: |
1207 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 1208 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 1209 | case PM_EVENT_HIBERNATE: |
ca078bae | 1210 | return PCI_D3hot; |
1da177e4 | 1211 | default: |
7506dc79 | 1212 | pci_info(dev, "unrecognized suspend event %d\n", |
80ccba11 | 1213 | state.event); |
1da177e4 LT |
1214 | BUG(); |
1215 | } | |
1216 | return PCI_D0; | |
1217 | } | |
1da177e4 LT |
1218 | EXPORT_SYMBOL(pci_choose_state); |
1219 | ||
89858517 YZ |
1220 | #define PCI_EXP_SAVE_REGS 7 |
1221 | ||
fd0f7f73 AW |
1222 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
1223 | u16 cap, bool extended) | |
34a4876e YL |
1224 | { |
1225 | struct pci_cap_saved_state *tmp; | |
34a4876e | 1226 | |
b67bfe0d | 1227 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 1228 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
1229 | return tmp; |
1230 | } | |
1231 | return NULL; | |
1232 | } | |
1233 | ||
fd0f7f73 AW |
1234 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
1235 | { | |
1236 | return _pci_find_saved_cap(dev, cap, false); | |
1237 | } | |
1238 | ||
1239 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
1240 | { | |
1241 | return _pci_find_saved_cap(dev, cap, true); | |
1242 | } | |
1243 | ||
b56a5a23 MT |
1244 | static int pci_save_pcie_state(struct pci_dev *dev) |
1245 | { | |
59875ae4 | 1246 | int i = 0; |
b56a5a23 MT |
1247 | struct pci_cap_saved_state *save_state; |
1248 | u16 *cap; | |
1249 | ||
59875ae4 | 1250 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
1251 | return 0; |
1252 | ||
9f35575d | 1253 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 1254 | if (!save_state) { |
7506dc79 | 1255 | pci_err(dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
1256 | return -ENOMEM; |
1257 | } | |
63f4898a | 1258 | |
59875ae4 JL |
1259 | cap = (u16 *)&save_state->cap.data[0]; |
1260 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
1261 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1262 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1263 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1264 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1265 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1266 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1267 | |
b56a5a23 MT |
1268 | return 0; |
1269 | } | |
1270 | ||
1271 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
1272 | { | |
59875ae4 | 1273 | int i = 0; |
b56a5a23 MT |
1274 | struct pci_cap_saved_state *save_state; |
1275 | u16 *cap; | |
1276 | ||
1277 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1278 | if (!save_state) |
9cb604ed MS |
1279 | return; |
1280 | ||
59875ae4 JL |
1281 | cap = (u16 *)&save_state->cap.data[0]; |
1282 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1283 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1284 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1285 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1286 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1287 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1288 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1289 | } |
1290 | ||
cc692a5f SH |
1291 | static int pci_save_pcix_state(struct pci_dev *dev) |
1292 | { | |
63f4898a | 1293 | int pos; |
cc692a5f | 1294 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1295 | |
1296 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1297 | if (!pos) |
cc692a5f SH |
1298 | return 0; |
1299 | ||
f34303de | 1300 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1301 | if (!save_state) { |
7506dc79 | 1302 | pci_err(dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1303 | return -ENOMEM; |
1304 | } | |
cc692a5f | 1305 | |
24a4742f AW |
1306 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1307 | (u16 *)save_state->cap.data); | |
63f4898a | 1308 | |
cc692a5f SH |
1309 | return 0; |
1310 | } | |
1311 | ||
1312 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1313 | { | |
1314 | int i = 0, pos; | |
1315 | struct pci_cap_saved_state *save_state; | |
1316 | u16 *cap; | |
1317 | ||
1318 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1319 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1320 | if (!save_state || !pos) |
cc692a5f | 1321 | return; |
24a4742f | 1322 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1323 | |
1324 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1325 | } |
1326 | ||
dbbfadf2 BH |
1327 | static void pci_save_ltr_state(struct pci_dev *dev) |
1328 | { | |
1329 | int ltr; | |
1330 | struct pci_cap_saved_state *save_state; | |
1331 | u16 *cap; | |
1332 | ||
1333 | if (!pci_is_pcie(dev)) | |
1334 | return; | |
1335 | ||
1336 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1337 | if (!ltr) | |
1338 | return; | |
1339 | ||
1340 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1341 | if (!save_state) { | |
1342 | pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n"); | |
1343 | return; | |
1344 | } | |
1345 | ||
1346 | cap = (u16 *)&save_state->cap.data[0]; | |
1347 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++); | |
1348 | pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++); | |
1349 | } | |
1350 | ||
1351 | static void pci_restore_ltr_state(struct pci_dev *dev) | |
1352 | { | |
1353 | struct pci_cap_saved_state *save_state; | |
1354 | int ltr; | |
1355 | u16 *cap; | |
1356 | ||
1357 | save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR); | |
1358 | ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR); | |
1359 | if (!save_state || !ltr) | |
1360 | return; | |
1361 | ||
1362 | cap = (u16 *)&save_state->cap.data[0]; | |
1363 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++); | |
1364 | pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++); | |
1365 | } | |
cc692a5f | 1366 | |
1da177e4 | 1367 | /** |
74356add BH |
1368 | * pci_save_state - save the PCI configuration space of a device before |
1369 | * suspending | |
1370 | * @dev: PCI device that we're dealing with | |
1da177e4 | 1371 | */ |
3c78bc61 | 1372 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1373 | { |
1374 | int i; | |
1375 | /* XXX: 100% dword access ok here? */ | |
47b802d5 | 1376 | for (i = 0; i < 16; i++) { |
9e0b5b2c | 1377 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
47b802d5 CY |
1378 | pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n", |
1379 | i * 4, dev->saved_config_space[i]); | |
1380 | } | |
aa8c6c93 | 1381 | dev->state_saved = true; |
79e50e72 QL |
1382 | |
1383 | i = pci_save_pcie_state(dev); | |
1384 | if (i != 0) | |
b56a5a23 | 1385 | return i; |
79e50e72 QL |
1386 | |
1387 | i = pci_save_pcix_state(dev); | |
1388 | if (i != 0) | |
cc692a5f | 1389 | return i; |
79e50e72 | 1390 | |
dbbfadf2 | 1391 | pci_save_ltr_state(dev); |
4f802170 | 1392 | pci_save_dpc_state(dev); |
af65d1ad | 1393 | pci_save_aer_state(dev); |
754834b9 | 1394 | return pci_save_vc_state(dev); |
1da177e4 | 1395 | } |
b7fe9434 | 1396 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1397 | |
ebfc5b80 | 1398 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
08387454 | 1399 | u32 saved_val, int retry, bool force) |
ebfc5b80 RW |
1400 | { |
1401 | u32 val; | |
1402 | ||
1403 | pci_read_config_dword(pdev, offset, &val); | |
08387454 | 1404 | if (!force && val == saved_val) |
ebfc5b80 RW |
1405 | return; |
1406 | ||
1407 | for (;;) { | |
7506dc79 | 1408 | pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
227f0647 | 1409 | offset, val, saved_val); |
ebfc5b80 RW |
1410 | pci_write_config_dword(pdev, offset, saved_val); |
1411 | if (retry-- <= 0) | |
1412 | return; | |
1413 | ||
1414 | pci_read_config_dword(pdev, offset, &val); | |
1415 | if (val == saved_val) | |
1416 | return; | |
1417 | ||
1418 | mdelay(1); | |
1419 | } | |
1420 | } | |
1421 | ||
a6cb9ee7 | 1422 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
08387454 DD |
1423 | int start, int end, int retry, |
1424 | bool force) | |
ebfc5b80 RW |
1425 | { |
1426 | int index; | |
1427 | ||
1428 | for (index = end; index >= start; index--) | |
1429 | pci_restore_config_dword(pdev, 4 * index, | |
1430 | pdev->saved_config_space[index], | |
08387454 | 1431 | retry, force); |
ebfc5b80 RW |
1432 | } |
1433 | ||
a6cb9ee7 RW |
1434 | static void pci_restore_config_space(struct pci_dev *pdev) |
1435 | { | |
1436 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
08387454 | 1437 | pci_restore_config_space_range(pdev, 10, 15, 0, false); |
a6cb9ee7 | 1438 | /* Restore BARs before the command register. */ |
08387454 DD |
1439 | pci_restore_config_space_range(pdev, 4, 9, 10, false); |
1440 | pci_restore_config_space_range(pdev, 0, 3, 0, false); | |
1441 | } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1442 | pci_restore_config_space_range(pdev, 12, 15, 0, false); | |
1443 | ||
1444 | /* | |
1445 | * Force rewriting of prefetch registers to avoid S3 resume | |
1446 | * issues on Intel PCI bridges that occur when these | |
1447 | * registers are not explicitly written. | |
1448 | */ | |
1449 | pci_restore_config_space_range(pdev, 9, 11, 0, true); | |
1450 | pci_restore_config_space_range(pdev, 0, 8, 0, false); | |
a6cb9ee7 | 1451 | } else { |
08387454 | 1452 | pci_restore_config_space_range(pdev, 0, 15, 0, false); |
a6cb9ee7 RW |
1453 | } |
1454 | } | |
1455 | ||
d3252ace CK |
1456 | static void pci_restore_rebar_state(struct pci_dev *pdev) |
1457 | { | |
1458 | unsigned int pos, nbars, i; | |
1459 | u32 ctrl; | |
1460 | ||
1461 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
1462 | if (!pos) | |
1463 | return; | |
1464 | ||
1465 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1466 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
1467 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
1468 | ||
1469 | for (i = 0; i < nbars; i++, pos += 8) { | |
1470 | struct resource *res; | |
1471 | int bar_idx, size; | |
1472 | ||
1473 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
1474 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
1475 | res = pdev->resource + bar_idx; | |
d2182b2d | 1476 | size = ilog2(resource_size(res)) - 20; |
d3252ace | 1477 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; |
b1277a22 | 1478 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
d3252ace CK |
1479 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
1480 | } | |
1481 | } | |
1482 | ||
f7625980 | 1483 | /** |
1da177e4 | 1484 | * pci_restore_state - Restore the saved state of a PCI device |
74356add | 1485 | * @dev: PCI device that we're dealing with |
1da177e4 | 1486 | */ |
1d3c16a8 | 1487 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1488 | { |
c82f63e4 | 1489 | if (!dev->state_saved) |
1d3c16a8 | 1490 | return; |
4b77b0a2 | 1491 | |
dbbfadf2 BH |
1492 | /* |
1493 | * Restore max latencies (in the LTR capability) before enabling | |
1494 | * LTR itself (in the PCIe capability). | |
1495 | */ | |
1496 | pci_restore_ltr_state(dev); | |
1497 | ||
b56a5a23 | 1498 | pci_restore_pcie_state(dev); |
4ebeb1ec CT |
1499 | pci_restore_pasid_state(dev); |
1500 | pci_restore_pri_state(dev); | |
1900ca13 | 1501 | pci_restore_ats_state(dev); |
425c1b22 | 1502 | pci_restore_vc_state(dev); |
d3252ace | 1503 | pci_restore_rebar_state(dev); |
4f802170 | 1504 | pci_restore_dpc_state(dev); |
b56a5a23 | 1505 | |
b07461a8 | 1506 | pci_cleanup_aer_error_status_regs(dev); |
af65d1ad | 1507 | pci_restore_aer_state(dev); |
b07461a8 | 1508 | |
a6cb9ee7 | 1509 | pci_restore_config_space(dev); |
ebfc5b80 | 1510 | |
cc692a5f | 1511 | pci_restore_pcix_state(dev); |
41017f0c | 1512 | pci_restore_msi_state(dev); |
ccbc175a AD |
1513 | |
1514 | /* Restore ACS and IOV configuration state */ | |
1515 | pci_enable_acs(dev); | |
8c5cdb6a | 1516 | pci_restore_iov_state(dev); |
8fed4b65 | 1517 | |
4b77b0a2 | 1518 | dev->state_saved = false; |
1da177e4 | 1519 | } |
b7fe9434 | 1520 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1521 | |
ffbdd3f7 AW |
1522 | struct pci_saved_state { |
1523 | u32 config_space[16]; | |
1524 | struct pci_cap_saved_data cap[0]; | |
1525 | }; | |
1526 | ||
1527 | /** | |
1528 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1529 | * the device saved state. | |
1530 | * @dev: PCI device that we're dealing with | |
1531 | * | |
f7625980 | 1532 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1533 | */ |
1534 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1535 | { | |
1536 | struct pci_saved_state *state; | |
1537 | struct pci_cap_saved_state *tmp; | |
1538 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1539 | size_t size; |
1540 | ||
1541 | if (!dev->state_saved) | |
1542 | return NULL; | |
1543 | ||
1544 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1545 | ||
b67bfe0d | 1546 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1547 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1548 | ||
1549 | state = kzalloc(size, GFP_KERNEL); | |
1550 | if (!state) | |
1551 | return NULL; | |
1552 | ||
1553 | memcpy(state->config_space, dev->saved_config_space, | |
1554 | sizeof(state->config_space)); | |
1555 | ||
1556 | cap = state->cap; | |
b67bfe0d | 1557 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1558 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1559 | memcpy(cap, &tmp->cap, len); | |
1560 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1561 | } | |
1562 | /* Empty cap_save terminates list */ | |
1563 | ||
1564 | return state; | |
1565 | } | |
1566 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1567 | ||
1568 | /** | |
1569 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1570 | * @dev: PCI device that we're dealing with | |
1571 | * @state: Saved state returned from pci_store_saved_state() | |
1572 | */ | |
98d9b271 KRW |
1573 | int pci_load_saved_state(struct pci_dev *dev, |
1574 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1575 | { |
1576 | struct pci_cap_saved_data *cap; | |
1577 | ||
1578 | dev->state_saved = false; | |
1579 | ||
1580 | if (!state) | |
1581 | return 0; | |
1582 | ||
1583 | memcpy(dev->saved_config_space, state->config_space, | |
1584 | sizeof(state->config_space)); | |
1585 | ||
1586 | cap = state->cap; | |
1587 | while (cap->size) { | |
1588 | struct pci_cap_saved_state *tmp; | |
1589 | ||
fd0f7f73 | 1590 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1591 | if (!tmp || tmp->cap.size != cap->size) |
1592 | return -EINVAL; | |
1593 | ||
1594 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1595 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1596 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1597 | } | |
1598 | ||
1599 | dev->state_saved = true; | |
1600 | return 0; | |
1601 | } | |
98d9b271 | 1602 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1603 | |
1604 | /** | |
1605 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1606 | * and free the memory allocated for it. | |
1607 | * @dev: PCI device that we're dealing with | |
1608 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1609 | */ | |
1610 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1611 | struct pci_saved_state **state) | |
1612 | { | |
1613 | int ret = pci_load_saved_state(dev, *state); | |
1614 | kfree(*state); | |
1615 | *state = NULL; | |
1616 | return ret; | |
1617 | } | |
1618 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1619 | ||
8a9d5609 BH |
1620 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1621 | { | |
1622 | return pci_enable_resources(dev, bars); | |
1623 | } | |
1624 | ||
38cc1302 HS |
1625 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1626 | { | |
1627 | int err; | |
1f6ae47e | 1628 | struct pci_dev *bridge; |
1e2571a7 BH |
1629 | u16 cmd; |
1630 | u8 pin; | |
38cc1302 HS |
1631 | |
1632 | err = pci_set_power_state(dev, PCI_D0); | |
1633 | if (err < 0 && err != -EIO) | |
1634 | return err; | |
1f6ae47e VS |
1635 | |
1636 | bridge = pci_upstream_bridge(dev); | |
1637 | if (bridge) | |
1638 | pcie_aspm_powersave_config_link(bridge); | |
1639 | ||
38cc1302 HS |
1640 | err = pcibios_enable_device(dev, bars); |
1641 | if (err < 0) | |
1642 | return err; | |
1643 | pci_fixup_device(pci_fixup_enable, dev); | |
1644 | ||
866d5417 BH |
1645 | if (dev->msi_enabled || dev->msix_enabled) |
1646 | return 0; | |
1647 | ||
1e2571a7 BH |
1648 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1649 | if (pin) { | |
1650 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1651 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1652 | pci_write_config_word(dev, PCI_COMMAND, | |
1653 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1654 | } | |
1655 | ||
38cc1302 HS |
1656 | return 0; |
1657 | } | |
1658 | ||
1659 | /** | |
0b62e13b | 1660 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1661 | * @dev: PCI device to be resumed |
1662 | * | |
74356add BH |
1663 | * NOTE: This function is a backend of pci_default_resume() and is not supposed |
1664 | * to be called by normal code, write proper resume handler and use it instead. | |
38cc1302 | 1665 | */ |
0b62e13b | 1666 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1667 | { |
296ccb08 | 1668 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1669 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1670 | return 0; | |
1671 | } | |
b7fe9434 | 1672 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1673 | |
928bea96 YL |
1674 | static void pci_enable_bridge(struct pci_dev *dev) |
1675 | { | |
79272138 | 1676 | struct pci_dev *bridge; |
928bea96 YL |
1677 | int retval; |
1678 | ||
79272138 BH |
1679 | bridge = pci_upstream_bridge(dev); |
1680 | if (bridge) | |
1681 | pci_enable_bridge(bridge); | |
928bea96 | 1682 | |
cf3e1feb | 1683 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1684 | if (!dev->is_busmaster) |
cf3e1feb | 1685 | pci_set_master(dev); |
0f50a49e | 1686 | return; |
cf3e1feb YL |
1687 | } |
1688 | ||
928bea96 YL |
1689 | retval = pci_enable_device(dev); |
1690 | if (retval) | |
7506dc79 | 1691 | pci_err(dev, "Error enabling bridge (%d), continuing\n", |
928bea96 YL |
1692 | retval); |
1693 | pci_set_master(dev); | |
1694 | } | |
1695 | ||
b4b4fbba | 1696 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1697 | { |
79272138 | 1698 | struct pci_dev *bridge; |
1da177e4 | 1699 | int err; |
b718989d | 1700 | int i, bars = 0; |
1da177e4 | 1701 | |
97c145f7 JB |
1702 | /* |
1703 | * Power state could be unknown at this point, either due to a fresh | |
1704 | * boot or a device removal call. So get the current power state | |
1705 | * so that things like MSI message writing will behave as expected | |
1706 | * (e.g. if the device really is in D0 at enable time). | |
1707 | */ | |
1708 | if (dev->pm_cap) { | |
1709 | u16 pmcsr; | |
1710 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1711 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1712 | } | |
1713 | ||
cc7ba39b | 1714 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1715 | return 0; /* already enabled */ |
1716 | ||
79272138 | 1717 | bridge = pci_upstream_bridge(dev); |
0f50a49e | 1718 | if (bridge) |
79272138 | 1719 | pci_enable_bridge(bridge); |
928bea96 | 1720 | |
497f16f2 YL |
1721 | /* only skip sriov related */ |
1722 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1723 | if (dev->resource[i].flags & flags) | |
1724 | bars |= (1 << i); | |
1725 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1726 | if (dev->resource[i].flags & flags) |
1727 | bars |= (1 << i); | |
1728 | ||
38cc1302 | 1729 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1730 | if (err < 0) |
38cc1302 | 1731 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1732 | return err; |
1da177e4 LT |
1733 | } |
1734 | ||
b718989d BH |
1735 | /** |
1736 | * pci_enable_device_io - Initialize a device for use with IO space | |
1737 | * @dev: PCI device to be initialized | |
1738 | * | |
74356add BH |
1739 | * Initialize device before it's used by a driver. Ask low-level code |
1740 | * to enable I/O resources. Wake up the device if it was suspended. | |
1741 | * Beware, this function can fail. | |
b718989d BH |
1742 | */ |
1743 | int pci_enable_device_io(struct pci_dev *dev) | |
1744 | { | |
b4b4fbba | 1745 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1746 | } |
b7fe9434 | 1747 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1748 | |
1749 | /** | |
1750 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1751 | * @dev: PCI device to be initialized | |
1752 | * | |
74356add BH |
1753 | * Initialize device before it's used by a driver. Ask low-level code |
1754 | * to enable Memory resources. Wake up the device if it was suspended. | |
1755 | * Beware, this function can fail. | |
b718989d BH |
1756 | */ |
1757 | int pci_enable_device_mem(struct pci_dev *dev) | |
1758 | { | |
b4b4fbba | 1759 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1760 | } |
b7fe9434 | 1761 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1762 | |
bae94d02 IPG |
1763 | /** |
1764 | * pci_enable_device - Initialize device before it's used by a driver. | |
1765 | * @dev: PCI device to be initialized | |
1766 | * | |
74356add BH |
1767 | * Initialize device before it's used by a driver. Ask low-level code |
1768 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1769 | * Beware, this function can fail. | |
bae94d02 | 1770 | * |
74356add BH |
1771 | * Note we don't actually enable the device many times if we call |
1772 | * this function repeatedly (we just increment the count). | |
bae94d02 IPG |
1773 | */ |
1774 | int pci_enable_device(struct pci_dev *dev) | |
1775 | { | |
b4b4fbba | 1776 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1777 | } |
b7fe9434 | 1778 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1779 | |
9ac7849e | 1780 | /* |
74356add BH |
1781 | * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X |
1782 | * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so | |
9ac7849e TH |
1783 | * there's no need to track it separately. pci_devres is initialized |
1784 | * when a device is enabled using managed PCI device enable interface. | |
1785 | */ | |
1786 | struct pci_devres { | |
7f375f32 TH |
1787 | unsigned int enabled:1; |
1788 | unsigned int pinned:1; | |
9ac7849e TH |
1789 | unsigned int orig_intx:1; |
1790 | unsigned int restore_intx:1; | |
fc0f9f4d | 1791 | unsigned int mwi:1; |
9ac7849e TH |
1792 | u32 region_mask; |
1793 | }; | |
1794 | ||
1795 | static void pcim_release(struct device *gendev, void *res) | |
1796 | { | |
f3d2f165 | 1797 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
1798 | struct pci_devres *this = res; |
1799 | int i; | |
1800 | ||
1801 | if (dev->msi_enabled) | |
1802 | pci_disable_msi(dev); | |
1803 | if (dev->msix_enabled) | |
1804 | pci_disable_msix(dev); | |
1805 | ||
1806 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1807 | if (this->region_mask & (1 << i)) | |
1808 | pci_release_region(dev, i); | |
1809 | ||
fc0f9f4d HK |
1810 | if (this->mwi) |
1811 | pci_clear_mwi(dev); | |
1812 | ||
9ac7849e TH |
1813 | if (this->restore_intx) |
1814 | pci_intx(dev, this->orig_intx); | |
1815 | ||
7f375f32 | 1816 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1817 | pci_disable_device(dev); |
1818 | } | |
1819 | ||
07656d83 | 1820 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1821 | { |
1822 | struct pci_devres *dr, *new_dr; | |
1823 | ||
1824 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1825 | if (dr) | |
1826 | return dr; | |
1827 | ||
1828 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1829 | if (!new_dr) | |
1830 | return NULL; | |
1831 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1832 | } | |
1833 | ||
07656d83 | 1834 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1835 | { |
1836 | if (pci_is_managed(pdev)) | |
1837 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1838 | return NULL; | |
1839 | } | |
1840 | ||
1841 | /** | |
1842 | * pcim_enable_device - Managed pci_enable_device() | |
1843 | * @pdev: PCI device to be initialized | |
1844 | * | |
1845 | * Managed pci_enable_device(). | |
1846 | */ | |
1847 | int pcim_enable_device(struct pci_dev *pdev) | |
1848 | { | |
1849 | struct pci_devres *dr; | |
1850 | int rc; | |
1851 | ||
1852 | dr = get_pci_dr(pdev); | |
1853 | if (unlikely(!dr)) | |
1854 | return -ENOMEM; | |
b95d58ea TH |
1855 | if (dr->enabled) |
1856 | return 0; | |
9ac7849e TH |
1857 | |
1858 | rc = pci_enable_device(pdev); | |
1859 | if (!rc) { | |
1860 | pdev->is_managed = 1; | |
7f375f32 | 1861 | dr->enabled = 1; |
9ac7849e TH |
1862 | } |
1863 | return rc; | |
1864 | } | |
b7fe9434 | 1865 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1866 | |
1867 | /** | |
1868 | * pcim_pin_device - Pin managed PCI device | |
1869 | * @pdev: PCI device to pin | |
1870 | * | |
1871 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1872 | * driver detach. @pdev must have been enabled with | |
1873 | * pcim_enable_device(). | |
1874 | */ | |
1875 | void pcim_pin_device(struct pci_dev *pdev) | |
1876 | { | |
1877 | struct pci_devres *dr; | |
1878 | ||
1879 | dr = find_pci_dr(pdev); | |
7f375f32 | 1880 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1881 | if (dr) |
7f375f32 | 1882 | dr->pinned = 1; |
9ac7849e | 1883 | } |
b7fe9434 | 1884 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1885 | |
eca0d467 MG |
1886 | /* |
1887 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1888 | * @dev: the PCI device being added | |
1889 | * | |
1890 | * Permits the platform to provide architecture specific functionality when | |
1891 | * devices are added. This is the default implementation. Architecture | |
1892 | * implementations can override this. | |
1893 | */ | |
3c78bc61 | 1894 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
1895 | { |
1896 | return 0; | |
1897 | } | |
1898 | ||
6ae32c53 | 1899 | /** |
74356add BH |
1900 | * pcibios_release_device - provide arch specific hooks when releasing |
1901 | * device dev | |
6ae32c53 SO |
1902 | * @dev: the PCI device being released |
1903 | * | |
1904 | * Permits the platform to provide architecture specific functionality when | |
1905 | * devices are released. This is the default implementation. Architecture | |
1906 | * implementations can override this. | |
1907 | */ | |
1908 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1909 | ||
1da177e4 LT |
1910 | /** |
1911 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1912 | * @dev: the PCI device to disable | |
1913 | * | |
1914 | * Disables architecture specific PCI resources for the device. This | |
1915 | * is the default implementation. Architecture implementations can | |
1916 | * override this. | |
1917 | */ | |
ff3ce480 | 1918 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 1919 | |
a43ae58c HG |
1920 | /** |
1921 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1922 | * @irq: ISA IRQ to penalize | |
1923 | * @active: IRQ active or not | |
1924 | * | |
1925 | * Permits the platform to provide architecture-specific functionality when | |
1926 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1927 | * implementations can override this. | |
1928 | */ | |
1929 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1930 | ||
fa58d305 RW |
1931 | static void do_pci_disable_device(struct pci_dev *dev) |
1932 | { | |
1933 | u16 pci_command; | |
1934 | ||
1935 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1936 | if (pci_command & PCI_COMMAND_MASTER) { | |
1937 | pci_command &= ~PCI_COMMAND_MASTER; | |
1938 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1939 | } | |
1940 | ||
1941 | pcibios_disable_device(dev); | |
1942 | } | |
1943 | ||
1944 | /** | |
1945 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1946 | * @dev: PCI device to disable | |
1947 | * | |
1948 | * NOTE: This function is a backend of PCI power management routines and is | |
1949 | * not supposed to be called drivers. | |
1950 | */ | |
1951 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1952 | { | |
296ccb08 | 1953 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1954 | do_pci_disable_device(dev); |
1955 | } | |
1956 | ||
1da177e4 LT |
1957 | /** |
1958 | * pci_disable_device - Disable PCI device after use | |
1959 | * @dev: PCI device to be disabled | |
1960 | * | |
1961 | * Signal to the system that the PCI device is not in use by the system | |
1962 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1963 | * |
1964 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1965 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 1966 | */ |
3c78bc61 | 1967 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 1968 | { |
9ac7849e | 1969 | struct pci_devres *dr; |
99dc804d | 1970 | |
9ac7849e TH |
1971 | dr = find_pci_dr(dev); |
1972 | if (dr) | |
7f375f32 | 1973 | dr->enabled = 0; |
9ac7849e | 1974 | |
fd6dceab KK |
1975 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1976 | "disabling already-disabled device"); | |
1977 | ||
cc7ba39b | 1978 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1979 | return; |
1980 | ||
fa58d305 | 1981 | do_pci_disable_device(dev); |
1da177e4 | 1982 | |
fa58d305 | 1983 | dev->is_busmaster = 0; |
1da177e4 | 1984 | } |
b7fe9434 | 1985 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1986 | |
f7bdd12d BK |
1987 | /** |
1988 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1989 | * @dev: the PCIe device reset |
f7bdd12d BK |
1990 | * @state: Reset state to enter into |
1991 | * | |
74356add | 1992 | * Set the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1993 | * implementation. Architecture implementations can override this. |
1994 | */ | |
d6d88c83 BH |
1995 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1996 | enum pcie_reset_state state) | |
f7bdd12d BK |
1997 | { |
1998 | return -EINVAL; | |
1999 | } | |
2000 | ||
2001 | /** | |
2002 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 2003 | * @dev: the PCIe device reset |
f7bdd12d BK |
2004 | * @state: Reset state to enter into |
2005 | * | |
f7bdd12d BK |
2006 | * Sets the PCI reset state for the device. |
2007 | */ | |
2008 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
2009 | { | |
2010 | return pcibios_set_pcie_reset_state(dev, state); | |
2011 | } | |
b7fe9434 | 2012 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 2013 | |
dcb0453d BH |
2014 | /** |
2015 | * pcie_clear_root_pme_status - Clear root port PME interrupt status. | |
2016 | * @dev: PCIe root port or event collector. | |
2017 | */ | |
2018 | void pcie_clear_root_pme_status(struct pci_dev *dev) | |
2019 | { | |
2020 | pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME); | |
2021 | } | |
2022 | ||
58ff4633 RW |
2023 | /** |
2024 | * pci_check_pme_status - Check if given device has generated PME. | |
2025 | * @dev: Device to check. | |
2026 | * | |
2027 | * Check the PME status of the device and if set, clear it and clear PME enable | |
2028 | * (if set). Return 'true' if PME status and PME enable were both set or | |
2029 | * 'false' otherwise. | |
2030 | */ | |
2031 | bool pci_check_pme_status(struct pci_dev *dev) | |
2032 | { | |
2033 | int pmcsr_pos; | |
2034 | u16 pmcsr; | |
2035 | bool ret = false; | |
2036 | ||
2037 | if (!dev->pm_cap) | |
2038 | return false; | |
2039 | ||
2040 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
2041 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
2042 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
2043 | return false; | |
2044 | ||
2045 | /* Clear PME status. */ | |
2046 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2047 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
2048 | /* Disable PME to avoid interrupt flood. */ | |
2049 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2050 | ret = true; | |
2051 | } | |
2052 | ||
2053 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
2054 | ||
2055 | return ret; | |
2056 | } | |
2057 | ||
b67ea761 RW |
2058 | /** |
2059 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
2060 | * @dev: Device to handle. | |
379021d5 | 2061 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
2062 | * |
2063 | * Check if @dev has generated PME and queue a resume request for it in that | |
2064 | * case. | |
2065 | */ | |
379021d5 | 2066 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 2067 | { |
379021d5 RW |
2068 | if (pme_poll_reset && dev->pme_poll) |
2069 | dev->pme_poll = false; | |
2070 | ||
c125e96f | 2071 | if (pci_check_pme_status(dev)) { |
c125e96f | 2072 | pci_wakeup_event(dev); |
0f953bf6 | 2073 | pm_request_resume(&dev->dev); |
c125e96f | 2074 | } |
b67ea761 RW |
2075 | return 0; |
2076 | } | |
2077 | ||
2078 | /** | |
2079 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
2080 | * @bus: Top bus of the subtree to walk. | |
2081 | */ | |
2082 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
2083 | { | |
2084 | if (bus) | |
379021d5 | 2085 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
2086 | } |
2087 | ||
448bd857 | 2088 | |
eb9d0fe4 RW |
2089 | /** |
2090 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
2091 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
2092 | * @state: PCI state from which device will issue PME#. |
2093 | */ | |
e5899e1b | 2094 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 2095 | { |
337001b6 | 2096 | if (!dev->pm_cap) |
eb9d0fe4 RW |
2097 | return false; |
2098 | ||
337001b6 | 2099 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 2100 | } |
b7fe9434 | 2101 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 2102 | |
df17e62e MG |
2103 | static void pci_pme_list_scan(struct work_struct *work) |
2104 | { | |
379021d5 | 2105 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
2106 | |
2107 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
2108 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
2109 | if (pme_dev->dev->pme_poll) { | |
2110 | struct pci_dev *bridge; | |
2111 | ||
2112 | bridge = pme_dev->dev->bus->self; | |
2113 | /* | |
2114 | * If bridge is in low power state, the | |
2115 | * configuration space of subordinate devices | |
2116 | * may be not accessible | |
2117 | */ | |
2118 | if (bridge && bridge->current_state != PCI_D0) | |
2119 | continue; | |
000dd531 MW |
2120 | /* |
2121 | * If the device is in D3cold it should not be | |
2122 | * polled either. | |
2123 | */ | |
2124 | if (pme_dev->dev->current_state == PCI_D3cold) | |
2125 | continue; | |
2126 | ||
ce300008 BH |
2127 | pci_pme_wakeup(pme_dev->dev, NULL); |
2128 | } else { | |
2129 | list_del(&pme_dev->list); | |
2130 | kfree(pme_dev); | |
379021d5 | 2131 | } |
df17e62e | 2132 | } |
ce300008 | 2133 | if (!list_empty(&pci_pme_list)) |
ea00353f LW |
2134 | queue_delayed_work(system_freezable_wq, &pci_pme_work, |
2135 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2136 | mutex_unlock(&pci_pme_list_mutex); |
2137 | } | |
2138 | ||
2cef548a | 2139 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
2140 | { |
2141 | u16 pmcsr; | |
2142 | ||
ffaddbe8 | 2143 | if (!dev->pme_support) |
eb9d0fe4 RW |
2144 | return; |
2145 | ||
337001b6 | 2146 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
2147 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
2148 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
2149 | if (!enable) | |
2150 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2151 | ||
337001b6 | 2152 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
2153 | } |
2154 | ||
0ce3fcaf RW |
2155 | /** |
2156 | * pci_pme_restore - Restore PME configuration after config space restore. | |
2157 | * @dev: PCI device to update. | |
2158 | */ | |
2159 | void pci_pme_restore(struct pci_dev *dev) | |
dc15e71e RW |
2160 | { |
2161 | u16 pmcsr; | |
2162 | ||
2163 | if (!dev->pme_support) | |
2164 | return; | |
2165 | ||
2166 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
2167 | if (dev->wakeup_prepared) { | |
2168 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
0ce3fcaf | 2169 | pmcsr &= ~PCI_PM_CTRL_PME_STATUS; |
dc15e71e RW |
2170 | } else { |
2171 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
2172 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
2173 | } | |
2174 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); | |
2175 | } | |
2176 | ||
2cef548a RW |
2177 | /** |
2178 | * pci_pme_active - enable or disable PCI device's PME# function | |
2179 | * @dev: PCI device to handle. | |
2180 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
2181 | * | |
2182 | * The caller must verify that the device is capable of generating PME# before | |
2183 | * calling this function with @enable equal to 'true'. | |
2184 | */ | |
2185 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
2186 | { | |
2187 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 2188 | |
6e965e0d HY |
2189 | /* |
2190 | * PCI (as opposed to PCIe) PME requires that the device have | |
2191 | * its PME# line hooked up correctly. Not all hardware vendors | |
2192 | * do this, so the PME never gets delivered and the device | |
2193 | * remains asleep. The easiest way around this is to | |
2194 | * periodically walk the list of suspended devices and check | |
2195 | * whether any have their PME flag set. The assumption is that | |
2196 | * we'll wake up often enough anyway that this won't be a huge | |
2197 | * hit, and the power savings from the devices will still be a | |
2198 | * win. | |
2199 | * | |
2200 | * Although PCIe uses in-band PME message instead of PME# line | |
2201 | * to report PME, PME does not work for some PCIe devices in | |
2202 | * reality. For example, there are devices that set their PME | |
2203 | * status bits, but don't really bother to send a PME message; | |
2204 | * there are PCI Express Root Ports that don't bother to | |
2205 | * trigger interrupts when they receive PME messages from the | |
2206 | * devices below. So PME poll is used for PCIe devices too. | |
2207 | */ | |
df17e62e | 2208 | |
379021d5 | 2209 | if (dev->pme_poll) { |
df17e62e MG |
2210 | struct pci_pme_device *pme_dev; |
2211 | if (enable) { | |
2212 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
2213 | GFP_KERNEL); | |
0394cb19 | 2214 | if (!pme_dev) { |
7506dc79 | 2215 | pci_warn(dev, "can't enable PME#\n"); |
0394cb19 BH |
2216 | return; |
2217 | } | |
df17e62e MG |
2218 | pme_dev->dev = dev; |
2219 | mutex_lock(&pci_pme_list_mutex); | |
2220 | list_add(&pme_dev->list, &pci_pme_list); | |
2221 | if (list_is_singular(&pci_pme_list)) | |
ea00353f LW |
2222 | queue_delayed_work(system_freezable_wq, |
2223 | &pci_pme_work, | |
2224 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
2225 | mutex_unlock(&pci_pme_list_mutex); |
2226 | } else { | |
2227 | mutex_lock(&pci_pme_list_mutex); | |
2228 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
2229 | if (pme_dev->dev == dev) { | |
2230 | list_del(&pme_dev->list); | |
2231 | kfree(pme_dev); | |
2232 | break; | |
2233 | } | |
2234 | } | |
2235 | mutex_unlock(&pci_pme_list_mutex); | |
2236 | } | |
2237 | } | |
2238 | ||
7506dc79 | 2239 | pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 2240 | } |
b7fe9434 | 2241 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 2242 | |
1da177e4 | 2243 | /** |
cfcadfaa | 2244 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
2245 | * @dev: PCI device affected |
2246 | * @state: PCI state from which device will issue wakeup events | |
2247 | * @enable: True to enable event generation; false to disable | |
2248 | * | |
2249 | * This enables the device as a wakeup event source, or disables it. | |
2250 | * When such events involves platform-specific hooks, those hooks are | |
2251 | * called automatically by this routine. | |
2252 | * | |
2253 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 2254 | * always require such platform hooks. |
075c1771 | 2255 | * |
eb9d0fe4 RW |
2256 | * RETURN VALUE: |
2257 | * 0 is returned on success | |
2258 | * -EINVAL is returned if device is not supposed to wake up the system | |
2259 | * Error code depending on the platform is returned if both the platform and | |
2260 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 2261 | */ |
cfcadfaa | 2262 | static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1da177e4 | 2263 | { |
5bcc2fb4 | 2264 | int ret = 0; |
075c1771 | 2265 | |
baecc470 | 2266 | /* |
ac86e8ee MW |
2267 | * Bridges that are not power-manageable directly only signal |
2268 | * wakeup on behalf of subordinate devices which is set up | |
2269 | * elsewhere, so skip them. However, bridges that are | |
2270 | * power-manageable may signal wakeup for themselves (for example, | |
2271 | * on a hotplug event) and they need to be covered here. | |
baecc470 | 2272 | */ |
ac86e8ee | 2273 | if (!pci_power_manageable(dev)) |
baecc470 RW |
2274 | return 0; |
2275 | ||
0ce3fcaf RW |
2276 | /* Don't do the same thing twice in a row for one device. */ |
2277 | if (!!enable == !!dev->wakeup_prepared) | |
e80bb09d RW |
2278 | return 0; |
2279 | ||
eb9d0fe4 RW |
2280 | /* |
2281 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
2282 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
2283 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 2284 | */ |
1da177e4 | 2285 | |
5bcc2fb4 RW |
2286 | if (enable) { |
2287 | int error; | |
1da177e4 | 2288 | |
5bcc2fb4 RW |
2289 | if (pci_pme_capable(dev, state)) |
2290 | pci_pme_active(dev, true); | |
2291 | else | |
2292 | ret = 1; | |
0847684c | 2293 | error = platform_pci_set_wakeup(dev, true); |
5bcc2fb4 RW |
2294 | if (ret) |
2295 | ret = error; | |
e80bb09d RW |
2296 | if (!ret) |
2297 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 2298 | } else { |
0847684c | 2299 | platform_pci_set_wakeup(dev, false); |
5bcc2fb4 | 2300 | pci_pme_active(dev, false); |
e80bb09d | 2301 | dev->wakeup_prepared = false; |
5bcc2fb4 | 2302 | } |
1da177e4 | 2303 | |
5bcc2fb4 | 2304 | return ret; |
eb9d0fe4 | 2305 | } |
cfcadfaa RW |
2306 | |
2307 | /** | |
2308 | * pci_enable_wake - change wakeup settings for a PCI device | |
2309 | * @pci_dev: Target device | |
2310 | * @state: PCI state from which device will issue wakeup events | |
2311 | * @enable: Whether or not to enable event generation | |
2312 | * | |
2313 | * If @enable is set, check device_may_wakeup() for the device before calling | |
2314 | * __pci_enable_wake() for it. | |
2315 | */ | |
2316 | int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) | |
2317 | { | |
2318 | if (enable && !device_may_wakeup(&pci_dev->dev)) | |
2319 | return -EINVAL; | |
2320 | ||
2321 | return __pci_enable_wake(pci_dev, state, enable); | |
2322 | } | |
0847684c | 2323 | EXPORT_SYMBOL(pci_enable_wake); |
1da177e4 | 2324 | |
0235c4fc RW |
2325 | /** |
2326 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
2327 | * @dev: PCI device to prepare | |
2328 | * @enable: True to enable wake-up event generation; false to disable | |
2329 | * | |
2330 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
2331 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
2332 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
2333 | * ordering constraints. | |
2334 | * | |
cfcadfaa RW |
2335 | * This function only returns error code if the device is not allowed to wake |
2336 | * up the system from sleep or it is not capable of generating PME# from both | |
2337 | * D3_hot and D3_cold and the platform is unable to enable wake-up power for it. | |
0235c4fc RW |
2338 | */ |
2339 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
2340 | { | |
2341 | return pci_pme_capable(dev, PCI_D3cold) ? | |
2342 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
2343 | pci_enable_wake(dev, PCI_D3hot, enable); | |
2344 | } | |
b7fe9434 | 2345 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 2346 | |
404cc2d8 | 2347 | /** |
37139074 JB |
2348 | * pci_target_state - find an appropriate low power state for a given PCI dev |
2349 | * @dev: PCI device | |
666ff6f8 | 2350 | * @wakeup: Whether or not wakeup functionality will be enabled for the device. |
37139074 JB |
2351 | * |
2352 | * Use underlying platform code to find a supported low power state for @dev. | |
2353 | * If the platform can't manage @dev, return the deepest state from which it | |
2354 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 2355 | */ |
666ff6f8 | 2356 | static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) |
404cc2d8 RW |
2357 | { |
2358 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
2359 | |
2360 | if (platform_pci_power_manageable(dev)) { | |
2361 | /* | |
60ee031a | 2362 | * Call the platform to find the target state for the device. |
404cc2d8 RW |
2363 | */ |
2364 | pci_power_t state = platform_pci_choose_state(dev); | |
2365 | ||
2366 | switch (state) { | |
2367 | case PCI_POWER_ERROR: | |
2368 | case PCI_UNKNOWN: | |
2369 | break; | |
2370 | case PCI_D1: | |
2371 | case PCI_D2: | |
2372 | if (pci_no_d1d2(dev)) | |
2373 | break; | |
1d09d577 | 2374 | /* else, fall through */ |
404cc2d8 RW |
2375 | default: |
2376 | target_state = state; | |
404cc2d8 | 2377 | } |
4132a577 LW |
2378 | |
2379 | return target_state; | |
2380 | } | |
2381 | ||
2382 | if (!dev->pm_cap) | |
d2abdf62 | 2383 | target_state = PCI_D0; |
4132a577 LW |
2384 | |
2385 | /* | |
2386 | * If the device is in D3cold even though it's not power-manageable by | |
2387 | * the platform, it may have been powered down by non-standard means. | |
2388 | * Best to let it slumber. | |
2389 | */ | |
2390 | if (dev->current_state == PCI_D3cold) | |
2391 | target_state = PCI_D3cold; | |
2392 | ||
666ff6f8 | 2393 | if (wakeup) { |
404cc2d8 RW |
2394 | /* |
2395 | * Find the deepest state from which the device can generate | |
60ee031a | 2396 | * PME#. |
404cc2d8 | 2397 | */ |
337001b6 RW |
2398 | if (dev->pme_support) { |
2399 | while (target_state | |
2400 | && !(dev->pme_support & (1 << target_state))) | |
2401 | target_state--; | |
404cc2d8 RW |
2402 | } |
2403 | } | |
2404 | ||
e5899e1b RW |
2405 | return target_state; |
2406 | } | |
2407 | ||
2408 | /** | |
74356add BH |
2409 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition |
2410 | * into a sleep state | |
e5899e1b RW |
2411 | * @dev: Device to handle. |
2412 | * | |
2413 | * Choose the power state appropriate for the device depending on whether | |
2414 | * it can wake up the system and/or is power manageable by the platform | |
2415 | * (PCI_D3hot is the default) and put the device into that state. | |
2416 | */ | |
2417 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
2418 | { | |
666ff6f8 RW |
2419 | bool wakeup = device_may_wakeup(&dev->dev); |
2420 | pci_power_t target_state = pci_target_state(dev, wakeup); | |
e5899e1b RW |
2421 | int error; |
2422 | ||
2423 | if (target_state == PCI_POWER_ERROR) | |
2424 | return -EIO; | |
2425 | ||
666ff6f8 | 2426 | pci_enable_wake(dev, target_state, wakeup); |
c157dfa3 | 2427 | |
404cc2d8 RW |
2428 | error = pci_set_power_state(dev, target_state); |
2429 | ||
2430 | if (error) | |
2431 | pci_enable_wake(dev, target_state, false); | |
2432 | ||
2433 | return error; | |
2434 | } | |
b7fe9434 | 2435 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2436 | |
2437 | /** | |
74356add BH |
2438 | * pci_back_from_sleep - turn PCI device on during system-wide transition |
2439 | * into working state | |
404cc2d8 RW |
2440 | * @dev: Device to handle. |
2441 | * | |
88393161 | 2442 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2443 | */ |
2444 | int pci_back_from_sleep(struct pci_dev *dev) | |
2445 | { | |
2446 | pci_enable_wake(dev, PCI_D0, false); | |
2447 | return pci_set_power_state(dev, PCI_D0); | |
2448 | } | |
b7fe9434 | 2449 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2450 | |
6cbf8214 RW |
2451 | /** |
2452 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2453 | * @dev: PCI device being suspended. | |
2454 | * | |
2455 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2456 | * power state. | |
2457 | */ | |
2458 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2459 | { | |
666ff6f8 | 2460 | pci_power_t target_state; |
6cbf8214 RW |
2461 | int error; |
2462 | ||
666ff6f8 | 2463 | target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); |
6cbf8214 RW |
2464 | if (target_state == PCI_POWER_ERROR) |
2465 | return -EIO; | |
2466 | ||
448bd857 HY |
2467 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2468 | ||
cfcadfaa | 2469 | __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); |
6cbf8214 RW |
2470 | |
2471 | error = pci_set_power_state(dev, target_state); | |
2472 | ||
448bd857 | 2473 | if (error) { |
0847684c | 2474 | pci_enable_wake(dev, target_state, false); |
448bd857 HY |
2475 | dev->runtime_d3cold = false; |
2476 | } | |
6cbf8214 RW |
2477 | |
2478 | return error; | |
2479 | } | |
2480 | ||
b67ea761 RW |
2481 | /** |
2482 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2483 | * @dev: Device to check. | |
2484 | * | |
f7625980 | 2485 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2486 | * (through the platform or using the native PCIe PME) or if the device supports |
2487 | * PME and one of its upstream bridges can generate wake-up events. | |
2488 | */ | |
2489 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2490 | { | |
2491 | struct pci_bus *bus = dev->bus; | |
2492 | ||
b67ea761 RW |
2493 | if (!dev->pme_support) |
2494 | return false; | |
2495 | ||
666ff6f8 | 2496 | /* PME-capable in principle, but not from the target power state */ |
8feaec33 | 2497 | if (!pci_pme_capable(dev, pci_target_state(dev, true))) |
6496ebd7 AS |
2498 | return false; |
2499 | ||
8feaec33 KHF |
2500 | if (device_can_wakeup(&dev->dev)) |
2501 | return true; | |
2502 | ||
b67ea761 RW |
2503 | while (bus->parent) { |
2504 | struct pci_dev *bridge = bus->self; | |
2505 | ||
de3ef1eb | 2506 | if (device_can_wakeup(&bridge->dev)) |
b67ea761 RW |
2507 | return true; |
2508 | ||
2509 | bus = bus->parent; | |
2510 | } | |
2511 | ||
2512 | /* We have reached the root bus. */ | |
2513 | if (bus->bridge) | |
de3ef1eb | 2514 | return device_can_wakeup(bus->bridge); |
b67ea761 RW |
2515 | |
2516 | return false; | |
2517 | } | |
2518 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2519 | ||
bac2a909 | 2520 | /** |
0c7376ad | 2521 | * pci_dev_need_resume - Check if it is necessary to resume the device. |
bac2a909 RW |
2522 | * @pci_dev: Device to check. |
2523 | * | |
0c7376ad | 2524 | * Return 'true' if the device is not runtime-suspended or it has to be |
bac2a909 | 2525 | * reconfigured due to wakeup settings difference between system and runtime |
0c7376ad RW |
2526 | * suspend, or the current power state of it is not suitable for the upcoming |
2527 | * (system-wide) transition. | |
bac2a909 | 2528 | */ |
0c7376ad | 2529 | bool pci_dev_need_resume(struct pci_dev *pci_dev) |
bac2a909 RW |
2530 | { |
2531 | struct device *dev = &pci_dev->dev; | |
234f223d RW |
2532 | pci_power_t target_state; |
2533 | ||
2534 | if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev)) | |
0c7376ad | 2535 | return true; |
bac2a909 | 2536 | |
0c7376ad | 2537 | target_state = pci_target_state(pci_dev, device_may_wakeup(dev)); |
234f223d RW |
2538 | |
2539 | /* | |
2540 | * If the earlier platform check has not triggered, D3cold is just power | |
2541 | * removal on top of D3hot, so no need to resume the device in that | |
2542 | * case. | |
2543 | */ | |
0c7376ad RW |
2544 | return target_state != pci_dev->current_state && |
2545 | target_state != PCI_D3cold && | |
2546 | pci_dev->current_state != PCI_D3hot; | |
2547 | } | |
2548 | ||
2549 | /** | |
2550 | * pci_dev_adjust_pme - Adjust PME setting for a suspended device. | |
2551 | * @pci_dev: Device to check. | |
2552 | * | |
2553 | * If the device is suspended and it is not configured for system wakeup, | |
2554 | * disable PME for it to prevent it from waking up the system unnecessarily. | |
2555 | * | |
2556 | * Note that if the device's power state is D3cold and the platform check in | |
2557 | * pci_dev_need_resume() has not triggered, the device's configuration need not | |
2558 | * be changed. | |
2559 | */ | |
2560 | void pci_dev_adjust_pme(struct pci_dev *pci_dev) | |
2561 | { | |
2562 | struct device *dev = &pci_dev->dev; | |
bac2a909 | 2563 | |
2cef548a RW |
2564 | spin_lock_irq(&dev->power.lock); |
2565 | ||
0c7376ad RW |
2566 | if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) && |
2567 | pci_dev->current_state < PCI_D3cold) | |
2cef548a RW |
2568 | __pci_pme_active(pci_dev, false); |
2569 | ||
2570 | spin_unlock_irq(&dev->power.lock); | |
2cef548a RW |
2571 | } |
2572 | ||
2573 | /** | |
2574 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2575 | * @pci_dev: Device to handle. | |
2576 | * | |
2577 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2578 | * it might have been disabled during the prepare phase of system suspend if | |
2579 | * the device was not configured for system wakeup. | |
2580 | */ | |
2581 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2582 | { | |
2583 | struct device *dev = &pci_dev->dev; | |
2584 | ||
2585 | if (!pci_dev_run_wake(pci_dev)) | |
2586 | return; | |
2587 | ||
2588 | spin_lock_irq(&dev->power.lock); | |
2589 | ||
2590 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2591 | __pci_pme_active(pci_dev, true); | |
2592 | ||
2593 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2594 | } |
2595 | ||
b3c32c4f HY |
2596 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2597 | { | |
2598 | struct device *dev = &pdev->dev; | |
2599 | struct device *parent = dev->parent; | |
2600 | ||
2601 | if (parent) | |
2602 | pm_runtime_get_sync(parent); | |
2603 | pm_runtime_get_noresume(dev); | |
2604 | /* | |
2605 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2606 | * so wait until suspending completes | |
2607 | */ | |
2608 | pm_runtime_barrier(dev); | |
2609 | /* | |
2610 | * Only need to resume devices in D3cold, because config | |
2611 | * registers are still accessible for devices suspended but | |
2612 | * not in D3cold. | |
2613 | */ | |
2614 | if (pdev->current_state == PCI_D3cold) | |
2615 | pm_runtime_resume(dev); | |
2616 | } | |
2617 | ||
2618 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2619 | { | |
2620 | struct device *dev = &pdev->dev; | |
2621 | struct device *parent = dev->parent; | |
2622 | ||
2623 | pm_runtime_put(dev); | |
2624 | if (parent) | |
2625 | pm_runtime_put_sync(parent); | |
2626 | } | |
2627 | ||
85b0cae8 MW |
2628 | static const struct dmi_system_id bridge_d3_blacklist[] = { |
2629 | #ifdef CONFIG_X86 | |
2630 | { | |
2631 | /* | |
2632 | * Gigabyte X299 root port is not marked as hotplug capable | |
2633 | * which allows Linux to power manage it. However, this | |
2634 | * confuses the BIOS SMI handler so don't power manage root | |
2635 | * ports on that system. | |
2636 | */ | |
2637 | .ident = "X299 DESIGNARE EX-CF", | |
2638 | .matches = { | |
2639 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
2640 | DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"), | |
2641 | }, | |
2642 | }, | |
2643 | #endif | |
2644 | { } | |
2645 | }; | |
2646 | ||
9d26d3a8 MW |
2647 | /** |
2648 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2649 | * @bridge: Bridge to check | |
2650 | * | |
2651 | * This function checks if it is possible to move the bridge to D3. | |
47a8e237 | 2652 | * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt. |
9d26d3a8 | 2653 | */ |
c6a63307 | 2654 | bool pci_bridge_d3_possible(struct pci_dev *bridge) |
9d26d3a8 | 2655 | { |
9d26d3a8 MW |
2656 | if (!pci_is_pcie(bridge)) |
2657 | return false; | |
2658 | ||
2659 | switch (pci_pcie_type(bridge)) { | |
2660 | case PCI_EXP_TYPE_ROOT_PORT: | |
2661 | case PCI_EXP_TYPE_UPSTREAM: | |
2662 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2663 | if (pci_bridge_d3_disable) | |
2664 | return false; | |
97a90aee LW |
2665 | |
2666 | /* | |
eb3b5bf1 | 2667 | * Hotplug ports handled by firmware in System Management Mode |
97a90aee | 2668 | * may not be put into D3 by the OS (Thunderbolt on non-Macs). |
97a90aee | 2669 | */ |
eb3b5bf1 | 2670 | if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) |
97a90aee LW |
2671 | return false; |
2672 | ||
9d26d3a8 MW |
2673 | if (pci_bridge_d3_force) |
2674 | return true; | |
2675 | ||
47a8e237 LW |
2676 | /* Even the oldest 2010 Thunderbolt controller supports D3. */ |
2677 | if (bridge->is_thunderbolt) | |
2678 | return true; | |
2679 | ||
26ad34d5 MW |
2680 | /* Platform might know better if the bridge supports D3 */ |
2681 | if (platform_pci_bridge_d3(bridge)) | |
2682 | return true; | |
2683 | ||
eb3b5bf1 LW |
2684 | /* |
2685 | * Hotplug ports handled natively by the OS were not validated | |
2686 | * by vendors for runtime D3 at least until 2018 because there | |
2687 | * was no OS support. | |
2688 | */ | |
2689 | if (bridge->is_hotplug_bridge) | |
2690 | return false; | |
2691 | ||
85b0cae8 MW |
2692 | if (dmi_check_system(bridge_d3_blacklist)) |
2693 | return false; | |
2694 | ||
9d26d3a8 MW |
2695 | /* |
2696 | * It should be safe to put PCIe ports from 2015 or newer | |
2697 | * to D3. | |
2698 | */ | |
ac95090a | 2699 | if (dmi_get_bios_year() >= 2015) |
9d26d3a8 | 2700 | return true; |
9d26d3a8 MW |
2701 | break; |
2702 | } | |
2703 | ||
2704 | return false; | |
2705 | } | |
2706 | ||
2707 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2708 | { | |
2709 | bool *d3cold_ok = data; | |
9d26d3a8 | 2710 | |
718a0609 LW |
2711 | if (/* The device needs to be allowed to go D3cold ... */ |
2712 | dev->no_d3cold || !dev->d3cold_allowed || | |
2713 | ||
2714 | /* ... and if it is wakeup capable to do so from D3cold. */ | |
2715 | (device_may_wakeup(&dev->dev) && | |
2716 | !pci_pme_capable(dev, PCI_D3cold)) || | |
2717 | ||
2718 | /* If it is a bridge it must be allowed to go to D3. */ | |
d98e0929 | 2719 | !pci_power_manageable(dev)) |
9d26d3a8 | 2720 | |
718a0609 | 2721 | *d3cold_ok = false; |
9d26d3a8 | 2722 | |
718a0609 | 2723 | return !*d3cold_ok; |
9d26d3a8 MW |
2724 | } |
2725 | ||
2726 | /* | |
2727 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
2728 | * @dev: PCI device which is changed | |
9d26d3a8 MW |
2729 | * |
2730 | * Update upstream bridge PM capabilities accordingly depending on if the | |
2731 | * device PM configuration was changed or the device is being removed. The | |
2732 | * change is also propagated upstream. | |
2733 | */ | |
1ed276a7 | 2734 | void pci_bridge_d3_update(struct pci_dev *dev) |
9d26d3a8 | 2735 | { |
1ed276a7 | 2736 | bool remove = !device_is_registered(&dev->dev); |
9d26d3a8 MW |
2737 | struct pci_dev *bridge; |
2738 | bool d3cold_ok = true; | |
2739 | ||
2740 | bridge = pci_upstream_bridge(dev); | |
2741 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
2742 | return; | |
2743 | ||
9d26d3a8 | 2744 | /* |
e8559b71 LW |
2745 | * If D3 is currently allowed for the bridge, removing one of its |
2746 | * children won't change that. | |
2747 | */ | |
2748 | if (remove && bridge->bridge_d3) | |
2749 | return; | |
2750 | ||
2751 | /* | |
2752 | * If D3 is currently allowed for the bridge and a child is added or | |
2753 | * changed, disallowance of D3 can only be caused by that child, so | |
2754 | * we only need to check that single device, not any of its siblings. | |
2755 | * | |
2756 | * If D3 is currently not allowed for the bridge, checking the device | |
2757 | * first may allow us to skip checking its siblings. | |
9d26d3a8 MW |
2758 | */ |
2759 | if (!remove) | |
2760 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
2761 | ||
e8559b71 LW |
2762 | /* |
2763 | * If D3 is currently not allowed for the bridge, this may be caused | |
2764 | * either by the device being changed/removed or any of its siblings, | |
2765 | * so we need to go through all children to find out if one of them | |
2766 | * continues to block D3. | |
2767 | */ | |
2768 | if (d3cold_ok && !bridge->bridge_d3) | |
9d26d3a8 MW |
2769 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, |
2770 | &d3cold_ok); | |
9d26d3a8 MW |
2771 | |
2772 | if (bridge->bridge_d3 != d3cold_ok) { | |
2773 | bridge->bridge_d3 = d3cold_ok; | |
2774 | /* Propagate change to upstream bridges */ | |
1ed276a7 | 2775 | pci_bridge_d3_update(bridge); |
9d26d3a8 | 2776 | } |
9d26d3a8 MW |
2777 | } |
2778 | ||
9d26d3a8 MW |
2779 | /** |
2780 | * pci_d3cold_enable - Enable D3cold for device | |
2781 | * @dev: PCI device to handle | |
2782 | * | |
2783 | * This function can be used in drivers to enable D3cold from the device | |
2784 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2785 | * accordingly. | |
2786 | */ | |
2787 | void pci_d3cold_enable(struct pci_dev *dev) | |
2788 | { | |
2789 | if (dev->no_d3cold) { | |
2790 | dev->no_d3cold = false; | |
1ed276a7 | 2791 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2792 | } |
2793 | } | |
2794 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
2795 | ||
2796 | /** | |
2797 | * pci_d3cold_disable - Disable D3cold for device | |
2798 | * @dev: PCI device to handle | |
2799 | * | |
2800 | * This function can be used in drivers to disable D3cold from the device | |
2801 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2802 | * accordingly. | |
2803 | */ | |
2804 | void pci_d3cold_disable(struct pci_dev *dev) | |
2805 | { | |
2806 | if (!dev->no_d3cold) { | |
2807 | dev->no_d3cold = true; | |
1ed276a7 | 2808 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2809 | } |
2810 | } | |
2811 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
2812 | ||
eb9d0fe4 RW |
2813 | /** |
2814 | * pci_pm_init - Initialize PM functions of given PCI device | |
2815 | * @dev: PCI device to handle. | |
2816 | */ | |
2817 | void pci_pm_init(struct pci_dev *dev) | |
2818 | { | |
2819 | int pm; | |
d6112f8d | 2820 | u16 status; |
eb9d0fe4 | 2821 | u16 pmc; |
1da177e4 | 2822 | |
bb910a70 | 2823 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2824 | pm_runtime_set_active(&dev->dev); |
2825 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2826 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2827 | dev->wakeup_prepared = false; |
bb910a70 | 2828 | |
337001b6 | 2829 | dev->pm_cap = 0; |
ffaddbe8 | 2830 | dev->pme_support = 0; |
337001b6 | 2831 | |
eb9d0fe4 RW |
2832 | /* find PCI PM capability in list */ |
2833 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2834 | if (!pm) | |
50246dd4 | 2835 | return; |
eb9d0fe4 RW |
2836 | /* Check device's ability to generate PME# */ |
2837 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2838 | |
eb9d0fe4 | 2839 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
7506dc79 | 2840 | pci_err(dev, "unsupported PM cap regs version (%u)\n", |
eb9d0fe4 | 2841 | pmc & PCI_PM_CAP_VER_MASK); |
50246dd4 | 2842 | return; |
eb9d0fe4 RW |
2843 | } |
2844 | ||
337001b6 | 2845 | dev->pm_cap = pm; |
1ae861e6 | 2846 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2847 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 2848 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 2849 | dev->d3cold_allowed = true; |
337001b6 RW |
2850 | |
2851 | dev->d1_support = false; | |
2852 | dev->d2_support = false; | |
2853 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2854 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2855 | dev->d1_support = true; |
c9ed77ee | 2856 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2857 | dev->d2_support = true; |
c9ed77ee BH |
2858 | |
2859 | if (dev->d1_support || dev->d2_support) | |
34c6b710 | 2860 | pci_info(dev, "supports%s%s\n", |
ec84f126 JB |
2861 | dev->d1_support ? " D1" : "", |
2862 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2863 | } |
2864 | ||
2865 | pmc &= PCI_PM_CAP_PME_MASK; | |
2866 | if (pmc) { | |
34c6b710 | 2867 | pci_info(dev, "PME# supported from%s%s%s%s%s\n", |
c9ed77ee BH |
2868 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2869 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2870 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2871 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2872 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2873 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2874 | dev->pme_poll = true; |
eb9d0fe4 RW |
2875 | /* |
2876 | * Make device's PM flags reflect the wake-up capability, but | |
2877 | * let the user space enable it to wake up the system as needed. | |
2878 | */ | |
2879 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2880 | /* Disable the PME# generation functionality */ |
337001b6 | 2881 | pci_pme_active(dev, false); |
eb9d0fe4 | 2882 | } |
d6112f8d FB |
2883 | |
2884 | pci_read_config_word(dev, PCI_STATUS, &status); | |
2885 | if (status & PCI_STATUS_IMM_READY) | |
2886 | dev->imm_ready = 1; | |
1da177e4 LT |
2887 | } |
2888 | ||
938174e5 SS |
2889 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
2890 | { | |
92efb1bd | 2891 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
2892 | |
2893 | switch (prop) { | |
2894 | case PCI_EA_P_MEM: | |
2895 | case PCI_EA_P_VF_MEM: | |
2896 | flags |= IORESOURCE_MEM; | |
2897 | break; | |
2898 | case PCI_EA_P_MEM_PREFETCH: | |
2899 | case PCI_EA_P_VF_MEM_PREFETCH: | |
2900 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
2901 | break; | |
2902 | case PCI_EA_P_IO: | |
2903 | flags |= IORESOURCE_IO; | |
2904 | break; | |
2905 | default: | |
2906 | return 0; | |
2907 | } | |
2908 | ||
2909 | return flags; | |
2910 | } | |
2911 | ||
2912 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
2913 | u8 prop) | |
2914 | { | |
2915 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
2916 | return &dev->resource[bei]; | |
11183991 DD |
2917 | #ifdef CONFIG_PCI_IOV |
2918 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
2919 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
2920 | return &dev->resource[PCI_IOV_RESOURCES + | |
2921 | bei - PCI_EA_BEI_VF_BAR0]; | |
2922 | #endif | |
938174e5 SS |
2923 | else if (bei == PCI_EA_BEI_ROM) |
2924 | return &dev->resource[PCI_ROM_RESOURCE]; | |
2925 | else | |
2926 | return NULL; | |
2927 | } | |
2928 | ||
2929 | /* Read an Enhanced Allocation (EA) entry */ | |
2930 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
2931 | { | |
2932 | struct resource *res; | |
2933 | int ent_size, ent_offset = offset; | |
2934 | resource_size_t start, end; | |
2935 | unsigned long flags; | |
26635112 | 2936 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
2937 | u8 prop; |
2938 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
2939 | ||
2940 | pci_read_config_dword(dev, ent_offset, &dw0); | |
2941 | ent_offset += 4; | |
2942 | ||
2943 | /* Entry size field indicates DWORDs after 1st */ | |
2944 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
2945 | ||
2946 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
2947 | goto out; | |
2948 | ||
26635112 BH |
2949 | bei = (dw0 & PCI_EA_BEI) >> 4; |
2950 | prop = (dw0 & PCI_EA_PP) >> 8; | |
2951 | ||
938174e5 SS |
2952 | /* |
2953 | * If the Property is in the reserved range, try the Secondary | |
2954 | * Property instead. | |
2955 | */ | |
2956 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 2957 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
2958 | if (prop > PCI_EA_P_BRIDGE_IO) |
2959 | goto out; | |
2960 | ||
26635112 | 2961 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 2962 | if (!res) { |
7506dc79 | 2963 | pci_err(dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
2964 | goto out; |
2965 | } | |
2966 | ||
2967 | flags = pci_ea_flags(dev, prop); | |
2968 | if (!flags) { | |
7506dc79 | 2969 | pci_err(dev, "Unsupported EA properties: %#x\n", prop); |
938174e5 SS |
2970 | goto out; |
2971 | } | |
2972 | ||
2973 | /* Read Base */ | |
2974 | pci_read_config_dword(dev, ent_offset, &base); | |
2975 | start = (base & PCI_EA_FIELD_MASK); | |
2976 | ent_offset += 4; | |
2977 | ||
2978 | /* Read MaxOffset */ | |
2979 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
2980 | ent_offset += 4; | |
2981 | ||
2982 | /* Read Base MSBs (if 64-bit entry) */ | |
2983 | if (base & PCI_EA_IS_64) { | |
2984 | u32 base_upper; | |
2985 | ||
2986 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
2987 | ent_offset += 4; | |
2988 | ||
2989 | flags |= IORESOURCE_MEM_64; | |
2990 | ||
2991 | /* entry starts above 32-bit boundary, can't use */ | |
2992 | if (!support_64 && base_upper) | |
2993 | goto out; | |
2994 | ||
2995 | if (support_64) | |
2996 | start |= ((u64)base_upper << 32); | |
2997 | } | |
2998 | ||
2999 | end = start + (max_offset | 0x03); | |
3000 | ||
3001 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
3002 | if (max_offset & PCI_EA_IS_64) { | |
3003 | u32 max_offset_upper; | |
3004 | ||
3005 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
3006 | ent_offset += 4; | |
3007 | ||
3008 | flags |= IORESOURCE_MEM_64; | |
3009 | ||
3010 | /* entry too big, can't use */ | |
3011 | if (!support_64 && max_offset_upper) | |
3012 | goto out; | |
3013 | ||
3014 | if (support_64) | |
3015 | end += ((u64)max_offset_upper << 32); | |
3016 | } | |
3017 | ||
3018 | if (end < start) { | |
7506dc79 | 3019 | pci_err(dev, "EA Entry crosses address boundary\n"); |
938174e5 SS |
3020 | goto out; |
3021 | } | |
3022 | ||
3023 | if (ent_size != ent_offset - offset) { | |
7506dc79 | 3024 | pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", |
938174e5 SS |
3025 | ent_size, ent_offset - offset); |
3026 | goto out; | |
3027 | } | |
3028 | ||
3029 | res->name = pci_name(dev); | |
3030 | res->start = start; | |
3031 | res->end = end; | |
3032 | res->flags = flags; | |
597becb4 BH |
3033 | |
3034 | if (bei <= PCI_EA_BEI_BAR5) | |
34c6b710 | 3035 | pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3036 | bei, res, prop); |
3037 | else if (bei == PCI_EA_BEI_ROM) | |
34c6b710 | 3038 | pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3039 | res, prop); |
3040 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
34c6b710 | 3041 | pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3042 | bei - PCI_EA_BEI_VF_BAR0, res, prop); |
3043 | else | |
34c6b710 | 3044 | pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", |
597becb4 BH |
3045 | bei, res, prop); |
3046 | ||
938174e5 SS |
3047 | out: |
3048 | return offset + ent_size; | |
3049 | } | |
3050 | ||
dcbb408a | 3051 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
3052 | void pci_ea_init(struct pci_dev *dev) |
3053 | { | |
3054 | int ea; | |
3055 | u8 num_ent; | |
3056 | int offset; | |
3057 | int i; | |
3058 | ||
3059 | /* find PCI EA capability in list */ | |
3060 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
3061 | if (!ea) | |
3062 | return; | |
3063 | ||
3064 | /* determine the number of entries */ | |
3065 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
3066 | &num_ent); | |
3067 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
3068 | ||
3069 | offset = ea + PCI_EA_FIRST_ENT; | |
3070 | ||
3071 | /* Skip DWORD 2 for type 1 functions */ | |
3072 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
3073 | offset += 4; | |
3074 | ||
3075 | /* parse each EA entry */ | |
3076 | for (i = 0; i < num_ent; ++i) | |
3077 | offset = pci_ea_read(dev, offset); | |
3078 | } | |
3079 | ||
34a4876e YL |
3080 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
3081 | struct pci_cap_saved_state *new_cap) | |
3082 | { | |
3083 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
3084 | } | |
3085 | ||
63f4898a | 3086 | /** |
fd0f7f73 | 3087 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
74356add | 3088 | * capability registers |
63f4898a RW |
3089 | * @dev: the PCI device |
3090 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 3091 | * @extended: Standard or Extended capability ID |
63f4898a RW |
3092 | * @size: requested size of the buffer |
3093 | */ | |
fd0f7f73 AW |
3094 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
3095 | bool extended, unsigned int size) | |
63f4898a RW |
3096 | { |
3097 | int pos; | |
3098 | struct pci_cap_saved_state *save_state; | |
3099 | ||
fd0f7f73 AW |
3100 | if (extended) |
3101 | pos = pci_find_ext_capability(dev, cap); | |
3102 | else | |
3103 | pos = pci_find_capability(dev, cap); | |
3104 | ||
0a1a9b49 | 3105 | if (!pos) |
63f4898a RW |
3106 | return 0; |
3107 | ||
3108 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
3109 | if (!save_state) | |
3110 | return -ENOMEM; | |
3111 | ||
24a4742f | 3112 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 3113 | save_state->cap.cap_extended = extended; |
24a4742f | 3114 | save_state->cap.size = size; |
63f4898a RW |
3115 | pci_add_saved_cap(dev, save_state); |
3116 | ||
3117 | return 0; | |
3118 | } | |
3119 | ||
fd0f7f73 AW |
3120 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
3121 | { | |
3122 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
3123 | } | |
3124 | ||
3125 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
3126 | { | |
3127 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
3128 | } | |
3129 | ||
63f4898a RW |
3130 | /** |
3131 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
3132 | * @dev: the PCI device | |
3133 | */ | |
3134 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
3135 | { | |
3136 | int error; | |
3137 | ||
89858517 YZ |
3138 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
3139 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a | 3140 | if (error) |
7506dc79 | 3141 | pci_err(dev, "unable to preallocate PCI Express save buffer\n"); |
63f4898a RW |
3142 | |
3143 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
3144 | if (error) | |
7506dc79 | 3145 | pci_err(dev, "unable to preallocate PCI-X save buffer\n"); |
425c1b22 | 3146 | |
dbbfadf2 BH |
3147 | error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR, |
3148 | 2 * sizeof(u16)); | |
3149 | if (error) | |
3150 | pci_err(dev, "unable to allocate suspend buffer for LTR\n"); | |
3151 | ||
425c1b22 | 3152 | pci_allocate_vc_save_buffers(dev); |
63f4898a RW |
3153 | } |
3154 | ||
f796841e YL |
3155 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
3156 | { | |
3157 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 3158 | struct hlist_node *n; |
f796841e | 3159 | |
b67bfe0d | 3160 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
3161 | kfree(tmp); |
3162 | } | |
3163 | ||
58c3a727 | 3164 | /** |
31ab2476 | 3165 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 3166 | * @dev: the PCI device |
b0cc6020 YW |
3167 | * |
3168 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
3169 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 3170 | */ |
31ab2476 | 3171 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 3172 | { |
58c3a727 | 3173 | u32 cap; |
8113587c | 3174 | struct pci_dev *bridge; |
58c3a727 | 3175 | |
6748dcc2 | 3176 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
3177 | return; |
3178 | ||
8113587c | 3179 | bridge = dev->bus->self; |
cb97ae34 | 3180 | if (!bridge) |
8113587c ZY |
3181 | return; |
3182 | ||
59875ae4 | 3183 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
3184 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
3185 | return; | |
3186 | ||
b0cc6020 YW |
3187 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
3188 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
3189 | PCI_EXP_DEVCTL2_ARI); | |
3190 | bridge->ari_enabled = 1; | |
3191 | } else { | |
3192 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
3193 | PCI_EXP_DEVCTL2_ARI); | |
3194 | bridge->ari_enabled = 0; | |
3195 | } | |
58c3a727 YZ |
3196 | } |
3197 | ||
5d990b62 CW |
3198 | static int pci_acs_enable; |
3199 | ||
3200 | /** | |
3201 | * pci_request_acs - ask for ACS to be enabled if supported | |
3202 | */ | |
3203 | void pci_request_acs(void) | |
3204 | { | |
3205 | pci_acs_enable = 1; | |
3206 | } | |
3207 | ||
aaca43fd LG |
3208 | static const char *disable_acs_redir_param; |
3209 | ||
3210 | /** | |
3211 | * pci_disable_acs_redir - disable ACS redirect capabilities | |
3212 | * @dev: the PCI device | |
3213 | * | |
3214 | * For only devices specified in the disable_acs_redir parameter. | |
3215 | */ | |
3216 | static void pci_disable_acs_redir(struct pci_dev *dev) | |
3217 | { | |
3218 | int ret = 0; | |
3219 | const char *p; | |
3220 | int pos; | |
3221 | u16 ctrl; | |
3222 | ||
3223 | if (!disable_acs_redir_param) | |
3224 | return; | |
3225 | ||
3226 | p = disable_acs_redir_param; | |
3227 | while (*p) { | |
3228 | ret = pci_dev_str_match(dev, p, &p); | |
3229 | if (ret < 0) { | |
3230 | pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n", | |
3231 | disable_acs_redir_param); | |
3232 | ||
3233 | break; | |
3234 | } else if (ret == 1) { | |
3235 | /* Found a match */ | |
3236 | break; | |
3237 | } | |
3238 | ||
3239 | if (*p != ';' && *p != ',') { | |
3240 | /* End of param or invalid format */ | |
3241 | break; | |
3242 | } | |
3243 | p++; | |
3244 | } | |
3245 | ||
3246 | if (ret != 1) | |
3247 | return; | |
3248 | ||
73c47dde LG |
3249 | if (!pci_dev_specific_disable_acs_redir(dev)) |
3250 | return; | |
3251 | ||
aaca43fd LG |
3252 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
3253 | if (!pos) { | |
3254 | pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n"); | |
3255 | return; | |
3256 | } | |
3257 | ||
3258 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
3259 | ||
3260 | /* P2P Request & Completion Redirect */ | |
3261 | ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); | |
3262 | ||
3263 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
3264 | ||
3265 | pci_info(dev, "disabled ACS redirect\n"); | |
3266 | } | |
3267 | ||
ae21ee65 | 3268 | /** |
74356add | 3269 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities |
ae21ee65 AK |
3270 | * @dev: the PCI device |
3271 | */ | |
c1d61c9b | 3272 | static void pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
3273 | { |
3274 | int pos; | |
3275 | u16 cap; | |
3276 | u16 ctrl; | |
3277 | ||
ae21ee65 AK |
3278 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
3279 | if (!pos) | |
c1d61c9b | 3280 | return; |
ae21ee65 AK |
3281 | |
3282 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
3283 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
3284 | ||
3285 | /* Source Validation */ | |
3286 | ctrl |= (cap & PCI_ACS_SV); | |
3287 | ||
3288 | /* P2P Request Redirect */ | |
3289 | ctrl |= (cap & PCI_ACS_RR); | |
3290 | ||
3291 | /* P2P Completion Redirect */ | |
3292 | ctrl |= (cap & PCI_ACS_CR); | |
3293 | ||
3294 | /* Upstream Forwarding */ | |
3295 | ctrl |= (cap & PCI_ACS_UF); | |
3296 | ||
3297 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
3298 | } |
3299 | ||
3300 | /** | |
3301 | * pci_enable_acs - enable ACS if hardware support it | |
3302 | * @dev: the PCI device | |
3303 | */ | |
3304 | void pci_enable_acs(struct pci_dev *dev) | |
3305 | { | |
3306 | if (!pci_acs_enable) | |
aaca43fd | 3307 | goto disable_acs_redir; |
2c744244 | 3308 | |
c1d61c9b | 3309 | if (!pci_dev_specific_enable_acs(dev)) |
aaca43fd | 3310 | goto disable_acs_redir; |
2c744244 | 3311 | |
c1d61c9b | 3312 | pci_std_enable_acs(dev); |
aaca43fd LG |
3313 | |
3314 | disable_acs_redir: | |
3315 | /* | |
3316 | * Note: pci_disable_acs_redir() must be called even if ACS was not | |
3317 | * enabled by the kernel because it may have been enabled by | |
3318 | * platform firmware. So if we are told to disable it, we should | |
3319 | * always disable it after setting the kernel's default | |
3320 | * preferences. | |
3321 | */ | |
3322 | pci_disable_acs_redir(dev); | |
ae21ee65 AK |
3323 | } |
3324 | ||
0a67119f AW |
3325 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
3326 | { | |
3327 | int pos; | |
83db7e0b | 3328 | u16 cap, ctrl; |
0a67119f AW |
3329 | |
3330 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
3331 | if (!pos) | |
3332 | return false; | |
3333 | ||
83db7e0b AW |
3334 | /* |
3335 | * Except for egress control, capabilities are either required | |
3336 | * or only required if controllable. Features missing from the | |
3337 | * capability field can therefore be assumed as hard-wired enabled. | |
3338 | */ | |
3339 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
3340 | acs_flags &= (cap | PCI_ACS_EC); | |
3341 | ||
0a67119f AW |
3342 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
3343 | return (ctrl & acs_flags) == acs_flags; | |
3344 | } | |
3345 | ||
ad805758 AW |
3346 | /** |
3347 | * pci_acs_enabled - test ACS against required flags for a given device | |
3348 | * @pdev: device to test | |
3349 | * @acs_flags: required PCI ACS flags | |
3350 | * | |
3351 | * Return true if the device supports the provided flags. Automatically | |
3352 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
3353 | * |
3354 | * Note that this interface checks the effective ACS capabilities of the | |
3355 | * device rather than the actual capabilities. For instance, most single | |
3356 | * function endpoints are not required to support ACS because they have no | |
3357 | * opportunity for peer-to-peer access. We therefore return 'true' | |
3358 | * regardless of whether the device exposes an ACS capability. This makes | |
3359 | * it much easier for callers of this function to ignore the actual type | |
3360 | * or topology of the device when testing ACS support. | |
ad805758 AW |
3361 | */ |
3362 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
3363 | { | |
0a67119f | 3364 | int ret; |
ad805758 AW |
3365 | |
3366 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
3367 | if (ret >= 0) | |
3368 | return ret > 0; | |
3369 | ||
0a67119f AW |
3370 | /* |
3371 | * Conventional PCI and PCI-X devices never support ACS, either | |
3372 | * effectively or actually. The shared bus topology implies that | |
3373 | * any device on the bus can receive or snoop DMA. | |
3374 | */ | |
ad805758 AW |
3375 | if (!pci_is_pcie(pdev)) |
3376 | return false; | |
3377 | ||
0a67119f AW |
3378 | switch (pci_pcie_type(pdev)) { |
3379 | /* | |
3380 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 3381 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
3382 | * handle them as we would a non-PCIe device. |
3383 | */ | |
3384 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
3385 | /* | |
3386 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
3387 | * applicable... must never implement an ACS Extended Capability...". | |
3388 | * This seems arbitrary, but we take a conservative interpretation | |
3389 | * of this statement. | |
3390 | */ | |
3391 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
3392 | case PCI_EXP_TYPE_RC_EC: | |
3393 | return false; | |
3394 | /* | |
3395 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
3396 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
3397 | * regardless of whether they are single- or multi-function devices. | |
3398 | */ | |
3399 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3400 | case PCI_EXP_TYPE_ROOT_PORT: | |
3401 | return pci_acs_flags_enabled(pdev, acs_flags); | |
3402 | /* | |
3403 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
3404 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 3405 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
3406 | * device. The footnote for section 6.12 indicates the specific |
3407 | * PCIe types included here. | |
3408 | */ | |
3409 | case PCI_EXP_TYPE_ENDPOINT: | |
3410 | case PCI_EXP_TYPE_UPSTREAM: | |
3411 | case PCI_EXP_TYPE_LEG_END: | |
3412 | case PCI_EXP_TYPE_RC_END: | |
3413 | if (!pdev->multifunction) | |
3414 | break; | |
3415 | ||
0a67119f | 3416 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
3417 | } |
3418 | ||
0a67119f | 3419 | /* |
f7625980 | 3420 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
3421 | * to single function devices with the exception of downstream ports. |
3422 | */ | |
ad805758 AW |
3423 | return true; |
3424 | } | |
3425 | ||
3426 | /** | |
3427 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
3428 | * @start: starting downstream device | |
3429 | * @end: ending upstream device or NULL to search to the root bus | |
3430 | * @acs_flags: required flags | |
3431 | * | |
3432 | * Walk up a device tree from start to end testing PCI ACS support. If | |
3433 | * any step along the way does not support the required flags, return false. | |
3434 | */ | |
3435 | bool pci_acs_path_enabled(struct pci_dev *start, | |
3436 | struct pci_dev *end, u16 acs_flags) | |
3437 | { | |
3438 | struct pci_dev *pdev, *parent = start; | |
3439 | ||
3440 | do { | |
3441 | pdev = parent; | |
3442 | ||
3443 | if (!pci_acs_enabled(pdev, acs_flags)) | |
3444 | return false; | |
3445 | ||
3446 | if (pci_is_root_bus(pdev->bus)) | |
3447 | return (end == NULL); | |
3448 | ||
3449 | parent = pdev->bus->self; | |
3450 | } while (pdev != end); | |
3451 | ||
3452 | return true; | |
3453 | } | |
3454 | ||
276b738d CK |
3455 | /** |
3456 | * pci_rebar_find_pos - find position of resize ctrl reg for BAR | |
3457 | * @pdev: PCI device | |
3458 | * @bar: BAR to find | |
3459 | * | |
3460 | * Helper to find the position of the ctrl register for a BAR. | |
3461 | * Returns -ENOTSUPP if resizable BARs are not supported at all. | |
3462 | * Returns -ENOENT if no ctrl register for the BAR could be found. | |
3463 | */ | |
3464 | static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) | |
3465 | { | |
3466 | unsigned int pos, nbars, i; | |
3467 | u32 ctrl; | |
3468 | ||
3469 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
3470 | if (!pos) | |
3471 | return -ENOTSUPP; | |
3472 | ||
3473 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3474 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
3475 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
3476 | ||
3477 | for (i = 0; i < nbars; i++, pos += 8) { | |
3478 | int bar_idx; | |
3479 | ||
3480 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3481 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
3482 | if (bar_idx == bar) | |
3483 | return pos; | |
3484 | } | |
3485 | ||
3486 | return -ENOENT; | |
3487 | } | |
3488 | ||
3489 | /** | |
3490 | * pci_rebar_get_possible_sizes - get possible sizes for BAR | |
3491 | * @pdev: PCI device | |
3492 | * @bar: BAR to query | |
3493 | * | |
3494 | * Get the possible sizes of a resizable BAR as bitmask defined in the spec | |
3495 | * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable. | |
3496 | */ | |
3497 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) | |
3498 | { | |
3499 | int pos; | |
3500 | u32 cap; | |
3501 | ||
3502 | pos = pci_rebar_find_pos(pdev, bar); | |
3503 | if (pos < 0) | |
3504 | return 0; | |
3505 | ||
3506 | pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); | |
3507 | return (cap & PCI_REBAR_CAP_SIZES) >> 4; | |
3508 | } | |
3509 | ||
3510 | /** | |
3511 | * pci_rebar_get_current_size - get the current size of a BAR | |
3512 | * @pdev: PCI device | |
3513 | * @bar: BAR to set size to | |
3514 | * | |
3515 | * Read the size of a BAR from the resizable BAR config. | |
3516 | * Returns size if found or negative error code. | |
3517 | */ | |
3518 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) | |
3519 | { | |
3520 | int pos; | |
3521 | u32 ctrl; | |
3522 | ||
3523 | pos = pci_rebar_find_pos(pdev, bar); | |
3524 | if (pos < 0) | |
3525 | return pos; | |
3526 | ||
3527 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
b1277a22 | 3528 | return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3529 | } |
3530 | ||
3531 | /** | |
3532 | * pci_rebar_set_size - set a new size for a BAR | |
3533 | * @pdev: PCI device | |
3534 | * @bar: BAR to set size to | |
3535 | * @size: new size as defined in the spec (0=1MB, 19=512GB) | |
3536 | * | |
3537 | * Set the new size of a BAR as defined in the spec. | |
3538 | * Returns zero if resizing was successful, error code otherwise. | |
3539 | */ | |
3540 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) | |
3541 | { | |
3542 | int pos; | |
3543 | u32 ctrl; | |
3544 | ||
3545 | pos = pci_rebar_find_pos(pdev, bar); | |
3546 | if (pos < 0) | |
3547 | return pos; | |
3548 | ||
3549 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3550 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
b1277a22 | 3551 | ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; |
276b738d CK |
3552 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |
3553 | return 0; | |
3554 | } | |
3555 | ||
430a2368 JC |
3556 | /** |
3557 | * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port | |
3558 | * @dev: the PCI device | |
3559 | * @cap_mask: mask of desired AtomicOp sizes, including one or more of: | |
3560 | * PCI_EXP_DEVCAP2_ATOMIC_COMP32 | |
3561 | * PCI_EXP_DEVCAP2_ATOMIC_COMP64 | |
3562 | * PCI_EXP_DEVCAP2_ATOMIC_COMP128 | |
3563 | * | |
3564 | * Return 0 if all upstream bridges support AtomicOp routing, egress | |
3565 | * blocking is disabled on all upstream ports, and the root port supports | |
3566 | * the requested completion capabilities (32-bit, 64-bit and/or 128-bit | |
3567 | * AtomicOp completion), or negative otherwise. | |
3568 | */ | |
3569 | int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) | |
3570 | { | |
3571 | struct pci_bus *bus = dev->bus; | |
3572 | struct pci_dev *bridge; | |
3573 | u32 cap, ctl2; | |
3574 | ||
3575 | if (!pci_is_pcie(dev)) | |
3576 | return -EINVAL; | |
3577 | ||
3578 | /* | |
3579 | * Per PCIe r4.0, sec 6.15, endpoints and root ports may be | |
3580 | * AtomicOp requesters. For now, we only support endpoints as | |
3581 | * requesters and root ports as completers. No endpoints as | |
3582 | * completers, and no peer-to-peer. | |
3583 | */ | |
3584 | ||
3585 | switch (pci_pcie_type(dev)) { | |
3586 | case PCI_EXP_TYPE_ENDPOINT: | |
3587 | case PCI_EXP_TYPE_LEG_END: | |
3588 | case PCI_EXP_TYPE_RC_END: | |
3589 | break; | |
3590 | default: | |
3591 | return -EINVAL; | |
3592 | } | |
3593 | ||
3594 | while (bus->parent) { | |
3595 | bridge = bus->self; | |
3596 | ||
3597 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); | |
3598 | ||
3599 | switch (pci_pcie_type(bridge)) { | |
3600 | /* Ensure switch ports support AtomicOp routing */ | |
3601 | case PCI_EXP_TYPE_UPSTREAM: | |
3602 | case PCI_EXP_TYPE_DOWNSTREAM: | |
3603 | if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) | |
3604 | return -EINVAL; | |
3605 | break; | |
3606 | ||
3607 | /* Ensure root port supports all the sizes we care about */ | |
3608 | case PCI_EXP_TYPE_ROOT_PORT: | |
3609 | if ((cap & cap_mask) != cap_mask) | |
3610 | return -EINVAL; | |
3611 | break; | |
3612 | } | |
3613 | ||
3614 | /* Ensure upstream ports don't block AtomicOps on egress */ | |
ca784104 | 3615 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) { |
430a2368 JC |
3616 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, |
3617 | &ctl2); | |
3618 | if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) | |
3619 | return -EINVAL; | |
3620 | } | |
3621 | ||
3622 | bus = bus->parent; | |
3623 | } | |
3624 | ||
3625 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, | |
3626 | PCI_EXP_DEVCTL2_ATOMIC_REQ); | |
3627 | return 0; | |
3628 | } | |
3629 | EXPORT_SYMBOL(pci_enable_atomic_ops_to_root); | |
3630 | ||
57c2cf71 BH |
3631 | /** |
3632 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
3633 | * @dev: the PCI device | |
bb5c2de2 | 3634 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
3635 | * |
3636 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
3637 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
3638 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
3639 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
3640 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 3641 | */ |
3df425f3 | 3642 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 3643 | { |
46b952a3 MW |
3644 | int slot; |
3645 | ||
3646 | if (pci_ari_enabled(dev->bus)) | |
3647 | slot = 0; | |
3648 | else | |
3649 | slot = PCI_SLOT(dev->devfn); | |
3650 | ||
3651 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
3652 | } |
3653 | ||
3c78bc61 | 3654 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
3655 | { |
3656 | u8 pin; | |
3657 | ||
514d207d | 3658 | pin = dev->pin; |
1da177e4 LT |
3659 | if (!pin) |
3660 | return -1; | |
878f2e50 | 3661 | |
8784fd4d | 3662 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 3663 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
3664 | dev = dev->bus->self; |
3665 | } | |
3666 | *bridge = dev; | |
3667 | return pin; | |
3668 | } | |
3669 | ||
68feac87 BH |
3670 | /** |
3671 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
3672 | * @dev: the PCI device | |
3673 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
3674 | * | |
3675 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
3676 | * bridges all the way up to a PCI root bus. | |
3677 | */ | |
3678 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
3679 | { | |
3680 | u8 pin = *pinp; | |
3681 | ||
1eb39487 | 3682 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
3683 | pin = pci_swizzle_interrupt_pin(dev, pin); |
3684 | dev = dev->bus->self; | |
3685 | } | |
3686 | *pinp = pin; | |
3687 | return PCI_SLOT(dev->devfn); | |
3688 | } | |
e6b29dea | 3689 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 3690 | |
1da177e4 | 3691 | /** |
74356add BH |
3692 | * pci_release_region - Release a PCI bar |
3693 | * @pdev: PCI device whose resources were previously reserved by | |
3694 | * pci_request_region() | |
3695 | * @bar: BAR to release | |
1da177e4 | 3696 | * |
74356add BH |
3697 | * Releases the PCI I/O and memory resources previously reserved by a |
3698 | * successful call to pci_request_region(). Call this function only | |
3699 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3700 | */ |
3701 | void pci_release_region(struct pci_dev *pdev, int bar) | |
3702 | { | |
9ac7849e TH |
3703 | struct pci_devres *dr; |
3704 | ||
1da177e4 LT |
3705 | if (pci_resource_len(pdev, bar) == 0) |
3706 | return; | |
3707 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
3708 | release_region(pci_resource_start(pdev, bar), | |
3709 | pci_resource_len(pdev, bar)); | |
3710 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
3711 | release_mem_region(pci_resource_start(pdev, bar), | |
3712 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
3713 | |
3714 | dr = find_pci_dr(pdev); | |
3715 | if (dr) | |
3716 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 3717 | } |
b7fe9434 | 3718 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
3719 | |
3720 | /** | |
74356add BH |
3721 | * __pci_request_region - Reserved PCI I/O and memory resource |
3722 | * @pdev: PCI device whose resources are to be reserved | |
3723 | * @bar: BAR to be reserved | |
3724 | * @res_name: Name to be associated with resource. | |
3725 | * @exclusive: whether the region access is exclusive or not | |
1da177e4 | 3726 | * |
74356add BH |
3727 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3728 | * being reserved by owner @res_name. Do not access any | |
3729 | * address inside the PCI regions unless this call returns | |
3730 | * successfully. | |
1da177e4 | 3731 | * |
74356add BH |
3732 | * If @exclusive is set, then the region is marked so that userspace |
3733 | * is explicitly not allowed to map the resource via /dev/mem or | |
3734 | * sysfs MMIO access. | |
f5ddcac4 | 3735 | * |
74356add BH |
3736 | * Returns 0 on success, or %EBUSY on error. A warning |
3737 | * message is also printed on failure. | |
1da177e4 | 3738 | */ |
3c78bc61 RD |
3739 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3740 | const char *res_name, int exclusive) | |
1da177e4 | 3741 | { |
9ac7849e TH |
3742 | struct pci_devres *dr; |
3743 | ||
1da177e4 LT |
3744 | if (pci_resource_len(pdev, bar) == 0) |
3745 | return 0; | |
f7625980 | 3746 | |
1da177e4 LT |
3747 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3748 | if (!request_region(pci_resource_start(pdev, bar), | |
3749 | pci_resource_len(pdev, bar), res_name)) | |
3750 | goto err_out; | |
3c78bc61 | 3751 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3752 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3753 | pci_resource_len(pdev, bar), res_name, | |
3754 | exclusive)) | |
1da177e4 LT |
3755 | goto err_out; |
3756 | } | |
9ac7849e TH |
3757 | |
3758 | dr = find_pci_dr(pdev); | |
3759 | if (dr) | |
3760 | dr->region_mask |= 1 << bar; | |
3761 | ||
1da177e4 LT |
3762 | return 0; |
3763 | ||
3764 | err_out: | |
7506dc79 | 3765 | pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3766 | &pdev->resource[bar]); |
1da177e4 LT |
3767 | return -EBUSY; |
3768 | } | |
3769 | ||
e8de1481 | 3770 | /** |
74356add BH |
3771 | * pci_request_region - Reserve PCI I/O and memory resource |
3772 | * @pdev: PCI device whose resources are to be reserved | |
3773 | * @bar: BAR to be reserved | |
3774 | * @res_name: Name to be associated with resource | |
e8de1481 | 3775 | * |
74356add BH |
3776 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
3777 | * being reserved by owner @res_name. Do not access any | |
3778 | * address inside the PCI regions unless this call returns | |
3779 | * successfully. | |
e8de1481 | 3780 | * |
74356add BH |
3781 | * Returns 0 on success, or %EBUSY on error. A warning |
3782 | * message is also printed on failure. | |
e8de1481 AV |
3783 | */ |
3784 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3785 | { | |
3786 | return __pci_request_region(pdev, bar, res_name, 0); | |
3787 | } | |
b7fe9434 | 3788 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 | 3789 | |
c87deff7 HS |
3790 | /** |
3791 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3792 | * @pdev: PCI device whose resources were previously reserved | |
3793 | * @bars: Bitmask of BARs to be released | |
3794 | * | |
3795 | * Release selected PCI I/O and memory resources previously reserved. | |
3796 | * Call this function only after all use of the PCI regions has ceased. | |
3797 | */ | |
3798 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3799 | { | |
3800 | int i; | |
3801 | ||
c9c13ba4 | 3802 | for (i = 0; i < PCI_STD_NUM_BARS; i++) |
c87deff7 HS |
3803 | if (bars & (1 << i)) |
3804 | pci_release_region(pdev, i); | |
3805 | } | |
b7fe9434 | 3806 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 3807 | |
9738abed | 3808 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 3809 | const char *res_name, int excl) |
c87deff7 HS |
3810 | { |
3811 | int i; | |
3812 | ||
c9c13ba4 | 3813 | for (i = 0; i < PCI_STD_NUM_BARS; i++) |
c87deff7 | 3814 | if (bars & (1 << i)) |
e8de1481 | 3815 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
3816 | goto err_out; |
3817 | return 0; | |
3818 | ||
3819 | err_out: | |
3c78bc61 | 3820 | while (--i >= 0) |
c87deff7 HS |
3821 | if (bars & (1 << i)) |
3822 | pci_release_region(pdev, i); | |
3823 | ||
3824 | return -EBUSY; | |
3825 | } | |
1da177e4 | 3826 | |
e8de1481 AV |
3827 | |
3828 | /** | |
3829 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
3830 | * @pdev: PCI device whose resources are to be reserved | |
3831 | * @bars: Bitmask of BARs to be requested | |
3832 | * @res_name: Name to be associated with resource | |
3833 | */ | |
3834 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
3835 | const char *res_name) | |
3836 | { | |
3837 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
3838 | } | |
b7fe9434 | 3839 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 3840 | |
3c78bc61 RD |
3841 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
3842 | const char *res_name) | |
e8de1481 AV |
3843 | { |
3844 | return __pci_request_selected_regions(pdev, bars, res_name, | |
3845 | IORESOURCE_EXCLUSIVE); | |
3846 | } | |
b7fe9434 | 3847 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 3848 | |
1da177e4 | 3849 | /** |
74356add BH |
3850 | * pci_release_regions - Release reserved PCI I/O and memory resources |
3851 | * @pdev: PCI device whose resources were previously reserved by | |
3852 | * pci_request_regions() | |
1da177e4 | 3853 | * |
74356add BH |
3854 | * Releases all PCI I/O and memory resources previously reserved by a |
3855 | * successful call to pci_request_regions(). Call this function only | |
3856 | * after all use of the PCI regions has ceased. | |
1da177e4 LT |
3857 | */ |
3858 | ||
3859 | void pci_release_regions(struct pci_dev *pdev) | |
3860 | { | |
c9c13ba4 | 3861 | pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); |
1da177e4 | 3862 | } |
b7fe9434 | 3863 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
3864 | |
3865 | /** | |
74356add BH |
3866 | * pci_request_regions - Reserve PCI I/O and memory resources |
3867 | * @pdev: PCI device whose resources are to be reserved | |
3868 | * @res_name: Name to be associated with resource. | |
1da177e4 | 3869 | * |
74356add BH |
3870 | * Mark all PCI regions associated with PCI device @pdev as |
3871 | * being reserved by owner @res_name. Do not access any | |
3872 | * address inside the PCI regions unless this call returns | |
3873 | * successfully. | |
1da177e4 | 3874 | * |
74356add BH |
3875 | * Returns 0 on success, or %EBUSY on error. A warning |
3876 | * message is also printed on failure. | |
1da177e4 | 3877 | */ |
3c990e92 | 3878 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 3879 | { |
c9c13ba4 DE |
3880 | return pci_request_selected_regions(pdev, |
3881 | ((1 << PCI_STD_NUM_BARS) - 1), res_name); | |
1da177e4 | 3882 | } |
b7fe9434 | 3883 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 3884 | |
e8de1481 | 3885 | /** |
74356add BH |
3886 | * pci_request_regions_exclusive - Reserve PCI I/O and memory resources |
3887 | * @pdev: PCI device whose resources are to be reserved | |
3888 | * @res_name: Name to be associated with resource. | |
e8de1481 | 3889 | * |
74356add BH |
3890 | * Mark all PCI regions associated with PCI device @pdev as being reserved |
3891 | * by owner @res_name. Do not access any address inside the PCI regions | |
3892 | * unless this call returns successfully. | |
e8de1481 | 3893 | * |
74356add BH |
3894 | * pci_request_regions_exclusive() will mark the region so that /dev/mem |
3895 | * and the sysfs MMIO access will not be allowed. | |
e8de1481 | 3896 | * |
74356add BH |
3897 | * Returns 0 on success, or %EBUSY on error. A warning message is also |
3898 | * printed on failure. | |
e8de1481 AV |
3899 | */ |
3900 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
3901 | { | |
3902 | return pci_request_selected_regions_exclusive(pdev, | |
c9c13ba4 | 3903 | ((1 << PCI_STD_NUM_BARS) - 1), res_name); |
e8de1481 | 3904 | } |
b7fe9434 | 3905 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 3906 | |
c5076cfe TN |
3907 | /* |
3908 | * Record the PCI IO range (expressed as CPU physical address + size). | |
74356add | 3909 | * Return a negative value if an error has occurred, zero otherwise |
c5076cfe | 3910 | */ |
fcfaab30 GP |
3911 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
3912 | resource_size_t size) | |
c5076cfe | 3913 | { |
5745392e | 3914 | int ret = 0; |
c5076cfe | 3915 | #ifdef PCI_IOBASE |
5745392e | 3916 | struct logic_pio_hwaddr *range; |
c5076cfe | 3917 | |
5745392e ZY |
3918 | if (!size || addr + size < addr) |
3919 | return -EINVAL; | |
c5076cfe | 3920 | |
c5076cfe | 3921 | range = kzalloc(sizeof(*range), GFP_ATOMIC); |
5745392e ZY |
3922 | if (!range) |
3923 | return -ENOMEM; | |
c5076cfe | 3924 | |
5745392e | 3925 | range->fwnode = fwnode; |
c5076cfe | 3926 | range->size = size; |
5745392e ZY |
3927 | range->hw_start = addr; |
3928 | range->flags = LOGIC_PIO_CPU_MMIO; | |
c5076cfe | 3929 | |
5745392e ZY |
3930 | ret = logic_pio_register_range(range); |
3931 | if (ret) | |
3932 | kfree(range); | |
c5076cfe TN |
3933 | #endif |
3934 | ||
5745392e | 3935 | return ret; |
c5076cfe TN |
3936 | } |
3937 | ||
3938 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
3939 | { | |
3940 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
3941 | ||
3942 | #ifdef PCI_IOBASE | |
5745392e | 3943 | if (pio >= MMIO_UPPER_LIMIT) |
c5076cfe TN |
3944 | return address; |
3945 | ||
5745392e | 3946 | address = logic_pio_to_hwaddr(pio); |
c5076cfe TN |
3947 | #endif |
3948 | ||
3949 | return address; | |
3950 | } | |
3951 | ||
3952 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
3953 | { | |
3954 | #ifdef PCI_IOBASE | |
5745392e | 3955 | return logic_pio_trans_cpuaddr(address); |
c5076cfe TN |
3956 | #else |
3957 | if (address > IO_SPACE_LIMIT) | |
3958 | return (unsigned long)-1; | |
3959 | ||
3960 | return (unsigned long) address; | |
3961 | #endif | |
3962 | } | |
3963 | ||
8b921acf | 3964 | /** |
74356add BH |
3965 | * pci_remap_iospace - Remap the memory mapped I/O space |
3966 | * @res: Resource describing the I/O space | |
3967 | * @phys_addr: physical address of range to be mapped | |
8b921acf | 3968 | * |
74356add BH |
3969 | * Remap the memory mapped I/O space described by the @res and the CPU |
3970 | * physical address @phys_addr into virtual address space. Only | |
3971 | * architectures that have memory mapped IO functions defined (and the | |
3972 | * PCI_IOBASE value defined) should call this function. | |
8b921acf | 3973 | */ |
7b309aef | 3974 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) |
8b921acf LD |
3975 | { |
3976 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3977 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3978 | ||
3979 | if (!(res->flags & IORESOURCE_IO)) | |
3980 | return -EINVAL; | |
3981 | ||
3982 | if (res->end > IO_SPACE_LIMIT) | |
3983 | return -EINVAL; | |
3984 | ||
3985 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
3986 | pgprot_device(PAGE_KERNEL)); | |
3987 | #else | |
74356add BH |
3988 | /* |
3989 | * This architecture does not have memory mapped I/O space, | |
3990 | * so this function should never be called | |
3991 | */ | |
8b921acf LD |
3992 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); |
3993 | return -ENODEV; | |
3994 | #endif | |
3995 | } | |
f90b0875 | 3996 | EXPORT_SYMBOL(pci_remap_iospace); |
8b921acf | 3997 | |
4d3f1384 | 3998 | /** |
74356add BH |
3999 | * pci_unmap_iospace - Unmap the memory mapped I/O space |
4000 | * @res: resource to be unmapped | |
4d3f1384 | 4001 | * |
74356add BH |
4002 | * Unmap the CPU virtual address @res from virtual address space. Only |
4003 | * architectures that have memory mapped IO functions defined (and the | |
4004 | * PCI_IOBASE value defined) should call this function. | |
4d3f1384 SK |
4005 | */ |
4006 | void pci_unmap_iospace(struct resource *res) | |
4007 | { | |
4008 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
4009 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
4010 | ||
4011 | unmap_kernel_range(vaddr, resource_size(res)); | |
4012 | #endif | |
4013 | } | |
f90b0875 | 4014 | EXPORT_SYMBOL(pci_unmap_iospace); |
4d3f1384 | 4015 | |
a5fb9fb0 SS |
4016 | static void devm_pci_unmap_iospace(struct device *dev, void *ptr) |
4017 | { | |
4018 | struct resource **res = ptr; | |
4019 | ||
4020 | pci_unmap_iospace(*res); | |
4021 | } | |
4022 | ||
4023 | /** | |
4024 | * devm_pci_remap_iospace - Managed pci_remap_iospace() | |
4025 | * @dev: Generic device to remap IO address for | |
4026 | * @res: Resource describing the I/O space | |
4027 | * @phys_addr: physical address of range to be mapped | |
4028 | * | |
4029 | * Managed pci_remap_iospace(). Map is automatically unmapped on driver | |
4030 | * detach. | |
4031 | */ | |
4032 | int devm_pci_remap_iospace(struct device *dev, const struct resource *res, | |
4033 | phys_addr_t phys_addr) | |
4034 | { | |
4035 | const struct resource **ptr; | |
4036 | int error; | |
4037 | ||
4038 | ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL); | |
4039 | if (!ptr) | |
4040 | return -ENOMEM; | |
4041 | ||
4042 | error = pci_remap_iospace(res, phys_addr); | |
4043 | if (error) { | |
4044 | devres_free(ptr); | |
4045 | } else { | |
4046 | *ptr = res; | |
4047 | devres_add(dev, ptr); | |
4048 | } | |
4049 | ||
4050 | return error; | |
4051 | } | |
4052 | EXPORT_SYMBOL(devm_pci_remap_iospace); | |
4053 | ||
490cb6dd LP |
4054 | /** |
4055 | * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace() | |
4056 | * @dev: Generic device to remap IO address for | |
4057 | * @offset: Resource address to map | |
4058 | * @size: Size of map | |
4059 | * | |
4060 | * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver | |
4061 | * detach. | |
4062 | */ | |
4063 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, | |
4064 | resource_size_t offset, | |
4065 | resource_size_t size) | |
4066 | { | |
4067 | void __iomem **ptr, *addr; | |
4068 | ||
4069 | ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); | |
4070 | if (!ptr) | |
4071 | return NULL; | |
4072 | ||
4073 | addr = pci_remap_cfgspace(offset, size); | |
4074 | if (addr) { | |
4075 | *ptr = addr; | |
4076 | devres_add(dev, ptr); | |
4077 | } else | |
4078 | devres_free(ptr); | |
4079 | ||
4080 | return addr; | |
4081 | } | |
4082 | EXPORT_SYMBOL(devm_pci_remap_cfgspace); | |
4083 | ||
4084 | /** | |
4085 | * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource | |
4086 | * @dev: generic device to handle the resource for | |
4087 | * @res: configuration space resource to be handled | |
4088 | * | |
4089 | * Checks that a resource is a valid memory region, requests the memory | |
4090 | * region and ioremaps with pci_remap_cfgspace() API that ensures the | |
4091 | * proper PCI configuration space memory attributes are guaranteed. | |
4092 | * | |
4093 | * All operations are managed and will be undone on driver detach. | |
4094 | * | |
4095 | * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code | |
505fb746 | 4096 | * on failure. Usage example:: |
490cb6dd LP |
4097 | * |
4098 | * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
4099 | * base = devm_pci_remap_cfg_resource(&pdev->dev, res); | |
4100 | * if (IS_ERR(base)) | |
4101 | * return PTR_ERR(base); | |
4102 | */ | |
4103 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
4104 | struct resource *res) | |
4105 | { | |
4106 | resource_size_t size; | |
4107 | const char *name; | |
4108 | void __iomem *dest_ptr; | |
4109 | ||
4110 | BUG_ON(!dev); | |
4111 | ||
4112 | if (!res || resource_type(res) != IORESOURCE_MEM) { | |
4113 | dev_err(dev, "invalid resource\n"); | |
4114 | return IOMEM_ERR_PTR(-EINVAL); | |
4115 | } | |
4116 | ||
4117 | size = resource_size(res); | |
4118 | name = res->name ?: dev_name(dev); | |
4119 | ||
4120 | if (!devm_request_mem_region(dev, res->start, size, name)) { | |
4121 | dev_err(dev, "can't request region for resource %pR\n", res); | |
4122 | return IOMEM_ERR_PTR(-EBUSY); | |
4123 | } | |
4124 | ||
4125 | dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); | |
4126 | if (!dest_ptr) { | |
4127 | dev_err(dev, "ioremap failed for resource %pR\n", res); | |
4128 | devm_release_mem_region(dev, res->start, size); | |
4129 | dest_ptr = IOMEM_ERR_PTR(-ENOMEM); | |
4130 | } | |
4131 | ||
4132 | return dest_ptr; | |
4133 | } | |
4134 | EXPORT_SYMBOL(devm_pci_remap_cfg_resource); | |
4135 | ||
6a479079 BH |
4136 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
4137 | { | |
4138 | u16 old_cmd, cmd; | |
4139 | ||
4140 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
4141 | if (enable) | |
4142 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
4143 | else | |
4144 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
4145 | if (cmd != old_cmd) { | |
7506dc79 | 4146 | pci_dbg(dev, "%s bus mastering\n", |
6a479079 BH |
4147 | enable ? "enabling" : "disabling"); |
4148 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4149 | } | |
4150 | dev->is_busmaster = enable; | |
4151 | } | |
e8de1481 | 4152 | |
2b6f2c35 MS |
4153 | /** |
4154 | * pcibios_setup - process "pci=" kernel boot arguments | |
4155 | * @str: string used to pass in "pci=" kernel boot arguments | |
4156 | * | |
4157 | * Process kernel boot arguments. This is the default implementation. | |
4158 | * Architecture specific implementations can override this as necessary. | |
4159 | */ | |
4160 | char * __weak __init pcibios_setup(char *str) | |
4161 | { | |
4162 | return str; | |
4163 | } | |
4164 | ||
96c55900 MS |
4165 | /** |
4166 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
4167 | * @dev: the PCI device to enable | |
4168 | * | |
4169 | * Enables PCI bus-mastering for the device. This is the default | |
4170 | * implementation. Architecture specific implementations can override | |
4171 | * this if necessary. | |
4172 | */ | |
4173 | void __weak pcibios_set_master(struct pci_dev *dev) | |
4174 | { | |
4175 | u8 lat; | |
4176 | ||
f676678f MS |
4177 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
4178 | if (pci_is_pcie(dev)) | |
4179 | return; | |
4180 | ||
96c55900 MS |
4181 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
4182 | if (lat < 16) | |
4183 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
4184 | else if (lat > pcibios_max_latency) | |
4185 | lat = pcibios_max_latency; | |
4186 | else | |
4187 | return; | |
a006482b | 4188 | |
96c55900 MS |
4189 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
4190 | } | |
4191 | ||
1da177e4 LT |
4192 | /** |
4193 | * pci_set_master - enables bus-mastering for device dev | |
4194 | * @dev: the PCI device to enable | |
4195 | * | |
4196 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
4197 | * to do the needed arch specific settings. | |
4198 | */ | |
6a479079 | 4199 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 4200 | { |
6a479079 | 4201 | __pci_set_master(dev, true); |
1da177e4 LT |
4202 | pcibios_set_master(dev); |
4203 | } | |
b7fe9434 | 4204 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 4205 | |
6a479079 BH |
4206 | /** |
4207 | * pci_clear_master - disables bus-mastering for device dev | |
4208 | * @dev: the PCI device to disable | |
4209 | */ | |
4210 | void pci_clear_master(struct pci_dev *dev) | |
4211 | { | |
4212 | __pci_set_master(dev, false); | |
4213 | } | |
b7fe9434 | 4214 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 4215 | |
1da177e4 | 4216 | /** |
edb2d97e MW |
4217 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
4218 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 4219 | * |
edb2d97e MW |
4220 | * Helper function for pci_set_mwi. |
4221 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
4222 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
4223 | * | |
4224 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4225 | */ | |
15ea76d4 | 4226 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
4227 | { |
4228 | u8 cacheline_size; | |
4229 | ||
4230 | if (!pci_cache_line_size) | |
15ea76d4 | 4231 | return -EINVAL; |
1da177e4 LT |
4232 | |
4233 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
4234 | equal to or multiple of the right value. */ | |
4235 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4236 | if (cacheline_size >= pci_cache_line_size && | |
4237 | (cacheline_size % pci_cache_line_size) == 0) | |
4238 | return 0; | |
4239 | ||
4240 | /* Write the correct value. */ | |
4241 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
4242 | /* Read it back. */ | |
4243 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
4244 | if (cacheline_size == pci_cache_line_size) | |
4245 | return 0; | |
4246 | ||
34c6b710 | 4247 | pci_info(dev, "cache line size of %d is not supported\n", |
227f0647 | 4248 | pci_cache_line_size << 2); |
1da177e4 LT |
4249 | |
4250 | return -EINVAL; | |
4251 | } | |
15ea76d4 TH |
4252 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
4253 | ||
1da177e4 LT |
4254 | /** |
4255 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
4256 | * @dev: the PCI device for which MWI is enabled | |
4257 | * | |
694625c0 | 4258 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
4259 | * |
4260 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4261 | */ | |
3c78bc61 | 4262 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 4263 | { |
b7fe9434 RD |
4264 | #ifdef PCI_DISABLE_MWI |
4265 | return 0; | |
4266 | #else | |
1da177e4 LT |
4267 | int rc; |
4268 | u16 cmd; | |
4269 | ||
edb2d97e | 4270 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
4271 | if (rc) |
4272 | return rc; | |
4273 | ||
4274 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 4275 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
7506dc79 | 4276 | pci_dbg(dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
4277 | cmd |= PCI_COMMAND_INVALIDATE; |
4278 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4279 | } | |
1da177e4 | 4280 | return 0; |
b7fe9434 | 4281 | #endif |
1da177e4 | 4282 | } |
b7fe9434 | 4283 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 4284 | |
fc0f9f4d HK |
4285 | /** |
4286 | * pcim_set_mwi - a device-managed pci_set_mwi() | |
4287 | * @dev: the PCI device for which MWI is enabled | |
4288 | * | |
4289 | * Managed pci_set_mwi(). | |
4290 | * | |
4291 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4292 | */ | |
4293 | int pcim_set_mwi(struct pci_dev *dev) | |
4294 | { | |
4295 | struct pci_devres *dr; | |
4296 | ||
4297 | dr = find_pci_dr(dev); | |
4298 | if (!dr) | |
4299 | return -ENOMEM; | |
4300 | ||
4301 | dr->mwi = 1; | |
4302 | return pci_set_mwi(dev); | |
4303 | } | |
4304 | EXPORT_SYMBOL(pcim_set_mwi); | |
4305 | ||
694625c0 RD |
4306 | /** |
4307 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
4308 | * @dev: the PCI device for which MWI is enabled | |
4309 | * | |
4310 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
4311 | * Callers are not required to check the return value. | |
4312 | * | |
4313 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
4314 | */ | |
4315 | int pci_try_set_mwi(struct pci_dev *dev) | |
4316 | { | |
b7fe9434 RD |
4317 | #ifdef PCI_DISABLE_MWI |
4318 | return 0; | |
4319 | #else | |
4320 | return pci_set_mwi(dev); | |
4321 | #endif | |
694625c0 | 4322 | } |
b7fe9434 | 4323 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 4324 | |
1da177e4 LT |
4325 | /** |
4326 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
4327 | * @dev: the PCI device to disable | |
4328 | * | |
4329 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
4330 | */ | |
3c78bc61 | 4331 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 4332 | { |
b7fe9434 | 4333 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
4334 | u16 cmd; |
4335 | ||
4336 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4337 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
4338 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
4339 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4340 | } | |
b7fe9434 | 4341 | #endif |
1da177e4 | 4342 | } |
b7fe9434 | 4343 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 4344 | |
a04ce0ff BR |
4345 | /** |
4346 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
4347 | * @pdev: the PCI device to operate on |
4348 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff | 4349 | * |
74356add | 4350 | * Enables/disables PCI INTx for device @pdev |
a04ce0ff | 4351 | */ |
3c78bc61 | 4352 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
4353 | { |
4354 | u16 pci_command, new; | |
4355 | ||
4356 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
4357 | ||
3c78bc61 | 4358 | if (enable) |
a04ce0ff | 4359 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 4360 | else |
a04ce0ff | 4361 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
4362 | |
4363 | if (new != pci_command) { | |
9ac7849e TH |
4364 | struct pci_devres *dr; |
4365 | ||
2fd9d74b | 4366 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
4367 | |
4368 | dr = find_pci_dr(pdev); | |
4369 | if (dr && !dr->restore_intx) { | |
4370 | dr->restore_intx = 1; | |
4371 | dr->orig_intx = !enable; | |
4372 | } | |
a04ce0ff BR |
4373 | } |
4374 | } | |
b7fe9434 | 4375 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 4376 | |
a2e27787 JK |
4377 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) |
4378 | { | |
4379 | struct pci_bus *bus = dev->bus; | |
4380 | bool mask_updated = true; | |
4381 | u32 cmd_status_dword; | |
4382 | u16 origcmd, newcmd; | |
4383 | unsigned long flags; | |
4384 | bool irq_pending; | |
4385 | ||
4386 | /* | |
4387 | * We do a single dword read to retrieve both command and status. | |
4388 | * Document assumptions that make this possible. | |
4389 | */ | |
4390 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
4391 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
4392 | ||
4393 | raw_spin_lock_irqsave(&pci_lock, flags); | |
4394 | ||
4395 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
4396 | ||
4397 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
4398 | ||
4399 | /* | |
4400 | * Check interrupt status register to see whether our device | |
4401 | * triggered the interrupt (when masking) or the next IRQ is | |
4402 | * already pending (when unmasking). | |
4403 | */ | |
4404 | if (mask != irq_pending) { | |
4405 | mask_updated = false; | |
4406 | goto done; | |
4407 | } | |
4408 | ||
4409 | origcmd = cmd_status_dword; | |
4410 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
4411 | if (mask) | |
4412 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
4413 | if (newcmd != origcmd) | |
4414 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
4415 | ||
4416 | done: | |
4417 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
4418 | ||
4419 | return mask_updated; | |
4420 | } | |
4421 | ||
4422 | /** | |
4423 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 4424 | * @dev: the PCI device to operate on |
a2e27787 | 4425 | * |
74356add BH |
4426 | * Check if the device dev has its INTx line asserted, mask it and return |
4427 | * true in that case. False is returned if no interrupt was pending. | |
a2e27787 JK |
4428 | */ |
4429 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
4430 | { | |
4431 | return pci_check_and_set_intx_mask(dev, true); | |
4432 | } | |
4433 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
4434 | ||
4435 | /** | |
ebd50b93 | 4436 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 4437 | * @dev: the PCI device to operate on |
a2e27787 | 4438 | * |
74356add BH |
4439 | * Check if the device dev has its INTx line asserted, unmask it if not and |
4440 | * return true. False is returned and the mask remains active if there was | |
4441 | * still an interrupt pending. | |
a2e27787 JK |
4442 | */ |
4443 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
4444 | { | |
4445 | return pci_check_and_set_intx_mask(dev, false); | |
4446 | } | |
4447 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
4448 | ||
3775a209 | 4449 | /** |
74356add | 4450 | * pci_wait_for_pending_transaction - wait for pending transaction |
3775a209 CL |
4451 | * @dev: the PCI device to operate on |
4452 | * | |
4453 | * Return 0 if transaction is pending 1 otherwise. | |
4454 | */ | |
4455 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 4456 | { |
157e876f AW |
4457 | if (!pci_is_pcie(dev)) |
4458 | return 1; | |
8c1c699f | 4459 | |
d0b4cc4e GS |
4460 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
4461 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
4462 | } |
4463 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
4464 | ||
a60a2b73 CH |
4465 | /** |
4466 | * pcie_has_flr - check if a device supports function level resets | |
74356add | 4467 | * @dev: device to check |
a60a2b73 CH |
4468 | * |
4469 | * Returns true if the device advertises support for PCIe function level | |
4470 | * resets. | |
4471 | */ | |
2d2917f7 | 4472 | bool pcie_has_flr(struct pci_dev *dev) |
3775a209 CL |
4473 | { |
4474 | u32 cap; | |
4475 | ||
f65fd1aa | 4476 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
a60a2b73 | 4477 | return false; |
3775a209 | 4478 | |
a60a2b73 CH |
4479 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
4480 | return cap & PCI_EXP_DEVCAP_FLR; | |
4481 | } | |
2d2917f7 | 4482 | EXPORT_SYMBOL_GPL(pcie_has_flr); |
3775a209 | 4483 | |
a60a2b73 CH |
4484 | /** |
4485 | * pcie_flr - initiate a PCIe function level reset | |
74356add | 4486 | * @dev: device to reset |
a60a2b73 CH |
4487 | * |
4488 | * Initiate a function level reset on @dev. The caller should ensure the | |
4489 | * device supports FLR before calling this function, e.g. by using the | |
4490 | * pcie_has_flr() helper. | |
4491 | */ | |
91295d79 | 4492 | int pcie_flr(struct pci_dev *dev) |
a60a2b73 | 4493 | { |
3775a209 | 4494 | if (!pci_wait_for_pending_transaction(dev)) |
7506dc79 | 4495 | pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 4496 | |
59875ae4 | 4497 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
a2758b6b | 4498 | |
d6112f8d FB |
4499 | if (dev->imm_ready) |
4500 | return 0; | |
4501 | ||
a2758b6b SK |
4502 | /* |
4503 | * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within | |
4504 | * 100ms, but may silently discard requests while the FLR is in | |
4505 | * progress. Wait 100ms before trying to access the device. | |
4506 | */ | |
4507 | msleep(100); | |
4508 | ||
4509 | return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); | |
8dd7f803 | 4510 | } |
a60a2b73 | 4511 | EXPORT_SYMBOL_GPL(pcie_flr); |
d91cdc74 | 4512 | |
8c1c699f | 4513 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 4514 | { |
8c1c699f | 4515 | int pos; |
1ca88797 SY |
4516 | u8 cap; |
4517 | ||
8c1c699f YZ |
4518 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
4519 | if (!pos) | |
1ca88797 | 4520 | return -ENOTTY; |
8c1c699f | 4521 | |
f65fd1aa SN |
4522 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
4523 | return -ENOTTY; | |
4524 | ||
8c1c699f | 4525 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); |
1ca88797 SY |
4526 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
4527 | return -ENOTTY; | |
4528 | ||
4529 | if (probe) | |
4530 | return 0; | |
4531 | ||
d066c946 AW |
4532 | /* |
4533 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
f6b6aefe | 4534 | * is used, so we use the control offset rather than status and shift |
d066c946 AW |
4535 | * the test bit to match. |
4536 | */ | |
bb383e28 | 4537 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 4538 | PCI_AF_STATUS_TP << 8)) |
7506dc79 | 4539 | pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 4540 | |
8c1c699f | 4541 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
a2758b6b | 4542 | |
d6112f8d FB |
4543 | if (dev->imm_ready) |
4544 | return 0; | |
4545 | ||
a2758b6b SK |
4546 | /* |
4547 | * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, | |
4548 | * updated 27 July 2006; a device must complete an FLR within | |
4549 | * 100ms, but may silently discard requests while the FLR is in | |
4550 | * progress. Wait 100ms before trying to access the device. | |
4551 | */ | |
4552 | msleep(100); | |
4553 | ||
4554 | return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); | |
1ca88797 SY |
4555 | } |
4556 | ||
83d74e03 RW |
4557 | /** |
4558 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
4559 | * @dev: Device to reset. | |
4560 | * @probe: If set, only check if the device can be reset this way. | |
4561 | * | |
4562 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
4563 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
4564 | * PCI_D0. If that's the case and the device is not in a low-power state | |
4565 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
4566 | * | |
4567 | * NOTE: This causes the caller to sleep for twice the device power transition | |
4568 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 4569 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
4570 | * Moreover, only devices in D0 can be reset by this function. |
4571 | */ | |
f85876ba | 4572 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 4573 | { |
f85876ba YZ |
4574 | u16 csr; |
4575 | ||
51e53738 | 4576 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 4577 | return -ENOTTY; |
d91cdc74 | 4578 | |
f85876ba YZ |
4579 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
4580 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
4581 | return -ENOTTY; | |
d91cdc74 | 4582 | |
f85876ba YZ |
4583 | if (probe) |
4584 | return 0; | |
1ca88797 | 4585 | |
f85876ba YZ |
4586 | if (dev->current_state != PCI_D0) |
4587 | return -EINVAL; | |
4588 | ||
4589 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4590 | csr |= PCI_D3hot; | |
4591 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4592 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
4593 | |
4594 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4595 | csr |= PCI_D0; | |
4596 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4597 | pci_dev_d3_sleep(dev); |
f85876ba | 4598 | |
993cc6d1 | 4599 | return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); |
f85876ba | 4600 | } |
4827d638 | 4601 | |
9f5a70f1 | 4602 | /** |
4827d638 | 4603 | * pcie_wait_for_link_delay - Wait until link is active or inactive |
9f5a70f1 OP |
4604 | * @pdev: Bridge device |
4605 | * @active: waiting for active or inactive? | |
4827d638 | 4606 | * @delay: Delay to wait after link has become active (in ms) |
9f5a70f1 OP |
4607 | * |
4608 | * Use this to wait till link becomes active or inactive. | |
4609 | */ | |
4827d638 MW |
4610 | static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, |
4611 | int delay) | |
9f5a70f1 OP |
4612 | { |
4613 | int timeout = 1000; | |
4614 | bool ret; | |
4615 | u16 lnk_status; | |
4616 | ||
f0157160 KB |
4617 | /* |
4618 | * Some controllers might not implement link active reporting. In this | |
4619 | * case, we wait for 1000 + 100 ms. | |
4620 | */ | |
4621 | if (!pdev->link_active_reporting) { | |
4622 | msleep(1100); | |
4623 | return true; | |
4624 | } | |
4625 | ||
4626 | /* | |
4627 | * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms, | |
4628 | * after which we should expect an link active if the reset was | |
4629 | * successful. If so, software must wait a minimum 100ms before sending | |
4630 | * configuration requests to devices downstream this port. | |
4631 | * | |
4632 | * If the link fails to activate, either the device was physically | |
4633 | * removed or the link is permanently failed. | |
4634 | */ | |
4635 | if (active) | |
4636 | msleep(20); | |
9f5a70f1 OP |
4637 | for (;;) { |
4638 | pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); | |
4639 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | |
4640 | if (ret == active) | |
f0157160 | 4641 | break; |
9f5a70f1 OP |
4642 | if (timeout <= 0) |
4643 | break; | |
4644 | msleep(10); | |
4645 | timeout -= 10; | |
4646 | } | |
f0157160 | 4647 | if (active && ret) |
4827d638 | 4648 | msleep(delay); |
f0157160 KB |
4649 | else if (ret != active) |
4650 | pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n", | |
4651 | active ? "set" : "cleared"); | |
4652 | return ret == active; | |
9f5a70f1 | 4653 | } |
f85876ba | 4654 | |
4827d638 MW |
4655 | /** |
4656 | * pcie_wait_for_link - Wait until link is active or inactive | |
4657 | * @pdev: Bridge device | |
4658 | * @active: waiting for active or inactive? | |
4659 | * | |
4660 | * Use this to wait till link becomes active or inactive. | |
4661 | */ | |
4662 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active) | |
4663 | { | |
4664 | return pcie_wait_for_link_delay(pdev, active, 100); | |
4665 | } | |
4666 | ||
ad9001f2 MW |
4667 | /* |
4668 | * Find maximum D3cold delay required by all the devices on the bus. The | |
4669 | * spec says 100 ms, but firmware can lower it and we allow drivers to | |
4670 | * increase it as well. | |
4671 | * | |
4672 | * Called with @pci_bus_sem locked for reading. | |
4673 | */ | |
4674 | static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) | |
4675 | { | |
4676 | const struct pci_dev *pdev; | |
4677 | int min_delay = 100; | |
4678 | int max_delay = 0; | |
4679 | ||
4680 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
4681 | if (pdev->d3cold_delay < min_delay) | |
4682 | min_delay = pdev->d3cold_delay; | |
4683 | if (pdev->d3cold_delay > max_delay) | |
4684 | max_delay = pdev->d3cold_delay; | |
4685 | } | |
4686 | ||
4687 | return max(min_delay, max_delay); | |
4688 | } | |
4689 | ||
4690 | /** | |
4691 | * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible | |
4692 | * @dev: PCI bridge | |
4693 | * | |
4694 | * Handle necessary delays before access to the devices on the secondary | |
4695 | * side of the bridge are permitted after D3cold to D0 transition. | |
4696 | * | |
4697 | * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For | |
4698 | * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section | |
4699 | * 4.3.2. | |
4700 | */ | |
4701 | void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev) | |
4702 | { | |
4703 | struct pci_dev *child; | |
4704 | int delay; | |
4705 | ||
4706 | if (pci_dev_is_disconnected(dev)) | |
4707 | return; | |
4708 | ||
4709 | if (!pci_is_bridge(dev) || !dev->bridge_d3) | |
4710 | return; | |
4711 | ||
4712 | down_read(&pci_bus_sem); | |
4713 | ||
4714 | /* | |
4715 | * We only deal with devices that are present currently on the bus. | |
4716 | * For any hot-added devices the access delay is handled in pciehp | |
4717 | * board_added(). In case of ACPI hotplug the firmware is expected | |
4718 | * to configure the devices before OS is notified. | |
4719 | */ | |
4720 | if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { | |
4721 | up_read(&pci_bus_sem); | |
4722 | return; | |
4723 | } | |
4724 | ||
4725 | /* Take d3cold_delay requirements into account */ | |
4726 | delay = pci_bus_max_d3cold_delay(dev->subordinate); | |
4727 | if (!delay) { | |
4728 | up_read(&pci_bus_sem); | |
4729 | return; | |
4730 | } | |
4731 | ||
4732 | child = list_first_entry(&dev->subordinate->devices, struct pci_dev, | |
4733 | bus_list); | |
4734 | up_read(&pci_bus_sem); | |
4735 | ||
4736 | /* | |
4737 | * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before | |
4738 | * accessing the device after reset (that is 1000 ms + 100 ms). In | |
4739 | * practice this should not be needed because we don't do power | |
4740 | * management for them (see pci_bridge_d3_possible()). | |
4741 | */ | |
4742 | if (!pci_is_pcie(dev)) { | |
4743 | pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay); | |
4744 | msleep(1000 + delay); | |
4745 | return; | |
4746 | } | |
4747 | ||
4748 | /* | |
4749 | * For PCIe downstream and root ports that do not support speeds | |
4750 | * greater than 5 GT/s need to wait minimum 100 ms. For higher | |
4751 | * speeds (gen3) we need to wait first for the data link layer to | |
4752 | * become active. | |
4753 | * | |
4754 | * However, 100 ms is the minimum and the PCIe spec says the | |
4755 | * software must allow at least 1s before it can determine that the | |
4756 | * device that did not respond is a broken device. There is | |
4757 | * evidence that 100 ms is not always enough, for example certain | |
4758 | * Titan Ridge xHCI controller does not always respond to | |
4759 | * configuration requests if we only wait for 100 ms (see | |
4760 | * https://bugzilla.kernel.org/show_bug.cgi?id=203885). | |
4761 | * | |
4762 | * Therefore we wait for 100 ms and check for the device presence. | |
4763 | * If it is still not present give it an additional 100 ms. | |
4764 | */ | |
4765 | if (!pcie_downstream_port(dev)) | |
4766 | return; | |
4767 | ||
4768 | if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) { | |
4769 | pci_dbg(dev, "waiting %d ms for downstream link\n", delay); | |
4770 | msleep(delay); | |
4771 | } else { | |
4772 | pci_dbg(dev, "waiting %d ms for downstream link, after activation\n", | |
4773 | delay); | |
4774 | if (!pcie_wait_for_link_delay(dev, true, delay)) { | |
4775 | /* Did not train, no need to wait any further */ | |
4776 | return; | |
4777 | } | |
4778 | } | |
4779 | ||
4780 | if (!pci_device_is_present(child)) { | |
4781 | pci_dbg(child, "waiting additional %d ms to become accessible\n", delay); | |
4782 | msleep(delay); | |
4783 | } | |
4784 | } | |
4785 | ||
9e33002f | 4786 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
4787 | { |
4788 | u16 ctrl; | |
64e8674f AW |
4789 | |
4790 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
4791 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
4792 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
df62ab5e | 4793 | |
de0c548c AW |
4794 | /* |
4795 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 4796 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
4797 | */ |
4798 | msleep(2); | |
64e8674f AW |
4799 | |
4800 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
4801 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
4802 | |
4803 | /* | |
4804 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
4805 | * Assuming a minimum 33MHz clock this results in a 1s | |
4806 | * delay before we can consider subordinate devices to | |
4807 | * be re-initialized. PCIe has some ways to shorten this, | |
4808 | * but we don't make use of them yet. | |
4809 | */ | |
4810 | ssleep(1); | |
64e8674f | 4811 | } |
d92a208d | 4812 | |
9e33002f GS |
4813 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
4814 | { | |
4815 | pci_reset_secondary_bus(dev); | |
4816 | } | |
4817 | ||
d92a208d | 4818 | /** |
381634ca | 4819 | * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge. |
d92a208d GS |
4820 | * @dev: Bridge device |
4821 | * | |
4822 | * Use the bridge control register to assert reset on the secondary bus. | |
4823 | * Devices on the secondary bus are left in power-on state. | |
4824 | */ | |
381634ca | 4825 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev) |
d92a208d GS |
4826 | { |
4827 | pcibios_reset_secondary_bus(dev); | |
01fd61c0 | 4828 | |
6b2f1351 | 4829 | return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); |
d92a208d | 4830 | } |
bfc45606 | 4831 | EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset); |
64e8674f AW |
4832 | |
4833 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
4834 | { | |
c12ff1df YZ |
4835 | struct pci_dev *pdev; |
4836 | ||
f331a859 AW |
4837 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
4838 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
4839 | return -ENOTTY; |
4840 | ||
4841 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4842 | if (pdev != dev) | |
4843 | return -ENOTTY; | |
4844 | ||
4845 | if (probe) | |
4846 | return 0; | |
4847 | ||
381634ca | 4848 | return pci_bridge_secondary_bus_reset(dev->bus->self); |
c12ff1df YZ |
4849 | } |
4850 | ||
608c3881 AW |
4851 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
4852 | { | |
4853 | int rc = -ENOTTY; | |
4854 | ||
81c4b5bf | 4855 | if (!hotplug || !try_module_get(hotplug->owner)) |
608c3881 AW |
4856 | return rc; |
4857 | ||
4858 | if (hotplug->ops->reset_slot) | |
4859 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
4860 | ||
81c4b5bf | 4861 | module_put(hotplug->owner); |
608c3881 AW |
4862 | |
4863 | return rc; | |
4864 | } | |
4865 | ||
4866 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
4867 | { | |
4868 | struct pci_dev *pdev; | |
4869 | ||
f331a859 AW |
4870 | if (dev->subordinate || !dev->slot || |
4871 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
4872 | return -ENOTTY; |
4873 | ||
4874 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4875 | if (pdev != dev && pdev->slot == dev->slot) | |
4876 | return -ENOTTY; | |
4877 | ||
4878 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
4879 | } | |
4880 | ||
77cb985a AW |
4881 | static void pci_dev_lock(struct pci_dev *dev) |
4882 | { | |
4883 | pci_cfg_access_lock(dev); | |
4884 | /* block PM suspend, driver probe, etc. */ | |
4885 | device_lock(&dev->dev); | |
4886 | } | |
4887 | ||
61cf16d8 AW |
4888 | /* Return 1 on successful lock, 0 on contention */ |
4889 | static int pci_dev_trylock(struct pci_dev *dev) | |
4890 | { | |
4891 | if (pci_cfg_access_trylock(dev)) { | |
4892 | if (device_trylock(&dev->dev)) | |
4893 | return 1; | |
4894 | pci_cfg_access_unlock(dev); | |
4895 | } | |
4896 | ||
4897 | return 0; | |
4898 | } | |
4899 | ||
77cb985a AW |
4900 | static void pci_dev_unlock(struct pci_dev *dev) |
4901 | { | |
4902 | device_unlock(&dev->dev); | |
4903 | pci_cfg_access_unlock(dev); | |
4904 | } | |
4905 | ||
775755ed | 4906 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3ebe7f9f KB |
4907 | { |
4908 | const struct pci_error_handlers *err_handler = | |
4909 | dev->driver ? dev->driver->err_handler : NULL; | |
3ebe7f9f | 4910 | |
b014e96d | 4911 | /* |
775755ed | 4912 | * dev->driver->err_handler->reset_prepare() is protected against |
b014e96d CH |
4913 | * races with ->remove() by the device lock, which must be held by |
4914 | * the caller. | |
4915 | */ | |
775755ed CH |
4916 | if (err_handler && err_handler->reset_prepare) |
4917 | err_handler->reset_prepare(dev); | |
3ebe7f9f | 4918 | |
a6cbaade AW |
4919 | /* |
4920 | * Wake-up device prior to save. PM registers default to D0 after | |
4921 | * reset and a simple register restore doesn't reliably return | |
4922 | * to a non-D0 state anyway. | |
4923 | */ | |
4924 | pci_set_power_state(dev, PCI_D0); | |
4925 | ||
77cb985a AW |
4926 | pci_save_state(dev); |
4927 | /* | |
4928 | * Disable the device by clearing the Command register, except for | |
4929 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
4930 | * BARs, but also prevents the device from being Bus Master, preventing | |
4931 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
4932 | * compliant devices, INTx-disable prevents legacy interrupts. | |
4933 | */ | |
4934 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
4935 | } | |
4936 | ||
4937 | static void pci_dev_restore(struct pci_dev *dev) | |
4938 | { | |
775755ed CH |
4939 | const struct pci_error_handlers *err_handler = |
4940 | dev->driver ? dev->driver->err_handler : NULL; | |
977f857c | 4941 | |
77cb985a | 4942 | pci_restore_state(dev); |
77cb985a | 4943 | |
775755ed CH |
4944 | /* |
4945 | * dev->driver->err_handler->reset_done() is protected against | |
4946 | * races with ->remove() by the device lock, which must be held by | |
4947 | * the caller. | |
4948 | */ | |
4949 | if (err_handler && err_handler->reset_done) | |
4950 | err_handler->reset_done(dev); | |
d91cdc74 | 4951 | } |
3ebe7f9f | 4952 | |
6fbf9e7a KRW |
4953 | /** |
4954 | * __pci_reset_function_locked - reset a PCI device function while holding | |
4955 | * the @dev mutex lock. | |
4956 | * @dev: PCI device to reset | |
4957 | * | |
4958 | * Some devices allow an individual function to be reset without affecting | |
4959 | * other functions in the same device. The PCI device must be responsive | |
4960 | * to PCI config space in order to use this function. | |
4961 | * | |
4962 | * The device function is presumed to be unused and the caller is holding | |
4963 | * the device mutex lock when this function is called. | |
74356add | 4964 | * |
6fbf9e7a KRW |
4965 | * Resetting the device will make the contents of PCI configuration space |
4966 | * random, so any caller of this must be prepared to reinitialise the | |
4967 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
4968 | * etc. | |
4969 | * | |
4970 | * Returns 0 if the device function was successfully reset or negative if the | |
4971 | * device doesn't support resetting a single function. | |
4972 | */ | |
4973 | int __pci_reset_function_locked(struct pci_dev *dev) | |
4974 | { | |
52354b9d CH |
4975 | int rc; |
4976 | ||
4977 | might_sleep(); | |
4978 | ||
832c418a BH |
4979 | /* |
4980 | * A reset method returns -ENOTTY if it doesn't support this device | |
4981 | * and we should try the next method. | |
4982 | * | |
4983 | * If it returns 0 (success), we're finished. If it returns any | |
4984 | * other error, we're also finished: this indicates that further | |
4985 | * reset mechanisms might be broken on the device. | |
4986 | */ | |
52354b9d CH |
4987 | rc = pci_dev_specific_reset(dev, 0); |
4988 | if (rc != -ENOTTY) | |
4989 | return rc; | |
4990 | if (pcie_has_flr(dev)) { | |
91295d79 SK |
4991 | rc = pcie_flr(dev); |
4992 | if (rc != -ENOTTY) | |
4993 | return rc; | |
52354b9d CH |
4994 | } |
4995 | rc = pci_af_flr(dev, 0); | |
4996 | if (rc != -ENOTTY) | |
4997 | return rc; | |
4998 | rc = pci_pm_reset(dev, 0); | |
4999 | if (rc != -ENOTTY) | |
5000 | return rc; | |
5001 | rc = pci_dev_reset_slot_function(dev, 0); | |
5002 | if (rc != -ENOTTY) | |
5003 | return rc; | |
5004 | return pci_parent_bus_reset(dev, 0); | |
6fbf9e7a KRW |
5005 | } |
5006 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
5007 | ||
711d5779 MT |
5008 | /** |
5009 | * pci_probe_reset_function - check whether the device can be safely reset | |
5010 | * @dev: PCI device to reset | |
5011 | * | |
5012 | * Some devices allow an individual function to be reset without affecting | |
5013 | * other functions in the same device. The PCI device must be responsive | |
5014 | * to PCI config space in order to use this function. | |
5015 | * | |
5016 | * Returns 0 if the device function can be reset or negative if the | |
5017 | * device doesn't support resetting a single function. | |
5018 | */ | |
5019 | int pci_probe_reset_function(struct pci_dev *dev) | |
5020 | { | |
52354b9d CH |
5021 | int rc; |
5022 | ||
5023 | might_sleep(); | |
5024 | ||
5025 | rc = pci_dev_specific_reset(dev, 1); | |
5026 | if (rc != -ENOTTY) | |
5027 | return rc; | |
5028 | if (pcie_has_flr(dev)) | |
5029 | return 0; | |
5030 | rc = pci_af_flr(dev, 1); | |
5031 | if (rc != -ENOTTY) | |
5032 | return rc; | |
5033 | rc = pci_pm_reset(dev, 1); | |
5034 | if (rc != -ENOTTY) | |
5035 | return rc; | |
5036 | rc = pci_dev_reset_slot_function(dev, 1); | |
5037 | if (rc != -ENOTTY) | |
5038 | return rc; | |
5039 | ||
5040 | return pci_parent_bus_reset(dev, 1); | |
711d5779 MT |
5041 | } |
5042 | ||
8dd7f803 | 5043 | /** |
8c1c699f YZ |
5044 | * pci_reset_function - quiesce and reset a PCI device function |
5045 | * @dev: PCI device to reset | |
8dd7f803 SY |
5046 | * |
5047 | * Some devices allow an individual function to be reset without affecting | |
5048 | * other functions in the same device. The PCI device must be responsive | |
5049 | * to PCI config space in order to use this function. | |
5050 | * | |
5051 | * This function does not just reset the PCI portion of a device, but | |
5052 | * clears all the state associated with the device. This function differs | |
79e699b6 JS |
5053 | * from __pci_reset_function_locked() in that it saves and restores device state |
5054 | * over the reset and takes the PCI device lock. | |
8dd7f803 | 5055 | * |
8c1c699f | 5056 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
5057 | * device doesn't support resetting a single function. |
5058 | */ | |
5059 | int pci_reset_function(struct pci_dev *dev) | |
5060 | { | |
8c1c699f | 5061 | int rc; |
8dd7f803 | 5062 | |
204f4afa BH |
5063 | if (!dev->reset_fn) |
5064 | return -ENOTTY; | |
8dd7f803 | 5065 | |
b014e96d | 5066 | pci_dev_lock(dev); |
77cb985a | 5067 | pci_dev_save_and_disable(dev); |
8dd7f803 | 5068 | |
52354b9d | 5069 | rc = __pci_reset_function_locked(dev); |
8dd7f803 | 5070 | |
77cb985a | 5071 | pci_dev_restore(dev); |
b014e96d | 5072 | pci_dev_unlock(dev); |
8dd7f803 | 5073 | |
8c1c699f | 5074 | return rc; |
8dd7f803 SY |
5075 | } |
5076 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
5077 | ||
a477b9cd MZ |
5078 | /** |
5079 | * pci_reset_function_locked - quiesce and reset a PCI device function | |
5080 | * @dev: PCI device to reset | |
5081 | * | |
5082 | * Some devices allow an individual function to be reset without affecting | |
5083 | * other functions in the same device. The PCI device must be responsive | |
5084 | * to PCI config space in order to use this function. | |
5085 | * | |
5086 | * This function does not just reset the PCI portion of a device, but | |
5087 | * clears all the state associated with the device. This function differs | |
79e699b6 | 5088 | * from __pci_reset_function_locked() in that it saves and restores device state |
a477b9cd MZ |
5089 | * over the reset. It also differs from pci_reset_function() in that it |
5090 | * requires the PCI device lock to be held. | |
5091 | * | |
5092 | * Returns 0 if the device function was successfully reset or negative if the | |
5093 | * device doesn't support resetting a single function. | |
5094 | */ | |
5095 | int pci_reset_function_locked(struct pci_dev *dev) | |
5096 | { | |
5097 | int rc; | |
5098 | ||
204f4afa BH |
5099 | if (!dev->reset_fn) |
5100 | return -ENOTTY; | |
a477b9cd MZ |
5101 | |
5102 | pci_dev_save_and_disable(dev); | |
5103 | ||
5104 | rc = __pci_reset_function_locked(dev); | |
5105 | ||
5106 | pci_dev_restore(dev); | |
5107 | ||
5108 | return rc; | |
5109 | } | |
5110 | EXPORT_SYMBOL_GPL(pci_reset_function_locked); | |
5111 | ||
61cf16d8 AW |
5112 | /** |
5113 | * pci_try_reset_function - quiesce and reset a PCI device function | |
5114 | * @dev: PCI device to reset | |
5115 | * | |
5116 | * Same as above, except return -EAGAIN if unable to lock device. | |
5117 | */ | |
5118 | int pci_try_reset_function(struct pci_dev *dev) | |
5119 | { | |
5120 | int rc; | |
5121 | ||
204f4afa BH |
5122 | if (!dev->reset_fn) |
5123 | return -ENOTTY; | |
61cf16d8 | 5124 | |
b014e96d CH |
5125 | if (!pci_dev_trylock(dev)) |
5126 | return -EAGAIN; | |
61cf16d8 | 5127 | |
b014e96d | 5128 | pci_dev_save_and_disable(dev); |
52354b9d | 5129 | rc = __pci_reset_function_locked(dev); |
cb5e0d06 | 5130 | pci_dev_restore(dev); |
b014e96d | 5131 | pci_dev_unlock(dev); |
61cf16d8 | 5132 | |
61cf16d8 AW |
5133 | return rc; |
5134 | } | |
5135 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
5136 | ||
f331a859 AW |
5137 | /* Do any devices on or below this bus prevent a bus reset? */ |
5138 | static bool pci_bus_resetable(struct pci_bus *bus) | |
5139 | { | |
5140 | struct pci_dev *dev; | |
5141 | ||
35702778 DD |
5142 | |
5143 | if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5144 | return false; | |
5145 | ||
f331a859 AW |
5146 | list_for_each_entry(dev, &bus->devices, bus_list) { |
5147 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5148 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5149 | return false; | |
5150 | } | |
5151 | ||
5152 | return true; | |
5153 | } | |
5154 | ||
090a3c53 AW |
5155 | /* Lock devices from the top of the tree down */ |
5156 | static void pci_bus_lock(struct pci_bus *bus) | |
5157 | { | |
5158 | struct pci_dev *dev; | |
5159 | ||
5160 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5161 | pci_dev_lock(dev); | |
5162 | if (dev->subordinate) | |
5163 | pci_bus_lock(dev->subordinate); | |
5164 | } | |
5165 | } | |
5166 | ||
5167 | /* Unlock devices from the bottom of the tree up */ | |
5168 | static void pci_bus_unlock(struct pci_bus *bus) | |
5169 | { | |
5170 | struct pci_dev *dev; | |
5171 | ||
5172 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5173 | if (dev->subordinate) | |
5174 | pci_bus_unlock(dev->subordinate); | |
5175 | pci_dev_unlock(dev); | |
5176 | } | |
5177 | } | |
5178 | ||
61cf16d8 AW |
5179 | /* Return 1 on successful lock, 0 on contention */ |
5180 | static int pci_bus_trylock(struct pci_bus *bus) | |
5181 | { | |
5182 | struct pci_dev *dev; | |
5183 | ||
5184 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5185 | if (!pci_dev_trylock(dev)) | |
5186 | goto unlock; | |
5187 | if (dev->subordinate) { | |
5188 | if (!pci_bus_trylock(dev->subordinate)) { | |
5189 | pci_dev_unlock(dev); | |
5190 | goto unlock; | |
5191 | } | |
5192 | } | |
5193 | } | |
5194 | return 1; | |
5195 | ||
5196 | unlock: | |
5197 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
5198 | if (dev->subordinate) | |
5199 | pci_bus_unlock(dev->subordinate); | |
5200 | pci_dev_unlock(dev); | |
5201 | } | |
5202 | return 0; | |
5203 | } | |
5204 | ||
f331a859 AW |
5205 | /* Do any devices on or below this slot prevent a bus reset? */ |
5206 | static bool pci_slot_resetable(struct pci_slot *slot) | |
5207 | { | |
5208 | struct pci_dev *dev; | |
5209 | ||
33ba90aa JG |
5210 | if (slot->bus->self && |
5211 | (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
5212 | return false; | |
5213 | ||
f331a859 AW |
5214 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { |
5215 | if (!dev->slot || dev->slot != slot) | |
5216 | continue; | |
5217 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
5218 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
5219 | return false; | |
5220 | } | |
5221 | ||
5222 | return true; | |
5223 | } | |
5224 | ||
090a3c53 AW |
5225 | /* Lock devices from the top of the tree down */ |
5226 | static void pci_slot_lock(struct pci_slot *slot) | |
5227 | { | |
5228 | struct pci_dev *dev; | |
5229 | ||
5230 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5231 | if (!dev->slot || dev->slot != slot) | |
5232 | continue; | |
5233 | pci_dev_lock(dev); | |
5234 | if (dev->subordinate) | |
5235 | pci_bus_lock(dev->subordinate); | |
5236 | } | |
5237 | } | |
5238 | ||
5239 | /* Unlock devices from the bottom of the tree up */ | |
5240 | static void pci_slot_unlock(struct pci_slot *slot) | |
5241 | { | |
5242 | struct pci_dev *dev; | |
5243 | ||
5244 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5245 | if (!dev->slot || dev->slot != slot) | |
5246 | continue; | |
5247 | if (dev->subordinate) | |
5248 | pci_bus_unlock(dev->subordinate); | |
5249 | pci_dev_unlock(dev); | |
5250 | } | |
5251 | } | |
5252 | ||
61cf16d8 AW |
5253 | /* Return 1 on successful lock, 0 on contention */ |
5254 | static int pci_slot_trylock(struct pci_slot *slot) | |
5255 | { | |
5256 | struct pci_dev *dev; | |
5257 | ||
5258 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5259 | if (!dev->slot || dev->slot != slot) | |
5260 | continue; | |
5261 | if (!pci_dev_trylock(dev)) | |
5262 | goto unlock; | |
5263 | if (dev->subordinate) { | |
5264 | if (!pci_bus_trylock(dev->subordinate)) { | |
5265 | pci_dev_unlock(dev); | |
5266 | goto unlock; | |
5267 | } | |
5268 | } | |
5269 | } | |
5270 | return 1; | |
5271 | ||
5272 | unlock: | |
5273 | list_for_each_entry_continue_reverse(dev, | |
5274 | &slot->bus->devices, bus_list) { | |
5275 | if (!dev->slot || dev->slot != slot) | |
5276 | continue; | |
5277 | if (dev->subordinate) | |
5278 | pci_bus_unlock(dev->subordinate); | |
5279 | pci_dev_unlock(dev); | |
5280 | } | |
5281 | return 0; | |
5282 | } | |
5283 | ||
ddefc033 AW |
5284 | /* |
5285 | * Save and disable devices from the top of the tree down while holding | |
5286 | * the @dev mutex lock for the entire tree. | |
5287 | */ | |
5288 | static void pci_bus_save_and_disable_locked(struct pci_bus *bus) | |
090a3c53 AW |
5289 | { |
5290 | struct pci_dev *dev; | |
5291 | ||
5292 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5293 | pci_dev_save_and_disable(dev); | |
5294 | if (dev->subordinate) | |
ddefc033 | 5295 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5296 | } |
5297 | } | |
5298 | ||
5299 | /* | |
ddefc033 AW |
5300 | * Restore devices from top of the tree down while holding @dev mutex lock |
5301 | * for the entire tree. Parent bridges need to be restored before we can | |
5302 | * get to subordinate devices. | |
090a3c53 | 5303 | */ |
ddefc033 | 5304 | static void pci_bus_restore_locked(struct pci_bus *bus) |
090a3c53 AW |
5305 | { |
5306 | struct pci_dev *dev; | |
5307 | ||
5308 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
5309 | pci_dev_restore(dev); | |
5310 | if (dev->subordinate) | |
ddefc033 | 5311 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5312 | } |
5313 | } | |
5314 | ||
ddefc033 AW |
5315 | /* |
5316 | * Save and disable devices from the top of the tree down while holding | |
5317 | * the @dev mutex lock for the entire tree. | |
5318 | */ | |
5319 | static void pci_slot_save_and_disable_locked(struct pci_slot *slot) | |
090a3c53 AW |
5320 | { |
5321 | struct pci_dev *dev; | |
5322 | ||
5323 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5324 | if (!dev->slot || dev->slot != slot) | |
5325 | continue; | |
5326 | pci_dev_save_and_disable(dev); | |
5327 | if (dev->subordinate) | |
ddefc033 | 5328 | pci_bus_save_and_disable_locked(dev->subordinate); |
090a3c53 AW |
5329 | } |
5330 | } | |
5331 | ||
5332 | /* | |
ddefc033 AW |
5333 | * Restore devices from top of the tree down while holding @dev mutex lock |
5334 | * for the entire tree. Parent bridges need to be restored before we can | |
5335 | * get to subordinate devices. | |
090a3c53 | 5336 | */ |
ddefc033 | 5337 | static void pci_slot_restore_locked(struct pci_slot *slot) |
090a3c53 AW |
5338 | { |
5339 | struct pci_dev *dev; | |
5340 | ||
5341 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
5342 | if (!dev->slot || dev->slot != slot) | |
5343 | continue; | |
5344 | pci_dev_restore(dev); | |
5345 | if (dev->subordinate) | |
ddefc033 | 5346 | pci_bus_restore_locked(dev->subordinate); |
090a3c53 AW |
5347 | } |
5348 | } | |
5349 | ||
5350 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
5351 | { | |
5352 | int rc; | |
5353 | ||
f331a859 | 5354 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
5355 | return -ENOTTY; |
5356 | ||
5357 | if (!probe) | |
5358 | pci_slot_lock(slot); | |
5359 | ||
5360 | might_sleep(); | |
5361 | ||
5362 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
5363 | ||
5364 | if (!probe) | |
5365 | pci_slot_unlock(slot); | |
5366 | ||
5367 | return rc; | |
5368 | } | |
5369 | ||
9a3d2b9b AW |
5370 | /** |
5371 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
5372 | * @slot: PCI slot to probe | |
5373 | * | |
5374 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
5375 | */ | |
5376 | int pci_probe_reset_slot(struct pci_slot *slot) | |
5377 | { | |
5378 | return pci_slot_reset(slot, 1); | |
5379 | } | |
5380 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
5381 | ||
090a3c53 | 5382 | /** |
c6a44ba9 | 5383 | * __pci_reset_slot - Try to reset a PCI slot |
090a3c53 AW |
5384 | * @slot: PCI slot to reset |
5385 | * | |
5386 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
5387 | * independent of other slots. For instance, some slots may support slot power | |
5388 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
5389 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
5390 | * Generally a slot reset should be attempted before a bus reset. All of the | |
5391 | * function of the slot and any subordinate buses behind the slot are reset | |
5392 | * through this function. PCI config space of all devices in the slot and | |
5393 | * behind the slot is saved before and restored after reset. | |
5394 | * | |
61cf16d8 AW |
5395 | * Same as above except return -EAGAIN if the slot cannot be locked |
5396 | */ | |
c6a44ba9 | 5397 | static int __pci_reset_slot(struct pci_slot *slot) |
61cf16d8 AW |
5398 | { |
5399 | int rc; | |
5400 | ||
5401 | rc = pci_slot_reset(slot, 1); | |
5402 | if (rc) | |
5403 | return rc; | |
5404 | ||
61cf16d8 | 5405 | if (pci_slot_trylock(slot)) { |
ddefc033 | 5406 | pci_slot_save_and_disable_locked(slot); |
61cf16d8 AW |
5407 | might_sleep(); |
5408 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
ddefc033 | 5409 | pci_slot_restore_locked(slot); |
61cf16d8 AW |
5410 | pci_slot_unlock(slot); |
5411 | } else | |
5412 | rc = -EAGAIN; | |
5413 | ||
61cf16d8 AW |
5414 | return rc; |
5415 | } | |
61cf16d8 | 5416 | |
090a3c53 AW |
5417 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
5418 | { | |
18426238 SK |
5419 | int ret; |
5420 | ||
f331a859 | 5421 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
5422 | return -ENOTTY; |
5423 | ||
5424 | if (probe) | |
5425 | return 0; | |
5426 | ||
5427 | pci_bus_lock(bus); | |
5428 | ||
5429 | might_sleep(); | |
5430 | ||
381634ca | 5431 | ret = pci_bridge_secondary_bus_reset(bus->self); |
090a3c53 AW |
5432 | |
5433 | pci_bus_unlock(bus); | |
5434 | ||
18426238 | 5435 | return ret; |
090a3c53 AW |
5436 | } |
5437 | ||
c4eed62a KB |
5438 | /** |
5439 | * pci_bus_error_reset - reset the bridge's subordinate bus | |
5440 | * @bridge: The parent device that connects to the bus to reset | |
5441 | * | |
5442 | * This function will first try to reset the slots on this bus if the method is | |
5443 | * available. If slot reset fails or is not available, this will fall back to a | |
5444 | * secondary bus reset. | |
5445 | */ | |
5446 | int pci_bus_error_reset(struct pci_dev *bridge) | |
5447 | { | |
5448 | struct pci_bus *bus = bridge->subordinate; | |
5449 | struct pci_slot *slot; | |
5450 | ||
5451 | if (!bus) | |
5452 | return -ENOTTY; | |
5453 | ||
5454 | mutex_lock(&pci_slot_mutex); | |
5455 | if (list_empty(&bus->slots)) | |
5456 | goto bus_reset; | |
5457 | ||
5458 | list_for_each_entry(slot, &bus->slots, list) | |
5459 | if (pci_probe_reset_slot(slot)) | |
5460 | goto bus_reset; | |
5461 | ||
5462 | list_for_each_entry(slot, &bus->slots, list) | |
5463 | if (pci_slot_reset(slot, 0)) | |
5464 | goto bus_reset; | |
5465 | ||
5466 | mutex_unlock(&pci_slot_mutex); | |
5467 | return 0; | |
5468 | bus_reset: | |
5469 | mutex_unlock(&pci_slot_mutex); | |
5470 | return pci_bus_reset(bridge->subordinate, 0); | |
5471 | } | |
5472 | ||
9a3d2b9b AW |
5473 | /** |
5474 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
5475 | * @bus: PCI bus to probe | |
5476 | * | |
5477 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
5478 | */ | |
5479 | int pci_probe_reset_bus(struct pci_bus *bus) | |
5480 | { | |
5481 | return pci_bus_reset(bus, 1); | |
5482 | } | |
5483 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
5484 | ||
090a3c53 | 5485 | /** |
c6a44ba9 | 5486 | * __pci_reset_bus - Try to reset a PCI bus |
090a3c53 AW |
5487 | * @bus: top level PCI bus to reset |
5488 | * | |
61cf16d8 | 5489 | * Same as above except return -EAGAIN if the bus cannot be locked |
090a3c53 | 5490 | */ |
c6a44ba9 | 5491 | static int __pci_reset_bus(struct pci_bus *bus) |
090a3c53 AW |
5492 | { |
5493 | int rc; | |
5494 | ||
5495 | rc = pci_bus_reset(bus, 1); | |
5496 | if (rc) | |
5497 | return rc; | |
5498 | ||
61cf16d8 | 5499 | if (pci_bus_trylock(bus)) { |
ddefc033 | 5500 | pci_bus_save_and_disable_locked(bus); |
61cf16d8 | 5501 | might_sleep(); |
381634ca | 5502 | rc = pci_bridge_secondary_bus_reset(bus->self); |
ddefc033 | 5503 | pci_bus_restore_locked(bus); |
61cf16d8 AW |
5504 | pci_bus_unlock(bus); |
5505 | } else | |
5506 | rc = -EAGAIN; | |
090a3c53 | 5507 | |
090a3c53 AW |
5508 | return rc; |
5509 | } | |
090a3c53 | 5510 | |
61cf16d8 | 5511 | /** |
c6a44ba9 | 5512 | * pci_reset_bus - Try to reset a PCI bus |
811c5cb3 | 5513 | * @pdev: top level PCI device to reset via slot/bus |
61cf16d8 AW |
5514 | * |
5515 | * Same as above except return -EAGAIN if the bus cannot be locked | |
5516 | */ | |
c6a44ba9 | 5517 | int pci_reset_bus(struct pci_dev *pdev) |
61cf16d8 | 5518 | { |
d8a52810 | 5519 | return (!pci_probe_reset_slot(pdev->slot)) ? |
c6a44ba9 | 5520 | __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); |
61cf16d8 | 5521 | } |
c6a44ba9 | 5522 | EXPORT_SYMBOL_GPL(pci_reset_bus); |
61cf16d8 | 5523 | |
d556ad4b PO |
5524 | /** |
5525 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
5526 | * @dev: PCI device to query | |
5527 | * | |
74356add BH |
5528 | * Returns mmrbc: maximum designed memory read count in bytes or |
5529 | * appropriate error value. | |
d556ad4b PO |
5530 | */ |
5531 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
5532 | { | |
7c9e2b1c | 5533 | int cap; |
d556ad4b PO |
5534 | u32 stat; |
5535 | ||
5536 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5537 | if (!cap) | |
5538 | return -EINVAL; | |
5539 | ||
7c9e2b1c | 5540 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
5541 | return -EINVAL; |
5542 | ||
25daeb55 | 5543 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
5544 | } |
5545 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
5546 | ||
5547 | /** | |
5548 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
5549 | * @dev: PCI device to query | |
5550 | * | |
74356add BH |
5551 | * Returns mmrbc: maximum memory read count in bytes or appropriate error |
5552 | * value. | |
d556ad4b PO |
5553 | */ |
5554 | int pcix_get_mmrbc(struct pci_dev *dev) | |
5555 | { | |
7c9e2b1c | 5556 | int cap; |
bdc2bda7 | 5557 | u16 cmd; |
d556ad4b PO |
5558 | |
5559 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5560 | if (!cap) | |
5561 | return -EINVAL; | |
5562 | ||
7c9e2b1c DN |
5563 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5564 | return -EINVAL; | |
d556ad4b | 5565 | |
7c9e2b1c | 5566 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
5567 | } |
5568 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
5569 | ||
5570 | /** | |
5571 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
5572 | * @dev: PCI device to query | |
5573 | * @mmrbc: maximum memory read count in bytes | |
5574 | * valid values are 512, 1024, 2048, 4096 | |
5575 | * | |
74356add | 5576 | * If possible sets maximum memory read byte count, some bridges have errata |
d556ad4b PO |
5577 | * that prevent this. |
5578 | */ | |
5579 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
5580 | { | |
7c9e2b1c | 5581 | int cap; |
bdc2bda7 DN |
5582 | u32 stat, v, o; |
5583 | u16 cmd; | |
d556ad4b | 5584 | |
229f5afd | 5585 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 5586 | return -EINVAL; |
d556ad4b PO |
5587 | |
5588 | v = ffs(mmrbc) - 10; | |
5589 | ||
5590 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
5591 | if (!cap) | |
7c9e2b1c | 5592 | return -EINVAL; |
d556ad4b | 5593 | |
7c9e2b1c DN |
5594 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
5595 | return -EINVAL; | |
d556ad4b PO |
5596 | |
5597 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
5598 | return -E2BIG; | |
5599 | ||
7c9e2b1c DN |
5600 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
5601 | return -EINVAL; | |
d556ad4b PO |
5602 | |
5603 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
5604 | if (o != v) { | |
809a3bf9 | 5605 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
5606 | return -EIO; |
5607 | ||
5608 | cmd &= ~PCI_X_CMD_MAX_READ; | |
5609 | cmd |= v << 2; | |
7c9e2b1c DN |
5610 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
5611 | return -EIO; | |
d556ad4b | 5612 | } |
7c9e2b1c | 5613 | return 0; |
d556ad4b PO |
5614 | } |
5615 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
5616 | ||
5617 | /** | |
5618 | * pcie_get_readrq - get PCI Express read request size | |
5619 | * @dev: PCI device to query | |
5620 | * | |
74356add | 5621 | * Returns maximum memory read request in bytes or appropriate error value. |
d556ad4b PO |
5622 | */ |
5623 | int pcie_get_readrq(struct pci_dev *dev) | |
5624 | { | |
d556ad4b PO |
5625 | u16 ctl; |
5626 | ||
59875ae4 | 5627 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 5628 | |
59875ae4 | 5629 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
5630 | } |
5631 | EXPORT_SYMBOL(pcie_get_readrq); | |
5632 | ||
5633 | /** | |
5634 | * pcie_set_readrq - set PCI Express maximum memory read request | |
5635 | * @dev: PCI device to query | |
42e61f4a | 5636 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
5637 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5638 | * | |
c9b378c7 | 5639 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
5640 | */ |
5641 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
5642 | { | |
59875ae4 | 5643 | u16 v; |
d556ad4b | 5644 | |
229f5afd | 5645 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 5646 | return -EINVAL; |
d556ad4b | 5647 | |
a1c473aa | 5648 | /* |
74356add BH |
5649 | * If using the "performance" PCIe config, we clamp the read rq |
5650 | * size to the max packet size to keep the host bridge from | |
5651 | * generating requests larger than we can cope with. | |
a1c473aa BH |
5652 | */ |
5653 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
5654 | int mps = pcie_get_mps(dev); | |
5655 | ||
a1c473aa BH |
5656 | if (mps < rq) |
5657 | rq = mps; | |
5658 | } | |
5659 | ||
5660 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 5661 | |
59875ae4 JL |
5662 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
5663 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
5664 | } |
5665 | EXPORT_SYMBOL(pcie_set_readrq); | |
5666 | ||
b03e7495 JM |
5667 | /** |
5668 | * pcie_get_mps - get PCI Express maximum payload size | |
5669 | * @dev: PCI device to query | |
5670 | * | |
5671 | * Returns maximum payload size in bytes | |
b03e7495 JM |
5672 | */ |
5673 | int pcie_get_mps(struct pci_dev *dev) | |
5674 | { | |
b03e7495 JM |
5675 | u16 ctl; |
5676 | ||
59875ae4 | 5677 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 5678 | |
59875ae4 | 5679 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 5680 | } |
f1c66c46 | 5681 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
5682 | |
5683 | /** | |
5684 | * pcie_set_mps - set PCI Express maximum payload size | |
5685 | * @dev: PCI device to query | |
47c08f31 | 5686 | * @mps: maximum payload size in bytes |
b03e7495 JM |
5687 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
5688 | * | |
5689 | * If possible sets maximum payload size | |
5690 | */ | |
5691 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
5692 | { | |
59875ae4 | 5693 | u16 v; |
b03e7495 JM |
5694 | |
5695 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 5696 | return -EINVAL; |
b03e7495 JM |
5697 | |
5698 | v = ffs(mps) - 8; | |
f7625980 | 5699 | if (v > dev->pcie_mpss) |
59875ae4 | 5700 | return -EINVAL; |
b03e7495 JM |
5701 | v <<= 5; |
5702 | ||
59875ae4 JL |
5703 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
5704 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 5705 | } |
f1c66c46 | 5706 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 5707 | |
6db79a88 TG |
5708 | /** |
5709 | * pcie_bandwidth_available - determine minimum link settings of a PCIe | |
5710 | * device and its bandwidth limitation | |
5711 | * @dev: PCI device to query | |
5712 | * @limiting_dev: storage for device causing the bandwidth limitation | |
5713 | * @speed: storage for speed of limiting device | |
5714 | * @width: storage for width of limiting device | |
5715 | * | |
5716 | * Walk up the PCI device chain and find the point where the minimum | |
5717 | * bandwidth is available. Return the bandwidth available there and (if | |
5718 | * limiting_dev, speed, and width pointers are supplied) information about | |
5719 | * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of | |
5720 | * raw bandwidth. | |
5721 | */ | |
5722 | u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, | |
5723 | enum pci_bus_speed *speed, | |
5724 | enum pcie_link_width *width) | |
5725 | { | |
5726 | u16 lnksta; | |
5727 | enum pci_bus_speed next_speed; | |
5728 | enum pcie_link_width next_width; | |
5729 | u32 bw, next_bw; | |
5730 | ||
5731 | if (speed) | |
5732 | *speed = PCI_SPEED_UNKNOWN; | |
5733 | if (width) | |
5734 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
5735 | ||
5736 | bw = 0; | |
5737 | ||
5738 | while (dev) { | |
5739 | pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
5740 | ||
5741 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
5742 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
5743 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
5744 | ||
5745 | next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); | |
5746 | ||
5747 | /* Check if current device limits the total bandwidth */ | |
5748 | if (!bw || next_bw <= bw) { | |
5749 | bw = next_bw; | |
5750 | ||
5751 | if (limiting_dev) | |
5752 | *limiting_dev = dev; | |
5753 | if (speed) | |
5754 | *speed = next_speed; | |
5755 | if (width) | |
5756 | *width = next_width; | |
5757 | } | |
5758 | ||
5759 | dev = pci_upstream_bridge(dev); | |
5760 | } | |
5761 | ||
5762 | return bw; | |
5763 | } | |
5764 | EXPORT_SYMBOL(pcie_bandwidth_available); | |
5765 | ||
6cf57be0 TG |
5766 | /** |
5767 | * pcie_get_speed_cap - query for the PCI device's link speed capability | |
5768 | * @dev: PCI device to query | |
5769 | * | |
5770 | * Query the PCI device speed capability. Return the maximum link speed | |
5771 | * supported by the device. | |
5772 | */ | |
5773 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) | |
5774 | { | |
5775 | u32 lnkcap2, lnkcap; | |
5776 | ||
5777 | /* | |
f1f90e25 MP |
5778 | * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The |
5779 | * implementation note there recommends using the Supported Link | |
5780 | * Speeds Vector in Link Capabilities 2 when supported. | |
5781 | * | |
5782 | * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software | |
5783 | * should use the Supported Link Speeds field in Link Capabilities, | |
5784 | * where only 2.5 GT/s and 5.0 GT/s speeds were defined. | |
6cf57be0 TG |
5785 | */ |
5786 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); | |
5787 | if (lnkcap2) { /* PCIe r3.0-compliant */ | |
de76cda2 GP |
5788 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) |
5789 | return PCIE_SPEED_32_0GT; | |
5790 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) | |
6cf57be0 TG |
5791 | return PCIE_SPEED_16_0GT; |
5792 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
5793 | return PCIE_SPEED_8_0GT; | |
5794 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
5795 | return PCIE_SPEED_5_0GT; | |
5796 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
5797 | return PCIE_SPEED_2_5GT; | |
5798 | return PCI_SPEED_UNKNOWN; | |
5799 | } | |
5800 | ||
5801 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
f1f90e25 MP |
5802 | if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB) |
5803 | return PCIE_SPEED_5_0GT; | |
5804 | else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB) | |
5805 | return PCIE_SPEED_2_5GT; | |
6cf57be0 TG |
5806 | |
5807 | return PCI_SPEED_UNKNOWN; | |
5808 | } | |
576c7218 | 5809 | EXPORT_SYMBOL(pcie_get_speed_cap); |
6cf57be0 | 5810 | |
c70b65fb TG |
5811 | /** |
5812 | * pcie_get_width_cap - query for the PCI device's link width capability | |
5813 | * @dev: PCI device to query | |
5814 | * | |
5815 | * Query the PCI device width capability. Return the maximum link width | |
5816 | * supported by the device. | |
5817 | */ | |
5818 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) | |
5819 | { | |
5820 | u32 lnkcap; | |
5821 | ||
5822 | pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); | |
5823 | if (lnkcap) | |
5824 | return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; | |
5825 | ||
5826 | return PCIE_LNK_WIDTH_UNKNOWN; | |
5827 | } | |
576c7218 | 5828 | EXPORT_SYMBOL(pcie_get_width_cap); |
c70b65fb | 5829 | |
b852f63a TG |
5830 | /** |
5831 | * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability | |
5832 | * @dev: PCI device | |
5833 | * @speed: storage for link speed | |
5834 | * @width: storage for link width | |
5835 | * | |
5836 | * Calculate a PCI device's link bandwidth by querying for its link speed | |
5837 | * and width, multiplying them, and applying encoding overhead. The result | |
5838 | * is in Mb/s, i.e., megabits/second of raw bandwidth. | |
5839 | */ | |
5840 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, | |
5841 | enum pcie_link_width *width) | |
5842 | { | |
5843 | *speed = pcie_get_speed_cap(dev); | |
5844 | *width = pcie_get_width_cap(dev); | |
5845 | ||
5846 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) | |
5847 | return 0; | |
5848 | ||
5849 | return *width * PCIE_SPEED2MBS_ENC(*speed); | |
5850 | } | |
5851 | ||
9e506a7b | 5852 | /** |
2d1ce5ec | 5853 | * __pcie_print_link_status - Report the PCI device's link speed and width |
9e506a7b | 5854 | * @dev: PCI device to query |
2d1ce5ec | 5855 | * @verbose: Print info even when enough bandwidth is available |
9e506a7b | 5856 | * |
2d1ce5ec AG |
5857 | * If the available bandwidth at the device is less than the device is |
5858 | * capable of, report the device's maximum possible bandwidth and the | |
5859 | * upstream link that limits its performance. If @verbose, always print | |
5860 | * the available bandwidth, even if the device isn't constrained. | |
9e506a7b | 5861 | */ |
2d1ce5ec | 5862 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose) |
9e506a7b TG |
5863 | { |
5864 | enum pcie_link_width width, width_cap; | |
5865 | enum pci_bus_speed speed, speed_cap; | |
5866 | struct pci_dev *limiting_dev = NULL; | |
5867 | u32 bw_avail, bw_cap; | |
5868 | ||
5869 | bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap); | |
5870 | bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width); | |
5871 | ||
2d1ce5ec | 5872 | if (bw_avail >= bw_cap && verbose) |
0cf22d6b | 5873 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n", |
9e506a7b TG |
5874 | bw_cap / 1000, bw_cap % 1000, |
5875 | PCIE_SPEED2STR(speed_cap), width_cap); | |
2d1ce5ec | 5876 | else if (bw_avail < bw_cap) |
0cf22d6b | 5877 | pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n", |
9e506a7b TG |
5878 | bw_avail / 1000, bw_avail % 1000, |
5879 | PCIE_SPEED2STR(speed), width, | |
5880 | limiting_dev ? pci_name(limiting_dev) : "<unknown>", | |
5881 | bw_cap / 1000, bw_cap % 1000, | |
5882 | PCIE_SPEED2STR(speed_cap), width_cap); | |
5883 | } | |
2d1ce5ec AG |
5884 | |
5885 | /** | |
5886 | * pcie_print_link_status - Report the PCI device's link speed and width | |
5887 | * @dev: PCI device to query | |
5888 | * | |
5889 | * Report the available bandwidth at the device. | |
5890 | */ | |
5891 | void pcie_print_link_status(struct pci_dev *dev) | |
5892 | { | |
5893 | __pcie_print_link_status(dev, true); | |
5894 | } | |
9e506a7b TG |
5895 | EXPORT_SYMBOL(pcie_print_link_status); |
5896 | ||
c87deff7 HS |
5897 | /** |
5898 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 5899 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
5900 | * @flags: resource type mask to be selected |
5901 | * | |
5902 | * This helper routine makes bar mask from the type of resource. | |
5903 | */ | |
5904 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
5905 | { | |
5906 | int i, bars = 0; | |
5907 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
5908 | if (pci_resource_flags(dev, i) & flags) | |
5909 | bars |= (1 << i); | |
5910 | return bars; | |
5911 | } | |
b7fe9434 | 5912 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 5913 | |
95a8b6ef MT |
5914 | /* Some architectures require additional programming to enable VGA */ |
5915 | static arch_set_vga_state_t arch_set_vga_state; | |
5916 | ||
5917 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
5918 | { | |
5919 | arch_set_vga_state = func; /* NULL disables */ | |
5920 | } | |
5921 | ||
5922 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 5923 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
5924 | { |
5925 | if (arch_set_vga_state) | |
5926 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 5927 | flags); |
95a8b6ef MT |
5928 | return 0; |
5929 | } | |
5930 | ||
deb2d2ec BH |
5931 | /** |
5932 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
5933 | * @dev: the PCI device |
5934 | * @decode: true = enable decoding, false = disable decoding | |
5935 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 5936 | * @flags: traverse ancestors and change bridges |
3448a19d | 5937 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
5938 | */ |
5939 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 5940 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
5941 | { |
5942 | struct pci_bus *bus; | |
5943 | struct pci_dev *bridge; | |
5944 | u16 cmd; | |
95a8b6ef | 5945 | int rc; |
deb2d2ec | 5946 | |
67ebd814 | 5947 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 5948 | |
95a8b6ef | 5949 | /* ARCH specific VGA enables */ |
3448a19d | 5950 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
5951 | if (rc) |
5952 | return rc; | |
5953 | ||
3448a19d DA |
5954 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
5955 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
5956 | if (decode == true) | |
5957 | cmd |= command_bits; | |
5958 | else | |
5959 | cmd &= ~command_bits; | |
5960 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
5961 | } | |
deb2d2ec | 5962 | |
3448a19d | 5963 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
5964 | return 0; |
5965 | ||
5966 | bus = dev->bus; | |
5967 | while (bus) { | |
5968 | bridge = bus->self; | |
5969 | if (bridge) { | |
5970 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
5971 | &cmd); | |
5972 | if (decode == true) | |
5973 | cmd |= PCI_BRIDGE_CTL_VGA; | |
5974 | else | |
5975 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
5976 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
5977 | cmd); | |
5978 | } | |
5979 | bus = bus->parent; | |
5980 | } | |
5981 | return 0; | |
5982 | } | |
5983 | ||
52525b7a KHF |
5984 | #ifdef CONFIG_ACPI |
5985 | bool pci_pr3_present(struct pci_dev *pdev) | |
5986 | { | |
5987 | struct acpi_device *adev; | |
5988 | ||
5989 | if (acpi_disabled) | |
5990 | return false; | |
5991 | ||
5992 | adev = ACPI_COMPANION(&pdev->dev); | |
5993 | if (!adev) | |
5994 | return false; | |
5995 | ||
5996 | return adev->power.flags.power_resources && | |
5997 | acpi_has_method(adev->handle, "_PR3"); | |
5998 | } | |
5999 | EXPORT_SYMBOL_GPL(pci_pr3_present); | |
6000 | #endif | |
6001 | ||
f0af9593 BH |
6002 | /** |
6003 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
6004 | * @dev: the PCI device for which alias is added | |
09298542 JS |
6005 | * @devfn_from: alias slot and function |
6006 | * @nr_devfns: number of subsequent devfns to alias | |
f0af9593 | 6007 | * |
f778a0d2 LG |
6008 | * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask |
6009 | * which is used to program permissible bus-devfn source addresses for DMA | |
6010 | * requests in an IOMMU. These aliases factor into IOMMU group creation | |
6011 | * and are useful for devices generating DMA requests beyond or different | |
6012 | * from their logical bus-devfn. Examples include device quirks where the | |
6013 | * device simply uses the wrong devfn, as well as non-transparent bridges | |
6014 | * where the alias may be a proxy for devices in another domain. | |
6015 | * | |
6016 | * IOMMU group creation is performed during device discovery or addition, | |
6017 | * prior to any potential DMA mapping and therefore prior to driver probing | |
6018 | * (especially for userspace assigned devices where IOMMU group definition | |
6019 | * cannot be left as a userspace activity). DMA aliases should therefore | |
6020 | * be configured via quirks, such as the PCI fixup header quirk. | |
f0af9593 | 6021 | */ |
09298542 | 6022 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns) |
f0af9593 | 6023 | { |
09298542 JS |
6024 | int devfn_to; |
6025 | ||
6026 | nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from); | |
6027 | devfn_to = devfn_from + nr_devfns - 1; | |
6028 | ||
338c3149 | 6029 | if (!dev->dma_alias_mask) |
f8bf2aeb | 6030 | dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); |
338c3149 | 6031 | if (!dev->dma_alias_mask) { |
7506dc79 | 6032 | pci_warn(dev, "Unable to allocate DMA alias mask\n"); |
338c3149 JL |
6033 | return; |
6034 | } | |
6035 | ||
09298542 JS |
6036 | bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); |
6037 | ||
6038 | if (nr_devfns == 1) | |
6039 | pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n", | |
6040 | PCI_SLOT(devfn_from), PCI_FUNC(devfn_from)); | |
6041 | else if (nr_devfns > 1) | |
6042 | pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n", | |
6043 | PCI_SLOT(devfn_from), PCI_FUNC(devfn_from), | |
6044 | PCI_SLOT(devfn_to), PCI_FUNC(devfn_to)); | |
f0af9593 BH |
6045 | } |
6046 | ||
338c3149 JL |
6047 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
6048 | { | |
6049 | return (dev1->dma_alias_mask && | |
6050 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
6051 | (dev2->dma_alias_mask && | |
2856ba60 JD |
6052 | test_bit(dev1->devfn, dev2->dma_alias_mask)) || |
6053 | pci_real_dma_dev(dev1) == dev2 || | |
6054 | pci_real_dma_dev(dev2) == dev1; | |
338c3149 JL |
6055 | } |
6056 | ||
8496e85c RW |
6057 | bool pci_device_is_present(struct pci_dev *pdev) |
6058 | { | |
6059 | u32 v; | |
6060 | ||
fe2bd75b KB |
6061 | if (pci_dev_is_disconnected(pdev)) |
6062 | return false; | |
8496e85c RW |
6063 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); |
6064 | } | |
6065 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
6066 | ||
08249651 RW |
6067 | void pci_ignore_hotplug(struct pci_dev *dev) |
6068 | { | |
6069 | struct pci_dev *bridge = dev->bus->self; | |
6070 | ||
6071 | dev->ignore_hotplug = 1; | |
6072 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
6073 | if (bridge) | |
6074 | bridge->ignore_hotplug = 1; | |
6075 | } | |
6076 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
6077 | ||
2856ba60 JD |
6078 | /** |
6079 | * pci_real_dma_dev - Get PCI DMA device for PCI device | |
6080 | * @dev: the PCI device that may have a PCI DMA alias | |
6081 | * | |
6082 | * Permits the platform to provide architecture-specific functionality to | |
6083 | * devices needing to alias DMA to another PCI device on another PCI bus. If | |
6084 | * the PCI device is on the same bus, it is recommended to use | |
6085 | * pci_add_dma_alias(). This is the default implementation. Architecture | |
6086 | * implementations can override this. | |
6087 | */ | |
6088 | struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev) | |
6089 | { | |
6090 | return dev; | |
6091 | } | |
6092 | ||
0a701aa6 YX |
6093 | resource_size_t __weak pcibios_default_alignment(void) |
6094 | { | |
6095 | return 0; | |
6096 | } | |
6097 | ||
b8074aa2 DE |
6098 | /* |
6099 | * Arches that don't want to expose struct resource to userland as-is in | |
6100 | * sysfs and /proc can implement their own pci_resource_to_user(). | |
6101 | */ | |
6102 | void __weak pci_resource_to_user(const struct pci_dev *dev, int bar, | |
6103 | const struct resource *rsrc, | |
6104 | resource_size_t *start, resource_size_t *end) | |
6105 | { | |
6106 | *start = rsrc->start; | |
6107 | *end = rsrc->end; | |
6108 | } | |
6109 | ||
70aaf61a | 6110 | static char *resource_alignment_param; |
e9d1e492 | 6111 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
6112 | |
6113 | /** | |
6114 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
6115 | * @dev: the PCI device to get | |
e3adec72 | 6116 | * @resize: whether or not to change resources' size when reassigning alignment |
32a9a682 YS |
6117 | * |
6118 | * RETURNS: Resource alignment if it is specified. | |
6119 | * Zero if it is not specified. | |
6120 | */ | |
e3adec72 YX |
6121 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, |
6122 | bool *resize) | |
32a9a682 | 6123 | { |
07d8d7e5 | 6124 | int align_order, count; |
0a701aa6 | 6125 | resource_size_t align = pcibios_default_alignment(); |
07d8d7e5 LG |
6126 | const char *p; |
6127 | int ret; | |
32a9a682 YS |
6128 | |
6129 | spin_lock(&resource_alignment_lock); | |
6130 | p = resource_alignment_param; | |
70aaf61a | 6131 | if (!p || !*p) |
f0b99f70 YX |
6132 | goto out; |
6133 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
0a701aa6 | 6134 | align = 0; |
f0b99f70 YX |
6135 | pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); |
6136 | goto out; | |
6137 | } | |
6138 | ||
32a9a682 YS |
6139 | while (*p) { |
6140 | count = 0; | |
6141 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
6142 | p[count] == '@') { | |
6143 | p += count + 1; | |
6144 | } else { | |
6145 | align_order = -1; | |
6146 | } | |
07d8d7e5 LG |
6147 | |
6148 | ret = pci_dev_str_match(dev, p, &p); | |
6149 | if (ret == 1) { | |
6150 | *resize = true; | |
6151 | if (align_order == -1) | |
6152 | align = PAGE_SIZE; | |
6153 | else | |
6154 | align = 1 << align_order; | |
6155 | break; | |
6156 | } else if (ret < 0) { | |
6157 | pr_err("PCI: Can't parse resource_alignment parameter: %s\n", | |
6158 | p); | |
6159 | break; | |
32a9a682 | 6160 | } |
07d8d7e5 | 6161 | |
32a9a682 YS |
6162 | if (*p != ';' && *p != ',') { |
6163 | /* End of param or invalid format */ | |
6164 | break; | |
6165 | } | |
6166 | p++; | |
6167 | } | |
f0b99f70 | 6168 | out: |
32a9a682 YS |
6169 | spin_unlock(&resource_alignment_lock); |
6170 | return align; | |
6171 | } | |
6172 | ||
81a5e70e | 6173 | static void pci_request_resource_alignment(struct pci_dev *dev, int bar, |
e3adec72 | 6174 | resource_size_t align, bool resize) |
81a5e70e BH |
6175 | { |
6176 | struct resource *r = &dev->resource[bar]; | |
6177 | resource_size_t size; | |
6178 | ||
6179 | if (!(r->flags & IORESOURCE_MEM)) | |
6180 | return; | |
6181 | ||
6182 | if (r->flags & IORESOURCE_PCI_FIXED) { | |
7506dc79 | 6183 | pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n", |
81a5e70e BH |
6184 | bar, r, (unsigned long long)align); |
6185 | return; | |
6186 | } | |
6187 | ||
6188 | size = resource_size(r); | |
0dde1c08 BH |
6189 | if (size >= align) |
6190 | return; | |
81a5e70e | 6191 | |
0dde1c08 | 6192 | /* |
e3adec72 YX |
6193 | * Increase the alignment of the resource. There are two ways we |
6194 | * can do this: | |
0dde1c08 | 6195 | * |
e3adec72 YX |
6196 | * 1) Increase the size of the resource. BARs are aligned on their |
6197 | * size, so when we reallocate space for this resource, we'll | |
6198 | * allocate it with the larger alignment. This also prevents | |
6199 | * assignment of any other BARs inside the alignment region, so | |
6200 | * if we're requesting page alignment, this means no other BARs | |
6201 | * will share the page. | |
6202 | * | |
6203 | * The disadvantage is that this makes the resource larger than | |
6204 | * the hardware BAR, which may break drivers that compute things | |
6205 | * based on the resource size, e.g., to find registers at a | |
6206 | * fixed offset before the end of the BAR. | |
6207 | * | |
6208 | * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and | |
6209 | * set r->start to the desired alignment. By itself this | |
6210 | * doesn't prevent other BARs being put inside the alignment | |
6211 | * region, but if we realign *every* resource of every device in | |
6212 | * the system, none of them will share an alignment region. | |
6213 | * | |
6214 | * When the user has requested alignment for only some devices via | |
6215 | * the "pci=resource_alignment" argument, "resize" is true and we | |
6216 | * use the first method. Otherwise we assume we're aligning all | |
6217 | * devices and we use the second. | |
0dde1c08 | 6218 | */ |
e3adec72 | 6219 | |
7506dc79 | 6220 | pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n", |
0dde1c08 | 6221 | bar, r, (unsigned long long)align); |
81a5e70e | 6222 | |
e3adec72 YX |
6223 | if (resize) { |
6224 | r->start = 0; | |
6225 | r->end = align - 1; | |
6226 | } else { | |
6227 | r->flags &= ~IORESOURCE_SIZEALIGN; | |
6228 | r->flags |= IORESOURCE_STARTALIGN; | |
6229 | r->start = align; | |
6230 | r->end = r->start + size - 1; | |
6231 | } | |
0dde1c08 | 6232 | r->flags |= IORESOURCE_UNSET; |
81a5e70e BH |
6233 | } |
6234 | ||
2069ecfb YL |
6235 | /* |
6236 | * This function disables memory decoding and releases memory resources | |
6237 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
6238 | * It also rounds up size to specified alignment. | |
6239 | * Later on, the kernel will assign page-aligned memory resource back | |
6240 | * to the device. | |
6241 | */ | |
6242 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
6243 | { | |
6244 | int i; | |
6245 | struct resource *r; | |
81a5e70e | 6246 | resource_size_t align; |
2069ecfb | 6247 | u16 command; |
e3adec72 | 6248 | bool resize = false; |
2069ecfb | 6249 | |
62d9a78f YX |
6250 | /* |
6251 | * VF BARs are read-only zero according to SR-IOV spec r1.1, sec | |
6252 | * 3.4.1.11. Their resources are allocated from the space | |
6253 | * described by the VF BARx register in the PF's SR-IOV capability. | |
6254 | * We can't influence their alignment here. | |
6255 | */ | |
6256 | if (dev->is_virtfn) | |
6257 | return; | |
6258 | ||
10c463a7 | 6259 | /* check if specified PCI is target device to reassign */ |
e3adec72 | 6260 | align = pci_specified_resource_alignment(dev, &resize); |
10c463a7 | 6261 | if (!align) |
2069ecfb YL |
6262 | return; |
6263 | ||
6264 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
6265 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
7506dc79 | 6266 | pci_warn(dev, "Can't reassign resources to host bridge\n"); |
2069ecfb YL |
6267 | return; |
6268 | } | |
6269 | ||
2069ecfb YL |
6270 | pci_read_config_word(dev, PCI_COMMAND, &command); |
6271 | command &= ~PCI_COMMAND_MEMORY; | |
6272 | pci_write_config_word(dev, PCI_COMMAND, command); | |
6273 | ||
81a5e70e | 6274 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
e3adec72 | 6275 | pci_request_resource_alignment(dev, i, align, resize); |
f0b99f70 | 6276 | |
81a5e70e BH |
6277 | /* |
6278 | * Need to disable bridge's resource window, | |
2069ecfb YL |
6279 | * to enable the kernel to reassign new resource |
6280 | * window later on. | |
6281 | */ | |
b2fb5cc5 | 6282 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { |
2069ecfb YL |
6283 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { |
6284 | r = &dev->resource[i]; | |
6285 | if (!(r->flags & IORESOURCE_MEM)) | |
6286 | continue; | |
bd064f0a | 6287 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
6288 | r->end = resource_size(r) - 1; |
6289 | r->start = 0; | |
6290 | } | |
6291 | pci_disable_bridge_window(dev); | |
6292 | } | |
6293 | } | |
6294 | ||
273b177c | 6295 | static ssize_t resource_alignment_show(struct bus_type *bus, char *buf) |
32a9a682 | 6296 | { |
70aaf61a | 6297 | size_t count = 0; |
32a9a682 | 6298 | |
32a9a682 | 6299 | spin_lock(&resource_alignment_lock); |
70aaf61a | 6300 | if (resource_alignment_param) |
273b177c | 6301 | count = snprintf(buf, PAGE_SIZE, "%s", resource_alignment_param); |
32a9a682 | 6302 | spin_unlock(&resource_alignment_lock); |
32a9a682 | 6303 | |
e499081d LG |
6304 | /* |
6305 | * When set by the command line, resource_alignment_param will not | |
6306 | * have a trailing line feed, which is ugly. So conditionally add | |
6307 | * it here. | |
6308 | */ | |
6309 | if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) { | |
6310 | buf[count - 1] = '\n'; | |
6311 | buf[count++] = 0; | |
6312 | } | |
6313 | ||
32a9a682 | 6314 | return count; |
32a9a682 YS |
6315 | } |
6316 | ||
d61dfafc | 6317 | static ssize_t resource_alignment_store(struct bus_type *bus, |
32a9a682 YS |
6318 | const char *buf, size_t count) |
6319 | { | |
273b177c LG |
6320 | char *param = kstrndup(buf, count, GFP_KERNEL); |
6321 | ||
6322 | if (!param) | |
6323 | return -ENOMEM; | |
6324 | ||
6325 | spin_lock(&resource_alignment_lock); | |
6326 | kfree(resource_alignment_param); | |
6327 | resource_alignment_param = param; | |
6328 | spin_unlock(&resource_alignment_lock); | |
6329 | return count; | |
32a9a682 YS |
6330 | } |
6331 | ||
d61dfafc | 6332 | static BUS_ATTR_RW(resource_alignment); |
32a9a682 YS |
6333 | |
6334 | static int __init pci_resource_alignment_sysfs_init(void) | |
6335 | { | |
6336 | return bus_create_file(&pci_bus_type, | |
6337 | &bus_attr_resource_alignment); | |
6338 | } | |
32a9a682 YS |
6339 | late_initcall(pci_resource_alignment_sysfs_init); |
6340 | ||
15856ad5 | 6341 | static void pci_no_domains(void) |
32a2eea7 JG |
6342 | { |
6343 | #ifdef CONFIG_PCI_DOMAINS | |
6344 | pci_domains_supported = 0; | |
6345 | #endif | |
6346 | } | |
6347 | ||
ae07b786 | 6348 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
41e5c0f8 LD |
6349 | static atomic_t __domain_nr = ATOMIC_INIT(-1); |
6350 | ||
ae07b786 | 6351 | static int pci_get_new_domain_nr(void) |
41e5c0f8 LD |
6352 | { |
6353 | return atomic_inc_return(&__domain_nr); | |
6354 | } | |
7c674700 | 6355 | |
1a4f93f7 | 6356 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
6357 | { |
6358 | static int use_dt_domains = -1; | |
54c6e2dd | 6359 | int domain = -1; |
7c674700 | 6360 | |
54c6e2dd KHC |
6361 | if (parent) |
6362 | domain = of_get_pci_domain_nr(parent->of_node); | |
74356add | 6363 | |
7c674700 LP |
6364 | /* |
6365 | * Check DT domain and use_dt_domains values. | |
6366 | * | |
6367 | * If DT domain property is valid (domain >= 0) and | |
6368 | * use_dt_domains != 0, the DT assignment is valid since this means | |
6369 | * we have not previously allocated a domain number by using | |
6370 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
6371 | * 1, to indicate that we have just assigned a domain number from | |
6372 | * DT. | |
6373 | * | |
6374 | * If DT domain property value is not valid (ie domain < 0), and we | |
6375 | * have not previously assigned a domain number from DT | |
6376 | * (use_dt_domains != 1) we should assign a domain number by | |
6377 | * using the: | |
6378 | * | |
6379 | * pci_get_new_domain_nr() | |
6380 | * | |
6381 | * API and update the use_dt_domains value to keep track of method we | |
6382 | * are using to assign domain numbers (use_dt_domains = 0). | |
6383 | * | |
6384 | * All other combinations imply we have a platform that is trying | |
6385 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
6386 | * which is a recipe for domain mishandling and it is prevented by | |
6387 | * invalidating the domain value (domain = -1) and printing a | |
6388 | * corresponding error. | |
6389 | */ | |
6390 | if (domain >= 0 && use_dt_domains) { | |
6391 | use_dt_domains = 1; | |
6392 | } else if (domain < 0 && use_dt_domains != 1) { | |
6393 | use_dt_domains = 0; | |
6394 | domain = pci_get_new_domain_nr(); | |
6395 | } else { | |
9df1c6ec SL |
6396 | if (parent) |
6397 | pr_err("Node %pOF has ", parent->of_node); | |
6398 | pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); | |
7c674700 LP |
6399 | domain = -1; |
6400 | } | |
6401 | ||
9c7cb891 | 6402 | return domain; |
7c674700 | 6403 | } |
1a4f93f7 TN |
6404 | |
6405 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
6406 | { | |
2ab51dde TN |
6407 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
6408 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
6409 | } |
6410 | #endif | |
41e5c0f8 | 6411 | |
0ef5f8f6 | 6412 | /** |
642c92da | 6413 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
6414 | * |
6415 | * Returns 1 if we can access PCI extended config space (offsets | |
6416 | * greater than 0xff). This is the default implementation. Architecture | |
6417 | * implementations can override this. | |
6418 | */ | |
642c92da | 6419 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
6420 | { |
6421 | return 1; | |
6422 | } | |
6423 | ||
2d1c8618 BH |
6424 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
6425 | { | |
6426 | } | |
6427 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
6428 | ||
ad04d31e | 6429 | static int __init pci_setup(char *str) |
1da177e4 LT |
6430 | { |
6431 | while (str) { | |
6432 | char *k = strchr(str, ','); | |
6433 | if (k) | |
6434 | *k++ = 0; | |
6435 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
6436 | if (!strcmp(str, "nomsi")) { |
6437 | pci_no_msi(); | |
cef74409 GK |
6438 | } else if (!strncmp(str, "noats", 5)) { |
6439 | pr_info("PCIe: ATS is disabled\n"); | |
6440 | pcie_ats_disabled = true; | |
7f785763 RD |
6441 | } else if (!strcmp(str, "noaer")) { |
6442 | pci_no_aer(); | |
11eb0e0e SK |
6443 | } else if (!strcmp(str, "earlydump")) { |
6444 | pci_early_dump = true; | |
b55438fd YL |
6445 | } else if (!strncmp(str, "realloc=", 8)) { |
6446 | pci_realloc_get_opt(str + 8); | |
f483d392 | 6447 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 6448 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
6449 | } else if (!strcmp(str, "nodomains")) { |
6450 | pci_no_domains(); | |
6748dcc2 RW |
6451 | } else if (!strncmp(str, "noari", 5)) { |
6452 | pcie_ari_disabled = true; | |
4516a618 AN |
6453 | } else if (!strncmp(str, "cbiosize=", 9)) { |
6454 | pci_cardbus_io_size = memparse(str + 9, &str); | |
6455 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
6456 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 | 6457 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
70aaf61a | 6458 | resource_alignment_param = str + 19; |
43c16408 AP |
6459 | } else if (!strncmp(str, "ecrc=", 5)) { |
6460 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
6461 | } else if (!strncmp(str, "hpiosize=", 9)) { |
6462 | pci_hotplug_io_size = memparse(str + 9, &str); | |
d7b8a217 NJ |
6463 | } else if (!strncmp(str, "hpmmiosize=", 11)) { |
6464 | pci_hotplug_mmio_size = memparse(str + 11, &str); | |
6465 | } else if (!strncmp(str, "hpmmioprefsize=", 15)) { | |
6466 | pci_hotplug_mmio_pref_size = memparse(str + 15, &str); | |
28760489 | 6467 | } else if (!strncmp(str, "hpmemsize=", 10)) { |
d7b8a217 NJ |
6468 | pci_hotplug_mmio_size = memparse(str + 10, &str); |
6469 | pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size; | |
e16b4660 KB |
6470 | } else if (!strncmp(str, "hpbussize=", 10)) { |
6471 | pci_hotplug_bus_size = | |
6472 | simple_strtoul(str + 10, &str, 0); | |
6473 | if (pci_hotplug_bus_size > 0xff) | |
6474 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
6475 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
6476 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
6477 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
6478 | pcie_bus_config = PCIE_BUS_SAFE; | |
6479 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
6480 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
6481 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
6482 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
6483 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
6484 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
aaca43fd | 6485 | } else if (!strncmp(str, "disable_acs_redir=", 18)) { |
d5bc73f3 | 6486 | disable_acs_redir_param = str + 18; |
309e57df | 6487 | } else { |
25da8dba | 6488 | pr_err("PCI: Unknown option `%s'\n", str); |
309e57df | 6489 | } |
1da177e4 LT |
6490 | } |
6491 | str = k; | |
6492 | } | |
0637a70a | 6493 | return 0; |
1da177e4 | 6494 | } |
0637a70a | 6495 | early_param("pci", pci_setup); |
d5bc73f3 LG |
6496 | |
6497 | /* | |
70aaf61a LG |
6498 | * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized |
6499 | * in pci_setup(), above, to point to data in the __initdata section which | |
6500 | * will be freed after the init sequence is complete. We can't allocate memory | |
6501 | * in pci_setup() because some architectures do not have any memory allocation | |
6502 | * service available during an early_param() call. So we allocate memory and | |
6503 | * copy the variable here before the init section is freed. | |
6504 | * | |
d5bc73f3 LG |
6505 | */ |
6506 | static int __init pci_realloc_setup_params(void) | |
6507 | { | |
70aaf61a LG |
6508 | resource_alignment_param = kstrdup(resource_alignment_param, |
6509 | GFP_KERNEL); | |
d5bc73f3 LG |
6510 | disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL); |
6511 | ||
6512 | return 0; | |
6513 | } | |
6514 | pure_initcall(pci_realloc_setup_params); |