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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
2ab51dde | 10 | #include <linux/acpi.h> |
1da177e4 LT |
11 | #include <linux/kernel.h> |
12 | #include <linux/delay.h> | |
9d26d3a8 | 13 | #include <linux/dmi.h> |
1da177e4 | 14 | #include <linux/init.h> |
7c674700 LP |
15 | #include <linux/of.h> |
16 | #include <linux/of_pci.h> | |
1da177e4 | 17 | #include <linux/pci.h> |
075c1771 | 18 | #include <linux/pm.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1da177e4 LT |
20 | #include <linux/module.h> |
21 | #include <linux/spinlock.h> | |
4e57b681 | 22 | #include <linux/string.h> |
229f5afd | 23 | #include <linux/log2.h> |
046ff9e6 | 24 | #include <linux/logic_pio.h> |
7d715a6c | 25 | #include <linux/pci-aspm.h> |
c300bd2f | 26 | #include <linux/pm_wakeup.h> |
8dd7f803 | 27 | #include <linux/interrupt.h> |
32a9a682 | 28 | #include <linux/device.h> |
b67ea761 | 29 | #include <linux/pm_runtime.h> |
608c3881 | 30 | #include <linux/pci_hotplug.h> |
4d3f1384 | 31 | #include <linux/vmalloc.h> |
4ebeb1ec | 32 | #include <linux/pci-ats.h> |
32a9a682 | 33 | #include <asm/setup.h> |
2a2aca31 | 34 | #include <asm/dma.h> |
b07461a8 | 35 | #include <linux/aer.h> |
bc56b9e0 | 36 | #include "pci.h" |
1da177e4 | 37 | |
00240c38 AS |
38 | const char *pci_power_names[] = { |
39 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
40 | }; | |
41 | EXPORT_SYMBOL_GPL(pci_power_names); | |
42 | ||
93177a74 RW |
43 | int isa_dma_bridge_buggy; |
44 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
45 | ||
46 | int pci_pci_problems; | |
47 | EXPORT_SYMBOL(pci_pci_problems); | |
48 | ||
1ae861e6 RW |
49 | unsigned int pci_pm_d3_delay; |
50 | ||
df17e62e MG |
51 | static void pci_pme_list_scan(struct work_struct *work); |
52 | ||
53 | static LIST_HEAD(pci_pme_list); | |
54 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
55 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
56 | ||
57 | struct pci_pme_device { | |
58 | struct list_head list; | |
59 | struct pci_dev *dev; | |
60 | }; | |
61 | ||
62 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
63 | ||
1ae861e6 RW |
64 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
65 | { | |
66 | unsigned int delay = dev->d3_delay; | |
67 | ||
68 | if (delay < pci_pm_d3_delay) | |
69 | delay = pci_pm_d3_delay; | |
70 | ||
50b2b540 AH |
71 | if (delay) |
72 | msleep(delay); | |
1ae861e6 | 73 | } |
1da177e4 | 74 | |
32a2eea7 JG |
75 | #ifdef CONFIG_PCI_DOMAINS |
76 | int pci_domains_supported = 1; | |
77 | #endif | |
78 | ||
4516a618 AN |
79 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
80 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
81 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
82 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
83 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
84 | ||
28760489 EB |
85 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
86 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
87 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
88 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
89 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
90 | ||
e16b4660 KB |
91 | #define DEFAULT_HOTPLUG_BUS_SIZE 1 |
92 | unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
93 | ||
27d868b5 | 94 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT; |
b03e7495 | 95 | |
ac1aa47b JB |
96 | /* |
97 | * The default CLS is used if arch didn't set CLS explicitly and not | |
98 | * all pci devices agree on the same value. Arch can override either | |
99 | * the dfl or actual value as it sees fit. Don't forget this is | |
100 | * measured in 32-bit words, not bytes. | |
101 | */ | |
15856ad5 | 102 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
103 | u8 pci_cache_line_size; |
104 | ||
96c55900 MS |
105 | /* |
106 | * If we set up a device for bus mastering, we need to check the latency | |
107 | * timer as certain BIOSes forget to set it properly. | |
108 | */ | |
109 | unsigned int pcibios_max_latency = 255; | |
110 | ||
6748dcc2 RW |
111 | /* If set, the PCIe ARI capability will not be used. */ |
112 | static bool pcie_ari_disabled; | |
113 | ||
9d26d3a8 MW |
114 | /* Disable bridge_d3 for all PCIe ports */ |
115 | static bool pci_bridge_d3_disable; | |
116 | /* Force bridge_d3 for all PCIe ports */ | |
117 | static bool pci_bridge_d3_force; | |
118 | ||
119 | static int __init pcie_port_pm_setup(char *str) | |
120 | { | |
121 | if (!strcmp(str, "off")) | |
122 | pci_bridge_d3_disable = true; | |
123 | else if (!strcmp(str, "force")) | |
124 | pci_bridge_d3_force = true; | |
125 | return 1; | |
126 | } | |
127 | __setup("pcie_port_pm=", pcie_port_pm_setup); | |
128 | ||
1da177e4 LT |
129 | /** |
130 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
131 | * @bus: pointer to PCI bus structure to search | |
132 | * | |
133 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
134 | * including the given PCI bus and its list of child PCI buses. | |
135 | */ | |
07656d83 | 136 | unsigned char pci_bus_max_busnr(struct pci_bus *bus) |
1da177e4 | 137 | { |
94e6a9b9 | 138 | struct pci_bus *tmp; |
1da177e4 LT |
139 | unsigned char max, n; |
140 | ||
b918c62e | 141 | max = bus->busn_res.end; |
94e6a9b9 YW |
142 | list_for_each_entry(tmp, &bus->children, node) { |
143 | n = pci_bus_max_busnr(tmp); | |
3c78bc61 | 144 | if (n > max) |
1da177e4 LT |
145 | max = n; |
146 | } | |
147 | return max; | |
148 | } | |
b82db5ce | 149 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 150 | |
1684f5dd AM |
151 | #ifdef CONFIG_HAS_IOMEM |
152 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
153 | { | |
1f7bf3bf BH |
154 | struct resource *res = &pdev->resource[bar]; |
155 | ||
1684f5dd AM |
156 | /* |
157 | * Make sure the BAR is actually a memory resource, not an IO resource | |
158 | */ | |
646c0282 | 159 | if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { |
1f7bf3bf | 160 | dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res); |
1684f5dd AM |
161 | return NULL; |
162 | } | |
1f7bf3bf | 163 | return ioremap_nocache(res->start, resource_size(res)); |
1684f5dd AM |
164 | } |
165 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
c43996f4 LR |
166 | |
167 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) | |
168 | { | |
169 | /* | |
170 | * Make sure the BAR is actually a memory resource, not an IO resource | |
171 | */ | |
172 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
173 | WARN_ON(1); | |
174 | return NULL; | |
175 | } | |
176 | return ioremap_wc(pci_resource_start(pdev, bar), | |
177 | pci_resource_len(pdev, bar)); | |
178 | } | |
179 | EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar); | |
1684f5dd AM |
180 | #endif |
181 | ||
687d5fe3 ME |
182 | |
183 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
184 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
185 | { |
186 | u8 id; | |
55db3208 SS |
187 | u16 ent; |
188 | ||
189 | pci_bus_read_config_byte(bus, devfn, pos, &pos); | |
24a4e377 | 190 | |
687d5fe3 | 191 | while ((*ttl)--) { |
24a4e377 RD |
192 | if (pos < 0x40) |
193 | break; | |
194 | pos &= ~3; | |
55db3208 SS |
195 | pci_bus_read_config_word(bus, devfn, pos, &ent); |
196 | ||
197 | id = ent & 0xff; | |
24a4e377 RD |
198 | if (id == 0xff) |
199 | break; | |
200 | if (id == cap) | |
201 | return pos; | |
55db3208 | 202 | pos = (ent >> 8); |
24a4e377 RD |
203 | } |
204 | return 0; | |
205 | } | |
206 | ||
687d5fe3 ME |
207 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
208 | u8 pos, int cap) | |
209 | { | |
210 | int ttl = PCI_FIND_CAP_TTL; | |
211 | ||
212 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
213 | } | |
214 | ||
24a4e377 RD |
215 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
216 | { | |
217 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
218 | pos + PCI_CAP_LIST_NEXT, cap); | |
219 | } | |
220 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
221 | ||
d3bac118 ME |
222 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
223 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
224 | { |
225 | u16 status; | |
1da177e4 LT |
226 | |
227 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
228 | if (!(status & PCI_STATUS_CAP_LIST)) | |
229 | return 0; | |
230 | ||
231 | switch (hdr_type) { | |
232 | case PCI_HEADER_TYPE_NORMAL: | |
233 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 234 | return PCI_CAPABILITY_LIST; |
1da177e4 | 235 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 236 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 | 237 | } |
d3bac118 ME |
238 | |
239 | return 0; | |
1da177e4 LT |
240 | } |
241 | ||
242 | /** | |
f7625980 | 243 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
244 | * @dev: PCI device to query |
245 | * @cap: capability code | |
246 | * | |
247 | * Tell if a device supports a given PCI capability. | |
248 | * Returns the address of the requested capability structure within the | |
249 | * device's PCI configuration space or 0 in case the device does not | |
250 | * support it. Possible values for @cap: | |
251 | * | |
f7625980 BH |
252 | * %PCI_CAP_ID_PM Power Management |
253 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
254 | * %PCI_CAP_ID_VPD Vital Product Data | |
255 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 256 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 257 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
258 | * %PCI_CAP_ID_PCIX PCI-X |
259 | * %PCI_CAP_ID_EXP PCI Express | |
260 | */ | |
261 | int pci_find_capability(struct pci_dev *dev, int cap) | |
262 | { | |
d3bac118 ME |
263 | int pos; |
264 | ||
265 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
266 | if (pos) | |
267 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
268 | ||
269 | return pos; | |
1da177e4 | 270 | } |
b7fe9434 | 271 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
272 | |
273 | /** | |
f7625980 | 274 | * pci_bus_find_capability - query for devices' capabilities |
1da177e4 LT |
275 | * @bus: the PCI bus to query |
276 | * @devfn: PCI device to query | |
277 | * @cap: capability code | |
278 | * | |
279 | * Like pci_find_capability() but works for pci devices that do not have a | |
f7625980 | 280 | * pci_dev structure set up yet. |
1da177e4 LT |
281 | * |
282 | * Returns the address of the requested capability structure within the | |
283 | * device's PCI configuration space or 0 in case the device does not | |
284 | * support it. | |
285 | */ | |
286 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
287 | { | |
d3bac118 | 288 | int pos; |
1da177e4 LT |
289 | u8 hdr_type; |
290 | ||
291 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
292 | ||
d3bac118 ME |
293 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
294 | if (pos) | |
295 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
296 | ||
297 | return pos; | |
1da177e4 | 298 | } |
b7fe9434 | 299 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
300 | |
301 | /** | |
44a9a36f | 302 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 303 | * @dev: PCI device to query |
44a9a36f | 304 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
305 | * @cap: capability code |
306 | * | |
44a9a36f | 307 | * Returns the address of the next matching extended capability structure |
1da177e4 | 308 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
309 | * not support it. Some capabilities can occur several times, e.g., the |
310 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 311 | */ |
44a9a36f | 312 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
313 | { |
314 | u32 header; | |
557848c3 ZY |
315 | int ttl; |
316 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 317 | |
557848c3 ZY |
318 | /* minimum 8 bytes per capability */ |
319 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
320 | ||
321 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
322 | return 0; |
323 | ||
44a9a36f BH |
324 | if (start) |
325 | pos = start; | |
326 | ||
1da177e4 LT |
327 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
328 | return 0; | |
329 | ||
330 | /* | |
331 | * If we have no capabilities, this is indicated by cap ID, | |
332 | * cap version and next pointer all being 0. | |
333 | */ | |
334 | if (header == 0) | |
335 | return 0; | |
336 | ||
337 | while (ttl-- > 0) { | |
44a9a36f | 338 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
339 | return pos; |
340 | ||
341 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 342 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
343 | break; |
344 | ||
345 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
346 | break; | |
347 | } | |
348 | ||
349 | return 0; | |
350 | } | |
44a9a36f BH |
351 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
352 | ||
353 | /** | |
354 | * pci_find_ext_capability - Find an extended capability | |
355 | * @dev: PCI device to query | |
356 | * @cap: capability code | |
357 | * | |
358 | * Returns the address of the requested extended capability structure | |
359 | * within the device's PCI configuration space or 0 if the device does | |
360 | * not support it. Possible values for @cap: | |
361 | * | |
362 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
363 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
364 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
365 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
366 | */ | |
367 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
368 | { | |
369 | return pci_find_next_ext_capability(dev, 0, cap); | |
370 | } | |
3a720d72 | 371 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 372 | |
687d5fe3 ME |
373 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
374 | { | |
375 | int rc, ttl = PCI_FIND_CAP_TTL; | |
376 | u8 cap, mask; | |
377 | ||
378 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
379 | mask = HT_3BIT_CAP_MASK; | |
380 | else | |
381 | mask = HT_5BIT_CAP_MASK; | |
382 | ||
383 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
384 | PCI_CAP_ID_HT, &ttl); | |
385 | while (pos) { | |
386 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
387 | if (rc != PCIBIOS_SUCCESSFUL) | |
388 | return 0; | |
389 | ||
390 | if ((cap & mask) == ht_cap) | |
391 | return pos; | |
392 | ||
47a4d5be BG |
393 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
394 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
395 | PCI_CAP_ID_HT, &ttl); |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | /** | |
401 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
402 | * @dev: PCI device to query | |
403 | * @pos: Position from which to continue searching | |
404 | * @ht_cap: Hypertransport capability code | |
405 | * | |
406 | * To be used in conjunction with pci_find_ht_capability() to search for | |
407 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
408 | * from pci_find_ht_capability(). | |
409 | * | |
410 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
411 | * steps to avoid an infinite loop. | |
412 | */ | |
413 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
414 | { | |
415 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
416 | } | |
417 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
418 | ||
419 | /** | |
420 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
421 | * @dev: PCI device to query | |
422 | * @ht_cap: Hypertransport capability code | |
423 | * | |
424 | * Tell if a device supports a given Hypertransport capability. | |
425 | * Returns an address within the device's PCI configuration space | |
426 | * or 0 in case the device does not support the request capability. | |
427 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
428 | * which has a Hypertransport capability matching @ht_cap. | |
429 | */ | |
430 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
431 | { | |
432 | int pos; | |
433 | ||
434 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
435 | if (pos) | |
436 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
437 | ||
438 | return pos; | |
439 | } | |
440 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
441 | ||
1da177e4 LT |
442 | /** |
443 | * pci_find_parent_resource - return resource region of parent bus of given region | |
444 | * @dev: PCI device structure contains resources to be searched | |
445 | * @res: child resource record for which parent is sought | |
446 | * | |
447 | * For given resource region of given device, return the resource | |
f44116ae | 448 | * region of parent bus the given region is contained in. |
1da177e4 | 449 | */ |
3c78bc61 RD |
450 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
451 | struct resource *res) | |
1da177e4 LT |
452 | { |
453 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 454 | struct resource *r; |
1da177e4 | 455 | int i; |
1da177e4 | 456 | |
89a74ecc | 457 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
458 | if (!r) |
459 | continue; | |
31342330 | 460 | if (resource_contains(r, res)) { |
f44116ae BH |
461 | |
462 | /* | |
463 | * If the window is prefetchable but the BAR is | |
464 | * not, the allocator made a mistake. | |
465 | */ | |
466 | if (r->flags & IORESOURCE_PREFETCH && | |
467 | !(res->flags & IORESOURCE_PREFETCH)) | |
468 | return NULL; | |
469 | ||
470 | /* | |
471 | * If we're below a transparent bridge, there may | |
472 | * be both a positively-decoded aperture and a | |
473 | * subtractively-decoded region that contain the BAR. | |
474 | * We want the positively-decoded one, so this depends | |
475 | * on pci_bus_for_each_resource() giving us those | |
476 | * first. | |
477 | */ | |
478 | return r; | |
479 | } | |
1da177e4 | 480 | } |
f44116ae | 481 | return NULL; |
1da177e4 | 482 | } |
b7fe9434 | 483 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 484 | |
afd29f90 MW |
485 | /** |
486 | * pci_find_resource - Return matching PCI device resource | |
487 | * @dev: PCI device to query | |
488 | * @res: Resource to look for | |
489 | * | |
490 | * Goes over standard PCI resources (BARs) and checks if the given resource | |
491 | * is partially or fully contained in any of them. In that case the | |
492 | * matching resource is returned, %NULL otherwise. | |
493 | */ | |
494 | struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res) | |
495 | { | |
496 | int i; | |
497 | ||
498 | for (i = 0; i < PCI_ROM_RESOURCE; i++) { | |
499 | struct resource *r = &dev->resource[i]; | |
500 | ||
501 | if (r->start && resource_contains(r, res)) | |
502 | return r; | |
503 | } | |
504 | ||
505 | return NULL; | |
506 | } | |
507 | EXPORT_SYMBOL(pci_find_resource); | |
508 | ||
c56d4450 HS |
509 | /** |
510 | * pci_find_pcie_root_port - return PCIe Root Port | |
511 | * @dev: PCI device to query | |
512 | * | |
513 | * Traverse up the parent chain and return the PCIe Root Port PCI Device | |
514 | * for a given PCI Device. | |
515 | */ | |
516 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev) | |
517 | { | |
b6f6d56c | 518 | struct pci_dev *bridge, *highest_pcie_bridge = dev; |
c56d4450 HS |
519 | |
520 | bridge = pci_upstream_bridge(dev); | |
521 | while (bridge && pci_is_pcie(bridge)) { | |
522 | highest_pcie_bridge = bridge; | |
523 | bridge = pci_upstream_bridge(bridge); | |
524 | } | |
525 | ||
b6f6d56c TR |
526 | if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT) |
527 | return NULL; | |
c56d4450 | 528 | |
b6f6d56c | 529 | return highest_pcie_bridge; |
c56d4450 HS |
530 | } |
531 | EXPORT_SYMBOL(pci_find_pcie_root_port); | |
532 | ||
157e876f AW |
533 | /** |
534 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
535 | * @dev: the PCI device to operate on | |
536 | * @pos: config space offset of status word | |
537 | * @mask: mask of bit(s) to care about in status word | |
538 | * | |
539 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
540 | */ | |
541 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
542 | { | |
543 | int i; | |
544 | ||
545 | /* Wait for Transaction Pending bit clean */ | |
546 | for (i = 0; i < 4; i++) { | |
547 | u16 status; | |
548 | if (i) | |
549 | msleep((1 << (i - 1)) * 100); | |
550 | ||
551 | pci_read_config_word(dev, pos, &status); | |
552 | if (!(status & mask)) | |
553 | return 1; | |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
064b53db | 559 | /** |
70675e0b | 560 | * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) |
064b53db JL |
561 | * @dev: PCI device to have its BARs restored |
562 | * | |
563 | * Restore the BAR values for a given device, so as to make it | |
564 | * accessible by its driver. | |
565 | */ | |
3c78bc61 | 566 | static void pci_restore_bars(struct pci_dev *dev) |
064b53db | 567 | { |
bc5f5a82 | 568 | int i; |
064b53db | 569 | |
bc5f5a82 | 570 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 571 | pci_update_resource(dev, i); |
064b53db JL |
572 | } |
573 | ||
299f2ffe | 574 | static const struct pci_platform_pm_ops *pci_platform_pm; |
961d9120 | 575 | |
299f2ffe | 576 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops) |
961d9120 | 577 | { |
cc7cc02b | 578 | if (!ops->is_manageable || !ops->set_state || !ops->get_state || |
0847684c | 579 | !ops->choose_state || !ops->set_wakeup || !ops->need_resume) |
961d9120 RW |
580 | return -EINVAL; |
581 | pci_platform_pm = ops; | |
582 | return 0; | |
583 | } | |
584 | ||
585 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
586 | { | |
587 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
588 | } | |
589 | ||
590 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
3c78bc61 | 591 | pci_power_t t) |
961d9120 RW |
592 | { |
593 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
594 | } | |
595 | ||
cc7cc02b LW |
596 | static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev) |
597 | { | |
598 | return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; | |
599 | } | |
600 | ||
961d9120 RW |
601 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) |
602 | { | |
603 | return pci_platform_pm ? | |
604 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
605 | } | |
8f7020d3 | 606 | |
0847684c | 607 | static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
608 | { |
609 | return pci_platform_pm ? | |
0847684c | 610 | pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; |
b67ea761 RW |
611 | } |
612 | ||
bac2a909 RW |
613 | static inline bool platform_pci_need_resume(struct pci_dev *dev) |
614 | { | |
615 | return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; | |
616 | } | |
617 | ||
1da177e4 | 618 | /** |
44e4e66e RW |
619 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
620 | * given PCI device | |
621 | * @dev: PCI device to handle. | |
44e4e66e | 622 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 623 | * |
44e4e66e RW |
624 | * RETURN VALUE: |
625 | * -EINVAL if the requested state is invalid. | |
626 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
627 | * wrong version, or device doesn't support the requested state. | |
628 | * 0 if device already is in the requested state. | |
629 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 630 | */ |
f00a20ef | 631 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 632 | { |
337001b6 | 633 | u16 pmcsr; |
44e4e66e | 634 | bool need_restore = false; |
1da177e4 | 635 | |
4a865905 RW |
636 | /* Check if we're already there */ |
637 | if (dev->current_state == state) | |
638 | return 0; | |
639 | ||
337001b6 | 640 | if (!dev->pm_cap) |
cca03dec AL |
641 | return -EIO; |
642 | ||
44e4e66e RW |
643 | if (state < PCI_D0 || state > PCI_D3hot) |
644 | return -EINVAL; | |
645 | ||
1da177e4 | 646 | /* Validate current state: |
f7625980 | 647 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
648 | * to sleep if we're already in a low power state |
649 | */ | |
4a865905 | 650 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 651 | && dev->current_state > state) { |
227f0647 RD |
652 | dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n", |
653 | dev->current_state, state); | |
1da177e4 | 654 | return -EINVAL; |
44e4e66e | 655 | } |
1da177e4 | 656 | |
1da177e4 | 657 | /* check if this device supports the desired state */ |
337001b6 RW |
658 | if ((state == PCI_D1 && !dev->d1_support) |
659 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 660 | return -EIO; |
1da177e4 | 661 | |
337001b6 | 662 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 663 | |
32a36585 | 664 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
665 | * This doesn't affect PME_Status, disables PME_En, and |
666 | * sets PowerState to 0. | |
667 | */ | |
32a36585 | 668 | switch (dev->current_state) { |
d3535fbb JL |
669 | case PCI_D0: |
670 | case PCI_D1: | |
671 | case PCI_D2: | |
672 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
673 | pmcsr |= state; | |
674 | break; | |
f62795f1 RW |
675 | case PCI_D3hot: |
676 | case PCI_D3cold: | |
32a36585 JL |
677 | case PCI_UNKNOWN: /* Boot-up */ |
678 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 679 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 680 | need_restore = true; |
32a36585 | 681 | /* Fall-through: force to D0 */ |
32a36585 | 682 | default: |
d3535fbb | 683 | pmcsr = 0; |
32a36585 | 684 | break; |
1da177e4 LT |
685 | } |
686 | ||
687 | /* enter specified state */ | |
337001b6 | 688 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
689 | |
690 | /* Mandatory power management transition delays */ | |
691 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
692 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 693 | pci_dev_d3_sleep(dev); |
1da177e4 | 694 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 695 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 696 | |
e13cdbd7 RW |
697 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
698 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
699 | if (dev->current_state != state && printk_ratelimit()) | |
227f0647 RD |
700 | dev_info(&dev->dev, "Refused to change power state, currently in D%d\n", |
701 | dev->current_state); | |
064b53db | 702 | |
448bd857 HY |
703 | /* |
704 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
705 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
706 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
707 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
708 | * For example, at least some versions of the 3c905B and the | |
709 | * 3c556B exhibit this behaviour. | |
710 | * | |
711 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
712 | * devices in a D3hot state at boot. Consequently, we need to | |
713 | * restore at least the BARs so that the device will be | |
714 | * accessible to its driver. | |
715 | */ | |
716 | if (need_restore) | |
717 | pci_restore_bars(dev); | |
718 | ||
f00a20ef | 719 | if (dev->bus->self) |
7d715a6c SL |
720 | pcie_aspm_pm_state_change(dev->bus->self); |
721 | ||
1da177e4 LT |
722 | return 0; |
723 | } | |
724 | ||
44e4e66e | 725 | /** |
a6a64026 | 726 | * pci_update_current_state - Read power state of given device and cache it |
44e4e66e | 727 | * @dev: PCI device to handle. |
f06fc0b6 | 728 | * @state: State to cache in case the device doesn't have the PM capability |
a6a64026 LW |
729 | * |
730 | * The power state is read from the PMCSR register, which however is | |
731 | * inaccessible in D3cold. The platform firmware is therefore queried first | |
732 | * to detect accessibility of the register. In case the platform firmware | |
733 | * reports an incorrect state or the device isn't power manageable by the | |
734 | * platform at all, we try to detect D3cold by testing accessibility of the | |
735 | * vendor ID in config space. | |
44e4e66e | 736 | */ |
73410429 | 737 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 738 | { |
a6a64026 LW |
739 | if (platform_pci_get_power_state(dev) == PCI_D3cold || |
740 | !pci_device_is_present(dev)) { | |
741 | dev->current_state = PCI_D3cold; | |
742 | } else if (dev->pm_cap) { | |
44e4e66e RW |
743 | u16 pmcsr; |
744 | ||
337001b6 | 745 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 746 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
747 | } else { |
748 | dev->current_state = state; | |
44e4e66e RW |
749 | } |
750 | } | |
751 | ||
db288c9c RW |
752 | /** |
753 | * pci_power_up - Put the given device into D0 forcibly | |
754 | * @dev: PCI device to power up | |
755 | */ | |
756 | void pci_power_up(struct pci_dev *dev) | |
757 | { | |
758 | if (platform_pci_power_manageable(dev)) | |
759 | platform_pci_set_power_state(dev, PCI_D0); | |
760 | ||
761 | pci_raw_set_power_state(dev, PCI_D0); | |
762 | pci_update_current_state(dev, PCI_D0); | |
763 | } | |
764 | ||
0e5dd46b RW |
765 | /** |
766 | * pci_platform_power_transition - Use platform to change device power state | |
767 | * @dev: PCI device to handle. | |
768 | * @state: State to put the device into. | |
769 | */ | |
770 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
771 | { | |
772 | int error; | |
773 | ||
774 | if (platform_pci_power_manageable(dev)) { | |
775 | error = platform_pci_set_power_state(dev, state); | |
776 | if (!error) | |
777 | pci_update_current_state(dev, state); | |
769ba721 | 778 | } else |
0e5dd46b | 779 | error = -ENODEV; |
769ba721 RW |
780 | |
781 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
782 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
783 | |
784 | return error; | |
785 | } | |
786 | ||
0b950f0f SH |
787 | /** |
788 | * pci_wakeup - Wake up a PCI device | |
789 | * @pci_dev: Device to handle. | |
790 | * @ign: ignored parameter | |
791 | */ | |
792 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
793 | { | |
794 | pci_wakeup_event(pci_dev); | |
795 | pm_request_resume(&pci_dev->dev); | |
796 | return 0; | |
797 | } | |
798 | ||
799 | /** | |
800 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
801 | * @bus: Top bus of the subtree to walk. | |
802 | */ | |
803 | static void pci_wakeup_bus(struct pci_bus *bus) | |
804 | { | |
805 | if (bus) | |
806 | pci_walk_bus(bus, pci_wakeup, NULL); | |
807 | } | |
808 | ||
0e5dd46b RW |
809 | /** |
810 | * __pci_start_power_transition - Start power transition of a PCI device | |
811 | * @dev: PCI device to handle. | |
812 | * @state: State to put the device into. | |
813 | */ | |
814 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
815 | { | |
448bd857 | 816 | if (state == PCI_D0) { |
0e5dd46b | 817 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
818 | /* |
819 | * Mandatory power management transition delays, see | |
820 | * PCI Express Base Specification Revision 2.0 Section | |
821 | * 6.6.1: Conventional Reset. Do not delay for | |
822 | * devices powered on/off by corresponding bridge, | |
823 | * because have already delayed for the bridge. | |
824 | */ | |
825 | if (dev->runtime_d3cold) { | |
50b2b540 AH |
826 | if (dev->d3cold_delay) |
827 | msleep(dev->d3cold_delay); | |
448bd857 HY |
828 | /* |
829 | * When powering on a bridge from D3cold, the | |
830 | * whole hierarchy may be powered on into | |
831 | * D0uninitialized state, resume them to give | |
832 | * them a chance to suspend again | |
833 | */ | |
834 | pci_wakeup_bus(dev->subordinate); | |
835 | } | |
836 | } | |
837 | } | |
838 | ||
839 | /** | |
840 | * __pci_dev_set_current_state - Set current state of a PCI device | |
841 | * @dev: Device to handle | |
842 | * @data: pointer to state to be set | |
843 | */ | |
844 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
845 | { | |
846 | pci_power_t state = *(pci_power_t *)data; | |
847 | ||
848 | dev->current_state = state; | |
849 | return 0; | |
850 | } | |
851 | ||
852 | /** | |
853 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
854 | * @bus: Top bus of the subtree to walk. | |
855 | * @state: state to be set | |
856 | */ | |
857 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
858 | { | |
859 | if (bus) | |
860 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
861 | } |
862 | ||
863 | /** | |
864 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
865 | * @dev: PCI device to handle. | |
866 | * @state: State to put the device into. | |
867 | * | |
868 | * This function should not be called directly by device drivers. | |
869 | */ | |
870 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
871 | { | |
448bd857 HY |
872 | int ret; |
873 | ||
db288c9c | 874 | if (state <= PCI_D0) |
448bd857 HY |
875 | return -EINVAL; |
876 | ret = pci_platform_power_transition(dev, state); | |
877 | /* Power off the bridge may power off the whole hierarchy */ | |
878 | if (!ret && state == PCI_D3cold) | |
879 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
880 | return ret; | |
0e5dd46b RW |
881 | } |
882 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
883 | ||
44e4e66e RW |
884 | /** |
885 | * pci_set_power_state - Set the power state of a PCI device | |
886 | * @dev: PCI device to handle. | |
887 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
888 | * | |
877d0310 | 889 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
890 | * the device's PCI PM registers. |
891 | * | |
892 | * RETURN VALUE: | |
893 | * -EINVAL if the requested state is invalid. | |
894 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
895 | * wrong version, or device doesn't support the requested state. | |
ab4b8a47 | 896 | * 0 if the transition is to D1 or D2 but D1 and D2 are not supported. |
44e4e66e | 897 | * 0 if device already is in the requested state. |
ab4b8a47 | 898 | * 0 if the transition is to D3 but D3 is not supported. |
44e4e66e RW |
899 | * 0 if device's power state has been successfully changed. |
900 | */ | |
901 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
902 | { | |
337001b6 | 903 | int error; |
44e4e66e RW |
904 | |
905 | /* bound the state we're entering */ | |
448bd857 HY |
906 | if (state > PCI_D3cold) |
907 | state = PCI_D3cold; | |
44e4e66e RW |
908 | else if (state < PCI_D0) |
909 | state = PCI_D0; | |
910 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
911 | /* | |
912 | * If the device or the parent bridge do not support PCI PM, | |
913 | * ignore the request if we're doing anything other than putting | |
914 | * it into D0 (which would only happen on boot). | |
915 | */ | |
916 | return 0; | |
917 | ||
db288c9c RW |
918 | /* Check if we're already there */ |
919 | if (dev->current_state == state) | |
920 | return 0; | |
921 | ||
0e5dd46b RW |
922 | __pci_start_power_transition(dev, state); |
923 | ||
979b1791 AC |
924 | /* This device is quirked not to be put into D3, so |
925 | don't put it in D3 */ | |
448bd857 | 926 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 927 | return 0; |
44e4e66e | 928 | |
448bd857 HY |
929 | /* |
930 | * To put device in D3cold, we put device into D3hot in native | |
931 | * way, then put device into D3cold with platform ops | |
932 | */ | |
933 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
934 | PCI_D3hot : state); | |
44e4e66e | 935 | |
0e5dd46b RW |
936 | if (!__pci_complete_power_transition(dev, state)) |
937 | error = 0; | |
44e4e66e RW |
938 | |
939 | return error; | |
940 | } | |
b7fe9434 | 941 | EXPORT_SYMBOL(pci_set_power_state); |
44e4e66e | 942 | |
1da177e4 LT |
943 | /** |
944 | * pci_choose_state - Choose the power state of a PCI device | |
945 | * @dev: PCI device to be suspended | |
946 | * @state: target sleep state for the whole system. This is the value | |
947 | * that is passed to suspend() function. | |
948 | * | |
949 | * Returns PCI power state suitable for given device and given system | |
950 | * message. | |
951 | */ | |
952 | ||
953 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
954 | { | |
ab826ca4 | 955 | pci_power_t ret; |
0f64474b | 956 | |
728cdb75 | 957 | if (!dev->pm_cap) |
1da177e4 LT |
958 | return PCI_D0; |
959 | ||
961d9120 RW |
960 | ret = platform_pci_choose_state(dev); |
961 | if (ret != PCI_POWER_ERROR) | |
962 | return ret; | |
ca078bae PM |
963 | |
964 | switch (state.event) { | |
965 | case PM_EVENT_ON: | |
966 | return PCI_D0; | |
967 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
968 | case PM_EVENT_PRETHAW: |
969 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 970 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 971 | case PM_EVENT_HIBERNATE: |
ca078bae | 972 | return PCI_D3hot; |
1da177e4 | 973 | default: |
80ccba11 BH |
974 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
975 | state.event); | |
1da177e4 LT |
976 | BUG(); |
977 | } | |
978 | return PCI_D0; | |
979 | } | |
1da177e4 LT |
980 | EXPORT_SYMBOL(pci_choose_state); |
981 | ||
89858517 YZ |
982 | #define PCI_EXP_SAVE_REGS 7 |
983 | ||
fd0f7f73 AW |
984 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
985 | u16 cap, bool extended) | |
34a4876e YL |
986 | { |
987 | struct pci_cap_saved_state *tmp; | |
34a4876e | 988 | |
b67bfe0d | 989 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 990 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
991 | return tmp; |
992 | } | |
993 | return NULL; | |
994 | } | |
995 | ||
fd0f7f73 AW |
996 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
997 | { | |
998 | return _pci_find_saved_cap(dev, cap, false); | |
999 | } | |
1000 | ||
1001 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
1002 | { | |
1003 | return _pci_find_saved_cap(dev, cap, true); | |
1004 | } | |
1005 | ||
b56a5a23 MT |
1006 | static int pci_save_pcie_state(struct pci_dev *dev) |
1007 | { | |
59875ae4 | 1008 | int i = 0; |
b56a5a23 MT |
1009 | struct pci_cap_saved_state *save_state; |
1010 | u16 *cap; | |
1011 | ||
59875ae4 | 1012 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
1013 | return 0; |
1014 | ||
9f35575d | 1015 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 1016 | if (!save_state) { |
e496b617 | 1017 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
1018 | return -ENOMEM; |
1019 | } | |
63f4898a | 1020 | |
59875ae4 JL |
1021 | cap = (u16 *)&save_state->cap.data[0]; |
1022 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
1023 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
1024 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
1025 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
1026 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
1027 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
1028 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 1029 | |
b56a5a23 MT |
1030 | return 0; |
1031 | } | |
1032 | ||
1033 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
1034 | { | |
59875ae4 | 1035 | int i = 0; |
b56a5a23 MT |
1036 | struct pci_cap_saved_state *save_state; |
1037 | u16 *cap; | |
1038 | ||
1039 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 1040 | if (!save_state) |
9cb604ed MS |
1041 | return; |
1042 | ||
59875ae4 JL |
1043 | cap = (u16 *)&save_state->cap.data[0]; |
1044 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
1045 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
1046 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
1047 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
1048 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
1049 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
1050 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
1051 | } |
1052 | ||
cc692a5f SH |
1053 | |
1054 | static int pci_save_pcix_state(struct pci_dev *dev) | |
1055 | { | |
63f4898a | 1056 | int pos; |
cc692a5f | 1057 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
1058 | |
1059 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1060 | if (!pos) |
cc692a5f SH |
1061 | return 0; |
1062 | ||
f34303de | 1063 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 1064 | if (!save_state) { |
e496b617 | 1065 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
1066 | return -ENOMEM; |
1067 | } | |
cc692a5f | 1068 | |
24a4742f AW |
1069 | pci_read_config_word(dev, pos + PCI_X_CMD, |
1070 | (u16 *)save_state->cap.data); | |
63f4898a | 1071 | |
cc692a5f SH |
1072 | return 0; |
1073 | } | |
1074 | ||
1075 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
1076 | { | |
1077 | int i = 0, pos; | |
1078 | struct pci_cap_saved_state *save_state; | |
1079 | u16 *cap; | |
1080 | ||
1081 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
1082 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
0a1a9b49 | 1083 | if (!save_state || !pos) |
cc692a5f | 1084 | return; |
24a4742f | 1085 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
1086 | |
1087 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1088 | } |
1089 | ||
1090 | ||
1da177e4 LT |
1091 | /** |
1092 | * pci_save_state - save the PCI configuration space of a device before suspending | |
1093 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1094 | */ |
3c78bc61 | 1095 | int pci_save_state(struct pci_dev *dev) |
1da177e4 LT |
1096 | { |
1097 | int i; | |
1098 | /* XXX: 100% dword access ok here? */ | |
1099 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1100 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1101 | dev->state_saved = true; |
79e50e72 QL |
1102 | |
1103 | i = pci_save_pcie_state(dev); | |
1104 | if (i != 0) | |
b56a5a23 | 1105 | return i; |
79e50e72 QL |
1106 | |
1107 | i = pci_save_pcix_state(dev); | |
1108 | if (i != 0) | |
cc692a5f | 1109 | return i; |
79e50e72 | 1110 | |
754834b9 | 1111 | return pci_save_vc_state(dev); |
1da177e4 | 1112 | } |
b7fe9434 | 1113 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1114 | |
ebfc5b80 RW |
1115 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
1116 | u32 saved_val, int retry) | |
1117 | { | |
1118 | u32 val; | |
1119 | ||
1120 | pci_read_config_dword(pdev, offset, &val); | |
1121 | if (val == saved_val) | |
1122 | return; | |
1123 | ||
1124 | for (;;) { | |
227f0647 RD |
1125 | dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n", |
1126 | offset, val, saved_val); | |
ebfc5b80 RW |
1127 | pci_write_config_dword(pdev, offset, saved_val); |
1128 | if (retry-- <= 0) | |
1129 | return; | |
1130 | ||
1131 | pci_read_config_dword(pdev, offset, &val); | |
1132 | if (val == saved_val) | |
1133 | return; | |
1134 | ||
1135 | mdelay(1); | |
1136 | } | |
1137 | } | |
1138 | ||
a6cb9ee7 RW |
1139 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
1140 | int start, int end, int retry) | |
ebfc5b80 RW |
1141 | { |
1142 | int index; | |
1143 | ||
1144 | for (index = end; index >= start; index--) | |
1145 | pci_restore_config_dword(pdev, 4 * index, | |
1146 | pdev->saved_config_space[index], | |
1147 | retry); | |
1148 | } | |
1149 | ||
a6cb9ee7 RW |
1150 | static void pci_restore_config_space(struct pci_dev *pdev) |
1151 | { | |
1152 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
1153 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
1154 | /* Restore BARs before the command register. */ | |
1155 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
1156 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
1157 | } else { | |
1158 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
1159 | } | |
1160 | } | |
1161 | ||
f7625980 | 1162 | /** |
1da177e4 LT |
1163 | * pci_restore_state - Restore the saved state of a PCI device |
1164 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1165 | */ |
1d3c16a8 | 1166 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1167 | { |
c82f63e4 | 1168 | if (!dev->state_saved) |
1d3c16a8 | 1169 | return; |
4b77b0a2 | 1170 | |
b56a5a23 MT |
1171 | /* PCI Express register must be restored first */ |
1172 | pci_restore_pcie_state(dev); | |
4ebeb1ec CT |
1173 | pci_restore_pasid_state(dev); |
1174 | pci_restore_pri_state(dev); | |
1900ca13 | 1175 | pci_restore_ats_state(dev); |
425c1b22 | 1176 | pci_restore_vc_state(dev); |
b56a5a23 | 1177 | |
b07461a8 TI |
1178 | pci_cleanup_aer_error_status_regs(dev); |
1179 | ||
a6cb9ee7 | 1180 | pci_restore_config_space(dev); |
ebfc5b80 | 1181 | |
cc692a5f | 1182 | pci_restore_pcix_state(dev); |
41017f0c | 1183 | pci_restore_msi_state(dev); |
ccbc175a AD |
1184 | |
1185 | /* Restore ACS and IOV configuration state */ | |
1186 | pci_enable_acs(dev); | |
8c5cdb6a | 1187 | pci_restore_iov_state(dev); |
8fed4b65 | 1188 | |
4b77b0a2 | 1189 | dev->state_saved = false; |
1da177e4 | 1190 | } |
b7fe9434 | 1191 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1192 | |
ffbdd3f7 AW |
1193 | struct pci_saved_state { |
1194 | u32 config_space[16]; | |
1195 | struct pci_cap_saved_data cap[0]; | |
1196 | }; | |
1197 | ||
1198 | /** | |
1199 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1200 | * the device saved state. | |
1201 | * @dev: PCI device that we're dealing with | |
1202 | * | |
f7625980 | 1203 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1204 | */ |
1205 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1206 | { | |
1207 | struct pci_saved_state *state; | |
1208 | struct pci_cap_saved_state *tmp; | |
1209 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1210 | size_t size; |
1211 | ||
1212 | if (!dev->state_saved) | |
1213 | return NULL; | |
1214 | ||
1215 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1216 | ||
b67bfe0d | 1217 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1218 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1219 | ||
1220 | state = kzalloc(size, GFP_KERNEL); | |
1221 | if (!state) | |
1222 | return NULL; | |
1223 | ||
1224 | memcpy(state->config_space, dev->saved_config_space, | |
1225 | sizeof(state->config_space)); | |
1226 | ||
1227 | cap = state->cap; | |
b67bfe0d | 1228 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1229 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1230 | memcpy(cap, &tmp->cap, len); | |
1231 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1232 | } | |
1233 | /* Empty cap_save terminates list */ | |
1234 | ||
1235 | return state; | |
1236 | } | |
1237 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1238 | ||
1239 | /** | |
1240 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1241 | * @dev: PCI device that we're dealing with | |
1242 | * @state: Saved state returned from pci_store_saved_state() | |
1243 | */ | |
98d9b271 KRW |
1244 | int pci_load_saved_state(struct pci_dev *dev, |
1245 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1246 | { |
1247 | struct pci_cap_saved_data *cap; | |
1248 | ||
1249 | dev->state_saved = false; | |
1250 | ||
1251 | if (!state) | |
1252 | return 0; | |
1253 | ||
1254 | memcpy(dev->saved_config_space, state->config_space, | |
1255 | sizeof(state->config_space)); | |
1256 | ||
1257 | cap = state->cap; | |
1258 | while (cap->size) { | |
1259 | struct pci_cap_saved_state *tmp; | |
1260 | ||
fd0f7f73 | 1261 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1262 | if (!tmp || tmp->cap.size != cap->size) |
1263 | return -EINVAL; | |
1264 | ||
1265 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1266 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1267 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1268 | } | |
1269 | ||
1270 | dev->state_saved = true; | |
1271 | return 0; | |
1272 | } | |
98d9b271 | 1273 | EXPORT_SYMBOL_GPL(pci_load_saved_state); |
ffbdd3f7 AW |
1274 | |
1275 | /** | |
1276 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1277 | * and free the memory allocated for it. | |
1278 | * @dev: PCI device that we're dealing with | |
1279 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1280 | */ | |
1281 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1282 | struct pci_saved_state **state) | |
1283 | { | |
1284 | int ret = pci_load_saved_state(dev, *state); | |
1285 | kfree(*state); | |
1286 | *state = NULL; | |
1287 | return ret; | |
1288 | } | |
1289 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1290 | ||
8a9d5609 BH |
1291 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1292 | { | |
1293 | return pci_enable_resources(dev, bars); | |
1294 | } | |
1295 | ||
38cc1302 HS |
1296 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1297 | { | |
1298 | int err; | |
1f6ae47e | 1299 | struct pci_dev *bridge; |
1e2571a7 BH |
1300 | u16 cmd; |
1301 | u8 pin; | |
38cc1302 HS |
1302 | |
1303 | err = pci_set_power_state(dev, PCI_D0); | |
1304 | if (err < 0 && err != -EIO) | |
1305 | return err; | |
1f6ae47e VS |
1306 | |
1307 | bridge = pci_upstream_bridge(dev); | |
1308 | if (bridge) | |
1309 | pcie_aspm_powersave_config_link(bridge); | |
1310 | ||
38cc1302 HS |
1311 | err = pcibios_enable_device(dev, bars); |
1312 | if (err < 0) | |
1313 | return err; | |
1314 | pci_fixup_device(pci_fixup_enable, dev); | |
1315 | ||
866d5417 BH |
1316 | if (dev->msi_enabled || dev->msix_enabled) |
1317 | return 0; | |
1318 | ||
1e2571a7 BH |
1319 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1320 | if (pin) { | |
1321 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1322 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1323 | pci_write_config_word(dev, PCI_COMMAND, | |
1324 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1325 | } | |
1326 | ||
38cc1302 HS |
1327 | return 0; |
1328 | } | |
1329 | ||
1330 | /** | |
0b62e13b | 1331 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1332 | * @dev: PCI device to be resumed |
1333 | * | |
1334 | * Note this function is a backend of pci_default_resume and is not supposed | |
1335 | * to be called by normal code, write proper resume handler and use it instead. | |
1336 | */ | |
0b62e13b | 1337 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1338 | { |
296ccb08 | 1339 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1340 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1341 | return 0; | |
1342 | } | |
b7fe9434 | 1343 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1344 | |
928bea96 YL |
1345 | static void pci_enable_bridge(struct pci_dev *dev) |
1346 | { | |
79272138 | 1347 | struct pci_dev *bridge; |
928bea96 YL |
1348 | int retval; |
1349 | ||
79272138 BH |
1350 | bridge = pci_upstream_bridge(dev); |
1351 | if (bridge) | |
1352 | pci_enable_bridge(bridge); | |
928bea96 | 1353 | |
cf3e1feb | 1354 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1355 | if (!dev->is_busmaster) |
cf3e1feb | 1356 | pci_set_master(dev); |
0f50a49e | 1357 | return; |
cf3e1feb YL |
1358 | } |
1359 | ||
928bea96 YL |
1360 | retval = pci_enable_device(dev); |
1361 | if (retval) | |
1362 | dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", | |
1363 | retval); | |
1364 | pci_set_master(dev); | |
1365 | } | |
1366 | ||
b4b4fbba | 1367 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1368 | { |
79272138 | 1369 | struct pci_dev *bridge; |
1da177e4 | 1370 | int err; |
b718989d | 1371 | int i, bars = 0; |
1da177e4 | 1372 | |
97c145f7 JB |
1373 | /* |
1374 | * Power state could be unknown at this point, either due to a fresh | |
1375 | * boot or a device removal call. So get the current power state | |
1376 | * so that things like MSI message writing will behave as expected | |
1377 | * (e.g. if the device really is in D0 at enable time). | |
1378 | */ | |
1379 | if (dev->pm_cap) { | |
1380 | u16 pmcsr; | |
1381 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1382 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1383 | } | |
1384 | ||
cc7ba39b | 1385 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1386 | return 0; /* already enabled */ |
1387 | ||
79272138 | 1388 | bridge = pci_upstream_bridge(dev); |
0f50a49e | 1389 | if (bridge) |
79272138 | 1390 | pci_enable_bridge(bridge); |
928bea96 | 1391 | |
497f16f2 YL |
1392 | /* only skip sriov related */ |
1393 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1394 | if (dev->resource[i].flags & flags) | |
1395 | bars |= (1 << i); | |
1396 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1397 | if (dev->resource[i].flags & flags) |
1398 | bars |= (1 << i); | |
1399 | ||
38cc1302 | 1400 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1401 | if (err < 0) |
38cc1302 | 1402 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1403 | return err; |
1da177e4 LT |
1404 | } |
1405 | ||
b718989d BH |
1406 | /** |
1407 | * pci_enable_device_io - Initialize a device for use with IO space | |
1408 | * @dev: PCI device to be initialized | |
1409 | * | |
1410 | * Initialize device before it's used by a driver. Ask low-level code | |
1411 | * to enable I/O resources. Wake up the device if it was suspended. | |
1412 | * Beware, this function can fail. | |
1413 | */ | |
1414 | int pci_enable_device_io(struct pci_dev *dev) | |
1415 | { | |
b4b4fbba | 1416 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1417 | } |
b7fe9434 | 1418 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1419 | |
1420 | /** | |
1421 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1422 | * @dev: PCI device to be initialized | |
1423 | * | |
1424 | * Initialize device before it's used by a driver. Ask low-level code | |
1425 | * to enable Memory resources. Wake up the device if it was suspended. | |
1426 | * Beware, this function can fail. | |
1427 | */ | |
1428 | int pci_enable_device_mem(struct pci_dev *dev) | |
1429 | { | |
b4b4fbba | 1430 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1431 | } |
b7fe9434 | 1432 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1433 | |
bae94d02 IPG |
1434 | /** |
1435 | * pci_enable_device - Initialize device before it's used by a driver. | |
1436 | * @dev: PCI device to be initialized | |
1437 | * | |
1438 | * Initialize device before it's used by a driver. Ask low-level code | |
1439 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1440 | * Beware, this function can fail. | |
1441 | * | |
1442 | * Note we don't actually enable the device many times if we call | |
1443 | * this function repeatedly (we just increment the count). | |
1444 | */ | |
1445 | int pci_enable_device(struct pci_dev *dev) | |
1446 | { | |
b4b4fbba | 1447 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1448 | } |
b7fe9434 | 1449 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1450 | |
9ac7849e TH |
1451 | /* |
1452 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1453 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1454 | * there's no need to track it separately. pci_devres is initialized | |
1455 | * when a device is enabled using managed PCI device enable interface. | |
1456 | */ | |
1457 | struct pci_devres { | |
7f375f32 TH |
1458 | unsigned int enabled:1; |
1459 | unsigned int pinned:1; | |
9ac7849e TH |
1460 | unsigned int orig_intx:1; |
1461 | unsigned int restore_intx:1; | |
1462 | u32 region_mask; | |
1463 | }; | |
1464 | ||
1465 | static void pcim_release(struct device *gendev, void *res) | |
1466 | { | |
f3d2f165 | 1467 | struct pci_dev *dev = to_pci_dev(gendev); |
9ac7849e TH |
1468 | struct pci_devres *this = res; |
1469 | int i; | |
1470 | ||
1471 | if (dev->msi_enabled) | |
1472 | pci_disable_msi(dev); | |
1473 | if (dev->msix_enabled) | |
1474 | pci_disable_msix(dev); | |
1475 | ||
1476 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1477 | if (this->region_mask & (1 << i)) | |
1478 | pci_release_region(dev, i); | |
1479 | ||
1480 | if (this->restore_intx) | |
1481 | pci_intx(dev, this->orig_intx); | |
1482 | ||
7f375f32 | 1483 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1484 | pci_disable_device(dev); |
1485 | } | |
1486 | ||
07656d83 | 1487 | static struct pci_devres *get_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1488 | { |
1489 | struct pci_devres *dr, *new_dr; | |
1490 | ||
1491 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1492 | if (dr) | |
1493 | return dr; | |
1494 | ||
1495 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1496 | if (!new_dr) | |
1497 | return NULL; | |
1498 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1499 | } | |
1500 | ||
07656d83 | 1501 | static struct pci_devres *find_pci_dr(struct pci_dev *pdev) |
9ac7849e TH |
1502 | { |
1503 | if (pci_is_managed(pdev)) | |
1504 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1505 | return NULL; | |
1506 | } | |
1507 | ||
1508 | /** | |
1509 | * pcim_enable_device - Managed pci_enable_device() | |
1510 | * @pdev: PCI device to be initialized | |
1511 | * | |
1512 | * Managed pci_enable_device(). | |
1513 | */ | |
1514 | int pcim_enable_device(struct pci_dev *pdev) | |
1515 | { | |
1516 | struct pci_devres *dr; | |
1517 | int rc; | |
1518 | ||
1519 | dr = get_pci_dr(pdev); | |
1520 | if (unlikely(!dr)) | |
1521 | return -ENOMEM; | |
b95d58ea TH |
1522 | if (dr->enabled) |
1523 | return 0; | |
9ac7849e TH |
1524 | |
1525 | rc = pci_enable_device(pdev); | |
1526 | if (!rc) { | |
1527 | pdev->is_managed = 1; | |
7f375f32 | 1528 | dr->enabled = 1; |
9ac7849e TH |
1529 | } |
1530 | return rc; | |
1531 | } | |
b7fe9434 | 1532 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1533 | |
1534 | /** | |
1535 | * pcim_pin_device - Pin managed PCI device | |
1536 | * @pdev: PCI device to pin | |
1537 | * | |
1538 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1539 | * driver detach. @pdev must have been enabled with | |
1540 | * pcim_enable_device(). | |
1541 | */ | |
1542 | void pcim_pin_device(struct pci_dev *pdev) | |
1543 | { | |
1544 | struct pci_devres *dr; | |
1545 | ||
1546 | dr = find_pci_dr(pdev); | |
7f375f32 | 1547 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1548 | if (dr) |
7f375f32 | 1549 | dr->pinned = 1; |
9ac7849e | 1550 | } |
b7fe9434 | 1551 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1552 | |
eca0d467 MG |
1553 | /* |
1554 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1555 | * @dev: the PCI device being added | |
1556 | * | |
1557 | * Permits the platform to provide architecture specific functionality when | |
1558 | * devices are added. This is the default implementation. Architecture | |
1559 | * implementations can override this. | |
1560 | */ | |
3c78bc61 | 1561 | int __weak pcibios_add_device(struct pci_dev *dev) |
eca0d467 MG |
1562 | { |
1563 | return 0; | |
1564 | } | |
1565 | ||
6ae32c53 SO |
1566 | /** |
1567 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1568 | * @dev: the PCI device being released | |
1569 | * | |
1570 | * Permits the platform to provide architecture specific functionality when | |
1571 | * devices are released. This is the default implementation. Architecture | |
1572 | * implementations can override this. | |
1573 | */ | |
1574 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1575 | ||
1da177e4 LT |
1576 | /** |
1577 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1578 | * @dev: the PCI device to disable | |
1579 | * | |
1580 | * Disables architecture specific PCI resources for the device. This | |
1581 | * is the default implementation. Architecture implementations can | |
1582 | * override this. | |
1583 | */ | |
ff3ce480 | 1584 | void __weak pcibios_disable_device(struct pci_dev *dev) {} |
1da177e4 | 1585 | |
a43ae58c HG |
1586 | /** |
1587 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1588 | * @irq: ISA IRQ to penalize | |
1589 | * @active: IRQ active or not | |
1590 | * | |
1591 | * Permits the platform to provide architecture-specific functionality when | |
1592 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1593 | * implementations can override this. | |
1594 | */ | |
1595 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1596 | ||
fa58d305 RW |
1597 | static void do_pci_disable_device(struct pci_dev *dev) |
1598 | { | |
1599 | u16 pci_command; | |
1600 | ||
1601 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1602 | if (pci_command & PCI_COMMAND_MASTER) { | |
1603 | pci_command &= ~PCI_COMMAND_MASTER; | |
1604 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1605 | } | |
1606 | ||
1607 | pcibios_disable_device(dev); | |
1608 | } | |
1609 | ||
1610 | /** | |
1611 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1612 | * @dev: PCI device to disable | |
1613 | * | |
1614 | * NOTE: This function is a backend of PCI power management routines and is | |
1615 | * not supposed to be called drivers. | |
1616 | */ | |
1617 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1618 | { | |
296ccb08 | 1619 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1620 | do_pci_disable_device(dev); |
1621 | } | |
1622 | ||
1da177e4 LT |
1623 | /** |
1624 | * pci_disable_device - Disable PCI device after use | |
1625 | * @dev: PCI device to be disabled | |
1626 | * | |
1627 | * Signal to the system that the PCI device is not in use by the system | |
1628 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1629 | * |
1630 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1631 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 | 1632 | */ |
3c78bc61 | 1633 | void pci_disable_device(struct pci_dev *dev) |
1da177e4 | 1634 | { |
9ac7849e | 1635 | struct pci_devres *dr; |
99dc804d | 1636 | |
9ac7849e TH |
1637 | dr = find_pci_dr(dev); |
1638 | if (dr) | |
7f375f32 | 1639 | dr->enabled = 0; |
9ac7849e | 1640 | |
fd6dceab KK |
1641 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1642 | "disabling already-disabled device"); | |
1643 | ||
cc7ba39b | 1644 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1645 | return; |
1646 | ||
fa58d305 | 1647 | do_pci_disable_device(dev); |
1da177e4 | 1648 | |
fa58d305 | 1649 | dev->is_busmaster = 0; |
1da177e4 | 1650 | } |
b7fe9434 | 1651 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1652 | |
f7bdd12d BK |
1653 | /** |
1654 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1655 | * @dev: the PCIe device reset |
f7bdd12d BK |
1656 | * @state: Reset state to enter into |
1657 | * | |
1658 | * | |
45e829ea | 1659 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1660 | * implementation. Architecture implementations can override this. |
1661 | */ | |
d6d88c83 BH |
1662 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1663 | enum pcie_reset_state state) | |
f7bdd12d BK |
1664 | { |
1665 | return -EINVAL; | |
1666 | } | |
1667 | ||
1668 | /** | |
1669 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1670 | * @dev: the PCIe device reset |
f7bdd12d BK |
1671 | * @state: Reset state to enter into |
1672 | * | |
1673 | * | |
1674 | * Sets the PCI reset state for the device. | |
1675 | */ | |
1676 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1677 | { | |
1678 | return pcibios_set_pcie_reset_state(dev, state); | |
1679 | } | |
b7fe9434 | 1680 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 1681 | |
58ff4633 RW |
1682 | /** |
1683 | * pci_check_pme_status - Check if given device has generated PME. | |
1684 | * @dev: Device to check. | |
1685 | * | |
1686 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1687 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1688 | * 'false' otherwise. | |
1689 | */ | |
1690 | bool pci_check_pme_status(struct pci_dev *dev) | |
1691 | { | |
1692 | int pmcsr_pos; | |
1693 | u16 pmcsr; | |
1694 | bool ret = false; | |
1695 | ||
1696 | if (!dev->pm_cap) | |
1697 | return false; | |
1698 | ||
1699 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1700 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1701 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1702 | return false; | |
1703 | ||
1704 | /* Clear PME status. */ | |
1705 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1706 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1707 | /* Disable PME to avoid interrupt flood. */ | |
1708 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1709 | ret = true; | |
1710 | } | |
1711 | ||
1712 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1713 | ||
1714 | return ret; | |
1715 | } | |
1716 | ||
b67ea761 RW |
1717 | /** |
1718 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1719 | * @dev: Device to handle. | |
379021d5 | 1720 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1721 | * |
1722 | * Check if @dev has generated PME and queue a resume request for it in that | |
1723 | * case. | |
1724 | */ | |
379021d5 | 1725 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1726 | { |
379021d5 RW |
1727 | if (pme_poll_reset && dev->pme_poll) |
1728 | dev->pme_poll = false; | |
1729 | ||
c125e96f | 1730 | if (pci_check_pme_status(dev)) { |
c125e96f | 1731 | pci_wakeup_event(dev); |
0f953bf6 | 1732 | pm_request_resume(&dev->dev); |
c125e96f | 1733 | } |
b67ea761 RW |
1734 | return 0; |
1735 | } | |
1736 | ||
1737 | /** | |
1738 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1739 | * @bus: Top bus of the subtree to walk. | |
1740 | */ | |
1741 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1742 | { | |
1743 | if (bus) | |
379021d5 | 1744 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1745 | } |
1746 | ||
448bd857 | 1747 | |
eb9d0fe4 RW |
1748 | /** |
1749 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1750 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1751 | * @state: PCI state from which device will issue PME#. |
1752 | */ | |
e5899e1b | 1753 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1754 | { |
337001b6 | 1755 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1756 | return false; |
1757 | ||
337001b6 | 1758 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 1759 | } |
b7fe9434 | 1760 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 1761 | |
df17e62e MG |
1762 | static void pci_pme_list_scan(struct work_struct *work) |
1763 | { | |
379021d5 | 1764 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1765 | |
1766 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
1767 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1768 | if (pme_dev->dev->pme_poll) { | |
1769 | struct pci_dev *bridge; | |
1770 | ||
1771 | bridge = pme_dev->dev->bus->self; | |
1772 | /* | |
1773 | * If bridge is in low power state, the | |
1774 | * configuration space of subordinate devices | |
1775 | * may be not accessible | |
1776 | */ | |
1777 | if (bridge && bridge->current_state != PCI_D0) | |
1778 | continue; | |
1779 | pci_pme_wakeup(pme_dev->dev, NULL); | |
1780 | } else { | |
1781 | list_del(&pme_dev->list); | |
1782 | kfree(pme_dev); | |
379021d5 | 1783 | } |
df17e62e | 1784 | } |
ce300008 | 1785 | if (!list_empty(&pci_pme_list)) |
ea00353f LW |
1786 | queue_delayed_work(system_freezable_wq, &pci_pme_work, |
1787 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1788 | mutex_unlock(&pci_pme_list_mutex); |
1789 | } | |
1790 | ||
2cef548a | 1791 | static void __pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1792 | { |
1793 | u16 pmcsr; | |
1794 | ||
ffaddbe8 | 1795 | if (!dev->pme_support) |
eb9d0fe4 RW |
1796 | return; |
1797 | ||
337001b6 | 1798 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1799 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1800 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1801 | if (!enable) | |
1802 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1803 | ||
337001b6 | 1804 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
2cef548a RW |
1805 | } |
1806 | ||
0ce3fcaf RW |
1807 | /** |
1808 | * pci_pme_restore - Restore PME configuration after config space restore. | |
1809 | * @dev: PCI device to update. | |
1810 | */ | |
1811 | void pci_pme_restore(struct pci_dev *dev) | |
dc15e71e RW |
1812 | { |
1813 | u16 pmcsr; | |
1814 | ||
1815 | if (!dev->pme_support) | |
1816 | return; | |
1817 | ||
1818 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1819 | if (dev->wakeup_prepared) { | |
1820 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | |
0ce3fcaf | 1821 | pmcsr &= ~PCI_PM_CTRL_PME_STATUS; |
dc15e71e RW |
1822 | } else { |
1823 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1824 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1825 | } | |
1826 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); | |
1827 | } | |
1828 | ||
2cef548a RW |
1829 | /** |
1830 | * pci_pme_active - enable or disable PCI device's PME# function | |
1831 | * @dev: PCI device to handle. | |
1832 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
1833 | * | |
1834 | * The caller must verify that the device is capable of generating PME# before | |
1835 | * calling this function with @enable equal to 'true'. | |
1836 | */ | |
1837 | void pci_pme_active(struct pci_dev *dev, bool enable) | |
1838 | { | |
1839 | __pci_pme_active(dev, enable); | |
eb9d0fe4 | 1840 | |
6e965e0d HY |
1841 | /* |
1842 | * PCI (as opposed to PCIe) PME requires that the device have | |
1843 | * its PME# line hooked up correctly. Not all hardware vendors | |
1844 | * do this, so the PME never gets delivered and the device | |
1845 | * remains asleep. The easiest way around this is to | |
1846 | * periodically walk the list of suspended devices and check | |
1847 | * whether any have their PME flag set. The assumption is that | |
1848 | * we'll wake up often enough anyway that this won't be a huge | |
1849 | * hit, and the power savings from the devices will still be a | |
1850 | * win. | |
1851 | * | |
1852 | * Although PCIe uses in-band PME message instead of PME# line | |
1853 | * to report PME, PME does not work for some PCIe devices in | |
1854 | * reality. For example, there are devices that set their PME | |
1855 | * status bits, but don't really bother to send a PME message; | |
1856 | * there are PCI Express Root Ports that don't bother to | |
1857 | * trigger interrupts when they receive PME messages from the | |
1858 | * devices below. So PME poll is used for PCIe devices too. | |
1859 | */ | |
df17e62e | 1860 | |
379021d5 | 1861 | if (dev->pme_poll) { |
df17e62e MG |
1862 | struct pci_pme_device *pme_dev; |
1863 | if (enable) { | |
1864 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1865 | GFP_KERNEL); | |
0394cb19 BH |
1866 | if (!pme_dev) { |
1867 | dev_warn(&dev->dev, "can't enable PME#\n"); | |
1868 | return; | |
1869 | } | |
df17e62e MG |
1870 | pme_dev->dev = dev; |
1871 | mutex_lock(&pci_pme_list_mutex); | |
1872 | list_add(&pme_dev->list, &pci_pme_list); | |
1873 | if (list_is_singular(&pci_pme_list)) | |
ea00353f LW |
1874 | queue_delayed_work(system_freezable_wq, |
1875 | &pci_pme_work, | |
1876 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1877 | mutex_unlock(&pci_pme_list_mutex); |
1878 | } else { | |
1879 | mutex_lock(&pci_pme_list_mutex); | |
1880 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1881 | if (pme_dev->dev == dev) { | |
1882 | list_del(&pme_dev->list); | |
1883 | kfree(pme_dev); | |
1884 | break; | |
1885 | } | |
1886 | } | |
1887 | mutex_unlock(&pci_pme_list_mutex); | |
1888 | } | |
1889 | } | |
1890 | ||
85b8582d | 1891 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 1892 | } |
b7fe9434 | 1893 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 1894 | |
1da177e4 | 1895 | /** |
0847684c | 1896 | * pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1897 | * @dev: PCI device affected |
1898 | * @state: PCI state from which device will issue wakeup events | |
1899 | * @enable: True to enable event generation; false to disable | |
1900 | * | |
1901 | * This enables the device as a wakeup event source, or disables it. | |
1902 | * When such events involves platform-specific hooks, those hooks are | |
1903 | * called automatically by this routine. | |
1904 | * | |
1905 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1906 | * always require such platform hooks. |
075c1771 | 1907 | * |
eb9d0fe4 RW |
1908 | * RETURN VALUE: |
1909 | * 0 is returned on success | |
1910 | * -EINVAL is returned if device is not supposed to wake up the system | |
1911 | * Error code depending on the platform is returned if both the platform and | |
1912 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1913 | */ |
0847684c | 1914 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) |
1da177e4 | 1915 | { |
5bcc2fb4 | 1916 | int ret = 0; |
075c1771 | 1917 | |
baecc470 RW |
1918 | /* |
1919 | * Bridges can only signal wakeup on behalf of subordinate devices, | |
1920 | * but that is set up elsewhere, so skip them. | |
1921 | */ | |
1922 | if (pci_has_subordinate(dev)) | |
1923 | return 0; | |
1924 | ||
0ce3fcaf RW |
1925 | /* Don't do the same thing twice in a row for one device. */ |
1926 | if (!!enable == !!dev->wakeup_prepared) | |
e80bb09d RW |
1927 | return 0; |
1928 | ||
eb9d0fe4 RW |
1929 | /* |
1930 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1931 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1932 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1933 | */ |
1da177e4 | 1934 | |
5bcc2fb4 RW |
1935 | if (enable) { |
1936 | int error; | |
1da177e4 | 1937 | |
5bcc2fb4 RW |
1938 | if (pci_pme_capable(dev, state)) |
1939 | pci_pme_active(dev, true); | |
1940 | else | |
1941 | ret = 1; | |
0847684c | 1942 | error = platform_pci_set_wakeup(dev, true); |
5bcc2fb4 RW |
1943 | if (ret) |
1944 | ret = error; | |
e80bb09d RW |
1945 | if (!ret) |
1946 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1947 | } else { |
0847684c | 1948 | platform_pci_set_wakeup(dev, false); |
5bcc2fb4 | 1949 | pci_pme_active(dev, false); |
e80bb09d | 1950 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1951 | } |
1da177e4 | 1952 | |
5bcc2fb4 | 1953 | return ret; |
eb9d0fe4 | 1954 | } |
0847684c | 1955 | EXPORT_SYMBOL(pci_enable_wake); |
1da177e4 | 1956 | |
0235c4fc RW |
1957 | /** |
1958 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1959 | * @dev: PCI device to prepare | |
1960 | * @enable: True to enable wake-up event generation; false to disable | |
1961 | * | |
1962 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1963 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1964 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1965 | * ordering constraints. | |
1966 | * | |
1967 | * This function only returns error code if the device is not capable of | |
1968 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1969 | * enable wake-up power for it. | |
1970 | */ | |
1971 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1972 | { | |
1973 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1974 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1975 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1976 | } | |
b7fe9434 | 1977 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 1978 | |
404cc2d8 | 1979 | /** |
37139074 JB |
1980 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1981 | * @dev: PCI device | |
666ff6f8 | 1982 | * @wakeup: Whether or not wakeup functionality will be enabled for the device. |
37139074 JB |
1983 | * |
1984 | * Use underlying platform code to find a supported low power state for @dev. | |
1985 | * If the platform can't manage @dev, return the deepest state from which it | |
1986 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1987 | */ |
666ff6f8 | 1988 | static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup) |
404cc2d8 RW |
1989 | { |
1990 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1991 | |
1992 | if (platform_pci_power_manageable(dev)) { | |
1993 | /* | |
1994 | * Call the platform to choose the target state of the device | |
1995 | * and enable wake-up from this state if supported. | |
1996 | */ | |
1997 | pci_power_t state = platform_pci_choose_state(dev); | |
1998 | ||
1999 | switch (state) { | |
2000 | case PCI_POWER_ERROR: | |
2001 | case PCI_UNKNOWN: | |
2002 | break; | |
2003 | case PCI_D1: | |
2004 | case PCI_D2: | |
2005 | if (pci_no_d1d2(dev)) | |
2006 | break; | |
2007 | default: | |
2008 | target_state = state; | |
404cc2d8 | 2009 | } |
4132a577 LW |
2010 | |
2011 | return target_state; | |
2012 | } | |
2013 | ||
2014 | if (!dev->pm_cap) | |
d2abdf62 | 2015 | target_state = PCI_D0; |
4132a577 LW |
2016 | |
2017 | /* | |
2018 | * If the device is in D3cold even though it's not power-manageable by | |
2019 | * the platform, it may have been powered down by non-standard means. | |
2020 | * Best to let it slumber. | |
2021 | */ | |
2022 | if (dev->current_state == PCI_D3cold) | |
2023 | target_state = PCI_D3cold; | |
2024 | ||
666ff6f8 | 2025 | if (wakeup) { |
404cc2d8 RW |
2026 | /* |
2027 | * Find the deepest state from which the device can generate | |
2028 | * wake-up events, make it the target state and enable device | |
2029 | * to generate PME#. | |
2030 | */ | |
337001b6 RW |
2031 | if (dev->pme_support) { |
2032 | while (target_state | |
2033 | && !(dev->pme_support & (1 << target_state))) | |
2034 | target_state--; | |
404cc2d8 RW |
2035 | } |
2036 | } | |
2037 | ||
e5899e1b RW |
2038 | return target_state; |
2039 | } | |
2040 | ||
2041 | /** | |
2042 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
2043 | * @dev: Device to handle. | |
2044 | * | |
2045 | * Choose the power state appropriate for the device depending on whether | |
2046 | * it can wake up the system and/or is power manageable by the platform | |
2047 | * (PCI_D3hot is the default) and put the device into that state. | |
2048 | */ | |
2049 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
2050 | { | |
666ff6f8 RW |
2051 | bool wakeup = device_may_wakeup(&dev->dev); |
2052 | pci_power_t target_state = pci_target_state(dev, wakeup); | |
e5899e1b RW |
2053 | int error; |
2054 | ||
2055 | if (target_state == PCI_POWER_ERROR) | |
2056 | return -EIO; | |
2057 | ||
666ff6f8 | 2058 | pci_enable_wake(dev, target_state, wakeup); |
c157dfa3 | 2059 | |
404cc2d8 RW |
2060 | error = pci_set_power_state(dev, target_state); |
2061 | ||
2062 | if (error) | |
2063 | pci_enable_wake(dev, target_state, false); | |
2064 | ||
2065 | return error; | |
2066 | } | |
b7fe9434 | 2067 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
2068 | |
2069 | /** | |
443bd1c4 | 2070 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
2071 | * @dev: Device to handle. |
2072 | * | |
88393161 | 2073 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
2074 | */ |
2075 | int pci_back_from_sleep(struct pci_dev *dev) | |
2076 | { | |
2077 | pci_enable_wake(dev, PCI_D0, false); | |
2078 | return pci_set_power_state(dev, PCI_D0); | |
2079 | } | |
b7fe9434 | 2080 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 2081 | |
6cbf8214 RW |
2082 | /** |
2083 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
2084 | * @dev: PCI device being suspended. | |
2085 | * | |
2086 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
2087 | * power state. | |
2088 | */ | |
2089 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
2090 | { | |
666ff6f8 | 2091 | pci_power_t target_state; |
6cbf8214 RW |
2092 | int error; |
2093 | ||
666ff6f8 | 2094 | target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); |
6cbf8214 RW |
2095 | if (target_state == PCI_POWER_ERROR) |
2096 | return -EIO; | |
2097 | ||
448bd857 HY |
2098 | dev->runtime_d3cold = target_state == PCI_D3cold; |
2099 | ||
0847684c | 2100 | pci_enable_wake(dev, target_state, pci_dev_run_wake(dev)); |
6cbf8214 RW |
2101 | |
2102 | error = pci_set_power_state(dev, target_state); | |
2103 | ||
448bd857 | 2104 | if (error) { |
0847684c | 2105 | pci_enable_wake(dev, target_state, false); |
448bd857 HY |
2106 | dev->runtime_d3cold = false; |
2107 | } | |
6cbf8214 RW |
2108 | |
2109 | return error; | |
2110 | } | |
2111 | ||
b67ea761 RW |
2112 | /** |
2113 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
2114 | * @dev: Device to check. | |
2115 | * | |
f7625980 | 2116 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
2117 | * (through the platform or using the native PCIe PME) or if the device supports |
2118 | * PME and one of its upstream bridges can generate wake-up events. | |
2119 | */ | |
2120 | bool pci_dev_run_wake(struct pci_dev *dev) | |
2121 | { | |
2122 | struct pci_bus *bus = dev->bus; | |
2123 | ||
de3ef1eb | 2124 | if (device_can_wakeup(&dev->dev)) |
b67ea761 RW |
2125 | return true; |
2126 | ||
2127 | if (!dev->pme_support) | |
2128 | return false; | |
2129 | ||
666ff6f8 RW |
2130 | /* PME-capable in principle, but not from the target power state */ |
2131 | if (!pci_pme_capable(dev, pci_target_state(dev, false))) | |
6496ebd7 AS |
2132 | return false; |
2133 | ||
b67ea761 RW |
2134 | while (bus->parent) { |
2135 | struct pci_dev *bridge = bus->self; | |
2136 | ||
de3ef1eb | 2137 | if (device_can_wakeup(&bridge->dev)) |
b67ea761 RW |
2138 | return true; |
2139 | ||
2140 | bus = bus->parent; | |
2141 | } | |
2142 | ||
2143 | /* We have reached the root bus. */ | |
2144 | if (bus->bridge) | |
de3ef1eb | 2145 | return device_can_wakeup(bus->bridge); |
b67ea761 RW |
2146 | |
2147 | return false; | |
2148 | } | |
2149 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2150 | ||
bac2a909 RW |
2151 | /** |
2152 | * pci_dev_keep_suspended - Check if the device can stay in the suspended state. | |
2153 | * @pci_dev: Device to check. | |
2154 | * | |
2155 | * Return 'true' if the device is runtime-suspended, it doesn't have to be | |
2156 | * reconfigured due to wakeup settings difference between system and runtime | |
2157 | * suspend and the current power state of it is suitable for the upcoming | |
2158 | * (system) transition. | |
2cef548a RW |
2159 | * |
2160 | * If the device is not configured for system wakeup, disable PME for it before | |
2161 | * returning 'true' to prevent it from waking up the system unnecessarily. | |
bac2a909 RW |
2162 | */ |
2163 | bool pci_dev_keep_suspended(struct pci_dev *pci_dev) | |
2164 | { | |
2165 | struct device *dev = &pci_dev->dev; | |
666ff6f8 | 2166 | bool wakeup = device_may_wakeup(dev); |
bac2a909 RW |
2167 | |
2168 | if (!pm_runtime_suspended(dev) | |
666ff6f8 | 2169 | || pci_target_state(pci_dev, wakeup) != pci_dev->current_state |
c2eac4d3 | 2170 | || platform_pci_need_resume(pci_dev)) |
bac2a909 RW |
2171 | return false; |
2172 | ||
2cef548a RW |
2173 | /* |
2174 | * At this point the device is good to go unless it's been configured | |
2175 | * to generate PME at the runtime suspend time, but it is not supposed | |
2176 | * to wake up the system. In that case, simply disable PME for it | |
2177 | * (it will have to be re-enabled on exit from system resume). | |
2178 | * | |
2179 | * If the device's power state is D3cold and the platform check above | |
2180 | * hasn't triggered, the device's configuration is suitable and we don't | |
2181 | * need to manipulate it at all. | |
2182 | */ | |
2183 | spin_lock_irq(&dev->power.lock); | |
2184 | ||
2185 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold && | |
666ff6f8 | 2186 | !wakeup) |
2cef548a RW |
2187 | __pci_pme_active(pci_dev, false); |
2188 | ||
2189 | spin_unlock_irq(&dev->power.lock); | |
2190 | return true; | |
2191 | } | |
2192 | ||
2193 | /** | |
2194 | * pci_dev_complete_resume - Finalize resume from system sleep for a device. | |
2195 | * @pci_dev: Device to handle. | |
2196 | * | |
2197 | * If the device is runtime suspended and wakeup-capable, enable PME for it as | |
2198 | * it might have been disabled during the prepare phase of system suspend if | |
2199 | * the device was not configured for system wakeup. | |
2200 | */ | |
2201 | void pci_dev_complete_resume(struct pci_dev *pci_dev) | |
2202 | { | |
2203 | struct device *dev = &pci_dev->dev; | |
2204 | ||
2205 | if (!pci_dev_run_wake(pci_dev)) | |
2206 | return; | |
2207 | ||
2208 | spin_lock_irq(&dev->power.lock); | |
2209 | ||
2210 | if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) | |
2211 | __pci_pme_active(pci_dev, true); | |
2212 | ||
2213 | spin_unlock_irq(&dev->power.lock); | |
bac2a909 RW |
2214 | } |
2215 | ||
b3c32c4f HY |
2216 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2217 | { | |
2218 | struct device *dev = &pdev->dev; | |
2219 | struct device *parent = dev->parent; | |
2220 | ||
2221 | if (parent) | |
2222 | pm_runtime_get_sync(parent); | |
2223 | pm_runtime_get_noresume(dev); | |
2224 | /* | |
2225 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2226 | * so wait until suspending completes | |
2227 | */ | |
2228 | pm_runtime_barrier(dev); | |
2229 | /* | |
2230 | * Only need to resume devices in D3cold, because config | |
2231 | * registers are still accessible for devices suspended but | |
2232 | * not in D3cold. | |
2233 | */ | |
2234 | if (pdev->current_state == PCI_D3cold) | |
2235 | pm_runtime_resume(dev); | |
2236 | } | |
2237 | ||
2238 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2239 | { | |
2240 | struct device *dev = &pdev->dev; | |
2241 | struct device *parent = dev->parent; | |
2242 | ||
2243 | pm_runtime_put(dev); | |
2244 | if (parent) | |
2245 | pm_runtime_put_sync(parent); | |
2246 | } | |
2247 | ||
9d26d3a8 MW |
2248 | /** |
2249 | * pci_bridge_d3_possible - Is it possible to put the bridge into D3 | |
2250 | * @bridge: Bridge to check | |
2251 | * | |
2252 | * This function checks if it is possible to move the bridge to D3. | |
2253 | * Currently we only allow D3 for recent enough PCIe ports. | |
2254 | */ | |
c6a63307 | 2255 | bool pci_bridge_d3_possible(struct pci_dev *bridge) |
9d26d3a8 MW |
2256 | { |
2257 | unsigned int year; | |
2258 | ||
2259 | if (!pci_is_pcie(bridge)) | |
2260 | return false; | |
2261 | ||
2262 | switch (pci_pcie_type(bridge)) { | |
2263 | case PCI_EXP_TYPE_ROOT_PORT: | |
2264 | case PCI_EXP_TYPE_UPSTREAM: | |
2265 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2266 | if (pci_bridge_d3_disable) | |
2267 | return false; | |
97a90aee LW |
2268 | |
2269 | /* | |
d98e0929 BH |
2270 | * Hotplug interrupts cannot be delivered if the link is down, |
2271 | * so parents of a hotplug port must stay awake. In addition, | |
2272 | * hotplug ports handled by firmware in System Management Mode | |
97a90aee | 2273 | * may not be put into D3 by the OS (Thunderbolt on non-Macs). |
d98e0929 | 2274 | * For simplicity, disallow in general for now. |
97a90aee | 2275 | */ |
d98e0929 | 2276 | if (bridge->is_hotplug_bridge) |
97a90aee LW |
2277 | return false; |
2278 | ||
9d26d3a8 MW |
2279 | if (pci_bridge_d3_force) |
2280 | return true; | |
2281 | ||
2282 | /* | |
2283 | * It should be safe to put PCIe ports from 2015 or newer | |
2284 | * to D3. | |
2285 | */ | |
2286 | if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && | |
2287 | year >= 2015) { | |
2288 | return true; | |
2289 | } | |
2290 | break; | |
2291 | } | |
2292 | ||
2293 | return false; | |
2294 | } | |
2295 | ||
2296 | static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) | |
2297 | { | |
2298 | bool *d3cold_ok = data; | |
9d26d3a8 | 2299 | |
718a0609 LW |
2300 | if (/* The device needs to be allowed to go D3cold ... */ |
2301 | dev->no_d3cold || !dev->d3cold_allowed || | |
2302 | ||
2303 | /* ... and if it is wakeup capable to do so from D3cold. */ | |
2304 | (device_may_wakeup(&dev->dev) && | |
2305 | !pci_pme_capable(dev, PCI_D3cold)) || | |
2306 | ||
2307 | /* If it is a bridge it must be allowed to go to D3. */ | |
d98e0929 | 2308 | !pci_power_manageable(dev)) |
9d26d3a8 | 2309 | |
718a0609 | 2310 | *d3cold_ok = false; |
9d26d3a8 | 2311 | |
718a0609 | 2312 | return !*d3cold_ok; |
9d26d3a8 MW |
2313 | } |
2314 | ||
2315 | /* | |
2316 | * pci_bridge_d3_update - Update bridge D3 capabilities | |
2317 | * @dev: PCI device which is changed | |
9d26d3a8 MW |
2318 | * |
2319 | * Update upstream bridge PM capabilities accordingly depending on if the | |
2320 | * device PM configuration was changed or the device is being removed. The | |
2321 | * change is also propagated upstream. | |
2322 | */ | |
1ed276a7 | 2323 | void pci_bridge_d3_update(struct pci_dev *dev) |
9d26d3a8 | 2324 | { |
1ed276a7 | 2325 | bool remove = !device_is_registered(&dev->dev); |
9d26d3a8 MW |
2326 | struct pci_dev *bridge; |
2327 | bool d3cold_ok = true; | |
2328 | ||
2329 | bridge = pci_upstream_bridge(dev); | |
2330 | if (!bridge || !pci_bridge_d3_possible(bridge)) | |
2331 | return; | |
2332 | ||
9d26d3a8 | 2333 | /* |
e8559b71 LW |
2334 | * If D3 is currently allowed for the bridge, removing one of its |
2335 | * children won't change that. | |
2336 | */ | |
2337 | if (remove && bridge->bridge_d3) | |
2338 | return; | |
2339 | ||
2340 | /* | |
2341 | * If D3 is currently allowed for the bridge and a child is added or | |
2342 | * changed, disallowance of D3 can only be caused by that child, so | |
2343 | * we only need to check that single device, not any of its siblings. | |
2344 | * | |
2345 | * If D3 is currently not allowed for the bridge, checking the device | |
2346 | * first may allow us to skip checking its siblings. | |
9d26d3a8 MW |
2347 | */ |
2348 | if (!remove) | |
2349 | pci_dev_check_d3cold(dev, &d3cold_ok); | |
2350 | ||
e8559b71 LW |
2351 | /* |
2352 | * If D3 is currently not allowed for the bridge, this may be caused | |
2353 | * either by the device being changed/removed or any of its siblings, | |
2354 | * so we need to go through all children to find out if one of them | |
2355 | * continues to block D3. | |
2356 | */ | |
2357 | if (d3cold_ok && !bridge->bridge_d3) | |
9d26d3a8 MW |
2358 | pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, |
2359 | &d3cold_ok); | |
9d26d3a8 MW |
2360 | |
2361 | if (bridge->bridge_d3 != d3cold_ok) { | |
2362 | bridge->bridge_d3 = d3cold_ok; | |
2363 | /* Propagate change to upstream bridges */ | |
1ed276a7 | 2364 | pci_bridge_d3_update(bridge); |
9d26d3a8 | 2365 | } |
9d26d3a8 MW |
2366 | } |
2367 | ||
9d26d3a8 MW |
2368 | /** |
2369 | * pci_d3cold_enable - Enable D3cold for device | |
2370 | * @dev: PCI device to handle | |
2371 | * | |
2372 | * This function can be used in drivers to enable D3cold from the device | |
2373 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2374 | * accordingly. | |
2375 | */ | |
2376 | void pci_d3cold_enable(struct pci_dev *dev) | |
2377 | { | |
2378 | if (dev->no_d3cold) { | |
2379 | dev->no_d3cold = false; | |
1ed276a7 | 2380 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2381 | } |
2382 | } | |
2383 | EXPORT_SYMBOL_GPL(pci_d3cold_enable); | |
2384 | ||
2385 | /** | |
2386 | * pci_d3cold_disable - Disable D3cold for device | |
2387 | * @dev: PCI device to handle | |
2388 | * | |
2389 | * This function can be used in drivers to disable D3cold from the device | |
2390 | * they handle. It also updates upstream PCI bridge PM capabilities | |
2391 | * accordingly. | |
2392 | */ | |
2393 | void pci_d3cold_disable(struct pci_dev *dev) | |
2394 | { | |
2395 | if (!dev->no_d3cold) { | |
2396 | dev->no_d3cold = true; | |
1ed276a7 | 2397 | pci_bridge_d3_update(dev); |
9d26d3a8 MW |
2398 | } |
2399 | } | |
2400 | EXPORT_SYMBOL_GPL(pci_d3cold_disable); | |
2401 | ||
eb9d0fe4 RW |
2402 | /** |
2403 | * pci_pm_init - Initialize PM functions of given PCI device | |
2404 | * @dev: PCI device to handle. | |
2405 | */ | |
2406 | void pci_pm_init(struct pci_dev *dev) | |
2407 | { | |
2408 | int pm; | |
2409 | u16 pmc; | |
1da177e4 | 2410 | |
bb910a70 | 2411 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2412 | pm_runtime_set_active(&dev->dev); |
2413 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2414 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2415 | dev->wakeup_prepared = false; |
bb910a70 | 2416 | |
337001b6 | 2417 | dev->pm_cap = 0; |
ffaddbe8 | 2418 | dev->pme_support = 0; |
337001b6 | 2419 | |
eb9d0fe4 RW |
2420 | /* find PCI PM capability in list */ |
2421 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2422 | if (!pm) | |
50246dd4 | 2423 | return; |
eb9d0fe4 RW |
2424 | /* Check device's ability to generate PME# */ |
2425 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2426 | |
eb9d0fe4 RW |
2427 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
2428 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
2429 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 2430 | return; |
eb9d0fe4 RW |
2431 | } |
2432 | ||
337001b6 | 2433 | dev->pm_cap = pm; |
1ae861e6 | 2434 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2435 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
9d26d3a8 | 2436 | dev->bridge_d3 = pci_bridge_d3_possible(dev); |
4f9c1397 | 2437 | dev->d3cold_allowed = true; |
337001b6 RW |
2438 | |
2439 | dev->d1_support = false; | |
2440 | dev->d2_support = false; | |
2441 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2442 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2443 | dev->d1_support = true; |
c9ed77ee | 2444 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2445 | dev->d2_support = true; |
c9ed77ee BH |
2446 | |
2447 | if (dev->d1_support || dev->d2_support) | |
2448 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
2449 | dev->d1_support ? " D1" : "", |
2450 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2451 | } |
2452 | ||
2453 | pmc &= PCI_PM_CAP_PME_MASK; | |
2454 | if (pmc) { | |
10c3d71d BH |
2455 | dev_printk(KERN_DEBUG, &dev->dev, |
2456 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
2457 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2458 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2459 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2460 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2461 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2462 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2463 | dev->pme_poll = true; |
eb9d0fe4 RW |
2464 | /* |
2465 | * Make device's PM flags reflect the wake-up capability, but | |
2466 | * let the user space enable it to wake up the system as needed. | |
2467 | */ | |
2468 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2469 | /* Disable the PME# generation functionality */ |
337001b6 | 2470 | pci_pme_active(dev, false); |
eb9d0fe4 | 2471 | } |
1da177e4 LT |
2472 | } |
2473 | ||
938174e5 SS |
2474 | static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop) |
2475 | { | |
92efb1bd | 2476 | unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI; |
938174e5 SS |
2477 | |
2478 | switch (prop) { | |
2479 | case PCI_EA_P_MEM: | |
2480 | case PCI_EA_P_VF_MEM: | |
2481 | flags |= IORESOURCE_MEM; | |
2482 | break; | |
2483 | case PCI_EA_P_MEM_PREFETCH: | |
2484 | case PCI_EA_P_VF_MEM_PREFETCH: | |
2485 | flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
2486 | break; | |
2487 | case PCI_EA_P_IO: | |
2488 | flags |= IORESOURCE_IO; | |
2489 | break; | |
2490 | default: | |
2491 | return 0; | |
2492 | } | |
2493 | ||
2494 | return flags; | |
2495 | } | |
2496 | ||
2497 | static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei, | |
2498 | u8 prop) | |
2499 | { | |
2500 | if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO) | |
2501 | return &dev->resource[bei]; | |
11183991 DD |
2502 | #ifdef CONFIG_PCI_IOV |
2503 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 && | |
2504 | (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH)) | |
2505 | return &dev->resource[PCI_IOV_RESOURCES + | |
2506 | bei - PCI_EA_BEI_VF_BAR0]; | |
2507 | #endif | |
938174e5 SS |
2508 | else if (bei == PCI_EA_BEI_ROM) |
2509 | return &dev->resource[PCI_ROM_RESOURCE]; | |
2510 | else | |
2511 | return NULL; | |
2512 | } | |
2513 | ||
2514 | /* Read an Enhanced Allocation (EA) entry */ | |
2515 | static int pci_ea_read(struct pci_dev *dev, int offset) | |
2516 | { | |
2517 | struct resource *res; | |
2518 | int ent_size, ent_offset = offset; | |
2519 | resource_size_t start, end; | |
2520 | unsigned long flags; | |
26635112 | 2521 | u32 dw0, bei, base, max_offset; |
938174e5 SS |
2522 | u8 prop; |
2523 | bool support_64 = (sizeof(resource_size_t) >= 8); | |
2524 | ||
2525 | pci_read_config_dword(dev, ent_offset, &dw0); | |
2526 | ent_offset += 4; | |
2527 | ||
2528 | /* Entry size field indicates DWORDs after 1st */ | |
2529 | ent_size = ((dw0 & PCI_EA_ES) + 1) << 2; | |
2530 | ||
2531 | if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ | |
2532 | goto out; | |
2533 | ||
26635112 BH |
2534 | bei = (dw0 & PCI_EA_BEI) >> 4; |
2535 | prop = (dw0 & PCI_EA_PP) >> 8; | |
2536 | ||
938174e5 SS |
2537 | /* |
2538 | * If the Property is in the reserved range, try the Secondary | |
2539 | * Property instead. | |
2540 | */ | |
2541 | if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED) | |
26635112 | 2542 | prop = (dw0 & PCI_EA_SP) >> 16; |
938174e5 SS |
2543 | if (prop > PCI_EA_P_BRIDGE_IO) |
2544 | goto out; | |
2545 | ||
26635112 | 2546 | res = pci_ea_get_resource(dev, bei, prop); |
938174e5 | 2547 | if (!res) { |
26635112 | 2548 | dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei); |
938174e5 SS |
2549 | goto out; |
2550 | } | |
2551 | ||
2552 | flags = pci_ea_flags(dev, prop); | |
2553 | if (!flags) { | |
2554 | dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop); | |
2555 | goto out; | |
2556 | } | |
2557 | ||
2558 | /* Read Base */ | |
2559 | pci_read_config_dword(dev, ent_offset, &base); | |
2560 | start = (base & PCI_EA_FIELD_MASK); | |
2561 | ent_offset += 4; | |
2562 | ||
2563 | /* Read MaxOffset */ | |
2564 | pci_read_config_dword(dev, ent_offset, &max_offset); | |
2565 | ent_offset += 4; | |
2566 | ||
2567 | /* Read Base MSBs (if 64-bit entry) */ | |
2568 | if (base & PCI_EA_IS_64) { | |
2569 | u32 base_upper; | |
2570 | ||
2571 | pci_read_config_dword(dev, ent_offset, &base_upper); | |
2572 | ent_offset += 4; | |
2573 | ||
2574 | flags |= IORESOURCE_MEM_64; | |
2575 | ||
2576 | /* entry starts above 32-bit boundary, can't use */ | |
2577 | if (!support_64 && base_upper) | |
2578 | goto out; | |
2579 | ||
2580 | if (support_64) | |
2581 | start |= ((u64)base_upper << 32); | |
2582 | } | |
2583 | ||
2584 | end = start + (max_offset | 0x03); | |
2585 | ||
2586 | /* Read MaxOffset MSBs (if 64-bit entry) */ | |
2587 | if (max_offset & PCI_EA_IS_64) { | |
2588 | u32 max_offset_upper; | |
2589 | ||
2590 | pci_read_config_dword(dev, ent_offset, &max_offset_upper); | |
2591 | ent_offset += 4; | |
2592 | ||
2593 | flags |= IORESOURCE_MEM_64; | |
2594 | ||
2595 | /* entry too big, can't use */ | |
2596 | if (!support_64 && max_offset_upper) | |
2597 | goto out; | |
2598 | ||
2599 | if (support_64) | |
2600 | end += ((u64)max_offset_upper << 32); | |
2601 | } | |
2602 | ||
2603 | if (end < start) { | |
2604 | dev_err(&dev->dev, "EA Entry crosses address boundary\n"); | |
2605 | goto out; | |
2606 | } | |
2607 | ||
2608 | if (ent_size != ent_offset - offset) { | |
2609 | dev_err(&dev->dev, | |
2610 | "EA Entry Size (%d) does not match length read (%d)\n", | |
2611 | ent_size, ent_offset - offset); | |
2612 | goto out; | |
2613 | } | |
2614 | ||
2615 | res->name = pci_name(dev); | |
2616 | res->start = start; | |
2617 | res->end = end; | |
2618 | res->flags = flags; | |
597becb4 BH |
2619 | |
2620 | if (bei <= PCI_EA_BEI_BAR5) | |
2621 | dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2622 | bei, res, prop); | |
2623 | else if (bei == PCI_EA_BEI_ROM) | |
2624 | dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2625 | res, prop); | |
2626 | else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5) | |
2627 | dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2628 | bei - PCI_EA_BEI_VF_BAR0, res, prop); | |
2629 | else | |
2630 | dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n", | |
2631 | bei, res, prop); | |
2632 | ||
938174e5 SS |
2633 | out: |
2634 | return offset + ent_size; | |
2635 | } | |
2636 | ||
dcbb408a | 2637 | /* Enhanced Allocation Initialization */ |
938174e5 SS |
2638 | void pci_ea_init(struct pci_dev *dev) |
2639 | { | |
2640 | int ea; | |
2641 | u8 num_ent; | |
2642 | int offset; | |
2643 | int i; | |
2644 | ||
2645 | /* find PCI EA capability in list */ | |
2646 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
2647 | if (!ea) | |
2648 | return; | |
2649 | ||
2650 | /* determine the number of entries */ | |
2651 | pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, | |
2652 | &num_ent); | |
2653 | num_ent &= PCI_EA_NUM_ENT_MASK; | |
2654 | ||
2655 | offset = ea + PCI_EA_FIRST_ENT; | |
2656 | ||
2657 | /* Skip DWORD 2 for type 1 functions */ | |
2658 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
2659 | offset += 4; | |
2660 | ||
2661 | /* parse each EA entry */ | |
2662 | for (i = 0; i < num_ent; ++i) | |
2663 | offset = pci_ea_read(dev, offset); | |
2664 | } | |
2665 | ||
34a4876e YL |
2666 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
2667 | struct pci_cap_saved_state *new_cap) | |
2668 | { | |
2669 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
2670 | } | |
2671 | ||
63f4898a | 2672 | /** |
fd0f7f73 AW |
2673 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
2674 | * capability registers | |
63f4898a RW |
2675 | * @dev: the PCI device |
2676 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 2677 | * @extended: Standard or Extended capability ID |
63f4898a RW |
2678 | * @size: requested size of the buffer |
2679 | */ | |
fd0f7f73 AW |
2680 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
2681 | bool extended, unsigned int size) | |
63f4898a RW |
2682 | { |
2683 | int pos; | |
2684 | struct pci_cap_saved_state *save_state; | |
2685 | ||
fd0f7f73 AW |
2686 | if (extended) |
2687 | pos = pci_find_ext_capability(dev, cap); | |
2688 | else | |
2689 | pos = pci_find_capability(dev, cap); | |
2690 | ||
0a1a9b49 | 2691 | if (!pos) |
63f4898a RW |
2692 | return 0; |
2693 | ||
2694 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2695 | if (!save_state) | |
2696 | return -ENOMEM; | |
2697 | ||
24a4742f | 2698 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 2699 | save_state->cap.cap_extended = extended; |
24a4742f | 2700 | save_state->cap.size = size; |
63f4898a RW |
2701 | pci_add_saved_cap(dev, save_state); |
2702 | ||
2703 | return 0; | |
2704 | } | |
2705 | ||
fd0f7f73 AW |
2706 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
2707 | { | |
2708 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
2709 | } | |
2710 | ||
2711 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
2712 | { | |
2713 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
2714 | } | |
2715 | ||
63f4898a RW |
2716 | /** |
2717 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2718 | * @dev: the PCI device | |
2719 | */ | |
2720 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2721 | { | |
2722 | int error; | |
2723 | ||
89858517 YZ |
2724 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2725 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2726 | if (error) |
2727 | dev_err(&dev->dev, | |
2728 | "unable to preallocate PCI Express save buffer\n"); | |
2729 | ||
2730 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2731 | if (error) | |
2732 | dev_err(&dev->dev, | |
2733 | "unable to preallocate PCI-X save buffer\n"); | |
425c1b22 AW |
2734 | |
2735 | pci_allocate_vc_save_buffers(dev); | |
63f4898a RW |
2736 | } |
2737 | ||
f796841e YL |
2738 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2739 | { | |
2740 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 2741 | struct hlist_node *n; |
f796841e | 2742 | |
b67bfe0d | 2743 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
2744 | kfree(tmp); |
2745 | } | |
2746 | ||
58c3a727 | 2747 | /** |
31ab2476 | 2748 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 2749 | * @dev: the PCI device |
b0cc6020 YW |
2750 | * |
2751 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
2752 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 2753 | */ |
31ab2476 | 2754 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 2755 | { |
58c3a727 | 2756 | u32 cap; |
8113587c | 2757 | struct pci_dev *bridge; |
58c3a727 | 2758 | |
6748dcc2 | 2759 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2760 | return; |
2761 | ||
8113587c | 2762 | bridge = dev->bus->self; |
cb97ae34 | 2763 | if (!bridge) |
8113587c ZY |
2764 | return; |
2765 | ||
59875ae4 | 2766 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2767 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2768 | return; | |
2769 | ||
b0cc6020 YW |
2770 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
2771 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
2772 | PCI_EXP_DEVCTL2_ARI); | |
2773 | bridge->ari_enabled = 1; | |
2774 | } else { | |
2775 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
2776 | PCI_EXP_DEVCTL2_ARI); | |
2777 | bridge->ari_enabled = 0; | |
2778 | } | |
58c3a727 YZ |
2779 | } |
2780 | ||
5d990b62 CW |
2781 | static int pci_acs_enable; |
2782 | ||
2783 | /** | |
2784 | * pci_request_acs - ask for ACS to be enabled if supported | |
2785 | */ | |
2786 | void pci_request_acs(void) | |
2787 | { | |
2788 | pci_acs_enable = 1; | |
2789 | } | |
2790 | ||
ae21ee65 | 2791 | /** |
2c744244 | 2792 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites |
ae21ee65 AK |
2793 | * @dev: the PCI device |
2794 | */ | |
c1d61c9b | 2795 | static void pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
2796 | { |
2797 | int pos; | |
2798 | u16 cap; | |
2799 | u16 ctrl; | |
2800 | ||
ae21ee65 AK |
2801 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2802 | if (!pos) | |
c1d61c9b | 2803 | return; |
ae21ee65 AK |
2804 | |
2805 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2806 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2807 | ||
2808 | /* Source Validation */ | |
2809 | ctrl |= (cap & PCI_ACS_SV); | |
2810 | ||
2811 | /* P2P Request Redirect */ | |
2812 | ctrl |= (cap & PCI_ACS_RR); | |
2813 | ||
2814 | /* P2P Completion Redirect */ | |
2815 | ctrl |= (cap & PCI_ACS_CR); | |
2816 | ||
2817 | /* Upstream Forwarding */ | |
2818 | ctrl |= (cap & PCI_ACS_UF); | |
2819 | ||
2820 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
2821 | } |
2822 | ||
2823 | /** | |
2824 | * pci_enable_acs - enable ACS if hardware support it | |
2825 | * @dev: the PCI device | |
2826 | */ | |
2827 | void pci_enable_acs(struct pci_dev *dev) | |
2828 | { | |
2829 | if (!pci_acs_enable) | |
2830 | return; | |
2831 | ||
c1d61c9b | 2832 | if (!pci_dev_specific_enable_acs(dev)) |
2c744244 AW |
2833 | return; |
2834 | ||
c1d61c9b | 2835 | pci_std_enable_acs(dev); |
ae21ee65 AK |
2836 | } |
2837 | ||
0a67119f AW |
2838 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
2839 | { | |
2840 | int pos; | |
83db7e0b | 2841 | u16 cap, ctrl; |
0a67119f AW |
2842 | |
2843 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2844 | if (!pos) | |
2845 | return false; | |
2846 | ||
83db7e0b AW |
2847 | /* |
2848 | * Except for egress control, capabilities are either required | |
2849 | * or only required if controllable. Features missing from the | |
2850 | * capability field can therefore be assumed as hard-wired enabled. | |
2851 | */ | |
2852 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
2853 | acs_flags &= (cap | PCI_ACS_EC); | |
2854 | ||
0a67119f AW |
2855 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
2856 | return (ctrl & acs_flags) == acs_flags; | |
2857 | } | |
2858 | ||
ad805758 AW |
2859 | /** |
2860 | * pci_acs_enabled - test ACS against required flags for a given device | |
2861 | * @pdev: device to test | |
2862 | * @acs_flags: required PCI ACS flags | |
2863 | * | |
2864 | * Return true if the device supports the provided flags. Automatically | |
2865 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
2866 | * |
2867 | * Note that this interface checks the effective ACS capabilities of the | |
2868 | * device rather than the actual capabilities. For instance, most single | |
2869 | * function endpoints are not required to support ACS because they have no | |
2870 | * opportunity for peer-to-peer access. We therefore return 'true' | |
2871 | * regardless of whether the device exposes an ACS capability. This makes | |
2872 | * it much easier for callers of this function to ignore the actual type | |
2873 | * or topology of the device when testing ACS support. | |
ad805758 AW |
2874 | */ |
2875 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2876 | { | |
0a67119f | 2877 | int ret; |
ad805758 AW |
2878 | |
2879 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2880 | if (ret >= 0) | |
2881 | return ret > 0; | |
2882 | ||
0a67119f AW |
2883 | /* |
2884 | * Conventional PCI and PCI-X devices never support ACS, either | |
2885 | * effectively or actually. The shared bus topology implies that | |
2886 | * any device on the bus can receive or snoop DMA. | |
2887 | */ | |
ad805758 AW |
2888 | if (!pci_is_pcie(pdev)) |
2889 | return false; | |
2890 | ||
0a67119f AW |
2891 | switch (pci_pcie_type(pdev)) { |
2892 | /* | |
2893 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 2894 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
2895 | * handle them as we would a non-PCIe device. |
2896 | */ | |
2897 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
2898 | /* | |
2899 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
2900 | * applicable... must never implement an ACS Extended Capability...". | |
2901 | * This seems arbitrary, but we take a conservative interpretation | |
2902 | * of this statement. | |
2903 | */ | |
2904 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
2905 | case PCI_EXP_TYPE_RC_EC: | |
2906 | return false; | |
2907 | /* | |
2908 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
2909 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
2910 | * regardless of whether they are single- or multi-function devices. | |
2911 | */ | |
2912 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2913 | case PCI_EXP_TYPE_ROOT_PORT: | |
2914 | return pci_acs_flags_enabled(pdev, acs_flags); | |
2915 | /* | |
2916 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
2917 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 2918 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
2919 | * device. The footnote for section 6.12 indicates the specific |
2920 | * PCIe types included here. | |
2921 | */ | |
2922 | case PCI_EXP_TYPE_ENDPOINT: | |
2923 | case PCI_EXP_TYPE_UPSTREAM: | |
2924 | case PCI_EXP_TYPE_LEG_END: | |
2925 | case PCI_EXP_TYPE_RC_END: | |
2926 | if (!pdev->multifunction) | |
2927 | break; | |
2928 | ||
0a67119f | 2929 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
2930 | } |
2931 | ||
0a67119f | 2932 | /* |
f7625980 | 2933 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
2934 | * to single function devices with the exception of downstream ports. |
2935 | */ | |
ad805758 AW |
2936 | return true; |
2937 | } | |
2938 | ||
2939 | /** | |
2940 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2941 | * @start: starting downstream device | |
2942 | * @end: ending upstream device or NULL to search to the root bus | |
2943 | * @acs_flags: required flags | |
2944 | * | |
2945 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2946 | * any step along the way does not support the required flags, return false. | |
2947 | */ | |
2948 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2949 | struct pci_dev *end, u16 acs_flags) | |
2950 | { | |
2951 | struct pci_dev *pdev, *parent = start; | |
2952 | ||
2953 | do { | |
2954 | pdev = parent; | |
2955 | ||
2956 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2957 | return false; | |
2958 | ||
2959 | if (pci_is_root_bus(pdev->bus)) | |
2960 | return (end == NULL); | |
2961 | ||
2962 | parent = pdev->bus->self; | |
2963 | } while (pdev != end); | |
2964 | ||
2965 | return true; | |
2966 | } | |
2967 | ||
276b738d CK |
2968 | /** |
2969 | * pci_rebar_find_pos - find position of resize ctrl reg for BAR | |
2970 | * @pdev: PCI device | |
2971 | * @bar: BAR to find | |
2972 | * | |
2973 | * Helper to find the position of the ctrl register for a BAR. | |
2974 | * Returns -ENOTSUPP if resizable BARs are not supported at all. | |
2975 | * Returns -ENOENT if no ctrl register for the BAR could be found. | |
2976 | */ | |
2977 | static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) | |
2978 | { | |
2979 | unsigned int pos, nbars, i; | |
2980 | u32 ctrl; | |
2981 | ||
2982 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); | |
2983 | if (!pos) | |
2984 | return -ENOTSUPP; | |
2985 | ||
2986 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
2987 | nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> | |
2988 | PCI_REBAR_CTRL_NBAR_SHIFT; | |
2989 | ||
2990 | for (i = 0; i < nbars; i++, pos += 8) { | |
2991 | int bar_idx; | |
2992 | ||
2993 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
2994 | bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; | |
2995 | if (bar_idx == bar) | |
2996 | return pos; | |
2997 | } | |
2998 | ||
2999 | return -ENOENT; | |
3000 | } | |
3001 | ||
3002 | /** | |
3003 | * pci_rebar_get_possible_sizes - get possible sizes for BAR | |
3004 | * @pdev: PCI device | |
3005 | * @bar: BAR to query | |
3006 | * | |
3007 | * Get the possible sizes of a resizable BAR as bitmask defined in the spec | |
3008 | * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable. | |
3009 | */ | |
3010 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) | |
3011 | { | |
3012 | int pos; | |
3013 | u32 cap; | |
3014 | ||
3015 | pos = pci_rebar_find_pos(pdev, bar); | |
3016 | if (pos < 0) | |
3017 | return 0; | |
3018 | ||
3019 | pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); | |
3020 | return (cap & PCI_REBAR_CAP_SIZES) >> 4; | |
3021 | } | |
3022 | ||
3023 | /** | |
3024 | * pci_rebar_get_current_size - get the current size of a BAR | |
3025 | * @pdev: PCI device | |
3026 | * @bar: BAR to set size to | |
3027 | * | |
3028 | * Read the size of a BAR from the resizable BAR config. | |
3029 | * Returns size if found or negative error code. | |
3030 | */ | |
3031 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) | |
3032 | { | |
3033 | int pos; | |
3034 | u32 ctrl; | |
3035 | ||
3036 | pos = pci_rebar_find_pos(pdev, bar); | |
3037 | if (pos < 0) | |
3038 | return pos; | |
3039 | ||
3040 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3041 | return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8; | |
3042 | } | |
3043 | ||
3044 | /** | |
3045 | * pci_rebar_set_size - set a new size for a BAR | |
3046 | * @pdev: PCI device | |
3047 | * @bar: BAR to set size to | |
3048 | * @size: new size as defined in the spec (0=1MB, 19=512GB) | |
3049 | * | |
3050 | * Set the new size of a BAR as defined in the spec. | |
3051 | * Returns zero if resizing was successful, error code otherwise. | |
3052 | */ | |
3053 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) | |
3054 | { | |
3055 | int pos; | |
3056 | u32 ctrl; | |
3057 | ||
3058 | pos = pci_rebar_find_pos(pdev, bar); | |
3059 | if (pos < 0) | |
3060 | return pos; | |
3061 | ||
3062 | pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); | |
3063 | ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; | |
3064 | ctrl |= size << 8; | |
3065 | pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); | |
3066 | return 0; | |
3067 | } | |
3068 | ||
57c2cf71 BH |
3069 | /** |
3070 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
3071 | * @dev: the PCI device | |
bb5c2de2 | 3072 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
3073 | * |
3074 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
3075 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
3076 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
3077 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
3078 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 3079 | */ |
3df425f3 | 3080 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 3081 | { |
46b952a3 MW |
3082 | int slot; |
3083 | ||
3084 | if (pci_ari_enabled(dev->bus)) | |
3085 | slot = 0; | |
3086 | else | |
3087 | slot = PCI_SLOT(dev->devfn); | |
3088 | ||
3089 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
3090 | } |
3091 | ||
3c78bc61 | 3092 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
1da177e4 LT |
3093 | { |
3094 | u8 pin; | |
3095 | ||
514d207d | 3096 | pin = dev->pin; |
1da177e4 LT |
3097 | if (!pin) |
3098 | return -1; | |
878f2e50 | 3099 | |
8784fd4d | 3100 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 3101 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
3102 | dev = dev->bus->self; |
3103 | } | |
3104 | *bridge = dev; | |
3105 | return pin; | |
3106 | } | |
3107 | ||
68feac87 BH |
3108 | /** |
3109 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
3110 | * @dev: the PCI device | |
3111 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
3112 | * | |
3113 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
3114 | * bridges all the way up to a PCI root bus. | |
3115 | */ | |
3116 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
3117 | { | |
3118 | u8 pin = *pinp; | |
3119 | ||
1eb39487 | 3120 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
3121 | pin = pci_swizzle_interrupt_pin(dev, pin); |
3122 | dev = dev->bus->self; | |
3123 | } | |
3124 | *pinp = pin; | |
3125 | return PCI_SLOT(dev->devfn); | |
3126 | } | |
e6b29dea | 3127 | EXPORT_SYMBOL_GPL(pci_common_swizzle); |
68feac87 | 3128 | |
1da177e4 LT |
3129 | /** |
3130 | * pci_release_region - Release a PCI bar | |
3131 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
3132 | * @bar: BAR to release | |
3133 | * | |
3134 | * Releases the PCI I/O and memory resources previously reserved by a | |
3135 | * successful call to pci_request_region. Call this function only | |
3136 | * after all use of the PCI regions has ceased. | |
3137 | */ | |
3138 | void pci_release_region(struct pci_dev *pdev, int bar) | |
3139 | { | |
9ac7849e TH |
3140 | struct pci_devres *dr; |
3141 | ||
1da177e4 LT |
3142 | if (pci_resource_len(pdev, bar) == 0) |
3143 | return; | |
3144 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
3145 | release_region(pci_resource_start(pdev, bar), | |
3146 | pci_resource_len(pdev, bar)); | |
3147 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
3148 | release_mem_region(pci_resource_start(pdev, bar), | |
3149 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
3150 | |
3151 | dr = find_pci_dr(pdev); | |
3152 | if (dr) | |
3153 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 3154 | } |
b7fe9434 | 3155 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
3156 | |
3157 | /** | |
f5ddcac4 | 3158 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
3159 | * @pdev: PCI device whose resources are to be reserved |
3160 | * @bar: BAR to be reserved | |
3161 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 3162 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
3163 | * |
3164 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
3165 | * being reserved by owner @res_name. Do not access any | |
3166 | * address inside the PCI regions unless this call returns | |
3167 | * successfully. | |
3168 | * | |
f5ddcac4 RD |
3169 | * If @exclusive is set, then the region is marked so that userspace |
3170 | * is explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 3171 | * sysfs MMIO access. |
f5ddcac4 | 3172 | * |
1da177e4 LT |
3173 | * Returns 0 on success, or %EBUSY on error. A warning |
3174 | * message is also printed on failure. | |
3175 | */ | |
3c78bc61 RD |
3176 | static int __pci_request_region(struct pci_dev *pdev, int bar, |
3177 | const char *res_name, int exclusive) | |
1da177e4 | 3178 | { |
9ac7849e TH |
3179 | struct pci_devres *dr; |
3180 | ||
1da177e4 LT |
3181 | if (pci_resource_len(pdev, bar) == 0) |
3182 | return 0; | |
f7625980 | 3183 | |
1da177e4 LT |
3184 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
3185 | if (!request_region(pci_resource_start(pdev, bar), | |
3186 | pci_resource_len(pdev, bar), res_name)) | |
3187 | goto err_out; | |
3c78bc61 | 3188 | } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
e8de1481 AV |
3189 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
3190 | pci_resource_len(pdev, bar), res_name, | |
3191 | exclusive)) | |
1da177e4 LT |
3192 | goto err_out; |
3193 | } | |
9ac7849e TH |
3194 | |
3195 | dr = find_pci_dr(pdev); | |
3196 | if (dr) | |
3197 | dr->region_mask |= 1 << bar; | |
3198 | ||
1da177e4 LT |
3199 | return 0; |
3200 | ||
3201 | err_out: | |
c7dabef8 | 3202 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 3203 | &pdev->resource[bar]); |
1da177e4 LT |
3204 | return -EBUSY; |
3205 | } | |
3206 | ||
e8de1481 | 3207 | /** |
f5ddcac4 | 3208 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
3209 | * @pdev: PCI device whose resources are to be reserved |
3210 | * @bar: BAR to be reserved | |
f5ddcac4 | 3211 | * @res_name: Name to be associated with resource |
e8de1481 | 3212 | * |
f5ddcac4 | 3213 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
3214 | * being reserved by owner @res_name. Do not access any |
3215 | * address inside the PCI regions unless this call returns | |
3216 | * successfully. | |
3217 | * | |
3218 | * Returns 0 on success, or %EBUSY on error. A warning | |
3219 | * message is also printed on failure. | |
3220 | */ | |
3221 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
3222 | { | |
3223 | return __pci_request_region(pdev, bar, res_name, 0); | |
3224 | } | |
b7fe9434 | 3225 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 AV |
3226 | |
3227 | /** | |
3228 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
3229 | * @pdev: PCI device whose resources are to be reserved | |
3230 | * @bar: BAR to be reserved | |
3231 | * @res_name: Name to be associated with resource. | |
3232 | * | |
3233 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
3234 | * being reserved by owner @res_name. Do not access any | |
3235 | * address inside the PCI regions unless this call returns | |
3236 | * successfully. | |
3237 | * | |
3238 | * Returns 0 on success, or %EBUSY on error. A warning | |
3239 | * message is also printed on failure. | |
3240 | * | |
3241 | * The key difference that _exclusive makes it that userspace is | |
3242 | * explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 3243 | * sysfs. |
e8de1481 | 3244 | */ |
3c78bc61 RD |
3245 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, |
3246 | const char *res_name) | |
e8de1481 AV |
3247 | { |
3248 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
3249 | } | |
b7fe9434 RD |
3250 | EXPORT_SYMBOL(pci_request_region_exclusive); |
3251 | ||
c87deff7 HS |
3252 | /** |
3253 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
3254 | * @pdev: PCI device whose resources were previously reserved | |
3255 | * @bars: Bitmask of BARs to be released | |
3256 | * | |
3257 | * Release selected PCI I/O and memory resources previously reserved. | |
3258 | * Call this function only after all use of the PCI regions has ceased. | |
3259 | */ | |
3260 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
3261 | { | |
3262 | int i; | |
3263 | ||
3264 | for (i = 0; i < 6; i++) | |
3265 | if (bars & (1 << i)) | |
3266 | pci_release_region(pdev, i); | |
3267 | } | |
b7fe9434 | 3268 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 3269 | |
9738abed | 3270 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
3c78bc61 | 3271 | const char *res_name, int excl) |
c87deff7 HS |
3272 | { |
3273 | int i; | |
3274 | ||
3275 | for (i = 0; i < 6; i++) | |
3276 | if (bars & (1 << i)) | |
e8de1481 | 3277 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
3278 | goto err_out; |
3279 | return 0; | |
3280 | ||
3281 | err_out: | |
3c78bc61 | 3282 | while (--i >= 0) |
c87deff7 HS |
3283 | if (bars & (1 << i)) |
3284 | pci_release_region(pdev, i); | |
3285 | ||
3286 | return -EBUSY; | |
3287 | } | |
1da177e4 | 3288 | |
e8de1481 AV |
3289 | |
3290 | /** | |
3291 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
3292 | * @pdev: PCI device whose resources are to be reserved | |
3293 | * @bars: Bitmask of BARs to be requested | |
3294 | * @res_name: Name to be associated with resource | |
3295 | */ | |
3296 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
3297 | const char *res_name) | |
3298 | { | |
3299 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
3300 | } | |
b7fe9434 | 3301 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 | 3302 | |
3c78bc61 RD |
3303 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, |
3304 | const char *res_name) | |
e8de1481 AV |
3305 | { |
3306 | return __pci_request_selected_regions(pdev, bars, res_name, | |
3307 | IORESOURCE_EXCLUSIVE); | |
3308 | } | |
b7fe9434 | 3309 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 3310 | |
1da177e4 LT |
3311 | /** |
3312 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
3313 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
3314 | * | |
3315 | * Releases all PCI I/O and memory resources previously reserved by a | |
3316 | * successful call to pci_request_regions. Call this function only | |
3317 | * after all use of the PCI regions has ceased. | |
3318 | */ | |
3319 | ||
3320 | void pci_release_regions(struct pci_dev *pdev) | |
3321 | { | |
c87deff7 | 3322 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 | 3323 | } |
b7fe9434 | 3324 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
3325 | |
3326 | /** | |
3327 | * pci_request_regions - Reserved PCI I/O and memory resources | |
3328 | * @pdev: PCI device whose resources are to be reserved | |
3329 | * @res_name: Name to be associated with resource. | |
3330 | * | |
3331 | * Mark all PCI regions associated with PCI device @pdev as | |
3332 | * being reserved by owner @res_name. Do not access any | |
3333 | * address inside the PCI regions unless this call returns | |
3334 | * successfully. | |
3335 | * | |
3336 | * Returns 0 on success, or %EBUSY on error. A warning | |
3337 | * message is also printed on failure. | |
3338 | */ | |
3c990e92 | 3339 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 3340 | { |
c87deff7 | 3341 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 | 3342 | } |
b7fe9434 | 3343 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 3344 | |
e8de1481 AV |
3345 | /** |
3346 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
3347 | * @pdev: PCI device whose resources are to be reserved | |
3348 | * @res_name: Name to be associated with resource. | |
3349 | * | |
3350 | * Mark all PCI regions associated with PCI device @pdev as | |
3351 | * being reserved by owner @res_name. Do not access any | |
3352 | * address inside the PCI regions unless this call returns | |
3353 | * successfully. | |
3354 | * | |
3355 | * pci_request_regions_exclusive() will mark the region so that | |
f7625980 | 3356 | * /dev/mem and the sysfs MMIO access will not be allowed. |
e8de1481 AV |
3357 | * |
3358 | * Returns 0 on success, or %EBUSY on error. A warning | |
3359 | * message is also printed on failure. | |
3360 | */ | |
3361 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
3362 | { | |
3363 | return pci_request_selected_regions_exclusive(pdev, | |
3364 | ((1 << 6) - 1), res_name); | |
3365 | } | |
b7fe9434 | 3366 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 3367 | |
c5076cfe TN |
3368 | /* |
3369 | * Record the PCI IO range (expressed as CPU physical address + size). | |
3370 | * Return a negative value if an error has occured, zero otherwise | |
3371 | */ | |
36e6f3d4 GP |
3372 | int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr, |
3373 | resource_size_t size) | |
c5076cfe | 3374 | { |
046ff9e6 | 3375 | int ret = 0; |
c5076cfe | 3376 | #ifdef PCI_IOBASE |
046ff9e6 | 3377 | struct logic_pio_hwaddr *range; |
c5076cfe | 3378 | |
046ff9e6 ZY |
3379 | if (!size || addr + size < addr) |
3380 | return -EINVAL; | |
c5076cfe | 3381 | |
c5076cfe | 3382 | range = kzalloc(sizeof(*range), GFP_ATOMIC); |
046ff9e6 ZY |
3383 | if (!range) |
3384 | return -ENOMEM; | |
c5076cfe | 3385 | |
046ff9e6 | 3386 | range->fwnode = fwnode; |
c5076cfe | 3387 | range->size = size; |
046ff9e6 ZY |
3388 | range->hw_start = addr; |
3389 | range->flags = LOGIC_PIO_CPU_MMIO; | |
c5076cfe | 3390 | |
046ff9e6 ZY |
3391 | ret = logic_pio_register_range(range); |
3392 | if (ret) | |
3393 | kfree(range); | |
c5076cfe TN |
3394 | #endif |
3395 | ||
046ff9e6 | 3396 | return ret; |
c5076cfe TN |
3397 | } |
3398 | ||
3399 | phys_addr_t pci_pio_to_address(unsigned long pio) | |
3400 | { | |
3401 | phys_addr_t address = (phys_addr_t)OF_BAD_ADDR; | |
3402 | ||
3403 | #ifdef PCI_IOBASE | |
046ff9e6 | 3404 | if (pio >= MMIO_UPPER_LIMIT) |
c5076cfe TN |
3405 | return address; |
3406 | ||
046ff9e6 | 3407 | address = logic_pio_to_hwaddr(pio); |
c5076cfe TN |
3408 | #endif |
3409 | ||
3410 | return address; | |
3411 | } | |
3412 | ||
3413 | unsigned long __weak pci_address_to_pio(phys_addr_t address) | |
3414 | { | |
3415 | #ifdef PCI_IOBASE | |
046ff9e6 | 3416 | return logic_pio_trans_cpuaddr(address); |
c5076cfe TN |
3417 | #else |
3418 | if (address > IO_SPACE_LIMIT) | |
3419 | return (unsigned long)-1; | |
3420 | ||
3421 | return (unsigned long) address; | |
3422 | #endif | |
3423 | } | |
3424 | ||
8b921acf LD |
3425 | /** |
3426 | * pci_remap_iospace - Remap the memory mapped I/O space | |
3427 | * @res: Resource describing the I/O space | |
3428 | * @phys_addr: physical address of range to be mapped | |
3429 | * | |
3430 | * Remap the memory mapped I/O space described by the @res | |
3431 | * and the CPU physical address @phys_addr into virtual address space. | |
3432 | * Only architectures that have memory mapped IO functions defined | |
3433 | * (and the PCI_IOBASE value defined) should call this function. | |
3434 | */ | |
7b309aef | 3435 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) |
8b921acf LD |
3436 | { |
3437 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3438 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3439 | ||
3440 | if (!(res->flags & IORESOURCE_IO)) | |
3441 | return -EINVAL; | |
3442 | ||
3443 | if (res->end > IO_SPACE_LIMIT) | |
3444 | return -EINVAL; | |
3445 | ||
3446 | return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr, | |
3447 | pgprot_device(PAGE_KERNEL)); | |
3448 | #else | |
3449 | /* this architecture does not have memory mapped I/O space, | |
3450 | so this function should never be called */ | |
3451 | WARN_ONCE(1, "This architecture does not support memory mapped I/O\n"); | |
3452 | return -ENODEV; | |
3453 | #endif | |
3454 | } | |
f90b0875 | 3455 | EXPORT_SYMBOL(pci_remap_iospace); |
8b921acf | 3456 | |
4d3f1384 SK |
3457 | /** |
3458 | * pci_unmap_iospace - Unmap the memory mapped I/O space | |
3459 | * @res: resource to be unmapped | |
3460 | * | |
3461 | * Unmap the CPU virtual address @res from virtual address space. | |
3462 | * Only architectures that have memory mapped IO functions defined | |
3463 | * (and the PCI_IOBASE value defined) should call this function. | |
3464 | */ | |
3465 | void pci_unmap_iospace(struct resource *res) | |
3466 | { | |
3467 | #if defined(PCI_IOBASE) && defined(CONFIG_MMU) | |
3468 | unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; | |
3469 | ||
3470 | unmap_kernel_range(vaddr, resource_size(res)); | |
3471 | #endif | |
3472 | } | |
f90b0875 | 3473 | EXPORT_SYMBOL(pci_unmap_iospace); |
4d3f1384 | 3474 | |
490cb6dd LP |
3475 | /** |
3476 | * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace() | |
3477 | * @dev: Generic device to remap IO address for | |
3478 | * @offset: Resource address to map | |
3479 | * @size: Size of map | |
3480 | * | |
3481 | * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver | |
3482 | * detach. | |
3483 | */ | |
3484 | void __iomem *devm_pci_remap_cfgspace(struct device *dev, | |
3485 | resource_size_t offset, | |
3486 | resource_size_t size) | |
3487 | { | |
3488 | void __iomem **ptr, *addr; | |
3489 | ||
3490 | ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL); | |
3491 | if (!ptr) | |
3492 | return NULL; | |
3493 | ||
3494 | addr = pci_remap_cfgspace(offset, size); | |
3495 | if (addr) { | |
3496 | *ptr = addr; | |
3497 | devres_add(dev, ptr); | |
3498 | } else | |
3499 | devres_free(ptr); | |
3500 | ||
3501 | return addr; | |
3502 | } | |
3503 | EXPORT_SYMBOL(devm_pci_remap_cfgspace); | |
3504 | ||
3505 | /** | |
3506 | * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource | |
3507 | * @dev: generic device to handle the resource for | |
3508 | * @res: configuration space resource to be handled | |
3509 | * | |
3510 | * Checks that a resource is a valid memory region, requests the memory | |
3511 | * region and ioremaps with pci_remap_cfgspace() API that ensures the | |
3512 | * proper PCI configuration space memory attributes are guaranteed. | |
3513 | * | |
3514 | * All operations are managed and will be undone on driver detach. | |
3515 | * | |
3516 | * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code | |
505fb746 | 3517 | * on failure. Usage example:: |
490cb6dd LP |
3518 | * |
3519 | * res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
3520 | * base = devm_pci_remap_cfg_resource(&pdev->dev, res); | |
3521 | * if (IS_ERR(base)) | |
3522 | * return PTR_ERR(base); | |
3523 | */ | |
3524 | void __iomem *devm_pci_remap_cfg_resource(struct device *dev, | |
3525 | struct resource *res) | |
3526 | { | |
3527 | resource_size_t size; | |
3528 | const char *name; | |
3529 | void __iomem *dest_ptr; | |
3530 | ||
3531 | BUG_ON(!dev); | |
3532 | ||
3533 | if (!res || resource_type(res) != IORESOURCE_MEM) { | |
3534 | dev_err(dev, "invalid resource\n"); | |
3535 | return IOMEM_ERR_PTR(-EINVAL); | |
3536 | } | |
3537 | ||
3538 | size = resource_size(res); | |
3539 | name = res->name ?: dev_name(dev); | |
3540 | ||
3541 | if (!devm_request_mem_region(dev, res->start, size, name)) { | |
3542 | dev_err(dev, "can't request region for resource %pR\n", res); | |
3543 | return IOMEM_ERR_PTR(-EBUSY); | |
3544 | } | |
3545 | ||
3546 | dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); | |
3547 | if (!dest_ptr) { | |
3548 | dev_err(dev, "ioremap failed for resource %pR\n", res); | |
3549 | devm_release_mem_region(dev, res->start, size); | |
3550 | dest_ptr = IOMEM_ERR_PTR(-ENOMEM); | |
3551 | } | |
3552 | ||
3553 | return dest_ptr; | |
3554 | } | |
3555 | EXPORT_SYMBOL(devm_pci_remap_cfg_resource); | |
3556 | ||
6a479079 BH |
3557 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
3558 | { | |
3559 | u16 old_cmd, cmd; | |
3560 | ||
3561 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
3562 | if (enable) | |
3563 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
3564 | else | |
3565 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
3566 | if (cmd != old_cmd) { | |
3567 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
3568 | enable ? "enabling" : "disabling"); | |
3569 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3570 | } | |
3571 | dev->is_busmaster = enable; | |
3572 | } | |
e8de1481 | 3573 | |
2b6f2c35 MS |
3574 | /** |
3575 | * pcibios_setup - process "pci=" kernel boot arguments | |
3576 | * @str: string used to pass in "pci=" kernel boot arguments | |
3577 | * | |
3578 | * Process kernel boot arguments. This is the default implementation. | |
3579 | * Architecture specific implementations can override this as necessary. | |
3580 | */ | |
3581 | char * __weak __init pcibios_setup(char *str) | |
3582 | { | |
3583 | return str; | |
3584 | } | |
3585 | ||
96c55900 MS |
3586 | /** |
3587 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
3588 | * @dev: the PCI device to enable | |
3589 | * | |
3590 | * Enables PCI bus-mastering for the device. This is the default | |
3591 | * implementation. Architecture specific implementations can override | |
3592 | * this if necessary. | |
3593 | */ | |
3594 | void __weak pcibios_set_master(struct pci_dev *dev) | |
3595 | { | |
3596 | u8 lat; | |
3597 | ||
f676678f MS |
3598 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
3599 | if (pci_is_pcie(dev)) | |
3600 | return; | |
3601 | ||
96c55900 MS |
3602 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
3603 | if (lat < 16) | |
3604 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
3605 | else if (lat > pcibios_max_latency) | |
3606 | lat = pcibios_max_latency; | |
3607 | else | |
3608 | return; | |
a006482b | 3609 | |
96c55900 MS |
3610 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
3611 | } | |
3612 | ||
1da177e4 LT |
3613 | /** |
3614 | * pci_set_master - enables bus-mastering for device dev | |
3615 | * @dev: the PCI device to enable | |
3616 | * | |
3617 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
3618 | * to do the needed arch specific settings. | |
3619 | */ | |
6a479079 | 3620 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 3621 | { |
6a479079 | 3622 | __pci_set_master(dev, true); |
1da177e4 LT |
3623 | pcibios_set_master(dev); |
3624 | } | |
b7fe9434 | 3625 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 3626 | |
6a479079 BH |
3627 | /** |
3628 | * pci_clear_master - disables bus-mastering for device dev | |
3629 | * @dev: the PCI device to disable | |
3630 | */ | |
3631 | void pci_clear_master(struct pci_dev *dev) | |
3632 | { | |
3633 | __pci_set_master(dev, false); | |
3634 | } | |
b7fe9434 | 3635 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 3636 | |
1da177e4 | 3637 | /** |
edb2d97e MW |
3638 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
3639 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 3640 | * |
edb2d97e MW |
3641 | * Helper function for pci_set_mwi. |
3642 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
3643 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
3644 | * | |
3645 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3646 | */ | |
15ea76d4 | 3647 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
3648 | { |
3649 | u8 cacheline_size; | |
3650 | ||
3651 | if (!pci_cache_line_size) | |
15ea76d4 | 3652 | return -EINVAL; |
1da177e4 LT |
3653 | |
3654 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
3655 | equal to or multiple of the right value. */ | |
3656 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
3657 | if (cacheline_size >= pci_cache_line_size && | |
3658 | (cacheline_size % pci_cache_line_size) == 0) | |
3659 | return 0; | |
3660 | ||
3661 | /* Write the correct value. */ | |
3662 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
3663 | /* Read it back. */ | |
3664 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
3665 | if (cacheline_size == pci_cache_line_size) | |
3666 | return 0; | |
3667 | ||
227f0647 RD |
3668 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n", |
3669 | pci_cache_line_size << 2); | |
1da177e4 LT |
3670 | |
3671 | return -EINVAL; | |
3672 | } | |
15ea76d4 TH |
3673 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
3674 | ||
1da177e4 LT |
3675 | /** |
3676 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
3677 | * @dev: the PCI device for which MWI is enabled | |
3678 | * | |
694625c0 | 3679 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
3680 | * |
3681 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3682 | */ | |
3c78bc61 | 3683 | int pci_set_mwi(struct pci_dev *dev) |
1da177e4 | 3684 | { |
b7fe9434 RD |
3685 | #ifdef PCI_DISABLE_MWI |
3686 | return 0; | |
3687 | #else | |
1da177e4 LT |
3688 | int rc; |
3689 | u16 cmd; | |
3690 | ||
edb2d97e | 3691 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
3692 | if (rc) |
3693 | return rc; | |
3694 | ||
3695 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3c78bc61 | 3696 | if (!(cmd & PCI_COMMAND_INVALIDATE)) { |
80ccba11 | 3697 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
3698 | cmd |= PCI_COMMAND_INVALIDATE; |
3699 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3700 | } | |
1da177e4 | 3701 | return 0; |
b7fe9434 | 3702 | #endif |
1da177e4 | 3703 | } |
b7fe9434 | 3704 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 3705 | |
694625c0 RD |
3706 | /** |
3707 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
3708 | * @dev: the PCI device for which MWI is enabled | |
3709 | * | |
3710 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
3711 | * Callers are not required to check the return value. | |
3712 | * | |
3713 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
3714 | */ | |
3715 | int pci_try_set_mwi(struct pci_dev *dev) | |
3716 | { | |
b7fe9434 RD |
3717 | #ifdef PCI_DISABLE_MWI |
3718 | return 0; | |
3719 | #else | |
3720 | return pci_set_mwi(dev); | |
3721 | #endif | |
694625c0 | 3722 | } |
b7fe9434 | 3723 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 3724 | |
1da177e4 LT |
3725 | /** |
3726 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
3727 | * @dev: the PCI device to disable | |
3728 | * | |
3729 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
3730 | */ | |
3c78bc61 | 3731 | void pci_clear_mwi(struct pci_dev *dev) |
1da177e4 | 3732 | { |
b7fe9434 | 3733 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
3734 | u16 cmd; |
3735 | ||
3736 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
3737 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
3738 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
3739 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
3740 | } | |
b7fe9434 | 3741 | #endif |
1da177e4 | 3742 | } |
b7fe9434 | 3743 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 3744 | |
a04ce0ff BR |
3745 | /** |
3746 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
3747 | * @pdev: the PCI device to operate on |
3748 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
3749 | * |
3750 | * Enables/disables PCI INTx for device dev | |
3751 | */ | |
3c78bc61 | 3752 | void pci_intx(struct pci_dev *pdev, int enable) |
a04ce0ff BR |
3753 | { |
3754 | u16 pci_command, new; | |
3755 | ||
3756 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
3757 | ||
3c78bc61 | 3758 | if (enable) |
a04ce0ff | 3759 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; |
3c78bc61 | 3760 | else |
a04ce0ff | 3761 | new = pci_command | PCI_COMMAND_INTX_DISABLE; |
a04ce0ff BR |
3762 | |
3763 | if (new != pci_command) { | |
9ac7849e TH |
3764 | struct pci_devres *dr; |
3765 | ||
2fd9d74b | 3766 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
3767 | |
3768 | dr = find_pci_dr(pdev); | |
3769 | if (dr && !dr->restore_intx) { | |
3770 | dr->restore_intx = 1; | |
3771 | dr->orig_intx = !enable; | |
3772 | } | |
a04ce0ff BR |
3773 | } |
3774 | } | |
b7fe9434 | 3775 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 3776 | |
a2e27787 JK |
3777 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) |
3778 | { | |
3779 | struct pci_bus *bus = dev->bus; | |
3780 | bool mask_updated = true; | |
3781 | u32 cmd_status_dword; | |
3782 | u16 origcmd, newcmd; | |
3783 | unsigned long flags; | |
3784 | bool irq_pending; | |
3785 | ||
3786 | /* | |
3787 | * We do a single dword read to retrieve both command and status. | |
3788 | * Document assumptions that make this possible. | |
3789 | */ | |
3790 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
3791 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
3792 | ||
3793 | raw_spin_lock_irqsave(&pci_lock, flags); | |
3794 | ||
3795 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
3796 | ||
3797 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
3798 | ||
3799 | /* | |
3800 | * Check interrupt status register to see whether our device | |
3801 | * triggered the interrupt (when masking) or the next IRQ is | |
3802 | * already pending (when unmasking). | |
3803 | */ | |
3804 | if (mask != irq_pending) { | |
3805 | mask_updated = false; | |
3806 | goto done; | |
3807 | } | |
3808 | ||
3809 | origcmd = cmd_status_dword; | |
3810 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
3811 | if (mask) | |
3812 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
3813 | if (newcmd != origcmd) | |
3814 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
3815 | ||
3816 | done: | |
3817 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
3818 | ||
3819 | return mask_updated; | |
3820 | } | |
3821 | ||
3822 | /** | |
3823 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 3824 | * @dev: the PCI device to operate on |
a2e27787 JK |
3825 | * |
3826 | * Check if the device dev has its INTx line asserted, mask it and | |
99b3c58f | 3827 | * return true in that case. False is returned if no interrupt was |
a2e27787 JK |
3828 | * pending. |
3829 | */ | |
3830 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
3831 | { | |
3832 | return pci_check_and_set_intx_mask(dev, true); | |
3833 | } | |
3834 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
3835 | ||
3836 | /** | |
ebd50b93 | 3837 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 3838 | * @dev: the PCI device to operate on |
a2e27787 JK |
3839 | * |
3840 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3841 | * and return true. False is returned and the mask remains active if | |
3842 | * there was still an interrupt pending. | |
3843 | */ | |
3844 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3845 | { | |
3846 | return pci_check_and_set_intx_mask(dev, false); | |
3847 | } | |
3848 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3849 | ||
3775a209 CL |
3850 | /** |
3851 | * pci_wait_for_pending_transaction - waits for pending transaction | |
3852 | * @dev: the PCI device to operate on | |
3853 | * | |
3854 | * Return 0 if transaction is pending 1 otherwise. | |
3855 | */ | |
3856 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 3857 | { |
157e876f AW |
3858 | if (!pci_is_pcie(dev)) |
3859 | return 1; | |
8c1c699f | 3860 | |
d0b4cc4e GS |
3861 | return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA, |
3862 | PCI_EXP_DEVSTA_TRPND); | |
3775a209 CL |
3863 | } |
3864 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
3865 | ||
5adecf81 AW |
3866 | static void pci_flr_wait(struct pci_dev *dev) |
3867 | { | |
821cdad5 | 3868 | int delay = 1, timeout = 60000; |
5adecf81 AW |
3869 | u32 id; |
3870 | ||
821cdad5 SK |
3871 | /* |
3872 | * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within | |
3873 | * 100ms, but may silently discard requests while the FLR is in | |
3874 | * progress. Wait 100ms before trying to access the device. | |
3875 | */ | |
3876 | msleep(100); | |
3877 | ||
3878 | /* | |
3879 | * After 100ms, the device should not silently discard config | |
3880 | * requests, but it may still indicate that it needs more time by | |
3881 | * responding to them with CRS completions. The Root Port will | |
3882 | * generally synthesize ~0 data to complete the read (except when | |
3883 | * CRS SV is enabled and the read was for the Vendor ID; in that | |
3884 | * case it synthesizes 0x0001 data). | |
3885 | * | |
3886 | * Wait for the device to return a non-CRS completion. Read the | |
3887 | * Command register instead of Vendor ID so we don't have to | |
3888 | * contend with the CRS SV value. | |
3889 | */ | |
3890 | pci_read_config_dword(dev, PCI_COMMAND, &id); | |
3891 | while (id == ~0) { | |
3892 | if (delay > timeout) { | |
3893 | dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n", | |
3894 | 100 + delay - 1); | |
3895 | return; | |
3896 | } | |
3897 | ||
3898 | if (delay > 1000) | |
3899 | dev_info(&dev->dev, "not ready %dms after FLR; waiting\n", | |
3900 | 100 + delay - 1); | |
3901 | ||
3902 | msleep(delay); | |
3903 | delay *= 2; | |
5adecf81 | 3904 | pci_read_config_dword(dev, PCI_COMMAND, &id); |
821cdad5 | 3905 | } |
5adecf81 | 3906 | |
821cdad5 SK |
3907 | if (delay > 1000) |
3908 | dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1); | |
5adecf81 AW |
3909 | } |
3910 | ||
a60a2b73 CH |
3911 | /** |
3912 | * pcie_has_flr - check if a device supports function level resets | |
3913 | * @dev: device to check | |
3914 | * | |
3915 | * Returns true if the device advertises support for PCIe function level | |
3916 | * resets. | |
3917 | */ | |
3918 | static bool pcie_has_flr(struct pci_dev *dev) | |
3775a209 CL |
3919 | { |
3920 | u32 cap; | |
3921 | ||
f65fd1aa | 3922 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
a60a2b73 | 3923 | return false; |
3775a209 | 3924 | |
a60a2b73 CH |
3925 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
3926 | return cap & PCI_EXP_DEVCAP_FLR; | |
3927 | } | |
3775a209 | 3928 | |
a60a2b73 CH |
3929 | /** |
3930 | * pcie_flr - initiate a PCIe function level reset | |
3931 | * @dev: device to reset | |
3932 | * | |
3933 | * Initiate a function level reset on @dev. The caller should ensure the | |
3934 | * device supports FLR before calling this function, e.g. by using the | |
3935 | * pcie_has_flr() helper. | |
3936 | */ | |
3937 | void pcie_flr(struct pci_dev *dev) | |
3938 | { | |
3775a209 | 3939 | if (!pci_wait_for_pending_transaction(dev)) |
bb383e28 | 3940 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n"); |
8c1c699f | 3941 | |
59875ae4 | 3942 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
5adecf81 | 3943 | pci_flr_wait(dev); |
8dd7f803 | 3944 | } |
a60a2b73 | 3945 | EXPORT_SYMBOL_GPL(pcie_flr); |
d91cdc74 | 3946 | |
8c1c699f | 3947 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3948 | { |
8c1c699f | 3949 | int pos; |
1ca88797 SY |
3950 | u8 cap; |
3951 | ||
8c1c699f YZ |
3952 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3953 | if (!pos) | |
1ca88797 | 3954 | return -ENOTTY; |
8c1c699f | 3955 | |
f65fd1aa SN |
3956 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) |
3957 | return -ENOTTY; | |
3958 | ||
8c1c699f | 3959 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); |
1ca88797 SY |
3960 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3961 | return -ENOTTY; | |
3962 | ||
3963 | if (probe) | |
3964 | return 0; | |
3965 | ||
d066c946 AW |
3966 | /* |
3967 | * Wait for Transaction Pending bit to clear. A word-aligned test | |
3968 | * is used, so we use the conrol offset rather than status and shift | |
3969 | * the test bit to match. | |
3970 | */ | |
bb383e28 | 3971 | if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL, |
d066c946 | 3972 | PCI_AF_STATUS_TP << 8)) |
bb383e28 | 3973 | dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n"); |
5fe5db05 | 3974 | |
8c1c699f | 3975 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); |
5adecf81 | 3976 | pci_flr_wait(dev); |
1ca88797 SY |
3977 | return 0; |
3978 | } | |
3979 | ||
83d74e03 RW |
3980 | /** |
3981 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3982 | * @dev: Device to reset. | |
3983 | * @probe: If set, only check if the device can be reset this way. | |
3984 | * | |
3985 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3986 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3987 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3988 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3989 | * | |
3990 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3991 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 3992 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
3993 | * Moreover, only devices in D0 can be reset by this function. |
3994 | */ | |
f85876ba | 3995 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3996 | { |
f85876ba YZ |
3997 | u16 csr; |
3998 | ||
51e53738 | 3999 | if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) |
f85876ba | 4000 | return -ENOTTY; |
d91cdc74 | 4001 | |
f85876ba YZ |
4002 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
4003 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
4004 | return -ENOTTY; | |
d91cdc74 | 4005 | |
f85876ba YZ |
4006 | if (probe) |
4007 | return 0; | |
1ca88797 | 4008 | |
f85876ba YZ |
4009 | if (dev->current_state != PCI_D0) |
4010 | return -EINVAL; | |
4011 | ||
4012 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4013 | csr |= PCI_D3hot; | |
4014 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4015 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
4016 | |
4017 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
4018 | csr |= PCI_D0; | |
4019 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 4020 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
4021 | |
4022 | return 0; | |
4023 | } | |
4024 | ||
9e33002f | 4025 | void pci_reset_secondary_bus(struct pci_dev *dev) |
c12ff1df YZ |
4026 | { |
4027 | u16 ctrl; | |
64e8674f AW |
4028 | |
4029 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
4030 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
4031 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
4032 | /* |
4033 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 4034 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
4035 | */ |
4036 | msleep(2); | |
64e8674f AW |
4037 | |
4038 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
4039 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
4040 | |
4041 | /* | |
4042 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
4043 | * Assuming a minimum 33MHz clock this results in a 1s | |
4044 | * delay before we can consider subordinate devices to | |
4045 | * be re-initialized. PCIe has some ways to shorten this, | |
4046 | * but we don't make use of them yet. | |
4047 | */ | |
4048 | ssleep(1); | |
64e8674f | 4049 | } |
d92a208d | 4050 | |
9e33002f GS |
4051 | void __weak pcibios_reset_secondary_bus(struct pci_dev *dev) |
4052 | { | |
4053 | pci_reset_secondary_bus(dev); | |
4054 | } | |
4055 | ||
d92a208d GS |
4056 | /** |
4057 | * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. | |
4058 | * @dev: Bridge device | |
4059 | * | |
4060 | * Use the bridge control register to assert reset on the secondary bus. | |
4061 | * Devices on the secondary bus are left in power-on state. | |
4062 | */ | |
4063 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev) | |
4064 | { | |
4065 | pcibios_reset_secondary_bus(dev); | |
4066 | } | |
64e8674f AW |
4067 | EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); |
4068 | ||
4069 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
4070 | { | |
c12ff1df YZ |
4071 | struct pci_dev *pdev; |
4072 | ||
f331a859 AW |
4073 | if (pci_is_root_bus(dev->bus) || dev->subordinate || |
4074 | !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
c12ff1df YZ |
4075 | return -ENOTTY; |
4076 | ||
4077 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4078 | if (pdev != dev) | |
4079 | return -ENOTTY; | |
4080 | ||
4081 | if (probe) | |
4082 | return 0; | |
4083 | ||
64e8674f | 4084 | pci_reset_bridge_secondary_bus(dev->bus->self); |
c12ff1df YZ |
4085 | |
4086 | return 0; | |
4087 | } | |
4088 | ||
608c3881 AW |
4089 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
4090 | { | |
4091 | int rc = -ENOTTY; | |
4092 | ||
4093 | if (!hotplug || !try_module_get(hotplug->ops->owner)) | |
4094 | return rc; | |
4095 | ||
4096 | if (hotplug->ops->reset_slot) | |
4097 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
4098 | ||
4099 | module_put(hotplug->ops->owner); | |
4100 | ||
4101 | return rc; | |
4102 | } | |
4103 | ||
4104 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
4105 | { | |
4106 | struct pci_dev *pdev; | |
4107 | ||
f331a859 AW |
4108 | if (dev->subordinate || !dev->slot || |
4109 | dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) | |
608c3881 AW |
4110 | return -ENOTTY; |
4111 | ||
4112 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
4113 | if (pdev != dev && pdev->slot == dev->slot) | |
4114 | return -ENOTTY; | |
4115 | ||
4116 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
4117 | } | |
4118 | ||
77cb985a AW |
4119 | static void pci_dev_lock(struct pci_dev *dev) |
4120 | { | |
4121 | pci_cfg_access_lock(dev); | |
4122 | /* block PM suspend, driver probe, etc. */ | |
4123 | device_lock(&dev->dev); | |
4124 | } | |
4125 | ||
61cf16d8 AW |
4126 | /* Return 1 on successful lock, 0 on contention */ |
4127 | static int pci_dev_trylock(struct pci_dev *dev) | |
4128 | { | |
4129 | if (pci_cfg_access_trylock(dev)) { | |
4130 | if (device_trylock(&dev->dev)) | |
4131 | return 1; | |
4132 | pci_cfg_access_unlock(dev); | |
4133 | } | |
4134 | ||
4135 | return 0; | |
4136 | } | |
4137 | ||
77cb985a AW |
4138 | static void pci_dev_unlock(struct pci_dev *dev) |
4139 | { | |
4140 | device_unlock(&dev->dev); | |
4141 | pci_cfg_access_unlock(dev); | |
4142 | } | |
4143 | ||
775755ed | 4144 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3ebe7f9f KB |
4145 | { |
4146 | const struct pci_error_handlers *err_handler = | |
4147 | dev->driver ? dev->driver->err_handler : NULL; | |
3ebe7f9f | 4148 | |
b014e96d | 4149 | /* |
775755ed | 4150 | * dev->driver->err_handler->reset_prepare() is protected against |
b014e96d CH |
4151 | * races with ->remove() by the device lock, which must be held by |
4152 | * the caller. | |
4153 | */ | |
775755ed CH |
4154 | if (err_handler && err_handler->reset_prepare) |
4155 | err_handler->reset_prepare(dev); | |
3ebe7f9f | 4156 | |
a6cbaade AW |
4157 | /* |
4158 | * Wake-up device prior to save. PM registers default to D0 after | |
4159 | * reset and a simple register restore doesn't reliably return | |
4160 | * to a non-D0 state anyway. | |
4161 | */ | |
4162 | pci_set_power_state(dev, PCI_D0); | |
4163 | ||
77cb985a AW |
4164 | pci_save_state(dev); |
4165 | /* | |
4166 | * Disable the device by clearing the Command register, except for | |
4167 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
4168 | * BARs, but also prevents the device from being Bus Master, preventing | |
4169 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
4170 | * compliant devices, INTx-disable prevents legacy interrupts. | |
4171 | */ | |
4172 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
4173 | } | |
4174 | ||
4175 | static void pci_dev_restore(struct pci_dev *dev) | |
4176 | { | |
775755ed CH |
4177 | const struct pci_error_handlers *err_handler = |
4178 | dev->driver ? dev->driver->err_handler : NULL; | |
977f857c | 4179 | |
77cb985a | 4180 | pci_restore_state(dev); |
77cb985a | 4181 | |
775755ed CH |
4182 | /* |
4183 | * dev->driver->err_handler->reset_done() is protected against | |
4184 | * races with ->remove() by the device lock, which must be held by | |
4185 | * the caller. | |
4186 | */ | |
4187 | if (err_handler && err_handler->reset_done) | |
4188 | err_handler->reset_done(dev); | |
d91cdc74 | 4189 | } |
3ebe7f9f | 4190 | |
6fbf9e7a KRW |
4191 | /** |
4192 | * __pci_reset_function_locked - reset a PCI device function while holding | |
4193 | * the @dev mutex lock. | |
4194 | * @dev: PCI device to reset | |
4195 | * | |
4196 | * Some devices allow an individual function to be reset without affecting | |
4197 | * other functions in the same device. The PCI device must be responsive | |
4198 | * to PCI config space in order to use this function. | |
4199 | * | |
4200 | * The device function is presumed to be unused and the caller is holding | |
4201 | * the device mutex lock when this function is called. | |
4202 | * Resetting the device will make the contents of PCI configuration space | |
4203 | * random, so any caller of this must be prepared to reinitialise the | |
4204 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
4205 | * etc. | |
4206 | * | |
4207 | * Returns 0 if the device function was successfully reset or negative if the | |
4208 | * device doesn't support resetting a single function. | |
4209 | */ | |
4210 | int __pci_reset_function_locked(struct pci_dev *dev) | |
4211 | { | |
52354b9d CH |
4212 | int rc; |
4213 | ||
4214 | might_sleep(); | |
4215 | ||
832c418a BH |
4216 | /* |
4217 | * A reset method returns -ENOTTY if it doesn't support this device | |
4218 | * and we should try the next method. | |
4219 | * | |
4220 | * If it returns 0 (success), we're finished. If it returns any | |
4221 | * other error, we're also finished: this indicates that further | |
4222 | * reset mechanisms might be broken on the device. | |
4223 | */ | |
52354b9d CH |
4224 | rc = pci_dev_specific_reset(dev, 0); |
4225 | if (rc != -ENOTTY) | |
4226 | return rc; | |
4227 | if (pcie_has_flr(dev)) { | |
4228 | pcie_flr(dev); | |
4229 | return 0; | |
4230 | } | |
4231 | rc = pci_af_flr(dev, 0); | |
4232 | if (rc != -ENOTTY) | |
4233 | return rc; | |
4234 | rc = pci_pm_reset(dev, 0); | |
4235 | if (rc != -ENOTTY) | |
4236 | return rc; | |
4237 | rc = pci_dev_reset_slot_function(dev, 0); | |
4238 | if (rc != -ENOTTY) | |
4239 | return rc; | |
4240 | return pci_parent_bus_reset(dev, 0); | |
6fbf9e7a KRW |
4241 | } |
4242 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
4243 | ||
711d5779 MT |
4244 | /** |
4245 | * pci_probe_reset_function - check whether the device can be safely reset | |
4246 | * @dev: PCI device to reset | |
4247 | * | |
4248 | * Some devices allow an individual function to be reset without affecting | |
4249 | * other functions in the same device. The PCI device must be responsive | |
4250 | * to PCI config space in order to use this function. | |
4251 | * | |
4252 | * Returns 0 if the device function can be reset or negative if the | |
4253 | * device doesn't support resetting a single function. | |
4254 | */ | |
4255 | int pci_probe_reset_function(struct pci_dev *dev) | |
4256 | { | |
52354b9d CH |
4257 | int rc; |
4258 | ||
4259 | might_sleep(); | |
4260 | ||
4261 | rc = pci_dev_specific_reset(dev, 1); | |
4262 | if (rc != -ENOTTY) | |
4263 | return rc; | |
4264 | if (pcie_has_flr(dev)) | |
4265 | return 0; | |
4266 | rc = pci_af_flr(dev, 1); | |
4267 | if (rc != -ENOTTY) | |
4268 | return rc; | |
4269 | rc = pci_pm_reset(dev, 1); | |
4270 | if (rc != -ENOTTY) | |
4271 | return rc; | |
4272 | rc = pci_dev_reset_slot_function(dev, 1); | |
4273 | if (rc != -ENOTTY) | |
4274 | return rc; | |
4275 | ||
4276 | return pci_parent_bus_reset(dev, 1); | |
711d5779 MT |
4277 | } |
4278 | ||
8dd7f803 | 4279 | /** |
8c1c699f YZ |
4280 | * pci_reset_function - quiesce and reset a PCI device function |
4281 | * @dev: PCI device to reset | |
8dd7f803 SY |
4282 | * |
4283 | * Some devices allow an individual function to be reset without affecting | |
4284 | * other functions in the same device. The PCI device must be responsive | |
4285 | * to PCI config space in order to use this function. | |
4286 | * | |
4287 | * This function does not just reset the PCI portion of a device, but | |
4288 | * clears all the state associated with the device. This function differs | |
79e699b6 JS |
4289 | * from __pci_reset_function_locked() in that it saves and restores device state |
4290 | * over the reset and takes the PCI device lock. | |
8dd7f803 | 4291 | * |
8c1c699f | 4292 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
4293 | * device doesn't support resetting a single function. |
4294 | */ | |
4295 | int pci_reset_function(struct pci_dev *dev) | |
4296 | { | |
8c1c699f | 4297 | int rc; |
8dd7f803 | 4298 | |
52354b9d | 4299 | rc = pci_probe_reset_function(dev); |
8c1c699f YZ |
4300 | if (rc) |
4301 | return rc; | |
8dd7f803 | 4302 | |
b014e96d | 4303 | pci_dev_lock(dev); |
77cb985a | 4304 | pci_dev_save_and_disable(dev); |
8dd7f803 | 4305 | |
52354b9d | 4306 | rc = __pci_reset_function_locked(dev); |
8dd7f803 | 4307 | |
77cb985a | 4308 | pci_dev_restore(dev); |
b014e96d | 4309 | pci_dev_unlock(dev); |
8dd7f803 | 4310 | |
8c1c699f | 4311 | return rc; |
8dd7f803 SY |
4312 | } |
4313 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
4314 | ||
a477b9cd MZ |
4315 | /** |
4316 | * pci_reset_function_locked - quiesce and reset a PCI device function | |
4317 | * @dev: PCI device to reset | |
4318 | * | |
4319 | * Some devices allow an individual function to be reset without affecting | |
4320 | * other functions in the same device. The PCI device must be responsive | |
4321 | * to PCI config space in order to use this function. | |
4322 | * | |
4323 | * This function does not just reset the PCI portion of a device, but | |
4324 | * clears all the state associated with the device. This function differs | |
79e699b6 | 4325 | * from __pci_reset_function_locked() in that it saves and restores device state |
a477b9cd MZ |
4326 | * over the reset. It also differs from pci_reset_function() in that it |
4327 | * requires the PCI device lock to be held. | |
4328 | * | |
4329 | * Returns 0 if the device function was successfully reset or negative if the | |
4330 | * device doesn't support resetting a single function. | |
4331 | */ | |
4332 | int pci_reset_function_locked(struct pci_dev *dev) | |
4333 | { | |
4334 | int rc; | |
4335 | ||
4336 | rc = pci_probe_reset_function(dev); | |
4337 | if (rc) | |
4338 | return rc; | |
4339 | ||
4340 | pci_dev_save_and_disable(dev); | |
4341 | ||
4342 | rc = __pci_reset_function_locked(dev); | |
4343 | ||
4344 | pci_dev_restore(dev); | |
4345 | ||
4346 | return rc; | |
4347 | } | |
4348 | EXPORT_SYMBOL_GPL(pci_reset_function_locked); | |
4349 | ||
61cf16d8 AW |
4350 | /** |
4351 | * pci_try_reset_function - quiesce and reset a PCI device function | |
4352 | * @dev: PCI device to reset | |
4353 | * | |
4354 | * Same as above, except return -EAGAIN if unable to lock device. | |
4355 | */ | |
4356 | int pci_try_reset_function(struct pci_dev *dev) | |
4357 | { | |
4358 | int rc; | |
4359 | ||
52354b9d | 4360 | rc = pci_probe_reset_function(dev); |
61cf16d8 AW |
4361 | if (rc) |
4362 | return rc; | |
4363 | ||
b014e96d CH |
4364 | if (!pci_dev_trylock(dev)) |
4365 | return -EAGAIN; | |
61cf16d8 | 4366 | |
b014e96d | 4367 | pci_dev_save_and_disable(dev); |
52354b9d | 4368 | rc = __pci_reset_function_locked(dev); |
b014e96d | 4369 | pci_dev_unlock(dev); |
61cf16d8 AW |
4370 | |
4371 | pci_dev_restore(dev); | |
61cf16d8 AW |
4372 | return rc; |
4373 | } | |
4374 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
4375 | ||
f331a859 AW |
4376 | /* Do any devices on or below this bus prevent a bus reset? */ |
4377 | static bool pci_bus_resetable(struct pci_bus *bus) | |
4378 | { | |
4379 | struct pci_dev *dev; | |
4380 | ||
35702778 DD |
4381 | |
4382 | if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
4383 | return false; | |
4384 | ||
f331a859 AW |
4385 | list_for_each_entry(dev, &bus->devices, bus_list) { |
4386 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
4387 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
4388 | return false; | |
4389 | } | |
4390 | ||
4391 | return true; | |
4392 | } | |
4393 | ||
090a3c53 AW |
4394 | /* Lock devices from the top of the tree down */ |
4395 | static void pci_bus_lock(struct pci_bus *bus) | |
4396 | { | |
4397 | struct pci_dev *dev; | |
4398 | ||
4399 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4400 | pci_dev_lock(dev); | |
4401 | if (dev->subordinate) | |
4402 | pci_bus_lock(dev->subordinate); | |
4403 | } | |
4404 | } | |
4405 | ||
4406 | /* Unlock devices from the bottom of the tree up */ | |
4407 | static void pci_bus_unlock(struct pci_bus *bus) | |
4408 | { | |
4409 | struct pci_dev *dev; | |
4410 | ||
4411 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4412 | if (dev->subordinate) | |
4413 | pci_bus_unlock(dev->subordinate); | |
4414 | pci_dev_unlock(dev); | |
4415 | } | |
4416 | } | |
4417 | ||
61cf16d8 AW |
4418 | /* Return 1 on successful lock, 0 on contention */ |
4419 | static int pci_bus_trylock(struct pci_bus *bus) | |
4420 | { | |
4421 | struct pci_dev *dev; | |
4422 | ||
4423 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4424 | if (!pci_dev_trylock(dev)) | |
4425 | goto unlock; | |
4426 | if (dev->subordinate) { | |
4427 | if (!pci_bus_trylock(dev->subordinate)) { | |
4428 | pci_dev_unlock(dev); | |
4429 | goto unlock; | |
4430 | } | |
4431 | } | |
4432 | } | |
4433 | return 1; | |
4434 | ||
4435 | unlock: | |
4436 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
4437 | if (dev->subordinate) | |
4438 | pci_bus_unlock(dev->subordinate); | |
4439 | pci_dev_unlock(dev); | |
4440 | } | |
4441 | return 0; | |
4442 | } | |
4443 | ||
f331a859 AW |
4444 | /* Do any devices on or below this slot prevent a bus reset? */ |
4445 | static bool pci_slot_resetable(struct pci_slot *slot) | |
4446 | { | |
4447 | struct pci_dev *dev; | |
4448 | ||
33ba90aa JG |
4449 | if (slot->bus->self && |
4450 | (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) | |
4451 | return false; | |
4452 | ||
f331a859 AW |
4453 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { |
4454 | if (!dev->slot || dev->slot != slot) | |
4455 | continue; | |
4456 | if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || | |
4457 | (dev->subordinate && !pci_bus_resetable(dev->subordinate))) | |
4458 | return false; | |
4459 | } | |
4460 | ||
4461 | return true; | |
4462 | } | |
4463 | ||
090a3c53 AW |
4464 | /* Lock devices from the top of the tree down */ |
4465 | static void pci_slot_lock(struct pci_slot *slot) | |
4466 | { | |
4467 | struct pci_dev *dev; | |
4468 | ||
4469 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4470 | if (!dev->slot || dev->slot != slot) | |
4471 | continue; | |
4472 | pci_dev_lock(dev); | |
4473 | if (dev->subordinate) | |
4474 | pci_bus_lock(dev->subordinate); | |
4475 | } | |
4476 | } | |
4477 | ||
4478 | /* Unlock devices from the bottom of the tree up */ | |
4479 | static void pci_slot_unlock(struct pci_slot *slot) | |
4480 | { | |
4481 | struct pci_dev *dev; | |
4482 | ||
4483 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4484 | if (!dev->slot || dev->slot != slot) | |
4485 | continue; | |
4486 | if (dev->subordinate) | |
4487 | pci_bus_unlock(dev->subordinate); | |
4488 | pci_dev_unlock(dev); | |
4489 | } | |
4490 | } | |
4491 | ||
61cf16d8 AW |
4492 | /* Return 1 on successful lock, 0 on contention */ |
4493 | static int pci_slot_trylock(struct pci_slot *slot) | |
4494 | { | |
4495 | struct pci_dev *dev; | |
4496 | ||
4497 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4498 | if (!dev->slot || dev->slot != slot) | |
4499 | continue; | |
4500 | if (!pci_dev_trylock(dev)) | |
4501 | goto unlock; | |
4502 | if (dev->subordinate) { | |
4503 | if (!pci_bus_trylock(dev->subordinate)) { | |
4504 | pci_dev_unlock(dev); | |
4505 | goto unlock; | |
4506 | } | |
4507 | } | |
4508 | } | |
4509 | return 1; | |
4510 | ||
4511 | unlock: | |
4512 | list_for_each_entry_continue_reverse(dev, | |
4513 | &slot->bus->devices, bus_list) { | |
4514 | if (!dev->slot || dev->slot != slot) | |
4515 | continue; | |
4516 | if (dev->subordinate) | |
4517 | pci_bus_unlock(dev->subordinate); | |
4518 | pci_dev_unlock(dev); | |
4519 | } | |
4520 | return 0; | |
4521 | } | |
4522 | ||
090a3c53 AW |
4523 | /* Save and disable devices from the top of the tree down */ |
4524 | static void pci_bus_save_and_disable(struct pci_bus *bus) | |
4525 | { | |
4526 | struct pci_dev *dev; | |
4527 | ||
4528 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b014e96d | 4529 | pci_dev_lock(dev); |
090a3c53 | 4530 | pci_dev_save_and_disable(dev); |
b014e96d | 4531 | pci_dev_unlock(dev); |
090a3c53 AW |
4532 | if (dev->subordinate) |
4533 | pci_bus_save_and_disable(dev->subordinate); | |
4534 | } | |
4535 | } | |
4536 | ||
4537 | /* | |
4538 | * Restore devices from top of the tree down - parent bridges need to be | |
4539 | * restored before we can get to subordinate devices. | |
4540 | */ | |
4541 | static void pci_bus_restore(struct pci_bus *bus) | |
4542 | { | |
4543 | struct pci_dev *dev; | |
4544 | ||
4545 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b014e96d | 4546 | pci_dev_lock(dev); |
090a3c53 | 4547 | pci_dev_restore(dev); |
b014e96d | 4548 | pci_dev_unlock(dev); |
090a3c53 AW |
4549 | if (dev->subordinate) |
4550 | pci_bus_restore(dev->subordinate); | |
4551 | } | |
4552 | } | |
4553 | ||
4554 | /* Save and disable devices from the top of the tree down */ | |
4555 | static void pci_slot_save_and_disable(struct pci_slot *slot) | |
4556 | { | |
4557 | struct pci_dev *dev; | |
4558 | ||
4559 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4560 | if (!dev->slot || dev->slot != slot) | |
4561 | continue; | |
4562 | pci_dev_save_and_disable(dev); | |
4563 | if (dev->subordinate) | |
4564 | pci_bus_save_and_disable(dev->subordinate); | |
4565 | } | |
4566 | } | |
4567 | ||
4568 | /* | |
4569 | * Restore devices from top of the tree down - parent bridges need to be | |
4570 | * restored before we can get to subordinate devices. | |
4571 | */ | |
4572 | static void pci_slot_restore(struct pci_slot *slot) | |
4573 | { | |
4574 | struct pci_dev *dev; | |
4575 | ||
4576 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
4577 | if (!dev->slot || dev->slot != slot) | |
4578 | continue; | |
4579 | pci_dev_restore(dev); | |
4580 | if (dev->subordinate) | |
4581 | pci_bus_restore(dev->subordinate); | |
4582 | } | |
4583 | } | |
4584 | ||
4585 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
4586 | { | |
4587 | int rc; | |
4588 | ||
f331a859 | 4589 | if (!slot || !pci_slot_resetable(slot)) |
090a3c53 AW |
4590 | return -ENOTTY; |
4591 | ||
4592 | if (!probe) | |
4593 | pci_slot_lock(slot); | |
4594 | ||
4595 | might_sleep(); | |
4596 | ||
4597 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
4598 | ||
4599 | if (!probe) | |
4600 | pci_slot_unlock(slot); | |
4601 | ||
4602 | return rc; | |
4603 | } | |
4604 | ||
9a3d2b9b AW |
4605 | /** |
4606 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
4607 | * @slot: PCI slot to probe | |
4608 | * | |
4609 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
4610 | */ | |
4611 | int pci_probe_reset_slot(struct pci_slot *slot) | |
4612 | { | |
4613 | return pci_slot_reset(slot, 1); | |
4614 | } | |
4615 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
4616 | ||
090a3c53 AW |
4617 | /** |
4618 | * pci_reset_slot - reset a PCI slot | |
4619 | * @slot: PCI slot to reset | |
4620 | * | |
4621 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
4622 | * independent of other slots. For instance, some slots may support slot power | |
4623 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
4624 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
4625 | * Generally a slot reset should be attempted before a bus reset. All of the | |
4626 | * function of the slot and any subordinate buses behind the slot are reset | |
4627 | * through this function. PCI config space of all devices in the slot and | |
4628 | * behind the slot is saved before and restored after reset. | |
4629 | * | |
4630 | * Return 0 on success, non-zero on error. | |
4631 | */ | |
4632 | int pci_reset_slot(struct pci_slot *slot) | |
4633 | { | |
4634 | int rc; | |
4635 | ||
4636 | rc = pci_slot_reset(slot, 1); | |
4637 | if (rc) | |
4638 | return rc; | |
4639 | ||
4640 | pci_slot_save_and_disable(slot); | |
4641 | ||
4642 | rc = pci_slot_reset(slot, 0); | |
4643 | ||
4644 | pci_slot_restore(slot); | |
4645 | ||
4646 | return rc; | |
4647 | } | |
4648 | EXPORT_SYMBOL_GPL(pci_reset_slot); | |
4649 | ||
61cf16d8 AW |
4650 | /** |
4651 | * pci_try_reset_slot - Try to reset a PCI slot | |
4652 | * @slot: PCI slot to reset | |
4653 | * | |
4654 | * Same as above except return -EAGAIN if the slot cannot be locked | |
4655 | */ | |
4656 | int pci_try_reset_slot(struct pci_slot *slot) | |
4657 | { | |
4658 | int rc; | |
4659 | ||
4660 | rc = pci_slot_reset(slot, 1); | |
4661 | if (rc) | |
4662 | return rc; | |
4663 | ||
4664 | pci_slot_save_and_disable(slot); | |
4665 | ||
4666 | if (pci_slot_trylock(slot)) { | |
4667 | might_sleep(); | |
4668 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
4669 | pci_slot_unlock(slot); | |
4670 | } else | |
4671 | rc = -EAGAIN; | |
4672 | ||
4673 | pci_slot_restore(slot); | |
4674 | ||
4675 | return rc; | |
4676 | } | |
4677 | EXPORT_SYMBOL_GPL(pci_try_reset_slot); | |
4678 | ||
090a3c53 AW |
4679 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
4680 | { | |
f331a859 | 4681 | if (!bus->self || !pci_bus_resetable(bus)) |
090a3c53 AW |
4682 | return -ENOTTY; |
4683 | ||
4684 | if (probe) | |
4685 | return 0; | |
4686 | ||
4687 | pci_bus_lock(bus); | |
4688 | ||
4689 | might_sleep(); | |
4690 | ||
4691 | pci_reset_bridge_secondary_bus(bus->self); | |
4692 | ||
4693 | pci_bus_unlock(bus); | |
4694 | ||
4695 | return 0; | |
4696 | } | |
4697 | ||
9a3d2b9b AW |
4698 | /** |
4699 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
4700 | * @bus: PCI bus to probe | |
4701 | * | |
4702 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
4703 | */ | |
4704 | int pci_probe_reset_bus(struct pci_bus *bus) | |
4705 | { | |
4706 | return pci_bus_reset(bus, 1); | |
4707 | } | |
4708 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
4709 | ||
090a3c53 AW |
4710 | /** |
4711 | * pci_reset_bus - reset a PCI bus | |
4712 | * @bus: top level PCI bus to reset | |
4713 | * | |
4714 | * Do a bus reset on the given bus and any subordinate buses, saving | |
4715 | * and restoring state of all devices. | |
4716 | * | |
4717 | * Return 0 on success, non-zero on error. | |
4718 | */ | |
4719 | int pci_reset_bus(struct pci_bus *bus) | |
4720 | { | |
4721 | int rc; | |
4722 | ||
4723 | rc = pci_bus_reset(bus, 1); | |
4724 | if (rc) | |
4725 | return rc; | |
4726 | ||
4727 | pci_bus_save_and_disable(bus); | |
4728 | ||
4729 | rc = pci_bus_reset(bus, 0); | |
4730 | ||
4731 | pci_bus_restore(bus); | |
4732 | ||
4733 | return rc; | |
4734 | } | |
4735 | EXPORT_SYMBOL_GPL(pci_reset_bus); | |
4736 | ||
61cf16d8 AW |
4737 | /** |
4738 | * pci_try_reset_bus - Try to reset a PCI bus | |
4739 | * @bus: top level PCI bus to reset | |
4740 | * | |
4741 | * Same as above except return -EAGAIN if the bus cannot be locked | |
4742 | */ | |
4743 | int pci_try_reset_bus(struct pci_bus *bus) | |
4744 | { | |
4745 | int rc; | |
4746 | ||
4747 | rc = pci_bus_reset(bus, 1); | |
4748 | if (rc) | |
4749 | return rc; | |
4750 | ||
4751 | pci_bus_save_and_disable(bus); | |
4752 | ||
4753 | if (pci_bus_trylock(bus)) { | |
4754 | might_sleep(); | |
4755 | pci_reset_bridge_secondary_bus(bus->self); | |
4756 | pci_bus_unlock(bus); | |
4757 | } else | |
4758 | rc = -EAGAIN; | |
4759 | ||
4760 | pci_bus_restore(bus); | |
4761 | ||
4762 | return rc; | |
4763 | } | |
4764 | EXPORT_SYMBOL_GPL(pci_try_reset_bus); | |
4765 | ||
d556ad4b PO |
4766 | /** |
4767 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
4768 | * @dev: PCI device to query | |
4769 | * | |
4770 | * Returns mmrbc: maximum designed memory read count in bytes | |
4771 | * or appropriate error value. | |
4772 | */ | |
4773 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
4774 | { | |
7c9e2b1c | 4775 | int cap; |
d556ad4b PO |
4776 | u32 stat; |
4777 | ||
4778 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4779 | if (!cap) | |
4780 | return -EINVAL; | |
4781 | ||
7c9e2b1c | 4782 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
4783 | return -EINVAL; |
4784 | ||
25daeb55 | 4785 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
4786 | } |
4787 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
4788 | ||
4789 | /** | |
4790 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
4791 | * @dev: PCI device to query | |
4792 | * | |
4793 | * Returns mmrbc: maximum memory read count in bytes | |
4794 | * or appropriate error value. | |
4795 | */ | |
4796 | int pcix_get_mmrbc(struct pci_dev *dev) | |
4797 | { | |
7c9e2b1c | 4798 | int cap; |
bdc2bda7 | 4799 | u16 cmd; |
d556ad4b PO |
4800 | |
4801 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4802 | if (!cap) | |
4803 | return -EINVAL; | |
4804 | ||
7c9e2b1c DN |
4805 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4806 | return -EINVAL; | |
d556ad4b | 4807 | |
7c9e2b1c | 4808 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
4809 | } |
4810 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
4811 | ||
4812 | /** | |
4813 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
4814 | * @dev: PCI device to query | |
4815 | * @mmrbc: maximum memory read count in bytes | |
4816 | * valid values are 512, 1024, 2048, 4096 | |
4817 | * | |
4818 | * If possible sets maximum memory read byte count, some bridges have erratas | |
4819 | * that prevent this. | |
4820 | */ | |
4821 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
4822 | { | |
7c9e2b1c | 4823 | int cap; |
bdc2bda7 DN |
4824 | u32 stat, v, o; |
4825 | u16 cmd; | |
d556ad4b | 4826 | |
229f5afd | 4827 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 4828 | return -EINVAL; |
d556ad4b PO |
4829 | |
4830 | v = ffs(mmrbc) - 10; | |
4831 | ||
4832 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
4833 | if (!cap) | |
7c9e2b1c | 4834 | return -EINVAL; |
d556ad4b | 4835 | |
7c9e2b1c DN |
4836 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
4837 | return -EINVAL; | |
d556ad4b PO |
4838 | |
4839 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
4840 | return -E2BIG; | |
4841 | ||
7c9e2b1c DN |
4842 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
4843 | return -EINVAL; | |
d556ad4b PO |
4844 | |
4845 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
4846 | if (o != v) { | |
809a3bf9 | 4847 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
4848 | return -EIO; |
4849 | ||
4850 | cmd &= ~PCI_X_CMD_MAX_READ; | |
4851 | cmd |= v << 2; | |
7c9e2b1c DN |
4852 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
4853 | return -EIO; | |
d556ad4b | 4854 | } |
7c9e2b1c | 4855 | return 0; |
d556ad4b PO |
4856 | } |
4857 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
4858 | ||
4859 | /** | |
4860 | * pcie_get_readrq - get PCI Express read request size | |
4861 | * @dev: PCI device to query | |
4862 | * | |
4863 | * Returns maximum memory read request in bytes | |
4864 | * or appropriate error value. | |
4865 | */ | |
4866 | int pcie_get_readrq(struct pci_dev *dev) | |
4867 | { | |
d556ad4b PO |
4868 | u16 ctl; |
4869 | ||
59875ae4 | 4870 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 4871 | |
59875ae4 | 4872 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
4873 | } |
4874 | EXPORT_SYMBOL(pcie_get_readrq); | |
4875 | ||
4876 | /** | |
4877 | * pcie_set_readrq - set PCI Express maximum memory read request | |
4878 | * @dev: PCI device to query | |
42e61f4a | 4879 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
4880 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4881 | * | |
c9b378c7 | 4882 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
4883 | */ |
4884 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
4885 | { | |
59875ae4 | 4886 | u16 v; |
d556ad4b | 4887 | |
229f5afd | 4888 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 4889 | return -EINVAL; |
d556ad4b | 4890 | |
a1c473aa BH |
4891 | /* |
4892 | * If using the "performance" PCIe config, we clamp the | |
4893 | * read rq size to the max packet size to prevent the | |
4894 | * host bridge generating requests larger than we can | |
4895 | * cope with | |
4896 | */ | |
4897 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
4898 | int mps = pcie_get_mps(dev); | |
4899 | ||
a1c473aa BH |
4900 | if (mps < rq) |
4901 | rq = mps; | |
4902 | } | |
4903 | ||
4904 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 4905 | |
59875ae4 JL |
4906 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4907 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
4908 | } |
4909 | EXPORT_SYMBOL(pcie_set_readrq); | |
4910 | ||
b03e7495 JM |
4911 | /** |
4912 | * pcie_get_mps - get PCI Express maximum payload size | |
4913 | * @dev: PCI device to query | |
4914 | * | |
4915 | * Returns maximum payload size in bytes | |
b03e7495 JM |
4916 | */ |
4917 | int pcie_get_mps(struct pci_dev *dev) | |
4918 | { | |
b03e7495 JM |
4919 | u16 ctl; |
4920 | ||
59875ae4 | 4921 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 4922 | |
59875ae4 | 4923 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 4924 | } |
f1c66c46 | 4925 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
4926 | |
4927 | /** | |
4928 | * pcie_set_mps - set PCI Express maximum payload size | |
4929 | * @dev: PCI device to query | |
47c08f31 | 4930 | * @mps: maximum payload size in bytes |
b03e7495 JM |
4931 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4932 | * | |
4933 | * If possible sets maximum payload size | |
4934 | */ | |
4935 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
4936 | { | |
59875ae4 | 4937 | u16 v; |
b03e7495 JM |
4938 | |
4939 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 4940 | return -EINVAL; |
b03e7495 JM |
4941 | |
4942 | v = ffs(mps) - 8; | |
f7625980 | 4943 | if (v > dev->pcie_mpss) |
59875ae4 | 4944 | return -EINVAL; |
b03e7495 JM |
4945 | v <<= 5; |
4946 | ||
59875ae4 JL |
4947 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4948 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 4949 | } |
f1c66c46 | 4950 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 4951 | |
81377c8d JK |
4952 | /** |
4953 | * pcie_get_minimum_link - determine minimum link settings of a PCI device | |
4954 | * @dev: PCI device to query | |
4955 | * @speed: storage for minimum speed | |
4956 | * @width: storage for minimum width | |
4957 | * | |
4958 | * This function will walk up the PCI device chain and determine the minimum | |
4959 | * link width and speed of the device. | |
4960 | */ | |
4961 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, | |
4962 | enum pcie_link_width *width) | |
4963 | { | |
4964 | int ret; | |
4965 | ||
4966 | *speed = PCI_SPEED_UNKNOWN; | |
4967 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4968 | ||
4969 | while (dev) { | |
4970 | u16 lnksta; | |
4971 | enum pci_bus_speed next_speed; | |
4972 | enum pcie_link_width next_width; | |
4973 | ||
4974 | ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
4975 | if (ret) | |
4976 | return ret; | |
4977 | ||
4978 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
4979 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
4980 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
4981 | ||
4982 | if (next_speed < *speed) | |
4983 | *speed = next_speed; | |
4984 | ||
4985 | if (next_width < *width) | |
4986 | *width = next_width; | |
4987 | ||
4988 | dev = dev->bus->self; | |
4989 | } | |
4990 | ||
4991 | return 0; | |
4992 | } | |
4993 | EXPORT_SYMBOL(pcie_get_minimum_link); | |
4994 | ||
c87deff7 HS |
4995 | /** |
4996 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 4997 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
4998 | * @flags: resource type mask to be selected |
4999 | * | |
5000 | * This helper routine makes bar mask from the type of resource. | |
5001 | */ | |
5002 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
5003 | { | |
5004 | int i, bars = 0; | |
5005 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
5006 | if (pci_resource_flags(dev, i) & flags) | |
5007 | bars |= (1 << i); | |
5008 | return bars; | |
5009 | } | |
b7fe9434 | 5010 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 5011 | |
95a8b6ef MT |
5012 | /* Some architectures require additional programming to enable VGA */ |
5013 | static arch_set_vga_state_t arch_set_vga_state; | |
5014 | ||
5015 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
5016 | { | |
5017 | arch_set_vga_state = func; /* NULL disables */ | |
5018 | } | |
5019 | ||
5020 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
3c78bc61 | 5021 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
5022 | { |
5023 | if (arch_set_vga_state) | |
5024 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 5025 | flags); |
95a8b6ef MT |
5026 | return 0; |
5027 | } | |
5028 | ||
deb2d2ec BH |
5029 | /** |
5030 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
5031 | * @dev: the PCI device |
5032 | * @decode: true = enable decoding, false = disable decoding | |
5033 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 5034 | * @flags: traverse ancestors and change bridges |
3448a19d | 5035 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
5036 | */ |
5037 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 5038 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
5039 | { |
5040 | struct pci_bus *bus; | |
5041 | struct pci_dev *bridge; | |
5042 | u16 cmd; | |
95a8b6ef | 5043 | int rc; |
deb2d2ec | 5044 | |
67ebd814 | 5045 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 5046 | |
95a8b6ef | 5047 | /* ARCH specific VGA enables */ |
3448a19d | 5048 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
5049 | if (rc) |
5050 | return rc; | |
5051 | ||
3448a19d DA |
5052 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
5053 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
5054 | if (decode == true) | |
5055 | cmd |= command_bits; | |
5056 | else | |
5057 | cmd &= ~command_bits; | |
5058 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
5059 | } | |
deb2d2ec | 5060 | |
3448a19d | 5061 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
5062 | return 0; |
5063 | ||
5064 | bus = dev->bus; | |
5065 | while (bus) { | |
5066 | bridge = bus->self; | |
5067 | if (bridge) { | |
5068 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
5069 | &cmd); | |
5070 | if (decode == true) | |
5071 | cmd |= PCI_BRIDGE_CTL_VGA; | |
5072 | else | |
5073 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
5074 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
5075 | cmd); | |
5076 | } | |
5077 | bus = bus->parent; | |
5078 | } | |
5079 | return 0; | |
5080 | } | |
5081 | ||
f0af9593 BH |
5082 | /** |
5083 | * pci_add_dma_alias - Add a DMA devfn alias for a device | |
5084 | * @dev: the PCI device for which alias is added | |
5085 | * @devfn: alias slot and function | |
5086 | * | |
5087 | * This helper encodes 8-bit devfn as bit number in dma_alias_mask. | |
5088 | * It should be called early, preferably as PCI fixup header quirk. | |
5089 | */ | |
5090 | void pci_add_dma_alias(struct pci_dev *dev, u8 devfn) | |
5091 | { | |
338c3149 JL |
5092 | if (!dev->dma_alias_mask) |
5093 | dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX), | |
5094 | sizeof(long), GFP_KERNEL); | |
5095 | if (!dev->dma_alias_mask) { | |
5096 | dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n"); | |
5097 | return; | |
5098 | } | |
5099 | ||
5100 | set_bit(devfn, dev->dma_alias_mask); | |
48c83080 BH |
5101 | dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n", |
5102 | PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
f0af9593 BH |
5103 | } |
5104 | ||
338c3149 JL |
5105 | bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2) |
5106 | { | |
5107 | return (dev1->dma_alias_mask && | |
5108 | test_bit(dev2->devfn, dev1->dma_alias_mask)) || | |
5109 | (dev2->dma_alias_mask && | |
5110 | test_bit(dev1->devfn, dev2->dma_alias_mask)); | |
5111 | } | |
5112 | ||
8496e85c RW |
5113 | bool pci_device_is_present(struct pci_dev *pdev) |
5114 | { | |
5115 | u32 v; | |
5116 | ||
fe2bd75b KB |
5117 | if (pci_dev_is_disconnected(pdev)) |
5118 | return false; | |
8496e85c RW |
5119 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); |
5120 | } | |
5121 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
5122 | ||
08249651 RW |
5123 | void pci_ignore_hotplug(struct pci_dev *dev) |
5124 | { | |
5125 | struct pci_dev *bridge = dev->bus->self; | |
5126 | ||
5127 | dev->ignore_hotplug = 1; | |
5128 | /* Propagate the "ignore hotplug" setting to the parent bridge. */ | |
5129 | if (bridge) | |
5130 | bridge->ignore_hotplug = 1; | |
5131 | } | |
5132 | EXPORT_SYMBOL_GPL(pci_ignore_hotplug); | |
5133 | ||
0a701aa6 YX |
5134 | resource_size_t __weak pcibios_default_alignment(void) |
5135 | { | |
5136 | return 0; | |
5137 | } | |
5138 | ||
32a9a682 YS |
5139 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
5140 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 5141 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
5142 | |
5143 | /** | |
5144 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
5145 | * @dev: the PCI device to get | |
e3adec72 | 5146 | * @resize: whether or not to change resources' size when reassigning alignment |
32a9a682 YS |
5147 | * |
5148 | * RETURNS: Resource alignment if it is specified. | |
5149 | * Zero if it is not specified. | |
5150 | */ | |
e3adec72 YX |
5151 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, |
5152 | bool *resize) | |
32a9a682 YS |
5153 | { |
5154 | int seg, bus, slot, func, align_order, count; | |
644a544f | 5155 | unsigned short vendor, device, subsystem_vendor, subsystem_device; |
0a701aa6 | 5156 | resource_size_t align = pcibios_default_alignment(); |
32a9a682 YS |
5157 | char *p; |
5158 | ||
5159 | spin_lock(&resource_alignment_lock); | |
5160 | p = resource_alignment_param; | |
0a701aa6 | 5161 | if (!*p && !align) |
f0b99f70 YX |
5162 | goto out; |
5163 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
0a701aa6 | 5164 | align = 0; |
f0b99f70 YX |
5165 | pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n"); |
5166 | goto out; | |
5167 | } | |
5168 | ||
32a9a682 YS |
5169 | while (*p) { |
5170 | count = 0; | |
5171 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
5172 | p[count] == '@') { | |
5173 | p += count + 1; | |
5174 | } else { | |
5175 | align_order = -1; | |
5176 | } | |
644a544f KMEE |
5177 | if (strncmp(p, "pci:", 4) == 0) { |
5178 | /* PCI vendor/device (subvendor/subdevice) ids are specified */ | |
5179 | p += 4; | |
5180 | if (sscanf(p, "%hx:%hx:%hx:%hx%n", | |
5181 | &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) { | |
5182 | if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) { | |
5183 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n", | |
5184 | p); | |
5185 | break; | |
5186 | } | |
5187 | subsystem_vendor = subsystem_device = 0; | |
5188 | } | |
5189 | p += count; | |
5190 | if ((!vendor || (vendor == dev->vendor)) && | |
5191 | (!device || (device == dev->device)) && | |
5192 | (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) && | |
5193 | (!subsystem_device || (subsystem_device == dev->subsystem_device))) { | |
e3adec72 | 5194 | *resize = true; |
644a544f KMEE |
5195 | if (align_order == -1) |
5196 | align = PAGE_SIZE; | |
5197 | else | |
5198 | align = 1 << align_order; | |
5199 | /* Found */ | |
32a9a682 YS |
5200 | break; |
5201 | } | |
5202 | } | |
644a544f KMEE |
5203 | else { |
5204 | if (sscanf(p, "%x:%x:%x.%x%n", | |
5205 | &seg, &bus, &slot, &func, &count) != 4) { | |
5206 | seg = 0; | |
5207 | if (sscanf(p, "%x:%x.%x%n", | |
5208 | &bus, &slot, &func, &count) != 3) { | |
5209 | /* Invalid format */ | |
5210 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
5211 | p); | |
5212 | break; | |
5213 | } | |
5214 | } | |
5215 | p += count; | |
5216 | if (seg == pci_domain_nr(dev->bus) && | |
5217 | bus == dev->bus->number && | |
5218 | slot == PCI_SLOT(dev->devfn) && | |
5219 | func == PCI_FUNC(dev->devfn)) { | |
e3adec72 | 5220 | *resize = true; |
644a544f KMEE |
5221 | if (align_order == -1) |
5222 | align = PAGE_SIZE; | |
5223 | else | |
5224 | align = 1 << align_order; | |
5225 | /* Found */ | |
5226 | break; | |
5227 | } | |
32a9a682 YS |
5228 | } |
5229 | if (*p != ';' && *p != ',') { | |
5230 | /* End of param or invalid format */ | |
5231 | break; | |
5232 | } | |
5233 | p++; | |
5234 | } | |
f0b99f70 | 5235 | out: |
32a9a682 YS |
5236 | spin_unlock(&resource_alignment_lock); |
5237 | return align; | |
5238 | } | |
5239 | ||
81a5e70e | 5240 | static void pci_request_resource_alignment(struct pci_dev *dev, int bar, |
e3adec72 | 5241 | resource_size_t align, bool resize) |
81a5e70e BH |
5242 | { |
5243 | struct resource *r = &dev->resource[bar]; | |
5244 | resource_size_t size; | |
5245 | ||
5246 | if (!(r->flags & IORESOURCE_MEM)) | |
5247 | return; | |
5248 | ||
5249 | if (r->flags & IORESOURCE_PCI_FIXED) { | |
5250 | dev_info(&dev->dev, "BAR%d %pR: ignoring requested alignment %#llx\n", | |
5251 | bar, r, (unsigned long long)align); | |
5252 | return; | |
5253 | } | |
5254 | ||
5255 | size = resource_size(r); | |
0dde1c08 BH |
5256 | if (size >= align) |
5257 | return; | |
81a5e70e | 5258 | |
0dde1c08 | 5259 | /* |
e3adec72 YX |
5260 | * Increase the alignment of the resource. There are two ways we |
5261 | * can do this: | |
0dde1c08 | 5262 | * |
e3adec72 YX |
5263 | * 1) Increase the size of the resource. BARs are aligned on their |
5264 | * size, so when we reallocate space for this resource, we'll | |
5265 | * allocate it with the larger alignment. This also prevents | |
5266 | * assignment of any other BARs inside the alignment region, so | |
5267 | * if we're requesting page alignment, this means no other BARs | |
5268 | * will share the page. | |
5269 | * | |
5270 | * The disadvantage is that this makes the resource larger than | |
5271 | * the hardware BAR, which may break drivers that compute things | |
5272 | * based on the resource size, e.g., to find registers at a | |
5273 | * fixed offset before the end of the BAR. | |
5274 | * | |
5275 | * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and | |
5276 | * set r->start to the desired alignment. By itself this | |
5277 | * doesn't prevent other BARs being put inside the alignment | |
5278 | * region, but if we realign *every* resource of every device in | |
5279 | * the system, none of them will share an alignment region. | |
5280 | * | |
5281 | * When the user has requested alignment for only some devices via | |
5282 | * the "pci=resource_alignment" argument, "resize" is true and we | |
5283 | * use the first method. Otherwise we assume we're aligning all | |
5284 | * devices and we use the second. | |
0dde1c08 | 5285 | */ |
e3adec72 | 5286 | |
0dde1c08 BH |
5287 | dev_info(&dev->dev, "BAR%d %pR: requesting alignment to %#llx\n", |
5288 | bar, r, (unsigned long long)align); | |
81a5e70e | 5289 | |
e3adec72 YX |
5290 | if (resize) { |
5291 | r->start = 0; | |
5292 | r->end = align - 1; | |
5293 | } else { | |
5294 | r->flags &= ~IORESOURCE_SIZEALIGN; | |
5295 | r->flags |= IORESOURCE_STARTALIGN; | |
5296 | r->start = align; | |
5297 | r->end = r->start + size - 1; | |
5298 | } | |
0dde1c08 | 5299 | r->flags |= IORESOURCE_UNSET; |
81a5e70e BH |
5300 | } |
5301 | ||
2069ecfb YL |
5302 | /* |
5303 | * This function disables memory decoding and releases memory resources | |
5304 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
5305 | * It also rounds up size to specified alignment. | |
5306 | * Later on, the kernel will assign page-aligned memory resource back | |
5307 | * to the device. | |
5308 | */ | |
5309 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
5310 | { | |
5311 | int i; | |
5312 | struct resource *r; | |
81a5e70e | 5313 | resource_size_t align; |
2069ecfb | 5314 | u16 command; |
e3adec72 | 5315 | bool resize = false; |
2069ecfb | 5316 | |
62d9a78f YX |
5317 | /* |
5318 | * VF BARs are read-only zero according to SR-IOV spec r1.1, sec | |
5319 | * 3.4.1.11. Their resources are allocated from the space | |
5320 | * described by the VF BARx register in the PF's SR-IOV capability. | |
5321 | * We can't influence their alignment here. | |
5322 | */ | |
5323 | if (dev->is_virtfn) | |
5324 | return; | |
5325 | ||
10c463a7 | 5326 | /* check if specified PCI is target device to reassign */ |
e3adec72 | 5327 | align = pci_specified_resource_alignment(dev, &resize); |
10c463a7 | 5328 | if (!align) |
2069ecfb YL |
5329 | return; |
5330 | ||
5331 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
5332 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
5333 | dev_warn(&dev->dev, | |
5334 | "Can't reassign resources to host bridge.\n"); | |
5335 | return; | |
5336 | } | |
5337 | ||
5338 | dev_info(&dev->dev, | |
5339 | "Disabling memory decoding and releasing memory resources.\n"); | |
5340 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
5341 | command &= ~PCI_COMMAND_MEMORY; | |
5342 | pci_write_config_word(dev, PCI_COMMAND, command); | |
5343 | ||
81a5e70e | 5344 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
e3adec72 | 5345 | pci_request_resource_alignment(dev, i, align, resize); |
f0b99f70 | 5346 | |
81a5e70e BH |
5347 | /* |
5348 | * Need to disable bridge's resource window, | |
2069ecfb YL |
5349 | * to enable the kernel to reassign new resource |
5350 | * window later on. | |
5351 | */ | |
5352 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
5353 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
5354 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
5355 | r = &dev->resource[i]; | |
5356 | if (!(r->flags & IORESOURCE_MEM)) | |
5357 | continue; | |
bd064f0a | 5358 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
5359 | r->end = resource_size(r) - 1; |
5360 | r->start = 0; | |
5361 | } | |
5362 | pci_disable_bridge_window(dev); | |
5363 | } | |
5364 | } | |
5365 | ||
9738abed | 5366 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
5367 | { |
5368 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
5369 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
5370 | spin_lock(&resource_alignment_lock); | |
5371 | strncpy(resource_alignment_param, buf, count); | |
5372 | resource_alignment_param[count] = '\0'; | |
5373 | spin_unlock(&resource_alignment_lock); | |
5374 | return count; | |
5375 | } | |
5376 | ||
9738abed | 5377 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
5378 | { |
5379 | size_t count; | |
5380 | spin_lock(&resource_alignment_lock); | |
5381 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
5382 | spin_unlock(&resource_alignment_lock); | |
5383 | return count; | |
5384 | } | |
5385 | ||
5386 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
5387 | { | |
5388 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
5389 | } | |
5390 | ||
5391 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
5392 | const char *buf, size_t count) | |
5393 | { | |
5394 | return pci_set_resource_alignment_param(buf, count); | |
5395 | } | |
5396 | ||
21751a9a | 5397 | static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, |
32a9a682 YS |
5398 | pci_resource_alignment_store); |
5399 | ||
5400 | static int __init pci_resource_alignment_sysfs_init(void) | |
5401 | { | |
5402 | return bus_create_file(&pci_bus_type, | |
5403 | &bus_attr_resource_alignment); | |
5404 | } | |
32a9a682 YS |
5405 | late_initcall(pci_resource_alignment_sysfs_init); |
5406 | ||
15856ad5 | 5407 | static void pci_no_domains(void) |
32a2eea7 JG |
5408 | { |
5409 | #ifdef CONFIG_PCI_DOMAINS | |
5410 | pci_domains_supported = 0; | |
5411 | #endif | |
5412 | } | |
5413 | ||
41e5c0f8 LD |
5414 | #ifdef CONFIG_PCI_DOMAINS |
5415 | static atomic_t __domain_nr = ATOMIC_INIT(-1); | |
5416 | ||
5417 | int pci_get_new_domain_nr(void) | |
5418 | { | |
5419 | return atomic_inc_return(&__domain_nr); | |
5420 | } | |
7c674700 LP |
5421 | |
5422 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
1a4f93f7 | 5423 | static int of_pci_bus_find_domain_nr(struct device *parent) |
7c674700 LP |
5424 | { |
5425 | static int use_dt_domains = -1; | |
54c6e2dd | 5426 | int domain = -1; |
7c674700 | 5427 | |
54c6e2dd KHC |
5428 | if (parent) |
5429 | domain = of_get_pci_domain_nr(parent->of_node); | |
7c674700 LP |
5430 | /* |
5431 | * Check DT domain and use_dt_domains values. | |
5432 | * | |
5433 | * If DT domain property is valid (domain >= 0) and | |
5434 | * use_dt_domains != 0, the DT assignment is valid since this means | |
5435 | * we have not previously allocated a domain number by using | |
5436 | * pci_get_new_domain_nr(); we should also update use_dt_domains to | |
5437 | * 1, to indicate that we have just assigned a domain number from | |
5438 | * DT. | |
5439 | * | |
5440 | * If DT domain property value is not valid (ie domain < 0), and we | |
5441 | * have not previously assigned a domain number from DT | |
5442 | * (use_dt_domains != 1) we should assign a domain number by | |
5443 | * using the: | |
5444 | * | |
5445 | * pci_get_new_domain_nr() | |
5446 | * | |
5447 | * API and update the use_dt_domains value to keep track of method we | |
5448 | * are using to assign domain numbers (use_dt_domains = 0). | |
5449 | * | |
5450 | * All other combinations imply we have a platform that is trying | |
5451 | * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), | |
5452 | * which is a recipe for domain mishandling and it is prevented by | |
5453 | * invalidating the domain value (domain = -1) and printing a | |
5454 | * corresponding error. | |
5455 | */ | |
5456 | if (domain >= 0 && use_dt_domains) { | |
5457 | use_dt_domains = 1; | |
5458 | } else if (domain < 0 && use_dt_domains != 1) { | |
5459 | use_dt_domains = 0; | |
5460 | domain = pci_get_new_domain_nr(); | |
5461 | } else { | |
b63773a8 RH |
5462 | dev_err(parent, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n", |
5463 | parent->of_node); | |
7c674700 LP |
5464 | domain = -1; |
5465 | } | |
5466 | ||
9c7cb891 | 5467 | return domain; |
7c674700 | 5468 | } |
1a4f93f7 TN |
5469 | |
5470 | int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) | |
5471 | { | |
2ab51dde TN |
5472 | return acpi_disabled ? of_pci_bus_find_domain_nr(parent) : |
5473 | acpi_pci_bus_find_domain_nr(bus); | |
7c674700 LP |
5474 | } |
5475 | #endif | |
41e5c0f8 LD |
5476 | #endif |
5477 | ||
0ef5f8f6 | 5478 | /** |
642c92da | 5479 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
5480 | * |
5481 | * Returns 1 if we can access PCI extended config space (offsets | |
5482 | * greater than 0xff). This is the default implementation. Architecture | |
5483 | * implementations can override this. | |
5484 | */ | |
642c92da | 5485 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
5486 | { |
5487 | return 1; | |
5488 | } | |
5489 | ||
2d1c8618 BH |
5490 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
5491 | { | |
5492 | } | |
5493 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
5494 | ||
ad04d31e | 5495 | static int __init pci_setup(char *str) |
1da177e4 LT |
5496 | { |
5497 | while (str) { | |
5498 | char *k = strchr(str, ','); | |
5499 | if (k) | |
5500 | *k++ = 0; | |
5501 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
5502 | if (!strcmp(str, "nomsi")) { |
5503 | pci_no_msi(); | |
7f785763 RD |
5504 | } else if (!strcmp(str, "noaer")) { |
5505 | pci_no_aer(); | |
b55438fd YL |
5506 | } else if (!strncmp(str, "realloc=", 8)) { |
5507 | pci_realloc_get_opt(str + 8); | |
f483d392 | 5508 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 5509 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
5510 | } else if (!strcmp(str, "nodomains")) { |
5511 | pci_no_domains(); | |
6748dcc2 RW |
5512 | } else if (!strncmp(str, "noari", 5)) { |
5513 | pcie_ari_disabled = true; | |
4516a618 AN |
5514 | } else if (!strncmp(str, "cbiosize=", 9)) { |
5515 | pci_cardbus_io_size = memparse(str + 9, &str); | |
5516 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
5517 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
5518 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
5519 | pci_set_resource_alignment_param(str + 19, | |
5520 | strlen(str + 19)); | |
43c16408 AP |
5521 | } else if (!strncmp(str, "ecrc=", 5)) { |
5522 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
5523 | } else if (!strncmp(str, "hpiosize=", 9)) { |
5524 | pci_hotplug_io_size = memparse(str + 9, &str); | |
5525 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
5526 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
e16b4660 KB |
5527 | } else if (!strncmp(str, "hpbussize=", 10)) { |
5528 | pci_hotplug_bus_size = | |
5529 | simple_strtoul(str + 10, &str, 0); | |
5530 | if (pci_hotplug_bus_size > 0xff) | |
5531 | pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE; | |
5f39e670 JM |
5532 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
5533 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
5534 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
5535 | pcie_bus_config = PCIE_BUS_SAFE; | |
5536 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
5537 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
5538 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
5539 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
5540 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
5541 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
5542 | } else { |
5543 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
5544 | str); | |
5545 | } | |
1da177e4 LT |
5546 | } |
5547 | str = k; | |
5548 | } | |
0637a70a | 5549 | return 0; |
1da177e4 | 5550 | } |
0637a70a | 5551 | early_param("pci", pci_setup); |