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PCI/PM: add PCIe runtime D3cold support
[mirror_ubuntu-zesty-kernel.git] / drivers / pci / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
075c1771 14#include <linux/pm.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
229f5afd 19#include <linux/log2.h>
7d715a6c 20#include <linux/pci-aspm.h>
c300bd2f 21#include <linux/pm_wakeup.h>
8dd7f803 22#include <linux/interrupt.h>
32a9a682 23#include <linux/device.h>
b67ea761 24#include <linux/pm_runtime.h>
284f5f9d 25#include <asm-generic/pci-bridge.h>
32a9a682 26#include <asm/setup.h>
bc56b9e0 27#include "pci.h"
1da177e4 28
00240c38
AS		 29const char *pci_power_names[] = {
30 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31};
32EXPORT_SYMBOL_GPL(pci_power_names);
33
93177a74
RW		 34int isa_dma_bridge_buggy;
35EXPORT_SYMBOL(isa_dma_bridge_buggy);
36
37int pci_pci_problems;
38EXPORT_SYMBOL(pci_pci_problems);
39
1ae861e6
RW		 40unsigned int pci_pm_d3_delay;
41
df17e62e
MG		 42static void pci_pme_list_scan(struct work_struct *work);
43
44static LIST_HEAD(pci_pme_list);
45static DEFINE_MUTEX(pci_pme_list_mutex);
46static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47
48struct pci_pme_device {
49 struct list_head list;
50 struct pci_dev *dev;
51};
52
53#define PME_TIMEOUT 1000 /* How long between PME checks */
54
1ae861e6
RW		 55static void pci_dev_d3_sleep(struct pci_dev *dev)
56{
57 unsigned int delay = dev->d3_delay;
58
59 if (delay < pci_pm_d3_delay)
60 delay = pci_pm_d3_delay;
61
62 msleep(delay);
63}
1da177e4 64
32a2eea7
JG		 65#ifdef CONFIG_PCI_DOMAINS
66int pci_domains_supported = 1;
67#endif
68
4516a618
AN		 69#define DEFAULT_CARDBUS_IO_SIZE (256)
70#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
71/* pci=cbmemsize=nnM,cbiosize=nn can override this */
72unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
73unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74
28760489
EB		 75#define DEFAULT_HOTPLUG_IO_SIZE (256)
76#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
77/* pci=hpmemsize=nnM,hpiosize=nn can override this */
78unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
79unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
80
5f39e670 81enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495 82
ac1aa47b
JB		 83/*
84 * The default CLS is used if arch didn't set CLS explicitly and not
85 * all pci devices agree on the same value. Arch can override either
86 * the dfl or actual value as it sees fit. Don't forget this is
87 * measured in 32-bit words, not bytes.
88 */
98e724c7 89u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
ac1aa47b
JB		 90u8 pci_cache_line_size;
91
96c55900
MS		 92/*
93 * If we set up a device for bus mastering, we need to check the latency
94 * timer as certain BIOSes forget to set it properly.
95 */
96unsigned int pcibios_max_latency = 255;
97
6748dcc2
RW		 98/* If set, the PCIe ARI capability will not be used. */
99static bool pcie_ari_disabled;
100
1da177e4
LT		 101/**
102 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
103 * @bus: pointer to PCI bus structure to search
104 *
105 * Given a PCI bus, returns the highest PCI bus number present in the set
106 * including the given PCI bus and its list of child PCI buses.
107 */
96bde06a 108unsigned char pci_bus_max_busnr(struct pci_bus* bus)
1da177e4
LT		 109{
110 struct list_head *tmp;
111 unsigned char max, n;
112
b82db5ce 113 max = bus->subordinate;
1da177e4
LT		 114 list_for_each(tmp, &bus->children) {
115 n = pci_bus_max_busnr(pci_bus_b(tmp));
116 if(n > max)
117 max = n;
118 }
119 return max;
120}
b82db5ce 121EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 122
1684f5dd
AM		 123#ifdef CONFIG_HAS_IOMEM
124void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
125{
126 /*
127 * Make sure the BAR is actually a memory resource, not an IO resource
128 */
129 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
130 WARN_ON(1);
131 return NULL;
132 }
133 return ioremap_nocache(pci_resource_start(pdev, bar),
134 pci_resource_len(pdev, bar));
135}
136EXPORT_SYMBOL_GPL(pci_ioremap_bar);
137#endif
138
b82db5ce 139#if 0
1da177e4
LT		 140/**
141 * pci_max_busnr - returns maximum PCI bus number
142 *
143 * Returns the highest PCI bus number present in the system global list of
144 * PCI buses.
145 */
146unsigned char __devinit
147pci_max_busnr(void)
148{
149 struct pci_bus *bus = NULL;
150 unsigned char max, n;
151
152 max = 0;
153 while ((bus = pci_find_next_bus(bus)) != NULL) {
154 n = pci_bus_max_busnr(bus);
155 if(n > max)
156 max = n;
157 }
158 return max;
159}
160
54c762fe
AB		 161#endif /* 0 */
162
687d5fe3
ME		 163#define PCI_FIND_CAP_TTL 48
164
165static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
166 u8 pos, int cap, int *ttl)
24a4e377
RD		 167{
168 u8 id;
24a4e377 169
687d5fe3 170 while ((*ttl)--) {
24a4e377
RD		 171 pci_bus_read_config_byte(bus, devfn, pos, &pos);
172 if (pos < 0x40)
173 break;
174 pos &= ~3;
175 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
176 &id);
177 if (id == 0xff)
178 break;
179 if (id == cap)
180 return pos;
181 pos += PCI_CAP_LIST_NEXT;
182 }
183 return 0;
184}
185
687d5fe3
ME		 186static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
187 u8 pos, int cap)
188{
189 int ttl = PCI_FIND_CAP_TTL;
190
191 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
192}
193
24a4e377
RD		 194int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
195{
196 return __pci_find_next_cap(dev->bus, dev->devfn,
197 pos + PCI_CAP_LIST_NEXT, cap);
198}
199EXPORT_SYMBOL_GPL(pci_find_next_capability);
200
d3bac118
ME		 201static int __pci_bus_find_cap_start(struct pci_bus *bus,
202 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 203{
204 u16 status;
1da177e4
LT		 205
206 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
207 if (!(status & PCI_STATUS_CAP_LIST))
208 return 0;
209
210 switch (hdr_type) {
211 case PCI_HEADER_TYPE_NORMAL:
212 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 213 return PCI_CAPABILITY_LIST;
1da177e4 214 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 215 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 216 default:
217 return 0;
218 }
d3bac118
ME		 219
220 return 0;
1da177e4
LT		 221}
222
223/**
224 * pci_find_capability - query for devices' capabilities
225 * @dev: PCI device to query
226 * @cap: capability code
227 *
228 * Tell if a device supports a given PCI capability.
229 * Returns the address of the requested capability structure within the
230 * device's PCI configuration space or 0 in case the device does not
231 * support it. Possible values for @cap:
232 *
233 * %PCI_CAP_ID_PM Power Management
234 * %PCI_CAP_ID_AGP Accelerated Graphics Port
235 * %PCI_CAP_ID_VPD Vital Product Data
236 * %PCI_CAP_ID_SLOTID Slot Identification
237 * %PCI_CAP_ID_MSI Message Signalled Interrupts
238 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
239 * %PCI_CAP_ID_PCIX PCI-X
240 * %PCI_CAP_ID_EXP PCI Express
241 */
242int pci_find_capability(struct pci_dev *dev, int cap)
243{
d3bac118
ME		 244 int pos;
245
246 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
247 if (pos)
248 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
249
250 return pos;
1da177e4
LT		 251}
252
253/**
254 * pci_bus_find_capability - query for devices' capabilities
255 * @bus: the PCI bus to query
256 * @devfn: PCI device to query
257 * @cap: capability code
258 *
259 * Like pci_find_capability() but works for pci devices that do not have a
260 * pci_dev structure set up yet.
261 *
262 * Returns the address of the requested capability structure within the
263 * device's PCI configuration space or 0 in case the device does not
264 * support it.
265 */
266int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
267{
d3bac118 268 int pos;
1da177e4
LT		 269 u8 hdr_type;
270
271 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
272
d3bac118
ME		 273 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
274 if (pos)
275 pos = __pci_find_next_cap(bus, devfn, pos, cap);
276
277 return pos;
1da177e4
LT		 278}
279
280/**
281 * pci_find_ext_capability - Find an extended capability
282 * @dev: PCI device to query
283 * @cap: capability code
284 *
285 * Returns the address of the requested extended capability structure
286 * within the device's PCI configuration space or 0 if the device does
287 * not support it. Possible values for @cap:
288 *
289 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
290 * %PCI_EXT_CAP_ID_VC Virtual Channel
291 * %PCI_EXT_CAP_ID_DSN Device Serial Number
292 * %PCI_EXT_CAP_ID_PWR Power Budgeting
293 */
294int pci_find_ext_capability(struct pci_dev *dev, int cap)
295{
296 u32 header;
557848c3
ZY		 297 int ttl;
298 int pos = PCI_CFG_SPACE_SIZE;
1da177e4 299
557848c3
ZY		 300 /* minimum 8 bytes per capability */
301 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
302
303 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
1da177e4
LT		 304 return 0;
305
306 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
307 return 0;
308
309 /*
310 * If we have no capabilities, this is indicated by cap ID,
311 * cap version and next pointer all being 0.
312 */
313 if (header == 0)
314 return 0;
315
316 while (ttl-- > 0) {
317 if (PCI_EXT_CAP_ID(header) == cap)
318 return pos;
319
320 pos = PCI_EXT_CAP_NEXT(header);
557848c3 321 if (pos < PCI_CFG_SPACE_SIZE)
1da177e4
LT		 322 break;
323
324 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
325 break;
326 }
327
328 return 0;
329}
3a720d72 330EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 331
cf4c43dd
JB		 332/**
333 * pci_bus_find_ext_capability - find an extended capability
334 * @bus: the PCI bus to query
335 * @devfn: PCI device to query
336 * @cap: capability code
337 *
338 * Like pci_find_ext_capability() but works for pci devices that do not have a
339 * pci_dev structure set up yet.
340 *
341 * Returns the address of the requested capability structure within the
342 * device's PCI configuration space or 0 in case the device does not
343 * support it.
344 */
345int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
346 int cap)
347{
348 u32 header;
349 int ttl;
350 int pos = PCI_CFG_SPACE_SIZE;
351
352 /* minimum 8 bytes per capability */
353 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
354
355 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
356 return 0;
357 if (header == 0xffffffff || header == 0)
358 return 0;
359
360 while (ttl-- > 0) {
361 if (PCI_EXT_CAP_ID(header) == cap)
362 return pos;
363
364 pos = PCI_EXT_CAP_NEXT(header);
365 if (pos < PCI_CFG_SPACE_SIZE)
366 break;
367
368 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
369 break;
370 }
371
372 return 0;
373}
374
687d5fe3
ME		 375static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
376{
377 int rc, ttl = PCI_FIND_CAP_TTL;
378 u8 cap, mask;
379
380 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
381 mask = HT_3BIT_CAP_MASK;
382 else
383 mask = HT_5BIT_CAP_MASK;
384
385 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
386 PCI_CAP_ID_HT, &ttl);
387 while (pos) {
388 rc = pci_read_config_byte(dev, pos + 3, &cap);
389 if (rc != PCIBIOS_SUCCESSFUL)
390 return 0;
391
392 if ((cap & mask) == ht_cap)
393 return pos;
394
47a4d5be
BG		 395 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
396 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 397 PCI_CAP_ID_HT, &ttl);
398 }
399
400 return 0;
401}
402/**
403 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
404 * @dev: PCI device to query
405 * @pos: Position from which to continue searching
406 * @ht_cap: Hypertransport capability code
407 *
408 * To be used in conjunction with pci_find_ht_capability() to search for
409 * all capabilities matching @ht_cap. @pos should always be a value returned
410 * from pci_find_ht_capability().
411 *
412 * NB. To be 100% safe against broken PCI devices, the caller should take
413 * steps to avoid an infinite loop.
414 */
415int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
416{
417 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
418}
419EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
420
421/**
422 * pci_find_ht_capability - query a device's Hypertransport capabilities
423 * @dev: PCI device to query
424 * @ht_cap: Hypertransport capability code
425 *
426 * Tell if a device supports a given Hypertransport capability.
427 * Returns an address within the device's PCI configuration space
428 * or 0 in case the device does not support the request capability.
429 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
430 * which has a Hypertransport capability matching @ht_cap.
431 */
432int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
433{
434 int pos;
435
436 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
437 if (pos)
438 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
439
440 return pos;
441}
442EXPORT_SYMBOL_GPL(pci_find_ht_capability);
443
1da177e4
LT		 444/**
445 * pci_find_parent_resource - return resource region of parent bus of given region
446 * @dev: PCI device structure contains resources to be searched
447 * @res: child resource record for which parent is sought
448 *
449 * For given resource region of given device, return the resource
450 * region of parent bus the given region is contained in or where
451 * it should be allocated from.
452 */
453struct resource *
454pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
455{
456 const struct pci_bus *bus = dev->bus;
457 int i;
89a74ecc 458 struct resource *best = NULL, *r;
1da177e4 459
89a74ecc 460 pci_bus_for_each_resource(bus, r, i) {
1da177e4
LT		 461 if (!r)
462 continue;
463 if (res->start && !(res->start >= r->start && res->end <= r->end))
464 continue; /* Not contained */
465 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
466 continue; /* Wrong type */
467 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
468 return r; /* Exact match */
8c8def26
LT		 469 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
470 if (r->flags & IORESOURCE_PREFETCH)
471 continue;
472 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
473 if (!best)
474 best = r;
1da177e4
LT		 475 }
476 return best;
477}
478
064b53db
JL		 479/**
480 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
481 * @dev: PCI device to have its BARs restored
482 *
483 * Restore the BAR values for a given device, so as to make it
484 * accessible by its driver.
485 */
ad668599 486static void
064b53db
JL		 487pci_restore_bars(struct pci_dev *dev)
488{
bc5f5a82 489 int i;
064b53db 490
bc5f5a82 491 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
14add80b 492 pci_update_resource(dev, i);
064b53db
JL		 493}
494
961d9120
RW		 495static struct pci_platform_pm_ops *pci_platform_pm;
496
497int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
498{
eb9d0fe4
RW		 499 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
500 || !ops->sleep_wake || !ops->can_wakeup)
961d9120
RW		 501 return -EINVAL;
502 pci_platform_pm = ops;
503 return 0;
504}
505
506static inline bool platform_pci_power_manageable(struct pci_dev *dev)
507{
508 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
509}
510
511static inline int platform_pci_set_power_state(struct pci_dev *dev,
512 pci_power_t t)
513{
514 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
515}
516
517static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
518{
519 return pci_platform_pm ?
520 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
521}
8f7020d3 522
eb9d0fe4
RW		 523static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
524{
525 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
526}
527
528static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
529{
530 return pci_platform_pm ?
531 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
532}
533
b67ea761
RW		 534static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
535{
536 return pci_platform_pm ?
537 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
538}
539
1da177e4 540/**
44e4e66e
RW		 541 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
542 * given PCI device
543 * @dev: PCI device to handle.
44e4e66e 544 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1da177e4 545 *
44e4e66e
RW		 546 * RETURN VALUE:
547 * -EINVAL if the requested state is invalid.
548 * -EIO if device does not support PCI PM or its PM capabilities register has a
549 * wrong version, or device doesn't support the requested state.
550 * 0 if device already is in the requested state.
551 * 0 if device's power state has been successfully changed.
1da177e4 552 */
f00a20ef 553static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1da177e4 554{
337001b6 555 u16 pmcsr;
44e4e66e 556 bool need_restore = false;
1da177e4 557
4a865905
RW		 558 /* Check if we're already there */
559 if (dev->current_state == state)
560 return 0;
561
337001b6 562 if (!dev->pm_cap)
cca03dec
AL		 563 return -EIO;
564
44e4e66e
RW		 565 if (state < PCI_D0 || state > PCI_D3hot)
566 return -EINVAL;
567
1da177e4
LT		 568 /* Validate current state:
569 * Can enter D0 from any state, but if we can only go deeper
570 * to sleep if we're already in a low power state
571 */
4a865905 572 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
44e4e66e 573 && dev->current_state > state) {
80ccba11
BH		 574 dev_err(&dev->dev, "invalid power transition "
575 "(from state %d to %d)\n", dev->current_state, state);
1da177e4 576 return -EINVAL;
44e4e66e 577 }
1da177e4 578
1da177e4 579 /* check if this device supports the desired state */
337001b6
RW		 580 if ((state == PCI_D1 && !dev->d1_support)
581 || (state == PCI_D2 && !dev->d2_support))
3fe9d19f 582 return -EIO;
1da177e4 583
337001b6 584 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
064b53db 585
32a36585 586 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 587 * This doesn't affect PME_Status, disables PME_En, and
588 * sets PowerState to 0.
589 */
32a36585 590 switch (dev->current_state) {
d3535fbb
JL		 591 case PCI_D0:
592 case PCI_D1:
593 case PCI_D2:
594 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
595 pmcsr |= state;
596 break;
f62795f1
RW		 597 case PCI_D3hot:
598 case PCI_D3cold:
32a36585
JL		 599 case PCI_UNKNOWN: /* Boot-up */
600 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
f00a20ef 601 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
44e4e66e 602 need_restore = true;
32a36585 603 /* Fall-through: force to D0 */
32a36585 604 default:
d3535fbb 605 pmcsr = 0;
32a36585 606 break;
1da177e4
LT		 607 }
608
609 /* enter specified state */
337001b6 610 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1da177e4
LT		 611
612 /* Mandatory power management transition delays */
613 /* see PCI PM 1.1 5.6.1 table 18 */
614 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1ae861e6 615 pci_dev_d3_sleep(dev);
1da177e4 616 else if (state == PCI_D2 || dev->current_state == PCI_D2)
aa8c6c93 617 udelay(PCI_PM_D2_DELAY);
1da177e4 618
e13cdbd7
RW		 619 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
620 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
621 if (dev->current_state != state && printk_ratelimit())
622 dev_info(&dev->dev, "Refused to change power state, "
623 "currently in D%d\n", dev->current_state);
064b53db 624
448bd857
HY		 625 /*
626 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
064b53db
JL		 627 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
628 * from D3hot to D0 _may_ perform an internal reset, thereby
629 * going to "D0 Uninitialized" rather than "D0 Initialized".
630 * For example, at least some versions of the 3c905B and the
631 * 3c556B exhibit this behaviour.
632 *
633 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
634 * devices in a D3hot state at boot. Consequently, we need to
635 * restore at least the BARs so that the device will be
636 * accessible to its driver.
637 */
638 if (need_restore)
639 pci_restore_bars(dev);
640
f00a20ef 641 if (dev->bus->self)
7d715a6c
SL		 642 pcie_aspm_pm_state_change(dev->bus->self);
643
1da177e4
LT		 644 return 0;
645}
646
44e4e66e
RW		 647/**
648 * pci_update_current_state - Read PCI power state of given device from its
649 * PCI PM registers and cache it
650 * @dev: PCI device to handle.
f06fc0b6 651 * @state: State to cache in case the device doesn't have the PM capability
44e4e66e 652 */
73410429 653void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
44e4e66e 654{
337001b6 655 if (dev->pm_cap) {
44e4e66e
RW		 656 u16 pmcsr;
657
448bd857
HY		 658 /*
659 * Configuration space is not accessible for device in
660 * D3cold, so just keep or set D3cold for safety
661 */
662 if (dev->current_state == PCI_D3cold)
663 return;
664 if (state == PCI_D3cold) {
665 dev->current_state = PCI_D3cold;
666 return;
667 }
337001b6 668 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
44e4e66e 669 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
f06fc0b6
RW		 670 } else {
671 dev->current_state = state;
44e4e66e
RW		 672 }
673}
674
0e5dd46b
RW		 675/**
676 * pci_platform_power_transition - Use platform to change device power state
677 * @dev: PCI device to handle.
678 * @state: State to put the device into.
679 */
680static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
681{
682 int error;
683
684 if (platform_pci_power_manageable(dev)) {
685 error = platform_pci_set_power_state(dev, state);
686 if (!error)
687 pci_update_current_state(dev, state);
b51306c6
AH		 688 /* Fall back to PCI_D0 if native PM is not supported */
689 if (!dev->pm_cap)
690 dev->current_state = PCI_D0;
0e5dd46b
RW		 691 } else {
692 error = -ENODEV;
693 /* Fall back to PCI_D0 if native PM is not supported */
b3bad72e
RW		 694 if (!dev->pm_cap)
695 dev->current_state = PCI_D0;
0e5dd46b
RW		 696 }
697
698 return error;
699}
700
701/**
702 * __pci_start_power_transition - Start power transition of a PCI device
703 * @dev: PCI device to handle.
704 * @state: State to put the device into.
705 */
706static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
707{
448bd857 708 if (state == PCI_D0) {
0e5dd46b 709 pci_platform_power_transition(dev, PCI_D0);
448bd857
HY		 710 /*
711 * Mandatory power management transition delays, see
712 * PCI Express Base Specification Revision 2.0 Section
713 * 6.6.1: Conventional Reset. Do not delay for
714 * devices powered on/off by corresponding bridge,
715 * because have already delayed for the bridge.
716 */
717 if (dev->runtime_d3cold) {
718 msleep(dev->d3cold_delay);
719 /*
720 * When powering on a bridge from D3cold, the
721 * whole hierarchy may be powered on into
722 * D0uninitialized state, resume them to give
723 * them a chance to suspend again
724 */
725 pci_wakeup_bus(dev->subordinate);
726 }
727 }
728}
729
730/**
731 * __pci_dev_set_current_state - Set current state of a PCI device
732 * @dev: Device to handle
733 * @data: pointer to state to be set
734 */
735static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
736{
737 pci_power_t state = *(pci_power_t *)data;
738
739 dev->current_state = state;
740 return 0;
741}
742
743/**
744 * __pci_bus_set_current_state - Walk given bus and set current state of devices
745 * @bus: Top bus of the subtree to walk.
746 * @state: state to be set
747 */
748static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
749{
750 if (bus)
751 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
0e5dd46b
RW		 752}
753
754/**
755 * __pci_complete_power_transition - Complete power transition of a PCI device
756 * @dev: PCI device to handle.
757 * @state: State to put the device into.
758 *
759 * This function should not be called directly by device drivers.
760 */
761int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
762{
448bd857
HY		 763 int ret;
764
765 if (state < PCI_D0)
766 return -EINVAL;
767 ret = pci_platform_power_transition(dev, state);
768 /* Power off the bridge may power off the whole hierarchy */
769 if (!ret && state == PCI_D3cold)
770 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
771 return ret;
0e5dd46b
RW		 772}
773EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
774
44e4e66e
RW		 775/**
776 * pci_set_power_state - Set the power state of a PCI device
777 * @dev: PCI device to handle.
778 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
779 *
877d0310 780 * Transition a device to a new power state, using the platform firmware and/or
44e4e66e
RW		 781 * the device's PCI PM registers.
782 *
783 * RETURN VALUE:
784 * -EINVAL if the requested state is invalid.
785 * -EIO if device does not support PCI PM or its PM capabilities register has a
786 * wrong version, or device doesn't support the requested state.
787 * 0 if device already is in the requested state.
788 * 0 if device's power state has been successfully changed.
789 */
790int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
791{
337001b6 792 int error;
44e4e66e
RW		 793
794 /* bound the state we're entering */
448bd857
HY		 795 if (state > PCI_D3cold)
796 state = PCI_D3cold;
44e4e66e
RW		 797 else if (state < PCI_D0)
798 state = PCI_D0;
799 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
800 /*
801 * If the device or the parent bridge do not support PCI PM,
802 * ignore the request if we're doing anything other than putting
803 * it into D0 (which would only happen on boot).
804 */
805 return 0;
806
0e5dd46b
RW		 807 __pci_start_power_transition(dev, state);
808
979b1791
AC		 809 /* This device is quirked not to be put into D3, so
810 don't put it in D3 */
448bd857 811 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
979b1791 812 return 0;
44e4e66e 813
448bd857
HY		 814 /*
815 * To put device in D3cold, we put device into D3hot in native
816 * way, then put device into D3cold with platform ops
817 */
818 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
819 PCI_D3hot : state);
44e4e66e 820
0e5dd46b
RW		 821 if (!__pci_complete_power_transition(dev, state))
822 error = 0;
1a680b7c
NC		 823 /*
824 * When aspm_policy is "powersave" this call ensures
825 * that ASPM is configured.
826 */
827 if (!error && dev->bus->self)
828 pcie_aspm_powersave_config_link(dev->bus->self);
44e4e66e
RW		 829
830 return error;
831}
832
1da177e4
LT		 833/**
834 * pci_choose_state - Choose the power state of a PCI device
835 * @dev: PCI device to be suspended
836 * @state: target sleep state for the whole system. This is the value
837 * that is passed to suspend() function.
838 *
839 * Returns PCI power state suitable for given device and given system
840 * message.
841 */
842
843pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
844{
ab826ca4 845 pci_power_t ret;
0f64474b 846
1da177e4
LT		 847 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
848 return PCI_D0;
849
961d9120
RW		 850 ret = platform_pci_choose_state(dev);
851 if (ret != PCI_POWER_ERROR)
852 return ret;
ca078bae
PM		 853
854 switch (state.event) {
855 case PM_EVENT_ON:
856 return PCI_D0;
857 case PM_EVENT_FREEZE:
b887d2e6
DB		 858 case PM_EVENT_PRETHAW:
859 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae 860 case PM_EVENT_SUSPEND:
3a2d5b70 861 case PM_EVENT_HIBERNATE:
ca078bae 862 return PCI_D3hot;
1da177e4 863 default:
80ccba11
BH		 864 dev_info(&dev->dev, "unrecognized suspend event %d\n",
865 state.event);
1da177e4
LT		 866 BUG();
867 }
868 return PCI_D0;
869}
870
871EXPORT_SYMBOL(pci_choose_state);
872
89858517
YZ		 873#define PCI_EXP_SAVE_REGS 7
874
1b6b8ce2
YZ		 875#define pcie_cap_has_devctl(type, flags) 1
876#define pcie_cap_has_lnkctl(type, flags) \
877 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
878 (type == PCI_EXP_TYPE_ROOT_PORT || \
879 type == PCI_EXP_TYPE_ENDPOINT || \
880 type == PCI_EXP_TYPE_LEG_END))
881#define pcie_cap_has_sltctl(type, flags) \
882 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
883 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
884 (type == PCI_EXP_TYPE_DOWNSTREAM && \
885 (flags & PCI_EXP_FLAGS_SLOT))))
886#define pcie_cap_has_rtctl(type, flags) \
887 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
888 (type == PCI_EXP_TYPE_ROOT_PORT || \
889 type == PCI_EXP_TYPE_RC_EC))
890#define pcie_cap_has_devctl2(type, flags) \
891 ((flags & PCI_EXP_FLAGS_VERS) > 1)
892#define pcie_cap_has_lnkctl2(type, flags) \
893 ((flags & PCI_EXP_FLAGS_VERS) > 1)
894#define pcie_cap_has_sltctl2(type, flags) \
895 ((flags & PCI_EXP_FLAGS_VERS) > 1)
896
34a4876e
YL		 897static struct pci_cap_saved_state *pci_find_saved_cap(
898 struct pci_dev *pci_dev, char cap)
899{
900 struct pci_cap_saved_state *tmp;
901 struct hlist_node *pos;
902
903 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
904 if (tmp->cap.cap_nr == cap)
905 return tmp;
906 }
907 return NULL;
908}
909
b56a5a23
MT		 910static int pci_save_pcie_state(struct pci_dev *dev)
911{
912 int pos, i = 0;
913 struct pci_cap_saved_state *save_state;
914 u16 *cap;
1b6b8ce2 915 u16 flags;
b56a5a23 916
06a1cbaf
KK		 917 pos = pci_pcie_cap(dev);
918 if (!pos)
b56a5a23
MT		 919 return 0;
920
9f35575d 921 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
b56a5a23 922 if (!save_state) {
e496b617 923 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
b56a5a23
MT		 924 return -ENOMEM;
925 }
24a4742f 926 cap = (u16 *)&save_state->cap.data[0];
b56a5a23 927
1b6b8ce2
YZ		 928 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
929
930 if (pcie_cap_has_devctl(dev->pcie_type, flags))
931 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
932 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
933 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
934 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
935 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
936 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
937 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
938 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
939 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
940 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
941 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
942 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
943 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
63f4898a 944
b56a5a23
MT		 945 return 0;
946}
947
948static void pci_restore_pcie_state(struct pci_dev *dev)
949{
950 int i = 0, pos;
951 struct pci_cap_saved_state *save_state;
952 u16 *cap;
1b6b8ce2 953 u16 flags;
b56a5a23
MT		 954
955 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
956 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
957 if (!save_state || pos <= 0)
958 return;
24a4742f 959 cap = (u16 *)&save_state->cap.data[0];
b56a5a23 960
1b6b8ce2
YZ		 961 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
962
963 if (pcie_cap_has_devctl(dev->pcie_type, flags))
964 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
965 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
966 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
967 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
968 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
969 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
970 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
971 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
972 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
973 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
974 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
975 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
976 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
b56a5a23
MT		 977}
978
cc692a5f
SH		 979
980static int pci_save_pcix_state(struct pci_dev *dev)
981{
63f4898a 982 int pos;
cc692a5f 983 struct pci_cap_saved_state *save_state;
cc692a5f
SH		 984
985 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
986 if (pos <= 0)
987 return 0;
988
f34303de 989 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
cc692a5f 990 if (!save_state) {
e496b617 991 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
cc692a5f
SH		 992 return -ENOMEM;
993 }
cc692a5f 994
24a4742f
AW		 995 pci_read_config_word(dev, pos + PCI_X_CMD,
996 (u16 *)save_state->cap.data);
63f4898a 997
cc692a5f
SH		 998 return 0;
999}
1000
1001static void pci_restore_pcix_state(struct pci_dev *dev)
1002{
1003 int i = 0, pos;
1004 struct pci_cap_saved_state *save_state;
1005 u16 *cap;
1006
1007 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1008 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1009 if (!save_state || pos <= 0)
1010 return;
24a4742f 1011 cap = (u16 *)&save_state->cap.data[0];
cc692a5f
SH		 1012
1013 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
cc692a5f
SH		 1014}
1015
1016
1da177e4
LT		 1017/**
1018 * pci_save_state - save the PCI configuration space of a device before suspending
1019 * @dev: - PCI device that we're dealing with
1da177e4
LT		 1020 */
1021int
1022pci_save_state(struct pci_dev *dev)
1023{
1024 int i;
1025 /* XXX: 100% dword access ok here? */
1026 for (i = 0; i < 16; i++)
9e0b5b2c 1027 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
aa8c6c93 1028 dev->state_saved = true;
b56a5a23
MT		 1029 if ((i = pci_save_pcie_state(dev)) != 0)
1030 return i;
cc692a5f
SH		 1031 if ((i = pci_save_pcix_state(dev)) != 0)
1032 return i;
1da177e4
LT		 1033 return 0;
1034}
1035
ebfc5b80
RW		 1036static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1037 u32 saved_val, int retry)
1038{
1039 u32 val;
1040
1041 pci_read_config_dword(pdev, offset, &val);
1042 if (val == saved_val)
1043 return;
1044
1045 for (;;) {
1046 dev_dbg(&pdev->dev, "restoring config space at offset "
1047 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
1048 pci_write_config_dword(pdev, offset, saved_val);
1049 if (retry-- <= 0)
1050 return;
1051
1052 pci_read_config_dword(pdev, offset, &val);
1053 if (val == saved_val)
1054 return;
1055
1056 mdelay(1);
1057 }
1058}
1059
a6cb9ee7
RW		 1060static void pci_restore_config_space_range(struct pci_dev *pdev,
1061 int start, int end, int retry)
ebfc5b80
RW		 1062{
1063 int index;
1064
1065 for (index = end; index >= start; index--)
1066 pci_restore_config_dword(pdev, 4 * index,
1067 pdev->saved_config_space[index],
1068 retry);
1069}
1070
a6cb9ee7
RW		 1071static void pci_restore_config_space(struct pci_dev *pdev)
1072{
1073 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1074 pci_restore_config_space_range(pdev, 10, 15, 0);
1075 /* Restore BARs before the command register. */
1076 pci_restore_config_space_range(pdev, 4, 9, 10);
1077 pci_restore_config_space_range(pdev, 0, 3, 0);
1078 } else {
1079 pci_restore_config_space_range(pdev, 0, 15, 0);
1080 }
1081}
1082
1da177e4
LT		 1083/**
1084 * pci_restore_state - Restore the saved state of a PCI device
1085 * @dev: - PCI device that we're dealing with
1da177e4 1086 */
1d3c16a8 1087void pci_restore_state(struct pci_dev *dev)
1da177e4 1088{
c82f63e4 1089 if (!dev->state_saved)
1d3c16a8 1090 return;
4b77b0a2 1091
b56a5a23
MT		 1092 /* PCI Express register must be restored first */
1093 pci_restore_pcie_state(dev);
1900ca13 1094 pci_restore_ats_state(dev);
b56a5a23 1095
a6cb9ee7 1096 pci_restore_config_space(dev);
ebfc5b80 1097
cc692a5f 1098 pci_restore_pcix_state(dev);
41017f0c 1099 pci_restore_msi_state(dev);
8c5cdb6a 1100 pci_restore_iov_state(dev);
8fed4b65 1101
4b77b0a2 1102 dev->state_saved = false;
1da177e4
LT		 1103}
1104
ffbdd3f7
AW		 1105struct pci_saved_state {
1106 u32 config_space[16];
1107 struct pci_cap_saved_data cap[0];
1108};
1109
1110/**
1111 * pci_store_saved_state - Allocate and return an opaque struct containing
1112 * the device saved state.
1113 * @dev: PCI device that we're dealing with
1114 *
1115 * Rerturn NULL if no state or error.
1116 */
1117struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1118{
1119 struct pci_saved_state *state;
1120 struct pci_cap_saved_state *tmp;
1121 struct pci_cap_saved_data *cap;
1122 struct hlist_node *pos;
1123 size_t size;
1124
1125 if (!dev->state_saved)
1126 return NULL;
1127
1128 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1129
1130 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1131 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1132
1133 state = kzalloc(size, GFP_KERNEL);
1134 if (!state)
1135 return NULL;
1136
1137 memcpy(state->config_space, dev->saved_config_space,
1138 sizeof(state->config_space));
1139
1140 cap = state->cap;
1141 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1142 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1143 memcpy(cap, &tmp->cap, len);
1144 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1145 }
1146 /* Empty cap_save terminates list */
1147
1148 return state;
1149}
1150EXPORT_SYMBOL_GPL(pci_store_saved_state);
1151
1152/**
1153 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1154 * @dev: PCI device that we're dealing with
1155 * @state: Saved state returned from pci_store_saved_state()
1156 */
1157int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1158{
1159 struct pci_cap_saved_data *cap;
1160
1161 dev->state_saved = false;
1162
1163 if (!state)
1164 return 0;
1165
1166 memcpy(dev->saved_config_space, state->config_space,
1167 sizeof(state->config_space));
1168
1169 cap = state->cap;
1170 while (cap->size) {
1171 struct pci_cap_saved_state *tmp;
1172
1173 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1174 if (!tmp || tmp->cap.size != cap->size)
1175 return -EINVAL;
1176
1177 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1178 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1179 sizeof(struct pci_cap_saved_data) + cap->size);
1180 }
1181
1182 dev->state_saved = true;
1183 return 0;
1184}
1185EXPORT_SYMBOL_GPL(pci_load_saved_state);
1186
1187/**
1188 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1189 * and free the memory allocated for it.
1190 * @dev: PCI device that we're dealing with
1191 * @state: Pointer to saved state returned from pci_store_saved_state()
1192 */
1193int pci_load_and_free_saved_state(struct pci_dev *dev,
1194 struct pci_saved_state **state)
1195{
1196 int ret = pci_load_saved_state(dev, *state);
1197 kfree(*state);
1198 *state = NULL;
1199 return ret;
1200}
1201EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1202
38cc1302
HS		 1203static int do_pci_enable_device(struct pci_dev *dev, int bars)
1204{
1205 int err;
1206
1207 err = pci_set_power_state(dev, PCI_D0);
1208 if (err < 0 && err != -EIO)
1209 return err;
1210 err = pcibios_enable_device(dev, bars);
1211 if (err < 0)
1212 return err;
1213 pci_fixup_device(pci_fixup_enable, dev);
1214
1215 return 0;
1216}
1217
1218/**
0b62e13b 1219 * pci_reenable_device - Resume abandoned device
38cc1302
HS		 1220 * @dev: PCI device to be resumed
1221 *
1222 * Note this function is a backend of pci_default_resume and is not supposed
1223 * to be called by normal code, write proper resume handler and use it instead.
1224 */
0b62e13b 1225int pci_reenable_device(struct pci_dev *dev)
38cc1302 1226{
296ccb08 1227 if (pci_is_enabled(dev))
38cc1302
HS		 1228 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1229 return 0;
1230}
1231
b718989d
BH		 1232static int __pci_enable_device_flags(struct pci_dev *dev,
1233 resource_size_t flags)
1da177e4
LT		 1234{
1235 int err;
b718989d 1236 int i, bars = 0;
1da177e4 1237
97c145f7
JB		 1238 /*
1239 * Power state could be unknown at this point, either due to a fresh
1240 * boot or a device removal call. So get the current power state
1241 * so that things like MSI message writing will behave as expected
1242 * (e.g. if the device really is in D0 at enable time).
1243 */
1244 if (dev->pm_cap) {
1245 u16 pmcsr;
1246 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1247 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1248 }
1249
9fb625c3
HS		 1250 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1251 return 0; /* already enabled */
1252
497f16f2
YL		 1253 /* only skip sriov related */
1254 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1255 if (dev->resource[i].flags & flags)
1256 bars |= (1 << i);
1257 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
b718989d
BH		 1258 if (dev->resource[i].flags & flags)
1259 bars |= (1 << i);
1260
38cc1302 1261 err = do_pci_enable_device(dev, bars);
95a62965 1262 if (err < 0)
38cc1302 1263 atomic_dec(&dev->enable_cnt);
9fb625c3 1264 return err;
1da177e4
LT		 1265}
1266
b718989d
BH		 1267/**
1268 * pci_enable_device_io - Initialize a device for use with IO space
1269 * @dev: PCI device to be initialized
1270 *
1271 * Initialize device before it's used by a driver. Ask low-level code
1272 * to enable I/O resources. Wake up the device if it was suspended.
1273 * Beware, this function can fail.
1274 */
1275int pci_enable_device_io(struct pci_dev *dev)
1276{
1277 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1278}
1279
1280/**
1281 * pci_enable_device_mem - Initialize a device for use with Memory space
1282 * @dev: PCI device to be initialized
1283 *
1284 * Initialize device before it's used by a driver. Ask low-level code
1285 * to enable Memory resources. Wake up the device if it was suspended.
1286 * Beware, this function can fail.
1287 */
1288int pci_enable_device_mem(struct pci_dev *dev)
1289{
1290 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1291}
1292
bae94d02
IPG		 1293/**
1294 * pci_enable_device - Initialize device before it's used by a driver.
1295 * @dev: PCI device to be initialized
1296 *
1297 * Initialize device before it's used by a driver. Ask low-level code
1298 * to enable I/O and memory. Wake up the device if it was suspended.
1299 * Beware, this function can fail.
1300 *
1301 * Note we don't actually enable the device many times if we call
1302 * this function repeatedly (we just increment the count).
1303 */
1304int pci_enable_device(struct pci_dev *dev)
1305{
b718989d 1306 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
bae94d02
IPG		 1307}
1308
9ac7849e
TH		 1309/*
1310 * Managed PCI resources. This manages device on/off, intx/msi/msix
1311 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1312 * there's no need to track it separately. pci_devres is initialized
1313 * when a device is enabled using managed PCI device enable interface.
1314 */
1315struct pci_devres {
7f375f32
TH		 1316 unsigned int enabled:1;
1317 unsigned int pinned:1;
9ac7849e
TH		 1318 unsigned int orig_intx:1;
1319 unsigned int restore_intx:1;
1320 u32 region_mask;
1321};
1322
1323static void pcim_release(struct device *gendev, void *res)
1324{
1325 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1326 struct pci_devres *this = res;
1327 int i;
1328
1329 if (dev->msi_enabled)
1330 pci_disable_msi(dev);
1331 if (dev->msix_enabled)
1332 pci_disable_msix(dev);
1333
1334 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1335 if (this->region_mask & (1 << i))
1336 pci_release_region(dev, i);
1337
1338 if (this->restore_intx)
1339 pci_intx(dev, this->orig_intx);
1340
7f375f32 1341 if (this->enabled && !this->pinned)
9ac7849e
TH		 1342 pci_disable_device(dev);
1343}
1344
1345static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1346{
1347 struct pci_devres *dr, *new_dr;
1348
1349 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1350 if (dr)
1351 return dr;
1352
1353 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1354 if (!new_dr)
1355 return NULL;
1356 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1357}
1358
1359static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1360{
1361 if (pci_is_managed(pdev))
1362 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1363 return NULL;
1364}
1365
1366/**
1367 * pcim_enable_device - Managed pci_enable_device()
1368 * @pdev: PCI device to be initialized
1369 *
1370 * Managed pci_enable_device().
1371 */
1372int pcim_enable_device(struct pci_dev *pdev)
1373{
1374 struct pci_devres *dr;
1375 int rc;
1376
1377 dr = get_pci_dr(pdev);
1378 if (unlikely(!dr))
1379 return -ENOMEM;
b95d58ea
TH		 1380 if (dr->enabled)
1381 return 0;
9ac7849e
TH		 1382
1383 rc = pci_enable_device(pdev);
1384 if (!rc) {
1385 pdev->is_managed = 1;
7f375f32 1386 dr->enabled = 1;
9ac7849e
TH		 1387 }
1388 return rc;
1389}
1390
1391/**
1392 * pcim_pin_device - Pin managed PCI device
1393 * @pdev: PCI device to pin
1394 *
1395 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1396 * driver detach. @pdev must have been enabled with
1397 * pcim_enable_device().
1398 */
1399void pcim_pin_device(struct pci_dev *pdev)
1400{
1401 struct pci_devres *dr;
1402
1403 dr = find_pci_dr(pdev);
7f375f32 1404 WARN_ON(!dr || !dr->enabled);
9ac7849e 1405 if (dr)
7f375f32 1406 dr->pinned = 1;
9ac7849e
TH		 1407}
1408
1da177e4
LT		 1409/**
1410 * pcibios_disable_device - disable arch specific PCI resources for device dev
1411 * @dev: the PCI device to disable
1412 *
1413 * Disables architecture specific PCI resources for the device. This
1414 * is the default implementation. Architecture implementations can
1415 * override this.
1416 */
1417void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1418
fa58d305
RW		 1419static void do_pci_disable_device(struct pci_dev *dev)
1420{
1421 u16 pci_command;
1422
1423 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1424 if (pci_command & PCI_COMMAND_MASTER) {
1425 pci_command &= ~PCI_COMMAND_MASTER;
1426 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1427 }
1428
1429 pcibios_disable_device(dev);
1430}
1431
1432/**
1433 * pci_disable_enabled_device - Disable device without updating enable_cnt
1434 * @dev: PCI device to disable
1435 *
1436 * NOTE: This function is a backend of PCI power management routines and is
1437 * not supposed to be called drivers.
1438 */
1439void pci_disable_enabled_device(struct pci_dev *dev)
1440{
296ccb08 1441 if (pci_is_enabled(dev))
fa58d305
RW		 1442 do_pci_disable_device(dev);
1443}
1444
1da177e4
LT		 1445/**
1446 * pci_disable_device - Disable PCI device after use
1447 * @dev: PCI device to be disabled
1448 *
1449 * Signal to the system that the PCI device is not in use by the system
1450 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 1451 *
1452 * Note we don't actually disable the device until all callers of
ee6583f6 1453 * pci_enable_device() have called pci_disable_device().
1da177e4
LT		 1454 */
1455void
1456pci_disable_device(struct pci_dev *dev)
1457{
9ac7849e 1458 struct pci_devres *dr;
99dc804d 1459
9ac7849e
TH		 1460 dr = find_pci_dr(dev);
1461 if (dr)
7f375f32 1462 dr->enabled = 0;
9ac7849e 1463
bae94d02
IPG		 1464 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1465 return;
1466
fa58d305 1467 do_pci_disable_device(dev);
1da177e4 1468
fa58d305 1469 dev->is_busmaster = 0;
1da177e4
LT		 1470}
1471
f7bdd12d
BK		 1472/**
1473 * pcibios_set_pcie_reset_state - set reset state for device dev
45e829ea 1474 * @dev: the PCIe device reset
f7bdd12d
BK		 1475 * @state: Reset state to enter into
1476 *
1477 *
45e829ea 1478 * Sets the PCIe reset state for the device. This is the default
f7bdd12d
BK		 1479 * implementation. Architecture implementations can override this.
1480 */
1481int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1482 enum pcie_reset_state state)
1483{
1484 return -EINVAL;
1485}
1486
1487/**
1488 * pci_set_pcie_reset_state - set reset state for device dev
45e829ea 1489 * @dev: the PCIe device reset
f7bdd12d
BK		 1490 * @state: Reset state to enter into
1491 *
1492 *
1493 * Sets the PCI reset state for the device.
1494 */
1495int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1496{
1497 return pcibios_set_pcie_reset_state(dev, state);
1498}
1499
58ff4633
RW		 1500/**
1501 * pci_check_pme_status - Check if given device has generated PME.
1502 * @dev: Device to check.
1503 *
1504 * Check the PME status of the device and if set, clear it and clear PME enable
1505 * (if set). Return 'true' if PME status and PME enable were both set or
1506 * 'false' otherwise.
1507 */
1508bool pci_check_pme_status(struct pci_dev *dev)
1509{
1510 int pmcsr_pos;
1511 u16 pmcsr;
1512 bool ret = false;
1513
1514 if (!dev->pm_cap)
1515 return false;
1516
1517 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1518 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1519 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1520 return false;
1521
1522 /* Clear PME status. */
1523 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1524 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1525 /* Disable PME to avoid interrupt flood. */
1526 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1527 ret = true;
1528 }
1529
1530 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1531
1532 return ret;
1533}
1534
b67ea761
RW		 1535/**
1536 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1537 * @dev: Device to handle.
379021d5 1538 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
b67ea761
RW		 1539 *
1540 * Check if @dev has generated PME and queue a resume request for it in that
1541 * case.
1542 */
379021d5 1543static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
b67ea761 1544{
379021d5
RW		 1545 if (pme_poll_reset && dev->pme_poll)
1546 dev->pme_poll = false;
1547
c125e96f 1548 if (pci_check_pme_status(dev)) {
c125e96f 1549 pci_wakeup_event(dev);
0f953bf6 1550 pm_request_resume(&dev->dev);
c125e96f 1551 }
b67ea761
RW		 1552 return 0;
1553}
1554
1555/**
1556 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1557 * @bus: Top bus of the subtree to walk.
1558 */
1559void pci_pme_wakeup_bus(struct pci_bus *bus)
1560{
1561 if (bus)
379021d5 1562 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
b67ea761
RW		 1563}
1564
448bd857
HY		 1565/**
1566 * pci_wakeup - Wake up a PCI device
1567 * @dev: Device to handle.
1568 * @ign: ignored parameter
1569 */
1570static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1571{
1572 pci_wakeup_event(pci_dev);
1573 pm_request_resume(&pci_dev->dev);
1574 return 0;
1575}
1576
1577/**
1578 * pci_wakeup_bus - Walk given bus and wake up devices on it
1579 * @bus: Top bus of the subtree to walk.
1580 */
1581void pci_wakeup_bus(struct pci_bus *bus)
1582{
1583 if (bus)
1584 pci_walk_bus(bus, pci_wakeup, NULL);
1585}
1586
eb9d0fe4
RW		 1587/**
1588 * pci_pme_capable - check the capability of PCI device to generate PME#
1589 * @dev: PCI device to handle.
eb9d0fe4
RW		 1590 * @state: PCI state from which device will issue PME#.
1591 */
e5899e1b 1592bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
eb9d0fe4 1593{
337001b6 1594 if (!dev->pm_cap)
eb9d0fe4
RW		 1595 return false;
1596
337001b6 1597 return !!(dev->pme_support & (1 << state));
eb9d0fe4
RW		 1598}
1599
df17e62e
MG		 1600static void pci_pme_list_scan(struct work_struct *work)
1601{
379021d5 1602 struct pci_pme_device *pme_dev, *n;
df17e62e
MG		 1603
1604 mutex_lock(&pci_pme_list_mutex);
1605 if (!list_empty(&pci_pme_list)) {
379021d5
RW		 1606 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1607 if (pme_dev->dev->pme_poll) {
71a83bd7
ZY		 1608 struct pci_dev *bridge;
1609
1610 bridge = pme_dev->dev->bus->self;
1611 /*
1612 * If bridge is in low power state, the
1613 * configuration space of subordinate devices
1614 * may be not accessible
1615 */
1616 if (bridge && bridge->current_state != PCI_D0)
1617 continue;
379021d5
RW		 1618 pci_pme_wakeup(pme_dev->dev, NULL);
1619 } else {
1620 list_del(&pme_dev->list);
1621 kfree(pme_dev);
1622 }
1623 }
1624 if (!list_empty(&pci_pme_list))
1625 schedule_delayed_work(&pci_pme_work,
1626 msecs_to_jiffies(PME_TIMEOUT));
df17e62e
MG		 1627 }
1628 mutex_unlock(&pci_pme_list_mutex);
1629}
1630
eb9d0fe4
RW		 1631/**
1632 * pci_pme_active - enable or disable PCI device's PME# function
1633 * @dev: PCI device to handle.
eb9d0fe4
RW		 1634 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1635 *
1636 * The caller must verify that the device is capable of generating PME# before
1637 * calling this function with @enable equal to 'true'.
1638 */
5a6c9b60 1639void pci_pme_active(struct pci_dev *dev, bool enable)
eb9d0fe4
RW		 1640{
1641 u16 pmcsr;
1642
337001b6 1643 if (!dev->pm_cap)
eb9d0fe4
RW		 1644 return;
1645
337001b6 1646 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
eb9d0fe4
RW		 1647 /* Clear PME_Status by writing 1 to it and enable PME# */
1648 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1649 if (!enable)
1650 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1651
337001b6 1652 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
eb9d0fe4 1653
df17e62e
MG		 1654 /* PCI (as opposed to PCIe) PME requires that the device have
1655 its PME# line hooked up correctly. Not all hardware vendors
1656 do this, so the PME never gets delivered and the device
1657 remains asleep. The easiest way around this is to
1658 periodically walk the list of suspended devices and check
1659 whether any have their PME flag set. The assumption is that
1660 we'll wake up often enough anyway that this won't be a huge
1661 hit, and the power savings from the devices will still be a
1662 win. */
1663
379021d5 1664 if (dev->pme_poll) {
df17e62e
MG		 1665 struct pci_pme_device *pme_dev;
1666 if (enable) {
1667 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1668 GFP_KERNEL);
1669 if (!pme_dev)
1670 goto out;
1671 pme_dev->dev = dev;
1672 mutex_lock(&pci_pme_list_mutex);
1673 list_add(&pme_dev->list, &pci_pme_list);
1674 if (list_is_singular(&pci_pme_list))
1675 schedule_delayed_work(&pci_pme_work,
1676 msecs_to_jiffies(PME_TIMEOUT));
1677 mutex_unlock(&pci_pme_list_mutex);
1678 } else {
1679 mutex_lock(&pci_pme_list_mutex);
1680 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1681 if (pme_dev->dev == dev) {
1682 list_del(&pme_dev->list);
1683 kfree(pme_dev);
1684 break;
1685 }
1686 }
1687 mutex_unlock(&pci_pme_list_mutex);
1688 }
1689 }
1690
1691out:
85b8582d 1692 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
eb9d0fe4
RW		 1693}
1694
1da177e4 1695/**
6cbf8214 1696 * __pci_enable_wake - enable PCI device as wakeup event source
075c1771
DB		 1697 * @dev: PCI device affected
1698 * @state: PCI state from which device will issue wakeup events
6cbf8214 1699 * @runtime: True if the events are to be generated at run time
075c1771
DB		 1700 * @enable: True to enable event generation; false to disable
1701 *
1702 * This enables the device as a wakeup event source, or disables it.
1703 * When such events involves platform-specific hooks, those hooks are
1704 * called automatically by this routine.
1705 *
1706 * Devices with legacy power management (no standard PCI PM capabilities)
eb9d0fe4 1707 * always require such platform hooks.
075c1771 1708 *
eb9d0fe4
RW		 1709 * RETURN VALUE:
1710 * 0 is returned on success
1711 * -EINVAL is returned if device is not supposed to wake up the system
1712 * Error code depending on the platform is returned if both the platform and
1713 * the native mechanism fail to enable the generation of wake-up events
1da177e4 1714 */
6cbf8214
RW		 1715int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1716 bool runtime, bool enable)
1da177e4 1717{
5bcc2fb4 1718 int ret = 0;
075c1771 1719
6cbf8214 1720 if (enable && !runtime && !device_may_wakeup(&dev->dev))
eb9d0fe4 1721 return -EINVAL;
1da177e4 1722
e80bb09d
RW		 1723 /* Don't do the same thing twice in a row for one device. */
1724 if (!!enable == !!dev->wakeup_prepared)
1725 return 0;
1726
eb9d0fe4
RW		 1727 /*
1728 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1729 * Anderson we should be doing PME# wake enable followed by ACPI wake
1730 * enable. To disable wake-up we call the platform first, for symmetry.
075c1771 1731 */
1da177e4 1732
5bcc2fb4
RW		 1733 if (enable) {
1734 int error;
1da177e4 1735
5bcc2fb4
RW		 1736 if (pci_pme_capable(dev, state))
1737 pci_pme_active(dev, true);
1738 else
1739 ret = 1;
6cbf8214
RW		 1740 error = runtime ? platform_pci_run_wake(dev, true) :
1741 platform_pci_sleep_wake(dev, true);
5bcc2fb4
RW		 1742 if (ret)
1743 ret = error;
e80bb09d
RW		 1744 if (!ret)
1745 dev->wakeup_prepared = true;
5bcc2fb4 1746 } else {
6cbf8214
RW		 1747 if (runtime)
1748 platform_pci_run_wake(dev, false);
1749 else
1750 platform_pci_sleep_wake(dev, false);
5bcc2fb4 1751 pci_pme_active(dev, false);
e80bb09d 1752 dev->wakeup_prepared = false;
5bcc2fb4 1753 }
1da177e4 1754
5bcc2fb4 1755 return ret;
eb9d0fe4 1756}
6cbf8214 1757EXPORT_SYMBOL(__pci_enable_wake);
1da177e4 1758
0235c4fc
RW		 1759/**
1760 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1761 * @dev: PCI device to prepare
1762 * @enable: True to enable wake-up event generation; false to disable
1763 *
1764 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1765 * and this function allows them to set that up cleanly - pci_enable_wake()
1766 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1767 * ordering constraints.
1768 *
1769 * This function only returns error code if the device is not capable of
1770 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1771 * enable wake-up power for it.
1772 */
1773int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1774{
1775 return pci_pme_capable(dev, PCI_D3cold) ?
1776 pci_enable_wake(dev, PCI_D3cold, enable) :
1777 pci_enable_wake(dev, PCI_D3hot, enable);
1778}
1779
404cc2d8 1780/**
37139074
JB		 1781 * pci_target_state - find an appropriate low power state for a given PCI dev
1782 * @dev: PCI device
1783 *
1784 * Use underlying platform code to find a supported low power state for @dev.
1785 * If the platform can't manage @dev, return the deepest state from which it
1786 * can generate wake events, based on any available PME info.
404cc2d8 1787 */
e5899e1b 1788pci_power_t pci_target_state(struct pci_dev *dev)
404cc2d8
RW		 1789{
1790 pci_power_t target_state = PCI_D3hot;
404cc2d8
RW		 1791
1792 if (platform_pci_power_manageable(dev)) {
1793 /*
1794 * Call the platform to choose the target state of the device
1795 * and enable wake-up from this state if supported.
1796 */
1797 pci_power_t state = platform_pci_choose_state(dev);
1798
1799 switch (state) {
1800 case PCI_POWER_ERROR:
1801 case PCI_UNKNOWN:
1802 break;
1803 case PCI_D1:
1804 case PCI_D2:
1805 if (pci_no_d1d2(dev))
1806 break;
1807 default:
1808 target_state = state;
404cc2d8 1809 }
d2abdf62
RW		 1810 } else if (!dev->pm_cap) {
1811 target_state = PCI_D0;
404cc2d8
RW		 1812 } else if (device_may_wakeup(&dev->dev)) {
1813 /*
1814 * Find the deepest state from which the device can generate
1815 * wake-up events, make it the target state and enable device
1816 * to generate PME#.
1817 */
337001b6
RW		 1818 if (dev->pme_support) {
1819 while (target_state
1820 && !(dev->pme_support & (1 << target_state)))
1821 target_state--;
404cc2d8
RW		 1822 }
1823 }
1824
e5899e1b
RW		 1825 return target_state;
1826}
1827
1828/**
1829 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1830 * @dev: Device to handle.
1831 *
1832 * Choose the power state appropriate for the device depending on whether
1833 * it can wake up the system and/or is power manageable by the platform
1834 * (PCI_D3hot is the default) and put the device into that state.
1835 */
1836int pci_prepare_to_sleep(struct pci_dev *dev)
1837{
1838 pci_power_t target_state = pci_target_state(dev);
1839 int error;
1840
1841 if (target_state == PCI_POWER_ERROR)
1842 return -EIO;
1843
448bd857
HY		 1844 /* D3cold during system suspend/hibernate is not supported */
1845 if (target_state > PCI_D3hot)
1846 target_state = PCI_D3hot;
1847
8efb8c76 1848 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
c157dfa3 1849
404cc2d8
RW		 1850 error = pci_set_power_state(dev, target_state);
1851
1852 if (error)
1853 pci_enable_wake(dev, target_state, false);
1854
1855 return error;
1856}
1857
1858/**
443bd1c4 1859 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
404cc2d8
RW		 1860 * @dev: Device to handle.
1861 *
88393161 1862 * Disable device's system wake-up capability and put it into D0.
404cc2d8
RW		 1863 */
1864int pci_back_from_sleep(struct pci_dev *dev)
1865{
1866 pci_enable_wake(dev, PCI_D0, false);
1867 return pci_set_power_state(dev, PCI_D0);
1868}
1869
6cbf8214
RW		 1870/**
1871 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1872 * @dev: PCI device being suspended.
1873 *
1874 * Prepare @dev to generate wake-up events at run time and put it into a low
1875 * power state.
1876 */
1877int pci_finish_runtime_suspend(struct pci_dev *dev)
1878{
1879 pci_power_t target_state = pci_target_state(dev);
1880 int error;
1881
1882 if (target_state == PCI_POWER_ERROR)
1883 return -EIO;
1884
448bd857
HY		 1885 dev->runtime_d3cold = target_state == PCI_D3cold;
1886
6cbf8214
RW		 1887 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1888
1889 error = pci_set_power_state(dev, target_state);
1890
448bd857 1891 if (error) {
6cbf8214 1892 __pci_enable_wake(dev, target_state, true, false);
448bd857
HY		 1893 dev->runtime_d3cold = false;
1894 }
6cbf8214
RW		 1895
1896 return error;
1897}
1898
b67ea761
RW		 1899/**
1900 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1901 * @dev: Device to check.
1902 *
1903 * Return true if the device itself is cabable of generating wake-up events
1904 * (through the platform or using the native PCIe PME) or if the device supports
1905 * PME and one of its upstream bridges can generate wake-up events.
1906 */
1907bool pci_dev_run_wake(struct pci_dev *dev)
1908{
1909 struct pci_bus *bus = dev->bus;
1910
1911 if (device_run_wake(&dev->dev))
1912 return true;
1913
1914 if (!dev->pme_support)
1915 return false;
1916
1917 while (bus->parent) {
1918 struct pci_dev *bridge = bus->self;
1919
1920 if (device_run_wake(&bridge->dev))
1921 return true;
1922
1923 bus = bus->parent;
1924 }
1925
1926 /* We have reached the root bus. */
1927 if (bus->bridge)
1928 return device_run_wake(bus->bridge);
1929
1930 return false;
1931}
1932EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1933
eb9d0fe4
RW		 1934/**
1935 * pci_pm_init - Initialize PM functions of given PCI device
1936 * @dev: PCI device to handle.
1937 */
1938void pci_pm_init(struct pci_dev *dev)
1939{
1940 int pm;
1941 u16 pmc;
1da177e4 1942
bb910a70 1943 pm_runtime_forbid(&dev->dev);
a1e4d72c 1944 device_enable_async_suspend(&dev->dev);
e80bb09d 1945 dev->wakeup_prepared = false;
bb910a70 1946
337001b6
RW		 1947 dev->pm_cap = 0;
1948
eb9d0fe4
RW		 1949 /* find PCI PM capability in list */
1950 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1951 if (!pm)
50246dd4 1952 return;
eb9d0fe4
RW		 1953 /* Check device's ability to generate PME# */
1954 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
075c1771 1955
eb9d0fe4
RW		 1956 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1957 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1958 pmc & PCI_PM_CAP_VER_MASK);
50246dd4 1959 return;
eb9d0fe4
RW		 1960 }
1961
337001b6 1962 dev->pm_cap = pm;
1ae861e6 1963 dev->d3_delay = PCI_PM_D3_WAIT;
448bd857 1964 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
337001b6
RW		 1965
1966 dev->d1_support = false;
1967 dev->d2_support = false;
1968 if (!pci_no_d1d2(dev)) {
c9ed77ee 1969 if (pmc & PCI_PM_CAP_D1)
337001b6 1970 dev->d1_support = true;
c9ed77ee 1971 if (pmc & PCI_PM_CAP_D2)
337001b6 1972 dev->d2_support = true;
c9ed77ee
BH		 1973
1974 if (dev->d1_support || dev->d2_support)
1975 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
ec84f126
JB		 1976 dev->d1_support ? " D1" : "",
1977 dev->d2_support ? " D2" : "");
337001b6
RW		 1978 }
1979
1980 pmc &= PCI_PM_CAP_PME_MASK;
1981 if (pmc) {
10c3d71d
BH		 1982 dev_printk(KERN_DEBUG, &dev->dev,
1983 "PME# supported from%s%s%s%s%s\n",
c9ed77ee
BH		 1984 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1985 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1986 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1987 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1988 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
337001b6 1989 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
379021d5 1990 dev->pme_poll = true;
eb9d0fe4
RW		 1991 /*
1992 * Make device's PM flags reflect the wake-up capability, but
1993 * let the user space enable it to wake up the system as needed.
1994 */
1995 device_set_wakeup_capable(&dev->dev, true);
eb9d0fe4 1996 /* Disable the PME# generation functionality */
337001b6
RW		 1997 pci_pme_active(dev, false);
1998 } else {
1999 dev->pme_support = 0;
eb9d0fe4 2000 }
1da177e4
LT		 2001}
2002
eb9c39d0
JB		 2003/**
2004 * platform_pci_wakeup_init - init platform wakeup if present
2005 * @dev: PCI device
2006 *
2007 * Some devices don't have PCI PM caps but can still generate wakeup
2008 * events through platform methods (like ACPI events). If @dev supports
2009 * platform wakeup events, set the device flag to indicate as much. This
2010 * may be redundant if the device also supports PCI PM caps, but double
2011 * initialization should be safe in that case.
2012 */
2013void platform_pci_wakeup_init(struct pci_dev *dev)
2014{
2015 if (!platform_pci_can_wakeup(dev))
2016 return;
2017
2018 device_set_wakeup_capable(&dev->dev, true);
eb9c39d0
JB		 2019 platform_pci_sleep_wake(dev, false);
2020}
2021
34a4876e
YL		 2022static void pci_add_saved_cap(struct pci_dev *pci_dev,
2023 struct pci_cap_saved_state *new_cap)
2024{
2025 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2026}
2027
63f4898a
RW		 2028/**
2029 * pci_add_save_buffer - allocate buffer for saving given capability registers
2030 * @dev: the PCI device
2031 * @cap: the capability to allocate the buffer for
2032 * @size: requested size of the buffer
2033 */
2034static int pci_add_cap_save_buffer(
2035 struct pci_dev *dev, char cap, unsigned int size)
2036{
2037 int pos;
2038 struct pci_cap_saved_state *save_state;
2039
2040 pos = pci_find_capability(dev, cap);
2041 if (pos <= 0)
2042 return 0;
2043
2044 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2045 if (!save_state)
2046 return -ENOMEM;
2047
24a4742f
AW		 2048 save_state->cap.cap_nr = cap;
2049 save_state->cap.size = size;
63f4898a
RW		 2050 pci_add_saved_cap(dev, save_state);
2051
2052 return 0;
2053}
2054
2055/**
2056 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2057 * @dev: the PCI device
2058 */
2059void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2060{
2061 int error;
2062
89858517
YZ		 2063 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2064 PCI_EXP_SAVE_REGS * sizeof(u16));
63f4898a
RW		 2065 if (error)
2066 dev_err(&dev->dev,
2067 "unable to preallocate PCI Express save buffer\n");
2068
2069 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2070 if (error)
2071 dev_err(&dev->dev,
2072 "unable to preallocate PCI-X save buffer\n");
2073}
2074
f796841e
YL		 2075void pci_free_cap_save_buffers(struct pci_dev *dev)
2076{
2077 struct pci_cap_saved_state *tmp;
2078 struct hlist_node *pos, *n;
2079
2080 hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next)
2081 kfree(tmp);
2082}
2083
58c3a727
YZ		 2084/**
2085 * pci_enable_ari - enable ARI forwarding if hardware support it
2086 * @dev: the PCI device
2087 */
2088void pci_enable_ari(struct pci_dev *dev)
2089{
2090 int pos;
2091 u32 cap;
864d296c 2092 u16 flags, ctrl;
8113587c 2093 struct pci_dev *bridge;
58c3a727 2094
6748dcc2 2095 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
58c3a727
YZ		 2096 return;
2097
8113587c
ZY		 2098 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2099 if (!pos)
58c3a727
YZ		 2100 return;
2101
8113587c 2102 bridge = dev->bus->self;
5f4d91a1 2103 if (!bridge || !pci_is_pcie(bridge))
8113587c
ZY		 2104 return;
2105
06a1cbaf 2106 pos = pci_pcie_cap(bridge);
58c3a727
YZ		 2107 if (!pos)
2108 return;
2109
864d296c
CW		 2110 /* ARI is a PCIe v2 feature */
2111 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
2112 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
2113 return;
2114
8113587c 2115 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
58c3a727
YZ		 2116 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2117 return;
2118
8113587c 2119 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
58c3a727 2120 ctrl |= PCI_EXP_DEVCTL2_ARI;
8113587c 2121 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
58c3a727 2122
8113587c 2123 bridge->ari_enabled = 1;
58c3a727
YZ		 2124}
2125
b48d4425
JB		 2126/**
2127 * pci_enable_ido - enable ID-based ordering on a device
2128 * @dev: the PCI device
2129 * @type: which types of IDO to enable
2130 *
2131 * Enable ID-based ordering on @dev. @type can contain the bits
2132 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2133 * which types of transactions are allowed to be re-ordered.
2134 */
2135void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2136{
2137 int pos;
2138 u16 ctrl;
2139
2140 pos = pci_pcie_cap(dev);
2141 if (!pos)
2142 return;
2143
2144 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2145 if (type & PCI_EXP_IDO_REQUEST)
2146 ctrl |= PCI_EXP_IDO_REQ_EN;
2147 if (type & PCI_EXP_IDO_COMPLETION)
2148 ctrl |= PCI_EXP_IDO_CMP_EN;
2149 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2150}
2151EXPORT_SYMBOL(pci_enable_ido);
2152
2153/**
2154 * pci_disable_ido - disable ID-based ordering on a device
2155 * @dev: the PCI device
2156 * @type: which types of IDO to disable
2157 */
2158void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2159{
2160 int pos;
2161 u16 ctrl;
2162
2163 if (!pci_is_pcie(dev))
2164 return;
2165
2166 pos = pci_pcie_cap(dev);
2167 if (!pos)
2168 return;
2169
2170 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2171 if (type & PCI_EXP_IDO_REQUEST)
2172 ctrl &= ~PCI_EXP_IDO_REQ_EN;
2173 if (type & PCI_EXP_IDO_COMPLETION)
2174 ctrl &= ~PCI_EXP_IDO_CMP_EN;
2175 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2176}
2177EXPORT_SYMBOL(pci_disable_ido);
2178
48a92a81
JB		 2179/**
2180 * pci_enable_obff - enable optimized buffer flush/fill
2181 * @dev: PCI device
2182 * @type: type of signaling to use
2183 *
2184 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2185 * signaling if possible, falling back to message signaling only if
2186 * WAKE# isn't supported. @type should indicate whether the PCIe link
2187 * be brought out of L0s or L1 to send the message. It should be either
2188 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2189 *
2190 * If your device can benefit from receiving all messages, even at the
2191 * power cost of bringing the link back up from a low power state, use
2192 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2193 * preferred type).
2194 *
2195 * RETURNS:
2196 * Zero on success, appropriate error number on failure.
2197 */
2198int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2199{
2200 int pos;
2201 u32 cap;
2202 u16 ctrl;
2203 int ret;
2204
2205 if (!pci_is_pcie(dev))
2206 return -ENOTSUPP;
2207
2208 pos = pci_pcie_cap(dev);
2209 if (!pos)
2210 return -ENOTSUPP;
2211
2212 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2213 if (!(cap & PCI_EXP_OBFF_MASK))
2214 return -ENOTSUPP; /* no OBFF support at all */
2215
2216 /* Make sure the topology supports OBFF as well */
2217 if (dev->bus) {
2218 ret = pci_enable_obff(dev->bus->self, type);
2219 if (ret)
2220 return ret;
2221 }
2222
2223 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2224 if (cap & PCI_EXP_OBFF_WAKE)
2225 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2226 else {
2227 switch (type) {
2228 case PCI_EXP_OBFF_SIGNAL_L0:
2229 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2230 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2231 break;
2232 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2233 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2234 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2235 break;
2236 default:
2237 WARN(1, "bad OBFF signal type\n");
2238 return -ENOTSUPP;
2239 }
2240 }
2241 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2242
2243 return 0;
2244}
2245EXPORT_SYMBOL(pci_enable_obff);
2246
2247/**
2248 * pci_disable_obff - disable optimized buffer flush/fill
2249 * @dev: PCI device
2250 *
2251 * Disable OBFF on @dev.
2252 */
2253void pci_disable_obff(struct pci_dev *dev)
2254{
2255 int pos;
2256 u16 ctrl;
2257
2258 if (!pci_is_pcie(dev))
2259 return;
2260
2261 pos = pci_pcie_cap(dev);
2262 if (!pos)
2263 return;
2264
2265 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2266 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2267 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2268}
2269EXPORT_SYMBOL(pci_disable_obff);
2270
51c2e0a7
JB		 2271/**
2272 * pci_ltr_supported - check whether a device supports LTR
2273 * @dev: PCI device
2274 *
2275 * RETURNS:
2276 * True if @dev supports latency tolerance reporting, false otherwise.
2277 */
2278bool pci_ltr_supported(struct pci_dev *dev)
2279{
2280 int pos;
2281 u32 cap;
2282
2283 if (!pci_is_pcie(dev))
2284 return false;
2285
2286 pos = pci_pcie_cap(dev);
2287 if (!pos)
2288 return false;
2289
2290 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2291
2292 return cap & PCI_EXP_DEVCAP2_LTR;
2293}
2294EXPORT_SYMBOL(pci_ltr_supported);
2295
2296/**
2297 * pci_enable_ltr - enable latency tolerance reporting
2298 * @dev: PCI device
2299 *
2300 * Enable LTR on @dev if possible, which means enabling it first on
2301 * upstream ports.
2302 *
2303 * RETURNS:
2304 * Zero on success, errno on failure.
2305 */
2306int pci_enable_ltr(struct pci_dev *dev)
2307{
2308 int pos;
2309 u16 ctrl;
2310 int ret;
2311
2312 if (!pci_ltr_supported(dev))
2313 return -ENOTSUPP;
2314
2315 pos = pci_pcie_cap(dev);
2316 if (!pos)
2317 return -ENOTSUPP;
2318
2319 /* Only primary function can enable/disable LTR */
2320 if (PCI_FUNC(dev->devfn) != 0)
2321 return -EINVAL;
2322
2323 /* Enable upstream ports first */
2324 if (dev->bus) {
2325 ret = pci_enable_ltr(dev->bus->self);
2326 if (ret)
2327 return ret;
2328 }
2329
2330 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2331 ctrl |= PCI_EXP_LTR_EN;
2332 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2333
2334 return 0;
2335}
2336EXPORT_SYMBOL(pci_enable_ltr);
2337
2338/**
2339 * pci_disable_ltr - disable latency tolerance reporting
2340 * @dev: PCI device
2341 */
2342void pci_disable_ltr(struct pci_dev *dev)
2343{
2344 int pos;
2345 u16 ctrl;
2346
2347 if (!pci_ltr_supported(dev))
2348 return;
2349
2350 pos = pci_pcie_cap(dev);
2351 if (!pos)
2352 return;
2353
2354 /* Only primary function can enable/disable LTR */
2355 if (PCI_FUNC(dev->devfn) != 0)
2356 return;
2357
2358 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2359 ctrl &= ~PCI_EXP_LTR_EN;
2360 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2361}
2362EXPORT_SYMBOL(pci_disable_ltr);
2363
2364static int __pci_ltr_scale(int *val)
2365{
2366 int scale = 0;
2367
2368 while (*val > 1023) {
2369 *val = (*val + 31) / 32;
2370 scale++;
2371 }
2372 return scale;
2373}
2374
2375/**
2376 * pci_set_ltr - set LTR latency values
2377 * @dev: PCI device
2378 * @snoop_lat_ns: snoop latency in nanoseconds
2379 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2380 *
2381 * Figure out the scale and set the LTR values accordingly.
2382 */
2383int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2384{
2385 int pos, ret, snoop_scale, nosnoop_scale;
2386 u16 val;
2387
2388 if (!pci_ltr_supported(dev))
2389 return -ENOTSUPP;
2390
2391 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2392 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2393
2394 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2395 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2396 return -EINVAL;
2397
2398 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2399 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2400 return -EINVAL;
2401
2402 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2403 if (!pos)
2404 return -ENOTSUPP;
2405
2406 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2407 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2408 if (ret != 4)
2409 return -EIO;
2410
2411 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2412 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2413 if (ret != 4)
2414 return -EIO;
2415
2416 return 0;
2417}
2418EXPORT_SYMBOL(pci_set_ltr);
2419
5d990b62
CW		 2420static int pci_acs_enable;
2421
2422/**
2423 * pci_request_acs - ask for ACS to be enabled if supported
2424 */
2425void pci_request_acs(void)
2426{
2427 pci_acs_enable = 1;
2428}
2429
ae21ee65
AK		 2430/**
2431 * pci_enable_acs - enable ACS if hardware support it
2432 * @dev: the PCI device
2433 */
2434void pci_enable_acs(struct pci_dev *dev)
2435{
2436 int pos;
2437 u16 cap;
2438 u16 ctrl;
2439
5d990b62
CW		 2440 if (!pci_acs_enable)
2441 return;
2442
5f4d91a1 2443 if (!pci_is_pcie(dev))
ae21ee65
AK		 2444 return;
2445
2446 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2447 if (!pos)
2448 return;
2449
2450 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2451 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2452
2453 /* Source Validation */
2454 ctrl |= (cap & PCI_ACS_SV);
2455
2456 /* P2P Request Redirect */
2457 ctrl |= (cap & PCI_ACS_RR);
2458
2459 /* P2P Completion Redirect */
2460 ctrl |= (cap & PCI_ACS_CR);
2461
2462 /* Upstream Forwarding */
2463 ctrl |= (cap & PCI_ACS_UF);
2464
2465 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2466}
2467
57c2cf71
BH		 2468/**
2469 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2470 * @dev: the PCI device
2471 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2472 *
2473 * Perform INTx swizzling for a device behind one level of bridge. This is
2474 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
46b952a3
MW		 2475 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2476 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2477 * the PCI Express Base Specification, Revision 2.1)
57c2cf71 2478 */
3df425f3 2479u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
57c2cf71 2480{
46b952a3
MW		 2481 int slot;
2482
2483 if (pci_ari_enabled(dev->bus))
2484 slot = 0;
2485 else
2486 slot = PCI_SLOT(dev->devfn);
2487
2488 return (((pin - 1) + slot) % 4) + 1;
57c2cf71
BH		 2489}
2490
1da177e4
LT		 2491int
2492pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2493{
2494 u8 pin;
2495
514d207d 2496 pin = dev->pin;
1da177e4
LT		 2497 if (!pin)
2498 return -1;
878f2e50 2499
8784fd4d 2500 while (!pci_is_root_bus(dev->bus)) {
57c2cf71 2501 pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4
LT		 2502 dev = dev->bus->self;
2503 }
2504 *bridge = dev;
2505 return pin;
2506}
2507
68feac87
BH		 2508/**
2509 * pci_common_swizzle - swizzle INTx all the way to root bridge
2510 * @dev: the PCI device
2511 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2512 *
2513 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2514 * bridges all the way up to a PCI root bus.
2515 */
2516u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2517{
2518 u8 pin = *pinp;
2519
1eb39487 2520 while (!pci_is_root_bus(dev->bus)) {
68feac87
BH		 2521 pin = pci_swizzle_interrupt_pin(dev, pin);
2522 dev = dev->bus->self;
2523 }
2524 *pinp = pin;
2525 return PCI_SLOT(dev->devfn);
2526}
2527
1da177e4
LT		 2528/**
2529 * pci_release_region - Release a PCI bar
2530 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2531 * @bar: BAR to release
2532 *
2533 * Releases the PCI I/O and memory resources previously reserved by a
2534 * successful call to pci_request_region. Call this function only
2535 * after all use of the PCI regions has ceased.
2536 */
2537void pci_release_region(struct pci_dev *pdev, int bar)
2538{
9ac7849e
TH		 2539 struct pci_devres *dr;
2540
1da177e4
LT		 2541 if (pci_resource_len(pdev, bar) == 0)
2542 return;
2543 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2544 release_region(pci_resource_start(pdev, bar),
2545 pci_resource_len(pdev, bar));
2546 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2547 release_mem_region(pci_resource_start(pdev, bar),
2548 pci_resource_len(pdev, bar));
9ac7849e
TH		 2549
2550 dr = find_pci_dr(pdev);
2551 if (dr)
2552 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 2553}
2554
2555/**
f5ddcac4 2556 * __pci_request_region - Reserved PCI I/O and memory resource
1da177e4
LT		 2557 * @pdev: PCI device whose resources are to be reserved
2558 * @bar: BAR to be reserved
2559 * @res_name: Name to be associated with resource.
f5ddcac4 2560 * @exclusive: whether the region access is exclusive or not
1da177e4
LT		 2561 *
2562 * Mark the PCI region associated with PCI device @pdev BR @bar as
2563 * being reserved by owner @res_name. Do not access any
2564 * address inside the PCI regions unless this call returns
2565 * successfully.
2566 *
f5ddcac4
RD		 2567 * If @exclusive is set, then the region is marked so that userspace
2568 * is explicitly not allowed to map the resource via /dev/mem or
2569 * sysfs MMIO access.
2570 *
1da177e4
LT		 2571 * Returns 0 on success, or %EBUSY on error. A warning
2572 * message is also printed on failure.
2573 */
e8de1481
AV		 2574static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2575 int exclusive)
1da177e4 2576{
9ac7849e
TH		 2577 struct pci_devres *dr;
2578
1da177e4
LT		 2579 if (pci_resource_len(pdev, bar) == 0)
2580 return 0;
2581
2582 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2583 if (!request_region(pci_resource_start(pdev, bar),
2584 pci_resource_len(pdev, bar), res_name))
2585 goto err_out;
2586 }
2587 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
e8de1481
AV		 2588 if (!__request_mem_region(pci_resource_start(pdev, bar),
2589 pci_resource_len(pdev, bar), res_name,
2590 exclusive))
1da177e4
LT		 2591 goto err_out;
2592 }
9ac7849e
TH		 2593
2594 dr = find_pci_dr(pdev);
2595 if (dr)
2596 dr->region_mask |= 1 << bar;
2597
1da177e4
LT		 2598 return 0;
2599
2600err_out:
c7dabef8 2601 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
096e6f67 2602 &pdev->resource[bar]);
1da177e4
LT		 2603 return -EBUSY;
2604}
2605
e8de1481 2606/**
f5ddcac4 2607 * pci_request_region - Reserve PCI I/O and memory resource
e8de1481
AV		 2608 * @pdev: PCI device whose resources are to be reserved
2609 * @bar: BAR to be reserved
f5ddcac4 2610 * @res_name: Name to be associated with resource
e8de1481 2611 *
f5ddcac4 2612 * Mark the PCI region associated with PCI device @pdev BAR @bar as
e8de1481
AV		 2613 * being reserved by owner @res_name. Do not access any
2614 * address inside the PCI regions unless this call returns
2615 * successfully.
2616 *
2617 * Returns 0 on success, or %EBUSY on error. A warning
2618 * message is also printed on failure.
2619 */
2620int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2621{
2622 return __pci_request_region(pdev, bar, res_name, 0);
2623}
2624
2625/**
2626 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2627 * @pdev: PCI device whose resources are to be reserved
2628 * @bar: BAR to be reserved
2629 * @res_name: Name to be associated with resource.
2630 *
2631 * Mark the PCI region associated with PCI device @pdev BR @bar as
2632 * being reserved by owner @res_name. Do not access any
2633 * address inside the PCI regions unless this call returns
2634 * successfully.
2635 *
2636 * Returns 0 on success, or %EBUSY on error. A warning
2637 * message is also printed on failure.
2638 *
2639 * The key difference that _exclusive makes it that userspace is
2640 * explicitly not allowed to map the resource via /dev/mem or
2641 * sysfs.
2642 */
2643int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2644{
2645 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2646}
c87deff7
HS		 2647/**
2648 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2649 * @pdev: PCI device whose resources were previously reserved
2650 * @bars: Bitmask of BARs to be released
2651 *
2652 * Release selected PCI I/O and memory resources previously reserved.
2653 * Call this function only after all use of the PCI regions has ceased.
2654 */
2655void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2656{
2657 int i;
2658
2659 for (i = 0; i < 6; i++)
2660 if (bars & (1 << i))
2661 pci_release_region(pdev, i);
2662}
2663
e8de1481
AV		 2664int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2665 const char *res_name, int excl)
c87deff7
HS		 2666{
2667 int i;
2668
2669 for (i = 0; i < 6; i++)
2670 if (bars & (1 << i))
e8de1481 2671 if (__pci_request_region(pdev, i, res_name, excl))
c87deff7
HS		 2672 goto err_out;
2673 return 0;
2674
2675err_out:
2676 while(--i >= 0)
2677 if (bars & (1 << i))
2678 pci_release_region(pdev, i);
2679
2680 return -EBUSY;
2681}
1da177e4 2682
e8de1481
AV		 2683
2684/**
2685 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2686 * @pdev: PCI device whose resources are to be reserved
2687 * @bars: Bitmask of BARs to be requested
2688 * @res_name: Name to be associated with resource
2689 */
2690int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2691 const char *res_name)
2692{
2693 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2694}
2695
2696int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2697 int bars, const char *res_name)
2698{
2699 return __pci_request_selected_regions(pdev, bars, res_name,
2700 IORESOURCE_EXCLUSIVE);
2701}
2702
1da177e4
LT		 2703/**
2704 * pci_release_regions - Release reserved PCI I/O and memory resources
2705 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2706 *
2707 * Releases all PCI I/O and memory resources previously reserved by a
2708 * successful call to pci_request_regions. Call this function only
2709 * after all use of the PCI regions has ceased.
2710 */
2711
2712void pci_release_regions(struct pci_dev *pdev)
2713{
c87deff7 2714 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 2715}
2716
2717/**
2718 * pci_request_regions - Reserved PCI I/O and memory resources
2719 * @pdev: PCI device whose resources are to be reserved
2720 * @res_name: Name to be associated with resource.
2721 *
2722 * Mark all PCI regions associated with PCI device @pdev as
2723 * being reserved by owner @res_name. Do not access any
2724 * address inside the PCI regions unless this call returns
2725 * successfully.
2726 *
2727 * Returns 0 on success, or %EBUSY on error. A warning
2728 * message is also printed on failure.
2729 */
3c990e92 2730int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 2731{
c87deff7 2732 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 2733}
2734
e8de1481
AV		 2735/**
2736 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2737 * @pdev: PCI device whose resources are to be reserved
2738 * @res_name: Name to be associated with resource.
2739 *
2740 * Mark all PCI regions associated with PCI device @pdev as
2741 * being reserved by owner @res_name. Do not access any
2742 * address inside the PCI regions unless this call returns
2743 * successfully.
2744 *
2745 * pci_request_regions_exclusive() will mark the region so that
2746 * /dev/mem and the sysfs MMIO access will not be allowed.
2747 *
2748 * Returns 0 on success, or %EBUSY on error. A warning
2749 * message is also printed on failure.
2750 */
2751int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2752{
2753 return pci_request_selected_regions_exclusive(pdev,
2754 ((1 << 6) - 1), res_name);
2755}
2756
6a479079
BH		 2757static void __pci_set_master(struct pci_dev *dev, bool enable)
2758{
2759 u16 old_cmd, cmd;
2760
2761 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2762 if (enable)
2763 cmd = old_cmd | PCI_COMMAND_MASTER;
2764 else
2765 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2766 if (cmd != old_cmd) {
2767 dev_dbg(&dev->dev, "%s bus mastering\n",
2768 enable ? "enabling" : "disabling");
2769 pci_write_config_word(dev, PCI_COMMAND, cmd);
2770 }
2771 dev->is_busmaster = enable;
2772}
e8de1481 2773
96c55900
MS		 2774/**
2775 * pcibios_set_master - enable PCI bus-mastering for device dev
2776 * @dev: the PCI device to enable
2777 *
2778 * Enables PCI bus-mastering for the device. This is the default
2779 * implementation. Architecture specific implementations can override
2780 * this if necessary.
2781 */
2782void __weak pcibios_set_master(struct pci_dev *dev)
2783{
2784 u8 lat;
2785
f676678f
MS		 2786 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2787 if (pci_is_pcie(dev))
2788 return;
2789
96c55900
MS		 2790 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2791 if (lat < 16)
2792 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2793 else if (lat > pcibios_max_latency)
2794 lat = pcibios_max_latency;
2795 else
2796 return;
2797 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2798 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2799}
2800
1da177e4
LT		 2801/**
2802 * pci_set_master - enables bus-mastering for device dev
2803 * @dev: the PCI device to enable
2804 *
2805 * Enables bus-mastering on the device and calls pcibios_set_master()
2806 * to do the needed arch specific settings.
2807 */
6a479079 2808void pci_set_master(struct pci_dev *dev)
1da177e4 2809{
6a479079 2810 __pci_set_master(dev, true);
1da177e4
LT		 2811 pcibios_set_master(dev);
2812}
2813
6a479079
BH		 2814/**
2815 * pci_clear_master - disables bus-mastering for device dev
2816 * @dev: the PCI device to disable
2817 */
2818void pci_clear_master(struct pci_dev *dev)
2819{
2820 __pci_set_master(dev, false);
2821}
2822
1da177e4 2823/**
edb2d97e
MW		 2824 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2825 * @dev: the PCI device for which MWI is to be enabled
1da177e4 2826 *
edb2d97e
MW		 2827 * Helper function for pci_set_mwi.
2828 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 2829 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2830 *
2831 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2832 */
15ea76d4 2833int pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 2834{
2835 u8 cacheline_size;
2836
2837 if (!pci_cache_line_size)
15ea76d4 2838 return -EINVAL;
1da177e4
LT		 2839
2840 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2841 equal to or multiple of the right value. */
2842 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2843 if (cacheline_size >= pci_cache_line_size &&
2844 (cacheline_size % pci_cache_line_size) == 0)
2845 return 0;
2846
2847 /* Write the correct value. */
2848 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2849 /* Read it back. */
2850 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2851 if (cacheline_size == pci_cache_line_size)
2852 return 0;
2853
80ccba11
BH		 2854 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2855 "supported\n", pci_cache_line_size << 2);
1da177e4
LT		 2856
2857 return -EINVAL;
2858}
15ea76d4
TH		 2859EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2860
2861#ifdef PCI_DISABLE_MWI
2862int pci_set_mwi(struct pci_dev *dev)
2863{
2864 return 0;
2865}
2866
2867int pci_try_set_mwi(struct pci_dev *dev)
2868{
2869 return 0;
2870}
2871
2872void pci_clear_mwi(struct pci_dev *dev)
2873{
2874}
2875
2876#else
1da177e4
LT		 2877
2878/**
2879 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2880 * @dev: the PCI device for which MWI is enabled
2881 *
694625c0 2882 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1da177e4
LT		 2883 *
2884 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2885 */
2886int
2887pci_set_mwi(struct pci_dev *dev)
2888{
2889 int rc;
2890 u16 cmd;
2891
edb2d97e 2892 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 2893 if (rc)
2894 return rc;
2895
2896 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2897 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
80ccba11 2898 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1da177e4
LT		 2899 cmd |= PCI_COMMAND_INVALIDATE;
2900 pci_write_config_word(dev, PCI_COMMAND, cmd);
2901 }
2902
2903 return 0;
2904}
2905
694625c0
RD		 2906/**
2907 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2908 * @dev: the PCI device for which MWI is enabled
2909 *
2910 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2911 * Callers are not required to check the return value.
2912 *
2913 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2914 */
2915int pci_try_set_mwi(struct pci_dev *dev)
2916{
2917 int rc = pci_set_mwi(dev);
2918 return rc;
2919}
2920
1da177e4
LT		 2921/**
2922 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2923 * @dev: the PCI device to disable
2924 *
2925 * Disables PCI Memory-Write-Invalidate transaction on the device
2926 */
2927void
2928pci_clear_mwi(struct pci_dev *dev)
2929{
2930 u16 cmd;
2931
2932 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2933 if (cmd & PCI_COMMAND_INVALIDATE) {
2934 cmd &= ~PCI_COMMAND_INVALIDATE;
2935 pci_write_config_word(dev, PCI_COMMAND, cmd);
2936 }
2937}
edb2d97e 2938#endif /* ! PCI_DISABLE_MWI */
1da177e4 2939
a04ce0ff
BR		 2940/**
2941 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 2942 * @pdev: the PCI device to operate on
2943 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 2944 *
2945 * Enables/disables PCI INTx for device dev
2946 */
2947void
2948pci_intx(struct pci_dev *pdev, int enable)
2949{
2950 u16 pci_command, new;
2951
2952 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2953
2954 if (enable) {
2955 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2956 } else {
2957 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2958 }
2959
2960 if (new != pci_command) {
9ac7849e
TH		 2961 struct pci_devres *dr;
2962
2fd9d74b 2963 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 2964
2965 dr = find_pci_dr(pdev);
2966 if (dr && !dr->restore_intx) {
2967 dr->restore_intx = 1;
2968 dr->orig_intx = !enable;
2969 }
a04ce0ff
BR		 2970 }
2971}
2972
a2e27787
JK		 2973/**
2974 * pci_intx_mask_supported - probe for INTx masking support
6e9292c5 2975 * @dev: the PCI device to operate on
a2e27787
JK		 2976 *
2977 * Check if the device dev support INTx masking via the config space
2978 * command word.
2979 */
2980bool pci_intx_mask_supported(struct pci_dev *dev)
2981{
2982 bool mask_supported = false;
2983 u16 orig, new;
2984
2985 pci_cfg_access_lock(dev);
2986
2987 pci_read_config_word(dev, PCI_COMMAND, &orig);
2988 pci_write_config_word(dev, PCI_COMMAND,
2989 orig ^ PCI_COMMAND_INTX_DISABLE);
2990 pci_read_config_word(dev, PCI_COMMAND, &new);
2991
2992 /*
2993 * There's no way to protect against hardware bugs or detect them
2994 * reliably, but as long as we know what the value should be, let's
2995 * go ahead and check it.
2996 */
2997 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2998 dev_err(&dev->dev, "Command register changed from "
2999 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
3000 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3001 mask_supported = true;
3002 pci_write_config_word(dev, PCI_COMMAND, orig);
3003 }
3004
3005 pci_cfg_access_unlock(dev);
3006 return mask_supported;
3007}
3008EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3009
3010static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3011{
3012 struct pci_bus *bus = dev->bus;
3013 bool mask_updated = true;
3014 u32 cmd_status_dword;
3015 u16 origcmd, newcmd;
3016 unsigned long flags;
3017 bool irq_pending;
3018
3019 /*
3020 * We do a single dword read to retrieve both command and status.
3021 * Document assumptions that make this possible.
3022 */
3023 BUILD_BUG_ON(PCI_COMMAND % 4);
3024 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3025
3026 raw_spin_lock_irqsave(&pci_lock, flags);
3027
3028 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3029
3030 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3031
3032 /*
3033 * Check interrupt status register to see whether our device
3034 * triggered the interrupt (when masking) or the next IRQ is
3035 * already pending (when unmasking).
3036 */
3037 if (mask != irq_pending) {
3038 mask_updated = false;
3039 goto done;
3040 }
3041
3042 origcmd = cmd_status_dword;
3043 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3044 if (mask)
3045 newcmd |= PCI_COMMAND_INTX_DISABLE;
3046 if (newcmd != origcmd)
3047 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3048
3049done:
3050 raw_spin_unlock_irqrestore(&pci_lock, flags);
3051
3052 return mask_updated;
3053}
3054
3055/**
3056 * pci_check_and_mask_intx - mask INTx on pending interrupt
6e9292c5 3057 * @dev: the PCI device to operate on
a2e27787
JK		 3058 *
3059 * Check if the device dev has its INTx line asserted, mask it and
3060 * return true in that case. False is returned if not interrupt was
3061 * pending.
3062 */
3063bool pci_check_and_mask_intx(struct pci_dev *dev)
3064{
3065 return pci_check_and_set_intx_mask(dev, true);
3066}
3067EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3068
3069/**
3070 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
6e9292c5 3071 * @dev: the PCI device to operate on
a2e27787
JK		 3072 *
3073 * Check if the device dev has its INTx line asserted, unmask it if not
3074 * and return true. False is returned and the mask remains active if
3075 * there was still an interrupt pending.
3076 */
3077bool pci_check_and_unmask_intx(struct pci_dev *dev)
3078{
3079 return pci_check_and_set_intx_mask(dev, false);
3080}
3081EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3082
f5f2b131
EB		 3083/**
3084 * pci_msi_off - disables any msi or msix capabilities
8d7d86e9 3085 * @dev: the PCI device to operate on
f5f2b131
EB		 3086 *
3087 * If you want to use msi see pci_enable_msi and friends.
3088 * This is a lower level primitive that allows us to disable
3089 * msi operation at the device level.
3090 */
3091void pci_msi_off(struct pci_dev *dev)
3092{
3093 int pos;
3094 u16 control;
3095
3096 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3097 if (pos) {
3098 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3099 control &= ~PCI_MSI_FLAGS_ENABLE;
3100 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3101 }
3102 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3103 if (pos) {
3104 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3105 control &= ~PCI_MSIX_FLAGS_ENABLE;
3106 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3107 }
3108}
b03214d5 3109EXPORT_SYMBOL_GPL(pci_msi_off);
f5f2b131 3110
4d57cdfa
FT		 3111int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3112{
3113 return dma_set_max_seg_size(&dev->dev, size);
3114}
3115EXPORT_SYMBOL(pci_set_dma_max_seg_size);
4d57cdfa 3116
59fc67de
FT		 3117int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3118{
3119 return dma_set_seg_boundary(&dev->dev, mask);
3120}
3121EXPORT_SYMBOL(pci_set_dma_seg_boundary);
59fc67de 3122
8c1c699f 3123static int pcie_flr(struct pci_dev *dev, int probe)
8dd7f803 3124{
8c1c699f
YZ		 3125 int i;
3126 int pos;
8dd7f803 3127 u32 cap;
04b55c47 3128 u16 status, control;
8dd7f803 3129
06a1cbaf 3130 pos = pci_pcie_cap(dev);
8c1c699f 3131 if (!pos)
8dd7f803 3132 return -ENOTTY;
8c1c699f
YZ		 3133
3134 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
8dd7f803
SY		 3135 if (!(cap & PCI_EXP_DEVCAP_FLR))
3136 return -ENOTTY;
3137
d91cdc74
SY		 3138 if (probe)
3139 return 0;
3140
8dd7f803 3141 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 3142 for (i = 0; i < 4; i++) {
3143 if (i)
3144 msleep((1 << (i - 1)) * 100);
5fe5db05 3145
8c1c699f
YZ		 3146 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
3147 if (!(status & PCI_EXP_DEVSTA_TRPND))
3148 goto clear;
3149 }
3150
3151 dev_err(&dev->dev, "transaction is not cleared; "
3152 "proceeding with reset anyway\n");
3153
3154clear:
04b55c47
SR		 3155 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
3156 control |= PCI_EXP_DEVCTL_BCR_FLR;
3157 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
3158
8c1c699f 3159 msleep(100);
8dd7f803 3160
8dd7f803
SY		 3161 return 0;
3162}
d91cdc74 3163
8c1c699f 3164static int pci_af_flr(struct pci_dev *dev, int probe)
1ca88797 3165{
8c1c699f
YZ		 3166 int i;
3167 int pos;
1ca88797 3168 u8 cap;
8c1c699f 3169 u8 status;
1ca88797 3170
8c1c699f
YZ		 3171 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3172 if (!pos)
1ca88797 3173 return -ENOTTY;
8c1c699f
YZ		 3174
3175 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
1ca88797
SY		 3176 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3177 return -ENOTTY;
3178
3179 if (probe)
3180 return 0;
3181
1ca88797 3182 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 3183 for (i = 0; i < 4; i++) {
3184 if (i)
3185 msleep((1 << (i - 1)) * 100);
3186
3187 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3188 if (!(status & PCI_AF_STATUS_TP))
3189 goto clear;
3190 }
5fe5db05 3191
8c1c699f
YZ		 3192 dev_err(&dev->dev, "transaction is not cleared; "
3193 "proceeding with reset anyway\n");
5fe5db05 3194
8c1c699f
YZ		 3195clear:
3196 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1ca88797 3197 msleep(100);
8c1c699f 3198
1ca88797
SY		 3199 return 0;
3200}
3201
83d74e03
RW		 3202/**
3203 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3204 * @dev: Device to reset.
3205 * @probe: If set, only check if the device can be reset this way.
3206 *
3207 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3208 * unset, it will be reinitialized internally when going from PCI_D3hot to
3209 * PCI_D0. If that's the case and the device is not in a low-power state
3210 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3211 *
3212 * NOTE: This causes the caller to sleep for twice the device power transition
3213 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3214 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3215 * Moreover, only devices in D0 can be reset by this function.
3216 */
f85876ba 3217static int pci_pm_reset(struct pci_dev *dev, int probe)
d91cdc74 3218{
f85876ba
YZ		 3219 u16 csr;
3220
3221 if (!dev->pm_cap)
3222 return -ENOTTY;
d91cdc74 3223
f85876ba
YZ		 3224 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3225 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3226 return -ENOTTY;
d91cdc74 3227
f85876ba
YZ		 3228 if (probe)
3229 return 0;
1ca88797 3230
f85876ba
YZ		 3231 if (dev->current_state != PCI_D0)
3232 return -EINVAL;
3233
3234 csr &= ~PCI_PM_CTRL_STATE_MASK;
3235 csr |= PCI_D3hot;
3236 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 3237 pci_dev_d3_sleep(dev);
f85876ba
YZ		 3238
3239 csr &= ~PCI_PM_CTRL_STATE_MASK;
3240 csr |= PCI_D0;
3241 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 3242 pci_dev_d3_sleep(dev);
f85876ba
YZ		 3243
3244 return 0;
3245}
3246
c12ff1df
YZ		 3247static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3248{
3249 u16 ctrl;
3250 struct pci_dev *pdev;
3251
654b75e0 3252 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
c12ff1df
YZ		 3253 return -ENOTTY;
3254
3255 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3256 if (pdev != dev)
3257 return -ENOTTY;
3258
3259 if (probe)
3260 return 0;
3261
3262 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3263 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3264 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3265 msleep(100);
3266
3267 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3268 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3269 msleep(100);
3270
3271 return 0;
3272}
3273
977f857c 3274static int __pci_dev_reset(struct pci_dev *dev, int probe)
d91cdc74 3275{
8c1c699f
YZ		 3276 int rc;
3277
3278 might_sleep();
3279
b9c3b266
DC		 3280 rc = pci_dev_specific_reset(dev, probe);
3281 if (rc != -ENOTTY)
3282 goto done;
3283
8c1c699f
YZ		 3284 rc = pcie_flr(dev, probe);
3285 if (rc != -ENOTTY)
3286 goto done;
d91cdc74 3287
8c1c699f 3288 rc = pci_af_flr(dev, probe);
f85876ba
YZ		 3289 if (rc != -ENOTTY)
3290 goto done;
3291
3292 rc = pci_pm_reset(dev, probe);
c12ff1df
YZ		 3293 if (rc != -ENOTTY)
3294 goto done;
3295
3296 rc = pci_parent_bus_reset(dev, probe);
8c1c699f 3297done:
977f857c
KRW		 3298 return rc;
3299}
3300
3301static int pci_dev_reset(struct pci_dev *dev, int probe)
3302{
3303 int rc;
3304
3305 if (!probe) {
3306 pci_cfg_access_lock(dev);
3307 /* block PM suspend, driver probe, etc. */
3308 device_lock(&dev->dev);
3309 }
3310
3311 rc = __pci_dev_reset(dev, probe);
3312
8c1c699f 3313 if (!probe) {
8e9394ce 3314 device_unlock(&dev->dev);
fb51ccbf 3315 pci_cfg_access_unlock(dev);
8c1c699f 3316 }
8c1c699f 3317 return rc;
d91cdc74 3318}
d91cdc74 3319/**
8c1c699f
YZ		 3320 * __pci_reset_function - reset a PCI device function
3321 * @dev: PCI device to reset
d91cdc74
SY		 3322 *
3323 * Some devices allow an individual function to be reset without affecting
3324 * other functions in the same device. The PCI device must be responsive
3325 * to PCI config space in order to use this function.
3326 *
3327 * The device function is presumed to be unused when this function is called.
3328 * Resetting the device will make the contents of PCI configuration space
3329 * random, so any caller of this must be prepared to reinitialise the
3330 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3331 * etc.
3332 *
8c1c699f 3333 * Returns 0 if the device function was successfully reset or negative if the
d91cdc74
SY		 3334 * device doesn't support resetting a single function.
3335 */
8c1c699f 3336int __pci_reset_function(struct pci_dev *dev)
d91cdc74 3337{
8c1c699f 3338 return pci_dev_reset(dev, 0);
d91cdc74 3339}
8c1c699f 3340EXPORT_SYMBOL_GPL(__pci_reset_function);
8dd7f803 3341
6fbf9e7a
KRW		 3342/**
3343 * __pci_reset_function_locked - reset a PCI device function while holding
3344 * the @dev mutex lock.
3345 * @dev: PCI device to reset
3346 *
3347 * Some devices allow an individual function to be reset without affecting
3348 * other functions in the same device. The PCI device must be responsive
3349 * to PCI config space in order to use this function.
3350 *
3351 * The device function is presumed to be unused and the caller is holding
3352 * the device mutex lock when this function is called.
3353 * Resetting the device will make the contents of PCI configuration space
3354 * random, so any caller of this must be prepared to reinitialise the
3355 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3356 * etc.
3357 *
3358 * Returns 0 if the device function was successfully reset or negative if the
3359 * device doesn't support resetting a single function.
3360 */
3361int __pci_reset_function_locked(struct pci_dev *dev)
3362{
977f857c 3363 return __pci_dev_reset(dev, 0);
6fbf9e7a
KRW		 3364}
3365EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3366
711d5779
MT		 3367/**
3368 * pci_probe_reset_function - check whether the device can be safely reset
3369 * @dev: PCI device to reset
3370 *
3371 * Some devices allow an individual function to be reset without affecting
3372 * other functions in the same device. The PCI device must be responsive
3373 * to PCI config space in order to use this function.
3374 *
3375 * Returns 0 if the device function can be reset or negative if the
3376 * device doesn't support resetting a single function.
3377 */
3378int pci_probe_reset_function(struct pci_dev *dev)
3379{
3380 return pci_dev_reset(dev, 1);
3381}
3382
8dd7f803 3383/**
8c1c699f
YZ		 3384 * pci_reset_function - quiesce and reset a PCI device function
3385 * @dev: PCI device to reset
8dd7f803
SY		 3386 *
3387 * Some devices allow an individual function to be reset without affecting
3388 * other functions in the same device. The PCI device must be responsive
3389 * to PCI config space in order to use this function.
3390 *
3391 * This function does not just reset the PCI portion of a device, but
3392 * clears all the state associated with the device. This function differs
8c1c699f 3393 * from __pci_reset_function in that it saves and restores device state
8dd7f803
SY		 3394 * over the reset.
3395 *
8c1c699f 3396 * Returns 0 if the device function was successfully reset or negative if the
8dd7f803
SY		 3397 * device doesn't support resetting a single function.
3398 */
3399int pci_reset_function(struct pci_dev *dev)
3400{
8c1c699f 3401 int rc;
8dd7f803 3402
8c1c699f
YZ		 3403 rc = pci_dev_reset(dev, 1);
3404 if (rc)
3405 return rc;
8dd7f803 3406
8dd7f803
SY		 3407 pci_save_state(dev);
3408
8c1c699f
YZ		 3409 /*
3410 * both INTx and MSI are disabled after the Interrupt Disable bit
3411 * is set and the Bus Master bit is cleared.
3412 */
8dd7f803
SY		 3413 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3414
8c1c699f 3415 rc = pci_dev_reset(dev, 0);
8dd7f803
SY		 3416
3417 pci_restore_state(dev);
8dd7f803 3418
8c1c699f 3419 return rc;
8dd7f803
SY		 3420}
3421EXPORT_SYMBOL_GPL(pci_reset_function);
3422
d556ad4b
PO		 3423/**
3424 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3425 * @dev: PCI device to query
3426 *
3427 * Returns mmrbc: maximum designed memory read count in bytes
3428 * or appropriate error value.
3429 */
3430int pcix_get_max_mmrbc(struct pci_dev *dev)
3431{
7c9e2b1c 3432 int cap;
d556ad4b
PO		 3433 u32 stat;
3434
3435 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3436 if (!cap)
3437 return -EINVAL;
3438
7c9e2b1c 3439 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
d556ad4b
PO		 3440 return -EINVAL;
3441
25daeb55 3442 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
d556ad4b
PO		 3443}
3444EXPORT_SYMBOL(pcix_get_max_mmrbc);
3445
3446/**
3447 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3448 * @dev: PCI device to query
3449 *
3450 * Returns mmrbc: maximum memory read count in bytes
3451 * or appropriate error value.
3452 */
3453int pcix_get_mmrbc(struct pci_dev *dev)
3454{
7c9e2b1c 3455 int cap;
bdc2bda7 3456 u16 cmd;
d556ad4b
PO		 3457
3458 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3459 if (!cap)
3460 return -EINVAL;
3461
7c9e2b1c
DN		 3462 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3463 return -EINVAL;
d556ad4b 3464
7c9e2b1c 3465 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
d556ad4b
PO		 3466}
3467EXPORT_SYMBOL(pcix_get_mmrbc);
3468
3469/**
3470 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3471 * @dev: PCI device to query
3472 * @mmrbc: maximum memory read count in bytes
3473 * valid values are 512, 1024, 2048, 4096
3474 *
3475 * If possible sets maximum memory read byte count, some bridges have erratas
3476 * that prevent this.
3477 */
3478int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3479{
7c9e2b1c 3480 int cap;
bdc2bda7
DN		 3481 u32 stat, v, o;
3482 u16 cmd;
d556ad4b 3483
229f5afd 3484 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
7c9e2b1c 3485 return -EINVAL;
d556ad4b
PO		 3486
3487 v = ffs(mmrbc) - 10;
3488
3489 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3490 if (!cap)
7c9e2b1c 3491 return -EINVAL;
d556ad4b 3492
7c9e2b1c
DN		 3493 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3494 return -EINVAL;
d556ad4b
PO		 3495
3496 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3497 return -E2BIG;
3498
7c9e2b1c
DN		 3499 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3500 return -EINVAL;
d556ad4b
PO		 3501
3502 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3503 if (o != v) {
3504 if (v > o && dev->bus &&
3505 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3506 return -EIO;
3507
3508 cmd &= ~PCI_X_CMD_MAX_READ;
3509 cmd |= v << 2;
7c9e2b1c
DN		 3510 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3511 return -EIO;
d556ad4b 3512 }
7c9e2b1c 3513 return 0;
d556ad4b
PO		 3514}
3515EXPORT_SYMBOL(pcix_set_mmrbc);
3516
3517/**
3518 * pcie_get_readrq - get PCI Express read request size
3519 * @dev: PCI device to query
3520 *
3521 * Returns maximum memory read request in bytes
3522 * or appropriate error value.
3523 */
3524int pcie_get_readrq(struct pci_dev *dev)
3525{
3526 int ret, cap;
3527 u16 ctl;
3528
06a1cbaf 3529 cap = pci_pcie_cap(dev);
d556ad4b
PO		 3530 if (!cap)
3531 return -EINVAL;
3532
3533 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3534 if (!ret)
93e75fab 3535 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
d556ad4b
PO		 3536
3537 return ret;
3538}
3539EXPORT_SYMBOL(pcie_get_readrq);
3540
3541/**
3542 * pcie_set_readrq - set PCI Express maximum memory read request
3543 * @dev: PCI device to query
42e61f4a 3544 * @rq: maximum memory read count in bytes
d556ad4b
PO		 3545 * valid values are 128, 256, 512, 1024, 2048, 4096
3546 *
c9b378c7 3547 * If possible sets maximum memory read request in bytes
d556ad4b
PO		 3548 */
3549int pcie_set_readrq(struct pci_dev *dev, int rq)
3550{
3551 int cap, err = -EINVAL;
3552 u16 ctl, v;
3553
229f5afd 3554 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
d556ad4b
PO		 3555 goto out;
3556
06a1cbaf 3557 cap = pci_pcie_cap(dev);
d556ad4b
PO		 3558 if (!cap)
3559 goto out;
3560
3561 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3562 if (err)
3563 goto out;
a1c473aa
BH		 3564 /*
3565 * If using the "performance" PCIe config, we clamp the
3566 * read rq size to the max packet size to prevent the
3567 * host bridge generating requests larger than we can
3568 * cope with
3569 */
3570 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3571 int mps = pcie_get_mps(dev);
3572
3573 if (mps < 0)
3574 return mps;
3575 if (mps < rq)
3576 rq = mps;
3577 }
3578
3579 v = (ffs(rq) - 8) << 12;
d556ad4b
PO		 3580
3581 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3582 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3583 ctl |= v;
c9b378c7 3584 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
d556ad4b
PO		 3585 }
3586
3587out:
3588 return err;
3589}
3590EXPORT_SYMBOL(pcie_set_readrq);
3591
b03e7495
JM		 3592/**
3593 * pcie_get_mps - get PCI Express maximum payload size
3594 * @dev: PCI device to query
3595 *
3596 * Returns maximum payload size in bytes
3597 * or appropriate error value.
3598 */
3599int pcie_get_mps(struct pci_dev *dev)
3600{
3601 int ret, cap;
3602 u16 ctl;
3603
3604 cap = pci_pcie_cap(dev);
3605 if (!cap)
3606 return -EINVAL;
3607
3608 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3609 if (!ret)
3610 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3611
3612 return ret;
3613}
3614
3615/**
3616 * pcie_set_mps - set PCI Express maximum payload size
3617 * @dev: PCI device to query
47c08f31 3618 * @mps: maximum payload size in bytes
b03e7495
JM		 3619 * valid values are 128, 256, 512, 1024, 2048, 4096
3620 *
3621 * If possible sets maximum payload size
3622 */
3623int pcie_set_mps(struct pci_dev *dev, int mps)
3624{
3625 int cap, err = -EINVAL;
3626 u16 ctl, v;
3627
3628 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3629 goto out;
3630
3631 v = ffs(mps) - 8;
3632 if (v > dev->pcie_mpss)
3633 goto out;
3634 v <<= 5;
3635
3636 cap = pci_pcie_cap(dev);
3637 if (!cap)
3638 goto out;
3639
3640 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3641 if (err)
3642 goto out;
3643
3644 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3645 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3646 ctl |= v;
3647 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3648 }
3649out:
3650 return err;
3651}
3652
c87deff7
HS		 3653/**
3654 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 3655 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 3656 * @flags: resource type mask to be selected
3657 *
3658 * This helper routine makes bar mask from the type of resource.
3659 */
3660int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3661{
3662 int i, bars = 0;
3663 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3664 if (pci_resource_flags(dev, i) & flags)
3665 bars |= (1 << i);
3666 return bars;
3667}
3668
613e7ed6
YZ		 3669/**
3670 * pci_resource_bar - get position of the BAR associated with a resource
3671 * @dev: the PCI device
3672 * @resno: the resource number
3673 * @type: the BAR type to be filled in
3674 *
3675 * Returns BAR position in config space, or 0 if the BAR is invalid.
3676 */
3677int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3678{
d1b054da
YZ		 3679 int reg;
3680
613e7ed6
YZ		 3681 if (resno < PCI_ROM_RESOURCE) {
3682 *type = pci_bar_unknown;
3683 return PCI_BASE_ADDRESS_0 + 4 * resno;
3684 } else if (resno == PCI_ROM_RESOURCE) {
3685 *type = pci_bar_mem32;
3686 return dev->rom_base_reg;
d1b054da
YZ		 3687 } else if (resno < PCI_BRIDGE_RESOURCES) {
3688 /* device specific resource */
3689 reg = pci_iov_resource_bar(dev, resno, type);
3690 if (reg)
3691 return reg;
613e7ed6
YZ		 3692 }
3693
865df576 3694 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
613e7ed6
YZ		 3695 return 0;
3696}
3697
95a8b6ef
MT		 3698/* Some architectures require additional programming to enable VGA */
3699static arch_set_vga_state_t arch_set_vga_state;
3700
3701void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3702{
3703 arch_set_vga_state = func; /* NULL disables */
3704}
3705
3706static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
7ad35cf2 3707 unsigned int command_bits, u32 flags)
95a8b6ef
MT		 3708{
3709 if (arch_set_vga_state)
3710 return arch_set_vga_state(dev, decode, command_bits,
7ad35cf2 3711 flags);
95a8b6ef
MT		 3712 return 0;
3713}
3714
deb2d2ec
BH		 3715/**
3716 * pci_set_vga_state - set VGA decode state on device and parents if requested
19eea630
RD		 3717 * @dev: the PCI device
3718 * @decode: true = enable decoding, false = disable decoding
3719 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3f37d622 3720 * @flags: traverse ancestors and change bridges
3448a19d 3721 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
deb2d2ec
BH		 3722 */
3723int pci_set_vga_state(struct pci_dev *dev, bool decode,
3448a19d 3724 unsigned int command_bits, u32 flags)
deb2d2ec
BH		 3725{
3726 struct pci_bus *bus;
3727 struct pci_dev *bridge;
3728 u16 cmd;
95a8b6ef 3729 int rc;
deb2d2ec 3730
3448a19d 3731 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
deb2d2ec 3732
95a8b6ef 3733 /* ARCH specific VGA enables */
3448a19d 3734 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
95a8b6ef
MT		 3735 if (rc)
3736 return rc;
3737
3448a19d
DA		 3738 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3739 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3740 if (decode == true)
3741 cmd |= command_bits;
3742 else
3743 cmd &= ~command_bits;
3744 pci_write_config_word(dev, PCI_COMMAND, cmd);
3745 }
deb2d2ec 3746
3448a19d 3747 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
deb2d2ec
BH		 3748 return 0;
3749
3750 bus = dev->bus;
3751 while (bus) {
3752 bridge = bus->self;
3753 if (bridge) {
3754 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3755 &cmd);
3756 if (decode == true)
3757 cmd |= PCI_BRIDGE_CTL_VGA;
3758 else
3759 cmd &= ~PCI_BRIDGE_CTL_VGA;
3760 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3761 cmd);
3762 }
3763 bus = bus->parent;
3764 }
3765 return 0;
3766}
3767
32a9a682
YS		 3768#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3769static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
e9d1e492 3770static DEFINE_SPINLOCK(resource_alignment_lock);
32a9a682
YS		 3771
3772/**
3773 * pci_specified_resource_alignment - get resource alignment specified by user.
3774 * @dev: the PCI device to get
3775 *
3776 * RETURNS: Resource alignment if it is specified.
3777 * Zero if it is not specified.
3778 */
3779resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3780{
3781 int seg, bus, slot, func, align_order, count;
3782 resource_size_t align = 0;
3783 char *p;
3784
3785 spin_lock(&resource_alignment_lock);
3786 p = resource_alignment_param;
3787 while (*p) {
3788 count = 0;
3789 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3790 p[count] == '@') {
3791 p += count + 1;
3792 } else {
3793 align_order = -1;
3794 }
3795 if (sscanf(p, "%x:%x:%x.%x%n",
3796 &seg, &bus, &slot, &func, &count) != 4) {
3797 seg = 0;
3798 if (sscanf(p, "%x:%x.%x%n",
3799 &bus, &slot, &func, &count) != 3) {
3800 /* Invalid format */
3801 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3802 p);
3803 break;
3804 }
3805 }
3806 p += count;
3807 if (seg == pci_domain_nr(dev->bus) &&
3808 bus == dev->bus->number &&
3809 slot == PCI_SLOT(dev->devfn) &&
3810 func == PCI_FUNC(dev->devfn)) {
3811 if (align_order == -1) {
3812 align = PAGE_SIZE;
3813 } else {
3814 align = 1 << align_order;
3815 }
3816 /* Found */
3817 break;
3818 }
3819 if (*p != ';' && *p != ',') {
3820 /* End of param or invalid format */
3821 break;
3822 }
3823 p++;
3824 }
3825 spin_unlock(&resource_alignment_lock);
3826 return align;
3827}
3828
3829/**
3830 * pci_is_reassigndev - check if specified PCI is target device to reassign
3831 * @dev: the PCI device to check
3832 *
3833 * RETURNS: non-zero for PCI device is a target device to reassign,
3834 * or zero is not.
3835 */
3836int pci_is_reassigndev(struct pci_dev *dev)
3837{
3838 return (pci_specified_resource_alignment(dev) != 0);
3839}
3840
2069ecfb
YL		 3841/*
3842 * This function disables memory decoding and releases memory resources
3843 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3844 * It also rounds up size to specified alignment.
3845 * Later on, the kernel will assign page-aligned memory resource back
3846 * to the device.
3847 */
3848void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3849{
3850 int i;
3851 struct resource *r;
3852 resource_size_t align, size;
3853 u16 command;
3854
3855 if (!pci_is_reassigndev(dev))
3856 return;
3857
3858 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3859 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3860 dev_warn(&dev->dev,
3861 "Can't reassign resources to host bridge.\n");
3862 return;
3863 }
3864
3865 dev_info(&dev->dev,
3866 "Disabling memory decoding and releasing memory resources.\n");
3867 pci_read_config_word(dev, PCI_COMMAND, &command);
3868 command &= ~PCI_COMMAND_MEMORY;
3869 pci_write_config_word(dev, PCI_COMMAND, command);
3870
3871 align = pci_specified_resource_alignment(dev);
3872 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3873 r = &dev->resource[i];
3874 if (!(r->flags & IORESOURCE_MEM))
3875 continue;
3876 size = resource_size(r);
3877 if (size < align) {
3878 size = align;
3879 dev_info(&dev->dev,
3880 "Rounding up size of resource #%d to %#llx.\n",
3881 i, (unsigned long long)size);
3882 }
3883 r->end = size - 1;
3884 r->start = 0;
3885 }
3886 /* Need to disable bridge's resource window,
3887 * to enable the kernel to reassign new resource
3888 * window later on.
3889 */
3890 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3891 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3892 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3893 r = &dev->resource[i];
3894 if (!(r->flags & IORESOURCE_MEM))
3895 continue;
3896 r->end = resource_size(r) - 1;
3897 r->start = 0;
3898 }
3899 pci_disable_bridge_window(dev);
3900 }
3901}
3902
32a9a682
YS		 3903ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3904{
3905 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3906 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3907 spin_lock(&resource_alignment_lock);
3908 strncpy(resource_alignment_param, buf, count);
3909 resource_alignment_param[count] = '\0';
3910 spin_unlock(&resource_alignment_lock);
3911 return count;
3912}
3913
3914ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3915{
3916 size_t count;
3917 spin_lock(&resource_alignment_lock);
3918 count = snprintf(buf, size, "%s", resource_alignment_param);
3919 spin_unlock(&resource_alignment_lock);
3920 return count;
3921}
3922
3923static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3924{
3925 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3926}
3927
3928static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3929 const char *buf, size_t count)
3930{
3931 return pci_set_resource_alignment_param(buf, count);
3932}
3933
3934BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3935 pci_resource_alignment_store);
3936
3937static int __init pci_resource_alignment_sysfs_init(void)
3938{
3939 return bus_create_file(&pci_bus_type,
3940 &bus_attr_resource_alignment);
3941}
3942
3943late_initcall(pci_resource_alignment_sysfs_init);
3944
32a2eea7
JG		 3945static void __devinit pci_no_domains(void)
3946{
3947#ifdef CONFIG_PCI_DOMAINS
3948 pci_domains_supported = 0;
3949#endif
3950}
3951
0ef5f8f6
AP		 3952/**
3953 * pci_ext_cfg_enabled - can we access extended PCI config space?
3954 * @dev: The PCI device of the root bridge.
3955 *
3956 * Returns 1 if we can access PCI extended config space (offsets
3957 * greater than 0xff). This is the default implementation. Architecture
3958 * implementations can override this.
3959 */
3960int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3961{
3962 return 1;
3963}
3964
2d1c8618
BH		 3965void __weak pci_fixup_cardbus(struct pci_bus *bus)
3966{
3967}
3968EXPORT_SYMBOL(pci_fixup_cardbus);
3969
ad04d31e 3970static int __init pci_setup(char *str)
1da177e4
LT		 3971{
3972 while (str) {
3973 char *k = strchr(str, ',');
3974 if (k)
3975 *k++ = 0;
3976 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 3977 if (!strcmp(str, "nomsi")) {
3978 pci_no_msi();
7f785763
RD		 3979 } else if (!strcmp(str, "noaer")) {
3980 pci_no_aer();
b55438fd
YL		 3981 } else if (!strncmp(str, "realloc=", 8)) {
3982 pci_realloc_get_opt(str + 8);
f483d392 3983 } else if (!strncmp(str, "realloc", 7)) {
b55438fd 3984 pci_realloc_get_opt("on");
32a2eea7
JG		 3985 } else if (!strcmp(str, "nodomains")) {
3986 pci_no_domains();
6748dcc2
RW		 3987 } else if (!strncmp(str, "noari", 5)) {
3988 pcie_ari_disabled = true;
4516a618
AN		 3989 } else if (!strncmp(str, "cbiosize=", 9)) {
3990 pci_cardbus_io_size = memparse(str + 9, &str);
3991 } else if (!strncmp(str, "cbmemsize=", 10)) {
3992 pci_cardbus_mem_size = memparse(str + 10, &str);
32a9a682
YS		 3993 } else if (!strncmp(str, "resource_alignment=", 19)) {
3994 pci_set_resource_alignment_param(str + 19,
3995 strlen(str + 19));
43c16408
AP		 3996 } else if (!strncmp(str, "ecrc=", 5)) {
3997 pcie_ecrc_get_policy(str + 5);
28760489
EB		 3998 } else if (!strncmp(str, "hpiosize=", 9)) {
3999 pci_hotplug_io_size = memparse(str + 9, &str);
4000 } else if (!strncmp(str, "hpmemsize=", 10)) {
4001 pci_hotplug_mem_size = memparse(str + 10, &str);
5f39e670
JM		 4002 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4003 pcie_bus_config = PCIE_BUS_TUNE_OFF;
b03e7495
JM		 4004 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4005 pcie_bus_config = PCIE_BUS_SAFE;
4006 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4007 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5f39e670
JM		 4008 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4009 pcie_bus_config = PCIE_BUS_PEER2PEER;
284f5f9d
BH		 4010 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4011 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
309e57df
MW		 4012 } else {
4013 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4014 str);
4015 }
1da177e4
LT		 4016 }
4017 str = k;
4018 }
0637a70a 4019 return 0;
1da177e4 4020}
0637a70a 4021early_param("pci", pci_setup);
1da177e4 4022
0b62e13b 4023EXPORT_SYMBOL(pci_reenable_device);
b718989d
BH		 4024EXPORT_SYMBOL(pci_enable_device_io);
4025EXPORT_SYMBOL(pci_enable_device_mem);
1da177e4 4026EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 4027EXPORT_SYMBOL(pcim_enable_device);
4028EXPORT_SYMBOL(pcim_pin_device);
1da177e4 4029EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 4030EXPORT_SYMBOL(pci_find_capability);
4031EXPORT_SYMBOL(pci_bus_find_capability);
4032EXPORT_SYMBOL(pci_release_regions);
4033EXPORT_SYMBOL(pci_request_regions);
e8de1481 4034EXPORT_SYMBOL(pci_request_regions_exclusive);
1da177e4
LT		 4035EXPORT_SYMBOL(pci_release_region);
4036EXPORT_SYMBOL(pci_request_region);
e8de1481 4037EXPORT_SYMBOL(pci_request_region_exclusive);
c87deff7
HS		 4038EXPORT_SYMBOL(pci_release_selected_regions);
4039EXPORT_SYMBOL(pci_request_selected_regions);
e8de1481 4040EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
1da177e4 4041EXPORT_SYMBOL(pci_set_master);
6a479079 4042EXPORT_SYMBOL(pci_clear_master);
1da177e4 4043EXPORT_SYMBOL(pci_set_mwi);
694625c0 4044EXPORT_SYMBOL(pci_try_set_mwi);
1da177e4 4045EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 4046EXPORT_SYMBOL_GPL(pci_intx);
1da177e4
LT		 4047EXPORT_SYMBOL(pci_assign_resource);
4048EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 4049EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 4050
4051EXPORT_SYMBOL(pci_set_power_state);
4052EXPORT_SYMBOL(pci_save_state);
4053EXPORT_SYMBOL(pci_restore_state);
e5899e1b 4054EXPORT_SYMBOL(pci_pme_capable);
5a6c9b60 4055EXPORT_SYMBOL(pci_pme_active);
0235c4fc 4056EXPORT_SYMBOL(pci_wake_from_d3);
e5899e1b 4057EXPORT_SYMBOL(pci_target_state);
404cc2d8
RW		 4058EXPORT_SYMBOL(pci_prepare_to_sleep);
4059EXPORT_SYMBOL(pci_back_from_sleep);
f7bdd12d 4060EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
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